Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31126

1

T1

48

T2

2

T3

18

auto[1]

30375

1

T1

52

T2

4

T3

14

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31369

1

T1

62

T2

3

T3

14

auto[1]

30132

1

T1

38

T2

3

T3

18

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30286

1

T1

40

T2

2

T3

28

auto[1]

31215

1

T1

60

T2

4

T3

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34527

1

T1

50

T2

4

T3

16

auto[1]

26974

1

T1

50

T2

2

T3

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30196

1

T1

42

T2

5

T3

12

auto[1]

31305

1

T1

58

T2

1

T3

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31587

1

T1

40

T2

3

T3

20

auto[1]

29914

1

T1

60

T2

3

T3

12

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1029

1

T1

1

T3

1

T5

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

796

1

T1

1

T3

1

T5

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1047

1

T1

1

T5

8

T40

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

845

1

T1

1

T5

6

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1063

1

T3

2

T5

4

T13

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

832

1

T3

2

T5

4

T13

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1713

1

T1

3

T5

5

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1464

1

T1

3

T5

3

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1052

1

T1

2

T3

1

T5

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

820

1

T1

2

T3

1

T5

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1005

1

T1

1

T5

7

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

777

1

T1

1

T5

6

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1048

1

T1

3

T5

4

T25

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

817

1

T1

3

T5

4

T25

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1041

1

T1

2

T5

4

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

824

1

T1

2

T5

4

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1084

1

T3

1

T5

2

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

835

1

T3

1

T5

1

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1031

1

T1

2

T5

5

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

808

1

T1

2

T5

4

T40

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1068

1

T1

2

T5

6

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

835

1

T1

2

T5

6

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1006

1

T1

2

T3

1

T5

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

779

1

T1

2

T3

1

T5

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1079

1

T1

1

T5

5

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

832

1

T1

1

T5

4

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1046

1

T1

2

T2

1

T5

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

777

1

T1

2

T2

1

T5

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1045

1

T1

1

T3

3

T5

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

806

1

T1

1

T3

3

T5

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1079

1

T1

1

T5

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

843

1

T1

1

T5

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1077

1

T1

2

T2

1

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

853

1

T1

2

T2

1

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1078

1

T1

2

T5

3

T13

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

813

1

T1

2

T5

2

T13

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1133

1

T1

1

T3

1

T5

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

881

1

T1

1

T3

1

T5

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1056

1

T1

1

T5

4

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

808

1

T1

1

T5

3

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1086

1

T1

2

T3

1

T5

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

856

1

T1

2

T3

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1067

1

T1

2

T2

1

T5

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

837

1

T1

2

T5

1

T25

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1021

1

T1

1

T5

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

792

1

T1

1

T5

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1037

1

T1

7

T5

5

T13

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

801

1

T1

7

T5

5

T13

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1079

1

T1

1

T3

1

T5

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

853

1

T1

1

T3

1

T5

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1110

1

T5

5

T25

1

T13

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

865

1

T5

4

T25

1

T13

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1040

1

T1

1

T3

1

T5

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

807

1

T1

1

T3

1

T5

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1073

1

T1

1

T2

1

T3

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

826

1

T1

1

T3

1

T5

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1055

1

T5

4

T40

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

822

1

T5

3

T40

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1077

1

T1

2

T5

6

T13

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

805

1

T1

2

T5

5

T13

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1053

1

T1

2

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

837

1

T1

2

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1049

1

T1

1

T5

4

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

828

1

T1

1

T5

2

T25

4