Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 6 0 6 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17039 1 T1 40 T4 6 T5 113
auto[1] 25752 1 T1 42 T4 3 T5 113


Summary for Variable reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for reset_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35650 1 T1 59 T3 16 T4 4
auto[1] 9623 1 T1 23 T4 5 T5 52


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18410 1 T1 32 T4 9 T5 120
auto[1] 26863 1 T1 50 T3 16 T5 110


Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
reset_cpenable_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 4085 1 T1 4 T4 3 T5 35
auto[0] auto[0] auto[1] 9630 1 T1 26 T5 60 T25 23
auto[0] auto[1] auto[0] 4402 1 T1 5 T4 1 T5 33
auto[0] auto[1] auto[1] 15051 1 T1 24 T5 46 T25 27
auto[1] auto[0] auto[0] 3324 1 T1 10 T4 3 T5 18
auto[1] auto[1] auto[0] 6299 1 T1 13 T4 2 T5 34


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%