Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31661 1 T1 6 T3 681 T8 8
auto[1] 30067 1 T1 8 T3 566 T8 10


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31685 1 T1 10 T3 581 T8 8
auto[1] 30043 1 T1 4 T3 666 T8 10


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30048 1 T1 2 T3 610 T8 12
auto[1] 31680 1 T1 12 T3 637 T8 6


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34208 1 T1 7 T3 712 T8 9
auto[1] 27520 1 T1 7 T3 535 T8 9


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30191 1 T1 2 T3 633 T8 12
auto[1] 31537 1 T1 12 T3 614 T8 6


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31238 1 T1 6 T3 620 T8 6
auto[1] 30490 1 T1 8 T3 627 T8 12


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1060 1 T3 15 T8 1 T11 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 861 1 T3 12 T8 1 T11 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1071 1 T3 25 T11 1 T53 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 858 1 T3 17 T11 1 T53 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1028 1 T3 19 T11 4 T37 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 824 1 T3 15 T11 4 T37 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1762 1 T1 1 T3 35 T8 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1540 1 T1 1 T3 31 T8 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1052 1 T3 24 T11 2 T12 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 852 1 T3 18 T11 2 T37 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 990 1 T1 1 T3 13 T11 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 804 1 T1 1 T3 8 T11 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1125 1 T1 1 T3 32 T11 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 889 1 T1 1 T3 24 T11 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1072 1 T3 20 T11 2 T53 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 883 1 T3 9 T11 2 T53 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1040 1 T3 29 T11 1 T53 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 835 1 T3 24 T11 1 T53 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 999 1 T3 31 T11 2 T37 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 786 1 T3 22 T11 2 T37 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1001 1 T3 27 T11 5 T37 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 816 1 T3 22 T11 5 T37 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1018 1 T3 27 T11 1 T53 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 788 1 T3 18 T11 1 T23 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1045 1 T3 19 T11 1 T37 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 846 1 T3 14 T11 1 T37 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1079 1 T3 31 T8 1 T12 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 857 1 T3 24 T8 1 T37 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1047 1 T3 19 T8 1 T11 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 813 1 T3 11 T8 1 T11 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1132 1 T3 27 T11 1 T37 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 888 1 T3 19 T11 1 T37 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 997 1 T3 15 T8 1 T11 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 795 1 T3 11 T8 1 T11 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1045 1 T3 15 T74 1 T23 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 853 1 T3 12 T74 1 T23 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1017 1 T3 16 T11 1 T37 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 811 1 T3 13 T11 1 T37 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1058 1 T1 1 T3 19 T12 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 839 1 T1 1 T3 16 T37 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1077 1 T3 15 T8 1 T74 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 868 1 T3 10 T8 1 T74 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1111 1 T3 27 T37 1 T74 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 913 1 T3 22 T37 1 T74 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1000 1 T3 18 T11 2 T37 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 804 1 T3 14 T11 2 T37 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1020 1 T1 1 T3 23 T11 5
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 806 1 T1 1 T3 18 T11 5
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1031 1 T3 29 T11 5 T12 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 831 1 T3 22 T11 5 T37 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1036 1 T3 19 T11 2 T37 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 828 1 T3 15 T11 2 T37 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1025 1 T3 18 T74 2 T23 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 829 1 T3 14 T74 2 T23 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1088 1 T1 1 T3 9 T23 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 868 1 T1 1 T3 8 T23 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1056 1 T3 29 T8 1 T11 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 886 1 T3 26 T8 1 T11 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1036 1 T3 25 T8 1 T53 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 793 1 T3 15 T8 1 T17 7
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1047 1 T3 20 T8 1 T12 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 840 1 T3 16 T8 1 T23 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1043 1 T1 1 T3 22 T11 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 816 1 T1 1 T3 15 T11 2

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