Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.74 98.23 96.58 90.98 96.00 96.37 100.00 99.02


Total test records in report: 1120
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T1013 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.984159320 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:05 PM PDT 24 29910835 ps
T69 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2572939615 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:05 PM PDT 24 473237903 ps
T1014 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2177084478 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:50 PM PDT 24 28136212 ps
T1015 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.806735239 Jul 10 05:09:18 PM PDT 24 Jul 10 05:09:22 PM PDT 24 48534574 ps
T1016 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.4183070070 Jul 10 05:09:32 PM PDT 24 Jul 10 05:09:38 PM PDT 24 21558883 ps
T1017 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3816606190 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:18 PM PDT 24 54887251 ps
T157 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.455895449 Jul 10 05:09:07 PM PDT 24 Jul 10 05:09:09 PM PDT 24 146017804 ps
T1018 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1257598484 Jul 10 05:08:58 PM PDT 24 Jul 10 05:09:00 PM PDT 24 68419745 ps
T1019 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3076730318 Jul 10 05:09:10 PM PDT 24 Jul 10 05:09:13 PM PDT 24 147995036 ps
T1020 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.334717475 Jul 10 05:09:17 PM PDT 24 Jul 10 05:09:21 PM PDT 24 18470013 ps
T1021 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2049667343 Jul 10 05:09:27 PM PDT 24 Jul 10 05:09:30 PM PDT 24 16270979 ps
T1022 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2790522408 Jul 10 05:09:09 PM PDT 24 Jul 10 05:09:12 PM PDT 24 41230092 ps
T1023 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2684952302 Jul 10 05:08:58 PM PDT 24 Jul 10 05:09:00 PM PDT 24 41648799 ps
T1024 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3768510879 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:04 PM PDT 24 46736871 ps
T1025 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3695869087 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:32 PM PDT 24 32422143 ps
T1026 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.158528408 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 89259808 ps
T66 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1148171124 Jul 10 05:09:09 PM PDT 24 Jul 10 05:09:13 PM PDT 24 312354005 ps
T1027 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3128053632 Jul 10 05:09:24 PM PDT 24 Jul 10 05:09:27 PM PDT 24 24421259 ps
T1028 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.682002146 Jul 10 05:09:03 PM PDT 24 Jul 10 05:09:07 PM PDT 24 93747657 ps
T1029 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.523435685 Jul 10 05:09:19 PM PDT 24 Jul 10 05:09:22 PM PDT 24 34221584 ps
T1030 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.277564934 Jul 10 05:09:24 PM PDT 24 Jul 10 05:09:27 PM PDT 24 21186608 ps
T1031 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.814349711 Jul 10 05:08:32 PM PDT 24 Jul 10 05:08:35 PM PDT 24 123126755 ps
T1032 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1221940302 Jul 10 05:09:11 PM PDT 24 Jul 10 05:09:15 PM PDT 24 275686273 ps
T1033 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2099051747 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:10 PM PDT 24 76641616 ps
T1034 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1143330413 Jul 10 05:09:04 PM PDT 24 Jul 10 05:09:08 PM PDT 24 184493460 ps
T1035 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2701768982 Jul 10 05:09:26 PM PDT 24 Jul 10 05:09:29 PM PDT 24 16534799 ps
T1036 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1701194808 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:48 PM PDT 24 183347196 ps
T1037 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.85203318 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 191487888 ps
T1038 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4237092313 Jul 10 05:09:05 PM PDT 24 Jul 10 05:09:08 PM PDT 24 38984718 ps
T1039 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1266264031 Jul 10 05:08:47 PM PDT 24 Jul 10 05:08:53 PM PDT 24 1182924414 ps
T1040 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2325546345 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:18 PM PDT 24 22258237 ps
T1041 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.149273033 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:05 PM PDT 24 46082028 ps
T1042 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.797980529 Jul 10 05:09:06 PM PDT 24 Jul 10 05:09:09 PM PDT 24 162385235 ps
T1043 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2991433049 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 17592087 ps
T1044 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3051408884 Jul 10 05:09:22 PM PDT 24 Jul 10 05:09:25 PM PDT 24 38841351 ps
T1045 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.678999824 Jul 10 05:09:06 PM PDT 24 Jul 10 05:09:09 PM PDT 24 94718889 ps
T1046 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2098280425 Jul 10 05:09:23 PM PDT 24 Jul 10 05:09:26 PM PDT 24 20288444 ps
T105 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.4233561197 Jul 10 05:08:47 PM PDT 24 Jul 10 05:08:51 PM PDT 24 50174253 ps
T1047 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.926315479 Jul 10 05:08:46 PM PDT 24 Jul 10 05:08:52 PM PDT 24 47741270 ps
T1048 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3678451215 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:12 PM PDT 24 43806115 ps
T1049 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.582147158 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:47 PM PDT 24 108098272 ps
T1050 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.193073768 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:13 PM PDT 24 614730108 ps
T158 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1650931087 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:10 PM PDT 24 115181345 ps
T106 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2758382 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:17 PM PDT 24 57708875 ps
T1051 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3430498818 Jul 10 05:08:46 PM PDT 24 Jul 10 05:08:51 PM PDT 24 31103815 ps
T1052 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1823840924 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:02 PM PDT 24 23133793 ps
T1053 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3040048985 Jul 10 05:09:17 PM PDT 24 Jul 10 05:09:21 PM PDT 24 23426045 ps
T1054 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2036808548 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:03 PM PDT 24 341016091 ps
T1055 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1126438370 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:18 PM PDT 24 38930980 ps
T1056 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.372095475 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:18 PM PDT 24 18050057 ps
T70 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2499336818 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:02 PM PDT 24 91955324 ps
T1057 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2840730510 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:17 PM PDT 24 142670610 ps
T1058 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1260809576 Jul 10 05:09:11 PM PDT 24 Jul 10 05:09:14 PM PDT 24 18791561 ps
T1059 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.88630129 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:05 PM PDT 24 29419988 ps
T1060 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.679653689 Jul 10 05:09:17 PM PDT 24 Jul 10 05:09:20 PM PDT 24 32263035 ps
T109 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2069370973 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:49 PM PDT 24 1425567977 ps
T1061 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3063004863 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:17 PM PDT 24 81061333 ps
T1062 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.686376839 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:04 PM PDT 24 60946065 ps
T1063 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2691148100 Jul 10 05:09:25 PM PDT 24 Jul 10 05:09:29 PM PDT 24 110393619 ps
T1064 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.435606102 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 25922995 ps
T1065 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2839688380 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:17 PM PDT 24 24102864 ps
T1066 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.49167346 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 63750038 ps
T1067 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4004162556 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:05 PM PDT 24 41360618 ps
T107 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1397862434 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:03 PM PDT 24 22070970 ps
T1068 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2481432370 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:10 PM PDT 24 46062383 ps
T1069 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3044029635 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 91242007 ps
T1070 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3168691909 Jul 10 05:08:47 PM PDT 24 Jul 10 05:08:53 PM PDT 24 193800821 ps
T1071 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2343852221 Jul 10 05:09:14 PM PDT 24 Jul 10 05:09:18 PM PDT 24 28637057 ps
T1072 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.170021527 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 33405439 ps
T1073 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.33300593 Jul 10 05:09:26 PM PDT 24 Jul 10 05:09:30 PM PDT 24 110843632 ps
T71 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1961371828 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:18 PM PDT 24 187214640 ps
T108 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3264981270 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:04 PM PDT 24 76356718 ps
T1074 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3326770078 Jul 10 05:09:11 PM PDT 24 Jul 10 05:09:16 PM PDT 24 57014687 ps
T1075 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2321490528 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:17 PM PDT 24 65779224 ps
T1076 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2417997106 Jul 10 05:08:45 PM PDT 24 Jul 10 05:08:50 PM PDT 24 32994653 ps
T1077 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2544915763 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:02 PM PDT 24 36445663 ps
T1078 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2339793973 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:02 PM PDT 24 44176049 ps
T1079 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3134088639 Jul 10 05:08:44 PM PDT 24 Jul 10 05:08:49 PM PDT 24 44675237 ps
T1080 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2067600449 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:49 PM PDT 24 116026410 ps
T110 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3202857775 Jul 10 05:09:08 PM PDT 24 Jul 10 05:09:10 PM PDT 24 47636049 ps
T1081 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2237692564 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:03 PM PDT 24 74797315 ps
T1082 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.156187330 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:47 PM PDT 24 87147095 ps
T1083 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2861672697 Jul 10 05:09:26 PM PDT 24 Jul 10 05:09:29 PM PDT 24 51153755 ps
T1084 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2005231615 Jul 10 05:08:45 PM PDT 24 Jul 10 05:08:51 PM PDT 24 158276742 ps
T1085 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2047748938 Jul 10 05:09:18 PM PDT 24 Jul 10 05:09:22 PM PDT 24 20549996 ps
T1086 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1096164334 Jul 10 05:09:10 PM PDT 24 Jul 10 05:09:15 PM PDT 24 660702977 ps
T1087 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4179667690 Jul 10 05:09:16 PM PDT 24 Jul 10 05:09:20 PM PDT 24 27342473 ps
T1088 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1868953568 Jul 10 05:09:26 PM PDT 24 Jul 10 05:09:30 PM PDT 24 21071861 ps
T1089 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1600101499 Jul 10 05:09:10 PM PDT 24 Jul 10 05:09:14 PM PDT 24 213310162 ps
T1090 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3742132341 Jul 10 05:09:10 PM PDT 24 Jul 10 05:09:15 PM PDT 24 239770536 ps
T1091 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3774476774 Jul 10 05:09:15 PM PDT 24 Jul 10 05:09:20 PM PDT 24 26412380 ps
T1092 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3588968319 Jul 10 05:08:42 PM PDT 24 Jul 10 05:08:46 PM PDT 24 24962398 ps
T1093 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.216396822 Jul 10 05:08:43 PM PDT 24 Jul 10 05:08:47 PM PDT 24 41461084 ps
T1094 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1126602086 Jul 10 05:09:09 PM PDT 24 Jul 10 05:09:12 PM PDT 24 18767119 ps
T1095 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2591569977 Jul 10 05:09:10 PM PDT 24 Jul 10 05:09:14 PM PDT 24 39433004 ps
T1096 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1687541485 Jul 10 05:08:33 PM PDT 24 Jul 10 05:08:38 PM PDT 24 960894781 ps
T1097 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3731462519 Jul 10 05:09:17 PM PDT 24 Jul 10 05:09:20 PM PDT 24 119813570 ps
T1098 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2215174060 Jul 10 05:08:47 PM PDT 24 Jul 10 05:08:52 PM PDT 24 20107410 ps
T1099 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2512505953 Jul 10 05:09:25 PM PDT 24 Jul 10 05:09:29 PM PDT 24 58796253 ps
T1100 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1402690510 Jul 10 05:08:46 PM PDT 24 Jul 10 05:08:51 PM PDT 24 51424816 ps
T1101 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1156260264 Jul 10 05:09:25 PM PDT 24 Jul 10 05:09:28 PM PDT 24 18956932 ps
T1102 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1122178039 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:04 PM PDT 24 34475296 ps
T1103 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1269991531 Jul 10 05:09:25 PM PDT 24 Jul 10 05:09:28 PM PDT 24 20265030 ps
T1104 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3974403301 Jul 10 05:09:09 PM PDT 24 Jul 10 05:09:12 PM PDT 24 113376838 ps
T1105 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.647114853 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:03 PM PDT 24 81384930 ps
T1106 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.342399995 Jul 10 05:08:46 PM PDT 24 Jul 10 05:08:52 PM PDT 24 422573582 ps
T1107 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1450031102 Jul 10 05:09:00 PM PDT 24 Jul 10 05:09:04 PM PDT 24 85513849 ps
T1108 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.4086848004 Jul 10 05:09:26 PM PDT 24 Jul 10 05:09:29 PM PDT 24 26719128 ps
T1109 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2243473847 Jul 10 05:09:25 PM PDT 24 Jul 10 05:09:29 PM PDT 24 20708139 ps
T1110 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.705757399 Jul 10 05:09:23 PM PDT 24 Jul 10 05:09:26 PM PDT 24 19360250 ps
T1111 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1342806858 Jul 10 05:09:18 PM PDT 24 Jul 10 05:09:22 PM PDT 24 73834998 ps
T1112 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1074910860 Jul 10 05:09:17 PM PDT 24 Jul 10 05:09:21 PM PDT 24 93230257 ps
T1113 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.523957106 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:05 PM PDT 24 119898939 ps
T1114 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1190726609 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:06 PM PDT 24 38764708 ps
T1115 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1469689851 Jul 10 05:09:13 PM PDT 24 Jul 10 05:09:17 PM PDT 24 19548102 ps
T1116 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1821428924 Jul 10 05:09:01 PM PDT 24 Jul 10 05:09:06 PM PDT 24 48305730 ps
T1117 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2997066578 Jul 10 05:08:46 PM PDT 24 Jul 10 05:08:51 PM PDT 24 26834994 ps
T1118 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.384929779 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:03 PM PDT 24 55209781 ps
T1119 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1413018892 Jul 10 05:09:07 PM PDT 24 Jul 10 05:09:10 PM PDT 24 24363046 ps
T1120 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3265212100 Jul 10 05:08:59 PM PDT 24 Jul 10 05:09:02 PM PDT 24 106849451 ps

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2166521288
Short name T3
Test name
Test status
Simulation time 9660680974 ps
CPU time 35.36 seconds
Started Jul 10 05:13:48 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 200920 kb
Host smart-a8c27902-7f3c-403a-83a4-a2dc50532666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166521288 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.2166521288
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2759552274
Short name T174
Test name
Test status
Simulation time 119382846 ps
CPU time 0.85 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 209232 kb
Host smart-66a1ae54-dc98-46a8-884e-89186ec846b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759552274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2759552274
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2856787852
Short name T43
Test name
Test status
Simulation time 43162446 ps
CPU time 0.75 seconds
Started Jul 10 05:12:12 PM PDT 24
Finished Jul 10 05:12:14 PM PDT 24
Peak memory 201144 kb
Host smart-9bb67e34-ed1f-411c-a652-58cdce6bd62f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856787852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2856787852
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2605118635
Short name T52
Test name
Test status
Simulation time 874887946 ps
CPU time 1.58 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 195320 kb
Host smart-fce4b102-004b-4069-bfc1-262f43b877b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605118635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2605118635
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3878440083
Short name T151
Test name
Test status
Simulation time 1353261791 ps
CPU time 2.11 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 200756 kb
Host smart-0c389448-4ac5-49ac-8f90-57019ff0342d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878440083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3878440083
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2267263756
Short name T4
Test name
Test status
Simulation time 339095073 ps
CPU time 1.54 seconds
Started Jul 10 05:12:11 PM PDT 24
Finished Jul 10 05:12:14 PM PDT 24
Peak memory 216352 kb
Host smart-a1161b41-7d1f-4f7c-9926-a8ee74568bf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267263756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2267263756
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2233531269
Short name T62
Test name
Test status
Simulation time 223991674 ps
CPU time 0.64 seconds
Started Jul 10 05:09:16 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 194988 kb
Host smart-618cc738-4ff8-4e94-9a3e-5f43474e8343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233531269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2233531269
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3581795210
Short name T57
Test name
Test status
Simulation time 313301891 ps
CPU time 3.4 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:07 PM PDT 24
Peak memory 199064 kb
Host smart-fc754805-aa29-47ee-a39d-4716d9879606
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581795210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.3
581795210
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2048286381
Short name T32
Test name
Test status
Simulation time 938675741 ps
CPU time 0.97 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:21 PM PDT 24
Peak memory 197732 kb
Host smart-c4f67563-2743-49f8-9dc4-d3c6607a3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048286381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2048286381
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.3823632012
Short name T17
Test name
Test status
Simulation time 3007654140 ps
CPU time 10.95 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:55 PM PDT 24
Peak memory 200980 kb
Host smart-f4dff8d4-a1a0-4ba1-83d1-ff01a3a12877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823632012 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.3823632012
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.4227544701
Short name T50
Test name
Test status
Simulation time 49988000 ps
CPU time 2.26 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 197544 kb
Host smart-86252c1c-ff40-4a0a-a25d-5ccccd3e2c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227544701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.4227544701
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2845700958
Short name T248
Test name
Test status
Simulation time 100105716 ps
CPU time 0.7 seconds
Started Jul 10 05:12:15 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 198340 kb
Host smart-acab3cb5-39e8-41e7-ab2c-e5b9758637c3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845700958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.2845700958
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3177251465
Short name T12
Test name
Test status
Simulation time 44102830 ps
CPU time 0.9 seconds
Started Jul 10 05:15:00 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 199928 kb
Host smart-5077f9a7-d320-4137-8ee4-037bc3a06940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177251465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3177251465
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1085089667
Short name T31
Test name
Test status
Simulation time 51343319 ps
CPU time 0.78 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 198872 kb
Host smart-74f78970-7637-44c3-808b-638ce6d1e9c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085089667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1085089667
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2086275270
Short name T47
Test name
Test status
Simulation time 243566588 ps
CPU time 1.09 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:50 PM PDT 24
Peak memory 195252 kb
Host smart-c700fa3d-8760-4329-ba4e-6b39e948ad23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086275270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2086275270
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.334717475
Short name T1020
Test name
Test status
Simulation time 18470013 ps
CPU time 0.62 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:21 PM PDT 24
Peak memory 195016 kb
Host smart-afcb431c-fcf2-4839-925e-971fcc44ab85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334717475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.334717475
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.2221033895
Short name T168
Test name
Test status
Simulation time 152776084 ps
CPU time 0.7 seconds
Started Jul 10 05:15:01 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 198808 kb
Host smart-c0a89fb9-0e44-4205-bffc-93e1e11b37cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221033895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.2221033895
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.188630261
Short name T113
Test name
Test status
Simulation time 27252994 ps
CPU time 0.66 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 195172 kb
Host smart-1188d5f4-015d-4cef-9a59-ab9c25d597eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188630261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.188630261
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.4097142515
Short name T95
Test name
Test status
Simulation time 37932044 ps
CPU time 0.94 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 200428 kb
Host smart-7556091c-c508-40db-b35f-1ad0079724c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097142515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.4097142515
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3273453189
Short name T156
Test name
Test status
Simulation time 268600268 ps
CPU time 1.61 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:08:36 PM PDT 24
Peak memory 195380 kb
Host smart-aa712993-89ba-4f4e-a763-28d7a9021d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273453189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.3273453189
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3143664910
Short name T167
Test name
Test status
Simulation time 79099846 ps
CPU time 0.72 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198872 kb
Host smart-613f9579-0d22-4e29-b0e3-80e515d79220
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143664910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3143664910
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1266264031
Short name T1039
Test name
Test status
Simulation time 1182924414 ps
CPU time 2.43 seconds
Started Jul 10 05:08:47 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 197304 kb
Host smart-cf9d1b6f-654a-4227-9d59-cfa0ea23202e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266264031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.1266264031
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2572939615
Short name T69
Test name
Test status
Simulation time 473237903 ps
CPU time 1.48 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 200140 kb
Host smart-8b24cf67-126a-447b-876c-65370f90460a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572939615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.2572939615
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.974596566
Short name T28
Test name
Test status
Simulation time 165937201 ps
CPU time 0.63 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:13 PM PDT 24
Peak memory 197044 kb
Host smart-c6dd7252-3ddd-4ea0-b644-2a4dec51046d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974596566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.974596566
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.2062822680
Short name T1
Test name
Test status
Simulation time 291752966 ps
CPU time 0.76 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:12 PM PDT 24
Peak memory 197952 kb
Host smart-f2453639-7f90-4311-8dcb-5e954c180835
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062822680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.2062822680
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3951024321
Short name T101
Test name
Test status
Simulation time 33178855 ps
CPU time 0.79 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 194988 kb
Host smart-57b6d583-597e-4aff-8d32-bcc7da8bacd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951024321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3
951024321
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2067600449
Short name T1080
Test name
Test status
Simulation time 116026410 ps
CPU time 1.9 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 195160 kb
Host smart-6657180a-3e03-41e3-8ce5-18fd65fc4500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067600449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.2
067600449
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2133082323
Short name T102
Test name
Test status
Simulation time 116589950 ps
CPU time 0.61 seconds
Started Jul 10 05:08:31 PM PDT 24
Finished Jul 10 05:08:33 PM PDT 24
Peak memory 195064 kb
Host smart-4f45aec6-3d02-49ed-9a5c-9d65a3f8e754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133082323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
133082323
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.156187330
Short name T1082
Test name
Test status
Simulation time 87147095 ps
CPU time 0.74 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:47 PM PDT 24
Peak memory 195124 kb
Host smart-ca4c3036-677f-493e-9ada-010a7dc83ac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156187330 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.156187330
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3588968319
Short name T1092
Test name
Test status
Simulation time 24962398 ps
CPU time 0.62 seconds
Started Jul 10 05:08:42 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 195136 kb
Host smart-4fec807e-ac77-41fd-9b71-87d1d5eb9524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588968319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3588968319
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.814349711
Short name T1031
Test name
Test status
Simulation time 123126755 ps
CPU time 0.62 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:08:35 PM PDT 24
Peak memory 194996 kb
Host smart-3b6c9841-3595-4bda-90ca-30f855ffef20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814349711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.814349711
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2997066578
Short name T1117
Test name
Test status
Simulation time 26834994 ps
CPU time 0.73 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 197252 kb
Host smart-6b903723-d16c-476c-8cb5-7e27d855a149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997066578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2997066578
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1687541485
Short name T1096
Test name
Test status
Simulation time 960894781 ps
CPU time 2.44 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:08:38 PM PDT 24
Peak memory 196448 kb
Host smart-b8d2c17f-d7cb-429b-8811-a3f8a90bbc72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687541485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1687541485
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.4233561197
Short name T105
Test name
Test status
Simulation time 50174253 ps
CPU time 0.8 seconds
Started Jul 10 05:08:47 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 197400 kb
Host smart-c93ec020-c3b0-4bbc-953f-a0fb0ab8947a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233561197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.4
233561197
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2069370973
Short name T109
Test name
Test status
Simulation time 1425567977 ps
CPU time 3.49 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 195260 kb
Host smart-5a799da6-d1ca-4b8e-aeb6-6ee746474751
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069370973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
069370973
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2417997106
Short name T1076
Test name
Test status
Simulation time 32994653 ps
CPU time 0.77 seconds
Started Jul 10 05:08:45 PM PDT 24
Finished Jul 10 05:08:50 PM PDT 24
Peak memory 197316 kb
Host smart-3dfaea40-b896-4938-9419-2b88b1840a47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417997106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
417997106
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.216396822
Short name T1093
Test name
Test status
Simulation time 41461084 ps
CPU time 0.96 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:47 PM PDT 24
Peak memory 195104 kb
Host smart-9b148efb-490a-44de-b92a-2868628e5181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216396822 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.216396822
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2215174060
Short name T1098
Test name
Test status
Simulation time 20107410 ps
CPU time 0.64 seconds
Started Jul 10 05:08:47 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 197292 kb
Host smart-12d8f09d-fe53-47b8-ae83-a1d7a7f98c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215174060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2215174060
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3921700744
Short name T1006
Test name
Test status
Simulation time 51930963 ps
CPU time 0.64 seconds
Started Jul 10 05:08:45 PM PDT 24
Finished Jul 10 05:08:50 PM PDT 24
Peak memory 194948 kb
Host smart-adf5472d-f7d3-4290-bbfd-c2a133cd9c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921700744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3921700744
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.170021527
Short name T1072
Test name
Test status
Simulation time 33405439 ps
CPU time 0.75 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 199452 kb
Host smart-47e40972-d47a-4c5c-bbe3-380bbb786e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170021527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.170021527
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1701194808
Short name T1036
Test name
Test status
Simulation time 183347196 ps
CPU time 1.55 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:48 PM PDT 24
Peak memory 200592 kb
Host smart-3e7c0310-fef0-4181-a6f8-923d9315b8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701194808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1701194808
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.647114853
Short name T1105
Test name
Test status
Simulation time 81384930 ps
CPU time 1.07 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 196628 kb
Host smart-f249a091-54de-413e-8147-482ef53ffdac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647114853 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.647114853
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3264981270
Short name T108
Test name
Test status
Simulation time 76356718 ps
CPU time 0.71 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 197068 kb
Host smart-786546f2-043c-4051-9ed3-062cce8b540d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264981270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3264981270
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.984159320
Short name T1013
Test name
Test status
Simulation time 29910835 ps
CPU time 0.62 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 195004 kb
Host smart-f6c83238-41a8-4233-8931-67b4eedfc3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984159320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.984159320
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2544915763
Short name T1077
Test name
Test status
Simulation time 36445663 ps
CPU time 0.76 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 195024 kb
Host smart-a2c21fe9-e042-485d-ab52-98e5a4cac0c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544915763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.2544915763
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2215627071
Short name T68
Test name
Test status
Simulation time 388204497 ps
CPU time 2.06 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:07 PM PDT 24
Peak memory 197312 kb
Host smart-82cd1a7f-58e8-4a96-9330-83d1d6fe78fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215627071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2215627071
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1143330413
Short name T1034
Test name
Test status
Simulation time 184493460 ps
CPU time 1.58 seconds
Started Jul 10 05:09:04 PM PDT 24
Finished Jul 10 05:09:08 PM PDT 24
Peak memory 200248 kb
Host smart-6d787282-6426-4269-a8d7-a040109e9811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143330413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1143330413
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4237092313
Short name T1038
Test name
Test status
Simulation time 38984718 ps
CPU time 0.78 seconds
Started Jul 10 05:09:05 PM PDT 24
Finished Jul 10 05:09:08 PM PDT 24
Peak memory 195136 kb
Host smart-8cdd9a0e-9cab-411a-8955-845558c25b06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237092313 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.4237092313
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2684952302
Short name T1023
Test name
Test status
Simulation time 41648799 ps
CPU time 0.6 seconds
Started Jul 10 05:08:58 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 194924 kb
Host smart-41e8c160-065f-42b9-814c-85bfcce57c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684952302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2684952302
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2339793973
Short name T1078
Test name
Test status
Simulation time 44176049 ps
CPU time 0.9 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 198704 kb
Host smart-45d0cd9a-b1a0-42d2-99f9-9299d0347cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339793973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.2339793973
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.352983753
Short name T60
Test name
Test status
Simulation time 45415652 ps
CPU time 1.12 seconds
Started Jul 10 05:08:58 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 196064 kb
Host smart-217bf66d-9e97-430e-9f96-0b2b8524acfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352983753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.352983753
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2099051747
Short name T1033
Test name
Test status
Simulation time 76641616 ps
CPU time 1.1 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 200408 kb
Host smart-6ba07b71-5959-472d-96af-a7bd37c33382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099051747 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2099051747
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3202857775
Short name T110
Test name
Test status
Simulation time 47636049 ps
CPU time 0.6 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 195152 kb
Host smart-3c94a471-8bae-4b62-9469-aa06fd244b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202857775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3202857775
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.997521792
Short name T1003
Test name
Test status
Simulation time 51793408 ps
CPU time 0.59 seconds
Started Jul 10 05:09:07 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 195004 kb
Host smart-6b3a4475-34bc-41b1-90a0-587ff03da707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997521792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.997521792
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2799830930
Short name T65
Test name
Test status
Simulation time 70370822 ps
CPU time 0.83 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 195040 kb
Host smart-4cea9791-fb19-46f9-b59c-9ee786924dd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799830930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2799830930
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2591569977
Short name T1095
Test name
Test status
Simulation time 39433004 ps
CPU time 1.61 seconds
Started Jul 10 05:09:10 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 197316 kb
Host smart-bbd5fb5a-ea6a-454b-a637-2dfb798547a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591569977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2591569977
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1096164334
Short name T1086
Test name
Test status
Simulation time 660702977 ps
CPU time 1.64 seconds
Started Jul 10 05:09:10 PM PDT 24
Finished Jul 10 05:09:15 PM PDT 24
Peak memory 200564 kb
Host smart-3a29aad5-8f74-4952-a1f3-d2ac56f33b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096164334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1096164334
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3076730318
Short name T1019
Test name
Test status
Simulation time 147995036 ps
CPU time 0.99 seconds
Started Jul 10 05:09:10 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 196132 kb
Host smart-e9c1b942-2ad3-4c01-892e-83dd318bb46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076730318 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3076730318
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2758382
Short name T106
Test name
Test status
Simulation time 57708875 ps
CPU time 0.66 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 198236 kb
Host smart-17585ab3-7c18-4563-ba48-e65f1e3f43fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2758382
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.3716269302
Short name T162
Test name
Test status
Simulation time 19111721 ps
CPU time 0.64 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 194920 kb
Host smart-d78a2f28-6c11-4ce8-860b-8cbae079af97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716269302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.3716269302
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1126438370
Short name T1055
Test name
Test status
Simulation time 38930980 ps
CPU time 0.94 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 195056 kb
Host smart-16827fcd-82e4-4848-b138-423e9ae7db9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126438370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1126438370
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3326770078
Short name T1074
Test name
Test status
Simulation time 57014687 ps
CPU time 2.73 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:16 PM PDT 24
Peak memory 197308 kb
Host smart-64d0ea39-8a9c-484b-89dc-e38909cdd046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326770078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3326770078
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.797980529
Short name T1042
Test name
Test status
Simulation time 162385235 ps
CPU time 1.68 seconds
Started Jul 10 05:09:06 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 200456 kb
Host smart-fbfde39e-6837-4c35-aec7-96961a10a5db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797980529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err
.797980529
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.874566082
Short name T1010
Test name
Test status
Simulation time 57341811 ps
CPU time 1.15 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 196248 kb
Host smart-f8dadb24-8159-487d-b5e3-04d84302b81d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874566082 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.874566082
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.372095475
Short name T1056
Test name
Test status
Simulation time 18050057 ps
CPU time 0.64 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 197136 kb
Host smart-9689baa9-d911-4f34-a000-04bcee09fb1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372095475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.372095475
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2481432370
Short name T1068
Test name
Test status
Simulation time 46062383 ps
CPU time 0.64 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 195000 kb
Host smart-87c9d57f-a14e-4aff-b047-c9c83fe231da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481432370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2481432370
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2840730510
Short name T1057
Test name
Test status
Simulation time 142670610 ps
CPU time 0.85 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 194988 kb
Host smart-f7d6c514-32e6-4673-8c86-2ba342a481b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840730510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2840730510
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2415803633
Short name T59
Test name
Test status
Simulation time 49474095 ps
CPU time 2.4 seconds
Started Jul 10 05:09:12 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 196456 kb
Host smart-aef22c35-0127-405f-9613-9b31b37ecaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415803633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2415803633
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1961371828
Short name T71
Test name
Test status
Simulation time 187214640 ps
CPU time 1.58 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 195228 kb
Host smart-c195dd1c-5d8f-4203-9348-9456919f6b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961371828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1961371828
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2107935054
Short name T164
Test name
Test status
Simulation time 55847317 ps
CPU time 0.68 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 195208 kb
Host smart-2d063688-c87d-428f-8ba5-5ddf6c8832ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107935054 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2107935054
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2325546345
Short name T1040
Test name
Test status
Simulation time 22258237 ps
CPU time 0.68 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 194988 kb
Host smart-eaa0bff6-322b-4116-854f-471e5e2d237e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325546345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2325546345
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3331936970
Short name T63
Test name
Test status
Simulation time 65935522 ps
CPU time 0.63 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 194920 kb
Host smart-5a5f63ff-9088-4256-99d1-1380a54aaf08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331936970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3331936970
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1600101499
Short name T1089
Test name
Test status
Simulation time 213310162 ps
CPU time 0.82 seconds
Started Jul 10 05:09:10 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 195040 kb
Host smart-ec62c10a-beb0-4a23-bc1b-fb97c0763f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600101499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1600101499
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1221940302
Short name T1032
Test name
Test status
Simulation time 275686273 ps
CPU time 1.33 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:15 PM PDT 24
Peak memory 196328 kb
Host smart-6fa032dc-5994-404f-87dc-9ba8aab5cd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221940302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1221940302
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1650931087
Short name T158
Test name
Test status
Simulation time 115181345 ps
CPU time 1.17 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 195060 kb
Host smart-c4ab75ad-fd41-44e7-9914-b1fde191b455
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650931087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1650931087
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3063004863
Short name T1061
Test name
Test status
Simulation time 81061333 ps
CPU time 1.17 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 196696 kb
Host smart-fbc520f3-06da-45cb-93be-621898a57276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063004863 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3063004863
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1469689851
Short name T1115
Test name
Test status
Simulation time 19548102 ps
CPU time 0.68 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 195084 kb
Host smart-93a44ede-4efe-4ddc-9a55-97a46c1b3aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469689851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1469689851
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1260809576
Short name T1058
Test name
Test status
Simulation time 18791561 ps
CPU time 0.62 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 194924 kb
Host smart-6819f902-44ff-4ac9-a603-e9a8385cbbe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260809576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1260809576
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3974403301
Short name T1104
Test name
Test status
Simulation time 113376838 ps
CPU time 0.69 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 197276 kb
Host smart-f47dfe70-4c2b-424e-9c02-8730d73e8f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974403301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3974403301
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.678999824
Short name T1045
Test name
Test status
Simulation time 94718889 ps
CPU time 1.56 seconds
Started Jul 10 05:09:06 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 196800 kb
Host smart-e29baa92-6732-4f82-9a22-98d7661ce91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678999824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.678999824
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1148171124
Short name T66
Test name
Test status
Simulation time 312354005 ps
CPU time 1.56 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 200532 kb
Host smart-6dca8955-a489-44fd-b75d-47af1f863bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148171124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.1148171124
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2321490528
Short name T1075
Test name
Test status
Simulation time 65779224 ps
CPU time 0.77 seconds
Started Jul 10 05:09:13 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 195128 kb
Host smart-dc9c896b-8cc8-4b34-9592-020abf15fa5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321490528 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.2321490528
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1413018892
Short name T1119
Test name
Test status
Simulation time 24363046 ps
CPU time 0.69 seconds
Started Jul 10 05:09:07 PM PDT 24
Finished Jul 10 05:09:10 PM PDT 24
Peak memory 195088 kb
Host smart-a6cf46c6-cd78-439a-8b9f-6e25c35004e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413018892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1413018892
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2212981670
Short name T1009
Test name
Test status
Simulation time 28837915 ps
CPU time 0.59 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 194924 kb
Host smart-85c472d0-c89b-4db7-8520-0b59c0fb2aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212981670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2212981670
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2343852221
Short name T1071
Test name
Test status
Simulation time 28637057 ps
CPU time 0.72 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 197248 kb
Host smart-962843c0-bc2b-4ed0-aa4a-5250a3cd0bea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343852221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2343852221
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.193073768
Short name T1050
Test name
Test status
Simulation time 614730108 ps
CPU time 2.85 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 197360 kb
Host smart-98c873c6-c5dc-4d07-b765-610a10889200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193073768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.193073768
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2357404116
Short name T51
Test name
Test status
Simulation time 740337283 ps
CPU time 1.58 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 195308 kb
Host smart-76c61ead-a160-4e07-b687-71cfd0d97a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357404116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.2357404116
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3816606190
Short name T1017
Test name
Test status
Simulation time 54887251 ps
CPU time 0.95 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 195208 kb
Host smart-914384e0-c043-4eaf-9031-975483194c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816606190 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3816606190
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.660244486
Short name T100
Test name
Test status
Simulation time 177920732 ps
CPU time 0.63 seconds
Started Jul 10 05:09:11 PM PDT 24
Finished Jul 10 05:09:14 PM PDT 24
Peak memory 195076 kb
Host smart-1319ab96-8d0d-4571-a2d2-c4e466b6a4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660244486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.660244486
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2839688380
Short name T1065
Test name
Test status
Simulation time 24102864 ps
CPU time 0.63 seconds
Started Jul 10 05:09:14 PM PDT 24
Finished Jul 10 05:09:17 PM PDT 24
Peak memory 194916 kb
Host smart-3bf4682f-73ca-450a-8cb2-41e85670e49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839688380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2839688380
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.309246445
Short name T114
Test name
Test status
Simulation time 122874805 ps
CPU time 0.88 seconds
Started Jul 10 05:09:18 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 198728 kb
Host smart-ebb508d2-90e3-436d-9d01-5e42b24a3bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309246445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.309246445
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3678451215
Short name T1048
Test name
Test status
Simulation time 43806115 ps
CPU time 2.05 seconds
Started Jul 10 05:09:08 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 196248 kb
Host smart-971cb2df-e44f-4ff5-ab92-5b057f4c3be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678451215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.3678451215
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3742132341
Short name T1090
Test name
Test status
Simulation time 239770536 ps
CPU time 1.56 seconds
Started Jul 10 05:09:10 PM PDT 24
Finished Jul 10 05:09:15 PM PDT 24
Peak memory 195248 kb
Host smart-034e6153-3ccd-4d61-9de3-8e41d68869e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742132341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3742132341
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2691148100
Short name T1063
Test name
Test status
Simulation time 110393619 ps
CPU time 1.31 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 195388 kb
Host smart-bda64504-3598-4f78-8ee1-3a751ff9a794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691148100 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2691148100
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3128053632
Short name T1027
Test name
Test status
Simulation time 24421259 ps
CPU time 0.62 seconds
Started Jul 10 05:09:24 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 196224 kb
Host smart-831f0b78-bc4a-41de-88aa-e339b5124c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128053632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3128053632
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4179667690
Short name T1087
Test name
Test status
Simulation time 27342473 ps
CPU time 0.6 seconds
Started Jul 10 05:09:16 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 195004 kb
Host smart-2a6df803-92a4-4bdd-ba39-5ff63467b581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179667690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4179667690
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3774476774
Short name T1091
Test name
Test status
Simulation time 26412380 ps
CPU time 0.77 seconds
Started Jul 10 05:09:15 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 195156 kb
Host smart-502a0ffb-c7b7-4525-b670-d88e438a14fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774476774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3774476774
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3679731302
Short name T67
Test name
Test status
Simulation time 351302505 ps
CPU time 2.07 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 196316 kb
Host smart-a11aa444-7d00-43df-99e0-676f124fe64d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679731302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3679731302
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1074910860
Short name T1112
Test name
Test status
Simulation time 93230257 ps
CPU time 1.18 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:21 PM PDT 24
Peak memory 200324 kb
Host smart-24963f34-25f5-4b97-a95e-b101e87151fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074910860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1074910860
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2821134784
Short name T1011
Test name
Test status
Simulation time 50090187 ps
CPU time 1.04 seconds
Started Jul 10 05:08:49 PM PDT 24
Finished Jul 10 05:08:54 PM PDT 24
Peak memory 194988 kb
Host smart-5e619ef9-cf13-4fc2-81c6-d8b120fece55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821134784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
821134784
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3168691909
Short name T1070
Test name
Test status
Simulation time 193800821 ps
CPU time 1.69 seconds
Started Jul 10 05:08:47 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 195252 kb
Host smart-7ea9ec48-1e4d-488e-ac64-9d08e5bdade1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168691909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
168691909
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3141287263
Short name T1001
Test name
Test status
Simulation time 142798427 ps
CPU time 0.63 seconds
Started Jul 10 05:08:49 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 195260 kb
Host smart-abc843b9-7326-4b0f-bb4e-24e8bf7c6d2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141287263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
141287263
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.158528408
Short name T1026
Test name
Test status
Simulation time 89259808 ps
CPU time 0.76 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 195128 kb
Host smart-b4515472-9bab-41ac-b381-4d172d380c93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158528408 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.158528408
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.49167346
Short name T1066
Test name
Test status
Simulation time 63750038 ps
CPU time 0.62 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 195068 kb
Host smart-a36dd94d-4382-43d7-8083-cad19146e1cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49167346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.49167346
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.582147158
Short name T1049
Test name
Test status
Simulation time 108098272 ps
CPU time 0.61 seconds
Started Jul 10 05:08:43 PM PDT 24
Finished Jul 10 05:08:47 PM PDT 24
Peak memory 194996 kb
Host smart-bd73539c-ab18-4631-a261-34da699ce22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582147158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.582147158
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3044029635
Short name T1069
Test name
Test status
Simulation time 91242007 ps
CPU time 0.73 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 197280 kb
Host smart-b64ceb2a-9e1f-409e-afe5-6f7faeccb9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044029635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3044029635
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2498870333
Short name T64
Test name
Test status
Simulation time 162903807 ps
CPU time 1.08 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:48 PM PDT 24
Peak memory 195288 kb
Host smart-d35c3864-5abd-414b-b2cf-597634265cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498870333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2498870333
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3896320112
Short name T1008
Test name
Test status
Simulation time 153103793 ps
CPU time 1.09 seconds
Started Jul 10 05:08:47 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 195228 kb
Host smart-e0d7af2e-427d-43bf-ae6c-c5bae78daeb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896320112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3896320112
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3198739446
Short name T1012
Test name
Test status
Simulation time 16374816 ps
CPU time 0.61 seconds
Started Jul 10 05:09:15 PM PDT 24
Finished Jul 10 05:09:19 PM PDT 24
Peak memory 194900 kb
Host smart-7956113b-9823-4e20-874f-e910037911b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198739446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3198739446
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2243473847
Short name T1109
Test name
Test status
Simulation time 20708139 ps
CPU time 0.62 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 194924 kb
Host smart-d130ce40-d545-488b-9f8c-01810f67ecf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243473847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2243473847
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.523435685
Short name T1029
Test name
Test status
Simulation time 34221584 ps
CPU time 0.59 seconds
Started Jul 10 05:09:19 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 195224 kb
Host smart-088c39e1-7d5e-4737-888c-70affcf4de78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523435685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.523435685
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1342806858
Short name T1111
Test name
Test status
Simulation time 73834998 ps
CPU time 0.63 seconds
Started Jul 10 05:09:18 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 195024 kb
Host smart-8ff358fd-a2b1-48e6-b311-19108043b9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342806858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1342806858
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2701768982
Short name T1035
Test name
Test status
Simulation time 16534799 ps
CPU time 0.6 seconds
Started Jul 10 05:09:26 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 194920 kb
Host smart-5a84e2b9-5aa9-42ef-b8a0-937ffa56607d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701768982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2701768982
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3040048985
Short name T1053
Test name
Test status
Simulation time 23426045 ps
CPU time 0.62 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:21 PM PDT 24
Peak memory 194924 kb
Host smart-47aaffe7-6d1f-4925-bd0f-8bb0070afeb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040048985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3040048985
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.4086848004
Short name T1108
Test name
Test status
Simulation time 26719128 ps
CPU time 0.61 seconds
Started Jul 10 05:09:26 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 194924 kb
Host smart-15f47cae-ba5a-49b3-aad0-21dbd25eff05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086848004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.4086848004
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3051408884
Short name T1044
Test name
Test status
Simulation time 38841351 ps
CPU time 0.61 seconds
Started Jul 10 05:09:22 PM PDT 24
Finished Jul 10 05:09:25 PM PDT 24
Peak memory 195196 kb
Host smart-7935ee5f-c327-4692-b720-96d420e540ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051408884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3051408884
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3731462519
Short name T1097
Test name
Test status
Simulation time 119813570 ps
CPU time 0.69 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 195004 kb
Host smart-f7d15f58-d12a-42a2-a941-c9a324456c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731462519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3731462519
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.85203318
Short name T1037
Test name
Test status
Simulation time 191487888 ps
CPU time 0.79 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 195112 kb
Host smart-4e9e0e33-c094-47f3-a4ac-c06da2f2eebd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85203318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.85203318
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.926315479
Short name T1047
Test name
Test status
Simulation time 47741270 ps
CPU time 1.7 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 195244 kb
Host smart-22b9d483-b27f-4556-9cd7-c4f7e6b69942
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926315479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.926315479
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2177084478
Short name T1014
Test name
Test status
Simulation time 28136212 ps
CPU time 0.69 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:50 PM PDT 24
Peak memory 197692 kb
Host smart-4e13a0d7-765b-458f-a4ff-cf5fcc8f54a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177084478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
177084478
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.411028363
Short name T1007
Test name
Test status
Simulation time 93779667 ps
CPU time 1.05 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 196156 kb
Host smart-b2b05c13-98fe-4a6b-b808-fbcda9d7f56b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411028363 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.411028363
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.435606102
Short name T1064
Test name
Test status
Simulation time 25922995 ps
CPU time 0.61 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 197392 kb
Host smart-6230297c-0dff-4a91-bdd8-7b18309f1700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435606102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.435606102
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2991433049
Short name T1043
Test name
Test status
Simulation time 17592087 ps
CPU time 0.63 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 194980 kb
Host smart-89f899a6-dc01-4585-b87c-77e547a8ff0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991433049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.2991433049
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3134088639
Short name T1079
Test name
Test status
Simulation time 44675237 ps
CPU time 0.74 seconds
Started Jul 10 05:08:44 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 197248 kb
Host smart-01e8f096-b37e-42f8-8122-d988bb88e22d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134088639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3134088639
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2005231615
Short name T1084
Test name
Test status
Simulation time 158276742 ps
CPU time 1.62 seconds
Started Jul 10 05:08:45 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 200596 kb
Host smart-0f169836-7cc5-453a-b0c3-3587bbbf5b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005231615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2005231615
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.806735239
Short name T1015
Test name
Test status
Simulation time 48534574 ps
CPU time 0.61 seconds
Started Jul 10 05:09:18 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 194912 kb
Host smart-0c1c43e9-e55a-4120-9945-6557da24021d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806735239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.806735239
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.746564544
Short name T1002
Test name
Test status
Simulation time 16578894 ps
CPU time 0.63 seconds
Started Jul 10 05:09:15 PM PDT 24
Finished Jul 10 05:09:19 PM PDT 24
Peak memory 194920 kb
Host smart-48b8b3aa-fee0-4866-bdb5-3546ca0c60c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746564544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.746564544
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.679653689
Short name T1060
Test name
Test status
Simulation time 32263035 ps
CPU time 0.6 seconds
Started Jul 10 05:09:17 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 194916 kb
Host smart-a0b45bae-d896-4b0b-a3f5-8a628eeda6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679653689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.679653689
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2861672697
Short name T1083
Test name
Test status
Simulation time 51153755 ps
CPU time 0.61 seconds
Started Jul 10 05:09:26 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 194924 kb
Host smart-6d203811-8d6d-4314-ab74-c08bac7f0fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861672697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2861672697
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2047748938
Short name T1085
Test name
Test status
Simulation time 20549996 ps
CPU time 0.62 seconds
Started Jul 10 05:09:18 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 194920 kb
Host smart-95363fd8-1c33-424c-bae5-eccbff1b6774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047748938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2047748938
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3695869087
Short name T1025
Test name
Test status
Simulation time 32422143 ps
CPU time 0.66 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 194988 kb
Host smart-295aa87e-5c31-4df9-b58e-716fc393305d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695869087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3695869087
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1156260264
Short name T1101
Test name
Test status
Simulation time 18956932 ps
CPU time 0.64 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:28 PM PDT 24
Peak memory 195024 kb
Host smart-9f652f87-201e-406a-99cc-dcb137f79efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156260264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1156260264
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1868953568
Short name T1088
Test name
Test status
Simulation time 21071861 ps
CPU time 0.61 seconds
Started Jul 10 05:09:26 PM PDT 24
Finished Jul 10 05:09:30 PM PDT 24
Peak memory 195004 kb
Host smart-fc8f8f58-5454-4746-9609-bf7ef83130a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868953568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1868953568
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2049667343
Short name T1021
Test name
Test status
Simulation time 16270979 ps
CPU time 0.61 seconds
Started Jul 10 05:09:27 PM PDT 24
Finished Jul 10 05:09:30 PM PDT 24
Peak memory 195004 kb
Host smart-153c8d1e-077a-482e-b0e5-9780abb8fc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049667343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2049667343
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2040901215
Short name T58
Test name
Test status
Simulation time 35383451 ps
CPU time 0.82 seconds
Started Jul 10 05:08:58 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 195072 kb
Host smart-8b99b47b-186a-4c2a-be12-28bef1e546f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040901215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2
040901215
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2735229383
Short name T1005
Test name
Test status
Simulation time 25332813 ps
CPU time 0.65 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 195052 kb
Host smart-3e776747-5d3b-4766-bb64-f1f09957830b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735229383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.2
735229383
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1450031102
Short name T1107
Test name
Test status
Simulation time 85513849 ps
CPU time 0.86 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 195224 kb
Host smart-d88b6097-2046-46e6-bd27-92aee04c917e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450031102 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1450031102
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2790522408
Short name T1022
Test name
Test status
Simulation time 41230092 ps
CPU time 0.6 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 197292 kb
Host smart-99ab7134-6cc0-4568-8f4d-32690d2c73d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790522408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2790522408
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1402690510
Short name T1100
Test name
Test status
Simulation time 51424816 ps
CPU time 0.64 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 194924 kb
Host smart-61fad2ce-50c0-4658-b610-284ecbd19d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402690510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1402690510
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.76856427
Short name T115
Test name
Test status
Simulation time 81167580 ps
CPU time 0.82 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 198276 kb
Host smart-1922c330-054b-41e5-a393-e6a25c3b2045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76856427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same
_csr_outstanding.76856427
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3430498818
Short name T1051
Test name
Test status
Simulation time 31103815 ps
CPU time 1.27 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 196280 kb
Host smart-b5890ee3-a6ce-480e-b276-06d826953050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430498818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3430498818
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.342399995
Short name T1106
Test name
Test status
Simulation time 422573582 ps
CPU time 1.58 seconds
Started Jul 10 05:08:46 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 200180 kb
Host smart-be4bb7f3-363b-40a7-a022-73bc0c1145a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342399995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
342399995
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.4183070070
Short name T1016
Test name
Test status
Simulation time 21558883 ps
CPU time 0.62 seconds
Started Jul 10 05:09:32 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 194924 kb
Host smart-bd80dbd4-dbbb-4913-b921-0f0538c2cfeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183070070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.4183070070
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.277564934
Short name T1030
Test name
Test status
Simulation time 21186608 ps
CPU time 0.61 seconds
Started Jul 10 05:09:24 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 195004 kb
Host smart-371a25dc-b2cd-4521-93fe-af6d96ca1177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277564934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.277564934
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2098280425
Short name T1046
Test name
Test status
Simulation time 20288444 ps
CPU time 0.6 seconds
Started Jul 10 05:09:23 PM PDT 24
Finished Jul 10 05:09:26 PM PDT 24
Peak memory 194920 kb
Host smart-71bfcae6-1032-49b0-9c6f-e394b8d431bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098280425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.2098280425
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2512505953
Short name T1099
Test name
Test status
Simulation time 58796253 ps
CPU time 0.6 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 195028 kb
Host smart-fe33b53e-76a2-40d7-9777-052d4191a84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512505953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2512505953
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2243670378
Short name T159
Test name
Test status
Simulation time 18034507 ps
CPU time 0.65 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 194988 kb
Host smart-87dd6a42-d9b6-4fae-b709-89ff1238f80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243670378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2243670378
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3263020288
Short name T61
Test name
Test status
Simulation time 44837353 ps
CPU time 0.61 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:29 PM PDT 24
Peak memory 194900 kb
Host smart-f9f769f5-80d3-480e-8790-0ea15363ca54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263020288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3263020288
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3341541655
Short name T160
Test name
Test status
Simulation time 21116332 ps
CPU time 0.64 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:28 PM PDT 24
Peak memory 195004 kb
Host smart-38698980-571b-4a10-9649-2f3c40503156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341541655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3341541655
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1269991531
Short name T1103
Test name
Test status
Simulation time 20265030 ps
CPU time 0.62 seconds
Started Jul 10 05:09:25 PM PDT 24
Finished Jul 10 05:09:28 PM PDT 24
Peak memory 194924 kb
Host smart-5b6b7c47-5ebc-4f4c-999e-78aec838afa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269991531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1269991531
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.33300593
Short name T1073
Test name
Test status
Simulation time 110843632 ps
CPU time 0.64 seconds
Started Jul 10 05:09:26 PM PDT 24
Finished Jul 10 05:09:30 PM PDT 24
Peak memory 194908 kb
Host smart-011d0d9d-e662-4bed-9c97-b4e454a4b5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.33300593
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.705757399
Short name T1110
Test name
Test status
Simulation time 19360250 ps
CPU time 0.64 seconds
Started Jul 10 05:09:23 PM PDT 24
Finished Jul 10 05:09:26 PM PDT 24
Peak memory 194924 kb
Host smart-b1fcaedb-b6fe-4e11-860a-87ce836bacdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705757399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.705757399
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.149273033
Short name T1041
Test name
Test status
Simulation time 46082028 ps
CPU time 0.83 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 195132 kb
Host smart-93383516-7133-4f21-a4bc-154c9df73694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149273033 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.149273033
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.686376839
Short name T1062
Test name
Test status
Simulation time 60946065 ps
CPU time 0.63 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 197288 kb
Host smart-40939cd9-2f44-4044-a0b1-9b1b36aceea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686376839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.686376839
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1126602086
Short name T1094
Test name
Test status
Simulation time 18767119 ps
CPU time 0.61 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 195000 kb
Host smart-71662c1b-a8a8-4185-b1e0-dbe559eb6bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126602086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1126602086
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1190726609
Short name T1114
Test name
Test status
Simulation time 38764708 ps
CPU time 0.73 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 198076 kb
Host smart-b5f33837-4bf1-4748-9f06-52077e994c59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190726609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.1190726609
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.523957106
Short name T1113
Test name
Test status
Simulation time 119898939 ps
CPU time 0.78 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 200448 kb
Host smart-4e8865b4-cd61-4f73-b584-fcd3cfca39bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523957106 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.523957106
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3676137659
Short name T104
Test name
Test status
Simulation time 41406683 ps
CPU time 0.63 seconds
Started Jul 10 05:08:58 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 196312 kb
Host smart-3f629b61-fbe1-4750-b8f3-aa99856e2c98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676137659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3676137659
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2237692564
Short name T1081
Test name
Test status
Simulation time 74797315 ps
CPU time 0.61 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 194924 kb
Host smart-c71d6b3a-cff0-46a7-b229-ac26504fa76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237692564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2237692564
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.682002146
Short name T1028
Test name
Test status
Simulation time 93747657 ps
CPU time 0.74 seconds
Started Jul 10 05:09:03 PM PDT 24
Finished Jul 10 05:09:07 PM PDT 24
Peak memory 197208 kb
Host smart-c06e0f20-9a37-460a-8244-8c9f0e326acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682002146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.682002146
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.88630129
Short name T1059
Test name
Test status
Simulation time 29419988 ps
CPU time 1.22 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 195468 kb
Host smart-252064cf-617b-4e79-8598-01379f423121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88630129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.88630129
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3265212100
Short name T1120
Test name
Test status
Simulation time 106849451 ps
CPU time 1.17 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 200388 kb
Host smart-30ffce3d-742d-4287-b607-98cfc3323557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265212100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3265212100
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3768510879
Short name T1024
Test name
Test status
Simulation time 46736871 ps
CPU time 0.87 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 195204 kb
Host smart-41f4fb46-65da-4ccd-b3be-2a371045396e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768510879 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.3768510879
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1974004337
Short name T103
Test name
Test status
Simulation time 20010536 ps
CPU time 0.66 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 195052 kb
Host smart-e518fc8f-8135-4b90-b701-1f13e1ac7d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974004337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1974004337
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1742753535
Short name T163
Test name
Test status
Simulation time 18339911 ps
CPU time 0.65 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 194920 kb
Host smart-e1afe353-0449-415a-a1d0-c773a84a4144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742753535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1742753535
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1432361435
Short name T112
Test name
Test status
Simulation time 65532724 ps
CPU time 0.86 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 195056 kb
Host smart-2903f634-6d75-4b8f-85eb-e0cda97b5b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432361435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1432361435
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1900524998
Short name T1004
Test name
Test status
Simulation time 365539216 ps
CPU time 1.44 seconds
Started Jul 10 05:09:03 PM PDT 24
Finished Jul 10 05:09:07 PM PDT 24
Peak memory 196556 kb
Host smart-11af7ee4-268b-4ed8-ac39-bb23fe1e0cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900524998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1900524998
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2036808548
Short name T1054
Test name
Test status
Simulation time 341016091 ps
CPU time 1.49 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 200284 kb
Host smart-a9504471-623f-42d0-8b61-21fe0f6ea5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036808548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2036808548
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4004162556
Short name T1067
Test name
Test status
Simulation time 41360618 ps
CPU time 0.79 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 194972 kb
Host smart-396247f9-acf4-4dd3-b032-04f73b13d4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004162556 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.4004162556
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1397862434
Short name T107
Test name
Test status
Simulation time 22070970 ps
CPU time 0.68 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 197220 kb
Host smart-6c0b5e64-68e9-4949-89fa-bae0c0230291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397862434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.1397862434
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1257598484
Short name T1018
Test name
Test status
Simulation time 68419745 ps
CPU time 0.61 seconds
Started Jul 10 05:08:58 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 194924 kb
Host smart-7a3c4b26-f000-4380-8ffa-9277a601bb35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257598484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1257598484
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1959292586
Short name T111
Test name
Test status
Simulation time 53064200 ps
CPU time 0.77 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 199660 kb
Host smart-28cca50d-316e-4666-b2ef-355df555751f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959292586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.1959292586
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1122178039
Short name T1102
Test name
Test status
Simulation time 34475296 ps
CPU time 1.45 seconds
Started Jul 10 05:09:00 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 196248 kb
Host smart-908ec301-4dbd-496f-a1c2-e47f70d09119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122178039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1122178039
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2499336818
Short name T70
Test name
Test status
Simulation time 91955324 ps
CPU time 1.13 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 200064 kb
Host smart-168af132-d9dd-4a51-acd8-2710a5ff0d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499336818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2499336818
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1821428924
Short name T1116
Test name
Test status
Simulation time 48305730 ps
CPU time 0.86 seconds
Started Jul 10 05:09:01 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 195200 kb
Host smart-94272648-b019-4f3b-a211-7548f570cbf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821428924 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1821428924
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1823840924
Short name T1052
Test name
Test status
Simulation time 23133793 ps
CPU time 0.68 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 197452 kb
Host smart-f1bc5566-a4a9-4ef5-b6b6-861fb5f70468
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823840924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1823840924
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2560710424
Short name T161
Test name
Test status
Simulation time 17482391 ps
CPU time 0.61 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 194912 kb
Host smart-3b883f1d-2614-49c5-a9a0-6960abe61df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560710424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2560710424
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.565340663
Short name T56
Test name
Test status
Simulation time 248543674 ps
CPU time 0.89 seconds
Started Jul 10 05:09:09 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 198260 kb
Host smart-e3987427-dda5-4a31-8469-40acb5cbfe04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565340663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.565340663
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.384929779
Short name T1118
Test name
Test status
Simulation time 55209781 ps
CPU time 1.33 seconds
Started Jul 10 05:08:59 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 196324 kb
Host smart-4b8d17af-210e-4a73-9501-88308c070c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384929779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.384929779
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.455895449
Short name T157
Test name
Test status
Simulation time 146017804 ps
CPU time 1.1 seconds
Started Jul 10 05:09:07 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 195236 kb
Host smart-7429994a-a3e5-41d5-9244-6475fa8b1405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455895449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
455895449
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1442723933
Short name T330
Test name
Test status
Simulation time 63359880 ps
CPU time 0.87 seconds
Started Jul 10 05:12:09 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 198820 kb
Host smart-82ce8722-4d46-42c5-80d8-81324c6af136
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442723933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1442723933
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1041723984
Short name T318
Test name
Test status
Simulation time 91939884 ps
CPU time 0.57 seconds
Started Jul 10 05:12:11 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 196984 kb
Host smart-d59db0cd-4c02-4da6-9162-35645c939d36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041723984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1041723984
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3892754837
Short name T143
Test name
Test status
Simulation time 167390617 ps
CPU time 0.98 seconds
Started Jul 10 05:12:09 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 198120 kb
Host smart-827fbb70-4ed6-4ef2-aa9e-dae3f3252bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892754837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3892754837
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3558895536
Short name T966
Test name
Test status
Simulation time 51146290 ps
CPU time 0.68 seconds
Started Jul 10 05:12:09 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 197748 kb
Host smart-51e61f73-2a03-4bca-bdd0-272cc3c28947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558895536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3558895536
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.4063754244
Short name T262
Test name
Test status
Simulation time 42106304 ps
CPU time 0.64 seconds
Started Jul 10 05:12:11 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 197700 kb
Host smart-2a3eebe9-0a5c-4157-9098-25c3ba40e9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063754244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.4063754244
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.3485339618
Short name T487
Test name
Test status
Simulation time 162849114 ps
CPU time 0.77 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 198428 kb
Host smart-0f2c1ba2-d1c6-4e53-bdaa-a28018e746f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485339618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.3485339618
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.2799472857
Short name T925
Test name
Test status
Simulation time 50606225 ps
CPU time 0.77 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 198804 kb
Host smart-051c0d63-9137-47fc-bb32-11482409fbbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799472857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2799472857
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.4073378596
Short name T549
Test name
Test status
Simulation time 262628567 ps
CPU time 0.78 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 209248 kb
Host smart-5b3c89fe-52b2-4502-abf7-c775e70c6e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073378596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.4073378596
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.395066242
Short name T723
Test name
Test status
Simulation time 34734848 ps
CPU time 0.69 seconds
Started Jul 10 05:12:09 PM PDT 24
Finished Jul 10 05:12:11 PM PDT 24
Peak memory 198316 kb
Host smart-54946872-70e0-4545-acdd-e38e43f14656
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395066242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm
_ctrl_config_regwen.395066242
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.199284354
Short name T783
Test name
Test status
Simulation time 851955877 ps
CPU time 3.02 seconds
Started Jul 10 05:12:04 PM PDT 24
Finished Jul 10 05:12:08 PM PDT 24
Peak memory 200860 kb
Host smart-0166eb2c-f11e-48fb-9bc2-d470352ddb9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199284354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.199284354
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1510324456
Short name T828
Test name
Test status
Simulation time 1009416705 ps
CPU time 2.18 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:08 PM PDT 24
Peak memory 200820 kb
Host smart-069f7200-b6a0-45a2-96c4-5a7067ff3519
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510324456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1510324456
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.922981673
Short name T307
Test name
Test status
Simulation time 80263546 ps
CPU time 0.85 seconds
Started Jul 10 05:12:06 PM PDT 24
Finished Jul 10 05:12:08 PM PDT 24
Peak memory 199204 kb
Host smart-c43b1085-4e60-449d-8db3-cc356e881100
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922981673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.922981673
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.709413553
Short name T263
Test name
Test status
Simulation time 117696044 ps
CPU time 0.67 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 198256 kb
Host smart-789a3773-c92b-447f-b7ba-85608c88d1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709413553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.709413553
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.1445795868
Short name T661
Test name
Test status
Simulation time 83611218 ps
CPU time 0.79 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 199164 kb
Host smart-6f3913e7-b91c-4f87-929e-59d59ff0ed33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445795868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.1445795868
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.577151263
Short name T79
Test name
Test status
Simulation time 13825838476 ps
CPU time 19.83 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 200972 kb
Host smart-b278ab0d-cf3e-4065-a49f-971c0cda46b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577151263 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.577151263
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.1247261163
Short name T274
Test name
Test status
Simulation time 217701741 ps
CPU time 1.16 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:08 PM PDT 24
Peak memory 199320 kb
Host smart-dccb19eb-0d71-462b-9c32-759389c34466
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247261163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.1247261163
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.3840454665
Short name T628
Test name
Test status
Simulation time 253850458 ps
CPU time 0.9 seconds
Started Jul 10 05:12:02 PM PDT 24
Finished Jul 10 05:12:04 PM PDT 24
Peak memory 199548 kb
Host smart-2c104a70-9430-4e7b-814b-338ff17a0249
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840454665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3840454665
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.649601476
Short name T852
Test name
Test status
Simulation time 110600772 ps
CPU time 0.76 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 198608 kb
Host smart-e7216486-e51a-4fa1-9652-077ff330a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649601476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.649601476
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1548981876
Short name T433
Test name
Test status
Simulation time 94864604 ps
CPU time 0.69 seconds
Started Jul 10 05:12:15 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 198792 kb
Host smart-f10afc83-98d3-474d-a5d0-97ab852a4eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548981876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1548981876
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3572816108
Short name T800
Test name
Test status
Simulation time 29643752 ps
CPU time 0.67 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 197100 kb
Host smart-97332c01-085a-489c-900f-3838e7c5b444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572816108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.3572816108
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.801974764
Short name T601
Test name
Test status
Simulation time 31294005 ps
CPU time 0.69 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 197808 kb
Host smart-194e711b-b196-47f0-817a-f7d655da781f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801974764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.801974764
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2576838111
Short name T41
Test name
Test status
Simulation time 24005128 ps
CPU time 0.6 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 197712 kb
Host smart-091ddf41-e740-4f3e-a38a-71a0cdc7573b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576838111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2576838111
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2121804288
Short name T290
Test name
Test status
Simulation time 53519697 ps
CPU time 0.72 seconds
Started Jul 10 05:12:15 PM PDT 24
Finished Jul 10 05:12:17 PM PDT 24
Peak memory 201080 kb
Host smart-4d84ed4b-95ba-42f9-bea8-2116cf74ce82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121804288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2121804288
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.3627560239
Short name T285
Test name
Test status
Simulation time 126009746 ps
CPU time 0.71 seconds
Started Jul 10 05:12:09 PM PDT 24
Finished Jul 10 05:12:11 PM PDT 24
Peak memory 198008 kb
Host smart-6620e753-5ba0-4020-83d4-7c4cb4791aa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627560239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.3627560239
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2615686809
Short name T851
Test name
Test status
Simulation time 111018695 ps
CPU time 0.65 seconds
Started Jul 10 05:12:15 PM PDT 24
Finished Jul 10 05:12:17 PM PDT 24
Peak memory 198796 kb
Host smart-07166ac3-de54-4838-ad77-dc859795a910
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615686809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2615686809
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.1114778063
Short name T597
Test name
Test status
Simulation time 164496159 ps
CPU time 0.86 seconds
Started Jul 10 05:12:16 PM PDT 24
Finished Jul 10 05:12:19 PM PDT 24
Peak memory 201056 kb
Host smart-46d4a0cb-1325-45a3-a5e1-f82b9bb8d1f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114778063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1114778063
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2764171938
Short name T25
Test name
Test status
Simulation time 607428522 ps
CPU time 1.09 seconds
Started Jul 10 05:12:16 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 216316 kb
Host smart-f6f71406-ef53-44e4-b479-fda577158f72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764171938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2764171938
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.246690375
Short name T429
Test name
Test status
Simulation time 1066405137 ps
CPU time 1.93 seconds
Started Jul 10 05:12:16 PM PDT 24
Finished Jul 10 05:12:21 PM PDT 24
Peak memory 200796 kb
Host smart-beef0152-3403-4464-954b-7fba4f6c159a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246690375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.246690375
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1016737966
Short name T333
Test name
Test status
Simulation time 958425922 ps
CPU time 2.27 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:22 PM PDT 24
Peak memory 200884 kb
Host smart-5086fcd3-0235-473c-ac3e-33d22347de4d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016737966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1016737966
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1766590016
Short name T816
Test name
Test status
Simulation time 64323415 ps
CPU time 0.88 seconds
Started Jul 10 05:12:16 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 199076 kb
Host smart-172edd3b-112c-4631-af21-95ce85f4c53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766590016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1766590016
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3374261139
Short name T476
Test name
Test status
Simulation time 28100456 ps
CPU time 0.75 seconds
Started Jul 10 05:12:13 PM PDT 24
Finished Jul 10 05:12:15 PM PDT 24
Peak memory 199132 kb
Host smart-64b5b14e-32ee-492d-b37e-e3be2e1c5d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374261139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3374261139
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.4014137547
Short name T464
Test name
Test status
Simulation time 999853775 ps
CPU time 4 seconds
Started Jul 10 05:12:18 PM PDT 24
Finished Jul 10 05:12:24 PM PDT 24
Peak memory 200864 kb
Host smart-40d2f560-b3d6-4f4d-a831-918defb7d3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014137547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.4014137547
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3224324239
Short name T122
Test name
Test status
Simulation time 9836860972 ps
CPU time 13.4 seconds
Started Jul 10 05:12:17 PM PDT 24
Finished Jul 10 05:12:33 PM PDT 24
Peak memory 201024 kb
Host smart-2d424d9f-9523-49a9-a549-61047347ae27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224324239 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.3224324239
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.4092051906
Short name T645
Test name
Test status
Simulation time 198388787 ps
CPU time 0.91 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 198228 kb
Host smart-4059cc6e-32d0-4327-9158-7c55ee1d72a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092051906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.4092051906
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.3476957138
Short name T200
Test name
Test status
Simulation time 404373423 ps
CPU time 1.04 seconds
Started Jul 10 05:12:10 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 200712 kb
Host smart-17213d94-806a-40a1-aca7-87e78e8afeae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476957138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3476957138
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2346828583
Short name T491
Test name
Test status
Simulation time 59409844 ps
CPU time 0.77 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 199760 kb
Host smart-c6cba940-2b32-4b8a-be6f-cdbbe1a24167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346828583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2346828583
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1464378519
Short name T641
Test name
Test status
Simulation time 68375853 ps
CPU time 0.7 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 198188 kb
Host smart-34df7974-8312-4ed6-ad73-26bf2b332b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464378519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1464378519
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1563029005
Short name T441
Test name
Test status
Simulation time 39055224 ps
CPU time 0.6 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 197724 kb
Host smart-23663a48-fb2a-4ecf-b744-ac25da55915e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563029005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1563029005
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.1702884563
Short name T265
Test name
Test status
Simulation time 311238857 ps
CPU time 0.95 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:08 PM PDT 24
Peak memory 197740 kb
Host smart-ab92ff88-55f8-45e6-bc66-f52ee629591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702884563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1702884563
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.4137869186
Short name T368
Test name
Test status
Simulation time 132516968 ps
CPU time 0.6 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 197676 kb
Host smart-0ec48bc3-9335-43cf-96a9-d30567eee8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137869186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.4137869186
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.1714673674
Short name T177
Test name
Test status
Simulation time 88226232 ps
CPU time 0.63 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 198088 kb
Host smart-55c810a2-f1fc-4491-a305-6ae1dcdc070c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714673674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1714673674
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.2008548549
Short name T660
Test name
Test status
Simulation time 55614649 ps
CPU time 0.75 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 201072 kb
Host smart-88339cb9-1f90-4662-a02f-dac36e507c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008548549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.2008548549
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.1760552798
Short name T592
Test name
Test status
Simulation time 654599861 ps
CPU time 0.89 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 199300 kb
Host smart-8d5368a3-1835-43a2-9554-8c7a636f2244
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760552798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.1760552798
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.201264016
Short name T179
Test name
Test status
Simulation time 70833862 ps
CPU time 1 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 199632 kb
Host smart-337d119e-5f3c-429b-b473-924a1d8b2409
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201264016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.201264016
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.3003850448
Short name T195
Test name
Test status
Simulation time 107265455 ps
CPU time 0.97 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 209172 kb
Host smart-fc312fe1-e2b6-44af-8d01-7c1da19ce81c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003850448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3003850448
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.665496434
Short name T917
Test name
Test status
Simulation time 444988546 ps
CPU time 1.06 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 200480 kb
Host smart-14515a13-973d-417c-9396-59dc10d61387
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665496434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_c
m_ctrl_config_regwen.665496434
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1640182183
Short name T419
Test name
Test status
Simulation time 1441779256 ps
CPU time 2.25 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:08 PM PDT 24
Peak memory 200904 kb
Host smart-f3519f53-f9a7-4785-ae5f-1aaf8b10d3fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640182183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1640182183
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1554937129
Short name T543
Test name
Test status
Simulation time 865118410 ps
CPU time 3.19 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:08 PM PDT 24
Peak memory 200840 kb
Host smart-2560516e-1784-4578-a5e8-8fe504bcf817
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554937129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1554937129
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2291137753
Short name T607
Test name
Test status
Simulation time 136014713 ps
CPU time 0.83 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 199000 kb
Host smart-3bb581d1-79d7-400c-bfda-1d0cadedfa6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291137753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2291137753
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.976955423
Short name T357
Test name
Test status
Simulation time 36942052 ps
CPU time 0.72 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 199064 kb
Host smart-e2c678cb-289d-4762-b6fd-aa52bedbb474
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976955423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.976955423
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.2995520118
Short name T577
Test name
Test status
Simulation time 2566245115 ps
CPU time 3.88 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200904 kb
Host smart-6dd829d0-2d21-4202-8590-8ece481cf134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995520118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.2995520118
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.717312801
Short name T395
Test name
Test status
Simulation time 6595970597 ps
CPU time 20.63 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 200988 kb
Host smart-2bb4c6a4-5a4b-4cdf-bef7-7a8d8535393b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717312801 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.717312801
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.776972764
Short name T392
Test name
Test status
Simulation time 70006761 ps
CPU time 0.85 seconds
Started Jul 10 05:13:06 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 198144 kb
Host smart-d72c38c6-06fb-46e8-b59e-cf9236491f7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776972764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.776972764
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.3297930353
Short name T808
Test name
Test status
Simulation time 92908028 ps
CPU time 0.9 seconds
Started Jul 10 05:13:05 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 198920 kb
Host smart-ac9a456f-e344-4560-b68d-30905403914c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297930353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3297930353
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2091852084
Short name T391
Test name
Test status
Simulation time 43277209 ps
CPU time 0.74 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:12 PM PDT 24
Peak memory 198400 kb
Host smart-da1e2a7a-25d9-4ade-b1e5-dae0702df8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091852084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2091852084
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.2904902013
Short name T27
Test name
Test status
Simulation time 81755962 ps
CPU time 0.74 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 198872 kb
Host smart-b57b6d48-fae8-4b7b-bda1-663cfe9b143c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904902013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.2904902013
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.928870198
Short name T275
Test name
Test status
Simulation time 40895587 ps
CPU time 0.58 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:12 PM PDT 24
Peak memory 197640 kb
Host smart-1f1b492b-d532-4190-aa05-7061b2039e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928870198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_
malfunc.928870198
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.53556542
Short name T348
Test name
Test status
Simulation time 280928506 ps
CPU time 1 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 197832 kb
Host smart-da510e83-2227-43a3-8aff-db4adff6bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53556542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.53556542
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.3513088765
Short name T827
Test name
Test status
Simulation time 105150337 ps
CPU time 0.6 seconds
Started Jul 10 05:21:05 PM PDT 24
Finished Jul 10 05:21:07 PM PDT 24
Peak memory 197820 kb
Host smart-6fe96266-effe-4767-8c3d-48aa1bf230bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513088765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3513088765
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.3115712486
Short name T600
Test name
Test status
Simulation time 160418288 ps
CPU time 0.65 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 198028 kb
Host smart-68255e30-3069-4870-9216-36b7e82c3bc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115712486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.3115712486
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1535743449
Short name T375
Test name
Test status
Simulation time 64775844 ps
CPU time 0.69 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 201100 kb
Host smart-15e743da-55cf-49ce-997d-b00e877f8b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535743449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1535743449
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.3754706708
Short name T765
Test name
Test status
Simulation time 274373091 ps
CPU time 1.27 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 199476 kb
Host smart-74b4866d-d4f7-4a4b-8c87-f3a523d9fd3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754706708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.3754706708
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2379665360
Short name T366
Test name
Test status
Simulation time 161138500 ps
CPU time 0.88 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 199664 kb
Host smart-f72b9ea8-99bb-49fe-b7d4-fb83ec9ab50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379665360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2379665360
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1879137387
Short name T941
Test name
Test status
Simulation time 116200275 ps
CPU time 0.89 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 209120 kb
Host smart-772ae5e6-fc1e-4cbd-ba65-7a5b8174ffe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879137387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1879137387
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2720568022
Short name T985
Test name
Test status
Simulation time 270619787 ps
CPU time 0.95 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 199904 kb
Host smart-7137dab7-6a73-4dcb-9ebc-11ed47447100
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720568022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_
cm_ctrl_config_regwen.2720568022
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3919687355
Short name T260
Test name
Test status
Simulation time 1233452134 ps
CPU time 2.29 seconds
Started Jul 10 05:13:12 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 200816 kb
Host smart-f69dd1f0-fb5e-46fb-9c8a-5a3981ea3997
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919687355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3919687355
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2021409674
Short name T777
Test name
Test status
Simulation time 1038184324 ps
CPU time 2.21 seconds
Started Jul 10 05:13:10 PM PDT 24
Finished Jul 10 05:13:16 PM PDT 24
Peak memory 200908 kb
Host smart-42fcfb83-7a09-49b3-80de-d6a9e52531ae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021409674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2021409674
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3740538773
Short name T378
Test name
Test status
Simulation time 129517056 ps
CPU time 0.81 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 199268 kb
Host smart-3dcd3a28-5019-4e11-a697-4c6883ca8313
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740538773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3740538773
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1554329038
Short name T750
Test name
Test status
Simulation time 108470299 ps
CPU time 0.66 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 198216 kb
Host smart-de221b5d-9c28-4348-9212-e8884bd30481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554329038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1554329038
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.1777363731
Short name T117
Test name
Test status
Simulation time 1380272629 ps
CPU time 2.48 seconds
Started Jul 10 05:13:12 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 200720 kb
Host smart-888eb93c-d608-4020-a88a-f5cd5a106ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777363731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1777363731
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.4097360446
Short name T81
Test name
Test status
Simulation time 7449602761 ps
CPU time 28.33 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:39 PM PDT 24
Peak memory 201052 kb
Host smart-4461c50a-ef5e-45e2-99e1-aa12a118d5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097360446 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.4097360446
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.2871685580
Short name T382
Test name
Test status
Simulation time 287110667 ps
CPU time 1.35 seconds
Started Jul 10 05:13:04 PM PDT 24
Finished Jul 10 05:13:08 PM PDT 24
Peak memory 199412 kb
Host smart-07f11592-e3c9-430f-8639-3ccab547dec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871685580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.2871685580
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.1783375419
Short name T343
Test name
Test status
Simulation time 134351950 ps
CPU time 0.74 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 199060 kb
Host smart-a062c9d9-2572-4eda-aaf8-c8ae7463ebd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783375419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1783375419
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.223724525
Short name T615
Test name
Test status
Simulation time 45100698 ps
CPU time 0.91 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:11 PM PDT 24
Peak memory 200056 kb
Host smart-fd0ec4f6-73b6-41d9-ab8c-1fcdc9279294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223724525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.223724525
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.992785544
Short name T401
Test name
Test status
Simulation time 64755936 ps
CPU time 0.75 seconds
Started Jul 10 05:13:13 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 198816 kb
Host smart-ad5a93ef-f0de-4b31-9990-b3999702e1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992785544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.992785544
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.899728907
Short name T443
Test name
Test status
Simulation time 39525098 ps
CPU time 0.6 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 196948 kb
Host smart-04681703-9afe-4fe4-9858-bb78e9b72c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899728907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_
malfunc.899728907
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.1756356788
Short name T829
Test name
Test status
Simulation time 325835383 ps
CPU time 0.97 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 197820 kb
Host smart-c406fe55-4f7e-4002-bb70-d51941af29be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756356788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1756356788
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.394134658
Short name T704
Test name
Test status
Simulation time 55312232 ps
CPU time 0.69 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:12 PM PDT 24
Peak memory 197784 kb
Host smart-d790a67c-7e54-45cb-a31f-11f9b18ad6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394134658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.394134658
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.960586457
Short name T510
Test name
Test status
Simulation time 56993959 ps
CPU time 0.67 seconds
Started Jul 10 05:13:12 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 201120 kb
Host smart-84e48a23-deb2-42cb-b517-0108f1e36423
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960586457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.960586457
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.432354277
Short name T398
Test name
Test status
Simulation time 67817299 ps
CPU time 0.66 seconds
Started Jul 10 05:13:13 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 198780 kb
Host smart-9ef2c3a5-9aa2-4a35-a568-7ae4738189f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432354277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wa
keup_race.432354277
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.4013438759
Short name T637
Test name
Test status
Simulation time 152387941 ps
CPU time 0.87 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 198872 kb
Host smart-c408ad72-6baa-4ecb-95db-c5e4d47e10df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013438759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.4013438759
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.1129993476
Short name T369
Test name
Test status
Simulation time 117948272 ps
CPU time 0.86 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 209288 kb
Host smart-924d07f7-81c8-4ee1-ba8e-7ebf910deac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129993476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1129993476
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2723139665
Short name T454
Test name
Test status
Simulation time 56727459 ps
CPU time 0.75 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:11 PM PDT 24
Peak memory 198240 kb
Host smart-e17c3206-ebd6-4749-b4cf-7c35d82dd060
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723139665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2723139665
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2411279404
Short name T980
Test name
Test status
Simulation time 838008763 ps
CPU time 3.1 seconds
Started Jul 10 05:13:11 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 200924 kb
Host smart-804dfab8-b052-4034-8a71-f2fac67661c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411279404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2411279404
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2981950611
Short name T482
Test name
Test status
Simulation time 1451049246 ps
CPU time 2.13 seconds
Started Jul 10 05:13:13 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 200820 kb
Host smart-6f05485a-ae60-48ff-813e-6fa6961574e8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981950611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2981950611
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3439596114
Short name T854
Test name
Test status
Simulation time 82337491 ps
CPU time 0.82 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:11 PM PDT 24
Peak memory 198988 kb
Host smart-c493f561-da2d-466b-a6e5-1bf4a7f41545
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439596114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3439596114
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.923085880
Short name T225
Test name
Test status
Simulation time 33891568 ps
CPU time 0.67 seconds
Started Jul 10 05:13:10 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 199068 kb
Host smart-56ad990c-702a-4ed5-865c-eb906ec56ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923085880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.923085880
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.4095443659
Short name T118
Test name
Test status
Simulation time 501949882 ps
CPU time 1.98 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 200912 kb
Host smart-7a56117b-7ebf-4434-b127-d6ce61202b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095443659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.4095443659
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.2742081366
Short name T473
Test name
Test status
Simulation time 2050979528 ps
CPU time 4.91 seconds
Started Jul 10 05:13:10 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 201044 kb
Host smart-ff137103-a4c0-484a-88ce-7f963aac61f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742081366 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.2742081366
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.2422053731
Short name T489
Test name
Test status
Simulation time 148938320 ps
CPU time 0.84 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:11 PM PDT 24
Peak memory 198764 kb
Host smart-b576a9a7-82fd-41d5-94f7-3386512c1eb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422053731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2422053731
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.703242938
Short name T272
Test name
Test status
Simulation time 106893511 ps
CPU time 0.76 seconds
Started Jul 10 05:13:08 PM PDT 24
Finished Jul 10 05:13:11 PM PDT 24
Peak memory 198996 kb
Host smart-59ea5aea-2958-4b54-8e83-5f6bf82b9e7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703242938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.703242938
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1194266893
Short name T924
Test name
Test status
Simulation time 70481621 ps
CPU time 0.77 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 198528 kb
Host smart-ddd455c2-a172-4634-8ede-f76851501f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194266893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1194266893
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2604453428
Short name T224
Test name
Test status
Simulation time 37899585 ps
CPU time 0.63 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 197724 kb
Host smart-d8d3cc43-103e-4408-ad44-4475c5bfc902
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604453428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2604453428
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.22796292
Short name T418
Test name
Test status
Simulation time 166328432 ps
CPU time 0.99 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 197812 kb
Host smart-4998ac7f-03c2-4f69-8c96-0f56458a40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22796292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.22796292
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2551405443
Short name T710
Test name
Test status
Simulation time 57501274 ps
CPU time 0.62 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 197820 kb
Host smart-af9902fc-aa58-4167-b389-6c14bb3cb63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551405443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2551405443
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.1060741202
Short name T708
Test name
Test status
Simulation time 37829786 ps
CPU time 0.61 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 197320 kb
Host smart-cca366ef-3399-42af-b6da-b5b6801a8ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060741202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1060741202
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3422758918
Short name T690
Test name
Test status
Simulation time 44396167 ps
CPU time 0.69 seconds
Started Jul 10 05:13:17 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 201068 kb
Host smart-a139abf8-b887-4ef7-b6b2-fabc780891b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422758918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3422758918
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.2100271767
Short name T856
Test name
Test status
Simulation time 119763912 ps
CPU time 0.9 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 198092 kb
Host smart-ecc21fe7-534c-424e-a275-21baa9569eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100271767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.2100271767
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2285385118
Short name T832
Test name
Test status
Simulation time 137903553 ps
CPU time 0.73 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:13 PM PDT 24
Peak memory 198432 kb
Host smart-0215b637-2047-47a3-943f-64770533cf2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285385118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2285385118
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.3160629310
Short name T550
Test name
Test status
Simulation time 153869452 ps
CPU time 0.87 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 209284 kb
Host smart-60e630b1-b0c5-41c0-a612-e6f1b69514d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160629310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3160629310
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.497291119
Short name T282
Test name
Test status
Simulation time 145777038 ps
CPU time 1.01 seconds
Started Jul 10 05:13:18 PM PDT 24
Finished Jul 10 05:13:22 PM PDT 24
Peak memory 199692 kb
Host smart-c3b98ae6-7f63-4421-9d70-7ffa6f178aef
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497291119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_c
m_ctrl_config_regwen.497291119
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3499667402
Short name T381
Test name
Test status
Simulation time 2754288672 ps
CPU time 2.03 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 200888 kb
Host smart-f1efff76-c2f4-4f3d-8388-7ba32005b484
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499667402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3499667402
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3241557610
Short name T323
Test name
Test status
Simulation time 1388398066 ps
CPU time 2.22 seconds
Started Jul 10 05:13:18 PM PDT 24
Finished Jul 10 05:13:23 PM PDT 24
Peak memory 200792 kb
Host smart-fc783bdc-1673-4518-b6f4-e1d6705bf7b8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241557610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3241557610
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3981374135
Short name T364
Test name
Test status
Simulation time 69370867 ps
CPU time 0.93 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 199064 kb
Host smart-1afdc052-fa76-4437-be5c-755c2c3e8782
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981374135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3981374135
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2826709225
Short name T877
Test name
Test status
Simulation time 31714597 ps
CPU time 0.69 seconds
Started Jul 10 05:13:10 PM PDT 24
Finished Jul 10 05:13:14 PM PDT 24
Peak memory 198300 kb
Host smart-e9ec9bb3-771a-42d6-85ea-9f04e2967c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826709225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2826709225
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.2991020463
Short name T611
Test name
Test status
Simulation time 822048818 ps
CPU time 4.05 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 200928 kb
Host smart-ca9ce7a6-7992-43dd-93bd-a0a8cbab4d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991020463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2991020463
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3032591088
Short name T892
Test name
Test status
Simulation time 11048655376 ps
CPU time 9.22 seconds
Started Jul 10 05:13:18 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 201128 kb
Host smart-217bc4d5-75ac-454e-b22d-fe2559ab195b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032591088 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.3032591088
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.3496054583
Short name T894
Test name
Test status
Simulation time 83397144 ps
CPU time 0.65 seconds
Started Jul 10 05:13:12 PM PDT 24
Finished Jul 10 05:13:16 PM PDT 24
Peak memory 198792 kb
Host smart-97ea7906-2c2c-4d79-a976-15e627f558b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496054583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3496054583
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2577137926
Short name T474
Test name
Test status
Simulation time 65451933 ps
CPU time 0.77 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 199736 kb
Host smart-498bd678-16e3-4e10-a73f-1e39017b9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577137926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2577137926
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1824051328
Short name T255
Test name
Test status
Simulation time 62241162 ps
CPU time 0.81 seconds
Started Jul 10 05:13:18 PM PDT 24
Finished Jul 10 05:13:22 PM PDT 24
Peak memory 198752 kb
Host smart-3a701188-5f55-4369-abc4-6f2c68dbfcd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824051328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1824051328
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.47586039
Short name T234
Test name
Test status
Simulation time 39926651 ps
CPU time 0.57 seconds
Started Jul 10 05:13:17 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 197028 kb
Host smart-79906f08-0db3-4098-b635-f22c6c30b905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47586039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_m
alfunc.47586039
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.1004799810
Short name T555
Test name
Test status
Simulation time 343929244 ps
CPU time 0.9 seconds
Started Jul 10 05:13:13 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 197772 kb
Host smart-dab6a0da-a8db-43f2-8982-ec00d9aab547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004799810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1004799810
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.3435893165
Short name T992
Test name
Test status
Simulation time 75071617 ps
CPU time 0.69 seconds
Started Jul 10 05:13:17 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 197720 kb
Host smart-fff68647-3d00-4887-978e-d8a4cee7d6a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435893165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3435893165
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.2855886456
Short name T518
Test name
Test status
Simulation time 56779159 ps
CPU time 0.62 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 198104 kb
Host smart-c45a468f-c977-4814-af5e-61aaffa1e422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855886456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2855886456
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1630369290
Short name T426
Test name
Test status
Simulation time 70427583 ps
CPU time 0.67 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:24 PM PDT 24
Peak memory 201048 kb
Host smart-36105200-2d30-4ce2-bc1e-795a5e2618e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630369290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1630369290
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.2176744821
Short name T291
Test name
Test status
Simulation time 281145054 ps
CPU time 0.82 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 199268 kb
Host smart-e5bbd7d1-65c9-4d70-8d69-75bfa415ee54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176744821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.2176744821
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.4063437941
Short name T456
Test name
Test status
Simulation time 148233101 ps
CPU time 0.8 seconds
Started Jul 10 05:13:17 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 198864 kb
Host smart-c891395e-cd07-49a5-93ab-376ecf1c93fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063437941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.4063437941
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3288023839
Short name T774
Test name
Test status
Simulation time 100944026 ps
CPU time 0.96 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:39 PM PDT 24
Peak memory 209048 kb
Host smart-277535de-4ee3-4caf-afd9-c8a5aaafa90a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288023839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3288023839
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.1691831084
Short name T53
Test name
Test status
Simulation time 114835925 ps
CPU time 0.98 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:18 PM PDT 24
Peak memory 198432 kb
Host smart-955282ec-b111-4efc-a4c7-8a96310ed787
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691831084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.1691831084
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.952275718
Short name T155
Test name
Test status
Simulation time 816755377 ps
CPU time 2.75 seconds
Started Jul 10 05:13:14 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 200828 kb
Host smart-334b8dad-7fe9-4ac0-b332-7df3314995c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952275718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.952275718
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1308025212
Short name T334
Test name
Test status
Simulation time 2278067092 ps
CPU time 2.15 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 200928 kb
Host smart-33b0305a-e160-4295-b548-a16bbeee7829
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308025212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1308025212
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.847561924
Short name T794
Test name
Test status
Simulation time 99006528 ps
CPU time 0.93 seconds
Started Jul 10 05:13:17 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 199092 kb
Host smart-5e788f11-dceb-4b16-809f-a25a285562a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847561924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.847561924
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.3043467403
Short name T448
Test name
Test status
Simulation time 54369283 ps
CPU time 0.62 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 198208 kb
Host smart-c57978fc-0dbe-4178-8429-873a6299d862
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043467403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3043467403
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.1949123134
Short name T367
Test name
Test status
Simulation time 864637370 ps
CPU time 3.75 seconds
Started Jul 10 05:13:23 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 200920 kb
Host smart-2b2a0b69-9690-48d4-88e6-2a10f0da0627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949123134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.1949123134
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1791327631
Short name T347
Test name
Test status
Simulation time 7861007461 ps
CPU time 30.3 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 201056 kb
Host smart-a3beb28a-6c9e-4e87-ad68-b33a6e27b77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791327631 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.1791327631
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.1405848674
Short name T35
Test name
Test status
Simulation time 82400689 ps
CPU time 0.78 seconds
Started Jul 10 05:13:16 PM PDT 24
Finished Jul 10 05:13:20 PM PDT 24
Peak memory 197560 kb
Host smart-a35ed2a6-967f-405b-95a2-cbbae12d0447
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405848674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.1405848674
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.2503778588
Short name T344
Test name
Test status
Simulation time 73693523 ps
CPU time 0.76 seconds
Started Jul 10 05:13:15 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 198916 kb
Host smart-bfc256b8-dcb2-4f60-aa25-cd47bad620b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503778588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2503778588
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3513458817
Short name T739
Test name
Test status
Simulation time 48481510 ps
CPU time 0.63 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:23 PM PDT 24
Peak memory 198208 kb
Host smart-40322e37-3481-4bd9-bb31-53f505299a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513458817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3513458817
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.608734519
Short name T631
Test name
Test status
Simulation time 71357516 ps
CPU time 0.78 seconds
Started Jul 10 05:13:24 PM PDT 24
Finished Jul 10 05:13:26 PM PDT 24
Peak memory 198868 kb
Host smart-650480b9-bf90-4632-a3fc-8c7d33b2b9cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608734519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa
ble_rom_integrity_check.608734519
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1814338495
Short name T608
Test name
Test status
Simulation time 31861769 ps
CPU time 0.61 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 196948 kb
Host smart-f519cbba-550e-4bab-b142-181912ec99de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814338495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.1814338495
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.1699298032
Short name T422
Test name
Test status
Simulation time 316433439 ps
CPU time 0.97 seconds
Started Jul 10 05:13:24 PM PDT 24
Finished Jul 10 05:13:27 PM PDT 24
Peak memory 197496 kb
Host smart-8a90b153-c64f-4657-ba03-1848823ac14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699298032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1699298032
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.1881021369
Short name T516
Test name
Test status
Simulation time 54714079 ps
CPU time 0.58 seconds
Started Jul 10 05:13:24 PM PDT 24
Finished Jul 10 05:13:26 PM PDT 24
Peak memory 197440 kb
Host smart-6cd8a7e1-e91e-40b9-acdd-a59a05c5faf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881021369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.1881021369
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.2657721670
Short name T408
Test name
Test status
Simulation time 39352147 ps
CPU time 0.61 seconds
Started Jul 10 05:13:23 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 198096 kb
Host smart-e23727c9-aab9-423c-9c54-568825a26dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657721670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.2657721670
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2737265746
Short name T341
Test name
Test status
Simulation time 40467603 ps
CPU time 0.73 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:23 PM PDT 24
Peak memory 201072 kb
Host smart-7628202e-c922-47e4-ab85-c1b620b7549f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737265746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2737265746
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.3555825130
Short name T928
Test name
Test status
Simulation time 145491989 ps
CPU time 0.88 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:24 PM PDT 24
Peak memory 198208 kb
Host smart-542628b2-dea7-4801-84f2-6711899c8b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555825130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.3555825130
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3826703596
Short name T483
Test name
Test status
Simulation time 40617790 ps
CPU time 0.79 seconds
Started Jul 10 05:13:23 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 198780 kb
Host smart-7b04c20e-7594-4f21-974f-59969fa8dc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826703596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3826703596
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1815039379
Short name T499
Test name
Test status
Simulation time 102283926 ps
CPU time 0.95 seconds
Started Jul 10 05:13:23 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 209168 kb
Host smart-71a47b94-9fd4-46bd-a9b8-3f89d79fb2c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815039379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1815039379
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.3005028427
Short name T938
Test name
Test status
Simulation time 266445340 ps
CPU time 1.15 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:23 PM PDT 24
Peak memory 200540 kb
Host smart-22cbd928-4605-4f50-a60f-226d3309deef
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005028427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.3005028427
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2873515301
Short name T702
Test name
Test status
Simulation time 845398351 ps
CPU time 3.49 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:26 PM PDT 24
Peak memory 200808 kb
Host smart-37b85697-dea0-4d75-a276-9aec37a498d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873515301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2873515301
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2235419457
Short name T640
Test name
Test status
Simulation time 1064028562 ps
CPU time 1.99 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 200740 kb
Host smart-6043cd38-3e54-491d-bd94-f51187bc9d43
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235419457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2235419457
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.864975823
Short name T7
Test name
Test status
Simulation time 51002067 ps
CPU time 0.88 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 199108 kb
Host smart-8e839086-b6c3-4d30-ab57-2c3480dd2393
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864975823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.864975823
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3910008041
Short name T766
Test name
Test status
Simulation time 28862492 ps
CPU time 0.7 seconds
Started Jul 10 05:13:24 PM PDT 24
Finished Jul 10 05:13:26 PM PDT 24
Peak memory 199068 kb
Host smart-183490d1-bc1e-4ec2-9fe4-2f709c5ca707
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910008041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3910008041
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.696568069
Short name T746
Test name
Test status
Simulation time 967972681 ps
CPU time 2.36 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 200892 kb
Host smart-b89cbe5e-f194-478d-8733-f032fb9a3ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696568069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.696568069
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2765205238
Short name T84
Test name
Test status
Simulation time 6260881459 ps
CPU time 10.2 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:33 PM PDT 24
Peak memory 201084 kb
Host smart-912016a2-e003-4e44-929d-7ff8cca5b656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765205238 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.2765205238
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.4098492803
Short name T273
Test name
Test status
Simulation time 158450950 ps
CPU time 0.78 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:24 PM PDT 24
Peak memory 197992 kb
Host smart-9a0d642b-dafc-499d-8452-8992f4a671c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098492803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.4098492803
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.3703576611
Short name T206
Test name
Test status
Simulation time 284288334 ps
CPU time 1.19 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 200624 kb
Host smart-f9363993-f34d-4310-9afa-8f8d2417778b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703576611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3703576611
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.3622056094
Short name T342
Test name
Test status
Simulation time 32161317 ps
CPU time 0.93 seconds
Started Jul 10 05:13:21 PM PDT 24
Finished Jul 10 05:13:24 PM PDT 24
Peak memory 199708 kb
Host smart-475fd45c-9bac-4fcb-a761-dcc52d68ca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622056094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3622056094
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.1024184137
Short name T269
Test name
Test status
Simulation time 69435958 ps
CPU time 0.85 seconds
Started Jul 10 05:13:27 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 198732 kb
Host smart-0b145933-2a40-4f7d-a56a-0b495702faeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024184137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.1024184137
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4172110396
Short name T149
Test name
Test status
Simulation time 56558886 ps
CPU time 0.61 seconds
Started Jul 10 05:13:28 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 197716 kb
Host smart-e179dc86-8e69-424b-8940-3a6cca18c6fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172110396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.4172110396
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.751350055
Short name T565
Test name
Test status
Simulation time 320719841 ps
CPU time 1 seconds
Started Jul 10 05:13:28 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 197836 kb
Host smart-468f9811-d64e-4dc1-b11c-b47798c9b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751350055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.751350055
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.1949686279
Short name T991
Test name
Test status
Simulation time 32785980 ps
CPU time 0.65 seconds
Started Jul 10 05:13:31 PM PDT 24
Finished Jul 10 05:13:32 PM PDT 24
Peak memory 197048 kb
Host smart-a7f52e16-73a8-499e-8053-8bb0580da7c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949686279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1949686279
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.1299785900
Short name T444
Test name
Test status
Simulation time 60436006 ps
CPU time 0.65 seconds
Started Jul 10 05:13:28 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 197780 kb
Host smart-a69bf077-aa18-4898-8947-de0fdcaee0b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299785900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.1299785900
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1851350381
Short name T383
Test name
Test status
Simulation time 76223122 ps
CPU time 0.69 seconds
Started Jul 10 05:13:27 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 201076 kb
Host smart-0ff553c8-68c3-44e0-8815-900206db101b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851350381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1851350381
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.2364214964
Short name T320
Test name
Test status
Simulation time 144683651 ps
CPU time 0.87 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 198880 kb
Host smart-e88aadcf-0162-4376-9a40-f3b80227ef4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364214964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.2364214964
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3843023568
Short name T500
Test name
Test status
Simulation time 21563436 ps
CPU time 0.65 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:39 PM PDT 24
Peak memory 197896 kb
Host smart-c337a910-2814-47b7-b0dd-0aa7ca9e801d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843023568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3843023568
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2210549522
Short name T457
Test name
Test status
Simulation time 118751706 ps
CPU time 0.84 seconds
Started Jul 10 05:13:27 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 209476 kb
Host smart-0695a12e-d5f7-454f-83ab-ae16a2e4d36e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210549522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2210549522
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1539299675
Short name T638
Test name
Test status
Simulation time 277468922 ps
CPU time 1.22 seconds
Started Jul 10 05:13:29 PM PDT 24
Finished Jul 10 05:13:32 PM PDT 24
Peak memory 199552 kb
Host smart-48e84ca3-c1df-4458-b16c-0f728b424c8c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539299675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.1539299675
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1501702209
Short name T664
Test name
Test status
Simulation time 1236254273 ps
CPU time 2.29 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:27 PM PDT 24
Peak memory 200764 kb
Host smart-d83fc8b1-a9d5-494d-9b79-da8945ab20c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501702209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1501702209
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2937734092
Short name T325
Test name
Test status
Simulation time 1371705550 ps
CPU time 2.5 seconds
Started Jul 10 05:13:20 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 200752 kb
Host smart-32d586c9-5ae3-4873-94ed-a4a261fc76a9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937734092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2937734092
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1021573088
Short name T463
Test name
Test status
Simulation time 145113698 ps
CPU time 0.85 seconds
Started Jul 10 05:13:26 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 199120 kb
Host smart-59c8a1fa-1ba2-4436-98cf-93abe3b7810e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021573088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1021573088
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2477453620
Short name T373
Test name
Test status
Simulation time 127164137 ps
CPU time 0.62 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:39 PM PDT 24
Peak memory 198144 kb
Host smart-502f7ba5-9ebe-4c3d-b0d2-820027051adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477453620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2477453620
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.2573213145
Short name T840
Test name
Test status
Simulation time 2626877937 ps
CPU time 4 seconds
Started Jul 10 05:13:26 PM PDT 24
Finished Jul 10 05:13:31 PM PDT 24
Peak memory 200912 kb
Host smart-6637ad14-8a03-467d-8079-e7f04edd9d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573213145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.2573213145
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.2491607678
Short name T667
Test name
Test status
Simulation time 9378063112 ps
CPU time 35.28 seconds
Started Jul 10 05:13:31 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 201320 kb
Host smart-c020d446-87ee-46f3-a4c8-be9212cff637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491607678 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.2491607678
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.4210889368
Short name T520
Test name
Test status
Simulation time 256902436 ps
CPU time 0.95 seconds
Started Jul 10 05:13:24 PM PDT 24
Finished Jul 10 05:13:27 PM PDT 24
Peak memory 199336 kb
Host smart-a9e6d7dd-f407-4234-b7e9-26c9a1877644
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210889368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.4210889368
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.3762659559
Short name T202
Test name
Test status
Simulation time 135008350 ps
CPU time 0.97 seconds
Started Jul 10 05:13:22 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 199064 kb
Host smart-9ac442b1-55c4-4d4b-ae43-d200b0274aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762659559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3762659559
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2073564506
Short name T742
Test name
Test status
Simulation time 121336703 ps
CPU time 0.72 seconds
Started Jul 10 05:13:28 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 198392 kb
Host smart-a49958de-0b77-4499-ab01-f8bb61937865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073564506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2073564506
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.2622431004
Short name T22
Test name
Test status
Simulation time 61246597 ps
CPU time 0.8 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:38 PM PDT 24
Peak memory 198816 kb
Host smart-8f4dfdaf-eb8c-4c6d-bb1d-d6458dfd7577
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622431004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.2622431004
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.741693126
Short name T393
Test name
Test status
Simulation time 39209833 ps
CPU time 0.61 seconds
Started Jul 10 05:13:32 PM PDT 24
Finished Jul 10 05:13:34 PM PDT 24
Peak memory 197752 kb
Host smart-b090bd98-0642-4ce2-a2c8-063fcfcc4234
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741693126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.741693126
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.4226138124
Short name T264
Test name
Test status
Simulation time 310084933 ps
CPU time 0.95 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:36 PM PDT 24
Peak memory 198120 kb
Host smart-50774f0a-9e2d-4084-9102-f314adb18eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226138124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.4226138124
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3628232162
Short name T416
Test name
Test status
Simulation time 64788402 ps
CPU time 0.71 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 197768 kb
Host smart-6d34c713-effd-4f4e-a57f-95dc602004a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628232162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3628232162
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3332944765
Short name T916
Test name
Test status
Simulation time 91541963 ps
CPU time 0.64 seconds
Started Jul 10 05:13:34 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 198008 kb
Host smart-f43a7fac-c8a2-4ce7-94e1-41ec104d74a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332944765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3332944765
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3155442485
Short name T639
Test name
Test status
Simulation time 42760703 ps
CPU time 0.7 seconds
Started Jul 10 05:13:31 PM PDT 24
Finished Jul 10 05:13:33 PM PDT 24
Peak memory 201076 kb
Host smart-8f8415bb-49a4-47e8-8d0e-018f9e322a5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155442485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3155442485
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.3892306981
Short name T677
Test name
Test status
Simulation time 341968896 ps
CPU time 1.17 seconds
Started Jul 10 05:13:26 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 199380 kb
Host smart-5cb8b5fe-9756-4eac-b2cd-9f0faac9c03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892306981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.3892306981
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2779436114
Short name T360
Test name
Test status
Simulation time 104753912 ps
CPU time 1.02 seconds
Started Jul 10 05:13:27 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 199380 kb
Host smart-e407d170-5545-4451-9dbe-a09b7e6b47b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779436114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2779436114
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3588227845
Short name T665
Test name
Test status
Simulation time 73480871 ps
CPU time 0.7 seconds
Started Jul 10 05:13:34 PM PDT 24
Finished Jul 10 05:13:36 PM PDT 24
Peak memory 199380 kb
Host smart-92bcb8ec-e5cb-427c-886b-b1bc5fd8adfc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588227845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.3588227845
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1071806479
Short name T154
Test name
Test status
Simulation time 990359519 ps
CPU time 2.08 seconds
Started Jul 10 05:13:29 PM PDT 24
Finished Jul 10 05:13:32 PM PDT 24
Peak memory 200772 kb
Host smart-ddb26fdf-dffc-4e6d-a956-fe04e2046d05
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071806479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1071806479
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1425573187
Short name T505
Test name
Test status
Simulation time 1093033714 ps
CPU time 2.78 seconds
Started Jul 10 05:13:31 PM PDT 24
Finished Jul 10 05:13:34 PM PDT 24
Peak memory 200684 kb
Host smart-5d544a6b-b8a2-4151-a3a4-2d55d98904d1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425573187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1425573187
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2692365287
Short name T9
Test name
Test status
Simulation time 110242240 ps
CPU time 0.79 seconds
Started Jul 10 05:13:25 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 198928 kb
Host smart-d858d2a0-194f-44bd-b02d-60eb363012e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692365287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2692365287
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.801191888
Short name T913
Test name
Test status
Simulation time 61575582 ps
CPU time 0.62 seconds
Started Jul 10 05:13:27 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 199100 kb
Host smart-f5679372-720e-449b-87ad-e11de44fdfe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801191888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.801191888
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.479434814
Short name T93
Test name
Test status
Simulation time 913706367 ps
CPU time 2.87 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 200816 kb
Host smart-40055d3b-6071-441f-886b-14f3fd8a716c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479434814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.479434814
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.4102526621
Short name T975
Test name
Test status
Simulation time 180350805 ps
CPU time 1.02 seconds
Started Jul 10 05:13:28 PM PDT 24
Finished Jul 10 05:13:30 PM PDT 24
Peak memory 199372 kb
Host smart-9c8303b8-6b4b-4bd2-9e26-6e5c68e2373b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102526621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.4102526621
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.1242350453
Short name T906
Test name
Test status
Simulation time 94842134 ps
CPU time 0.79 seconds
Started Jul 10 05:13:26 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 199028 kb
Host smart-8a1f5875-36e3-4482-9f0a-8a051eb4ded5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242350453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.1242350453
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3557710309
Short name T719
Test name
Test status
Simulation time 163353062 ps
CPU time 0.74 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:43 PM PDT 24
Peak memory 198324 kb
Host smart-d8f02585-baef-4f6d-92c0-95ec8f9b1f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557710309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3557710309
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2201600839
Short name T170
Test name
Test status
Simulation time 51708410 ps
CPU time 0.81 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:38 PM PDT 24
Peak memory 198836 kb
Host smart-0be2cb01-ee84-44d8-907d-1c3ef7c48ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201600839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2201600839
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1410781611
Short name T15
Test name
Test status
Simulation time 38219324 ps
CPU time 0.59 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 197632 kb
Host smart-700c46e1-5af6-4945-8c8b-be1252d42759
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410781611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1410781611
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.4181068822
Short name T910
Test name
Test status
Simulation time 156838311 ps
CPU time 0.99 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:36 PM PDT 24
Peak memory 197824 kb
Host smart-09db6ab2-3b67-4976-8be7-cb9e3f0dc830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181068822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4181068822
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2261141414
Short name T535
Test name
Test status
Simulation time 35367231 ps
CPU time 0.67 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 197740 kb
Host smart-b6922fb5-7e22-423f-a53f-76fe59931870
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261141414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2261141414
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.2317088535
Short name T658
Test name
Test status
Simulation time 39947793 ps
CPU time 0.62 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:38 PM PDT 24
Peak memory 198088 kb
Host smart-31fb5b86-0e6e-4236-8abf-5aee30885784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317088535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.2317088535
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.3389261166
Short name T173
Test name
Test status
Simulation time 74075114 ps
CPU time 0.66 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 200928 kb
Host smart-341fbbad-e9a8-41f2-a497-9dc03633fe7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389261166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.3389261166
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.1032370242
Short name T247
Test name
Test status
Simulation time 303025303 ps
CPU time 1 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 199240 kb
Host smart-d15ed44f-f05c-4d15-bac5-f4d9890c719a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032370242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.1032370242
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.2145690919
Short name T123
Test name
Test status
Simulation time 123913320 ps
CPU time 0.89 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:38 PM PDT 24
Peak memory 199504 kb
Host smart-3925e0dd-0bda-40da-b332-ed3681d584a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145690919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2145690919
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.4005913465
Short name T814
Test name
Test status
Simulation time 170553144 ps
CPU time 0.84 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:42 PM PDT 24
Peak memory 209184 kb
Host smart-f3a4b0a6-92e7-4317-a7af-06e4e9521449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005913465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.4005913465
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3304083603
Short name T579
Test name
Test status
Simulation time 75468828 ps
CPU time 0.87 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 199720 kb
Host smart-47774498-21c5-4a90-a30b-2d57e87acba0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304083603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.3304083603
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.324979018
Short name T227
Test name
Test status
Simulation time 770178447 ps
CPU time 3.13 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:41 PM PDT 24
Peak memory 200816 kb
Host smart-35c1feeb-34e3-401d-abcb-64a25597d73a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324979018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.324979018
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3077958965
Short name T125
Test name
Test status
Simulation time 1382116169 ps
CPU time 2.18 seconds
Started Jul 10 05:13:34 PM PDT 24
Finished Jul 10 05:13:38 PM PDT 24
Peak memory 200912 kb
Host smart-e76f8c89-729e-4adf-af84-656204ceeac2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077958965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3077958965
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1629474790
Short name T311
Test name
Test status
Simulation time 80122395 ps
CPU time 0.95 seconds
Started Jul 10 05:13:35 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 198968 kb
Host smart-6d11a10a-cdcf-4c3b-b571-e0c97b53dec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629474790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1629474790
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.345131083
Short name T940
Test name
Test status
Simulation time 54756097 ps
CPU time 0.63 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:39 PM PDT 24
Peak memory 198932 kb
Host smart-fd4e78f3-7f24-4331-9722-bc821be09b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345131083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.345131083
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.276947532
Short name T223
Test name
Test status
Simulation time 1035624028 ps
CPU time 3.57 seconds
Started Jul 10 05:13:36 PM PDT 24
Finished Jul 10 05:13:41 PM PDT 24
Peak memory 200888 kb
Host smart-9ff9b7c3-34c0-46d2-a112-184e4dc5766f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276947532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.276947532
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.343069632
Short name T479
Test name
Test status
Simulation time 12733723641 ps
CPU time 16.91 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 201096 kb
Host smart-3f872c90-601d-4108-875c-242f8c736167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343069632 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.343069632
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.2541049549
Short name T958
Test name
Test status
Simulation time 485955796 ps
CPU time 0.84 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:43 PM PDT 24
Peak memory 199096 kb
Host smart-b9f9f663-8ac0-44f3-84d3-a943ff9ee181
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541049549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.2541049549
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.2593783102
Short name T72
Test name
Test status
Simulation time 282439750 ps
CPU time 1.44 seconds
Started Jul 10 05:13:37 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 200628 kb
Host smart-dab8c7b8-8353-4b98-9642-0f9db8393faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593783102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2593783102
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.2954204940
Short name T532
Test name
Test status
Simulation time 47457377 ps
CPU time 0.73 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 198552 kb
Host smart-65f8251d-6d41-4b50-a316-43f77d94532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954204940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.2954204940
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3741224034
Short name T923
Test name
Test status
Simulation time 93837699 ps
CPU time 0.68 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:43 PM PDT 24
Peak memory 198348 kb
Host smart-0baf44e7-fab7-4a07-941f-47cb18c01860
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741224034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.3741224034
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3850922221
Short name T788
Test name
Test status
Simulation time 48675984 ps
CPU time 0.62 seconds
Started Jul 10 05:13:32 PM PDT 24
Finished Jul 10 05:13:33 PM PDT 24
Peak memory 197004 kb
Host smart-8fc0ccc5-2735-4bd6-a026-08a23b1d7f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850922221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.3850922221
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.1900672807
Short name T306
Test name
Test status
Simulation time 456463510 ps
CPU time 0.98 seconds
Started Jul 10 05:13:38 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 198032 kb
Host smart-727345a4-290d-4731-97df-fae9f16c8efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900672807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1900672807
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.4196481015
Short name T846
Test name
Test status
Simulation time 60867876 ps
CPU time 0.69 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:48 PM PDT 24
Peak memory 197008 kb
Host smart-ebbaecd2-3c9e-414e-a0f8-02bca5e805ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196481015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.4196481015
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.3369689418
Short name T328
Test name
Test status
Simulation time 148323212 ps
CPU time 0.58 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 197704 kb
Host smart-3707919b-a4a1-4f5c-8e1d-a5f7ec7e75cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369689418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.3369689418
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2988737967
Short name T944
Test name
Test status
Simulation time 57798309 ps
CPU time 0.67 seconds
Started Jul 10 05:13:48 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 200980 kb
Host smart-3ebba451-eb00-4480-8aa8-7b6c5429466c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988737967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2988737967
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2546331666
Short name T679
Test name
Test status
Simulation time 46699924 ps
CPU time 0.69 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 197996 kb
Host smart-ad1ec559-61ca-4b6e-a35f-a3e86813fd75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546331666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.2546331666
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2539485772
Short name T782
Test name
Test status
Simulation time 60874189 ps
CPU time 0.98 seconds
Started Jul 10 05:13:31 PM PDT 24
Finished Jul 10 05:13:33 PM PDT 24
Peak memory 199680 kb
Host smart-4a655d66-102e-4370-b8f7-974555102858
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539485772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2539485772
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3742981690
Short name T697
Test name
Test status
Simulation time 108612874 ps
CPU time 0.96 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 209224 kb
Host smart-8ba984b7-a7c5-4fef-a027-9b45455c7a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742981690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3742981690
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1010290068
Short name T857
Test name
Test status
Simulation time 60064167 ps
CPU time 0.71 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 199160 kb
Host smart-958be7ed-8dd1-4b0d-9b52-7efb1efbbb31
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010290068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.1010290068
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.411873537
Short name T948
Test name
Test status
Simulation time 1235090189 ps
CPU time 2.15 seconds
Started Jul 10 05:13:32 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 200804 kb
Host smart-7bb6ca07-0654-42a8-b362-5df400220e61
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411873537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.411873537
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3627659856
Short name T836
Test name
Test status
Simulation time 1256922746 ps
CPU time 2.26 seconds
Started Jul 10 05:13:33 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 200764 kb
Host smart-9588fda6-0bdd-4636-b530-d6fc8b04254d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627659856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3627659856
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3476904877
Short name T250
Test name
Test status
Simulation time 62979627 ps
CPU time 0.81 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198696 kb
Host smart-acd1a4f3-61eb-4b6d-8232-cc9d514f2bdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476904877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3476904877
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1029317195
Short name T769
Test name
Test status
Simulation time 32718546 ps
CPU time 0.7 seconds
Started Jul 10 05:13:38 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 198264 kb
Host smart-e3b9f01b-7880-454e-9708-8693ed133de9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029317195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1029317195
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.1291040951
Short name T30
Test name
Test status
Simulation time 2191858085 ps
CPU time 3.49 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:47 PM PDT 24
Peak memory 200984 kb
Host smart-21c8c231-0f83-49fb-9f1c-725028b03fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291040951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.1291040951
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.2251197291
Short name T632
Test name
Test status
Simulation time 127155761 ps
CPU time 0.76 seconds
Started Jul 10 05:13:32 PM PDT 24
Finished Jul 10 05:13:34 PM PDT 24
Peak memory 198844 kb
Host smart-dfa56691-b999-4a39-b893-6531fd5b790f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251197291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.2251197291
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.411349411
Short name T886
Test name
Test status
Simulation time 522969877 ps
CPU time 0.97 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 199964 kb
Host smart-24f62b43-9bdd-48f5-a960-c55ec02ac9b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411349411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.411349411
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.1013993870
Short name T436
Test name
Test status
Simulation time 33612163 ps
CPU time 1 seconds
Started Jul 10 05:12:24 PM PDT 24
Finished Jul 10 05:12:27 PM PDT 24
Peak memory 200612 kb
Host smart-1c8bb6b9-dba8-4c1e-b74d-ba96a5f6615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013993870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1013993870
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3665650921
Short name T881
Test name
Test status
Simulation time 92435600 ps
CPU time 0.75 seconds
Started Jul 10 05:12:25 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 198876 kb
Host smart-f0468952-ee03-4844-9e05-1617ab9c42f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665650921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3665650921
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1278900192
Short name T844
Test name
Test status
Simulation time 28381171 ps
CPU time 0.62 seconds
Started Jul 10 05:12:23 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 197620 kb
Host smart-3ea4e08f-c779-441d-aab3-3f944ea04ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278900192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1278900192
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2735151633
Short name T847
Test name
Test status
Simulation time 166430407 ps
CPU time 0.93 seconds
Started Jul 10 05:12:23 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 197800 kb
Host smart-4a5708d3-5d0e-4ec6-888f-d568f273e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735151633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2735151633
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3696827132
Short name T711
Test name
Test status
Simulation time 36475206 ps
CPU time 0.65 seconds
Started Jul 10 05:12:23 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 197724 kb
Host smart-31be68b1-cedd-4762-9fbc-52840f5a038f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696827132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3696827132
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1591731175
Short name T537
Test name
Test status
Simulation time 90016760 ps
CPU time 0.67 seconds
Started Jul 10 05:12:24 PM PDT 24
Finished Jul 10 05:12:27 PM PDT 24
Peak memory 197776 kb
Host smart-1de0df31-03e1-4b88-a74e-af1b7e68d5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591731175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1591731175
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2196748876
Short name T863
Test name
Test status
Simulation time 84825113 ps
CPU time 0.68 seconds
Started Jul 10 05:12:22 PM PDT 24
Finished Jul 10 05:12:24 PM PDT 24
Peak memory 201076 kb
Host smart-2b770f69-962e-44c8-803e-da09fc87467d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196748876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2196748876
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.3876347470
Short name T595
Test name
Test status
Simulation time 273645745 ps
CPU time 1.23 seconds
Started Jul 10 05:12:22 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 199176 kb
Host smart-5625cdac-91c7-42a4-a7fe-a2a07f77eb0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876347470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.3876347470
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1510716488
Short name T13
Test name
Test status
Simulation time 141250941 ps
CPU time 0.91 seconds
Started Jul 10 05:12:23 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 199652 kb
Host smart-f7661275-1390-4312-a237-673d93b6201c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510716488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1510716488
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.2871098165
Short name T459
Test name
Test status
Simulation time 102444619 ps
CPU time 0.96 seconds
Started Jul 10 05:12:22 PM PDT 24
Finished Jul 10 05:12:24 PM PDT 24
Peak memory 209312 kb
Host smart-fe308e69-f034-487d-b794-4200fb450d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871098165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2871098165
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.977431365
Short name T6
Test name
Test status
Simulation time 699922716 ps
CPU time 2.13 seconds
Started Jul 10 05:12:22 PM PDT 24
Finished Jul 10 05:12:26 PM PDT 24
Peak memory 217204 kb
Host smart-abbbb8b9-cacd-4888-9600-43d48c35bfd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977431365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.977431365
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3303757428
Short name T693
Test name
Test status
Simulation time 332718561 ps
CPU time 0.92 seconds
Started Jul 10 05:12:25 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 199624 kb
Host smart-36a34e2e-40c4-44de-a064-d594aa73623b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303757428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.3303757428
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.284178928
Short name T979
Test name
Test status
Simulation time 896258980 ps
CPU time 2.67 seconds
Started Jul 10 05:12:25 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 200868 kb
Host smart-442d4675-e988-483e-a7f7-04e94cc8d8b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284178928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.284178928
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1256254061
Short name T629
Test name
Test status
Simulation time 1098081495 ps
CPU time 1.98 seconds
Started Jul 10 05:12:26 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 200764 kb
Host smart-534579dc-b815-4ce1-898d-ff6f37f7bf01
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256254061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1256254061
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2951045768
Short name T338
Test name
Test status
Simulation time 53447652 ps
CPU time 0.9 seconds
Started Jul 10 05:12:27 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 199272 kb
Host smart-d2f0a86d-4f54-4cbf-b175-aa092446ad55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951045768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2951045768
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.2133939303
Short name T207
Test name
Test status
Simulation time 36287390 ps
CPU time 0.65 seconds
Started Jul 10 05:12:16 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 199000 kb
Host smart-c1a7d3fd-2faa-4121-98de-0382e5cc6eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133939303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2133939303
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.1624635109
Short name T625
Test name
Test status
Simulation time 1240090075 ps
CPU time 3.66 seconds
Started Jul 10 05:12:21 PM PDT 24
Finished Jul 10 05:12:26 PM PDT 24
Peak memory 200876 kb
Host smart-cd58c364-48ce-4f13-ac7e-613c7729b19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624635109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.1624635109
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.513711632
Short name T780
Test name
Test status
Simulation time 5743910280 ps
CPU time 20.43 seconds
Started Jul 10 05:12:21 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 201052 kb
Host smart-035a4e04-e011-486e-8556-b80b9ec04d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513711632 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.513711632
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.1463701360
Short name T287
Test name
Test status
Simulation time 154478364 ps
CPU time 0.84 seconds
Started Jul 10 05:12:21 PM PDT 24
Finished Jul 10 05:12:23 PM PDT 24
Peak memory 198856 kb
Host smart-38f5247a-e766-4414-9ab9-c02750c01408
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463701360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1463701360
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1379571637
Short name T818
Test name
Test status
Simulation time 305513983 ps
CPU time 1.45 seconds
Started Jul 10 05:12:24 PM PDT 24
Finished Jul 10 05:12:27 PM PDT 24
Peak memory 200892 kb
Host smart-6e19b9e5-1a7e-4dc8-bd20-983d1599f350
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379571637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1379571637
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1093682102
Short name T811
Test name
Test status
Simulation time 27879939 ps
CPU time 0.94 seconds
Started Jul 10 05:13:41 PM PDT 24
Finished Jul 10 05:13:45 PM PDT 24
Peak memory 200508 kb
Host smart-b58fcef6-1212-4b17-b1d6-eb3395409ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093682102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1093682102
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.910598100
Short name T152
Test name
Test status
Simulation time 61308687 ps
CPU time 0.85 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 198816 kb
Host smart-9669fa51-dfbc-43be-8be4-ab6e8803289e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910598100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.910598100
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2692540087
Short name T803
Test name
Test status
Simulation time 38498025 ps
CPU time 0.59 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 197016 kb
Host smart-823f8c90-4577-4980-ac94-eb9cacc3132e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692540087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2692540087
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2595978098
Short name T283
Test name
Test status
Simulation time 623621895 ps
CPU time 1.01 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:43 PM PDT 24
Peak memory 198120 kb
Host smart-09a733e0-bf15-47fa-9e80-38bafa56cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595978098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2595978098
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.3061171965
Short name T305
Test name
Test status
Simulation time 74247369 ps
CPU time 0.62 seconds
Started Jul 10 05:13:40 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 197764 kb
Host smart-b8821abf-01bd-428c-8a32-fd10a1c13ae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061171965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3061171965
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.442791854
Short name T450
Test name
Test status
Simulation time 41897470 ps
CPU time 0.7 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:42 PM PDT 24
Peak memory 197784 kb
Host smart-19cbd957-51eb-4877-8c44-808e99130115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442791854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.442791854
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.4230828825
Short name T915
Test name
Test status
Simulation time 41139835 ps
CPU time 0.72 seconds
Started Jul 10 05:13:38 PM PDT 24
Finished Jul 10 05:13:41 PM PDT 24
Peak memory 201060 kb
Host smart-c90ef320-18ff-4236-8b6c-cb0a8c3054ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230828825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.4230828825
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.1842199858
Short name T245
Test name
Test status
Simulation time 105417900 ps
CPU time 0.84 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:42 PM PDT 24
Peak memory 198148 kb
Host smart-7d26f091-20da-43f6-a989-fd3142de15dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842199858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.1842199858
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.3011711709
Short name T512
Test name
Test status
Simulation time 50124824 ps
CPU time 0.81 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:42 PM PDT 24
Peak memory 198780 kb
Host smart-f10b3cd9-8a8c-41ad-a905-9d39448509f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011711709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3011711709
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1657463085
Short name T349
Test name
Test status
Simulation time 102397734 ps
CPU time 1.11 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:49 PM PDT 24
Peak memory 209256 kb
Host smart-3df80086-c197-4b38-9e87-97ed55ed11ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657463085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1657463085
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3471106113
Short name T779
Test name
Test status
Simulation time 196514501 ps
CPU time 0.82 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:49 PM PDT 24
Peak memory 198876 kb
Host smart-26063218-767a-4157-a2d6-8856c39a2b34
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471106113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.3471106113
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.816380287
Short name T790
Test name
Test status
Simulation time 1277053072 ps
CPU time 2.22 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 200744 kb
Host smart-2b6c1b58-5aa5-4055-8324-0987bb7fcd2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816380287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.816380287
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3264584764
Short name T949
Test name
Test status
Simulation time 1235134470 ps
CPU time 2.19 seconds
Started Jul 10 05:13:42 PM PDT 24
Finished Jul 10 05:13:48 PM PDT 24
Peak memory 200732 kb
Host smart-41b33ad3-54a4-45e4-81f4-1d8e1f6c95d5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264584764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3264584764
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3802084477
Short name T647
Test name
Test status
Simulation time 51230619 ps
CPU time 0.88 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 199008 kb
Host smart-f412a7ed-fa07-43c5-879c-1e52c3f49cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802084477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3802084477
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1077467643
Short name T559
Test name
Test status
Simulation time 39220049 ps
CPU time 0.73 seconds
Started Jul 10 05:13:38 PM PDT 24
Finished Jul 10 05:13:40 PM PDT 24
Peak memory 199084 kb
Host smart-8a362537-8415-42a1-8575-1f08fc3282ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077467643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1077467643
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.437148866
Short name T926
Test name
Test status
Simulation time 478112932 ps
CPU time 1.75 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 200796 kb
Host smart-b8949367-9975-4be7-b206-e0d8b19a5590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437148866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.437148866
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.1755372732
Short name T787
Test name
Test status
Simulation time 11312008846 ps
CPU time 20.31 seconds
Started Jul 10 05:13:43 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 200984 kb
Host smart-cc3c9e2c-0ddb-45d2-a898-5dc382959958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755372732 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.1755372732
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.2850867439
Short name T823
Test name
Test status
Simulation time 472584807 ps
CPU time 0.96 seconds
Started Jul 10 05:13:41 PM PDT 24
Finished Jul 10 05:13:45 PM PDT 24
Peak memory 199476 kb
Host smart-356676c2-ddf1-487d-ac25-61b9b71ac757
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850867439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2850867439
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.874660601
Short name T893
Test name
Test status
Simulation time 153161513 ps
CPU time 0.93 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 199576 kb
Host smart-510ad3c5-8a05-40fc-9ae6-cc0036e3b9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874660601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.874660601
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1644645703
Short name T984
Test name
Test status
Simulation time 52323038 ps
CPU time 0.67 seconds
Started Jul 10 05:13:42 PM PDT 24
Finished Jul 10 05:13:47 PM PDT 24
Peak memory 198712 kb
Host smart-e6337fe4-5273-49b5-adcd-7fb6ec6efdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644645703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1644645703
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3964813242
Short name T963
Test name
Test status
Simulation time 64595034 ps
CPU time 0.75 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198316 kb
Host smart-aa406a31-205f-4750-a7eb-04d866d256b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964813242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3964813242
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.812137631
Short name T883
Test name
Test status
Simulation time 29674260 ps
CPU time 0.61 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 197740 kb
Host smart-e85b6ca1-7c58-4d50-a56f-83ec8fd3b94a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812137631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.812137631
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.734303200
Short name T764
Test name
Test status
Simulation time 582191299 ps
CPU time 0.97 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198120 kb
Host smart-dd9bca83-0742-4240-9e0a-05b05e909444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734303200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.734303200
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.1979827639
Short name T33
Test name
Test status
Simulation time 61061127 ps
CPU time 0.59 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 197824 kb
Host smart-63606bbb-5263-4001-ad54-a4643b0a0017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979827639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1979827639
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3390160459
Short name T340
Test name
Test status
Simulation time 41501441 ps
CPU time 0.62 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 197784 kb
Host smart-cb4d2312-6b8e-4aee-b5f5-8cbb2875dcba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390160459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3390160459
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.2690458632
Short name T950
Test name
Test status
Simulation time 45631007 ps
CPU time 0.75 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:50 PM PDT 24
Peak memory 201060 kb
Host smart-d5b57a70-61d3-42ff-85e3-d185b43ad64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690458632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.2690458632
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.2689734820
Short name T789
Test name
Test status
Simulation time 115722749 ps
CPU time 0.73 seconds
Started Jul 10 05:13:42 PM PDT 24
Finished Jul 10 05:13:46 PM PDT 24
Peak memory 198028 kb
Host smart-9addacc5-67b2-48fb-97c3-521297f1a5b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689734820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.2689734820
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3419348551
Short name T385
Test name
Test status
Simulation time 93312459 ps
CPU time 0.91 seconds
Started Jul 10 05:13:43 PM PDT 24
Finished Jul 10 05:13:47 PM PDT 24
Peak memory 199532 kb
Host smart-bd36c880-3b5f-4eee-a7c6-d0563ad66da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419348551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3419348551
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3743245752
Short name T421
Test name
Test status
Simulation time 152415257 ps
CPU time 0.84 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 209284 kb
Host smart-0d530d02-93e3-43c6-867e-fda676fdde08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743245752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3743245752
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.3543058598
Short name T352
Test name
Test status
Simulation time 279557064 ps
CPU time 1.25 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 199912 kb
Host smart-57223967-6166-43a9-8ec8-9ff2510abc10
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543058598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.3543058598
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3647969556
Short name T521
Test name
Test status
Simulation time 1011865129 ps
CPU time 2 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:45 PM PDT 24
Peak memory 200756 kb
Host smart-2ba1b232-9497-42cd-b626-515ed91b6c6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647969556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3647969556
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1495898760
Short name T838
Test name
Test status
Simulation time 835634146 ps
CPU time 3.33 seconds
Started Jul 10 05:13:48 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 200816 kb
Host smart-fa5cc4cd-edd4-4d8a-91dc-7c01d080caf2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495898760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1495898760
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3178000986
Short name T651
Test name
Test status
Simulation time 68242042 ps
CPU time 0.91 seconds
Started Jul 10 05:13:39 PM PDT 24
Finished Jul 10 05:13:44 PM PDT 24
Peak memory 198976 kb
Host smart-2ad80ae9-d26e-495d-b467-207eb6b0210b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178000986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3178000986
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2675650542
Short name T957
Test name
Test status
Simulation time 191918517 ps
CPU time 0.64 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:49 PM PDT 24
Peak memory 198320 kb
Host smart-ce257a61-52e0-4760-af78-bf25e790bd15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675650542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2675650542
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.4006695563
Short name T92
Test name
Test status
Simulation time 557288301 ps
CPU time 2.3 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:14:00 PM PDT 24
Peak memory 200888 kb
Host smart-e4789306-8774-4e30-a522-2a568ab0c476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006695563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.4006695563
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2571638749
Short name T80
Test name
Test status
Simulation time 5071212249 ps
CPU time 10.44 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 200984 kb
Host smart-fe98b950-2acb-4b9f-b632-2e48a24f98e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571638749 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.2571638749
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.3496899504
Short name T196
Test name
Test status
Simulation time 39575756 ps
CPU time 0.62 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 197828 kb
Host smart-bffe77f8-ff66-42f3-8a43-0e7b539302a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496899504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.3496899504
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.3440564296
Short name T855
Test name
Test status
Simulation time 207999710 ps
CPU time 1.11 seconds
Started Jul 10 05:13:48 PM PDT 24
Finished Jul 10 05:13:55 PM PDT 24
Peak memory 199644 kb
Host smart-72b7f72b-2d65-460c-8cba-70d1eee1d871
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440564296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.3440564296
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.717230706
Short name T508
Test name
Test status
Simulation time 32651827 ps
CPU time 0.77 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:50 PM PDT 24
Peak memory 198772 kb
Host smart-a76fa00f-5951-455b-82df-06923a3abfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717230706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.717230706
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3710477979
Short name T586
Test name
Test status
Simulation time 66734491 ps
CPU time 0.73 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198452 kb
Host smart-e245889e-c6ef-44d1-8d9c-8293a6d9f5d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710477979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.3710477979
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2673319339
Short name T229
Test name
Test status
Simulation time 30727334 ps
CPU time 0.67 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:52 PM PDT 24
Peak memory 197672 kb
Host smart-c984cb75-de6e-4f1b-b01b-dd4469c56535
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673319339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2673319339
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.614854849
Short name T899
Test name
Test status
Simulation time 683822168 ps
CPU time 1.01 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 197816 kb
Host smart-e202182a-fe92-4311-94f8-7f86df4084fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614854849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.614854849
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.29085550
Short name T461
Test name
Test status
Simulation time 234392099 ps
CPU time 0.63 seconds
Started Jul 10 05:13:49 PM PDT 24
Finished Jul 10 05:13:56 PM PDT 24
Peak memory 197744 kb
Host smart-b7f607b7-350f-40ba-8f2f-35cb8bd1cc9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.29085550
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.967889775
Short name T951
Test name
Test status
Simulation time 239301245 ps
CPU time 0.61 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 197704 kb
Host smart-c97b38e5-b4ea-4d19-aff1-0ae855fb8312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967889775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.967889775
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.751489347
Short name T517
Test name
Test status
Simulation time 73970073 ps
CPU time 0.7 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 201004 kb
Host smart-94045f79-b830-4fb7-85f4-7a3b7c6a8446
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751489347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.751489347
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.2735033525
Short name T830
Test name
Test status
Simulation time 469621328 ps
CPU time 1.05 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 199484 kb
Host smart-8e69358b-bbe5-4018-92df-d097de6378d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735033525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.2735033525
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.835718652
Short name T324
Test name
Test status
Simulation time 105171122 ps
CPU time 0.67 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198004 kb
Host smart-13208f61-a49e-472b-a725-c766e39c1c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835718652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.835718652
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3085709273
Short name T39
Test name
Test status
Simulation time 106564129 ps
CPU time 0.96 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:50 PM PDT 24
Peak memory 209220 kb
Host smart-9b095c3e-db64-4398-aa63-aaf913f5e959
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085709273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3085709273
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1928274106
Short name T652
Test name
Test status
Simulation time 214126109 ps
CPU time 0.98 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 199900 kb
Host smart-ea78bd4f-223f-4a30-aee4-cc8e1921a77a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928274106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.1928274106
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034075778
Short name T720
Test name
Test status
Simulation time 932746682 ps
CPU time 2.57 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 201096 kb
Host smart-469629d5-c3c6-4bf6-bbd9-cbcf2a31873a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034075778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034075778
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4049684089
Short name T146
Test name
Test status
Simulation time 836603494 ps
CPU time 2.41 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 200816 kb
Host smart-0b597b40-f485-4692-ae15-69d28da7abfa
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049684089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4049684089
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3736585802
Short name T253
Test name
Test status
Simulation time 98157510 ps
CPU time 0.81 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:50 PM PDT 24
Peak memory 198872 kb
Host smart-d74336e5-63f2-4388-876b-196d24f05479
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736585802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3736585802
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1345009264
Short name T848
Test name
Test status
Simulation time 46443118 ps
CPU time 0.65 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 199068 kb
Host smart-59d5148c-91fe-44a6-bb93-7f5ddab25504
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345009264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1345009264
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.4151197433
Short name T76
Test name
Test status
Simulation time 1872032735 ps
CPU time 5.84 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 200896 kb
Host smart-4f901f9a-b1ef-4cda-b1d3-59fdeea5cf2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151197433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.4151197433
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.798277670
Short name T78
Test name
Test status
Simulation time 8084799402 ps
CPU time 11.35 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 200996 kb
Host smart-879ace63-0f08-4e1c-ab42-749cd0756bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798277670 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.798277670
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.174701905
Short name T849
Test name
Test status
Simulation time 151352207 ps
CPU time 1.01 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 199304 kb
Host smart-697bad11-cd51-4ef2-8ad7-0453359122e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174701905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.174701905
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.616828506
Short name T214
Test name
Test status
Simulation time 430028235 ps
CPU time 1.14 seconds
Started Jul 10 05:13:50 PM PDT 24
Finished Jul 10 05:13:56 PM PDT 24
Peak memory 200516 kb
Host smart-4958938b-2f61-4820-8e21-55be9eb8c4a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616828506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.616828506
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2438111719
Short name T379
Test name
Test status
Simulation time 52383567 ps
CPU time 0.73 seconds
Started Jul 10 05:13:43 PM PDT 24
Finished Jul 10 05:13:48 PM PDT 24
Peak memory 199848 kb
Host smart-d87aa461-5f92-4045-9534-b545b2904332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438111719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2438111719
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1139411191
Short name T954
Test name
Test status
Simulation time 32162380 ps
CPU time 0.64 seconds
Started Jul 10 05:13:48 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 196956 kb
Host smart-3edc2306-e8b4-48c3-a37d-b8c03390566c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139411191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1139411191
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1010729392
Short name T141
Test name
Test status
Simulation time 601860066 ps
CPU time 1.04 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198120 kb
Host smart-f7e2e012-4283-45d4-b3f1-69b11a451424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010729392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1010729392
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2543582656
Short name T18
Test name
Test status
Simulation time 61438136 ps
CPU time 0.65 seconds
Started Jul 10 05:13:43 PM PDT 24
Finished Jul 10 05:13:48 PM PDT 24
Peak memory 197664 kb
Host smart-4d41cbbc-ece5-4703-bb8f-4b5088a27afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543582656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2543582656
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3566941663
Short name T321
Test name
Test status
Simulation time 43867141 ps
CPU time 0.67 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 198104 kb
Host smart-d67eade5-f047-4aab-a8bd-333c18dc0288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566941663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3566941663
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1967509897
Short name T897
Test name
Test status
Simulation time 69175830 ps
CPU time 0.68 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 201064 kb
Host smart-5152e377-a3fa-4972-9874-5aafe977610a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967509897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1967509897
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.3482944335
Short name T728
Test name
Test status
Simulation time 43098696 ps
CPU time 0.63 seconds
Started Jul 10 05:13:47 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 198744 kb
Host smart-c3b52020-4987-4f82-98e4-c8e1a5cec9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482944335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.3482944335
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.1022246647
Short name T191
Test name
Test status
Simulation time 74633681 ps
CPU time 0.72 seconds
Started Jul 10 05:13:44 PM PDT 24
Finished Jul 10 05:13:49 PM PDT 24
Peak memory 198056 kb
Host smart-bcbac2ea-ebf7-4a94-8389-96f71ce0473b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022246647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1022246647
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.885018114
Short name T40
Test name
Test status
Simulation time 152026680 ps
CPU time 0.8 seconds
Started Jul 10 05:13:49 PM PDT 24
Finished Jul 10 05:13:55 PM PDT 24
Peak memory 209100 kb
Host smart-38964564-8203-4bbb-b05a-3c63a632d322
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885018114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.885018114
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2383682811
Short name T678
Test name
Test status
Simulation time 99000926 ps
CPU time 0.93 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 198880 kb
Host smart-bd531fac-07c6-4817-b6ad-dbf8b7e480f9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383682811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.2383682811
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3947692725
Short name T919
Test name
Test status
Simulation time 831829750 ps
CPU time 3.24 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:53 PM PDT 24
Peak memory 200888 kb
Host smart-c1b26cf4-5fe7-4ff4-b7ba-1020897b52a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947692725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3947692725
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3384156783
Short name T804
Test name
Test status
Simulation time 1218134083 ps
CPU time 2.37 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 200768 kb
Host smart-e36691fc-2ac3-4444-a4ed-5a9e6dfa55d8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384156783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3384156783
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3429916513
Short name T656
Test name
Test status
Simulation time 130493821 ps
CPU time 0.87 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 199072 kb
Host smart-aad32309-7edf-427f-98f6-11c9fb7ffce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429916513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3429916513
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.4012120329
Short name T748
Test name
Test status
Simulation time 30794556 ps
CPU time 0.68 seconds
Started Jul 10 05:13:45 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 199084 kb
Host smart-1cc19e65-7f30-43b0-be48-05b8eb53b017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012120329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.4012120329
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.124532605
Short name T605
Test name
Test status
Simulation time 103773839 ps
CPU time 1.33 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 200732 kb
Host smart-3715bef7-9630-46c6-a176-4523de1bd825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124532605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.124532605
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2181742748
Short name T48
Test name
Test status
Simulation time 10732330218 ps
CPU time 26.22 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:14:22 PM PDT 24
Peak memory 201040 kb
Host smart-328e6690-7884-4e18-a569-4c93ac085f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181742748 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.2181742748
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.4218350699
Short name T731
Test name
Test status
Simulation time 74064725 ps
CPU time 0.77 seconds
Started Jul 10 05:13:46 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 197976 kb
Host smart-a6027ce9-01e9-47af-b3c0-30c59724f388
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218350699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.4218350699
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.2871271569
Short name T203
Test name
Test status
Simulation time 139490152 ps
CPU time 0.83 seconds
Started Jul 10 05:13:50 PM PDT 24
Finished Jul 10 05:13:56 PM PDT 24
Peak memory 199000 kb
Host smart-070e041f-f9d9-4f56-a132-de5d61c454f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871271569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.2871271569
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.4274592327
Short name T659
Test name
Test status
Simulation time 25419243 ps
CPU time 0.78 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 199552 kb
Host smart-835bb397-c886-490c-b011-4577c52aa9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274592327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.4274592327
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1935158498
Short name T414
Test name
Test status
Simulation time 68471420 ps
CPU time 0.7 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 198748 kb
Host smart-8a7fff29-63b3-4a24-a13e-3722e06be949
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935158498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1935158498
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3662850940
Short name T144
Test name
Test status
Simulation time 37010374 ps
CPU time 0.59 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 197724 kb
Host smart-ae7717d4-3d2f-4350-bce0-9e72a2989da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662850940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3662850940
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2252312257
Short name T740
Test name
Test status
Simulation time 166772703 ps
CPU time 0.94 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 198140 kb
Host smart-6c68d1e3-4ac6-4070-8b26-a3f91c5a60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252312257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2252312257
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.2343670869
Short name T315
Test name
Test status
Simulation time 45233345 ps
CPU time 0.62 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 197936 kb
Host smart-a6091949-e133-4b80-8878-a35f07e6a731
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343670869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.2343670869
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.4173172485
Short name T339
Test name
Test status
Simulation time 89563000 ps
CPU time 0.59 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 197708 kb
Host smart-3ffa99fb-dd67-4817-a8ad-257ec38640f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173172485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.4173172485
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3075964617
Short name T574
Test name
Test status
Simulation time 36893499 ps
CPU time 0.72 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 201056 kb
Host smart-1d734fe4-813d-41fa-817d-a7956f184f4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075964617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3075964617
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.3698641165
Short name T358
Test name
Test status
Simulation time 295548825 ps
CPU time 1.31 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 199540 kb
Host smart-05e9bf34-71b5-46a8-a3f0-119119e1e61e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698641165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.3698641165
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2760365510
Short name T931
Test name
Test status
Simulation time 55983714 ps
CPU time 0.89 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 199432 kb
Host smart-1d2c6eb6-2c5a-4217-8996-6d3db3ab0df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760365510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2760365510
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2246127357
Short name T539
Test name
Test status
Simulation time 171594411 ps
CPU time 0.8 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 209192 kb
Host smart-9fbc3033-496d-4490-a0a3-a8f2155d306b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246127357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2246127357
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1792247716
Short name T495
Test name
Test status
Simulation time 407061995 ps
CPU time 1.03 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 200416 kb
Host smart-a82ad549-b95e-49a9-a91d-8a2549570989
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792247716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1792247716
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1615536257
Short name T394
Test name
Test status
Simulation time 1541285632 ps
CPU time 2.11 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:14:00 PM PDT 24
Peak memory 200860 kb
Host smart-b6c1f003-1e97-4fcb-aaaf-61f7de6f6ecb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615536257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1615536257
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.720820471
Short name T477
Test name
Test status
Simulation time 851987082 ps
CPU time 2.47 seconds
Started Jul 10 05:13:55 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 200760 kb
Host smart-65a767fc-3fff-4434-9a9d-d2ff351122c0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720820471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.720820471
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4114030400
Short name T606
Test name
Test status
Simulation time 72256879 ps
CPU time 0.83 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 199000 kb
Host smart-678be67a-8afb-482d-aab0-599d53a07494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114030400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4114030400
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3867384017
Short name T842
Test name
Test status
Simulation time 29227524 ps
CPU time 0.77 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 198980 kb
Host smart-309fff69-6eb1-4bb0-9643-348893ffa81a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867384017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3867384017
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.2774718035
Short name T722
Test name
Test status
Simulation time 828291151 ps
CPU time 3.35 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:14:00 PM PDT 24
Peak memory 200892 kb
Host smart-c8ed2a2d-ffbb-4b58-9136-3f8161e3bd50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774718035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2774718035
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.64997862
Short name T683
Test name
Test status
Simulation time 9157167740 ps
CPU time 15.69 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 201068 kb
Host smart-c93d1a66-d14f-44f1-bdb2-856d81019aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64997862 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.64997862
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.755960938
Short name T232
Test name
Test status
Simulation time 121069280 ps
CPU time 0.73 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 197932 kb
Host smart-abe34b46-4cbe-4e95-9b01-f984b762be12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755960938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.755960938
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.321277039
Short name T701
Test name
Test status
Simulation time 119164673 ps
CPU time 0.8 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 199044 kb
Host smart-921b36c3-14ba-48ea-a118-967f7bb66c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321277039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.321277039
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.2342189111
Short name T542
Test name
Test status
Simulation time 36214007 ps
CPU time 1.18 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 200676 kb
Host smart-13e85d92-8f5a-4b94-9690-36d662ccceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342189111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2342189111
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3893786241
Short name T562
Test name
Test status
Simulation time 98711538 ps
CPU time 0.73 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198820 kb
Host smart-428b62af-86d1-4c01-95c5-b7de45d7da92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893786241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3893786241
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2740813031
Short name T767
Test name
Test status
Simulation time 51448734 ps
CPU time 0.63 seconds
Started Jul 10 05:13:57 PM PDT 24
Finished Jul 10 05:14:01 PM PDT 24
Peak memory 197024 kb
Host smart-fc1a0d5b-19d5-4d76-811c-ce4d96bcf59a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740813031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.2740813031
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.644020756
Short name T805
Test name
Test status
Simulation time 553280441 ps
CPU time 0.95 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:05 PM PDT 24
Peak memory 197800 kb
Host smart-dbfdddb5-dd46-43cb-91d1-23c27a2ced25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644020756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.644020756
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2545629992
Short name T784
Test name
Test status
Simulation time 155343333 ps
CPU time 0.64 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 197088 kb
Host smart-5bf736a9-d501-4138-83ac-47e6a1521bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545629992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2545629992
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.745474811
Short name T815
Test name
Test status
Simulation time 113492011 ps
CPU time 0.63 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 197964 kb
Host smart-685b9f5c-0127-4bd8-81d4-564b93b67ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745474811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.745474811
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.794013270
Short name T528
Test name
Test status
Simulation time 45641225 ps
CPU time 0.71 seconds
Started Jul 10 05:14:01 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 201072 kb
Host smart-d707bda5-0298-486b-bafe-0414666232d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794013270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.794013270
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.3433996851
Short name T216
Test name
Test status
Simulation time 50139877 ps
CPU time 0.66 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 198216 kb
Host smart-4aec0eda-b017-49ef-9afc-e933536804d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433996851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.3433996851
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.3560013274
Short name T38
Test name
Test status
Simulation time 25763753 ps
CPU time 0.71 seconds
Started Jul 10 05:13:53 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 198756 kb
Host smart-671dc4fc-e325-44a0-ba12-75bef0a001b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560013274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.3560013274
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.428488232
Short name T707
Test name
Test status
Simulation time 121109814 ps
CPU time 1 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 209112 kb
Host smart-83a1d71c-ac72-4fbf-a4bf-8ac306a22508
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428488232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.428488232
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.446545135
Short name T634
Test name
Test status
Simulation time 110530695 ps
CPU time 0.69 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 198836 kb
Host smart-d711d16f-f74a-454d-ac0e-01ec00ccfe6c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446545135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_c
m_ctrl_config_regwen.446545135
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3166811394
Short name T700
Test name
Test status
Simulation time 2393718795 ps
CPU time 1.96 seconds
Started Jul 10 05:13:51 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 200764 kb
Host smart-bf3f3189-b0d8-4b25-afa2-c2740805a16d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166811394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3166811394
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2033454868
Short name T685
Test name
Test status
Simulation time 61092457 ps
CPU time 0.88 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 198900 kb
Host smart-5ec89223-c003-4da7-b32e-05ae4f0e9f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033454868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2033454868
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.4292587923
Short name T201
Test name
Test status
Simulation time 30421053 ps
CPU time 0.67 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:13:59 PM PDT 24
Peak memory 198272 kb
Host smart-a6aaeebe-b46c-4245-bacc-7ba52d8aab48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292587923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.4292587923
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1097659124
Short name T959
Test name
Test status
Simulation time 128642082 ps
CPU time 0.75 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 198936 kb
Host smart-e1c88431-1571-4a32-9623-f3be613ab292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097659124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1097659124
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.1198298061
Short name T120
Test name
Test status
Simulation time 8464791895 ps
CPU time 14.61 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 201028 kb
Host smart-e9f3e0f0-088f-462f-b238-b6ac6e24cd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198298061 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.1198298061
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.4250636152
Short name T266
Test name
Test status
Simulation time 228425450 ps
CPU time 1.17 seconds
Started Jul 10 05:13:54 PM PDT 24
Finished Jul 10 05:14:00 PM PDT 24
Peak memory 199388 kb
Host smart-f2d8625c-999a-4263-b0a5-96a734dde14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250636152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.4250636152
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.1941728812
Short name T841
Test name
Test status
Simulation time 207166825 ps
CPU time 0.96 seconds
Started Jul 10 05:13:52 PM PDT 24
Finished Jul 10 05:13:57 PM PDT 24
Peak memory 199300 kb
Host smart-e6fcb872-5889-447d-8b1b-5ae4874a34ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941728812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1941728812
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.2184745835
Short name T998
Test name
Test status
Simulation time 38013977 ps
CPU time 0.83 seconds
Started Jul 10 05:14:01 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 199792 kb
Host smart-312474a3-b01e-48a7-a658-f0bcfd5e33c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184745835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.2184745835
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.4173320691
Short name T744
Test name
Test status
Simulation time 56889299 ps
CPU time 0.79 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 198172 kb
Host smart-3a7be3b0-ebe2-4208-8c4c-ee0db1b1ceec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173320691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.4173320691
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2562990117
Short name T573
Test name
Test status
Simulation time 46785564 ps
CPU time 0.61 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 197744 kb
Host smart-cd206755-28bd-4f7a-9652-607dbd8764b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562990117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.2562990117
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2288045555
Short name T626
Test name
Test status
Simulation time 630015962 ps
CPU time 1 seconds
Started Jul 10 05:13:57 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 198120 kb
Host smart-a0cb46ac-f9f3-42b6-8260-bd25c0614d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288045555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2288045555
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.3126880341
Short name T90
Test name
Test status
Simulation time 40302041 ps
CPU time 0.62 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 197744 kb
Host smart-2fcf8f8e-faa4-449d-a4bf-223b381abeac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126880341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3126880341
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.824487037
Short name T716
Test name
Test status
Simulation time 30047110 ps
CPU time 0.64 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 197784 kb
Host smart-cc0d8647-d70d-4251-821d-ac60fd0f191b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824487037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.824487037
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.744412320
Short name T211
Test name
Test status
Simulation time 40234379 ps
CPU time 0.69 seconds
Started Jul 10 05:13:57 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 200984 kb
Host smart-da67d184-38ed-4279-9568-02778bde6c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744412320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invali
d.744412320
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.3089142520
Short name T895
Test name
Test status
Simulation time 39704664 ps
CPU time 0.7 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198000 kb
Host smart-36f0fd70-763b-44b8-86fc-d6d8702e3e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089142520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.3089142520
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3881544588
Short name T905
Test name
Test status
Simulation time 53550941 ps
CPU time 0.79 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198876 kb
Host smart-a45cd5d2-1907-4814-8534-ddf67ab8f4aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881544588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3881544588
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3929731322
Short name T440
Test name
Test status
Simulation time 163626008 ps
CPU time 0.82 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 209248 kb
Host smart-6c81b39c-999f-4a1f-8709-4b7802c742aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929731322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3929731322
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1371810237
Short name T424
Test name
Test status
Simulation time 188227558 ps
CPU time 1.01 seconds
Started Jul 10 05:14:01 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 199812 kb
Host smart-f0a8b4c5-1122-4d3c-858a-cef0b88c6fb1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371810237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.1371810237
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1868557596
Short name T267
Test name
Test status
Simulation time 1135158735 ps
CPU time 2.25 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 200964 kb
Host smart-ebad07e3-67b5-4420-93ee-04525d5b5217
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868557596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1868557596
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1099055077
Short name T380
Test name
Test status
Simulation time 1438238983 ps
CPU time 2.12 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 200884 kb
Host smart-e7581398-058a-4a11-a3bd-23926d2975e3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099055077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1099055077
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4143472693
Short name T932
Test name
Test status
Simulation time 141959546 ps
CPU time 0.96 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198936 kb
Host smart-a3bcd73a-d030-4ef8-a60b-704407745c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143472693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4143472693
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.977759027
Short name T738
Test name
Test status
Simulation time 32696102 ps
CPU time 0.74 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 199024 kb
Host smart-75108f9b-5328-40d3-af77-96caa628cff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977759027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.977759027
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.3366153549
Short name T197
Test name
Test status
Simulation time 308009882 ps
CPU time 1.56 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 200888 kb
Host smart-4bace68a-114a-400c-9b04-8046fffc931a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366153549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.3366153549
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3064662708
Short name T773
Test name
Test status
Simulation time 6173395357 ps
CPU time 8.52 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:12 PM PDT 24
Peak memory 201016 kb
Host smart-fc4eda51-2ec4-4455-9f00-206ffe2f75f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064662708 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.3064662708
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.1349365515
Short name T648
Test name
Test status
Simulation time 187733122 ps
CPU time 0.8 seconds
Started Jul 10 05:14:02 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 198220 kb
Host smart-f1d98be9-6484-4d95-b55f-c1d6654b2b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349365515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.1349365515
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.568327059
Short name T596
Test name
Test status
Simulation time 137598889 ps
CPU time 0.75 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 199000 kb
Host smart-a8059580-4bb2-4b9a-b7a1-4fc647d38a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568327059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.568327059
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3509781687
Short name T643
Test name
Test status
Simulation time 23195934 ps
CPU time 0.68 seconds
Started Jul 10 05:14:03 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 198340 kb
Host smart-7d2ba88a-de6e-4cf8-9c7b-d83e47b8d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509781687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3509781687
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2184202575
Short name T34
Test name
Test status
Simulation time 73235586 ps
CPU time 0.7 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198128 kb
Host smart-f16ef1ab-825b-435c-949f-9d3d6a6854c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184202575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.2184202575
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1192583657
Short name T853
Test name
Test status
Simulation time 29117967 ps
CPU time 0.72 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 197716 kb
Host smart-2db847e4-9f40-43c8-9cbf-52c8c8645b25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192583657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1192583657
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1426543784
Short name T967
Test name
Test status
Simulation time 314565823 ps
CPU time 0.99 seconds
Started Jul 10 05:13:57 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 197812 kb
Host smart-d132a5f4-734f-4604-b074-ca3726391175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426543784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1426543784
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3582775340
Short name T672
Test name
Test status
Simulation time 52165306 ps
CPU time 0.7 seconds
Started Jul 10 05:13:57 PM PDT 24
Finished Jul 10 05:14:01 PM PDT 24
Peak memory 197048 kb
Host smart-b0360e77-e653-485f-818e-b96b6b48fb2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582775340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3582775340
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2230133802
Short name T622
Test name
Test status
Simulation time 52290183 ps
CPU time 0.68 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:05 PM PDT 24
Peak memory 198104 kb
Host smart-416adc0a-46ad-4fbf-8f38-b18e8a0d1f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230133802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2230133802
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.563504462
Short name T752
Test name
Test status
Simulation time 41643757 ps
CPU time 0.72 seconds
Started Jul 10 05:14:03 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 201080 kb
Host smart-bddfdf26-0e4f-46c5-a2eb-f818d5f16281
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563504462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.563504462
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.3365811506
Short name T147
Test name
Test status
Simulation time 86773248 ps
CPU time 0.83 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198228 kb
Host smart-29ccd021-1ec3-4c8a-8207-6b1d8fecfeee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365811506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.3365811506
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1227039221
Short name T635
Test name
Test status
Simulation time 89247664 ps
CPU time 0.77 seconds
Started Jul 10 05:14:01 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 198800 kb
Host smart-5c0ad189-0d23-4ed6-adee-0e8179cb82ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227039221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1227039221
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.1747257756
Short name T271
Test name
Test status
Simulation time 92463270 ps
CPU time 1.03 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 209148 kb
Host smart-999ce040-761d-4767-af1e-5d906451a961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747257756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1747257756
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1312706026
Short name T208
Test name
Test status
Simulation time 31796056 ps
CPU time 0.68 seconds
Started Jul 10 05:14:03 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 198244 kb
Host smart-727539bc-418d-4cda-9076-d486f64481c4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312706026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.1312706026
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.723163105
Short name T310
Test name
Test status
Simulation time 920491578 ps
CPU time 2.44 seconds
Started Jul 10 05:13:56 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 200760 kb
Host smart-cad47f11-8e67-4719-a5db-ea56c849107d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723163105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.723163105
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2572011765
Short name T675
Test name
Test status
Simulation time 953939970 ps
CPU time 3.25 seconds
Started Jul 10 05:14:00 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 200884 kb
Host smart-24964da0-3071-47c8-b8dd-440c0621a9b9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572011765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2572011765
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.1856540395
Short name T438
Test name
Test status
Simulation time 140134723 ps
CPU time 0.89 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 198956 kb
Host smart-e4d54157-45e6-49af-94ef-0e08ffa0d28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856540395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1856540395
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.3856835049
Short name T442
Test name
Test status
Simulation time 31570707 ps
CPU time 0.71 seconds
Started Jul 10 05:13:58 PM PDT 24
Finished Jul 10 05:14:02 PM PDT 24
Peak memory 198128 kb
Host smart-2875f89d-f75b-464f-892f-0c78ddbfd37d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856835049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3856835049
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.2300283113
Short name T845
Test name
Test status
Simulation time 1255441699 ps
CPU time 4.66 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 200888 kb
Host smart-2e614d1b-33dd-4c7d-a538-c2fd66fa8bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300283113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.2300283113
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.987130640
Short name T377
Test name
Test status
Simulation time 3467325513 ps
CPU time 12.83 seconds
Started Jul 10 05:14:08 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 200992 kb
Host smart-29eba634-d1cc-4a05-aac2-c54020a1822a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987130640 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.987130640
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.1559748324
Short name T968
Test name
Test status
Simulation time 340084592 ps
CPU time 1.02 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 199520 kb
Host smart-8e5a13f8-a600-43f5-a8bb-397f6543355d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559748324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.1559748324
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.2467877938
Short name T376
Test name
Test status
Simulation time 141738453 ps
CPU time 0.77 seconds
Started Jul 10 05:13:59 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 199052 kb
Host smart-57d31ba7-56ea-4d89-9631-a34fee1a0b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467877938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.2467877938
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2766410346
Short name T620
Test name
Test status
Simulation time 105748950 ps
CPU time 0.68 seconds
Started Jul 10 05:14:03 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 198440 kb
Host smart-3ebdabc6-babc-4290-998f-9deaa66290a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766410346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2766410346
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3599061589
Short name T400
Test name
Test status
Simulation time 70676684 ps
CPU time 0.89 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198808 kb
Host smart-8e11ed5e-febd-4d7d-b922-a2351038d840
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599061589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3599061589
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3993711727
Short name T953
Test name
Test status
Simulation time 30092766 ps
CPU time 0.61 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 197684 kb
Host smart-922f0dec-b7b8-422d-a704-bf5d3abb2f42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993711727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3993711727
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1375508103
Short name T612
Test name
Test status
Simulation time 160120332 ps
CPU time 0.99 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 197500 kb
Host smart-84143bf5-8183-454d-84c5-3ca7029f89e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375508103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1375508103
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.1653935835
Short name T839
Test name
Test status
Simulation time 74562550 ps
CPU time 0.6 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:15 PM PDT 24
Peak memory 196976 kb
Host smart-d04f7892-4248-47e2-a0a4-1300f32b2e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653935835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1653935835
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.587092673
Short name T431
Test name
Test status
Simulation time 45095477 ps
CPU time 0.62 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 198088 kb
Host smart-dc56a053-3b1c-4d27-a644-e4b0e4dcb266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587092673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.587092673
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.4029740002
Short name T771
Test name
Test status
Simulation time 96191244 ps
CPU time 0.67 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 201024 kb
Host smart-067a78b4-f0e9-43a0-b08c-ee5616623104
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029740002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.4029740002
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2372656249
Short name T943
Test name
Test status
Simulation time 198433858 ps
CPU time 0.93 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 199364 kb
Host smart-52d41453-9695-4fa4-97aa-92c1e51590b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372656249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2372656249
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2164091133
Short name T599
Test name
Test status
Simulation time 44518804 ps
CPU time 0.79 seconds
Started Jul 10 05:14:06 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 198868 kb
Host smart-0080b454-4e57-4766-a479-26dcb5fc7274
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164091133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2164091133
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.536083129
Short name T900
Test name
Test status
Simulation time 111076014 ps
CPU time 0.95 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 209204 kb
Host smart-c50a8df6-8f8c-4b6d-8d9e-39f1800c1043
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536083129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.536083129
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1056829862
Short name T725
Test name
Test status
Simulation time 201901649 ps
CPU time 1.15 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 199548 kb
Host smart-535689f3-380c-40f6-a4f9-cbe7e6249c17
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056829862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1056829862
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2869705735
Short name T386
Test name
Test status
Simulation time 1102177395 ps
CPU time 2.37 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 200760 kb
Host smart-f28d6059-7402-4e5c-94b3-281c8837d825
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869705735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2869705735
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.785177875
Short name T891
Test name
Test status
Simulation time 876063502 ps
CPU time 3.24 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 200872 kb
Host smart-f7e8f073-f5df-4dae-a11d-822a4bd9a45c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785177875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.785177875
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1385286551
Short name T758
Test name
Test status
Simulation time 104184735 ps
CPU time 0.93 seconds
Started Jul 10 05:14:07 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 199036 kb
Host smart-ddafbf30-2601-4651-8d32-9eeed28fd7fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385286551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1385286551
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3262671005
Short name T952
Test name
Test status
Simulation time 32206811 ps
CPU time 0.71 seconds
Started Jul 10 05:14:08 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 198940 kb
Host smart-5dacfc16-d406-4884-b3be-b39b3052adce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262671005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3262671005
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.2907923831
Short name T481
Test name
Test status
Simulation time 1592206244 ps
CPU time 6.29 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 200868 kb
Host smart-cf6bbf52-ec6b-48c1-879a-777f5ae95f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907923831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2907923831
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2000043671
Short name T581
Test name
Test status
Simulation time 2112742016 ps
CPU time 7.21 seconds
Started Jul 10 05:14:07 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 201032 kb
Host smart-bb3e431c-adbf-4b93-b1fa-48f01b50516e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000043671 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.2000043671
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.2257831654
Short name T962
Test name
Test status
Simulation time 41456926 ps
CPU time 0.67 seconds
Started Jul 10 05:14:03 PM PDT 24
Finished Jul 10 05:14:07 PM PDT 24
Peak memory 197836 kb
Host smart-1c18bc9c-9977-47f0-a41e-2764cf6bfee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257831654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2257831654
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.121530704
Short name T356
Test name
Test status
Simulation time 139187295 ps
CPU time 0.95 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 198908 kb
Host smart-30fccb74-83f6-4fd6-86f8-9f8001dbc118
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121530704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.121530704
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2331380023
Short name T497
Test name
Test status
Simulation time 136090591 ps
CPU time 0.85 seconds
Started Jul 10 05:14:06 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 199932 kb
Host smart-3be6cf80-4807-4002-9c5c-600d52c86269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331380023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2331380023
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3720165785
Short name T374
Test name
Test status
Simulation time 141749684 ps
CPU time 0.71 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 198416 kb
Host smart-b20a87d4-c4eb-4060-8663-0f2a0317e4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720165785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3720165785
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.112716583
Short name T591
Test name
Test status
Simulation time 30816207 ps
CPU time 0.62 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 197052 kb
Host smart-665a7ee4-e053-4f4f-8fe3-3c05741c06a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112716583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.112716583
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3140046167
Short name T465
Test name
Test status
Simulation time 664369177 ps
CPU time 0.95 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 198120 kb
Host smart-a3961463-2ade-47a4-80b6-008b704c0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140046167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3140046167
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.319538462
Short name T650
Test name
Test status
Simulation time 77295835 ps
CPU time 0.63 seconds
Started Jul 10 05:14:08 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 197828 kb
Host smart-0193319c-d045-4595-8136-ff3cf72d426e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319538462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.319538462
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2499175809
Short name T406
Test name
Test status
Simulation time 75229483 ps
CPU time 0.61 seconds
Started Jul 10 05:14:06 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 197808 kb
Host smart-38cdc48d-603e-4ae8-a79f-30ee947aa7ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499175809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2499175809
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.33888287
Short name T188
Test name
Test status
Simulation time 40253713 ps
CPU time 0.71 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 201064 kb
Host smart-4df36c1b-fd63-40e3-9454-5b16ca8972d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid
.33888287
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.1823433871
Short name T575
Test name
Test status
Simulation time 130070740 ps
CPU time 0.76 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198860 kb
Host smart-7687bf28-025e-41de-ae00-0aae90a1ffa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823433871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.1823433871
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2893976144
Short name T747
Test name
Test status
Simulation time 208803655 ps
CPU time 0.75 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198412 kb
Host smart-40d849b5-2ee4-41c4-985e-f0fac4299451
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893976144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2893976144
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1210646569
Short name T994
Test name
Test status
Simulation time 111145519 ps
CPU time 0.83 seconds
Started Jul 10 05:14:09 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 209284 kb
Host smart-261177f8-0364-4d4c-9ae5-4509b5efaf1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210646569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1210646569
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.922209034
Short name T527
Test name
Test status
Simulation time 63954391 ps
CPU time 0.65 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 198304 kb
Host smart-ab539b8d-c277-443f-8ba4-fa18a7d32f8d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922209034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_c
m_ctrl_config_regwen.922209034
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1019177388
Short name T569
Test name
Test status
Simulation time 784759197 ps
CPU time 3.07 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 200836 kb
Host smart-26893a81-1d19-48f2-98bb-cd7e0a5b237b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019177388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1019177388
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1023758373
Short name T302
Test name
Test status
Simulation time 808540160 ps
CPU time 2.53 seconds
Started Jul 10 05:14:05 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 200592 kb
Host smart-c603ee06-3cde-41b4-abd2-bf33d3c967d3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023758373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1023758373
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.82855824
Short name T594
Test name
Test status
Simulation time 130561380 ps
CPU time 0.87 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198904 kb
Host smart-db21fbaa-3b0d-4177-afb9-9197a3d4b0b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82855824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.82855824
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2725230223
Short name T73
Test name
Test status
Simulation time 76545569 ps
CPU time 0.72 seconds
Started Jul 10 05:14:08 PM PDT 24
Finished Jul 10 05:14:11 PM PDT 24
Peak memory 198232 kb
Host smart-e6cd6afe-8a7a-408c-b398-2b947f987e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725230223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2725230223
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.2516645320
Short name T496
Test name
Test status
Simulation time 1694790487 ps
CPU time 5.67 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:20 PM PDT 24
Peak memory 200824 kb
Host smart-f87d05e6-381c-447f-9842-1d4386f49afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516645320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.2516645320
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.27074689
Short name T127
Test name
Test status
Simulation time 16693537088 ps
CPU time 23.41 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 201064 kb
Host smart-e79b1efa-c7a3-49bf-b4cf-0feadf5c3fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074689 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.27074689
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.33248931
Short name T134
Test name
Test status
Simulation time 250368798 ps
CPU time 0.79 seconds
Started Jul 10 05:14:04 PM PDT 24
Finished Jul 10 05:14:08 PM PDT 24
Peak memory 198236 kb
Host smart-801c4641-4b06-486e-a8e5-0ddc69e4070c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.33248931
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.1514540937
Short name T460
Test name
Test status
Simulation time 53701281 ps
CPU time 0.68 seconds
Started Jul 10 05:14:07 PM PDT 24
Finished Jul 10 05:14:10 PM PDT 24
Peak memory 198916 kb
Host smart-0085c526-a567-4c86-8d97-8516e537c95e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514540937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1514540937
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3115425177
Short name T561
Test name
Test status
Simulation time 37372293 ps
CPU time 0.84 seconds
Started Jul 10 05:13:09 PM PDT 24
Finished Jul 10 05:13:13 PM PDT 24
Peak memory 198664 kb
Host smart-f2e93224-050c-4f99-9b19-b370d1435598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115425177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3115425177
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.244065441
Short name T687
Test name
Test status
Simulation time 94619100 ps
CPU time 0.71 seconds
Started Jul 10 05:12:29 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 198260 kb
Host smart-ac22bb32-5510-41ad-9fdb-0e36a536387d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244065441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.244065441
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1973815210
Short name T506
Test name
Test status
Simulation time 38549187 ps
CPU time 0.61 seconds
Started Jul 10 05:12:27 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 197740 kb
Host smart-b820a0da-d786-44ac-8334-1fa23064746e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973815210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.1973815210
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2720104529
Short name T485
Test name
Test status
Simulation time 557637296 ps
CPU time 1 seconds
Started Jul 10 05:12:27 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 197812 kb
Host smart-1630fcfc-d8ad-4065-ac44-7fe4bf2d2eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720104529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2720104529
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.2025958920
Short name T778
Test name
Test status
Simulation time 67438647 ps
CPU time 0.6 seconds
Started Jul 10 05:12:29 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 197744 kb
Host smart-fbd3babb-5c30-4763-bfcb-5adcfd5307d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025958920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2025958920
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3490015523
Short name T336
Test name
Test status
Simulation time 48785875 ps
CPU time 0.66 seconds
Started Jul 10 05:12:27 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 197716 kb
Host smart-590160e4-2dc4-40d3-9d52-0820e63a0539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490015523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3490015523
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.540711446
Short name T887
Test name
Test status
Simulation time 52724247 ps
CPU time 0.71 seconds
Started Jul 10 05:12:29 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 201116 kb
Host smart-00ba75d2-923c-42b7-bf82-2d4fc0639431
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540711446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid
.540711446
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.4248465927
Short name T239
Test name
Test status
Simulation time 126830556 ps
CPU time 0.67 seconds
Started Jul 10 05:12:25 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 197984 kb
Host smart-378ce9b4-f83b-4109-9f2e-0a3a67191e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248465927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.4248465927
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1135198375
Short name T417
Test name
Test status
Simulation time 60017475 ps
CPU time 0.87 seconds
Started Jul 10 05:12:25 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 198324 kb
Host smart-55dddfc7-d848-445f-bcfe-0bfa46ee4e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135198375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1135198375
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3058497325
Short name T277
Test name
Test status
Simulation time 108428711 ps
CPU time 0.96 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 200932 kb
Host smart-fe7e18d2-d7b4-4698-abc9-ab5b143b42ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058497325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3058497325
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.1207783747
Short name T26
Test name
Test status
Simulation time 336143307 ps
CPU time 1.59 seconds
Started Jul 10 05:12:26 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 216372 kb
Host smart-0f956774-9a78-47af-b272-b3812e947a4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207783747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1207783747
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2279010351
Short name T286
Test name
Test status
Simulation time 284229518 ps
CPU time 1.39 seconds
Started Jul 10 05:12:26 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 200404 kb
Host smart-17dc7612-5af6-4661-b5a4-9976aa3cef53
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279010351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.2279010351
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1769601588
Short name T23
Test name
Test status
Simulation time 1239515848 ps
CPU time 2.21 seconds
Started Jul 10 05:12:30 PM PDT 24
Finished Jul 10 05:12:34 PM PDT 24
Peak memory 200772 kb
Host smart-4f63bcd3-1225-48bd-8e57-ff9f52572ec3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769601588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1769601588
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.247316733
Short name T757
Test name
Test status
Simulation time 1004819695 ps
CPU time 2.41 seconds
Started Jul 10 05:12:28 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 200880 kb
Host smart-fcb56d8b-1e65-476c-8aff-a52ae7ca1495
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247316733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.247316733
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3269663153
Short name T241
Test name
Test status
Simulation time 99935967 ps
CPU time 0.82 seconds
Started Jul 10 05:12:28 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 199092 kb
Host smart-53e77cdc-a2e6-4686-8c50-51ddf69dd120
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269663153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3269663153
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2962168817
Short name T515
Test name
Test status
Simulation time 40528305 ps
CPU time 0.67 seconds
Started Jul 10 05:12:21 PM PDT 24
Finished Jul 10 05:12:23 PM PDT 24
Peak memory 199080 kb
Host smart-ea9672d5-92ff-4b22-86ad-631ad5d35145
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962168817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2962168817
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.1426845734
Short name T251
Test name
Test status
Simulation time 355601816 ps
CPU time 0.93 seconds
Started Jul 10 05:12:31 PM PDT 24
Finished Jul 10 05:12:33 PM PDT 24
Peak memory 200132 kb
Host smart-9dc6b0ff-cc4f-4c0a-be79-0bc026d5d623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426845734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1426845734
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.843604381
Short name T564
Test name
Test status
Simulation time 6631274911 ps
CPU time 7.96 seconds
Started Jul 10 05:12:26 PM PDT 24
Finished Jul 10 05:12:36 PM PDT 24
Peak memory 201056 kb
Host smart-c5398298-6051-4bf0-9da2-561a161eaada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843604381 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.843604381
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.2114949982
Short name T293
Test name
Test status
Simulation time 819234543 ps
CPU time 0.87 seconds
Started Jul 10 05:12:28 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 199408 kb
Host smart-9f605fa3-d72a-4cce-8b9c-5fcc01e0afe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114949982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2114949982
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.4158023903
Short name T756
Test name
Test status
Simulation time 168724761 ps
CPU time 1.09 seconds
Started Jul 10 05:12:29 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 199636 kb
Host smart-d8635809-d6c9-4cce-a677-30e8cddd67ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158023903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.4158023903
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2426019068
Short name T859
Test name
Test status
Simulation time 81311990 ps
CPU time 0.74 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 198324 kb
Host smart-76e7a22a-f7cf-464b-8968-7beb573e3cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426019068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2426019068
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.166004009
Short name T399
Test name
Test status
Simulation time 56751556 ps
CPU time 0.87 seconds
Started Jul 10 05:14:13 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 198896 kb
Host smart-3f845dfe-a613-4f11-8d7d-a0a5598481a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166004009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.166004009
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3228987196
Short name T797
Test name
Test status
Simulation time 61927626 ps
CPU time 0.58 seconds
Started Jul 10 05:14:13 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 197756 kb
Host smart-bfca1ddc-8611-467f-b9dd-69626da3d200
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228987196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3228987196
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.228260312
Short name T295
Test name
Test status
Simulation time 163838289 ps
CPU time 1.02 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 197796 kb
Host smart-61eba18e-2f13-480e-a698-b4f4cb25e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228260312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.228260312
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.3556671919
Short name T475
Test name
Test status
Simulation time 55662136 ps
CPU time 0.63 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 197816 kb
Host smart-62cda1db-6101-46d3-8a39-08b43f59b070
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556671919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3556671919
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.1751461547
Short name T492
Test name
Test status
Simulation time 61843953 ps
CPU time 0.63 seconds
Started Jul 10 05:14:16 PM PDT 24
Finished Jul 10 05:14:20 PM PDT 24
Peak memory 197784 kb
Host smart-229bf3af-9080-4786-8a5c-03735efe9b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751461547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1751461547
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2507100485
Short name T435
Test name
Test status
Simulation time 113014915 ps
CPU time 0.7 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 201080 kb
Host smart-cf174e8d-2cb5-4540-8a58-61f88c9cd3f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507100485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2507100485
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1624355170
Short name T213
Test name
Test status
Simulation time 344681962 ps
CPU time 0.99 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 199508 kb
Host smart-fd32a24f-26a6-46e5-8999-fdfb4acc833e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624355170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.1624355170
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.303253803
Short name T603
Test name
Test status
Simulation time 32460066 ps
CPU time 0.62 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:15 PM PDT 24
Peak memory 197908 kb
Host smart-bc6ec8f7-85f7-44ae-a0e4-c38a36b79727
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303253803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.303253803
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.507807955
Short name T494
Test name
Test status
Simulation time 156435211 ps
CPU time 0.8 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 209204 kb
Host smart-cb904912-2517-4ba0-891e-e1673390b8b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507807955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.507807955
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.2476447407
Short name T54
Test name
Test status
Simulation time 180301307 ps
CPU time 1 seconds
Started Jul 10 05:14:13 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 199960 kb
Host smart-f455cc56-1b6a-4901-8144-4b1aa7e13936
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476447407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.2476447407
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379101050
Short name T576
Test name
Test status
Simulation time 695673273 ps
CPU time 3.09 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 200920 kb
Host smart-2d8b0e32-59c3-46d0-8cc3-4005dc2e16d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379101050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379101050
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.60278580
Short name T409
Test name
Test status
Simulation time 1014050071 ps
CPU time 2.69 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 200804 kb
Host smart-1f16c257-a64e-4a99-a0ab-d04c71b54d1d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60278580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.60278580
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2106181170
Short name T695
Test name
Test status
Simulation time 66700236 ps
CPU time 1 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 198944 kb
Host smart-37dbbb17-a44b-4d0f-8d1a-9471d5644fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106181170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2106181170
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.376116925
Short name T396
Test name
Test status
Simulation time 162762802 ps
CPU time 0.68 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 198212 kb
Host smart-0e79e120-0f52-4450-817b-574f7a92b737
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376116925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.376116925
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.3585538945
Short name T281
Test name
Test status
Simulation time 277538208 ps
CPU time 1.56 seconds
Started Jul 10 05:14:13 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 200888 kb
Host smart-30a3e753-c308-404a-b4e6-fe6b47b3f617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585538945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3585538945
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.208854713
Short name T45
Test name
Test status
Simulation time 7569277180 ps
CPU time 28.46 seconds
Started Jul 10 05:14:15 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 201064 kb
Host smart-2d48906a-165d-4ac9-97b6-64a73c72feec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208854713 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.208854713
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.1806680590
Short name T194
Test name
Test status
Simulation time 228413111 ps
CPU time 1 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 199184 kb
Host smart-16a5dc2f-0b28-4000-8e41-55ce365a2cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806680590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.1806680590
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.1399696595
Short name T190
Test name
Test status
Simulation time 359560143 ps
CPU time 1.01 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 200636 kb
Host smart-6028a9d8-fb9e-41f8-bfcc-f79351477ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399696595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1399696595
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.921101079
Short name T270
Test name
Test status
Simulation time 60440454 ps
CPU time 0.84 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 199840 kb
Host smart-30fa3110-1546-4ab4-9084-87ce45f94c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921101079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.921101079
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1178798246
Short name T166
Test name
Test status
Simulation time 73698171 ps
CPU time 0.75 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 198808 kb
Host smart-c601cf1f-143c-4dda-9dce-0aa5445c979f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178798246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1178798246
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.793906675
Short name T365
Test name
Test status
Simulation time 37246603 ps
CPU time 0.61 seconds
Started Jul 10 05:14:19 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 197736 kb
Host smart-d826f047-7e5e-4a2f-8e43-24f30d8650f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793906675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_
malfunc.793906675
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1200395394
Short name T999
Test name
Test status
Simulation time 160620576 ps
CPU time 0.94 seconds
Started Jul 10 05:14:18 PM PDT 24
Finished Jul 10 05:14:22 PM PDT 24
Peak memory 197832 kb
Host smart-0bddd8bb-e306-4b5d-83ef-5caaae422bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200395394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1200395394
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1933003127
Short name T428
Test name
Test status
Simulation time 39193027 ps
CPU time 0.59 seconds
Started Jul 10 05:14:18 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 197744 kb
Host smart-ddd84123-e46c-4c3e-9546-64c3c8fc74cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933003127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1933003127
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.398333355
Short name T501
Test name
Test status
Simulation time 58445527 ps
CPU time 0.59 seconds
Started Jul 10 05:14:13 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 197784 kb
Host smart-7eb9035d-7db3-4059-bf9a-aa5fc7a318ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398333355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.398333355
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2909629978
Short name T337
Test name
Test status
Simulation time 43120429 ps
CPU time 0.73 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 201076 kb
Host smart-bd559062-4191-428f-8d66-f3a10547a098
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909629978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2909629978
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.935996307
Short name T327
Test name
Test status
Simulation time 292955538 ps
CPU time 0.9 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 199360 kb
Host smart-83067937-25e3-47f5-9dcd-8c72cb008d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935996307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wa
keup_race.935996307
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.2070058881
Short name T189
Test name
Test status
Simulation time 80684880 ps
CPU time 0.8 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 198752 kb
Host smart-fe1cbc1e-ea47-40fc-a785-9bc0b92bdb21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070058881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2070058881
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1513487191
Short name T751
Test name
Test status
Simulation time 263490753 ps
CPU time 0.83 seconds
Started Jul 10 05:14:18 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 209436 kb
Host smart-5344da19-9285-4dfd-83e4-8ca92142b965
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513487191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1513487191
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.201278277
Short name T908
Test name
Test status
Simulation time 75141171 ps
CPU time 0.68 seconds
Started Jul 10 05:14:20 PM PDT 24
Finished Jul 10 05:14:24 PM PDT 24
Peak memory 198252 kb
Host smart-f85ea8bb-de25-4078-83e2-ac98eff53509
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201278277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_c
m_ctrl_config_regwen.201278277
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.839045560
Short name T231
Test name
Test status
Simulation time 2369182080 ps
CPU time 2.03 seconds
Started Jul 10 05:14:11 PM PDT 24
Finished Jul 10 05:14:16 PM PDT 24
Peak memory 200680 kb
Host smart-82125250-2506-4c16-9d0b-55e08ea72f9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839045560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.839045560
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2366873758
Short name T446
Test name
Test status
Simulation time 1009742307 ps
CPU time 2.64 seconds
Started Jul 10 05:14:16 PM PDT 24
Finished Jul 10 05:14:22 PM PDT 24
Peak memory 200800 kb
Host smart-ebeefe0e-5172-4fa3-83a0-556051a4b121
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366873758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2366873758
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3037546752
Short name T861
Test name
Test status
Simulation time 66963278 ps
CPU time 0.93 seconds
Started Jul 10 05:14:15 PM PDT 24
Finished Jul 10 05:14:19 PM PDT 24
Peak memory 198924 kb
Host smart-bdd653cc-846e-4e8a-8c30-9ad8b9586b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037546752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3037546752
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3590597857
Short name T709
Test name
Test status
Simulation time 38260431 ps
CPU time 0.67 seconds
Started Jul 10 05:14:14 PM PDT 24
Finished Jul 10 05:14:18 PM PDT 24
Peak memory 199100 kb
Host smart-97c3cc99-a9df-4f70-8ee7-6011f24c82b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590597857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3590597857
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.3318651378
Short name T580
Test name
Test status
Simulation time 1030081609 ps
CPU time 2.25 seconds
Started Jul 10 05:14:16 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 200952 kb
Host smart-1991eb70-34e9-4f16-b70a-2326859c7408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318651378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3318651378
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.1653510495
Short name T703
Test name
Test status
Simulation time 17950420354 ps
CPU time 21.99 seconds
Started Jul 10 05:14:15 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 201096 kb
Host smart-c2e175d8-d8f0-42d9-b80b-1e33acbcf33c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653510495 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.1653510495
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.3278768021
Short name T820
Test name
Test status
Simulation time 148672949 ps
CPU time 0.99 seconds
Started Jul 10 05:14:10 PM PDT 24
Finished Jul 10 05:14:12 PM PDT 24
Peak memory 198052 kb
Host smart-50841bad-6428-4b6b-9ac0-5ab5ac98c325
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278768021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3278768021
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.3313625740
Short name T882
Test name
Test status
Simulation time 268407652 ps
CPU time 1.36 seconds
Started Jul 10 05:14:12 PM PDT 24
Finished Jul 10 05:14:17 PM PDT 24
Peak memory 199636 kb
Host smart-3f6d99aa-d08b-4d8b-b51c-a29e65d6146b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313625740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3313625740
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.343217603
Short name T99
Test name
Test status
Simulation time 30652974 ps
CPU time 0.81 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 198524 kb
Host smart-c9061b58-0e2f-4813-b925-8fec8c3be2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343217603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.343217603
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2920150884
Short name T712
Test name
Test status
Simulation time 56473628 ps
CPU time 0.83 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 198844 kb
Host smart-231b5abd-7e07-4bb5-a17d-f4e223281848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920150884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.2920150884
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.947373525
Short name T759
Test name
Test status
Simulation time 37478372 ps
CPU time 0.65 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 197736 kb
Host smart-5ea90401-b773-4fc3-8fb8-20ff71ec42d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947373525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.947373525
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.796944333
Short name T822
Test name
Test status
Simulation time 378517449 ps
CPU time 1.03 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 198120 kb
Host smart-5edd1e73-5caa-412b-87f1-89bb1d248b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796944333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.796944333
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.895240638
Short name T19
Test name
Test status
Simulation time 50509664 ps
CPU time 0.64 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 197728 kb
Host smart-9c5274d2-0705-4cd1-a096-53db2861723d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895240638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.895240638
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.932412875
Short name T570
Test name
Test status
Simulation time 38738707 ps
CPU time 0.67 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:31 PM PDT 24
Peak memory 197780 kb
Host smart-86c348d0-db4a-4b9c-b908-826a92bdd9c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932412875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.932412875
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3141676902
Short name T873
Test name
Test status
Simulation time 45633548 ps
CPU time 0.82 seconds
Started Jul 10 05:14:19 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 201040 kb
Host smart-f198a075-2891-46f0-8c8d-cd7d8526fd06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141676902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3141676902
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.571568433
Short name T183
Test name
Test status
Simulation time 143421613 ps
CPU time 0.99 seconds
Started Jul 10 05:14:18 PM PDT 24
Finished Jul 10 05:14:22 PM PDT 24
Peak memory 198292 kb
Host smart-7e73891c-4242-4943-8866-3d7fdfd167d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571568433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wa
keup_race.571568433
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1760529819
Short name T217
Test name
Test status
Simulation time 103752378 ps
CPU time 0.73 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 198828 kb
Host smart-afee4de7-e731-4bdb-a9ea-fe20e04ca554
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760529819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1760529819
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.368674044
Short name T313
Test name
Test status
Simulation time 109532774 ps
CPU time 0.93 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:31 PM PDT 24
Peak memory 209212 kb
Host smart-1dffa40a-f8e2-4fc1-91af-c392df22cda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368674044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.368674044
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.538109526
Short name T219
Test name
Test status
Simulation time 107747629 ps
CPU time 0.77 seconds
Started Jul 10 05:14:19 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 198836 kb
Host smart-33ac01ee-039c-441f-b873-e46e72e5a880
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538109526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_c
m_ctrl_config_regwen.538109526
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3881803445
Short name T865
Test name
Test status
Simulation time 745173630 ps
CPU time 3.09 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:33 PM PDT 24
Peak memory 200812 kb
Host smart-93fc9f93-24a2-4501-8882-40cf931bfb79
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881803445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3881803445
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1002066173
Short name T554
Test name
Test status
Simulation time 920332167 ps
CPU time 3.56 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:24 PM PDT 24
Peak memory 200960 kb
Host smart-80727805-de30-40d0-b08c-8f5a0c6fb0f9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002066173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1002066173
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3920245449
Short name T372
Test name
Test status
Simulation time 61725989 ps
CPU time 0.85 seconds
Started Jul 10 05:14:20 PM PDT 24
Finished Jul 10 05:14:24 PM PDT 24
Peak memory 198848 kb
Host smart-8c56bdee-1311-4e1c-8c4f-360b09162ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920245449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3920245449
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1149534867
Short name T988
Test name
Test status
Simulation time 30649804 ps
CPU time 0.67 seconds
Started Jul 10 05:14:19 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 199048 kb
Host smart-785726cd-5ea6-4dfc-8123-1162aaf74724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149534867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1149534867
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.3758924443
Short name T98
Test name
Test status
Simulation time 2555895397 ps
CPU time 3.74 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:23 PM PDT 24
Peak memory 200948 kb
Host smart-c80da966-0ee7-4885-890e-5e24d29a9a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758924443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3758924443
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.1156730353
Short name T351
Test name
Test status
Simulation time 7276326941 ps
CPU time 23.57 seconds
Started Jul 10 05:14:19 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 201000 kb
Host smart-736a2710-6651-4961-8df3-8b136c5479a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156730353 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.1156730353
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.2239675182
Short name T387
Test name
Test status
Simulation time 29975124 ps
CPU time 0.67 seconds
Started Jul 10 05:14:15 PM PDT 24
Finished Jul 10 05:14:19 PM PDT 24
Peak memory 198800 kb
Host smart-8202436a-a05d-4902-8003-30918a1217a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239675182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.2239675182
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.2519769038
Short name T531
Test name
Test status
Simulation time 443535976 ps
CPU time 1.08 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:21 PM PDT 24
Peak memory 200644 kb
Host smart-66aa2de0-78fb-4159-947c-ccb7e234a9b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519769038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2519769038
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.28167556
Short name T519
Test name
Test status
Simulation time 20908340 ps
CPU time 0.62 seconds
Started Jul 10 05:14:22 PM PDT 24
Finished Jul 10 05:14:25 PM PDT 24
Peak memory 198308 kb
Host smart-3bd89dba-bb24-42fe-81c5-fd9b25ab2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28167556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.28167556
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.4203497346
Short name T735
Test name
Test status
Simulation time 76971621 ps
CPU time 0.73 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 198844 kb
Host smart-d7db4286-88d0-404f-93a9-cdcafa600469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203497346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.4203497346
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.4283011689
Short name T801
Test name
Test status
Simulation time 33338319 ps
CPU time 0.6 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:26 PM PDT 24
Peak memory 197724 kb
Host smart-5d642ce7-83de-49ef-a8f3-e49d95ec58e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283011689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.4283011689
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.175317133
Short name T284
Test name
Test status
Simulation time 678192249 ps
CPU time 0.92 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 198052 kb
Host smart-d49ad76e-f64a-40cd-bcc9-84b609f78b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175317133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.175317133
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3129359589
Short name T792
Test name
Test status
Simulation time 47585471 ps
CPU time 0.59 seconds
Started Jul 10 05:14:28 PM PDT 24
Finished Jul 10 05:14:33 PM PDT 24
Peak memory 197732 kb
Host smart-3ac77c96-e7f2-4e3a-9bdd-0761fb016031
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129359589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3129359589
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1265124599
Short name T132
Test name
Test status
Simulation time 33185725 ps
CPU time 0.65 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 197764 kb
Host smart-00e39932-e805-4f31-ba0f-6f45e828a71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265124599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1265124599
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.542145059
Short name T212
Test name
Test status
Simulation time 75186265 ps
CPU time 0.7 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 201068 kb
Host smart-f45c279a-ea1f-47b8-ae95-f31d8d087fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542145059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invali
d.542145059
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.995758810
Short name T718
Test name
Test status
Simulation time 226963581 ps
CPU time 0.89 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:28 PM PDT 24
Peak memory 199368 kb
Host smart-a42a8500-303d-4da5-b7e7-c7c9efdffa6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995758810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wa
keup_race.995758810
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2127767631
Short name T578
Test name
Test status
Simulation time 44935144 ps
CPU time 0.74 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:31 PM PDT 24
Peak memory 198860 kb
Host smart-aa0b729a-9533-46a1-939f-bc8e62939db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127767631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2127767631
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1640460647
Short name T875
Test name
Test status
Simulation time 93142321 ps
CPU time 1.04 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 209268 kb
Host smart-b3a164fd-3593-4569-b53a-8675c9344b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640460647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1640460647
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.379350841
Short name T584
Test name
Test status
Simulation time 423651518 ps
CPU time 0.96 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 199956 kb
Host smart-4f4dbc06-09ec-43e5-9705-eeccf520ec8d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379350841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_c
m_ctrl_config_regwen.379350841
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1291865501
Short name T810
Test name
Test status
Simulation time 1236738837 ps
CPU time 1.9 seconds
Started Jul 10 05:14:21 PM PDT 24
Finished Jul 10 05:14:26 PM PDT 24
Peak memory 200868 kb
Host smart-00f47e6b-57cd-4b11-bb0b-01eb4e6d6f85
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291865501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1291865501
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3283388084
Short name T942
Test name
Test status
Simulation time 1486376591 ps
CPU time 1.9 seconds
Started Jul 10 05:14:21 PM PDT 24
Finished Jul 10 05:14:25 PM PDT 24
Peak memory 200864 kb
Host smart-2d811f68-2afe-4b01-a93e-21163f12a0b9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283388084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3283388084
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.831104529
Short name T872
Test name
Test status
Simulation time 243059278 ps
CPU time 0.85 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 199052 kb
Host smart-83476837-e79e-4dee-b328-d5037d8722d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831104529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_
mubi.831104529
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.93494539
Short name T540
Test name
Test status
Simulation time 179224876 ps
CPU time 0.64 seconds
Started Jul 10 05:14:17 PM PDT 24
Finished Jul 10 05:14:20 PM PDT 24
Peak memory 198216 kb
Host smart-f801ad26-1262-4360-8a93-d4aa22b8d755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93494539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.93494539
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.3443779377
Short name T346
Test name
Test status
Simulation time 331600787 ps
CPU time 1.67 seconds
Started Jul 10 05:14:22 PM PDT 24
Finished Jul 10 05:14:26 PM PDT 24
Peak memory 200632 kb
Host smart-1671eac2-c069-469b-a153-4b1bf8ecdafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443779377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.3443779377
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1265410454
Short name T119
Test name
Test status
Simulation time 24428618769 ps
CPU time 21.24 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 201020 kb
Host smart-d84a1549-a48b-4c86-bf8a-21a68e17dc99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265410454 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1265410454
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.4088168641
Short name T879
Test name
Test status
Simulation time 279133595 ps
CPU time 1.29 seconds
Started Jul 10 05:14:21 PM PDT 24
Finished Jul 10 05:14:25 PM PDT 24
Peak memory 199436 kb
Host smart-e46284c4-9bae-446f-8e5b-527aa7437cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088168641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.4088168641
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.1127612839
Short name T411
Test name
Test status
Simulation time 162168980 ps
CPU time 0.82 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 199032 kb
Host smart-4455337e-b726-47c8-ab1a-3613786a51a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127612839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.1127612839
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2243080557
Short name T977
Test name
Test status
Simulation time 41592453 ps
CPU time 0.7 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:28 PM PDT 24
Peak memory 198816 kb
Host smart-a3ffa414-1fb4-4917-8b7f-78c83795c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243080557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2243080557
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2521703212
Short name T165
Test name
Test status
Simulation time 73587435 ps
CPU time 0.75 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:35 PM PDT 24
Peak memory 198700 kb
Host smart-c9abf029-d8ab-4796-a61f-70aff9c4f8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521703212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2521703212
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.963383503
Short name T760
Test name
Test status
Simulation time 29659901 ps
CPU time 0.69 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:31 PM PDT 24
Peak memory 197660 kb
Host smart-c49afc30-4da5-429f-b009-e299c39b083b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963383503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_
malfunc.963383503
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3720778454
Short name T142
Test name
Test status
Simulation time 322785156 ps
CPU time 0.93 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 198104 kb
Host smart-b240c7a7-9172-41ae-a12f-cceab556d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720778454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3720778454
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.528253957
Short name T945
Test name
Test status
Simulation time 166732778 ps
CPU time 0.62 seconds
Started Jul 10 05:14:31 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 197768 kb
Host smart-f45216d2-25ab-4748-813b-135ca1c4cbe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528253957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.528253957
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2704814203
Short name T937
Test name
Test status
Simulation time 63553977 ps
CPU time 0.62 seconds
Started Jul 10 05:14:27 PM PDT 24
Finished Jul 10 05:14:32 PM PDT 24
Peak memory 197796 kb
Host smart-a944fdfd-a6ba-47a1-9303-6c9eb5db0022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704814203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2704814203
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.974860160
Short name T795
Test name
Test status
Simulation time 100708927 ps
CPU time 0.69 seconds
Started Jul 10 05:14:28 PM PDT 24
Finished Jul 10 05:14:33 PM PDT 24
Peak memory 201076 kb
Host smart-83d3d6bb-c85c-4504-a53b-70bd295d2daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974860160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invali
d.974860160
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.1303601323
Short name T743
Test name
Test status
Simulation time 414991543 ps
CPU time 0.97 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 199568 kb
Host smart-e6f94a68-1f68-4c53-85c4-39ad0fd7e154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303601323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.1303601323
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1577953758
Short name T185
Test name
Test status
Simulation time 63071392 ps
CPU time 0.76 seconds
Started Jul 10 05:14:28 PM PDT 24
Finished Jul 10 05:14:33 PM PDT 24
Peak memory 198248 kb
Host smart-0a31c41d-764f-41aa-8229-dba7befc67dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577953758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1577953758
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.22761413
Short name T589
Test name
Test status
Simulation time 136821094 ps
CPU time 0.87 seconds
Started Jul 10 05:14:25 PM PDT 24
Finished Jul 10 05:14:29 PM PDT 24
Peak memory 209240 kb
Host smart-2f2149e0-175e-4e77-b981-e9cba4c1a83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22761413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.22761413
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.3579083637
Short name T452
Test name
Test status
Simulation time 255131904 ps
CPU time 1.29 seconds
Started Jul 10 05:14:27 PM PDT 24
Finished Jul 10 05:14:32 PM PDT 24
Peak memory 199956 kb
Host smart-26071225-5831-4e66-a05b-206332838a47
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579083637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.3579083637
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.860885841
Short name T964
Test name
Test status
Simulation time 893650095 ps
CPU time 3.19 seconds
Started Jul 10 05:14:24 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 200896 kb
Host smart-9c788c89-f0f7-47cd-a71a-cb5ae05d961b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860885841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.860885841
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2302983403
Short name T927
Test name
Test status
Simulation time 788277227 ps
CPU time 3.19 seconds
Started Jul 10 05:14:22 PM PDT 24
Finished Jul 10 05:14:28 PM PDT 24
Peak memory 200700 kb
Host smart-e7f8ddb9-39ca-45e7-a781-b22dca9aa19c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302983403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2302983403
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2410979555
Short name T289
Test name
Test status
Simulation time 75541968 ps
CPU time 1 seconds
Started Jul 10 05:14:27 PM PDT 24
Finished Jul 10 05:14:32 PM PDT 24
Peak memory 199004 kb
Host smart-e7628bee-3370-481e-8785-abd539b47536
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410979555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2410979555
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1546341815
Short name T768
Test name
Test status
Simulation time 31614243 ps
CPU time 0.73 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 199084 kb
Host smart-80a2c2fd-2758-4515-bf74-0bdfe2e5af87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546341815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1546341815
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.1964156418
Short name T77
Test name
Test status
Simulation time 2080151467 ps
CPU time 4.82 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:43 PM PDT 24
Peak memory 200928 kb
Host smart-35c4cd21-174a-4c67-8e9a-43441219ca86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964156418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1964156418
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2278720884
Short name T85
Test name
Test status
Simulation time 7657999756 ps
CPU time 17.05 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 201064 kb
Host smart-486db0cd-9b4b-4b34-a016-dc91b9d7cc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278720884 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.2278720884
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.2885229938
Short name T402
Test name
Test status
Simulation time 230777273 ps
CPU time 0.68 seconds
Started Jul 10 05:14:23 PM PDT 24
Finished Jul 10 05:14:26 PM PDT 24
Peak memory 198832 kb
Host smart-38cc8b38-8681-4207-8563-b71801babe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885229938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.2885229938
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.1048321021
Short name T171
Test name
Test status
Simulation time 199692905 ps
CPU time 0.94 seconds
Started Jul 10 05:14:21 PM PDT 24
Finished Jul 10 05:14:25 PM PDT 24
Peak memory 199572 kb
Host smart-c83bfbe8-d216-40cc-9bd3-721a51747bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048321021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1048321021
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.652620316
Short name T116
Test name
Test status
Simulation time 48737519 ps
CPU time 0.76 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 198360 kb
Host smart-34123966-98da-4b36-811a-aa18e92f11fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652620316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.652620316
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.236051727
Short name T947
Test name
Test status
Simulation time 94476971 ps
CPU time 0.71 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 198816 kb
Host smart-4f8d78ba-5474-4942-8af8-605a9ac90153
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236051727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.236051727
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.2159318552
Short name T976
Test name
Test status
Simulation time 30015085 ps
CPU time 0.73 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 197644 kb
Host smart-9e8111c9-5eaa-4338-8bb7-a01e40a4ef39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159318552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.2159318552
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3272078363
Short name T663
Test name
Test status
Simulation time 632504721 ps
CPU time 0.97 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 198104 kb
Host smart-56cf7bda-9896-4df6-aad9-ffae81a714b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272078363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3272078363
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1575008343
Short name T864
Test name
Test status
Simulation time 35860629 ps
CPU time 0.63 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 197560 kb
Host smart-c8386b63-303c-4836-a98d-254f94054563
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575008343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1575008343
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3996073045
Short name T806
Test name
Test status
Simulation time 39108904 ps
CPU time 0.62 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 198024 kb
Host smart-bf7aa228-7a83-495a-ad36-42b3bf981900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996073045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3996073045
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2001879767
Short name T736
Test name
Test status
Simulation time 100249617 ps
CPU time 0.66 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 201072 kb
Host smart-41364ccc-dbee-404d-a76c-7eefe5896c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001879767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.2001879767
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2999937895
Short name T193
Test name
Test status
Simulation time 165425625 ps
CPU time 0.98 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198236 kb
Host smart-af9af294-4b02-4d6b-95c4-c6c83eefb0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999937895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2999937895
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.997811241
Short name T730
Test name
Test status
Simulation time 38703707 ps
CPU time 0.72 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 198728 kb
Host smart-0505a8b0-0629-4658-a923-b552d1bfa5eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997811241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.997811241
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.3499564920
Short name T585
Test name
Test status
Simulation time 184783263 ps
CPU time 0.83 seconds
Started Jul 10 05:14:26 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 209476 kb
Host smart-d8650a8e-2c98-4886-93da-cc1a25103a6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499564920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3499564920
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3216295400
Short name T571
Test name
Test status
Simulation time 330292544 ps
CPU time 0.87 seconds
Started Jul 10 05:14:29 PM PDT 24
Finished Jul 10 05:14:34 PM PDT 24
Peak memory 199584 kb
Host smart-80c97d33-e147-41e8-9110-b85770f15158
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216295400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.3216295400
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1382238654
Short name T691
Test name
Test status
Simulation time 1243569493 ps
CPU time 2.42 seconds
Started Jul 10 05:14:31 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 200904 kb
Host smart-88b8af3e-c1f6-48f4-9499-51b2f0e28056
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382238654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1382238654
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445635636
Short name T175
Test name
Test status
Simulation time 1059652426 ps
CPU time 2.47 seconds
Started Jul 10 05:14:28 PM PDT 24
Finished Jul 10 05:14:34 PM PDT 24
Peak memory 200856 kb
Host smart-62d5192f-e706-46a5-90ec-d9103a76bfc3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445635636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445635636
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3647610337
Short name T903
Test name
Test status
Simulation time 72136368 ps
CPU time 0.95 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 199260 kb
Host smart-361872e4-5867-4ae1-b0b1-013427fb95f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647610337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3647610337
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2382733484
Short name T259
Test name
Test status
Simulation time 39280736 ps
CPU time 0.65 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:39 PM PDT 24
Peak memory 198264 kb
Host smart-73a374ae-893f-4bb4-8c03-afe2dc20a997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382733484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2382733484
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.290321476
Short name T813
Test name
Test status
Simulation time 2913656098 ps
CPU time 4.7 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 200928 kb
Host smart-d635884c-7487-44a3-bddb-ef3af3654ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290321476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.290321476
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.2582835964
Short name T835
Test name
Test status
Simulation time 8530632914 ps
CPU time 10.78 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 201088 kb
Host smart-e9069039-6eee-4a3c-bdd3-7efa4a37c0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582835964 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.2582835964
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.1608089965
Short name T186
Test name
Test status
Simulation time 137260599 ps
CPU time 0.88 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 198256 kb
Host smart-196cca52-2960-4f53-ae9a-2cd8f37b079e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608089965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1608089965
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.2464359456
Short name T568
Test name
Test status
Simulation time 709418107 ps
CPU time 0.88 seconds
Started Jul 10 05:14:30 PM PDT 24
Finished Jul 10 05:14:35 PM PDT 24
Peak memory 199900 kb
Host smart-6c35108a-b8b9-4752-9377-93bcf5d88041
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464359456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2464359456
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3816198765
Short name T655
Test name
Test status
Simulation time 33280212 ps
CPU time 0.8 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 199408 kb
Host smart-96827f06-552a-4587-9bf1-e056af747bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816198765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3816198765
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.4137492301
Short name T153
Test name
Test status
Simulation time 73655301 ps
CPU time 0.95 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 198812 kb
Host smart-7ab35de9-1ccb-4285-a42e-563e2204a167
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137492301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.4137492301
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1963874309
Short name T781
Test name
Test status
Simulation time 29631703 ps
CPU time 0.64 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 197060 kb
Host smart-b2484e99-1c97-4e0f-a2c9-4b1c3c4b7c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963874309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.1963874309
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.956967190
Short name T502
Test name
Test status
Simulation time 633260095 ps
CPU time 0.97 seconds
Started Jul 10 05:14:36 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 198096 kb
Host smart-9c3c87d8-dbb9-4d88-893b-8013f6e0aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956967190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.956967190
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.1537734812
Short name T763
Test name
Test status
Simulation time 47240507 ps
CPU time 0.65 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 197704 kb
Host smart-ee2c5265-1d66-4543-b8e0-35b819281039
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537734812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1537734812
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2894197093
Short name T209
Test name
Test status
Simulation time 24414635 ps
CPU time 0.61 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:39 PM PDT 24
Peak memory 197704 kb
Host smart-96c2fbb7-3416-4e5e-8af4-81ace949b41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894197093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2894197093
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3006828305
Short name T753
Test name
Test status
Simulation time 78223226 ps
CPU time 0.66 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 200980 kb
Host smart-b55959f7-e63d-45df-aad6-72ae29b06695
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006828305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3006828305
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.2954920649
Short name T403
Test name
Test status
Simulation time 119543120 ps
CPU time 0.67 seconds
Started Jul 10 05:14:31 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 198012 kb
Host smart-33a890f4-a212-4916-9e75-b943297fb53a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954920649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.2954920649
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2826463170
Short name T726
Test name
Test status
Simulation time 90890694 ps
CPU time 0.88 seconds
Started Jul 10 05:14:27 PM PDT 24
Finished Jul 10 05:14:31 PM PDT 24
Peak memory 199588 kb
Host smart-20fbb8b4-65ce-46af-a904-513cbe58289f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826463170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2826463170
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.206406332
Short name T316
Test name
Test status
Simulation time 114894243 ps
CPU time 0.92 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 209256 kb
Host smart-e7801446-44e0-4536-84bf-bc2c130521df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206406332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.206406332
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1593973516
Short name T240
Test name
Test status
Simulation time 467459882 ps
CPU time 0.73 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:37 PM PDT 24
Peak memory 198288 kb
Host smart-cb0c878d-0a20-468a-ba7e-08541fa4ac6b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593973516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.1593973516
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1505740560
Short name T604
Test name
Test status
Simulation time 1282209273 ps
CPU time 2.3 seconds
Started Jul 10 05:14:29 PM PDT 24
Finished Jul 10 05:14:36 PM PDT 24
Peak memory 200860 kb
Host smart-d70d3e29-5bdb-4554-aa52-66a7598d9dcd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505740560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1505740560
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3589063959
Short name T278
Test name
Test status
Simulation time 885359490 ps
CPU time 3.35 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 200796 kb
Host smart-b572fe42-8f8b-44a3-98f2-ac8056819438
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589063959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3589063959
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2562683664
Short name T876
Test name
Test status
Simulation time 51818500 ps
CPU time 0.88 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 199336 kb
Host smart-15c73e6f-53ec-49f0-bd93-349aeac8b3bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562683664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2562683664
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3480215741
Short name T868
Test name
Test status
Simulation time 35707523 ps
CPU time 0.71 seconds
Started Jul 10 05:14:29 PM PDT 24
Finished Jul 10 05:14:34 PM PDT 24
Peak memory 198160 kb
Host smart-f73243f0-8557-459f-a897-a65d45c6fdb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480215741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3480215741
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.737632055
Short name T714
Test name
Test status
Simulation time 735195277 ps
CPU time 2.74 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 200844 kb
Host smart-efcaa0d8-3dfc-4ae2-9fd9-e3897476287a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737632055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.737632055
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1354430013
Short name T826
Test name
Test status
Simulation time 12781626430 ps
CPU time 28.08 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:15:23 PM PDT 24
Peak memory 200964 kb
Host smart-f8696c9f-1b85-404e-9ae1-4581db389e25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354430013 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.1354430013
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.2884165585
Short name T522
Test name
Test status
Simulation time 192801479 ps
CPU time 0.84 seconds
Started Jul 10 05:14:31 PM PDT 24
Finished Jul 10 05:14:37 PM PDT 24
Peak memory 198312 kb
Host smart-e97c6c73-e73d-4443-8fdb-efcc8799fb70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884165585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.2884165585
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.1094420839
Short name T546
Test name
Test status
Simulation time 53581489 ps
CPU time 0.75 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 198984 kb
Host smart-da4302c9-5603-4899-bb45-b3a7483c477b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094420839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.1094420839
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.2574359708
Short name T529
Test name
Test status
Simulation time 27544491 ps
CPU time 0.88 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 199864 kb
Host smart-7c5a18fa-fb4b-4499-b3a9-cd2948354c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574359708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2574359708
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.562036630
Short name T299
Test name
Test status
Simulation time 68023153 ps
CPU time 0.72 seconds
Started Jul 10 05:14:36 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 198352 kb
Host smart-fefbac41-fe86-43f4-b6ed-97a09236e80d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562036630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.562036630
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1740397242
Short name T688
Test name
Test status
Simulation time 29698193 ps
CPU time 0.65 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 197732 kb
Host smart-f9f8f233-b8a6-49a7-a080-016a94083b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740397242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1740397242
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1511935371
Short name T434
Test name
Test status
Simulation time 664609381 ps
CPU time 0.97 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 198120 kb
Host smart-9afbe35a-bcc6-4175-9069-113f24ff92b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511935371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1511935371
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.980992910
Short name T684
Test name
Test status
Simulation time 73882517 ps
CPU time 0.62 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 197028 kb
Host smart-0b96e378-cabb-4d85-adbe-4f83f0ab296b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980992910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.980992910
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.419420561
Short name T869
Test name
Test status
Simulation time 95389920 ps
CPU time 0.63 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 197784 kb
Host smart-e28d4186-b66c-4e91-b624-204142d658a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419420561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.419420561
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3430914515
Short name T294
Test name
Test status
Simulation time 65206315 ps
CPU time 0.66 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 201060 kb
Host smart-f0bdd7f3-137b-4136-85e1-539dfcc02720
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430914515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3430914515
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.723353072
Short name T178
Test name
Test status
Simulation time 249516331 ps
CPU time 0.85 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198304 kb
Host smart-c1d5c41f-41d2-4dce-a0bc-da0910c7dd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723353072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wa
keup_race.723353072
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2998088127
Short name T896
Test name
Test status
Simulation time 311452641 ps
CPU time 0.83 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:39 PM PDT 24
Peak memory 199444 kb
Host smart-ce357c8a-2872-4277-a1e5-5d82d7e4ad11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998088127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2998088127
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.2654185780
Short name T547
Test name
Test status
Simulation time 95170024 ps
CPU time 0.89 seconds
Started Jul 10 05:14:31 PM PDT 24
Finished Jul 10 05:14:37 PM PDT 24
Peak memory 209284 kb
Host smart-5480621e-080b-49b5-ab4a-262aed166f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654185780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2654185780
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.249959707
Short name T541
Test name
Test status
Simulation time 373319113 ps
CPU time 1.04 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 199904 kb
Host smart-ab520b00-48ad-4e65-9ad8-aa644c5822d4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249959707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_c
m_ctrl_config_regwen.249959707
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1226650875
Short name T981
Test name
Test status
Simulation time 830256196 ps
CPU time 3.12 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 200944 kb
Host smart-a24eb127-a8e0-43da-873d-930755264202
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226650875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1226650875
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4167222961
Short name T961
Test name
Test status
Simulation time 1462048946 ps
CPU time 2.47 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 200672 kb
Host smart-20b220fa-1464-47be-ba86-79b5a0cfe505
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167222961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4167222961
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.882517891
Short name T319
Test name
Test status
Simulation time 137535009 ps
CPU time 0.86 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 198780 kb
Host smart-d990822b-6a67-42c3-aac4-32491afd511b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882517891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.882517891
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3025374794
Short name T935
Test name
Test status
Simulation time 52935088 ps
CPU time 0.66 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 198220 kb
Host smart-c2b0ff3a-6be0-402e-accf-0fa5bdf4f0f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025374794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3025374794
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.1925626177
Short name T673
Test name
Test status
Simulation time 81712172 ps
CPU time 0.81 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 198832 kb
Host smart-c1735c29-b9fb-4654-a384-b25c070f13e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925626177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.1925626177
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4073573019
Short name T131
Test name
Test status
Simulation time 16851548477 ps
CPU time 22.21 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 201048 kb
Host smart-9256a694-a2a0-4bcb-a78e-7e31fbccf03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073573019 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.4073573019
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.2693099391
Short name T353
Test name
Test status
Simulation time 141440173 ps
CPU time 0.73 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198188 kb
Host smart-fa7e3cfa-cc57-4331-8a5a-b7afd32d37e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693099391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2693099391
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.2562753495
Short name T662
Test name
Test status
Simulation time 166431141 ps
CPU time 1.02 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 199644 kb
Host smart-d80c400f-b008-4d8e-a521-0c76a88cc25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562753495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.2562753495
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2902040474
Short name T772
Test name
Test status
Simulation time 21542503 ps
CPU time 0.81 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:39 PM PDT 24
Peak memory 198828 kb
Host smart-4865319b-5f69-4293-80c7-3d11200137a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902040474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2902040474
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.923459637
Short name T934
Test name
Test status
Simulation time 67356983 ps
CPU time 0.73 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 198316 kb
Host smart-7c880003-c5d4-4f55-8548-db8ed3d1fdfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923459637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa
ble_rom_integrity_check.923459637
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3577622691
Short name T618
Test name
Test status
Simulation time 29276692 ps
CPU time 0.67 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:38 PM PDT 24
Peak memory 197948 kb
Host smart-3b11d9c6-3237-4aaa-99d7-7d2d3d4fbff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577622691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3577622691
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.2872472547
Short name T308
Test name
Test status
Simulation time 307187727 ps
CPU time 0.94 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 197700 kb
Host smart-caf16830-6f5b-4fe3-9fe8-5d47a3b92a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872472547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2872472547
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2951215018
Short name T478
Test name
Test status
Simulation time 50542833 ps
CPU time 0.69 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 197680 kb
Host smart-9c3c819d-fc8d-4bec-b138-593390ce76b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951215018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2951215018
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3193675085
Short name T525
Test name
Test status
Simulation time 30098120 ps
CPU time 0.62 seconds
Started Jul 10 05:14:32 PM PDT 24
Finished Jul 10 05:14:37 PM PDT 24
Peak memory 197808 kb
Host smart-439e4c3f-4775-4291-ba47-84c2fb3b2d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193675085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3193675085
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.781566565
Short name T866
Test name
Test status
Simulation time 81417367 ps
CPU time 0.67 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 200968 kb
Host smart-b8c48dfb-c0bb-4268-8c93-1a52840a1cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781566565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.781566565
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2928952678
Short name T588
Test name
Test status
Simulation time 638347921 ps
CPU time 0.97 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 199496 kb
Host smart-d371d5b6-cafd-4256-8fe7-121b0beb5460
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928952678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.2928952678
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.1521534826
Short name T699
Test name
Test status
Simulation time 107302390 ps
CPU time 0.79 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:39 PM PDT 24
Peak memory 198784 kb
Host smart-273e28ba-8237-4b32-842b-ac574606fee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521534826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.1521534826
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.892267534
Short name T480
Test name
Test status
Simulation time 149012015 ps
CPU time 0.78 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 209100 kb
Host smart-b2cc6984-0c1c-4b48-be68-cfa37a96ba2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892267534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.892267534
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3532359434
Short name T619
Test name
Test status
Simulation time 287453137 ps
CPU time 0.94 seconds
Started Jul 10 05:14:36 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 199676 kb
Host smart-7d9f63f0-176f-42a8-9782-909653f47f59
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532359434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.3532359434
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.746519979
Short name T649
Test name
Test status
Simulation time 899498979 ps
CPU time 2.3 seconds
Started Jul 10 05:14:35 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 200636 kb
Host smart-ba8a0f62-89ba-413d-bde2-0644bacd8ec2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746519979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.746519979
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3920381470
Short name T538
Test name
Test status
Simulation time 1539635991 ps
CPU time 2.36 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 200836 kb
Host smart-58417acf-bd71-4a8e-8925-46f159883dfb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920381470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3920381470
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2413633398
Short name T545
Test name
Test status
Simulation time 68055082 ps
CPU time 0.84 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198940 kb
Host smart-56210ad5-5531-45f7-9cbb-09f830c70833
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413633398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2413633398
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.717844793
Short name T405
Test name
Test status
Simulation time 29068838 ps
CPU time 0.73 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 199084 kb
Host smart-3ed1dc25-8e39-4ded-a609-27b200367497
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717844793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.717844793
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.3545962148
Short name T471
Test name
Test status
Simulation time 783767511 ps
CPU time 1.82 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 200928 kb
Host smart-4ab74ad7-4b5e-4df2-b4e9-203e96667e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545962148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.3545962148
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.300343518
Short name T776
Test name
Test status
Simulation time 10765340130 ps
CPU time 23.05 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 201064 kb
Host smart-47c921ab-9d8a-4f06-a0e6-6e1f7dcb0dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300343518 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.300343518
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.537296315
Short name T557
Test name
Test status
Simulation time 178639411 ps
CPU time 0.81 seconds
Started Jul 10 05:14:33 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198788 kb
Host smart-f7e5848e-cb6d-4a7d-995e-844e9ceec1e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537296315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.537296315
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.2109988582
Short name T180
Test name
Test status
Simulation time 92591740 ps
CPU time 0.78 seconds
Started Jul 10 05:14:34 PM PDT 24
Finished Jul 10 05:14:40 PM PDT 24
Peak memory 198864 kb
Host smart-73532f7d-68a0-467a-afa4-ff802f7fdc9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109988582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.2109988582
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3524553566
Short name T96
Test name
Test status
Simulation time 80887444 ps
CPU time 0.92 seconds
Started Jul 10 05:14:37 PM PDT 24
Finished Jul 10 05:14:43 PM PDT 24
Peak memory 200524 kb
Host smart-58145ad7-64a6-4f10-a3ea-3f16f2629889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524553566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3524553566
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2764386495
Short name T24
Test name
Test status
Simulation time 63280658 ps
CPU time 0.73 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198188 kb
Host smart-928e26b9-cd3b-4bc9-bed6-0c60e69d12a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764386495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2764386495
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4202293062
Short name T833
Test name
Test status
Simulation time 36781364 ps
CPU time 0.61 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 197736 kb
Host smart-72493231-0fbc-4645-a741-c69a17f41a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202293062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.4202293062
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1363160327
Short name T370
Test name
Test status
Simulation time 158732839 ps
CPU time 1.01 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 197736 kb
Host smart-4c2dbc06-ff19-4237-8fe1-3310202c84d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363160327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1363160327
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1851685144
Short name T345
Test name
Test status
Simulation time 39474123 ps
CPU time 0.61 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 197740 kb
Host smart-78a38f9f-988f-4cd9-b7a3-fe9539203405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851685144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1851685144
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2918903938
Short name T322
Test name
Test status
Simulation time 49592685 ps
CPU time 0.71 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 197788 kb
Host smart-2725dd66-6054-4935-a219-a44c700eaa16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918903938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2918903938
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2951978620
Short name T312
Test name
Test status
Simulation time 99024218 ps
CPU time 0.67 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 201076 kb
Host smart-a87dbb9b-9157-4df3-b188-33077c855957
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951978620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2951978620
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.622388498
Short name T192
Test name
Test status
Simulation time 698913741 ps
CPU time 0.82 seconds
Started Jul 10 05:14:36 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 199400 kb
Host smart-e0f3f403-3e23-42d7-8bae-4fabae1688f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622388498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wa
keup_race.622388498
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.3626700251
Short name T633
Test name
Test status
Simulation time 83440640 ps
CPU time 0.67 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 198812 kb
Host smart-5b9fcff9-b0a0-4bf0-9a50-9a272f6c9ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626700251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3626700251
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.376090053
Short name T181
Test name
Test status
Simulation time 155697170 ps
CPU time 0.88 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 200992 kb
Host smart-e4c2f9a3-93d0-48c2-bbee-099d34d71304
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376090053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.376090053
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2752606425
Short name T317
Test name
Test status
Simulation time 237158653 ps
CPU time 1.27 seconds
Started Jul 10 05:14:37 PM PDT 24
Finished Jul 10 05:14:43 PM PDT 24
Peak memory 199956 kb
Host smart-97fc32e5-622d-4e60-b23f-470a1758d7ab
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752606425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.2752606425
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1116804945
Short name T566
Test name
Test status
Simulation time 868381544 ps
CPU time 2.89 seconds
Started Jul 10 05:14:41 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 200924 kb
Host smart-c47a4ca7-b217-48d5-93d0-3dfe29290e1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116804945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1116804945
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2823580971
Short name T331
Test name
Test status
Simulation time 1314699473 ps
CPU time 2.15 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 200772 kb
Host smart-1cc1ebf5-1219-4f7c-bac0-2a6f2016db2d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823580971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2823580971
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.325973407
Short name T350
Test name
Test status
Simulation time 89970419 ps
CPU time 0.87 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 198972 kb
Host smart-a6316995-2b63-4ed1-82e7-e9bb4b24adc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325973407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.325973407
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.974127681
Short name T911
Test name
Test status
Simulation time 30073119 ps
CPU time 0.64 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 198200 kb
Host smart-8f476fa0-8cb6-42dc-bb6f-9595fb87c470
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974127681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.974127681
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.4021864798
Short name T230
Test name
Test status
Simulation time 2390409875 ps
CPU time 3.42 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 200844 kb
Host smart-ce62f901-a240-49c3-b69e-03cdfc074616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021864798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.4021864798
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.1343711485
Short name T21
Test name
Test status
Simulation time 4071010102 ps
CPU time 14.18 seconds
Started Jul 10 05:14:41 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 201052 kb
Host smart-5e53d367-05d7-48d2-9fd2-2ec0672b05aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343711485 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.1343711485
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.138243292
Short name T37
Test name
Test status
Simulation time 305643057 ps
CPU time 1.12 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 199500 kb
Host smart-faadb094-a7b5-47a2-a77f-e272100be60c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138243292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.138243292
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.3159447737
Short name T715
Test name
Test status
Simulation time 307714312 ps
CPU time 1.33 seconds
Started Jul 10 05:14:41 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 199588 kb
Host smart-827a8a3e-77e9-44c9-9178-31a531b4cac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159447737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3159447737
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.1591182262
Short name T862
Test name
Test status
Simulation time 63018655 ps
CPU time 0.81 seconds
Started Jul 10 05:12:34 PM PDT 24
Finished Jul 10 05:12:37 PM PDT 24
Peak memory 198528 kb
Host smart-fb02446d-b9a7-4296-b961-5d4e6c051b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591182262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1591182262
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1219255967
Short name T288
Test name
Test status
Simulation time 91239242 ps
CPU time 0.71 seconds
Started Jul 10 05:12:34 PM PDT 24
Finished Jul 10 05:12:36 PM PDT 24
Peak memory 198724 kb
Host smart-f898bab8-f2b5-4c41-b6f7-ca5f339fb3c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219255967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1219255967
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1543487175
Short name T630
Test name
Test status
Simulation time 29834354 ps
CPU time 0.65 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 197640 kb
Host smart-7c0122b2-a9a1-4ac8-8207-b17a32931bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543487175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1543487175
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1273936354
Short name T258
Test name
Test status
Simulation time 163289342 ps
CPU time 1 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:36 PM PDT 24
Peak memory 197824 kb
Host smart-c89ea082-307a-4db5-9bc5-56a6c84437fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273936354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1273936354
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2515398550
Short name T590
Test name
Test status
Simulation time 62212166 ps
CPU time 0.71 seconds
Started Jul 10 05:12:34 PM PDT 24
Finished Jul 10 05:12:36 PM PDT 24
Peak memory 197768 kb
Host smart-61667a92-fafd-42e7-835f-772a9c709931
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515398550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2515398550
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.836035923
Short name T733
Test name
Test status
Simulation time 37915859 ps
CPU time 0.66 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 198100 kb
Host smart-f9e916aa-c1c3-4ad0-8cda-9bbfa99aa184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836035923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.836035923
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2214609171
Short name T390
Test name
Test status
Simulation time 47007440 ps
CPU time 0.72 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 200976 kb
Host smart-08b9e0ae-6c24-437c-9ce9-b11ed84654a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214609171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2214609171
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.4057727744
Short name T75
Test name
Test status
Simulation time 113534145 ps
CPU time 0.81 seconds
Started Jul 10 05:12:30 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 198112 kb
Host smart-82dd63ee-1f7f-41d3-9fcd-eea52fe92b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057727744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.4057727744
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.3633689440
Short name T653
Test name
Test status
Simulation time 64838265 ps
CPU time 0.79 seconds
Started Jul 10 05:12:28 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 198860 kb
Host smart-2a0adb27-e0d3-4aba-b79f-b1ea913f77d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633689440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3633689440
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1852264562
Short name T889
Test name
Test status
Simulation time 101775301 ps
CPU time 0.93 seconds
Started Jul 10 05:12:33 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 209276 kb
Host smart-5df6fa29-c865-4ff1-b7c8-aa75c8d03f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852264562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1852264562
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.170429595
Short name T5
Test name
Test status
Simulation time 623498393 ps
CPU time 1.03 seconds
Started Jul 10 05:12:35 PM PDT 24
Finished Jul 10 05:12:38 PM PDT 24
Peak memory 217048 kb
Host smart-ac11f4d3-5bfb-4d13-a4da-29cbd7f27184
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170429595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.170429595
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.57321645
Short name T513
Test name
Test status
Simulation time 353665935 ps
CPU time 0.74 seconds
Started Jul 10 05:12:35 PM PDT 24
Finished Jul 10 05:12:38 PM PDT 24
Peak memory 199160 kb
Host smart-2a0e4950-0350-48a5-89ac-4df861f68340
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57321645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_
ctrl_config_regwen.57321645
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2992525050
Short name T410
Test name
Test status
Simulation time 1207935489 ps
CPU time 2.05 seconds
Started Jul 10 05:12:34 PM PDT 24
Finished Jul 10 05:12:37 PM PDT 24
Peak memory 200820 kb
Host smart-aa7fb014-ab71-464e-9032-40e7a5eb3ae1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992525050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2992525050
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3533595717
Short name T36
Test name
Test status
Simulation time 1636822293 ps
CPU time 2.07 seconds
Started Jul 10 05:12:38 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200468 kb
Host smart-9e121578-bae6-4ef2-a60a-c68044da79a8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533595717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3533595717
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3242150631
Short name T136
Test name
Test status
Simulation time 306102768 ps
CPU time 0.87 seconds
Started Jul 10 05:12:36 PM PDT 24
Finished Jul 10 05:12:38 PM PDT 24
Peak memory 198904 kb
Host smart-efe5fc3d-d5b9-433b-a262-ae7e4221d3fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242150631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3242150631
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2774943395
Short name T304
Test name
Test status
Simulation time 29771322 ps
CPU time 0.64 seconds
Started Jul 10 05:12:31 PM PDT 24
Finished Jul 10 05:12:33 PM PDT 24
Peak memory 199056 kb
Host smart-57ef38cb-8f58-4cba-a3ca-a581196900c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774943395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2774943395
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.2157423659
Short name T657
Test name
Test status
Simulation time 1014430861 ps
CPU time 3.17 seconds
Started Jul 10 05:12:36 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200828 kb
Host smart-6d00fb5e-91e1-4fbf-9491-cf4c721c44fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157423659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.2157423659
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3394354219
Short name T83
Test name
Test status
Simulation time 4065190406 ps
CPU time 13.54 seconds
Started Jul 10 05:12:35 PM PDT 24
Finished Jul 10 05:12:50 PM PDT 24
Peak memory 201064 kb
Host smart-1c7eed8b-0e2f-4459-bb80-d7e4dc94e735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394354219 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.3394354219
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.4102003667
Short name T536
Test name
Test status
Simulation time 219036317 ps
CPU time 1.11 seconds
Started Jul 10 05:12:34 PM PDT 24
Finished Jul 10 05:12:37 PM PDT 24
Peak memory 199180 kb
Host smart-1ed8f588-83ee-4411-b9a7-30742978a5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102003667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.4102003667
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.3764330434
Short name T890
Test name
Test status
Simulation time 75016837 ps
CPU time 0.8 seconds
Started Jul 10 05:12:35 PM PDT 24
Finished Jul 10 05:12:37 PM PDT 24
Peak memory 198668 kb
Host smart-8cc1eb05-330d-4819-bf4f-7aad05a50f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764330434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3764330434
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2138097711
Short name T636
Test name
Test status
Simulation time 31875264 ps
CPU time 0.82 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 198340 kb
Host smart-41597817-b81d-4a61-8aa8-114d4f091698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138097711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2138097711
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.1210257417
Short name T616
Test name
Test status
Simulation time 85086227 ps
CPU time 0.7 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 198344 kb
Host smart-434584cc-6883-4c6d-bc71-62e2e7ece6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210257417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.1210257417
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2237997730
Short name T16
Test name
Test status
Simulation time 36649276 ps
CPU time 0.62 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 197048 kb
Host smart-db010d7a-801d-457b-a678-aa1d2ecc1fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237997730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.2237997730
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.568086975
Short name T14
Test name
Test status
Simulation time 525407482 ps
CPU time 0.95 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 197772 kb
Host smart-aea14ccf-9600-4fbe-9ae0-78ad4e875f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568086975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.568086975
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1490509942
Short name T972
Test name
Test status
Simulation time 41256710 ps
CPU time 0.66 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 197664 kb
Host smart-eb3adaec-a1f7-4048-a2f0-b8b34c5f0786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490509942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1490509942
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3785138548
Short name T355
Test name
Test status
Simulation time 40762119 ps
CPU time 0.6 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 197732 kb
Host smart-0dc27c87-347e-4f2f-89db-9334d6c94bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785138548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3785138548
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.235480290
Short name T439
Test name
Test status
Simulation time 62010074 ps
CPU time 0.71 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 200996 kb
Host smart-b6710f1b-4a92-4939-9668-09153169d7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235480290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invali
d.235480290
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.2735687084
Short name T755
Test name
Test status
Simulation time 94266134 ps
CPU time 0.67 seconds
Started Jul 10 05:14:41 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 198000 kb
Host smart-856635a7-dcdf-4246-a911-4334088d1653
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735687084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.2735687084
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.1620981587
Short name T791
Test name
Test status
Simulation time 96179907 ps
CPU time 0.78 seconds
Started Jul 10 05:14:38 PM PDT 24
Finished Jul 10 05:14:44 PM PDT 24
Peak memory 198404 kb
Host smart-033cf5f5-7566-436e-b6c2-67a65a36d6a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620981587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1620981587
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2544828442
Short name T176
Test name
Test status
Simulation time 162091163 ps
CPU time 0.84 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 209224 kb
Host smart-778af8cb-f6eb-44e6-9fa6-7412c20c7cc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544828442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2544828442
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.4156271584
Short name T796
Test name
Test status
Simulation time 325643037 ps
CPU time 1.03 seconds
Started Jul 10 05:14:46 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 199892 kb
Host smart-18652a3b-673a-40e3-a524-2532347681d6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156271584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.4156271584
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3611400038
Short name T530
Test name
Test status
Simulation time 1085841660 ps
CPU time 2.12 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 200712 kb
Host smart-2e424571-bf5f-4814-80f6-02cdb902070d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611400038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3611400038
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2853020286
Short name T974
Test name
Test status
Simulation time 969022998 ps
CPU time 3.34 seconds
Started Jul 10 05:14:41 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 200804 kb
Host smart-a11c71c5-33cf-4cfa-8376-8e9d4cea332b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853020286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2853020286
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4275511769
Short name T969
Test name
Test status
Simulation time 66178222 ps
CPU time 0.88 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 198940 kb
Host smart-16cdf212-5fab-4632-83f9-d901d8f27943
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275511769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4275511769
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2860101626
Short name T199
Test name
Test status
Simulation time 62306491 ps
CPU time 0.65 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 199012 kb
Host smart-dd72343f-94c5-4c1b-906a-52ef59aabe9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860101626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2860101626
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.601629041
Short name T646
Test name
Test status
Simulation time 691963071 ps
CPU time 1.94 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 200612 kb
Host smart-c368b100-4f0e-4f6c-b7a7-d02db2b2a345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601629041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.601629041
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.190323490
Short name T901
Test name
Test status
Simulation time 8566646282 ps
CPU time 7.07 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 200960 kb
Host smart-936b0ad7-f999-4eeb-9485-0f7adea6cda4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190323490 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.190323490
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.1699124248
Short name T124
Test name
Test status
Simulation time 326770488 ps
CPU time 0.85 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198124 kb
Host smart-7061b5c3-66e2-4362-8d57-368da092557b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699124248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.1699124248
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.157325733
Short name T8
Test name
Test status
Simulation time 217626189 ps
CPU time 0.9 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 199636 kb
Host smart-450291c7-4c8d-4dfd-914d-65fa1880a167
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157325733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.157325733
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.538112756
Short name T279
Test name
Test status
Simulation time 170708030 ps
CPU time 0.85 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 199840 kb
Host smart-707da9e9-7831-47df-a755-37d1f9fa208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538112756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.538112756
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.262562137
Short name T798
Test name
Test status
Simulation time 82350380 ps
CPU time 0.72 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 198404 kb
Host smart-16411780-ab85-43f4-85f6-0a0126313746
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262562137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.262562137
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1693509333
Short name T946
Test name
Test status
Simulation time 29013706 ps
CPU time 0.63 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 197732 kb
Host smart-3dc86ded-2a31-4002-bd9d-7eb0bb906edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693509333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1693509333
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1414370996
Short name T867
Test name
Test status
Simulation time 445895898 ps
CPU time 0.95 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 197832 kb
Host smart-68a39261-e987-4694-97dd-ae76c4b1d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414370996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1414370996
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.313061516
Short name T563
Test name
Test status
Simulation time 33846591 ps
CPU time 0.63 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 197688 kb
Host smart-e39beaea-3707-4b64-923c-424ef1a754eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313061516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.313061516
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.3398812407
Short name T498
Test name
Test status
Simulation time 54063016 ps
CPU time 0.63 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 197784 kb
Host smart-48832dac-bf61-43ff-ab76-d54794456136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398812407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3398812407
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3645772547
Short name T280
Test name
Test status
Simulation time 43016520 ps
CPU time 0.71 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 200872 kb
Host smart-f21c5ade-d61a-4625-ba93-389fc685b850
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645772547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.3645772547
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.4247104598
Short name T621
Test name
Test status
Simulation time 60530469 ps
CPU time 0.74 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 198852 kb
Host smart-47021644-703c-433e-a580-595034ffe652
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247104598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.4247104598
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.157501882
Short name T187
Test name
Test status
Simulation time 73127484 ps
CPU time 0.78 seconds
Started Jul 10 05:14:40 PM PDT 24
Finished Jul 10 05:14:46 PM PDT 24
Peak memory 198728 kb
Host smart-2b9b5977-2f0e-44d3-95ff-50f0d721c5f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157501882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.157501882
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1864201504
Short name T10
Test name
Test status
Simulation time 110461663 ps
CPU time 1.08 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 209112 kb
Host smart-f41e0c36-a94b-44db-ac36-a21bdd330507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864201504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1864201504
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2332889895
Short name T978
Test name
Test status
Simulation time 30051934 ps
CPU time 0.69 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 198832 kb
Host smart-c59e2727-af61-4f28-881c-85630f43b3e1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332889895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.2332889895
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1187426602
Short name T676
Test name
Test status
Simulation time 1044227161 ps
CPU time 2.32 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 200716 kb
Host smart-a6ab468b-8c4c-4e94-a140-38d72b4eb9ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187426602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1187426602
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.995373469
Short name T898
Test name
Test status
Simulation time 866610985 ps
CPU time 3.27 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 200820 kb
Host smart-df21b2f1-59d3-44e9-86e5-f434034bbd1d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995373469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.995373469
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3686648325
Short name T544
Test name
Test status
Simulation time 72968195 ps
CPU time 0.86 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 198908 kb
Host smart-3b5b6bd1-c033-4e67-b000-63119259108a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686648325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3686648325
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.6881416
Short name T548
Test name
Test status
Simulation time 41319823 ps
CPU time 0.69 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:48 PM PDT 24
Peak memory 198236 kb
Host smart-d4c7e172-0624-4fcb-9fed-af707de14f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6881416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.6881416
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.4074907979
Short name T526
Test name
Test status
Simulation time 4760042494 ps
CPU time 5.1 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:58 PM PDT 24
Peak memory 200948 kb
Host smart-e332b9e4-1842-4fbc-8039-4095644a1ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074907979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.4074907979
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.283491102
Short name T126
Test name
Test status
Simulation time 1803931238 ps
CPU time 6.12 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:56 PM PDT 24
Peak memory 201008 kb
Host smart-324225b1-ee1a-48a3-b605-640a80593d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283491102 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.283491102
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.1811773650
Short name T184
Test name
Test status
Simulation time 390115153 ps
CPU time 1.03 seconds
Started Jul 10 05:14:39 PM PDT 24
Finished Jul 10 05:14:45 PM PDT 24
Peak memory 199484 kb
Host smart-3bf4dac8-5c4f-4095-9fee-dfad20b8e8cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811773650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1811773650
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.969074292
Short name T220
Test name
Test status
Simulation time 82085380 ps
CPU time 0.78 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 198868 kb
Host smart-483b6deb-2884-414b-917e-0ea3039855ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969074292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.969074292
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.3235016717
Short name T654
Test name
Test status
Simulation time 33037005 ps
CPU time 1.03 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 200680 kb
Host smart-e0f24b87-a97a-43f9-801c-f54922a0970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235016717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3235016717
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3437248381
Short name T490
Test name
Test status
Simulation time 74313423 ps
CPU time 0.69 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 198080 kb
Host smart-166465b0-5ed3-4238-9f0f-773f73a8e4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437248381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3437248381
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2586464051
Short name T812
Test name
Test status
Simulation time 30381777 ps
CPU time 0.65 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 197740 kb
Host smart-0e15ddc8-c142-4a0d-9373-798b9d0cd5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586464051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2586464051
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.4170132307
Short name T488
Test name
Test status
Simulation time 319762551 ps
CPU time 0.99 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 197812 kb
Host smart-c830bc86-ddf9-4eeb-a4ce-30ef5634870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170132307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.4170132307
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2673527270
Short name T20
Test name
Test status
Simulation time 41345767 ps
CPU time 0.61 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 197808 kb
Host smart-2604978d-22d4-4f02-8cbe-0afeef434121
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673527270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2673527270
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1072745669
Short name T821
Test name
Test status
Simulation time 22535082 ps
CPU time 0.63 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 197720 kb
Host smart-583b26dd-538f-49fd-9246-6f24a813d72d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072745669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1072745669
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3627149913
Short name T572
Test name
Test status
Simulation time 63685784 ps
CPU time 0.67 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 201008 kb
Host smart-202a709a-f078-4548-a076-84eedf4472c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627149913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3627149913
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.959010587
Short name T362
Test name
Test status
Simulation time 416688194 ps
CPU time 0.97 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 199140 kb
Host smart-f1575549-4401-48bb-ad92-696b48fd8dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959010587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wa
keup_race.959010587
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.4040775505
Short name T268
Test name
Test status
Simulation time 138897325 ps
CPU time 0.65 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 198876 kb
Host smart-998fd68c-897f-4e2d-99a5-b4b414780f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040775505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.4040775505
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2935470109
Short name T137
Test name
Test status
Simulation time 163295005 ps
CPU time 0.82 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 209220 kb
Host smart-6f1d7c09-8856-4e7b-b20a-ff0c65ef9faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935470109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2935470109
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2780950106
Short name T55
Test name
Test status
Simulation time 309065266 ps
CPU time 0.95 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 199748 kb
Host smart-ff74ddb5-3dff-4df6-a7f6-dfa7eaeb288a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780950106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2780950106
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3528935288
Short name T706
Test name
Test status
Simulation time 1063577893 ps
CPU time 2.02 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 200820 kb
Host smart-154f6730-7501-4181-bd56-5f7226bffeb6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528935288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3528935288
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.478922524
Short name T309
Test name
Test status
Simulation time 910569888 ps
CPU time 3.1 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:56 PM PDT 24
Peak memory 200840 kb
Host smart-a4e69128-2b0c-4cef-a32a-44bd548eb6dd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478922524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.478922524
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.338096230
Short name T182
Test name
Test status
Simulation time 154407699 ps
CPU time 0.86 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 199248 kb
Host smart-eb52c789-78e0-491f-b2bd-c2922fe138ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338096230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.338096230
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.4235114727
Short name T427
Test name
Test status
Simulation time 52149708 ps
CPU time 0.65 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 199064 kb
Host smart-b7c4c63d-b98b-4946-bdca-f61de73766d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235114727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.4235114727
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.1296529125
Short name T91
Test name
Test status
Simulation time 1372699012 ps
CPU time 4.16 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 200888 kb
Host smart-c212e44b-14fe-41c1-b553-936c545f2283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296529125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.1296529125
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1211108737
Short name T46
Test name
Test status
Simulation time 9992108454 ps
CPU time 27.73 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:15:18 PM PDT 24
Peak memory 201048 kb
Host smart-e879f2b3-8a06-4f12-89e9-ee380d6c9291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211108737 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.1211108737
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.1800167036
Short name T907
Test name
Test status
Simulation time 89936373 ps
CPU time 0.84 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 198836 kb
Host smart-4fd2c938-2baf-4a64-9fd7-b6515b0b6cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800167036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.1800167036
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.280949950
Short name T770
Test name
Test status
Simulation time 247794692 ps
CPU time 0.86 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:50 PM PDT 24
Peak memory 199308 kb
Host smart-21b5e602-2bcb-4bf9-9992-50c073f04558
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280949950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.280949950
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2234121662
Short name T447
Test name
Test status
Simulation time 43902694 ps
CPU time 0.75 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 198544 kb
Host smart-699e2f8d-39b0-415c-94d0-17e2a30e52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234121662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2234121662
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.611444830
Short name T843
Test name
Test status
Simulation time 64401055 ps
CPU time 0.75 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 198808 kb
Host smart-290c7087-b0e8-4a9b-9d83-f17f52e845f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611444830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.611444830
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3596698416
Short name T982
Test name
Test status
Simulation time 61827884 ps
CPU time 0.58 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 197760 kb
Host smart-2f2ee8d4-c15d-4f00-be68-ca3f7e0dc2a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596698416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3596698416
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.210625358
Short name T524
Test name
Test status
Simulation time 166397578 ps
CPU time 0.99 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198036 kb
Host smart-e77b9a3e-d658-49bb-a79a-1dbbf637bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210625358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.210625358
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2511378821
Short name T824
Test name
Test status
Simulation time 35364134 ps
CPU time 0.66 seconds
Started Jul 10 05:14:50 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 197744 kb
Host smart-e3c1c9e8-9505-4ccf-9247-755dc916abde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511378821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2511378821
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.742670320
Short name T983
Test name
Test status
Simulation time 98363011 ps
CPU time 0.63 seconds
Started Jul 10 05:14:53 PM PDT 24
Finished Jul 10 05:15:00 PM PDT 24
Peak memory 197712 kb
Host smart-ae2b6070-f06e-4f58-881d-392fd72d40ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742670320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.742670320
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2068044264
Short name T242
Test name
Test status
Simulation time 54640981 ps
CPU time 0.7 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:56 PM PDT 24
Peak memory 200996 kb
Host smart-20bc810c-c147-4af1-a6d4-1cb182d20b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068044264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2068044264
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.686749569
Short name T371
Test name
Test status
Simulation time 80482838 ps
CPU time 0.73 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 197928 kb
Host smart-09cb9569-f35d-4d1a-9662-693b0607b961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686749569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wa
keup_race.686749569
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.3748824820
Short name T858
Test name
Test status
Simulation time 81202929 ps
CPU time 0.7 seconds
Started Jul 10 05:14:45 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 198868 kb
Host smart-be4e2c45-627b-416d-8db6-579bd27a18a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748824820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3748824820
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.247671853
Short name T423
Test name
Test status
Simulation time 144216752 ps
CPU time 0.8 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 201080 kb
Host smart-d1afe81f-2fe2-4557-8ec2-5892287ce7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247671853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.247671853
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3984599404
Short name T486
Test name
Test status
Simulation time 680004275 ps
CPU time 0.91 seconds
Started Jul 10 05:14:47 PM PDT 24
Finished Jul 10 05:14:56 PM PDT 24
Peak memory 199832 kb
Host smart-9baa9487-de83-4205-a8c5-1e830d19b90c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984599404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.3984599404
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1443632061
Short name T933
Test name
Test status
Simulation time 934439120 ps
CPU time 2.76 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 200876 kb
Host smart-d4b683c9-e2ce-468b-9d98-06630092140d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443632061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1443632061
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4285033782
Short name T198
Test name
Test status
Simulation time 845227631 ps
CPU time 3.08 seconds
Started Jul 10 05:14:42 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 200808 kb
Host smart-bc6b0167-3a58-4a80-a370-d370e0160ff8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285033782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4285033782
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1733864500
Short name T466
Test name
Test status
Simulation time 122565906 ps
CPU time 0.81 seconds
Started Jul 10 05:14:43 PM PDT 24
Finished Jul 10 05:14:51 PM PDT 24
Peak memory 198952 kb
Host smart-c7d593d6-f90d-442f-9008-2665d3e90d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733864500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1733864500
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.2960257518
Short name T261
Test name
Test status
Simulation time 39788137 ps
CPU time 0.66 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:52 PM PDT 24
Peak memory 198300 kb
Host smart-0088f7cf-033f-4b01-a5c4-3625d4c0017b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960257518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.2960257518
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.4047682920
Short name T97
Test name
Test status
Simulation time 1638895719 ps
CPU time 4.12 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 201104 kb
Host smart-ea82d63e-aa01-47ae-b5a2-7694a1c377ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047682920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.4047682920
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.623357224
Short name T130
Test name
Test status
Simulation time 11557645267 ps
CPU time 14.43 seconds
Started Jul 10 05:14:50 PM PDT 24
Finished Jul 10 05:15:11 PM PDT 24
Peak memory 200996 kb
Host smart-d3623d0f-2f3e-42f6-9e88-6c143f2b9a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623357224 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.623357224
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.1180711910
Short name T698
Test name
Test status
Simulation time 143440513 ps
CPU time 0.83 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198876 kb
Host smart-f2703957-8f2f-4e2e-9a64-6bb139850a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180711910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1180711910
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.465404012
Short name T363
Test name
Test status
Simulation time 37230098 ps
CPU time 0.66 seconds
Started Jul 10 05:14:44 PM PDT 24
Finished Jul 10 05:14:53 PM PDT 24
Peak memory 198736 kb
Host smart-0c86e82d-cd34-4901-90b9-86d968fd479c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465404012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.465404012
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2641496423
Short name T94
Test name
Test status
Simulation time 48786520 ps
CPU time 0.76 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198928 kb
Host smart-8267269b-0a02-47fb-a18c-2e5d9e0e8a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641496423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2641496423
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3668645711
Short name T809
Test name
Test status
Simulation time 176379211 ps
CPU time 0.69 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198880 kb
Host smart-9e51ffb1-8a35-441f-b27e-cb69df494f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668645711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3668645711
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.4040134708
Short name T150
Test name
Test status
Simulation time 33723076 ps
CPU time 0.59 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 197688 kb
Host smart-f65bced6-cfa3-4133-bb45-fd9fa05b321e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040134708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.4040134708
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2096274775
Short name T453
Test name
Test status
Simulation time 159682028 ps
CPU time 0.95 seconds
Started Jul 10 05:14:52 PM PDT 24
Finished Jul 10 05:15:00 PM PDT 24
Peak memory 198116 kb
Host smart-473aaab9-32c6-4333-8c38-1ae1cc7d895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096274775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2096274775
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.2381557772
Short name T567
Test name
Test status
Simulation time 52322810 ps
CPU time 0.64 seconds
Started Jul 10 05:14:52 PM PDT 24
Finished Jul 10 05:15:00 PM PDT 24
Peak memory 197080 kb
Host smart-904c6340-e3c6-47ae-8a4b-aa18ea3bdb60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381557772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2381557772
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2501213417
Short name T682
Test name
Test status
Simulation time 21732545 ps
CPU time 0.61 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198088 kb
Host smart-65d06aab-047d-40ed-9ae4-a5ae1103f1dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501213417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2501213417
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.3482333651
Short name T671
Test name
Test status
Simulation time 43339502 ps
CPU time 0.73 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:14:56 PM PDT 24
Peak memory 201004 kb
Host smart-56acc877-31d1-475f-b0fe-623ec4895331
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482333651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.3482333651
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.2341688988
Short name T681
Test name
Test status
Simulation time 197077160 ps
CPU time 1.07 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 199404 kb
Host smart-2516c163-31c9-4e42-9ae4-9bea3d7dc52d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341688988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.2341688988
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2645060646
Short name T996
Test name
Test status
Simulation time 23615595 ps
CPU time 0.71 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198852 kb
Host smart-c59aa84b-86fa-45c6-a4f5-ce0e727fe07c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645060646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2645060646
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4049562793
Short name T921
Test name
Test status
Simulation time 115247429 ps
CPU time 0.94 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 209208 kb
Host smart-6868c630-c5ae-49ca-beae-00b5de880ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049562793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4049562793
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2898615197
Short name T235
Test name
Test status
Simulation time 731595652 ps
CPU time 0.92 seconds
Started Jul 10 05:14:46 PM PDT 24
Finished Jul 10 05:14:54 PM PDT 24
Peak memory 199620 kb
Host smart-0208bc20-ddf8-4ea8-94a4-80c8501d8243
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898615197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.2898615197
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1197539436
Short name T246
Test name
Test status
Simulation time 818047295 ps
CPU time 2.35 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 200800 kb
Host smart-14440db8-4a47-4ba6-a19e-a55a4860f43f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197539436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1197539436
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1424300027
Short name T276
Test name
Test status
Simulation time 1059234440 ps
CPU time 1.96 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:58 PM PDT 24
Peak memory 200772 kb
Host smart-bd37b17a-f16a-47f9-8d1d-34245ede83fc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424300027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1424300027
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2771690542
Short name T228
Test name
Test status
Simulation time 72561281 ps
CPU time 0.98 seconds
Started Jul 10 05:14:50 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198944 kb
Host smart-b1154df5-326d-459a-ba4e-51d29d6bd534
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771690542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2771690542
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.3714574534
Short name T507
Test name
Test status
Simulation time 32652093 ps
CPU time 0.7 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 199104 kb
Host smart-065df443-7aa1-4d7b-8ccf-6caa9b43f1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714574534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3714574534
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.2636771976
Short name T314
Test name
Test status
Simulation time 2141629897 ps
CPU time 6.43 seconds
Started Jul 10 05:14:48 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 200928 kb
Host smart-5fa88b58-c995-4035-8f27-4390a90d03c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636771976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.2636771976
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3993117021
Short name T49
Test name
Test status
Simulation time 6784853110 ps
CPU time 12.05 seconds
Started Jul 10 05:14:52 PM PDT 24
Finished Jul 10 05:15:11 PM PDT 24
Peak memory 201064 kb
Host smart-623b0d0a-494a-4f97-afd5-631db9a8ad40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993117021 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.3993117021
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.3768179698
Short name T221
Test name
Test status
Simulation time 171273254 ps
CPU time 1.02 seconds
Started Jul 10 05:14:54 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 199356 kb
Host smart-c93dda35-6212-4423-8a5e-0f741508a1d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768179698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3768179698
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.2076230213
Short name T335
Test name
Test status
Simulation time 95755303 ps
CPU time 0.88 seconds
Started Jul 10 05:14:52 PM PDT 24
Finished Jul 10 05:15:00 PM PDT 24
Peak memory 198720 kb
Host smart-7328f7b0-b9ed-4c84-9e18-1a0c7ddc224d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076230213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.2076230213
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.1706073957
Short name T831
Test name
Test status
Simulation time 30718261 ps
CPU time 0.69 seconds
Started Jul 10 05:14:52 PM PDT 24
Finished Jul 10 05:15:00 PM PDT 24
Peak memory 198852 kb
Host smart-57b773e6-3c13-4b57-b5dc-64cdecb81909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706073957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.1706073957
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4174168747
Short name T761
Test name
Test status
Simulation time 57857693 ps
CPU time 0.83 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 198376 kb
Host smart-016bb0e6-25de-4853-b342-7bedf42ffe47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174168747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.4174168747
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.859322073
Short name T148
Test name
Test status
Simulation time 30502319 ps
CPU time 0.67 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 197680 kb
Host smart-ce06b2b2-e99f-4100-a8cb-690f34c5f2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859322073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_
malfunc.859322073
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3659730858
Short name T793
Test name
Test status
Simulation time 161599215 ps
CPU time 0.99 seconds
Started Jul 10 05:14:59 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 198140 kb
Host smart-877ffa43-2e0f-43ce-8fab-07f4928fcdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659730858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3659730858
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2977144954
Short name T930
Test name
Test status
Simulation time 71279171 ps
CPU time 0.67 seconds
Started Jul 10 05:14:54 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 197828 kb
Host smart-b9fc9924-fe70-42d6-8563-f6f617210c3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977144954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2977144954
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.4207538029
Short name T415
Test name
Test status
Simulation time 37076637 ps
CPU time 0.66 seconds
Started Jul 10 05:14:59 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 197728 kb
Host smart-808a5487-a772-409f-b734-a5bcf71beca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207538029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.4207538029
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.889378153
Short name T238
Test name
Test status
Simulation time 41440481 ps
CPU time 0.72 seconds
Started Jul 10 05:14:55 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 201124 kb
Host smart-ea787ddc-0a47-409f-aa8b-e933416555a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889378153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invali
d.889378153
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.2262493525
Short name T504
Test name
Test status
Simulation time 126264496 ps
CPU time 0.86 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198156 kb
Host smart-b34ac33b-55a7-414b-b07c-e40a8769ae16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262493525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.2262493525
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2387509226
Short name T244
Test name
Test status
Simulation time 25093701 ps
CPU time 0.68 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 198868 kb
Host smart-77292196-0f3a-41f0-bbab-bbd88dc9bac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387509226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2387509226
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.646737210
Short name T734
Test name
Test status
Simulation time 169747444 ps
CPU time 0.81 seconds
Started Jul 10 05:14:54 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 209264 kb
Host smart-73e1aa82-fb98-4c96-8533-75812c02041a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646737210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.646737210
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.35739745
Short name T732
Test name
Test status
Simulation time 168652707 ps
CPU time 0.97 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 199636 kb
Host smart-b76de25d-45b5-4a21-a00d-fb0cdd743246
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35739745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm
_ctrl_config_regwen.35739745
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2853411412
Short name T686
Test name
Test status
Simulation time 866076446 ps
CPU time 2.41 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 200744 kb
Host smart-c662e565-9429-481d-a054-b9dac4b96fca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853411412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2853411412
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3222825971
Short name T254
Test name
Test status
Simulation time 1616062456 ps
CPU time 2.26 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 200804 kb
Host smart-3489b29e-45f5-4adb-845a-55133f0e161a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222825971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3222825971
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1344461678
Short name T914
Test name
Test status
Simulation time 90709679 ps
CPU time 0.88 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 198824 kb
Host smart-5f7140c5-8737-4d03-b12a-0ae0b7bf6475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344461678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1344461678
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1521216749
Short name T420
Test name
Test status
Simulation time 159946878 ps
CPU time 0.65 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198276 kb
Host smart-9c0e4bab-a439-4553-9cf4-038507893f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521216749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1521216749
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.4015409678
Short name T713
Test name
Test status
Simulation time 1371274028 ps
CPU time 4.61 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 200848 kb
Host smart-16848588-ddc7-4f2d-a65a-0efc927db5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015409678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.4015409678
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2225779156
Short name T412
Test name
Test status
Simulation time 7476406316 ps
CPU time 17.74 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:21 PM PDT 24
Peak memory 201068 kb
Host smart-5af63cbf-4c81-414f-ab3f-138baf29997a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225779156 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.2225779156
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.4230895305
Short name T762
Test name
Test status
Simulation time 65155754 ps
CPU time 0.7 seconds
Started Jul 10 05:14:49 PM PDT 24
Finished Jul 10 05:14:57 PM PDT 24
Peak memory 198848 kb
Host smart-9fec4bb6-96f6-433d-91ab-70e70af0637e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230895305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.4230895305
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.3626228093
Short name T215
Test name
Test status
Simulation time 151952453 ps
CPU time 0.86 seconds
Started Jul 10 05:14:51 PM PDT 24
Finished Jul 10 05:14:59 PM PDT 24
Peak memory 199088 kb
Host smart-7ad3d6d1-86b7-4286-adde-9bfe7e84e9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626228093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.3626228093
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2385490015
Short name T670
Test name
Test status
Simulation time 129019297 ps
CPU time 0.67 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 198348 kb
Host smart-9d5ced51-c2f1-4963-97e5-f22701669ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385490015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2385490015
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.964274551
Short name T472
Test name
Test status
Simulation time 66049104 ps
CPU time 0.78 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 198828 kb
Host smart-7b26c0b1-1ccb-4b4e-b110-942342c20e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964274551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.964274551
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.496850895
Short name T802
Test name
Test status
Simulation time 39611641 ps
CPU time 0.62 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 197732 kb
Host smart-2efe753b-3a6d-4b7a-abed-40d2e152b568
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496850895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.496850895
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.85569517
Short name T140
Test name
Test status
Simulation time 160758601 ps
CPU time 1.01 seconds
Started Jul 10 05:14:59 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 198148 kb
Host smart-4f8d7a08-50f7-4f6e-b910-32ee7608e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85569517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.85569517
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.3234267778
Short name T329
Test name
Test status
Simulation time 39157097 ps
CPU time 0.64 seconds
Started Jul 10 05:14:55 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 197052 kb
Host smart-de9d8ec2-e8d9-4b28-a05d-d2de4e76fab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234267778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3234267778
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.3636037973
Short name T989
Test name
Test status
Simulation time 41018129 ps
CPU time 0.72 seconds
Started Jul 10 05:14:57 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 197724 kb
Host smart-0a6f34c1-e6b0-4c8d-849e-3c17d2d6a6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636037973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3636037973
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.767962396
Short name T205
Test name
Test status
Simulation time 53333232 ps
CPU time 0.7 seconds
Started Jul 10 05:14:57 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 201076 kb
Host smart-d513fe05-4e83-45b3-9843-c3c181a03405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767962396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.767962396
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.1308678971
Short name T249
Test name
Test status
Simulation time 218334741 ps
CPU time 0.73 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 198000 kb
Host smart-578c7c0a-a2c9-4137-98ed-a7a3349a8d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308678971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.1308678971
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2812691057
Short name T624
Test name
Test status
Simulation time 55681839 ps
CPU time 0.75 seconds
Started Jul 10 05:14:57 PM PDT 24
Finished Jul 10 05:15:04 PM PDT 24
Peak memory 198820 kb
Host smart-adb91c5a-9d08-422e-881b-7232160b2983
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812691057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2812691057
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1443043257
Short name T674
Test name
Test status
Simulation time 108118263 ps
CPU time 1.11 seconds
Started Jul 10 05:14:55 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 209164 kb
Host smart-5b787f9f-ff1e-40ed-8f76-87b1a0b5374e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443043257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1443043257
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1661012659
Short name T610
Test name
Test status
Simulation time 484919049 ps
CPU time 1.02 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 199988 kb
Host smart-8ff67c97-c570-4787-b403-9666030d726c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661012659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.1661012659
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2053587330
Short name T257
Test name
Test status
Simulation time 754619460 ps
CPU time 3.5 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 200844 kb
Host smart-e92d09f2-3822-464e-9fae-9d0604ec833c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053587330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2053587330
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.436049527
Short name T878
Test name
Test status
Simulation time 808439138 ps
CPU time 3.48 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 200852 kb
Host smart-63921673-88ff-4312-abbe-ee2496972957
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436049527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.436049527
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2195495098
Short name T727
Test name
Test status
Simulation time 161285895 ps
CPU time 0.92 seconds
Started Jul 10 05:15:00 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 198744 kb
Host smart-3c21bf98-07e0-44d2-9809-4336034424ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195495098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2195495098
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.179671568
Short name T965
Test name
Test status
Simulation time 35450454 ps
CPU time 0.67 seconds
Started Jul 10 05:14:57 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 198128 kb
Host smart-eb426e36-159f-4706-bc32-592a5c15365c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179671568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.179671568
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.2453466321
Short name T669
Test name
Test status
Simulation time 1362219214 ps
CPU time 4.42 seconds
Started Jul 10 05:14:58 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 200844 kb
Host smart-3c001efd-eb77-4288-98ed-31340fad455e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453466321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.2453466321
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3194937832
Short name T129
Test name
Test status
Simulation time 8979217640 ps
CPU time 27.45 seconds
Started Jul 10 05:14:55 PM PDT 24
Finished Jul 10 05:15:29 PM PDT 24
Peak memory 201060 kb
Host smart-7672424a-9c0b-4992-a4e1-6519f0ec6a6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194937832 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.3194937832
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.4153230386
Short name T361
Test name
Test status
Simulation time 31866982 ps
CPU time 0.67 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 198840 kb
Host smart-92905618-6f15-4286-8e7b-2b9304e10702
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153230386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.4153230386
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.1022690378
Short name T724
Test name
Test status
Simulation time 251186025 ps
CPU time 1.23 seconds
Started Jul 10 05:14:54 PM PDT 24
Finished Jul 10 05:15:02 PM PDT 24
Peak memory 200596 kb
Host smart-2273e944-aeb1-485f-a125-ae5e26893df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022690378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.1022690378
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.30341576
Short name T920
Test name
Test status
Simulation time 41580059 ps
CPU time 0.91 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 199948 kb
Host smart-f1e0fb78-be6d-4965-b3cf-0a98c7bbeb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30341576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.30341576
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3018667166
Short name T503
Test name
Test status
Simulation time 31921642 ps
CPU time 0.62 seconds
Started Jul 10 05:15:02 PM PDT 24
Finished Jul 10 05:15:07 PM PDT 24
Peak memory 197024 kb
Host smart-a4f3412b-c42d-4efc-8d03-6ba327a458da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018667166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3018667166
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.467602545
Short name T960
Test name
Test status
Simulation time 1235321192 ps
CPU time 0.95 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 197748 kb
Host smart-f2272e53-2a1a-4d63-8fbd-91c496f2ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467602545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.467602545
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.2247312871
Short name T468
Test name
Test status
Simulation time 41732563 ps
CPU time 0.7 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 197704 kb
Host smart-e950d1fd-ce96-4c70-bf92-7c86cf9e65e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247312871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2247312871
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.1949218586
Short name T89
Test name
Test status
Simulation time 44019821 ps
CPU time 0.62 seconds
Started Jul 10 05:15:01 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 197808 kb
Host smart-407133b7-6353-4fdf-9dcc-9613e5840bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949218586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1949218586
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.3980447141
Short name T44
Test name
Test status
Simulation time 43005874 ps
CPU time 0.71 seconds
Started Jul 10 05:15:08 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 201260 kb
Host smart-b50a8c5a-f09e-41d2-848d-59c0197dd9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980447141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.3980447141
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.3607341388
Short name T583
Test name
Test status
Simulation time 57338233 ps
CPU time 0.77 seconds
Started Jul 10 05:15:00 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 198020 kb
Host smart-d70303cd-c1cf-4623-bacf-8dcdfd7d2f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607341388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.3607341388
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.1563807644
Short name T296
Test name
Test status
Simulation time 189836502 ps
CPU time 0.92 seconds
Started Jul 10 05:14:56 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 199556 kb
Host smart-bdff17b3-5237-45b9-9abf-21aa2543c13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563807644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1563807644
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3183619198
Short name T997
Test name
Test status
Simulation time 109607519 ps
CPU time 0.96 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 209192 kb
Host smart-a472269e-32fb-466a-8345-415cafdd6f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183619198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3183619198
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3680048957
Short name T986
Test name
Test status
Simulation time 152141582 ps
CPU time 0.82 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 198484 kb
Host smart-342db94d-5f81-4578-937f-3113304fed7f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680048957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.3680048957
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2002417697
Short name T807
Test name
Test status
Simulation time 757598017 ps
CPU time 3.22 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 200888 kb
Host smart-f1c7f080-bb0d-4ebd-b009-cb1067d8a6e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002417697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2002417697
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3244421163
Short name T534
Test name
Test status
Simulation time 1090884751 ps
CPU time 1.99 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 200880 kb
Host smart-838bd5d4-99c7-41b8-ba4a-5218af65fb14
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244421163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3244421163
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1017449814
Short name T430
Test name
Test status
Simulation time 89051797 ps
CPU time 0.83 seconds
Started Jul 10 05:15:08 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 199192 kb
Host smart-d74cfbd2-6e86-4b41-ab84-a4bc1886ecab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017449814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1017449814
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2196577578
Short name T458
Test name
Test status
Simulation time 121216877 ps
CPU time 0.64 seconds
Started Jul 10 05:14:54 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 198216 kb
Host smart-bbcb2bbb-3ec0-4033-8a47-a6ad53e3b0a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196577578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2196577578
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.2255192724
Short name T775
Test name
Test status
Simulation time 1516272411 ps
CPU time 3.81 seconds
Started Jul 10 05:15:00 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 200812 kb
Host smart-73eb0323-ca9f-4313-aeb9-4db83c70d7a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255192724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2255192724
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.892578201
Short name T874
Test name
Test status
Simulation time 5093312882 ps
CPU time 15.62 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:23 PM PDT 24
Peak memory 201000 kb
Host smart-4379a58f-267f-4577-b0d9-d1ef5764ed4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892578201 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.892578201
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.2273242452
Short name T359
Test name
Test status
Simulation time 174985006 ps
CPU time 0.9 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 199352 kb
Host smart-10c3e539-d8ca-48ff-b520-9b2295da711d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273242452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.2273242452
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.234457840
Short name T484
Test name
Test status
Simulation time 300379480 ps
CPU time 1.49 seconds
Started Jul 10 05:15:02 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 200716 kb
Host smart-d32dc804-09b4-4017-9ace-a00723a735ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234457840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.234457840
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.2455905564
Short name T451
Test name
Test status
Simulation time 65663141 ps
CPU time 0.77 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 198756 kb
Host smart-d1ebe8b1-7172-4b68-8f15-d1c379051709
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455905564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.2455905564
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2846464669
Short name T902
Test name
Test status
Simulation time 30660798 ps
CPU time 0.68 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:07 PM PDT 24
Peak memory 197948 kb
Host smart-4ff22580-28dd-4950-828c-3efef4ab57ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846464669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2846464669
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.3158160458
Short name T139
Test name
Test status
Simulation time 589001213 ps
CPU time 0.94 seconds
Started Jul 10 05:15:12 PM PDT 24
Finished Jul 10 05:15:17 PM PDT 24
Peak memory 198340 kb
Host smart-fb5c4650-b390-4054-b757-0de340f48610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158160458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3158160458
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3741409485
Short name T912
Test name
Test status
Simulation time 65992875 ps
CPU time 0.65 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 197820 kb
Host smart-ced57cd8-a55b-4a86-8ed1-c0b54c00dce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741409485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3741409485
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.2819830004
Short name T29
Test name
Test status
Simulation time 94535801 ps
CPU time 0.62 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 197792 kb
Host smart-ebb43c81-02ca-467c-8df9-6cb4cd6cb00b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819830004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2819830004
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1837749722
Short name T469
Test name
Test status
Simulation time 42444782 ps
CPU time 0.73 seconds
Started Jul 10 05:15:09 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 201124 kb
Host smart-6b438e29-6af2-4849-9265-09727c990f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837749722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1837749722
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.2191772918
Short name T694
Test name
Test status
Simulation time 135705502 ps
CPU time 0.92 seconds
Started Jul 10 05:15:01 PM PDT 24
Finished Jul 10 05:15:07 PM PDT 24
Peak memory 198344 kb
Host smart-25ce74aa-9b53-4e87-bf00-76b8a1933257
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191772918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.2191772918
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.2325019633
Short name T407
Test name
Test status
Simulation time 80933255 ps
CPU time 0.97 seconds
Started Jul 10 05:15:01 PM PDT 24
Finished Jul 10 05:15:06 PM PDT 24
Peak memory 199356 kb
Host smart-38c8353b-1476-4481-a48c-74277ebacc51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325019633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2325019633
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1291476240
Short name T397
Test name
Test status
Simulation time 112433803 ps
CPU time 0.96 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 209220 kb
Host smart-0e1209a8-fa09-43ac-a94c-ea2fec476f7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291476240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1291476240
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.40654097
Short name T237
Test name
Test status
Simulation time 184262831 ps
CPU time 1.18 seconds
Started Jul 10 05:15:09 PM PDT 24
Finished Jul 10 05:15:15 PM PDT 24
Peak memory 199644 kb
Host smart-e405e01d-d3de-4de3-b782-7b282718d82f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm
_ctrl_config_regwen.40654097
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.870973479
Short name T613
Test name
Test status
Simulation time 1629492112 ps
CPU time 2.1 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 200784 kb
Host smart-6bb8e97e-98d5-4e62-adec-196e2141566b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870973479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.870973479
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2650500462
Short name T145
Test name
Test status
Simulation time 811442719 ps
CPU time 2.37 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 200880 kb
Host smart-b2c4803f-7ad7-4847-8f90-5d435c8b6b7d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650500462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2650500462
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3006480731
Short name T602
Test name
Test status
Simulation time 80779699 ps
CPU time 0.94 seconds
Started Jul 10 05:15:08 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 199116 kb
Host smart-27f691d5-5fe3-42af-803c-e56a8061f94c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006480731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3006480731
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1615357991
Short name T956
Test name
Test status
Simulation time 33694031 ps
CPU time 0.68 seconds
Started Jul 10 05:15:03 PM PDT 24
Finished Jul 10 05:15:07 PM PDT 24
Peak memory 198292 kb
Host smart-144279b7-7517-435e-b181-7d9175ee4e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615357991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1615357991
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.1892723531
Short name T717
Test name
Test status
Simulation time 1644670172 ps
CPU time 3.8 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 200892 kb
Host smart-4ad92626-4378-438c-9686-815005db983e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892723531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1892723531
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.1184638195
Short name T128
Test name
Test status
Simulation time 15145265561 ps
CPU time 20.79 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:32 PM PDT 24
Peak memory 201004 kb
Host smart-71df919b-0366-4127-ae68-efb0e19d90cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184638195 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.1184638195
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.939068894
Short name T837
Test name
Test status
Simulation time 148228874 ps
CPU time 0.98 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:09 PM PDT 24
Peak memory 197980 kb
Host smart-6794ca34-da25-4b29-831e-ece9048b1650
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939068894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.939068894
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.967595693
Short name T354
Test name
Test status
Simulation time 145653645 ps
CPU time 1.03 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 199788 kb
Host smart-808c6297-1791-442b-a2a0-6f1148275a84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967595693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.967595693
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2350686982
Short name T88
Test name
Test status
Simulation time 21012520 ps
CPU time 0.71 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 198892 kb
Host smart-a3ce7278-6f5b-4473-8faa-4e6522bf6332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350686982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2350686982
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.603327126
Short name T556
Test name
Test status
Simulation time 67869773 ps
CPU time 0.68 seconds
Started Jul 10 05:15:13 PM PDT 24
Finished Jul 10 05:15:17 PM PDT 24
Peak memory 198280 kb
Host smart-285751bb-7119-487b-b311-14427ea6f463
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603327126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disa
ble_rom_integrity_check.603327126
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3602251898
Short name T553
Test name
Test status
Simulation time 29814137 ps
CPU time 0.66 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 196956 kb
Host smart-1778ff7a-d189-46e4-aaa9-794a9e51099b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602251898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3602251898
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.475448346
Short name T297
Test name
Test status
Simulation time 298103058 ps
CPU time 1.13 seconds
Started Jul 10 05:15:10 PM PDT 24
Finished Jul 10 05:15:15 PM PDT 24
Peak memory 197808 kb
Host smart-a3c0dffe-71dc-4290-94b2-91087ee2f6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475448346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.475448346
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2721935144
Short name T987
Test name
Test status
Simulation time 70804174 ps
CPU time 0.62 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 197820 kb
Host smart-5a712d51-3729-4c15-b83d-f6cb8411d61d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721935144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2721935144
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.564204654
Short name T172
Test name
Test status
Simulation time 29297974 ps
CPU time 0.62 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:11 PM PDT 24
Peak memory 197764 kb
Host smart-66505afd-92d1-47aa-b5bc-a0675d750d87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564204654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.564204654
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2544901768
Short name T467
Test name
Test status
Simulation time 41493914 ps
CPU time 0.72 seconds
Started Jul 10 05:15:05 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 201108 kb
Host smart-19cb4a4a-fcf7-4d36-a53e-a17ca8decfed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544901768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2544901768
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.2939345304
Short name T973
Test name
Test status
Simulation time 106193468 ps
CPU time 0.69 seconds
Started Jul 10 05:15:09 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 198852 kb
Host smart-b012636f-9929-4f27-8fe2-a94d9ea5203e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939345304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w
akeup_race.2939345304
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2140478137
Short name T236
Test name
Test status
Simulation time 40572369 ps
CPU time 0.72 seconds
Started Jul 10 05:15:04 PM PDT 24
Finished Jul 10 05:15:08 PM PDT 24
Peak memory 198804 kb
Host smart-d83c69e4-59c3-4f0f-bcb7-81bef62bea20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140478137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2140478137
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3997090172
Short name T884
Test name
Test status
Simulation time 102084214 ps
CPU time 1.13 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:11 PM PDT 24
Peak memory 209260 kb
Host smart-0afe9d99-5477-49bb-bc9f-73bff31e2e3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997090172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3997090172
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2409078631
Short name T696
Test name
Test status
Simulation time 248385976 ps
CPU time 1.29 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 199620 kb
Host smart-93115d14-8a17-4be6-ba0f-ab811b86f066
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409078631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.2409078631
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2740261827
Short name T598
Test name
Test status
Simulation time 1249197574 ps
CPU time 2.3 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 200772 kb
Host smart-03e9c3d9-463c-453b-a8f8-013a47007039
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740261827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2740261827
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3198051883
Short name T523
Test name
Test status
Simulation time 1033290405 ps
CPU time 2.11 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 200756 kb
Host smart-973d2bca-b4b2-4dda-beda-4274691ac548
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198051883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3198051883
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3162501241
Short name T729
Test name
Test status
Simulation time 51658411 ps
CPU time 0.91 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:10 PM PDT 24
Peak memory 199556 kb
Host smart-dfb4a4a3-4b25-4f0f-9b63-0735ae46b46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162501241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3162501241
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3985226034
Short name T455
Test name
Test status
Simulation time 32486520 ps
CPU time 0.68 seconds
Started Jul 10 05:15:11 PM PDT 24
Finished Jul 10 05:15:15 PM PDT 24
Peak memory 198280 kb
Host smart-216b0b83-b27f-4cc9-a3c3-80ea9f1e0482
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985226034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3985226034
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.2553208210
Short name T437
Test name
Test status
Simulation time 113680876 ps
CPU time 0.72 seconds
Started Jul 10 05:15:06 PM PDT 24
Finished Jul 10 05:15:11 PM PDT 24
Peak memory 198944 kb
Host smart-341a04f0-82c0-4dc0-a469-650ad2c51788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553208210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2553208210
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3826266764
Short name T121
Test name
Test status
Simulation time 8062279153 ps
CPU time 16.18 seconds
Started Jul 10 05:15:13 PM PDT 24
Finished Jul 10 05:15:33 PM PDT 24
Peak memory 201120 kb
Host smart-78db05cc-68a1-456a-947d-a5f04558366c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826266764 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.3826266764
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.1141698186
Short name T226
Test name
Test status
Simulation time 227852847 ps
CPU time 1.12 seconds
Started Jul 10 05:15:13 PM PDT 24
Finished Jul 10 05:15:18 PM PDT 24
Peak memory 199416 kb
Host smart-35e73243-708b-463c-8752-87e1b88a4915
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141698186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.1141698186
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.3807810744
Short name T462
Test name
Test status
Simulation time 408941930 ps
CPU time 1.14 seconds
Started Jul 10 05:15:07 PM PDT 24
Finished Jul 10 05:15:12 PM PDT 24
Peak memory 200656 kb
Host smart-ecfeba78-3d8a-4bc2-bfa2-a62e606ed66a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807810744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.3807810744
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3877628516
Short name T1000
Test name
Test status
Simulation time 26055924 ps
CPU time 0.89 seconds
Started Jul 10 05:12:42 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 200028 kb
Host smart-74f2ae33-26cb-40e2-a4db-03060dd13791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877628516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3877628516
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2554457694
Short name T885
Test name
Test status
Simulation time 57710594 ps
CPU time 0.7 seconds
Started Jul 10 05:12:38 PM PDT 24
Finished Jul 10 05:12:39 PM PDT 24
Peak memory 198796 kb
Host smart-8eab6c5e-67a3-410e-8e52-b21abf49dcdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554457694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2554457694
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.602883225
Short name T745
Test name
Test status
Simulation time 30248119 ps
CPU time 0.63 seconds
Started Jul 10 05:12:40 PM PDT 24
Finished Jul 10 05:12:42 PM PDT 24
Peak memory 197664 kb
Host smart-f5dc23b3-92ed-4660-94ce-ab558a7d9bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602883225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.602883225
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.1080160701
Short name T445
Test name
Test status
Simulation time 164543610 ps
CPU time 1.06 seconds
Started Jul 10 05:12:44 PM PDT 24
Finished Jul 10 05:12:46 PM PDT 24
Peak memory 197780 kb
Host smart-9b2843d5-5cee-4fc3-a429-c987dc230c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080160701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.1080160701
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.1419238788
Short name T834
Test name
Test status
Simulation time 56341600 ps
CPU time 0.71 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 197060 kb
Host smart-119d42d2-c62e-425c-8dd0-602228011574
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419238788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1419238788
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.698373238
Short name T2
Test name
Test status
Simulation time 49188951 ps
CPU time 0.62 seconds
Started Jul 10 05:12:42 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 197776 kb
Host smart-7c238c8a-ef7c-4380-944e-e7f0d25ec049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698373238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.698373238
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2576512627
Short name T825
Test name
Test status
Simulation time 82710985 ps
CPU time 0.7 seconds
Started Jul 10 05:12:41 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 201004 kb
Host smart-f6682379-5987-4f6d-88fc-7a058d8c0fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576512627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2576512627
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.1778782993
Short name T936
Test name
Test status
Simulation time 163029271 ps
CPU time 1.04 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 198768 kb
Host smart-1d00a232-cc50-45c6-94b0-f0f696a04c22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778782993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.1778782993
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2215088862
Short name T256
Test name
Test status
Simulation time 54147178 ps
CPU time 0.74 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 198188 kb
Host smart-15a75d9e-24f7-40f0-90ab-9e3ebc8b12c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215088862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2215088862
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2810250825
Short name T133
Test name
Test status
Simulation time 123531322 ps
CPU time 0.86 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 209288 kb
Host smart-4ec05ece-e5d2-429d-a8b7-894dad24bf4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810250825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2810250825
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2354184760
Short name T609
Test name
Test status
Simulation time 145974565 ps
CPU time 1.04 seconds
Started Jul 10 05:12:41 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 199740 kb
Host smart-c2816394-de5e-4de9-b524-ba96dd4db80c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354184760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.2354184760
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2039885087
Short name T880
Test name
Test status
Simulation time 1501738772 ps
CPU time 1.82 seconds
Started Jul 10 05:12:44 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 200736 kb
Host smart-876679cf-b23b-462b-96bb-1de214124971
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039885087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2039885087
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1666685620
Short name T204
Test name
Test status
Simulation time 1196569331 ps
CPU time 2.12 seconds
Started Jul 10 05:12:38 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200880 kb
Host smart-d047d634-7031-4706-9b4d-70ed061b39f2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666685620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1666685620
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1036146763
Short name T389
Test name
Test status
Simulation time 57791014 ps
CPU time 0.88 seconds
Started Jul 10 05:12:41 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 199268 kb
Host smart-ff7cd733-adf7-49e8-9f00-22e8b2ab65a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036146763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1036146763
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2805341679
Short name T993
Test name
Test status
Simulation time 58702739 ps
CPU time 0.68 seconds
Started Jul 10 05:12:35 PM PDT 24
Finished Jul 10 05:12:37 PM PDT 24
Peak memory 199068 kb
Host smart-01b2ddc6-f1cd-4151-add5-b49bc6233d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805341679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2805341679
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.3617809915
Short name T425
Test name
Test status
Simulation time 597159518 ps
CPU time 2.81 seconds
Started Jul 10 05:12:44 PM PDT 24
Finished Jul 10 05:12:48 PM PDT 24
Peak memory 200812 kb
Host smart-42f4556a-c31d-42c5-a73f-b9ef1ee4b6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617809915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3617809915
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1167918288
Short name T86
Test name
Test status
Simulation time 5519371313 ps
CPU time 17.05 seconds
Started Jul 10 05:12:40 PM PDT 24
Finished Jul 10 05:12:59 PM PDT 24
Peak memory 201068 kb
Host smart-255f660e-57b5-42a9-b345-32c619b48c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167918288 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.1167918288
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.3250052218
Short name T449
Test name
Test status
Simulation time 231631710 ps
CPU time 0.86 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 198848 kb
Host smart-89c45072-3c75-4688-af2f-0f461d6fa036
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250052218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.3250052218
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.2832754317
Short name T551
Test name
Test status
Simulation time 174235378 ps
CPU time 1 seconds
Started Jul 10 05:12:39 PM PDT 24
Finished Jul 10 05:12:42 PM PDT 24
Peak memory 199304 kb
Host smart-3e099c26-568d-43a8-8753-ee586b3f27bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832754317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.2832754317
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.2996642458
Short name T533
Test name
Test status
Simulation time 42702694 ps
CPU time 0.64 seconds
Started Jul 10 05:12:48 PM PDT 24
Finished Jul 10 05:12:50 PM PDT 24
Peak memory 199200 kb
Host smart-dd788334-baca-4960-bbe5-22292e9d9e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996642458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2996642458
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3373932771
Short name T850
Test name
Test status
Simulation time 72779029 ps
CPU time 0.71 seconds
Started Jul 10 05:12:46 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 198128 kb
Host smart-353a37fc-fd9e-4d42-9d3b-2c19e8336035
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373932771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.3373932771
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.4176714468
Short name T301
Test name
Test status
Simulation time 27713665 ps
CPU time 0.64 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:52 PM PDT 24
Peak memory 196944 kb
Host smart-44fa52e6-5020-476b-80c5-54143be8d7c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176714468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.4176714468
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.1262956458
Short name T593
Test name
Test status
Simulation time 165661686 ps
CPU time 1.03 seconds
Started Jul 10 05:12:52 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 198120 kb
Host smart-0b304d71-db59-4202-ad6a-13d4217f78c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262956458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1262956458
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.2377003452
Short name T292
Test name
Test status
Simulation time 49064254 ps
CPU time 0.66 seconds
Started Jul 10 05:12:46 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 197764 kb
Host smart-fd2f7916-0329-46d7-8679-d65c7c5b6bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377003452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.2377003452
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1462549189
Short name T749
Test name
Test status
Simulation time 49463413 ps
CPU time 0.57 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 197648 kb
Host smart-e5fbab82-22b3-4af7-8844-35f4ac6368e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462549189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1462549189
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2171605670
Short name T668
Test name
Test status
Simulation time 48156193 ps
CPU time 0.69 seconds
Started Jul 10 05:12:47 PM PDT 24
Finished Jul 10 05:12:49 PM PDT 24
Peak memory 200936 kb
Host smart-8104236e-0446-4cad-b32f-f765d0b1aef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171605670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2171605670
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.3161952981
Short name T404
Test name
Test status
Simulation time 403862427 ps
CPU time 0.97 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 199360 kb
Host smart-572b6f82-e7ef-4f58-a84c-cbcbac390d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161952981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.3161952981
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.4202143962
Short name T627
Test name
Test status
Simulation time 63197387 ps
CPU time 0.69 seconds
Started Jul 10 05:12:52 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 197964 kb
Host smart-894e2b6c-aa77-4cf4-bf8c-ee2c0d923072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202143962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.4202143962
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1615804066
Short name T971
Test name
Test status
Simulation time 93235168 ps
CPU time 1.06 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:52 PM PDT 24
Peak memory 209172 kb
Host smart-59c783ae-e338-4532-a0ae-13ef1e72c1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615804066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1615804066
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2479562075
Short name T614
Test name
Test status
Simulation time 68578913 ps
CPU time 0.69 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 199024 kb
Host smart-3a50ad5a-2d99-45eb-af9a-3e503bba025d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479562075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.2479562075
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2131445088
Short name T332
Test name
Test status
Simulation time 1193013044 ps
CPU time 2.27 seconds
Started Jul 10 05:12:45 PM PDT 24
Finished Jul 10 05:12:48 PM PDT 24
Peak memory 200804 kb
Host smart-7019e827-95fb-470a-80d9-5e49161f196d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131445088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2131445088
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4202244685
Short name T222
Test name
Test status
Simulation time 897807777 ps
CPU time 3.4 seconds
Started Jul 10 05:12:49 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 200816 kb
Host smart-6eb5c42e-569b-406c-9e59-5d5cf5b0d0f8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202244685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4202244685
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.126114614
Short name T909
Test name
Test status
Simulation time 244238777 ps
CPU time 0.84 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 198944 kb
Host smart-b6ffbf92-cb9d-4560-845a-24e0a92db913
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126114614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.126114614
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1430220595
Short name T138
Test name
Test status
Simulation time 38367933 ps
CPU time 0.65 seconds
Started Jul 10 05:12:45 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 198204 kb
Host smart-06fdde95-c423-49f7-8725-b18b3b434d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430220595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1430220595
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.92050686
Short name T995
Test name
Test status
Simulation time 2326420321 ps
CPU time 3.44 seconds
Started Jul 10 05:12:44 PM PDT 24
Finished Jul 10 05:12:49 PM PDT 24
Peak memory 200900 kb
Host smart-4ac43b15-f2bd-4576-bccc-d1c663a3ad1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92050686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.92050686
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.409306437
Short name T737
Test name
Test status
Simulation time 3497065185 ps
CPU time 10.53 seconds
Started Jul 10 05:12:48 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 201044 kb
Host smart-b36c4791-e0c1-48d1-be59-a6022ff37045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409306437 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.409306437
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.3982481803
Short name T754
Test name
Test status
Simulation time 305684901 ps
CPU time 1.36 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:52 PM PDT 24
Peak memory 199168 kb
Host smart-3491e8d9-a6f6-4d95-90ca-838532106922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982481803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3982481803
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.3996478559
Short name T558
Test name
Test status
Simulation time 163877168 ps
CPU time 1.12 seconds
Started Jul 10 05:12:44 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 199520 kb
Host smart-954f683b-a818-4c52-8add-0d8dd6b00a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996478559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.3996478559
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2061491401
Short name T470
Test name
Test status
Simulation time 56320353 ps
CPU time 0.75 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 198608 kb
Host smart-918114a9-734f-42dd-9c1c-c3e56c457305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061491401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2061491401
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3523732942
Short name T786
Test name
Test status
Simulation time 63838055 ps
CPU time 0.87 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 198872 kb
Host smart-cd33c735-1b82-452b-87c2-3e601edd2fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523732942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.3523732942
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3644717707
Short name T233
Test name
Test status
Simulation time 30964134 ps
CPU time 0.63 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 197960 kb
Host smart-d362c385-7fd8-4911-948e-6599f928e290
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644717707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.3644717707
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.67880972
Short name T741
Test name
Test status
Simulation time 2974272422 ps
CPU time 0.99 seconds
Started Jul 10 05:12:55 PM PDT 24
Finished Jul 10 05:12:59 PM PDT 24
Peak memory 197904 kb
Host smart-41afd945-af23-47c8-be59-aa93bace379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67880972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.67880972
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3089490801
Short name T560
Test name
Test status
Simulation time 109074304 ps
CPU time 0.62 seconds
Started Jul 10 05:12:53 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 197828 kb
Host smart-f5042834-862e-4ca5-8cbb-fec30e65a4ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089490801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3089490801
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.3090407894
Short name T644
Test name
Test status
Simulation time 22998539 ps
CPU time 0.61 seconds
Started Jul 10 05:12:53 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 197700 kb
Host smart-2b05522f-3cff-45e1-adea-e1c6dd2f9c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090407894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3090407894
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2152394535
Short name T326
Test name
Test status
Simulation time 44277110 ps
CPU time 0.77 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 201060 kb
Host smart-9492d1bd-ab89-4eab-b540-bafa7d51b698
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152394535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2152394535
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.585405502
Short name T990
Test name
Test status
Simulation time 110369826 ps
CPU time 0.69 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 198852 kb
Host smart-64b019bc-3541-446b-8896-7acbaf167de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585405502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wak
eup_race.585405502
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.267061307
Short name T300
Test name
Test status
Simulation time 85780892 ps
CPU time 1 seconds
Started Jul 10 05:12:48 PM PDT 24
Finished Jul 10 05:12:50 PM PDT 24
Peak memory 199576 kb
Host smart-f5039aa8-da8d-4ab6-bbc4-eb32249dcfd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267061307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.267061307
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3078808857
Short name T384
Test name
Test status
Simulation time 99940334 ps
CPU time 0.95 seconds
Started Jul 10 05:12:52 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 209284 kb
Host smart-b098edd2-82bb-4968-8718-517cb19eb6fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078808857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3078808857
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3826515663
Short name T511
Test name
Test status
Simulation time 237059946 ps
CPU time 0.99 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 199864 kb
Host smart-091be2e6-d9e1-4f7a-bd7e-c7ec70310f70
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826515663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.3826515663
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3194186805
Short name T785
Test name
Test status
Simulation time 800536924 ps
CPU time 2.83 seconds
Started Jul 10 05:12:54 PM PDT 24
Finished Jul 10 05:12:58 PM PDT 24
Peak memory 200692 kb
Host smart-c0817d25-53fc-48ab-ab02-6d6a537f8956
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194186805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3194186805
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4287976553
Short name T388
Test name
Test status
Simulation time 914806684 ps
CPU time 3.17 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:56 PM PDT 24
Peak memory 200852 kb
Host smart-7eb20c11-ef23-4b02-89a0-a4af10177896
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287976553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4287976553
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1228046659
Short name T493
Test name
Test status
Simulation time 95077376 ps
CPU time 0.93 seconds
Started Jul 10 05:12:55 PM PDT 24
Finished Jul 10 05:12:59 PM PDT 24
Peak memory 199080 kb
Host smart-e627e31d-2e90-460c-afed-531277aba0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228046659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1228046659
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3673645541
Short name T514
Test name
Test status
Simulation time 37022823 ps
CPU time 0.63 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 198068 kb
Host smart-4c6865b2-c242-44c3-8951-63efd5ed238f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673645541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3673645541
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.270551975
Short name T413
Test name
Test status
Simulation time 1174170140 ps
CPU time 2.98 seconds
Started Jul 10 05:12:52 PM PDT 24
Finished Jul 10 05:12:57 PM PDT 24
Peak memory 200884 kb
Host smart-9050601b-f9a2-4112-a8f6-0e0164031547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270551975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.270551975
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.4192236416
Short name T721
Test name
Test status
Simulation time 12172346237 ps
CPU time 13.91 seconds
Started Jul 10 05:12:49 PM PDT 24
Finished Jul 10 05:13:04 PM PDT 24
Peak memory 200984 kb
Host smart-6fabe360-55e2-47a1-815a-fe0f59d01a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192236416 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.4192236416
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.95810616
Short name T432
Test name
Test status
Simulation time 185972331 ps
CPU time 0.67 seconds
Started Jul 10 05:12:55 PM PDT 24
Finished Jul 10 05:12:58 PM PDT 24
Peak memory 198400 kb
Host smart-a9b56a03-1501-421f-bb0a-dafd8ac17ab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95810616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.95810616
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.782905785
Short name T552
Test name
Test status
Simulation time 201241586 ps
CPU time 0.79 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:53 PM PDT 24
Peak memory 198832 kb
Host smart-1464dd20-4775-4613-a3f0-0ff681adf714
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782905785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.782905785
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1619445362
Short name T955
Test name
Test status
Simulation time 166074300 ps
CPU time 0.88 seconds
Started Jul 10 05:12:54 PM PDT 24
Finished Jul 10 05:12:57 PM PDT 24
Peak memory 199864 kb
Host smart-41347273-97a1-4c3a-8d40-0397820f5b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619445362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1619445362
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1293367660
Short name T587
Test name
Test status
Simulation time 65508572 ps
CPU time 0.85 seconds
Started Jul 10 05:12:56 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 198832 kb
Host smart-83e30fe6-ae9f-4976-aa0c-7640a2307f48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293367660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1293367660
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.409397318
Short name T929
Test name
Test status
Simulation time 32156851 ps
CPU time 0.6 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:01 PM PDT 24
Peak memory 196944 kb
Host smart-7606ddce-8e2c-4d38-9863-ce8f0b0d1c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409397318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m
alfunc.409397318
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.1359554058
Short name T582
Test name
Test status
Simulation time 165277234 ps
CPU time 1.03 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:04 PM PDT 24
Peak memory 198120 kb
Host smart-a4b5570f-c7e5-4faa-8ab3-c6438b9e16f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359554058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1359554058
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2402404985
Short name T799
Test name
Test status
Simulation time 51645374 ps
CPU time 0.73 seconds
Started Jul 10 05:12:56 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 197820 kb
Host smart-274f3ec6-328f-4b42-8536-35e7beed0f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402404985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2402404985
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.4168519013
Short name T860
Test name
Test status
Simulation time 30588390 ps
CPU time 0.69 seconds
Started Jul 10 05:12:57 PM PDT 24
Finished Jul 10 05:13:01 PM PDT 24
Peak memory 198016 kb
Host smart-9d4477e8-7805-430f-a7b0-61fa99852cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168519013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.4168519013
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.794225929
Short name T42
Test name
Test status
Simulation time 49100105 ps
CPU time 0.72 seconds
Started Jul 10 05:12:56 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 201124 kb
Host smart-2ef9307d-c4f3-468e-87f3-5cd1c4bc80f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794225929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.794225929
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.4089647208
Short name T642
Test name
Test status
Simulation time 56098809 ps
CPU time 0.79 seconds
Started Jul 10 05:12:55 PM PDT 24
Finished Jul 10 05:12:58 PM PDT 24
Peak memory 198028 kb
Host smart-f4859c16-14f0-4a66-be3e-913f0b5b0eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089647208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.4089647208
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.479446679
Short name T509
Test name
Test status
Simulation time 75246362 ps
CPU time 0.98 seconds
Started Jul 10 05:12:52 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 199740 kb
Host smart-1bf0e497-4508-41c2-9345-1cc60b283282
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479446679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.479446679
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.3003305065
Short name T210
Test name
Test status
Simulation time 108080534 ps
CPU time 0.96 seconds
Started Jul 10 05:12:56 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 209208 kb
Host smart-93a60e43-6ee9-40fd-b421-367062556d09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003305065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3003305065
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.4071833067
Short name T922
Test name
Test status
Simulation time 245738926 ps
CPU time 0.74 seconds
Started Jul 10 05:12:57 PM PDT 24
Finished Jul 10 05:13:01 PM PDT 24
Peak memory 198356 kb
Host smart-b4eef825-f5f6-42f2-8521-9b907495acff
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071833067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.4071833067
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4097995662
Short name T243
Test name
Test status
Simulation time 1463587044 ps
CPU time 1.77 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 200604 kb
Host smart-1f9d424d-6d6c-4116-a893-7fbd9c2347ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097995662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4097995662
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3333707865
Short name T817
Test name
Test status
Simulation time 794551777 ps
CPU time 3.23 seconds
Started Jul 10 05:12:57 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 200616 kb
Host smart-fad4d36b-4144-4a65-9e73-316a5273fa7c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333707865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3333707865
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1263372862
Short name T298
Test name
Test status
Simulation time 103009391 ps
CPU time 0.96 seconds
Started Jul 10 05:12:51 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 199036 kb
Host smart-35cb2e05-aad2-43c9-a025-f6e3f334d111
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263372862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1263372862
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2471855474
Short name T904
Test name
Test status
Simulation time 55123577 ps
CPU time 0.64 seconds
Started Jul 10 05:12:54 PM PDT 24
Finished Jul 10 05:12:56 PM PDT 24
Peak memory 198984 kb
Host smart-4f3082bf-659b-486e-9902-68f2efdbc8c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471855474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2471855474
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.1290027335
Short name T692
Test name
Test status
Simulation time 2473860725 ps
CPU time 4.85 seconds
Started Jul 10 05:13:00 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 201000 kb
Host smart-b2f372a4-ee74-4135-863e-148fdf3b6326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290027335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1290027335
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1330321194
Short name T82
Test name
Test status
Simulation time 4370319034 ps
CPU time 9.95 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:13 PM PDT 24
Peak memory 200960 kb
Host smart-cb54114a-9d51-4bf3-8a5c-a110a7dd5999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330321194 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.1330321194
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.1860487740
Short name T74
Test name
Test status
Simulation time 385976488 ps
CPU time 1.01 seconds
Started Jul 10 05:12:54 PM PDT 24
Finished Jul 10 05:12:57 PM PDT 24
Peak memory 199400 kb
Host smart-7d578ffc-d4ef-4864-851e-ffe418982a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860487740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.1860487740
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.2838252448
Short name T666
Test name
Test status
Simulation time 179217144 ps
CPU time 1.06 seconds
Started Jul 10 05:12:50 PM PDT 24
Finished Jul 10 05:12:52 PM PDT 24
Peak memory 199928 kb
Host smart-f2e99420-704d-411e-9c7d-a8852b3757ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838252448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.2838252448
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.328540916
Short name T680
Test name
Test status
Simulation time 29462779 ps
CPU time 0.73 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 198496 kb
Host smart-09370ccd-6731-41dc-a82f-397c75feb0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328540916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.328540916
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2825737719
Short name T169
Test name
Test status
Simulation time 63246167 ps
CPU time 0.85 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 198724 kb
Host smart-94edb548-359e-4b41-abdd-0a99fd96022f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825737719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2825737719
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3606586394
Short name T135
Test name
Test status
Simulation time 38063482 ps
CPU time 0.59 seconds
Started Jul 10 05:12:55 PM PDT 24
Finished Jul 10 05:12:59 PM PDT 24
Peak memory 197748 kb
Host smart-4fe6b1f1-7aa1-47b0-8b32-6ebd667d2e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606586394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3606586394
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3207332646
Short name T871
Test name
Test status
Simulation time 317607719 ps
CPU time 0.95 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 197816 kb
Host smart-a93a2ea1-5a02-4a19-aba0-4bfd0b4de701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207332646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3207332646
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.3597986059
Short name T252
Test name
Test status
Simulation time 39936110 ps
CPU time 0.69 seconds
Started Jul 10 05:12:57 PM PDT 24
Finished Jul 10 05:13:01 PM PDT 24
Peak memory 197792 kb
Host smart-d261a788-92b3-4e04-9a3b-c9baa98bac56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597986059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3597986059
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.1893682353
Short name T870
Test name
Test status
Simulation time 23811266 ps
CPU time 0.65 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:01 PM PDT 24
Peak memory 198020 kb
Host smart-d40ef7a6-6384-4ec3-a12c-73ee2d508d3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893682353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1893682353
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3958447468
Short name T888
Test name
Test status
Simulation time 42747353 ps
CPU time 0.74 seconds
Started Jul 10 05:13:02 PM PDT 24
Finished Jul 10 05:13:06 PM PDT 24
Peak memory 201084 kb
Host smart-7b099a0a-e536-408f-a97a-8f9cc8fba810
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958447468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3958447468
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.2466288855
Short name T617
Test name
Test status
Simulation time 356175131 ps
CPU time 0.97 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 199260 kb
Host smart-ee303b49-c282-433e-987d-f1a2da07c81e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466288855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.2466288855
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1605718533
Short name T939
Test name
Test status
Simulation time 59360136 ps
CPU time 0.96 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 199344 kb
Host smart-1cc87130-8441-44ab-b002-f19a1be689f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605718533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1605718533
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.1051600095
Short name T218
Test name
Test status
Simulation time 132826012 ps
CPU time 0.82 seconds
Started Jul 10 05:13:00 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 209216 kb
Host smart-7771f950-f1ed-4c64-bc67-553abd96f83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051600095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1051600095
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.844450841
Short name T689
Test name
Test status
Simulation time 116335342 ps
CPU time 0.88 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 198444 kb
Host smart-9a9aaf66-219c-4c1e-9743-153a6943f821
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844450841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm
_ctrl_config_regwen.844450841
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.593197585
Short name T918
Test name
Test status
Simulation time 766453814 ps
CPU time 2.8 seconds
Started Jul 10 05:13:01 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 200712 kb
Host smart-69d6ea20-be8e-4558-8474-e8382865f91d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593197585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.593197585
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.727661742
Short name T11
Test name
Test status
Simulation time 905602894 ps
CPU time 3.29 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 200816 kb
Host smart-45abe717-a160-4cc8-9673-589c7eaea379
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727661742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.727661742
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797826736
Short name T303
Test name
Test status
Simulation time 84936454 ps
CPU time 0.83 seconds
Started Jul 10 05:13:01 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 198928 kb
Host smart-50308f60-a7ea-40e1-910c-daf2362c3cc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797826736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3797826736
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.863291277
Short name T970
Test name
Test status
Simulation time 29028126 ps
CPU time 0.75 seconds
Started Jul 10 05:12:59 PM PDT 24
Finished Jul 10 05:13:02 PM PDT 24
Peak memory 198992 kb
Host smart-535dcb25-d32b-412b-93b2-a986c5fd4ad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863291277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.863291277
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.3443209904
Short name T705
Test name
Test status
Simulation time 722561108 ps
CPU time 3.06 seconds
Started Jul 10 05:13:03 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200948 kb
Host smart-48df2221-e274-423c-a830-01ee7e8cd4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443209904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.3443209904
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2616044333
Short name T87
Test name
Test status
Simulation time 4014170148 ps
CPU time 13.7 seconds
Started Jul 10 05:13:01 PM PDT 24
Finished Jul 10 05:13:19 PM PDT 24
Peak memory 200976 kb
Host smart-aa774d57-d0e1-4254-9784-33c5efac88df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616044333 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.2616044333
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.2060162617
Short name T623
Test name
Test status
Simulation time 193301684 ps
CPU time 0.83 seconds
Started Jul 10 05:13:00 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 198152 kb
Host smart-c68e3899-a42a-4764-88aa-af31cfd0b758
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060162617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2060162617
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.382362207
Short name T819
Test name
Test status
Simulation time 478320853 ps
CPU time 1.23 seconds
Started Jul 10 05:12:58 PM PDT 24
Finished Jul 10 05:13:02 PM PDT 24
Peak memory 200716 kb
Host smart-4516319d-6f76-473a-9514-db2c346284c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382362207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.382362207
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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