Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32473

1

T1

6

T2

1

T4

4

auto[1]

31200

1

T1

5

T2

5

T4

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32554

1

T1

6

T2

1

T4

4

auto[1]

31119

1

T1

5

T2

5

T4

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30925

1

T1

7

T2

2

T4

4

auto[1]

32748

1

T1

4

T2

4

T4

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35736

1

T1

11

T2

4

T4

4

auto[1]

27937

1

T2

2

T4

4

T6

43

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31322

1

T1

4

T2

2

T4

4

auto[1]

32351

1

T1

7

T2

4

T4

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32371

1

T1

7

T2

1

T4

2

auto[1]

31302

1

T1

4

T2

5

T4

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1022

1

T6

2

T9

1

T10

25

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

785

1

T6

2

T9

1

T10

19

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1083

1

T6

2

T9

5

T10

29

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

859

1

T6

2

T9

5

T10

23

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1110

1

T1

2

T9

2

T10

34

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

874

1

T9

2

T10

29

T22

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1796

1

T6

3

T7

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1549

1

T6

3

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1156

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

891

1

T6

1

T9

1

T10

19

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1065

1

T6

1

T9

2

T10

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

836

1

T6

1

T9

2

T10

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1101

1

T9

2

T10

25

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

865

1

T9

2

T10

15

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1072

1

T6

2

T9

4

T10

36

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

833

1

T6

2

T9

4

T10

26

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1083

1

T1

1

T6

5

T10

32

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

838

1

T6

5

T10

24

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1148

1

T10

25

T37

5

T22

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

863

1

T10

19

T37

5

T22

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1115

1

T6

2

T9

3

T10

26

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

884

1

T6

2

T9

3

T10

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1036

1

T1

2

T6

1

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

808

1

T6

1

T9

2

T10

19

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1111

1

T6

2

T9

1

T10

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

845

1

T6

2

T9

1

T10

30

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1143

1

T4

1

T9

1

T10

27

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

875

1

T4

1

T9

1

T10

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1049

1

T1

1

T9

3

T10

26

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

831

1

T9

3

T10

16

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1100

1

T4

1

T6

1

T10

33

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

847

1

T4

1

T6

1

T10

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1081

1

T1

1

T6

1

T9

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

862

1

T6

1

T9

3

T10

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1141

1

T6

1

T9

3

T10

27

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

895

1

T6

1

T9

3

T10

18

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1077

1

T4

1

T6

3

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

817

1

T4

1

T6

3

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1084

1

T1

1

T6

4

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

845

1

T6

4

T9

1

T10

25

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1067

1

T4

1

T6

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

810

1

T4

1

T6

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1113

1

T1

1

T6

4

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

884

1

T6

4

T9

1

T10

13

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1098

1

T1

1

T10

24

T37

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

854

1

T10

21

T37

2

T59

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1147

1

T9

1

T10

24

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

882

1

T9

1

T10

19

T40

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1059

1

T2

1

T6

1

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

830

1

T6

1

T9

1

T10

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1131

1

T6

1

T9

4

T10

25

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

884

1

T6

1

T9

4

T10

18

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1081

1

T9

2

T10

18

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

859

1

T9

2

T10

12

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1070

1

T6

1

T10

24

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

802

1

T6

1

T10

19

T37

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1114

1

T1

1

T10

30

T37

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

876

1

T10

26

T37

1

T22

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1110

1

T6

1

T9

1

T10

21

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

862

1

T6

1

T9

1

T10

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1059

1

T6

2

T9

1

T10

31

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

821

1

T6

2

T9

1

T10

23

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1114

1

T2

2

T6

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

871

1

T2

2

T6

1

T9

1