Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1119
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1014 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.462863870 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:07 PM PDT 24 139426860 ps
T120 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1262402908 Jul 11 04:36:11 PM PDT 24 Jul 11 04:36:15 PM PDT 24 72694636 ps
T107 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1199636613 Jul 11 04:36:01 PM PDT 24 Jul 11 04:36:04 PM PDT 24 18238137 ps
T1015 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1159432838 Jul 11 04:36:15 PM PDT 24 Jul 11 04:36:18 PM PDT 24 45577697 ps
T1016 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3962496094 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:44 PM PDT 24 64882759 ps
T1017 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2428052024 Jul 11 04:36:15 PM PDT 24 Jul 11 04:36:17 PM PDT 24 49819203 ps
T190 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.291670991 Jul 11 04:35:47 PM PDT 24 Jul 11 04:35:52 PM PDT 24 281376554 ps
T1018 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.488711260 Jul 11 04:36:09 PM PDT 24 Jul 11 04:36:11 PM PDT 24 155704857 ps
T1019 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.829111317 Jul 11 04:36:01 PM PDT 24 Jul 11 04:36:05 PM PDT 24 85122249 ps
T1020 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.679443901 Jul 11 04:36:02 PM PDT 24 Jul 11 04:36:07 PM PDT 24 107339168 ps
T1021 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.566161155 Jul 11 04:35:54 PM PDT 24 Jul 11 04:35:56 PM PDT 24 162701948 ps
T1022 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2034094320 Jul 11 04:36:04 PM PDT 24 Jul 11 04:36:09 PM PDT 24 52851161 ps
T71 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.466772542 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:44 PM PDT 24 234746935 ps
T1023 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2544194657 Jul 11 04:36:11 PM PDT 24 Jul 11 04:36:14 PM PDT 24 141531270 ps
T1024 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.581745616 Jul 11 04:36:09 PM PDT 24 Jul 11 04:36:12 PM PDT 24 129879403 ps
T1025 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3622013516 Jul 11 04:35:41 PM PDT 24 Jul 11 04:35:45 PM PDT 24 91005843 ps
T1026 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2284438370 Jul 11 04:35:58 PM PDT 24 Jul 11 04:36:03 PM PDT 24 55682887 ps
T1027 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1715587660 Jul 11 04:35:58 PM PDT 24 Jul 11 04:36:02 PM PDT 24 71889316 ps
T1028 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1226212917 Jul 11 04:35:41 PM PDT 24 Jul 11 04:35:46 PM PDT 24 34580176 ps
T1029 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.410138188 Jul 11 04:35:44 PM PDT 24 Jul 11 04:35:48 PM PDT 24 54496082 ps
T1030 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1372499610 Jul 11 04:36:10 PM PDT 24 Jul 11 04:36:13 PM PDT 24 45002741 ps
T1031 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1496533589 Jul 11 04:36:12 PM PDT 24 Jul 11 04:36:15 PM PDT 24 43639250 ps
T1032 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.873670336 Jul 11 04:36:04 PM PDT 24 Jul 11 04:36:08 PM PDT 24 43936501 ps
T1033 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3540575988 Jul 11 04:35:44 PM PDT 24 Jul 11 04:35:50 PM PDT 24 216224843 ps
T1034 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1021823976 Jul 11 04:35:59 PM PDT 24 Jul 11 04:36:02 PM PDT 24 38871649 ps
T1035 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3927047272 Jul 11 04:35:52 PM PDT 24 Jul 11 04:35:55 PM PDT 24 19606445 ps
T1036 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3172768800 Jul 11 04:35:46 PM PDT 24 Jul 11 04:35:50 PM PDT 24 26531366 ps
T1037 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3130613523 Jul 11 04:35:57 PM PDT 24 Jul 11 04:36:00 PM PDT 24 94134884 ps
T1038 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3491237985 Jul 11 04:35:58 PM PDT 24 Jul 11 04:36:01 PM PDT 24 94884684 ps
T108 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2626311563 Jul 11 04:35:47 PM PDT 24 Jul 11 04:35:51 PM PDT 24 69014535 ps
T1039 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.337293398 Jul 11 04:36:15 PM PDT 24 Jul 11 04:36:18 PM PDT 24 20532357 ps
T1040 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3365073861 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:44 PM PDT 24 204919507 ps
T1041 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.383433114 Jul 11 04:36:09 PM PDT 24 Jul 11 04:36:11 PM PDT 24 43791402 ps
T1042 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1126376790 Jul 11 04:35:45 PM PDT 24 Jul 11 04:35:50 PM PDT 24 121455034 ps
T1043 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2287933521 Jul 11 04:35:53 PM PDT 24 Jul 11 04:35:56 PM PDT 24 133935283 ps
T1044 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1781620931 Jul 11 04:35:51 PM PDT 24 Jul 11 04:35:54 PM PDT 24 473449776 ps
T1045 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3408588772 Jul 11 04:36:23 PM PDT 24 Jul 11 04:36:25 PM PDT 24 21069951 ps
T1046 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.249280197 Jul 11 04:36:26 PM PDT 24 Jul 11 04:36:28 PM PDT 24 308000687 ps
T1047 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3947496001 Jul 11 04:36:11 PM PDT 24 Jul 11 04:36:14 PM PDT 24 17805417 ps
T1048 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3842921311 Jul 11 04:36:24 PM PDT 24 Jul 11 04:36:26 PM PDT 24 25230505 ps
T1049 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.214746121 Jul 11 04:35:53 PM PDT 24 Jul 11 04:35:56 PM PDT 24 170076359 ps
T109 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.201649161 Jul 11 04:35:56 PM PDT 24 Jul 11 04:35:59 PM PDT 24 45323511 ps
T1050 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2332701509 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:53 PM PDT 24 227387791 ps
T1051 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2688373925 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:07 PM PDT 24 35621187 ps
T72 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4031104596 Jul 11 04:36:01 PM PDT 24 Jul 11 04:36:04 PM PDT 24 192892082 ps
T1052 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.888641759 Jul 11 04:36:14 PM PDT 24 Jul 11 04:36:17 PM PDT 24 19270926 ps
T1053 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2614468587 Jul 11 04:36:04 PM PDT 24 Jul 11 04:36:10 PM PDT 24 210959175 ps
T1054 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3784812443 Jul 11 04:35:41 PM PDT 24 Jul 11 04:35:45 PM PDT 24 33348873 ps
T1055 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2245118899 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:07 PM PDT 24 39917746 ps
T1056 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2610388702 Jul 11 04:35:45 PM PDT 24 Jul 11 04:35:49 PM PDT 24 85808159 ps
T1057 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1971695283 Jul 11 04:36:02 PM PDT 24 Jul 11 04:36:07 PM PDT 24 29902358 ps
T111 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2258573372 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:45 PM PDT 24 169713528 ps
T1058 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1257185871 Jul 11 04:36:17 PM PDT 24 Jul 11 04:36:19 PM PDT 24 46432732 ps
T1059 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1230636029 Jul 11 04:35:45 PM PDT 24 Jul 11 04:35:48 PM PDT 24 102331863 ps
T1060 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3858961731 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:53 PM PDT 24 49260284 ps
T1061 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1940358906 Jul 11 04:35:38 PM PDT 24 Jul 11 04:35:40 PM PDT 24 18219541 ps
T1062 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2622218091 Jul 11 04:35:39 PM PDT 24 Jul 11 04:35:41 PM PDT 24 28573806 ps
T1063 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1946007980 Jul 11 04:35:42 PM PDT 24 Jul 11 04:35:48 PM PDT 24 671136620 ps
T1064 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4016505850 Jul 11 04:35:47 PM PDT 24 Jul 11 04:35:51 PM PDT 24 95817009 ps
T1065 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.337522960 Jul 11 04:35:49 PM PDT 24 Jul 11 04:35:54 PM PDT 24 152761204 ps
T1066 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2148189511 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:08 PM PDT 24 55629335 ps
T1067 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3846914890 Jul 11 04:36:02 PM PDT 24 Jul 11 04:36:08 PM PDT 24 305279174 ps
T1068 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1074019509 Jul 11 04:35:41 PM PDT 24 Jul 11 04:35:45 PM PDT 24 184769584 ps
T1069 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1614923989 Jul 11 04:35:55 PM PDT 24 Jul 11 04:35:59 PM PDT 24 223020491 ps
T1070 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2374639085 Jul 11 04:36:13 PM PDT 24 Jul 11 04:36:16 PM PDT 24 40363316 ps
T1071 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1763697877 Jul 11 04:36:11 PM PDT 24 Jul 11 04:36:15 PM PDT 24 57935599 ps
T1072 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.808514856 Jul 11 04:36:18 PM PDT 24 Jul 11 04:36:20 PM PDT 24 80960579 ps
T1073 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.851449492 Jul 11 04:35:42 PM PDT 24 Jul 11 04:35:47 PM PDT 24 85218170 ps
T1074 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1893414048 Jul 11 04:35:56 PM PDT 24 Jul 11 04:35:58 PM PDT 24 20296624 ps
T1075 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1828868654 Jul 11 04:35:57 PM PDT 24 Jul 11 04:36:00 PM PDT 24 63869532 ps
T110 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1338152203 Jul 11 04:36:17 PM PDT 24 Jul 11 04:36:19 PM PDT 24 20146008 ps
T1076 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2580976106 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:42 PM PDT 24 25757162 ps
T1077 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1777641754 Jul 11 04:35:40 PM PDT 24 Jul 11 04:35:44 PM PDT 24 34764029 ps
T1078 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3271195041 Jul 11 04:35:37 PM PDT 24 Jul 11 04:35:40 PM PDT 24 47500810 ps
T1079 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.729781555 Jul 11 04:36:05 PM PDT 24 Jul 11 04:36:09 PM PDT 24 35340576 ps
T1080 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2091851845 Jul 11 04:35:37 PM PDT 24 Jul 11 04:35:39 PM PDT 24 83169524 ps
T1081 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.520016774 Jul 11 04:36:06 PM PDT 24 Jul 11 04:36:09 PM PDT 24 48137322 ps
T1082 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3248939145 Jul 11 04:35:44 PM PDT 24 Jul 11 04:35:48 PM PDT 24 61534239 ps
T1083 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3177862112 Jul 11 04:36:09 PM PDT 24 Jul 11 04:36:12 PM PDT 24 66011040 ps
T1084 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4109713614 Jul 11 04:36:10 PM PDT 24 Jul 11 04:36:13 PM PDT 24 44181643 ps
T1085 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2566615943 Jul 11 04:35:59 PM PDT 24 Jul 11 04:36:02 PM PDT 24 16625951 ps
T1086 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1118322125 Jul 11 04:36:19 PM PDT 24 Jul 11 04:36:21 PM PDT 24 19329723 ps
T1087 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1462568330 Jul 11 04:35:45 PM PDT 24 Jul 11 04:35:50 PM PDT 24 110529878 ps
T112 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1337348445 Jul 11 04:35:57 PM PDT 24 Jul 11 04:35:59 PM PDT 24 50492992 ps
T1088 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.4067175750 Jul 11 04:36:02 PM PDT 24 Jul 11 04:36:07 PM PDT 24 33662410 ps
T1089 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.197202716 Jul 11 04:36:01 PM PDT 24 Jul 11 04:36:05 PM PDT 24 18941213 ps
T1090 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1747475333 Jul 11 04:36:02 PM PDT 24 Jul 11 04:36:06 PM PDT 24 75904110 ps
T1091 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3412984859 Jul 11 04:35:51 PM PDT 24 Jul 11 04:35:55 PM PDT 24 109425326 ps
T113 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2859166140 Jul 11 04:35:46 PM PDT 24 Jul 11 04:35:50 PM PDT 24 16343174 ps
T1092 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1664578587 Jul 11 04:36:06 PM PDT 24 Jul 11 04:36:10 PM PDT 24 34628439 ps
T1093 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.978242876 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:51 PM PDT 24 22002931 ps
T1094 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.170178255 Jul 11 04:36:15 PM PDT 24 Jul 11 04:36:18 PM PDT 24 128345105 ps
T1095 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.31864042 Jul 11 04:35:46 PM PDT 24 Jul 11 04:35:50 PM PDT 24 66110904 ps
T1096 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1021859156 Jul 11 04:35:46 PM PDT 24 Jul 11 04:35:55 PM PDT 24 85128308 ps
T1097 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2519814653 Jul 11 04:36:10 PM PDT 24 Jul 11 04:36:13 PM PDT 24 144922208 ps
T1098 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1659257858 Jul 11 04:35:54 PM PDT 24 Jul 11 04:35:58 PM PDT 24 108475113 ps
T114 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2831638008 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:52 PM PDT 24 35141050 ps
T1099 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1850886065 Jul 11 04:36:10 PM PDT 24 Jul 11 04:36:13 PM PDT 24 101855132 ps
T1100 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1257335964 Jul 11 04:36:15 PM PDT 24 Jul 11 04:36:18 PM PDT 24 90481820 ps
T1101 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2948627797 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:52 PM PDT 24 27931554 ps
T1102 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2113614165 Jul 11 04:36:13 PM PDT 24 Jul 11 04:36:16 PM PDT 24 42112478 ps
T1103 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2262474548 Jul 11 04:35:56 PM PDT 24 Jul 11 04:35:58 PM PDT 24 19328248 ps
T1104 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2049319655 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:08 PM PDT 24 43468244 ps
T1105 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.859989350 Jul 11 04:35:44 PM PDT 24 Jul 11 04:35:48 PM PDT 24 18534199 ps
T1106 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2891646778 Jul 11 04:36:11 PM PDT 24 Jul 11 04:36:14 PM PDT 24 53626523 ps
T1107 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1378977306 Jul 11 04:35:44 PM PDT 24 Jul 11 04:35:47 PM PDT 24 18911018 ps
T73 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1478103656 Jul 11 04:35:43 PM PDT 24 Jul 11 04:35:47 PM PDT 24 342377317 ps
T1108 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3059750469 Jul 11 04:36:04 PM PDT 24 Jul 11 04:36:10 PM PDT 24 71395198 ps
T1109 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.656481253 Jul 11 04:35:39 PM PDT 24 Jul 11 04:35:42 PM PDT 24 22044953 ps
T1110 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.892705633 Jul 11 04:36:03 PM PDT 24 Jul 11 04:36:08 PM PDT 24 35862830 ps
T1111 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2406493103 Jul 11 04:35:58 PM PDT 24 Jul 11 04:36:02 PM PDT 24 175641909 ps
T1112 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.4211987090 Jul 11 04:36:01 PM PDT 24 Jul 11 04:36:09 PM PDT 24 40874977 ps
T1113 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3952539623 Jul 11 04:35:41 PM PDT 24 Jul 11 04:35:45 PM PDT 24 108479441 ps
T1114 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3996021517 Jul 11 04:35:56 PM PDT 24 Jul 11 04:35:59 PM PDT 24 46844744 ps
T1115 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1655995858 Jul 11 04:35:57 PM PDT 24 Jul 11 04:36:00 PM PDT 24 73006783 ps
T1116 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3444913174 Jul 11 04:35:54 PM PDT 24 Jul 11 04:35:56 PM PDT 24 20998556 ps
T1117 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1729174862 Jul 11 04:35:50 PM PDT 24 Jul 11 04:35:53 PM PDT 24 22675612 ps
T1118 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1433445555 Jul 11 04:36:14 PM PDT 24 Jul 11 04:36:17 PM PDT 24 85767354 ps
T1119 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.532127024 Jul 11 04:35:48 PM PDT 24 Jul 11 04:35:52 PM PDT 24 467316620 ps

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3097602795
Short name T10
Test name
Test status
Simulation time 18661500529 ps
CPU time 25.52 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 201032 kb
Host smart-5e71fb3d-de69-4284-a14b-a860b0fc44dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097602795 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.3097602795
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3308786144
Short name T25
Test name
Test status
Simulation time 152337568 ps
CPU time 0.76 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 209100 kb
Host smart-21f4b4d6-9e4a-4866-88c3-7c672d7d59be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308786144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3308786144
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2488046739
Short name T19
Test name
Test status
Simulation time 689214388 ps
CPU time 1.66 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 217416 kb
Host smart-32d4eac5-b419-40ba-89a8-8a6b67f6bc47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488046739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2488046739
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4243080002
Short name T22
Test name
Test status
Simulation time 2249060397 ps
CPU time 2.04 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 200876 kb
Host smart-b59a7f6f-2314-4aff-b80a-071ea350ad24
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243080002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4243080002
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2261464848
Short name T50
Test name
Test status
Simulation time 516859995 ps
CPU time 1.5 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 200500 kb
Host smart-84d4586d-c80d-4be3-83d6-5fec933eebcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261464848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.2261464848
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.748632398
Short name T207
Test name
Test status
Simulation time 39755844 ps
CPU time 0.76 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:58 PM PDT 24
Peak memory 201076 kb
Host smart-3dba1776-c214-4237-86e3-b9ed141129b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748632398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.748632398
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.102315498
Short name T55
Test name
Test status
Simulation time 9497768143 ps
CPU time 27.43 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 200972 kb
Host smart-4cc807a5-8fe5-421c-865d-ac06943f323f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102315498 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.102315498
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.2933408414
Short name T13
Test name
Test status
Simulation time 2873211188 ps
CPU time 4.91 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 200840 kb
Host smart-5969bb3b-d0a3-424d-9181-0426ca8db1c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933408414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.2933408414
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2446858086
Short name T67
Test name
Test status
Simulation time 42463676 ps
CPU time 0.61 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194888 kb
Host smart-01493a1c-c428-4797-afbe-1b1f49451998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446858086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2446858086
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1560195862
Short name T102
Test name
Test status
Simulation time 100906102 ps
CPU time 0.65 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:43 PM PDT 24
Peak memory 197284 kb
Host smart-a53ded05-29df-42f6-a893-eb0bb72b7ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560195862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1560195862
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1979847968
Short name T137
Test name
Test status
Simulation time 3009495060 ps
CPU time 0.99 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 197744 kb
Host smart-e9090710-ae66-4e92-99c3-98fd37fa9878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979847968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1979847968
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1129196744
Short name T65
Test name
Test status
Simulation time 106490825 ps
CPU time 2.55 seconds
Started Jul 11 04:35:34 PM PDT 24
Finished Jul 11 04:35:38 PM PDT 24
Peak memory 200556 kb
Host smart-7bb8cb3f-811b-4d63-bff5-0aa40f880b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129196744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1129196744
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.570287496
Short name T220
Test name
Test status
Simulation time 326339660 ps
CPU time 1.32 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 199832 kb
Host smart-e81aa720-9625-4e5b-9004-a0cdad9a48e3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570287496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm
_ctrl_config_regwen.570287496
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1479717342
Short name T187
Test name
Test status
Simulation time 83132684 ps
CPU time 0.71 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 198284 kb
Host smart-a8626b34-7e8b-4174-8c5b-492f156c0d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479717342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1479717342
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2871865458
Short name T74
Test name
Test status
Simulation time 7780013929 ps
CPU time 29.55 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:56:01 PM PDT 24
Peak memory 200992 kb
Host smart-328bbb17-3508-46ad-8502-08bad8097dea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871865458 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.2871865458
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1478103656
Short name T73
Test name
Test status
Simulation time 342377317 ps
CPU time 1.43 seconds
Started Jul 11 04:35:43 PM PDT 24
Finished Jul 11 04:35:47 PM PDT 24
Peak memory 200548 kb
Host smart-0114d049-8a7a-4dce-9256-e69a168d6dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478103656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1478103656
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.530080775
Short name T106
Test name
Test status
Simulation time 18176182 ps
CPU time 0.66 seconds
Started Jul 11 04:35:54 PM PDT 24
Finished Jul 11 04:35:57 PM PDT 24
Peak memory 197300 kb
Host smart-9303fd80-a43c-4495-ac51-5777da2b386c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530080775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.530080775
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3927047272
Short name T1035
Test name
Test status
Simulation time 19606445 ps
CPU time 0.68 seconds
Started Jul 11 04:35:52 PM PDT 24
Finished Jul 11 04:35:55 PM PDT 24
Peak memory 194988 kb
Host smart-84d283e8-f6e0-4f05-a912-1925707c41f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927047272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3927047272
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2082522474
Short name T202
Test name
Test status
Simulation time 64983846 ps
CPU time 0.83 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 198700 kb
Host smart-0a8f7d45-35cd-4579-ba61-9fc0e319c118
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082522474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2082522474
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.3355762946
Short name T373
Test name
Test status
Simulation time 53900878 ps
CPU time 0.85 seconds
Started Jul 11 04:57:16 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 198868 kb
Host smart-7ed3470b-7fe3-4a97-95a8-9c4b3c141885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355762946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.3355762946
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3376233854
Short name T206
Test name
Test status
Simulation time 64291427 ps
CPU time 0.86 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 198644 kb
Host smart-45ff4db1-d1d0-429a-b04c-36175184a8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376233854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3376233854
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2850540283
Short name T14
Test name
Test status
Simulation time 42579847 ps
CPU time 0.64 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 197100 kb
Host smart-d047ac96-d6a9-4716-9862-985e1b3372ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850540283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2850540283
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.190739748
Short name T105
Test name
Test status
Simulation time 69860862 ps
CPU time 0.89 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:43 PM PDT 24
Peak memory 194932 kb
Host smart-252023b5-0ee2-460a-8eed-b6ba3f0bbf47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190739748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.190739748
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2258573372
Short name T111
Test name
Test status
Simulation time 169713528 ps
CPU time 2.02 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 199940 kb
Host smart-65fb998e-2d90-4983-9728-187c7e1db0dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258573372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.2
258573372
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2091851845
Short name T1080
Test name
Test status
Simulation time 83169524 ps
CPU time 0.65 seconds
Started Jul 11 04:35:37 PM PDT 24
Finished Jul 11 04:35:39 PM PDT 24
Peak memory 198304 kb
Host smart-1bb4ad2e-6e19-496e-8613-c871c0ad4b36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091851845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
091851845
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3130613523
Short name T1037
Test name
Test status
Simulation time 94134884 ps
CPU time 1.25 seconds
Started Jul 11 04:35:57 PM PDT 24
Finished Jul 11 04:36:00 PM PDT 24
Peak memory 198164 kb
Host smart-19f4e5b7-a988-42b9-8d7b-b7b6d42ba28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130613523 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3130613523
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2622218091
Short name T1062
Test name
Test status
Simulation time 28573806 ps
CPU time 0.61 seconds
Started Jul 11 04:35:39 PM PDT 24
Finished Jul 11 04:35:41 PM PDT 24
Peak memory 195136 kb
Host smart-21faf782-c307-4d4c-b1dd-394ebf0e14bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622218091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2622218091
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3022741523
Short name T66
Test name
Test status
Simulation time 18099245 ps
CPU time 0.6 seconds
Started Jul 11 04:35:29 PM PDT 24
Finished Jul 11 04:35:30 PM PDT 24
Peak memory 194896 kb
Host smart-93e42bd9-2cfb-40b2-8335-8683e5187bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022741523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3022741523
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2262474548
Short name T1103
Test name
Test status
Simulation time 19328248 ps
CPU time 0.72 seconds
Started Jul 11 04:35:56 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 197304 kb
Host smart-e2e39fce-b7ed-4feb-8046-f6400dc840ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262474548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2262474548
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2332701509
Short name T1050
Test name
Test status
Simulation time 227387791 ps
CPU time 1.14 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 195312 kb
Host smart-2ac8c9f0-6133-4f0d-ba5b-c08698a2187c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332701509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.2332701509
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1777641754
Short name T1077
Test name
Test status
Simulation time 34764029 ps
CPU time 0.8 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:44 PM PDT 24
Peak memory 197248 kb
Host smart-b467757f-88e7-4ba5-b8d9-3c8e9b31a43a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777641754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
777641754
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3858961731
Short name T1060
Test name
Test status
Simulation time 49260284 ps
CPU time 1.68 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 195232 kb
Host smart-26630192-4974-4146-a0a0-7795f6f21655
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858961731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
858961731
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2327692298
Short name T1009
Test name
Test status
Simulation time 42031561 ps
CPU time 0.68 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 195028 kb
Host smart-9a0ea4be-a42a-428a-9814-e034b5336ee1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327692298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
327692298
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.811683729
Short name T70
Test name
Test status
Simulation time 53770494 ps
CPU time 1.17 seconds
Started Jul 11 04:35:36 PM PDT 24
Finished Jul 11 04:35:39 PM PDT 24
Peak memory 195224 kb
Host smart-7f8afce7-4448-49e9-84dc-a7b2bebcbb29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811683729 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.811683729
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.656481253
Short name T1109
Test name
Test status
Simulation time 22044953 ps
CPU time 0.6 seconds
Started Jul 11 04:35:39 PM PDT 24
Finished Jul 11 04:35:42 PM PDT 24
Peak memory 195028 kb
Host smart-9f64d049-a7d5-4610-b255-91baf069dc3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656481253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.656481253
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2580976106
Short name T1076
Test name
Test status
Simulation time 25757162 ps
CPU time 0.63 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:42 PM PDT 24
Peak memory 194828 kb
Host smart-7b2a5b44-132f-46ad-ae24-51487e27b546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580976106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2580976106
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1230636029
Short name T1059
Test name
Test status
Simulation time 102331863 ps
CPU time 0.66 seconds
Started Jul 11 04:35:45 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 198240 kb
Host smart-f714babf-55aa-4435-986c-21c3ae892a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230636029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.1230636029
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1226212917
Short name T1028
Test name
Test status
Simulation time 34580176 ps
CPU time 1.4 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:46 PM PDT 24
Peak memory 196480 kb
Host smart-f6ff061a-39a1-4af8-84ec-8f8395191cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226212917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.1226212917
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.423599114
Short name T58
Test name
Test status
Simulation time 177843317 ps
CPU time 1.52 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 195316 kb
Host smart-08a6b6c2-d9fd-4e06-8d64-001994e63713
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423599114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.
423599114
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4016505850
Short name T1064
Test name
Test status
Simulation time 95817009 ps
CPU time 0.78 seconds
Started Jul 11 04:35:47 PM PDT 24
Finished Jul 11 04:35:51 PM PDT 24
Peak memory 195200 kb
Host smart-11c4627d-29db-4712-bc86-7451c9900fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016505850 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.4016505850
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.859989350
Short name T1105
Test name
Test status
Simulation time 18534199 ps
CPU time 0.61 seconds
Started Jul 11 04:35:44 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 195024 kb
Host smart-f6c0651b-c7b7-4bdc-ac2d-6620abc859bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859989350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.859989350
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1828868654
Short name T1075
Test name
Test status
Simulation time 63869532 ps
CPU time 0.62 seconds
Started Jul 11 04:35:57 PM PDT 24
Finished Jul 11 04:36:00 PM PDT 24
Peak memory 194896 kb
Host smart-d6643d19-1c85-4d32-b129-a1b35058b794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828868654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1828868654
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1781620931
Short name T1044
Test name
Test status
Simulation time 473449776 ps
CPU time 0.91 seconds
Started Jul 11 04:35:51 PM PDT 24
Finished Jul 11 04:35:54 PM PDT 24
Peak memory 198696 kb
Host smart-b7be60aa-2f56-4e12-ad68-1e8087e5c6c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781620931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1781620931
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1659257858
Short name T1098
Test name
Test status
Simulation time 108475113 ps
CPU time 1.99 seconds
Started Jul 11 04:35:54 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 196356 kb
Host smart-a0e53bdd-0c08-4a2c-b7b5-90d5278b5088
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659257858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1659257858
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3730002146
Short name T57
Test name
Test status
Simulation time 227650776 ps
CPU time 1.15 seconds
Started Jul 11 04:35:55 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 200344 kb
Host smart-43aef0d0-13e2-460e-931c-8aa326f94024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730002146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.3730002146
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.435791448
Short name T199
Test name
Test status
Simulation time 66890569 ps
CPU time 0.83 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 195036 kb
Host smart-415303ef-d272-4357-839d-8ef5329d8f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435791448 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.435791448
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2859166140
Short name T113
Test name
Test status
Simulation time 16343174 ps
CPU time 0.61 seconds
Started Jul 11 04:35:46 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 197112 kb
Host smart-6ffa418a-b5c7-4e49-a41d-a9d8a66d7363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859166140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2859166140
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1260497893
Short name T1013
Test name
Test status
Simulation time 26927720 ps
CPU time 0.61 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 194896 kb
Host smart-8bfe2d33-3cff-4bc4-8037-982ba8402d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260497893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1260497893
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1729174862
Short name T1117
Test name
Test status
Simulation time 22675612 ps
CPU time 0.87 seconds
Started Jul 11 04:35:50 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 198208 kb
Host smart-9432263a-383a-4011-a371-616964010524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729174862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1729174862
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1971695283
Short name T1057
Test name
Test status
Simulation time 29902358 ps
CPU time 1.27 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 196264 kb
Host smart-6f63cb0c-0dce-4b19-bf08-9a7dc995b45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971695283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1971695283
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2614468587
Short name T1053
Test name
Test status
Simulation time 210959175 ps
CPU time 1.67 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:10 PM PDT 24
Peak memory 200352 kb
Host smart-b5ccec87-7093-403b-85e9-b76d4ee06181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614468587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.2614468587
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1655995858
Short name T1115
Test name
Test status
Simulation time 73006783 ps
CPU time 0.95 seconds
Started Jul 11 04:35:57 PM PDT 24
Finished Jul 11 04:36:00 PM PDT 24
Peak memory 195092 kb
Host smart-d43f48e3-03a5-44c5-9438-70c5cba04b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655995858 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1655995858
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1338152203
Short name T110
Test name
Test status
Simulation time 20146008 ps
CPU time 0.63 seconds
Started Jul 11 04:36:17 PM PDT 24
Finished Jul 11 04:36:19 PM PDT 24
Peak memory 194492 kb
Host smart-11c4d60b-d94f-4c5c-b211-dc84a379aa55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338152203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1338152203
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1912331385
Short name T1006
Test name
Test status
Simulation time 19272312 ps
CPU time 0.61 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 194888 kb
Host smart-c2f0db88-9424-4e96-99be-d9145f4b952c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912331385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1912331385
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.892705633
Short name T1110
Test name
Test status
Simulation time 35862830 ps
CPU time 0.73 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 197288 kb
Host smart-f0922743-beec-4fc9-88cb-9ed070c51609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892705633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sa
me_csr_outstanding.892705633
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2734905071
Short name T1003
Test name
Test status
Simulation time 63887836 ps
CPU time 1.43 seconds
Started Jul 11 04:36:18 PM PDT 24
Finished Jul 11 04:36:21 PM PDT 24
Peak memory 196336 kb
Host smart-f2a7e252-9fb8-4e12-b353-260a7fcd498e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734905071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2734905071
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.808514856
Short name T1072
Test name
Test status
Simulation time 80960579 ps
CPU time 1.11 seconds
Started Jul 11 04:36:18 PM PDT 24
Finished Jul 11 04:36:20 PM PDT 24
Peak memory 196560 kb
Host smart-d1f257b1-dfc2-4b41-be0d-56e358a1b045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808514856 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.808514856
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2831638008
Short name T114
Test name
Test status
Simulation time 35141050 ps
CPU time 0.77 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:52 PM PDT 24
Peak memory 197156 kb
Host smart-81e77783-145b-4e50-bff2-0aabf1c57226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831638008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2831638008
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.3652021966
Short name T1007
Test name
Test status
Simulation time 32137685 ps
CPU time 0.64 seconds
Started Jul 11 04:35:58 PM PDT 24
Finished Jul 11 04:36:01 PM PDT 24
Peak memory 194996 kb
Host smart-5cb52447-efde-4fde-847c-c7c9b97e74f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652021966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.3652021966
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2999534609
Short name T116
Test name
Test status
Simulation time 31223390 ps
CPU time 0.85 seconds
Started Jul 11 04:35:55 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 195032 kb
Host smart-a1bdb4ee-8011-464a-b85b-690c716c3058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999534609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2999534609
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2284438370
Short name T1026
Test name
Test status
Simulation time 55682887 ps
CPU time 2.37 seconds
Started Jul 11 04:35:58 PM PDT 24
Finished Jul 11 04:36:03 PM PDT 24
Peak memory 197456 kb
Host smart-54488b80-0e58-45b0-bc45-7633b5ed9283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284438370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2284438370
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3722247031
Short name T189
Test name
Test status
Simulation time 404439108 ps
CPU time 1.66 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 200540 kb
Host smart-1a59414b-a5ac-4213-906a-f1468cbf78a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722247031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3722247031
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1747475333
Short name T1090
Test name
Test status
Simulation time 75904110 ps
CPU time 0.98 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:06 PM PDT 24
Peak memory 196148 kb
Host smart-16353c4d-686b-49d3-a65a-150c34986dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747475333 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1747475333
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1257185871
Short name T1058
Test name
Test status
Simulation time 46432732 ps
CPU time 0.61 seconds
Started Jul 11 04:36:17 PM PDT 24
Finished Jul 11 04:36:19 PM PDT 24
Peak memory 194412 kb
Host smart-6889ec8e-5661-461e-912b-66fe8972c1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257185871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1257185871
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3337671079
Short name T119
Test name
Test status
Simulation time 83712340 ps
CPU time 0.74 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:14 PM PDT 24
Peak memory 195032 kb
Host smart-e9d7ff46-c92b-47ec-b6bb-89817dfb49fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337671079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3337671079
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3846914890
Short name T1067
Test name
Test status
Simulation time 305279174 ps
CPU time 1.72 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 197356 kb
Host smart-5fd896af-38d5-4c9b-80be-a05f7113b0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846914890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3846914890
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1209545649
Short name T78
Test name
Test status
Simulation time 99859308 ps
CPU time 1.15 seconds
Started Jul 11 04:35:53 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 200176 kb
Host smart-52d768a6-1812-4578-bf95-18d25c151f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209545649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1209545649
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1389271972
Short name T157
Test name
Test status
Simulation time 113982158 ps
CPU time 0.81 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:12 PM PDT 24
Peak memory 195032 kb
Host smart-a8b7f2b8-0db0-45d2-b810-b7fa4076740b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389271972 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.1389271972
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1199636613
Short name T107
Test name
Test status
Simulation time 18238137 ps
CPU time 0.68 seconds
Started Jul 11 04:36:01 PM PDT 24
Finished Jul 11 04:36:04 PM PDT 24
Peak memory 197300 kb
Host smart-72460739-a3c3-4181-8059-c783f6763ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199636613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1199636613
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3172768800
Short name T1036
Test name
Test status
Simulation time 26531366 ps
CPU time 0.59 seconds
Started Jul 11 04:35:46 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 194944 kb
Host smart-054da4f6-0787-40f8-a621-b0a4b887d914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172768800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3172768800
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2428052024
Short name T1017
Test name
Test status
Simulation time 49819203 ps
CPU time 0.76 seconds
Started Jul 11 04:36:15 PM PDT 24
Finished Jul 11 04:36:17 PM PDT 24
Peak memory 195072 kb
Host smart-9c7c15a3-0192-4308-8583-228a8f7d1ce1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428052024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.2428052024
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1715587660
Short name T1027
Test name
Test status
Simulation time 71889316 ps
CPU time 1.1 seconds
Started Jul 11 04:35:58 PM PDT 24
Finished Jul 11 04:36:02 PM PDT 24
Peak memory 197060 kb
Host smart-a75c7440-3452-4109-aaa7-1ba857d4600b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715587660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1715587660
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2406493103
Short name T1111
Test name
Test status
Simulation time 175641909 ps
CPU time 1.67 seconds
Started Jul 11 04:35:58 PM PDT 24
Finished Jul 11 04:36:02 PM PDT 24
Peak memory 195200 kb
Host smart-e214ee38-1e77-49c0-be33-49bfea3200a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406493103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2406493103
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.170178255
Short name T1094
Test name
Test status
Simulation time 128345105 ps
CPU time 1.45 seconds
Started Jul 11 04:36:15 PM PDT 24
Finished Jul 11 04:36:18 PM PDT 24
Peak memory 197360 kb
Host smart-f6824856-8818-41eb-b1ea-5cdd8aec0b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170178255 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.170178255
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2245118899
Short name T1055
Test name
Test status
Simulation time 39917746 ps
CPU time 0.66 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 197140 kb
Host smart-836b7e41-920c-4dbc-b375-ff6b0b57401b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245118899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2245118899
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3755749266
Short name T192
Test name
Test status
Simulation time 45662549 ps
CPU time 0.61 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 195004 kb
Host smart-d1e75a00-5a0f-4403-9a44-a57ef3efe2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755749266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3755749266
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1262402908
Short name T120
Test name
Test status
Simulation time 72694636 ps
CPU time 0.75 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:15 PM PDT 24
Peak memory 194968 kb
Host smart-880b3bdc-ea49-4024-bcaf-f9f1c0206ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262402908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1262402908
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.955051842
Short name T1008
Test name
Test status
Simulation time 55863809 ps
CPU time 1.49 seconds
Started Jul 11 04:36:00 PM PDT 24
Finished Jul 11 04:36:04 PM PDT 24
Peak memory 197284 kb
Host smart-0df6cd04-ab05-41f9-920d-1e63c4a7f06b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955051842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.955051842
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.488711260
Short name T1018
Test name
Test status
Simulation time 155704857 ps
CPU time 1.13 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:11 PM PDT 24
Peak memory 200480 kb
Host smart-9c92ef56-2925-4ca3-8548-722b9340be5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488711260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.488711260
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1763697877
Short name T1071
Test name
Test status
Simulation time 57935599 ps
CPU time 0.98 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:15 PM PDT 24
Peak memory 200380 kb
Host smart-ac24817a-7ac0-4cf7-a6d2-a9b80c9778d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763697877 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1763697877
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.4211987090
Short name T1112
Test name
Test status
Simulation time 40874977 ps
CPU time 0.62 seconds
Started Jul 11 04:36:01 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 195040 kb
Host smart-189c9231-9070-4d80-9584-1771e2fcbc95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211987090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.4211987090
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2034094320
Short name T1022
Test name
Test status
Simulation time 52851161 ps
CPU time 0.62 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 195004 kb
Host smart-561ac0f9-e7bd-435f-b3f7-04d021a28ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034094320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2034094320
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2113614165
Short name T1102
Test name
Test status
Simulation time 42112478 ps
CPU time 0.86 seconds
Started Jul 11 04:36:13 PM PDT 24
Finished Jul 11 04:36:16 PM PDT 24
Peak memory 195136 kb
Host smart-f5704925-a35a-425f-8d06-7e8ffdbf0c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113614165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2113614165
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3059750469
Short name T1108
Test name
Test status
Simulation time 71395198 ps
CPU time 1.42 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:10 PM PDT 24
Peak memory 196256 kb
Host smart-8b228c26-6225-45b0-95b9-03f76f327021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059750469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3059750469
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.214746121
Short name T1049
Test name
Test status
Simulation time 170076359 ps
CPU time 1.1 seconds
Started Jul 11 04:35:53 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 200048 kb
Host smart-bcc25357-80ef-489f-8409-df7d28b19d42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214746121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err
.214746121
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.4250410541
Short name T63
Test name
Test status
Simulation time 94708439 ps
CPU time 1.22 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:15 PM PDT 24
Peak memory 197172 kb
Host smart-b58b106c-77e4-4a03-a348-a0a8512eef20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250410541 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.4250410541
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.829111317
Short name T1019
Test name
Test status
Simulation time 85122249 ps
CPU time 0.7 seconds
Started Jul 11 04:36:01 PM PDT 24
Finished Jul 11 04:36:05 PM PDT 24
Peak memory 196268 kb
Host smart-82e23e59-b5e7-4c3c-a4cb-2683757a88cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829111317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.829111317
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.873670336
Short name T1032
Test name
Test status
Simulation time 43936501 ps
CPU time 0.62 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 194884 kb
Host smart-82f99922-27aa-48bf-827e-a5554a0b5c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873670336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.873670336
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3009042499
Short name T118
Test name
Test status
Simulation time 46668292 ps
CPU time 0.9 seconds
Started Jul 11 04:35:59 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 194968 kb
Host smart-b3544622-55c6-4468-9958-b74378852c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009042499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.3009042499
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1159432838
Short name T1015
Test name
Test status
Simulation time 45577697 ps
CPU time 1.47 seconds
Started Jul 11 04:36:15 PM PDT 24
Finished Jul 11 04:36:18 PM PDT 24
Peak memory 196304 kb
Host smart-d3a5ec88-7c1e-4435-80b0-75b151c99fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159432838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1159432838
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4031104596
Short name T72
Test name
Test status
Simulation time 192892082 ps
CPU time 1.73 seconds
Started Jul 11 04:36:01 PM PDT 24
Finished Jul 11 04:36:04 PM PDT 24
Peak memory 200564 kb
Host smart-966fe987-40af-4fef-82c7-5d89e3ba9b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031104596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.4031104596
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2891646778
Short name T1106
Test name
Test status
Simulation time 53626523 ps
CPU time 0.98 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:14 PM PDT 24
Peak memory 195100 kb
Host smart-46e9a4d9-16d6-4f9e-b6c3-339948e81cbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891646778 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2891646778
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.201649161
Short name T109
Test name
Test status
Simulation time 45323511 ps
CPU time 0.64 seconds
Started Jul 11 04:35:56 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 195020 kb
Host smart-7ddbd394-5bb3-454f-952f-d10d251a546c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201649161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.201649161
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1021859156
Short name T1096
Test name
Test status
Simulation time 85128308 ps
CPU time 0.57 seconds
Started Jul 11 04:35:46 PM PDT 24
Finished Jul 11 04:35:55 PM PDT 24
Peak memory 194888 kb
Host smart-9315c25c-df91-4596-9fd3-26f14b264200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021859156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1021859156
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.679443901
Short name T1020
Test name
Test status
Simulation time 107339168 ps
CPU time 0.68 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 197252 kb
Host smart-e58ec580-9c2f-4492-94db-754a0aa801a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679443901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sa
me_csr_outstanding.679443901
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.479009966
Short name T1011
Test name
Test status
Simulation time 177781881 ps
CPU time 1.37 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:12 PM PDT 24
Peak memory 195316 kb
Host smart-9645f84d-a7fb-413d-910a-6031cdd1f4d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479009966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.479009966
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.581745616
Short name T1024
Test name
Test status
Simulation time 129879403 ps
CPU time 1.08 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:12 PM PDT 24
Peak memory 195216 kb
Host smart-f30ab2fe-efd1-43a0-8611-c3e698a76603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581745616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err
.581745616
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3622013516
Short name T1025
Test name
Test status
Simulation time 91005843 ps
CPU time 0.76 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 197588 kb
Host smart-9caa7533-015e-4758-9ee2-c64133cbccbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622013516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
622013516
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.377396760
Short name T167
Test name
Test status
Simulation time 115987659 ps
CPU time 1.9 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 195232 kb
Host smart-bf036ff2-8faa-469c-a971-3f44dbdcfa1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377396760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.377396760
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2626311563
Short name T108
Test name
Test status
Simulation time 69014535 ps
CPU time 0.67 seconds
Started Jul 11 04:35:47 PM PDT 24
Finished Jul 11 04:35:51 PM PDT 24
Peak memory 195040 kb
Host smart-beb0a8f0-07ae-4951-aaf0-2753940cba4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626311563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
626311563
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1462568330
Short name T1087
Test name
Test status
Simulation time 110529878 ps
CPU time 0.92 seconds
Started Jul 11 04:35:45 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 196156 kb
Host smart-77c50a15-fbc8-473f-a55a-b0d3b67f9595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462568330 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1462568330
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1074019509
Short name T1068
Test name
Test status
Simulation time 184769584 ps
CPU time 0.64 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 195116 kb
Host smart-e1f4be6a-a107-4c37-a613-e1eb66d0af98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074019509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1074019509
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2834395264
Short name T193
Test name
Test status
Simulation time 57522717 ps
CPU time 0.62 seconds
Started Jul 11 04:35:52 PM PDT 24
Finished Jul 11 04:35:55 PM PDT 24
Peak memory 194996 kb
Host smart-4818b3bf-6337-4b74-891c-b3d20d833a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834395264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2834395264
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.532127024
Short name T1119
Test name
Test status
Simulation time 467316620 ps
CPU time 0.83 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:52 PM PDT 24
Peak memory 198492 kb
Host smart-2429b14c-c6e1-4993-b7aa-8475575b72b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532127024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sam
e_csr_outstanding.532127024
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.851449492
Short name T1073
Test name
Test status
Simulation time 85218170 ps
CPU time 2.28 seconds
Started Jul 11 04:35:42 PM PDT 24
Finished Jul 11 04:35:47 PM PDT 24
Peak memory 197660 kb
Host smart-18c776c1-1884-4427-8b44-f851c94865aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851449492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.851449492
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3097399542
Short name T191
Test name
Test status
Simulation time 662320227 ps
CPU time 1.62 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 200488 kb
Host smart-8f217d58-34f3-4009-aff2-787dbc085f71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097399542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3097399542
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1496533589
Short name T1031
Test name
Test status
Simulation time 43639250 ps
CPU time 0.61 seconds
Started Jul 11 04:36:12 PM PDT 24
Finished Jul 11 04:36:15 PM PDT 24
Peak memory 194892 kb
Host smart-3a740e4d-9c37-4089-b10a-29b5cd9e945b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496533589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1496533589
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2566615943
Short name T1085
Test name
Test status
Simulation time 16625951 ps
CPU time 0.63 seconds
Started Jul 11 04:35:59 PM PDT 24
Finished Jul 11 04:36:02 PM PDT 24
Peak memory 195000 kb
Host smart-a9cf5ac0-18b0-4e66-b97a-646fbce97cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566615943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2566615943
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1433445555
Short name T1118
Test name
Test status
Simulation time 85767354 ps
CPU time 0.6 seconds
Started Jul 11 04:36:14 PM PDT 24
Finished Jul 11 04:36:17 PM PDT 24
Peak memory 194964 kb
Host smart-a0590497-af0e-4667-9e1e-b855660b35dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433445555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1433445555
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2148189511
Short name T1066
Test name
Test status
Simulation time 55629335 ps
CPU time 0.66 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 194996 kb
Host smart-7ee3936c-9315-47a1-87c4-a8e82194ff80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148189511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2148189511
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1021823976
Short name T1034
Test name
Test status
Simulation time 38871649 ps
CPU time 0.59 seconds
Started Jul 11 04:35:59 PM PDT 24
Finished Jul 11 04:36:02 PM PDT 24
Peak memory 194996 kb
Host smart-dc6f098c-f764-40ec-9fd6-2f503fa3936a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021823976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1021823976
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1664578587
Short name T1092
Test name
Test status
Simulation time 34628439 ps
CPU time 0.6 seconds
Started Jul 11 04:36:06 PM PDT 24
Finished Jul 11 04:36:10 PM PDT 24
Peak memory 194988 kb
Host smart-6e8968fc-e642-41e3-a6df-9cb4d6cdb5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664578587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1664578587
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3842921311
Short name T1048
Test name
Test status
Simulation time 25230505 ps
CPU time 0.58 seconds
Started Jul 11 04:36:24 PM PDT 24
Finished Jul 11 04:36:26 PM PDT 24
Peak memory 194968 kb
Host smart-c2d28f82-45e3-4e05-a182-0ca94524b976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842921311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3842921311
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.352215661
Short name T198
Test name
Test status
Simulation time 23301141 ps
CPU time 0.61 seconds
Started Jul 11 04:35:50 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 194888 kb
Host smart-4e87c4b0-c649-44d2-81a6-d8e3425d91bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352215661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.352215661
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2049319655
Short name T1104
Test name
Test status
Simulation time 43468244 ps
CPU time 0.61 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 194992 kb
Host smart-147e8c13-8013-44c9-987e-9614bcbc2f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049319655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2049319655
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1850886065
Short name T1099
Test name
Test status
Simulation time 101855132 ps
CPU time 0.58 seconds
Started Jul 11 04:36:10 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194996 kb
Host smart-7371fe38-2a63-41f2-974a-830ac9fc003f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850886065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1850886065
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3248939145
Short name T1082
Test name
Test status
Simulation time 61534239 ps
CPU time 0.99 seconds
Started Jul 11 04:35:44 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 195040 kb
Host smart-bc1ffc98-0014-437e-bdbd-fdcdd68993f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248939145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
248939145
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1614923989
Short name T1069
Test name
Test status
Simulation time 223020491 ps
CPU time 1.9 seconds
Started Jul 11 04:35:55 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 195148 kb
Host smart-e8d484b0-3ba7-4d5b-8c80-68f57d5c218f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614923989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
614923989
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3784812443
Short name T1054
Test name
Test status
Simulation time 33348873 ps
CPU time 0.68 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 197536 kb
Host smart-ffc303c5-8565-46ee-879b-4f7b56dc8baa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784812443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
784812443
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.410138188
Short name T1029
Test name
Test status
Simulation time 54496082 ps
CPU time 0.78 seconds
Started Jul 11 04:35:44 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 195156 kb
Host smart-f6e5682d-48e5-404a-8d02-6cd490dbd677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410138188 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.410138188
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1702968573
Short name T103
Test name
Test status
Simulation time 39796989 ps
CPU time 0.64 seconds
Started Jul 11 04:35:46 PM PDT 24
Finished Jul 11 04:35:49 PM PDT 24
Peak memory 197328 kb
Host smart-e3fa9b0d-78f2-40fe-beea-44f3aea2ae2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702968573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1702968573
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3962496094
Short name T1016
Test name
Test status
Simulation time 64882759 ps
CPU time 0.59 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:44 PM PDT 24
Peak memory 194996 kb
Host smart-9e13aca1-34b8-438e-a3b2-4a0e14905f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962496094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3962496094
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3650403295
Short name T115
Test name
Test status
Simulation time 43074173 ps
CPU time 0.83 seconds
Started Jul 11 04:35:59 PM PDT 24
Finished Jul 11 04:36:03 PM PDT 24
Peak memory 195064 kb
Host smart-e53bfedd-7664-4792-95f7-16fcb0b093d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650403295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3650403295
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1892995078
Short name T1004
Test name
Test status
Simulation time 123192876 ps
CPU time 1.37 seconds
Started Jul 11 04:35:47 PM PDT 24
Finished Jul 11 04:35:52 PM PDT 24
Peak memory 195352 kb
Host smart-70f20808-e221-423b-9f8c-e3ceb54cc181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892995078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1892995078
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.249280197
Short name T1046
Test name
Test status
Simulation time 308000687 ps
CPU time 0.99 seconds
Started Jul 11 04:36:26 PM PDT 24
Finished Jul 11 04:36:28 PM PDT 24
Peak memory 199976 kb
Host smart-315cd7b1-3c9e-432d-9f2d-24b8e4aa0e51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249280197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.
249280197
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.197202716
Short name T1089
Test name
Test status
Simulation time 18941213 ps
CPU time 0.61 seconds
Started Jul 11 04:36:01 PM PDT 24
Finished Jul 11 04:36:05 PM PDT 24
Peak memory 194996 kb
Host smart-cf92596c-2956-45bd-b454-be474eeaf6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197202716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.197202716
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4109713614
Short name T1084
Test name
Test status
Simulation time 44181643 ps
CPU time 0.59 seconds
Started Jul 11 04:36:10 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194824 kb
Host smart-99e804b4-73bc-4803-b650-8bb5afa9dd1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109713614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.4109713614
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.4067175750
Short name T1088
Test name
Test status
Simulation time 33662410 ps
CPU time 0.66 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 194884 kb
Host smart-fcc89ddf-5e58-4d41-9876-90090e76fbd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067175750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.4067175750
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2924776746
Short name T194
Test name
Test status
Simulation time 17766026 ps
CPU time 0.72 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:14 PM PDT 24
Peak memory 194900 kb
Host smart-eebe7286-f4e2-404b-a39f-3e8512df10b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924776746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2924776746
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.888641759
Short name T1052
Test name
Test status
Simulation time 19270926 ps
CPU time 0.64 seconds
Started Jul 11 04:36:14 PM PDT 24
Finished Jul 11 04:36:17 PM PDT 24
Peak memory 194932 kb
Host smart-24deab2a-540f-458b-a0f8-8b5bc45e908d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888641759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.888641759
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.692899167
Short name T196
Test name
Test status
Simulation time 32011925 ps
CPU time 0.64 seconds
Started Jul 11 04:36:02 PM PDT 24
Finished Jul 11 04:36:05 PM PDT 24
Peak memory 195004 kb
Host smart-5f953042-9535-47e2-8f64-ebf6e6e7fae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692899167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.692899167
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1372499610
Short name T1030
Test name
Test status
Simulation time 45002741 ps
CPU time 0.62 seconds
Started Jul 11 04:36:10 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194992 kb
Host smart-b026df30-e9e1-4fa8-bdbc-79204a847fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372499610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1372499610
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2519814653
Short name T1097
Test name
Test status
Simulation time 144922208 ps
CPU time 0.62 seconds
Started Jul 11 04:36:10 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194996 kb
Host smart-ab8d4547-40ee-4a5b-b080-065dbc85cf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519814653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2519814653
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2688373925
Short name T1051
Test name
Test status
Simulation time 35621187 ps
CPU time 0.64 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 194888 kb
Host smart-39cc8042-2a6d-495c-9f46-7c89459a7bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688373925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2688373925
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1698742265
Short name T104
Test name
Test status
Simulation time 23005913 ps
CPU time 0.78 seconds
Started Jul 11 04:36:50 PM PDT 24
Finished Jul 11 04:36:52 PM PDT 24
Peak memory 197372 kb
Host smart-e49b3679-fd8f-499f-a728-49c8411a641c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698742265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
698742265
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3540575988
Short name T1033
Test name
Test status
Simulation time 216224843 ps
CPU time 3.1 seconds
Started Jul 11 04:35:44 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 195232 kb
Host smart-9763e074-8e90-4798-99c3-e597022cc472
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540575988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.3
540575988
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3101462399
Short name T68
Test name
Test status
Simulation time 33522952 ps
CPU time 0.67 seconds
Started Jul 11 04:35:55 PM PDT 24
Finished Jul 11 04:35:57 PM PDT 24
Peak memory 197284 kb
Host smart-9fc64d80-c343-4259-8ebb-9d8989dabe9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101462399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
101462399
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2610388702
Short name T1056
Test name
Test status
Simulation time 85808159 ps
CPU time 0.93 seconds
Started Jul 11 04:35:45 PM PDT 24
Finished Jul 11 04:35:49 PM PDT 24
Peak memory 196152 kb
Host smart-d068f439-4629-4785-989e-bb0da1a0afc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610388702 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2610388702
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.978242876
Short name T1093
Test name
Test status
Simulation time 22002931 ps
CPU time 0.62 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:51 PM PDT 24
Peak memory 195016 kb
Host smart-c7a5e158-51cb-463a-bf1d-0af41ea9fcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978242876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.978242876
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.520016774
Short name T1081
Test name
Test status
Simulation time 48137322 ps
CPU time 0.59 seconds
Started Jul 11 04:36:06 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 194984 kb
Host smart-0caf391b-8e85-4602-a51b-7a61dba8da7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520016774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.520016774
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1211752594
Short name T62
Test name
Test status
Simulation time 40245818 ps
CPU time 0.89 seconds
Started Jul 11 04:35:55 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 198432 kb
Host smart-4f07ba3e-28e4-41ea-b21b-1d8f581cd29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211752594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1211752594
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1849871192
Short name T1005
Test name
Test status
Simulation time 62857609 ps
CPU time 0.98 seconds
Started Jul 11 04:35:53 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 195180 kb
Host smart-e73f7752-2abc-4cfd-8f84-e38b360cd170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849871192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1849871192
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.466772542
Short name T71
Test name
Test status
Simulation time 234746935 ps
CPU time 1.58 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:44 PM PDT 24
Peak memory 200548 kb
Host smart-4cf11e28-4bf5-47f7-bcab-5b814940a3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466772542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
466772542
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2948627797
Short name T1101
Test name
Test status
Simulation time 27931554 ps
CPU time 0.61 seconds
Started Jul 11 04:35:48 PM PDT 24
Finished Jul 11 04:35:52 PM PDT 24
Peak memory 194968 kb
Host smart-6ac13ac5-3c95-4e58-829b-496a7f88f4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948627797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2948627797
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.337293398
Short name T1039
Test name
Test status
Simulation time 20532357 ps
CPU time 0.67 seconds
Started Jul 11 04:36:15 PM PDT 24
Finished Jul 11 04:36:18 PM PDT 24
Peak memory 194992 kb
Host smart-24d180cc-848f-4057-b367-fde1632d4c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337293398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.337293398
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3177862112
Short name T1083
Test name
Test status
Simulation time 66011040 ps
CPU time 0.6 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:12 PM PDT 24
Peak memory 194824 kb
Host smart-53e89c02-35f8-4fc1-b93c-9bb6306786f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177862112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3177862112
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.462863870
Short name T1014
Test name
Test status
Simulation time 139426860 ps
CPU time 0.63 seconds
Started Jul 11 04:36:03 PM PDT 24
Finished Jul 11 04:36:07 PM PDT 24
Peak memory 194872 kb
Host smart-1cfb2bad-505c-441c-8bc4-b9bb6c7c3b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462863870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.462863870
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.693362480
Short name T1012
Test name
Test status
Simulation time 23539475 ps
CPU time 0.62 seconds
Started Jul 11 04:36:04 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 195204 kb
Host smart-ff904970-fc80-4343-8e52-5e36f6e6d500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693362480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.693362480
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3947496001
Short name T1047
Test name
Test status
Simulation time 17805417 ps
CPU time 0.67 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:14 PM PDT 24
Peak memory 194884 kb
Host smart-7dc257d1-f1bb-4e11-bc8d-299f3d0cfde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947496001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3947496001
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3408588772
Short name T1045
Test name
Test status
Simulation time 21069951 ps
CPU time 0.62 seconds
Started Jul 11 04:36:23 PM PDT 24
Finished Jul 11 04:36:25 PM PDT 24
Peak memory 194888 kb
Host smart-81991c57-efda-4fed-b6bd-10c0d9c3937b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408588772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3408588772
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1118322125
Short name T1086
Test name
Test status
Simulation time 19329723 ps
CPU time 0.67 seconds
Started Jul 11 04:36:19 PM PDT 24
Finished Jul 11 04:36:21 PM PDT 24
Peak memory 194888 kb
Host smart-914efe4d-a85d-4dca-b8cf-96a2a63c8292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118322125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1118322125
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3718290956
Short name T197
Test name
Test status
Simulation time 17763046 ps
CPU time 0.64 seconds
Started Jul 11 04:36:10 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 194884 kb
Host smart-5e8a2bb9-0f4b-4407-b3a5-20932ef86741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718290956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3718290956
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1257335964
Short name T1100
Test name
Test status
Simulation time 90481820 ps
CPU time 0.64 seconds
Started Jul 11 04:36:15 PM PDT 24
Finished Jul 11 04:36:18 PM PDT 24
Peak memory 195004 kb
Host smart-0bdf3a5b-8b6a-4228-9985-043b33670a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257335964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1257335964
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1126376790
Short name T1042
Test name
Test status
Simulation time 121455034 ps
CPU time 0.93 seconds
Started Jul 11 04:35:45 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 195168 kb
Host smart-17ba2349-3b8a-493a-beb5-33e0a7b15640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126376790 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1126376790
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3444913174
Short name T1116
Test name
Test status
Simulation time 20998556 ps
CPU time 0.65 seconds
Started Jul 11 04:35:54 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 195020 kb
Host smart-d385b5aa-549c-4196-9744-2d2d8bda4a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444913174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3444913174
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2270816021
Short name T64
Test name
Test status
Simulation time 276410629 ps
CPU time 0.86 seconds
Started Jul 11 04:35:50 PM PDT 24
Finished Jul 11 04:35:54 PM PDT 24
Peak memory 198240 kb
Host smart-6fb4cd10-db31-4510-8edd-f134a1a02877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270816021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2270816021
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3271195041
Short name T1078
Test name
Test status
Simulation time 47500810 ps
CPU time 1.09 seconds
Started Jul 11 04:35:37 PM PDT 24
Finished Jul 11 04:35:40 PM PDT 24
Peak memory 195372 kb
Host smart-3fce1b46-d04f-4aa1-84d6-b4557c8c563c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271195041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3271195041
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1430178951
Short name T77
Test name
Test status
Simulation time 1214244542 ps
CPU time 1.56 seconds
Started Jul 11 04:35:42 PM PDT 24
Finished Jul 11 04:35:46 PM PDT 24
Peak memory 195308 kb
Host smart-d057e1cd-e9ea-4367-a921-5e063bd474c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430178951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.1430178951
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2287933521
Short name T1043
Test name
Test status
Simulation time 133935283 ps
CPU time 0.89 seconds
Started Jul 11 04:35:53 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 200492 kb
Host smart-8788a234-3dc3-43d0-be55-a8a95bfa4f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287933521 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2287933521
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1893414048
Short name T1074
Test name
Test status
Simulation time 20296624 ps
CPU time 0.65 seconds
Started Jul 11 04:35:56 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 197244 kb
Host smart-553bbda4-cadf-41d0-9526-820fe0e44930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893414048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1893414048
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1576593482
Short name T195
Test name
Test status
Simulation time 50047520 ps
CPU time 0.64 seconds
Started Jul 11 04:36:00 PM PDT 24
Finished Jul 11 04:36:03 PM PDT 24
Peak memory 194892 kb
Host smart-1a8ad088-c900-45d0-aaf9-1f188aae9d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576593482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1576593482
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3365073861
Short name T1040
Test name
Test status
Simulation time 204919507 ps
CPU time 0.73 seconds
Started Jul 11 04:35:40 PM PDT 24
Finished Jul 11 04:35:44 PM PDT 24
Peak memory 195128 kb
Host smart-faebcb28-87d3-4737-b7c0-ce74dd4b62b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365073861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.3365073861
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1946007980
Short name T1063
Test name
Test status
Simulation time 671136620 ps
CPU time 1.97 seconds
Started Jul 11 04:35:42 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 196232 kb
Host smart-85e73b86-f05f-4b60-a97d-69551618456c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946007980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.1946007980
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.291670991
Short name T190
Test name
Test status
Simulation time 281376554 ps
CPU time 1.57 seconds
Started Jul 11 04:35:47 PM PDT 24
Finished Jul 11 04:35:52 PM PDT 24
Peak memory 195228 kb
Host smart-04592936-cb1e-4d10-9ab4-44b452c5a151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291670991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.
291670991
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.566161155
Short name T1021
Test name
Test status
Simulation time 162701948 ps
CPU time 0.68 seconds
Started Jul 11 04:35:54 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 195092 kb
Host smart-4719baad-d939-4da0-b4b5-298cacfc8d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566161155 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.566161155
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3996021517
Short name T1114
Test name
Test status
Simulation time 46844744 ps
CPU time 0.62 seconds
Started Jul 11 04:35:56 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 194960 kb
Host smart-7a791cb6-c421-4d99-882a-64cbfb392b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996021517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3996021517
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2606226471
Short name T117
Test name
Test status
Simulation time 94491819 ps
CPU time 0.79 seconds
Started Jul 11 04:35:37 PM PDT 24
Finished Jul 11 04:35:40 PM PDT 24
Peak memory 198324 kb
Host smart-cc7775c6-b868-40e8-8c57-bafbda91a0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606226471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2606226471
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3412984859
Short name T1091
Test name
Test status
Simulation time 109425326 ps
CPU time 1.47 seconds
Started Jul 11 04:35:51 PM PDT 24
Finished Jul 11 04:35:55 PM PDT 24
Peak memory 195352 kb
Host smart-d4b81af4-8b1f-472a-834e-d0d10ee6d616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412984859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3412984859
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3491237985
Short name T1038
Test name
Test status
Simulation time 94884684 ps
CPU time 1.11 seconds
Started Jul 11 04:35:58 PM PDT 24
Finished Jul 11 04:36:01 PM PDT 24
Peak memory 200384 kb
Host smart-3429c720-1bd5-44ce-b718-06ca2bbe63da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491237985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.3491237985
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.31864042
Short name T1095
Test name
Test status
Simulation time 66110904 ps
CPU time 1.39 seconds
Started Jul 11 04:35:46 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 196596 kb
Host smart-ccc42f7b-160a-4f3b-855a-031fc00c180c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864042 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.31864042
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1337348445
Short name T112
Test name
Test status
Simulation time 50492992 ps
CPU time 0.66 seconds
Started Jul 11 04:35:57 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 198296 kb
Host smart-c608b447-1aa1-4324-b596-632b7d6202a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337348445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.1337348445
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1378977306
Short name T1107
Test name
Test status
Simulation time 18911018 ps
CPU time 0.7 seconds
Started Jul 11 04:35:44 PM PDT 24
Finished Jul 11 04:35:47 PM PDT 24
Peak memory 194888 kb
Host smart-8e8ee13e-8116-41d1-891c-3b6f648df694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378977306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1378977306
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.383433114
Short name T1041
Test name
Test status
Simulation time 43791402 ps
CPU time 0.71 seconds
Started Jul 11 04:36:09 PM PDT 24
Finished Jul 11 04:36:11 PM PDT 24
Peak memory 198372 kb
Host smart-48f7a386-2905-4592-bb03-e7e7cfff3b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383433114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.383433114
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2265703076
Short name T1010
Test name
Test status
Simulation time 104135793 ps
CPU time 2.25 seconds
Started Jul 11 04:35:52 PM PDT 24
Finished Jul 11 04:35:57 PM PDT 24
Peak memory 196300 kb
Host smart-c8cceee7-bfe2-4117-8af1-9c35656e4d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265703076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2265703076
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2544194657
Short name T1023
Test name
Test status
Simulation time 141531270 ps
CPU time 1.11 seconds
Started Jul 11 04:36:11 PM PDT 24
Finished Jul 11 04:36:14 PM PDT 24
Peak memory 200152 kb
Host smart-aa9fa8a3-764f-4f03-943e-fca58ae1af8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544194657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2544194657
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2374639085
Short name T1070
Test name
Test status
Simulation time 40363316 ps
CPU time 1.08 seconds
Started Jul 11 04:36:13 PM PDT 24
Finished Jul 11 04:36:16 PM PDT 24
Peak memory 196056 kb
Host smart-a6a09760-1403-44d1-a710-b23819cfdd98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374639085 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2374639085
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1940358906
Short name T1061
Test name
Test status
Simulation time 18219541 ps
CPU time 0.64 seconds
Started Jul 11 04:35:38 PM PDT 24
Finished Jul 11 04:35:40 PM PDT 24
Peak memory 197180 kb
Host smart-1f65094b-1e61-423a-93d7-0d95edf909fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940358906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1940358906
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3952539623
Short name T1113
Test name
Test status
Simulation time 108479441 ps
CPU time 0.6 seconds
Started Jul 11 04:35:41 PM PDT 24
Finished Jul 11 04:35:45 PM PDT 24
Peak memory 195004 kb
Host smart-3baa67bf-7d2a-4e19-b3c8-23d8363d1355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952539623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3952539623
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.729781555
Short name T1079
Test name
Test status
Simulation time 35340576 ps
CPU time 0.76 seconds
Started Jul 11 04:36:05 PM PDT 24
Finished Jul 11 04:36:09 PM PDT 24
Peak memory 197208 kb
Host smart-db2e6a3b-431a-4182-a280-8f651d372450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729781555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.729781555
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.337522960
Short name T1065
Test name
Test status
Simulation time 152761204 ps
CPU time 1.63 seconds
Started Jul 11 04:35:49 PM PDT 24
Finished Jul 11 04:35:54 PM PDT 24
Peak memory 196336 kb
Host smart-63175ccf-e715-4c4b-98a8-32e6093aea99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337522960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.337522960
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.1135092155
Short name T122
Test name
Test status
Simulation time 26376692 ps
CPU time 0.74 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 198356 kb
Host smart-ba0aab4d-2871-44f8-aee1-d4c8419fc4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135092155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.1135092155
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3609163430
Short name T869
Test name
Test status
Simulation time 53076262 ps
CPU time 0.82 seconds
Started Jul 11 04:55:15 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 198756 kb
Host smart-494046cf-042f-404a-a12b-3b9a3bd23df3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609163430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.3609163430
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3470384178
Short name T868
Test name
Test status
Simulation time 45768140 ps
CPU time 0.6 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 197740 kb
Host smart-e106558b-b38b-4d1f-a8df-7c8a59825b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470384178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3470384178
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3466570588
Short name T916
Test name
Test status
Simulation time 213939354 ps
CPU time 0.97 seconds
Started Jul 11 04:55:18 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 198112 kb
Host smart-19e2a2dd-decf-48af-a7ff-101993086fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466570588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3466570588
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.230465314
Short name T544
Test name
Test status
Simulation time 47037364 ps
CPU time 0.64 seconds
Started Jul 11 04:55:23 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 197708 kb
Host smart-4a3c8735-de37-41f5-9190-c7b994e5904d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230465314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.230465314
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3291344497
Short name T378
Test name
Test status
Simulation time 42819853 ps
CPU time 0.69 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 197776 kb
Host smart-8e35caf8-3527-4471-ad59-20d9a82a3ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291344497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3291344497
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.3844586705
Short name T552
Test name
Test status
Simulation time 40365099 ps
CPU time 0.73 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 200868 kb
Host smart-ac07141c-cd80-4c61-9057-7b0942c9f3e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844586705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.3844586705
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.1764419093
Short name T242
Test name
Test status
Simulation time 202651141 ps
CPU time 1.17 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 199432 kb
Host smart-e7114986-fee6-4173-a06c-f55658c41a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764419093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.1764419093
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.608324148
Short name T406
Test name
Test status
Simulation time 67505591 ps
CPU time 0.99 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:21 PM PDT 24
Peak memory 199596 kb
Host smart-9ea1ac53-a9df-473f-ba6c-e07fb02ad132
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608324148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.608324148
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.4072107758
Short name T469
Test name
Test status
Simulation time 115839454 ps
CPU time 0.85 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 209280 kb
Host smart-6ddc6db5-6f21-4429-98d6-db9bf4e71915
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072107758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.4072107758
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1204588841
Short name T26
Test name
Test status
Simulation time 695664362 ps
CPU time 1.49 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 216424 kb
Host smart-4892130b-2647-48f8-9309-afd9420068d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204588841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1204588841
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1417327068
Short name T899
Test name
Test status
Simulation time 259741527 ps
CPU time 1.19 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 199688 kb
Host smart-5ca5d571-8e75-4ddd-a8ce-e6a6fa35ab2c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417327068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.1417327068
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1807962957
Short name T710
Test name
Test status
Simulation time 1267752236 ps
CPU time 2.26 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 200744 kb
Host smart-42f94b91-54f0-4a5b-8370-3620d76d590f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807962957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1807962957
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4040618525
Short name T661
Test name
Test status
Simulation time 902315921 ps
CPU time 3.18 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 200904 kb
Host smart-188a6847-fd95-4789-a933-5c6bd43fe430
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040618525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4040618525
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1182684203
Short name T87
Test name
Test status
Simulation time 608279860 ps
CPU time 0.93 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 198980 kb
Host smart-97b7b9e6-833e-4b07-a92b-0bdb874f037a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182684203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1182684203
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.952414581
Short name T352
Test name
Test status
Simulation time 55908420 ps
CPU time 0.65 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 199076 kb
Host smart-b05573c3-7388-4010-93b3-0e1edbb5e6db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952414581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.952414581
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.3715550404
Short name T436
Test name
Test status
Simulation time 1900333582 ps
CPU time 6.67 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 200872 kb
Host smart-375ffdc8-7e3f-4e7a-83fd-8a55df1d0306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715550404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3715550404
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2526597671
Short name T134
Test name
Test status
Simulation time 8853163216 ps
CPU time 7.86 seconds
Started Jul 11 04:55:23 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 200968 kb
Host smart-a9ce3c5d-d059-44fa-87c7-5bffe40d20fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526597671 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.2526597671
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.479528856
Short name T578
Test name
Test status
Simulation time 202044034 ps
CPU time 0.91 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 199248 kb
Host smart-0ca1f443-6677-418f-b3ec-055c8d07945a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479528856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.479528856
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.1767631381
Short name T246
Test name
Test status
Simulation time 89567414 ps
CPU time 0.89 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 198892 kb
Host smart-c4f0b2f1-b6b6-4075-81bc-4ce055454daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767631381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.1767631381
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.3318072180
Short name T929
Test name
Test status
Simulation time 107314482 ps
CPU time 0.76 seconds
Started Jul 11 04:55:20 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 198536 kb
Host smart-119bd7e3-c5cc-47c5-8f39-2ad3a20ca8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318072180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.3318072180
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2656914175
Short name T644
Test name
Test status
Simulation time 90216803 ps
CPU time 0.71 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 198244 kb
Host smart-25891b47-cd07-4a49-bae1-0d7dcec29a37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656914175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2656914175
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4037615237
Short name T683
Test name
Test status
Simulation time 31004557 ps
CPU time 0.58 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 197720 kb
Host smart-e83937f1-6f61-4899-9c8f-587ada3f2e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037615237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.4037615237
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3373963077
Short name T894
Test name
Test status
Simulation time 36457247 ps
CPU time 0.66 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 197828 kb
Host smart-364f5fb3-a664-45eb-987a-fa11e8c819de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373963077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3373963077
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2652111895
Short name T867
Test name
Test status
Simulation time 47259692 ps
CPU time 0.59 seconds
Started Jul 11 04:55:23 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 198096 kb
Host smart-c76a85d5-d65a-4e15-b294-1e4abdd9d9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652111895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2652111895
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.372614982
Short name T887
Test name
Test status
Simulation time 82868770 ps
CPU time 0.69 seconds
Started Jul 11 04:55:22 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 200944 kb
Host smart-0bcaed0d-c8f9-441b-ac4d-97e515db22e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372614982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid
.372614982
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.380584216
Short name T949
Test name
Test status
Simulation time 383121584 ps
CPU time 0.82 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 198012 kb
Host smart-6eb93f7b-923b-44e3-9a1f-235572b81061
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380584216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wak
eup_race.380584216
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.4269379780
Short name T954
Test name
Test status
Simulation time 91223985 ps
CPU time 0.77 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 198844 kb
Host smart-b49fee0e-c6a6-4b2d-8d01-0c1468fb14b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269379780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.4269379780
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.108165577
Short name T45
Test name
Test status
Simulation time 158625185 ps
CPU time 0.83 seconds
Started Jul 11 04:55:23 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 209160 kb
Host smart-0e4d7ade-f968-4beb-981f-49d6a419700c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108165577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.108165577
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3525513495
Short name T492
Test name
Test status
Simulation time 900108978 ps
CPU time 2 seconds
Started Jul 11 04:55:22 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 200872 kb
Host smart-4f35f8e7-dc19-43da-9396-11c715404a64
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525513495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3525513495
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3420498107
Short name T428
Test name
Test status
Simulation time 861395195 ps
CPU time 3.29 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 200884 kb
Host smart-8a9cdc38-519c-4be6-8e37-f2755209b27c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420498107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3420498107
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.4044240890
Short name T231
Test name
Test status
Simulation time 96434970 ps
CPU time 0.86 seconds
Started Jul 11 04:55:20 PM PDT 24
Finished Jul 11 04:55:24 PM PDT 24
Peak memory 198952 kb
Host smart-2703c446-0492-4306-bfc0-0bebd4ec42c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044240890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4044240890
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2884237317
Short name T942
Test name
Test status
Simulation time 61264862 ps
CPU time 0.66 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 199064 kb
Host smart-c2892d5b-3a8c-4a47-b7d4-0a8395881c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884237317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2884237317
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.831637562
Short name T248
Test name
Test status
Simulation time 1247773967 ps
CPU time 3.1 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 200804 kb
Host smart-7a860405-4eba-410b-a8dd-ead5786e9ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831637562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.831637562
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.4055470263
Short name T48
Test name
Test status
Simulation time 7842977238 ps
CPU time 27.4 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 200952 kb
Host smart-9f34bfe5-ed5d-4327-8ba6-617f6d09d86a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055470263 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.4055470263
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.1891901654
Short name T213
Test name
Test status
Simulation time 71659290 ps
CPU time 0.82 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:21 PM PDT 24
Peak memory 198780 kb
Host smart-c0aa05db-abd6-4354-b630-64e5717380cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891901654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1891901654
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.45405881
Short name T928
Test name
Test status
Simulation time 493471797 ps
CPU time 1.12 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 200604 kb
Host smart-e675e773-84db-4d34-8811-65983897dbbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45405881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.45405881
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2167367761
Short name T704
Test name
Test status
Simulation time 27034880 ps
CPU time 0.64 seconds
Started Jul 11 04:55:43 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 198788 kb
Host smart-67c5de8e-83d6-4c63-a1cd-fd02196f9b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167367761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2167367761
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.406930032
Short name T446
Test name
Test status
Simulation time 70911409 ps
CPU time 0.83 seconds
Started Jul 11 04:55:45 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 198808 kb
Host smart-a832aacf-dbf0-4d68-8c16-63ed8cb5b524
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406930032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disa
ble_rom_integrity_check.406930032
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1290613055
Short name T530
Test name
Test status
Simulation time 29628919 ps
CPU time 0.64 seconds
Started Jul 11 04:55:52 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 197612 kb
Host smart-8bd1e5fd-d737-44e3-9543-58fc282cdefd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290613055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1290613055
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3496005900
Short name T168
Test name
Test status
Simulation time 648376940 ps
CPU time 0.97 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 197796 kb
Host smart-2bc545f5-dcbf-44d5-889f-112726a91cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496005900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3496005900
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.1369284754
Short name T672
Test name
Test status
Simulation time 64528522 ps
CPU time 0.76 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 197652 kb
Host smart-9bbbc316-a6d9-40e4-b63b-252d5ff1b878
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369284754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1369284754
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.829711245
Short name T767
Test name
Test status
Simulation time 60244948 ps
CPU time 0.6 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 197736 kb
Host smart-8bbaf96b-45e0-4fae-a40c-fd8d31fb31da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829711245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.829711245
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.2887004205
Short name T550
Test name
Test status
Simulation time 41815108 ps
CPU time 0.71 seconds
Started Jul 11 04:55:47 PM PDT 24
Finished Jul 11 04:55:55 PM PDT 24
Peak memory 201068 kb
Host smart-9cddf164-9320-464a-af7e-cce679de3a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887004205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.2887004205
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.2071757885
Short name T642
Test name
Test status
Simulation time 168926428 ps
CPU time 0.78 seconds
Started Jul 11 04:55:53 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 198852 kb
Host smart-f1acddd8-77b0-41cd-a1ba-3f6cd3c47f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071757885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.2071757885
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.1064343692
Short name T823
Test name
Test status
Simulation time 108659878 ps
CPU time 0.73 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 198752 kb
Host smart-424d7fed-d399-46be-82ee-ab1b29d4a493
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064343692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1064343692
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1738262232
Short name T993
Test name
Test status
Simulation time 109954326 ps
CPU time 1.02 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 209184 kb
Host smart-0b20751c-98bd-40f3-9cfc-a7ea18da4065
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738262232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1738262232
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1628403814
Short name T362
Test name
Test status
Simulation time 393599992 ps
CPU time 1.04 seconds
Started Jul 11 04:55:45 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 199520 kb
Host smart-6072017a-5914-40f2-8088-f3e4727aa746
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628403814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.1628403814
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1023335890
Short name T878
Test name
Test status
Simulation time 924917585 ps
CPU time 2.3 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 200592 kb
Host smart-4a8737c4-f5ed-421b-aa3e-711fe90f4230
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023335890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1023335890
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2433980607
Short name T250
Test name
Test status
Simulation time 1098502977 ps
CPU time 2.45 seconds
Started Jul 11 04:55:54 PM PDT 24
Finished Jul 11 04:56:01 PM PDT 24
Peak memory 200860 kb
Host smart-8cd6b5ab-782c-45f2-8457-adce9c249183
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433980607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2433980607
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.677847639
Short name T532
Test name
Test status
Simulation time 196056639 ps
CPU time 0.88 seconds
Started Jul 11 04:55:54 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 199084 kb
Host smart-c9758e6e-8a90-4e34-ba38-3593726ad6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677847639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_
mubi.677847639
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1591063910
Short name T798
Test name
Test status
Simulation time 64061996 ps
CPU time 0.66 seconds
Started Jul 11 04:55:44 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 197980 kb
Host smart-318e4701-75e6-4f95-bd8d-3b3271bfac95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591063910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1591063910
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.2937483784
Short name T992
Test name
Test status
Simulation time 3314740194 ps
CPU time 4.79 seconds
Started Jul 11 04:55:44 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 200944 kb
Host smart-60225529-6bc1-4b34-ac33-6739173fe458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937483784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.2937483784
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.1867246459
Short name T133
Test name
Test status
Simulation time 9396538700 ps
CPU time 13.96 seconds
Started Jul 11 04:55:46 PM PDT 24
Finished Jul 11 04:56:08 PM PDT 24
Peak memory 201260 kb
Host smart-2d26be34-367a-4e21-843c-554d90a17c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867246459 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.1867246459
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.2748982780
Short name T695
Test name
Test status
Simulation time 222378895 ps
CPU time 1.22 seconds
Started Jul 11 04:55:44 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 199408 kb
Host smart-857cb0ea-daa4-4693-8ef9-ce2619614f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748982780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.2748982780
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.3684987863
Short name T621
Test name
Test status
Simulation time 99282677 ps
CPU time 0.89 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 198864 kb
Host smart-b72eb82e-63de-4a27-9ebc-2d2cc45c53a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684987863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3684987863
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3971680301
Short name T1
Test name
Test status
Simulation time 96358536 ps
CPU time 0.75 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 198536 kb
Host smart-78443d8f-ba82-406e-a9f7-7f8ca12ab557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971680301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3971680301
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.532427824
Short name T511
Test name
Test status
Simulation time 77433407 ps
CPU time 0.71 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 198728 kb
Host smart-4a1c7da6-a81c-42fd-98a0-1ea04ac0e321
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532427824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.532427824
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.2537583726
Short name T697
Test name
Test status
Simulation time 50545474 ps
CPU time 0.62 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 196956 kb
Host smart-19e40f95-b89f-469e-ba72-4704136bd2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537583726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.2537583726
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.2595193598
Short name T667
Test name
Test status
Simulation time 169050172 ps
CPU time 0.99 seconds
Started Jul 11 04:55:53 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 198076 kb
Host smart-259bb0f6-9c18-4973-ac45-f0751c2de74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595193598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2595193598
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1312470048
Short name T653
Test name
Test status
Simulation time 42886755 ps
CPU time 0.66 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 197804 kb
Host smart-e038008c-73e1-434f-976e-a93c44433a9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312470048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1312470048
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.3401020899
Short name T262
Test name
Test status
Simulation time 74468235 ps
CPU time 0.62 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 197740 kb
Host smart-3e2625de-c045-4aae-9030-76f9cc7fd29b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401020899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.3401020899
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.317281612
Short name T445
Test name
Test status
Simulation time 39521190 ps
CPU time 0.73 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 201328 kb
Host smart-26c22e66-22a6-46d7-810f-8f7377ee87d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317281612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.317281612
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.3759274342
Short name T457
Test name
Test status
Simulation time 196805770 ps
CPU time 1.03 seconds
Started Jul 11 04:55:46 PM PDT 24
Finished Jul 11 04:55:55 PM PDT 24
Peak memory 199176 kb
Host smart-b22eef24-58f5-49d5-a7a8-dbb9ce060d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759274342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.3759274342
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2442514860
Short name T890
Test name
Test status
Simulation time 95869913 ps
CPU time 0.74 seconds
Started Jul 11 04:55:43 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 198700 kb
Host smart-23a1a852-11d5-4647-85c4-d66b886d760e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442514860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2442514860
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.98938404
Short name T688
Test name
Test status
Simulation time 99818678 ps
CPU time 1.05 seconds
Started Jul 11 04:55:54 PM PDT 24
Finished Jul 11 04:56:00 PM PDT 24
Peak memory 209200 kb
Host smart-926a8b70-ba2d-4aa0-901d-1ac26a438d16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98938404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.98938404
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.101792841
Short name T592
Test name
Test status
Simulation time 192507754 ps
CPU time 1.09 seconds
Started Jul 11 04:55:45 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 199668 kb
Host smart-93036115-a84d-4d95-badb-547ce77e8419
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101792841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_c
m_ctrl_config_regwen.101792841
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.337691335
Short name T374
Test name
Test status
Simulation time 962785900 ps
CPU time 2.13 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 200920 kb
Host smart-1c63f44c-c661-41d6-b1d0-2d9f854dc330
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337691335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.337691335
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3898346684
Short name T494
Test name
Test status
Simulation time 873077806 ps
CPU time 2.91 seconds
Started Jul 11 04:55:46 PM PDT 24
Finished Jul 11 04:55:56 PM PDT 24
Peak memory 200844 kb
Host smart-6b2fd385-7ba2-4df9-8c9b-919b1c8dbf4a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898346684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3898346684
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2271289898
Short name T636
Test name
Test status
Simulation time 90616921 ps
CPU time 0.97 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 199016 kb
Host smart-9edfcdfc-8c5e-46eb-a7dd-640a05cf4138
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271289898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2271289898
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1590234517
Short name T983
Test name
Test status
Simulation time 65092807 ps
CPU time 0.66 seconds
Started Jul 11 04:55:42 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 199064 kb
Host smart-e0a2a5b2-ad7b-4085-932c-d1aa32fc028e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590234517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1590234517
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.1454755114
Short name T873
Test name
Test status
Simulation time 2192944832 ps
CPU time 3.34 seconds
Started Jul 11 04:55:48 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 200940 kb
Host smart-62862a00-dfea-49fb-8951-5de6d1bc3b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454755114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1454755114
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3349974047
Short name T600
Test name
Test status
Simulation time 6736251509 ps
CPU time 15 seconds
Started Jul 11 04:55:47 PM PDT 24
Finished Jul 11 04:56:09 PM PDT 24
Peak memory 201024 kb
Host smart-e706aeb0-7897-4339-b962-dc4f6e6dccdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349974047 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.3349974047
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.3825823795
Short name T561
Test name
Test status
Simulation time 206585042 ps
CPU time 1.2 seconds
Started Jul 11 04:55:53 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 199332 kb
Host smart-0fd0aeee-1f53-4d2f-9122-9e6ef2d6dd0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825823795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.3825823795
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.2500880825
Short name T941
Test name
Test status
Simulation time 287477422 ps
CPU time 1.12 seconds
Started Jul 11 04:55:42 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 200936 kb
Host smart-e01068ea-01d2-491d-be4e-42b65c158f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500880825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.2500880825
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.2206066411
Short name T634
Test name
Test status
Simulation time 121292847 ps
CPU time 0.87 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 199724 kb
Host smart-64f592fb-dccb-44e2-a364-6b74444669da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206066411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2206066411
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1362094095
Short name T3
Test name
Test status
Simulation time 28558405 ps
CPU time 0.64 seconds
Started Jul 11 04:55:54 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 197012 kb
Host smart-ff2fe920-27d2-4b7f-8bb7-240473e6cfb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362094095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1362094095
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3627885199
Short name T819
Test name
Test status
Simulation time 587360702 ps
CPU time 0.96 seconds
Started Jul 11 04:55:52 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 197724 kb
Host smart-f0ba94ed-2404-4f2c-b76e-31a76dade89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627885199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3627885199
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.4051169000
Short name T476
Test name
Test status
Simulation time 61442273 ps
CPU time 0.65 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 196944 kb
Host smart-0f4529a5-452f-4013-9fc7-4777aa2025d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051169000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.4051169000
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.950020014
Short name T235
Test name
Test status
Simulation time 37007578 ps
CPU time 0.65 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:01 PM PDT 24
Peak memory 198092 kb
Host smart-f2bf7537-3f7b-4b48-ad7b-094dc1c634e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950020014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.950020014
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2070895231
Short name T528
Test name
Test status
Simulation time 128158416 ps
CPU time 0.68 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:09 PM PDT 24
Peak memory 201084 kb
Host smart-1c761475-19a0-4862-89e0-8e5c2cf1dd14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070895231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2070895231
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.3278167981
Short name T769
Test name
Test status
Simulation time 349172055 ps
CPU time 0.93 seconds
Started Jul 11 04:55:53 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 199448 kb
Host smart-6f5a4799-5ab0-4a2d-a268-ab982530573a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278167981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.3278167981
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.848963364
Short name T285
Test name
Test status
Simulation time 112153169 ps
CPU time 0.94 seconds
Started Jul 11 04:55:48 PM PDT 24
Finished Jul 11 04:55:55 PM PDT 24
Peak memory 199424 kb
Host smart-8bcdc7ac-86d2-448b-9f9e-8c2404a55a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848963364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.848963364
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3451816120
Short name T922
Test name
Test status
Simulation time 98936825 ps
CPU time 1.03 seconds
Started Jul 11 04:55:51 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 209260 kb
Host smart-6194d303-961f-4b92-b2ef-9a121791437c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451816120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3451816120
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2994527432
Short name T912
Test name
Test status
Simulation time 117446195 ps
CPU time 0.91 seconds
Started Jul 11 04:55:51 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 199616 kb
Host smart-6e26463d-232e-455e-b93d-fc76602a8c95
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994527432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2994527432
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3308364022
Short name T201
Test name
Test status
Simulation time 1960805705 ps
CPU time 2.02 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 200696 kb
Host smart-b84cdc42-8b1d-49de-a001-91e783f3b780
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308364022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3308364022
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445550198
Short name T856
Test name
Test status
Simulation time 1490637635 ps
CPU time 2.12 seconds
Started Jul 11 04:55:52 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 200808 kb
Host smart-644beb1a-3497-44a1-97c7-57b375be2989
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445550198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445550198
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2243313940
Short name T940
Test name
Test status
Simulation time 233728256 ps
CPU time 0.92 seconds
Started Jul 11 04:55:51 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 199028 kb
Host smart-a6944364-1e5e-4815-9bbf-33b5a22473ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243313940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2243313940
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3119421680
Short name T536
Test name
Test status
Simulation time 26331484 ps
CPU time 0.76 seconds
Started Jul 11 04:55:58 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 199016 kb
Host smart-f6a3d1a8-d204-4cf1-8e5b-da5a0e34d36b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119421680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3119421680
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.2275322960
Short name T96
Test name
Test status
Simulation time 630966810 ps
CPU time 2.82 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 200804 kb
Host smart-fd7101fd-77c6-43bf-9380-7269748f66d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275322960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.2275322960
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.14157345
Short name T76
Test name
Test status
Simulation time 9128039688 ps
CPU time 25.64 seconds
Started Jul 11 04:55:56 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 200928 kb
Host smart-2e9097b2-d8ca-4fd7-a99c-656e64d46716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157345 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.14157345
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.2949725613
Short name T910
Test name
Test status
Simulation time 89823325 ps
CPU time 0.77 seconds
Started Jul 11 04:55:55 PM PDT 24
Finished Jul 11 04:56:00 PM PDT 24
Peak memory 198124 kb
Host smart-5adf77cb-41af-460d-abbc-f9af1abb9837
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949725613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2949725613
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.3492979188
Short name T837
Test name
Test status
Simulation time 198640373 ps
CPU time 1.16 seconds
Started Jul 11 04:55:55 PM PDT 24
Finished Jul 11 04:56:00 PM PDT 24
Peak memory 199720 kb
Host smart-e21c475d-369a-401a-bf6a-0b2446539009
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492979188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3492979188
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2716925977
Short name T551
Test name
Test status
Simulation time 31308848 ps
CPU time 0.76 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 198656 kb
Host smart-d4f4e2a0-7d57-4875-b1a4-7915e0c65829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716925977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2716925977
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.836537669
Short name T900
Test name
Test status
Simulation time 57689592 ps
CPU time 0.85 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 198788 kb
Host smart-ee932622-8939-47c1-85ec-f9ef9f454d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836537669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.836537669
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2224984509
Short name T923
Test name
Test status
Simulation time 40074287 ps
CPU time 0.63 seconds
Started Jul 11 04:56:00 PM PDT 24
Finished Jul 11 04:56:06 PM PDT 24
Peak memory 197716 kb
Host smart-b39582c6-7ed9-4f6d-bde3-b881e8b63f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224984509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2224984509
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.4082558011
Short name T516
Test name
Test status
Simulation time 293406825 ps
CPU time 1 seconds
Started Jul 11 04:55:59 PM PDT 24
Finished Jul 11 04:56:05 PM PDT 24
Peak memory 197692 kb
Host smart-bf8b3228-5237-4c9a-af13-f556d77f6fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082558011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4082558011
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3214680238
Short name T623
Test name
Test status
Simulation time 41256906 ps
CPU time 0.63 seconds
Started Jul 11 04:56:00 PM PDT 24
Finished Jul 11 04:56:06 PM PDT 24
Peak memory 196992 kb
Host smart-a2f3c8da-313b-49ec-9fa3-5af0fa81287a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214680238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3214680238
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2148581614
Short name T5
Test name
Test status
Simulation time 287412338 ps
CPU time 0.63 seconds
Started Jul 11 04:55:58 PM PDT 24
Finished Jul 11 04:56:04 PM PDT 24
Peak memory 197988 kb
Host smart-fc1b76b3-340c-4af6-bb41-d8f5de5bc530
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148581614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2148581614
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2287431132
Short name T393
Test name
Test status
Simulation time 99779955 ps
CPU time 0.64 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 201028 kb
Host smart-2fbee68b-fd71-481d-8b4c-d3af0c7037ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287431132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2287431132
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.1741554919
Short name T271
Test name
Test status
Simulation time 185625826 ps
CPU time 0.91 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:13 PM PDT 24
Peak memory 198132 kb
Host smart-0cc86e78-36b3-4231-bc28-f87f7a81051d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741554919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.1741554919
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3610268979
Short name T461
Test name
Test status
Simulation time 83546040 ps
CPU time 0.77 seconds
Started Jul 11 04:55:57 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 198696 kb
Host smart-81e2fe70-341b-41c5-b841-46db18022f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610268979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3610268979
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1593439823
Short name T38
Test name
Test status
Simulation time 126948439 ps
CPU time 0.86 seconds
Started Jul 11 04:55:59 PM PDT 24
Finished Jul 11 04:56:04 PM PDT 24
Peak memory 209212 kb
Host smart-025144a4-22f3-4f26-8f24-6a1c52d08227
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593439823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1593439823
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2286013534
Short name T736
Test name
Test status
Simulation time 149746925 ps
CPU time 0.76 seconds
Started Jul 11 04:55:59 PM PDT 24
Finished Jul 11 04:56:04 PM PDT 24
Peak memory 198376 kb
Host smart-5e32ff80-9989-4ceb-ae44-99226c9f599e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286013534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.2286013534
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1557997269
Short name T924
Test name
Test status
Simulation time 860975718 ps
CPU time 3.09 seconds
Started Jul 11 04:55:59 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 200764 kb
Host smart-536340fe-16f6-4e7b-97e6-ddc63624a6b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557997269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1557997269
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.650608326
Short name T613
Test name
Test status
Simulation time 881809682 ps
CPU time 3.23 seconds
Started Jul 11 04:55:55 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 200784 kb
Host smart-257a3fa1-c21d-4b12-9c50-e13fef9e7b77
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650608326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.650608326
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2391379079
Short name T548
Test name
Test status
Simulation time 75126066 ps
CPU time 0.94 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198868 kb
Host smart-a5eaca1c-2234-4307-a15f-3822bd2043d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391379079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2391379079
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2899551339
Short name T422
Test name
Test status
Simulation time 114312801 ps
CPU time 0.63 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 197884 kb
Host smart-ad7084e4-590c-4143-9a42-ee9b0a2d45c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899551339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2899551339
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.4068292376
Short name T602
Test name
Test status
Simulation time 1703779670 ps
CPU time 2.02 seconds
Started Jul 11 04:55:58 PM PDT 24
Finished Jul 11 04:56:05 PM PDT 24
Peak memory 200596 kb
Host smart-fbd2ec6a-68fc-4f9b-aaf2-b98830a7b76e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068292376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.4068292376
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.4115302940
Short name T985
Test name
Test status
Simulation time 6773761447 ps
CPU time 24.69 seconds
Started Jul 11 04:55:55 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 200956 kb
Host smart-3777e9f1-86f4-407a-8ce1-d28a2cf0eba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115302940 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.4115302940
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.193405583
Short name T766
Test name
Test status
Simulation time 210144213 ps
CPU time 0.8 seconds
Started Jul 11 04:55:58 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 198236 kb
Host smart-2d25dfed-6b6a-4aa6-98cd-fc815528d387
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193405583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.193405583
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.2324367133
Short name T130
Test name
Test status
Simulation time 119528345 ps
CPU time 0.91 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 198856 kb
Host smart-2515ab43-2151-4f09-a4b1-2c362f6f2709
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324367133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.2324367133
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1084101868
Short name T585
Test name
Test status
Simulation time 45909804 ps
CPU time 0.96 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 200024 kb
Host smart-33bc3f77-92d3-469e-9817-d7e738b542cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084101868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1084101868
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3510588395
Short name T141
Test name
Test status
Simulation time 90655508 ps
CPU time 0.7 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 198872 kb
Host smart-3cc64076-9c84-44f2-8678-a69d65a6e934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510588395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3510588395
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1389826948
Short name T484
Test name
Test status
Simulation time 33657284 ps
CPU time 0.61 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 197612 kb
Host smart-21998e47-043c-42a4-9fbd-eac9e80c5c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389826948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1389826948
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2097799437
Short name T675
Test name
Test status
Simulation time 2496002636 ps
CPU time 0.93 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:08 PM PDT 24
Peak memory 198144 kb
Host smart-bbb5d3ea-ed65-460f-a7ad-e1fec8b0b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097799437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2097799437
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.4245473978
Short name T732
Test name
Test status
Simulation time 44339552 ps
CPU time 0.61 seconds
Started Jul 11 04:56:08 PM PDT 24
Finished Jul 11 04:56:19 PM PDT 24
Peak memory 196932 kb
Host smart-4a1ddc8d-32b4-461b-ab19-c1aab8f5ca53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245473978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.4245473978
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3388057001
Short name T678
Test name
Test status
Simulation time 34025481 ps
CPU time 0.62 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 198044 kb
Host smart-8e06a95f-880d-42c9-97df-2b7fc98b2fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388057001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3388057001
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.370006454
Short name T240
Test name
Test status
Simulation time 40997277 ps
CPU time 0.74 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 201328 kb
Host smart-582d3c69-d4a2-4172-a227-8e09d194fe65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370006454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invali
d.370006454
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.2930031900
Short name T303
Test name
Test status
Simulation time 400573011 ps
CPU time 1.24 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:09 PM PDT 24
Peak memory 199336 kb
Host smart-120fcc6e-fb71-4d82-9ad1-36067ce5ed8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930031900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.2930031900
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2778900354
Short name T556
Test name
Test status
Simulation time 23067012 ps
CPU time 0.65 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 197972 kb
Host smart-b9ab3aab-5e8b-4ced-8936-1b6e61d04ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778900354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2778900354
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.779314135
Short name T886
Test name
Test status
Simulation time 150714681 ps
CPU time 0.79 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 209096 kb
Host smart-d50532f8-0013-4791-8415-9555452c49a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779314135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.779314135
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.4020289426
Short name T722
Test name
Test status
Simulation time 196636615 ps
CPU time 1.02 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 199276 kb
Host smart-c4ab315c-0f83-4736-b984-eb15e4fc630b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020289426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.4020289426
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2350064608
Short name T637
Test name
Test status
Simulation time 775144552 ps
CPU time 3.28 seconds
Started Jul 11 04:55:59 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 200728 kb
Host smart-c20c5d4a-0e90-41fc-9554-48af48bdb719
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350064608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2350064608
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3711182396
Short name T306
Test name
Test status
Simulation time 1471556588 ps
CPU time 1.79 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:15 PM PDT 24
Peak memory 200444 kb
Host smart-8ddbe87d-c353-4927-bab7-a19fc548c9d8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711182396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3711182396
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.721190631
Short name T917
Test name
Test status
Simulation time 67149130 ps
CPU time 0.97 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:08 PM PDT 24
Peak memory 198972 kb
Host smart-0ad8f1a8-1668-48f3-a6e0-d2e7207656f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721190631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.721190631
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2222182152
Short name T479
Test name
Test status
Simulation time 93596993 ps
CPU time 0.63 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 198192 kb
Host smart-35a7a497-1849-4ce1-9d43-463f44f6cd9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222182152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2222182152
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.4031451906
Short name T92
Test name
Test status
Simulation time 231323219 ps
CPU time 1.73 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:10 PM PDT 24
Peak memory 200764 kb
Host smart-9dc35977-2c2e-46b4-aa4d-6f58620a24cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031451906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.4031451906
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.3245507827
Short name T507
Test name
Test status
Simulation time 1337611170 ps
CPU time 3.92 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 200984 kb
Host smart-f38a88dc-895c-46a5-9b8c-94b9d3f5dd69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245507827 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.3245507827
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.342932152
Short name T839
Test name
Test status
Simulation time 131822213 ps
CPU time 0.81 seconds
Started Jul 11 04:56:01 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 198268 kb
Host smart-0a124df6-5a68-430f-9a7e-64f4512bc848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342932152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.342932152
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.1050480852
Short name T938
Test name
Test status
Simulation time 583894761 ps
CPU time 0.95 seconds
Started Jul 11 04:56:00 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 199840 kb
Host smart-499187c5-3c9c-4002-ab0b-cf8959aa25c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050480852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.1050480852
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.2246724225
Short name T123
Test name
Test status
Simulation time 113896547 ps
CPU time 0.88 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:10 PM PDT 24
Peak memory 200220 kb
Host smart-0adb6f18-e996-49ed-b9c6-2d1b826fdd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246724225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.2246724225
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1332657718
Short name T204
Test name
Test status
Simulation time 70874227 ps
CPU time 0.7 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 198420 kb
Host smart-3760a7d9-26a6-4e06-b0dc-13004d665532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332657718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1332657718
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.4204048788
Short name T305
Test name
Test status
Simulation time 29080876 ps
CPU time 0.72 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 196924 kb
Host smart-d77bdbc9-e648-4333-858c-1a7ad7a1552d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204048788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.4204048788
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.857411374
Short name T542
Test name
Test status
Simulation time 1153420271 ps
CPU time 0.98 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 197700 kb
Host smart-b3e11ab1-8725-4c69-ab7f-151611acc030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857411374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.857411374
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3615451421
Short name T802
Test name
Test status
Simulation time 50590506 ps
CPU time 0.68 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:09 PM PDT 24
Peak memory 197792 kb
Host smart-1083b295-56b4-45aa-b127-8c9abb3ae82b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615451421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3615451421
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.961989946
Short name T711
Test name
Test status
Simulation time 49361563 ps
CPU time 0.75 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 201120 kb
Host smart-72e250ad-0b24-488d-92e9-8b0561341500
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961989946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invali
d.961989946
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1896651476
Short name T998
Test name
Test status
Simulation time 154105204 ps
CPU time 1.05 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 199256 kb
Host smart-474504ce-5a38-447b-91d1-5c92ac1da6d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896651476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1896651476
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.1847364343
Short name T999
Test name
Test status
Simulation time 93457729 ps
CPU time 0.98 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 199360 kb
Host smart-b51a8a2f-6992-4818-b71b-5d7a4c03552a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847364343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.1847364343
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1706743843
Short name T967
Test name
Test status
Simulation time 100575035 ps
CPU time 0.9 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:13 PM PDT 24
Peak memory 209288 kb
Host smart-cea1e753-6ad8-4c9e-af08-04a5ffecafda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706743843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1706743843
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.1327946528
Short name T332
Test name
Test status
Simulation time 150512099 ps
CPU time 0.69 seconds
Started Jul 11 05:01:05 PM PDT 24
Finished Jul 11 05:01:07 PM PDT 24
Peak memory 198308 kb
Host smart-0a8fb016-8cca-457d-972f-242d49515523
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327946528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.1327946528
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.260589836
Short name T454
Test name
Test status
Simulation time 792238313 ps
CPU time 3.02 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 200672 kb
Host smart-e99dad3c-9da3-40b2-ac70-b8b87d857858
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260589836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.260589836
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3989213468
Short name T836
Test name
Test status
Simulation time 977623975 ps
CPU time 2.21 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 200748 kb
Host smart-56709281-7b58-42fa-ba44-0ecfbadf2af4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989213468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3989213468
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4151919884
Short name T498
Test name
Test status
Simulation time 64453891 ps
CPU time 0.84 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 199164 kb
Host smart-2525abf8-4d14-476d-ae50-c669a6145c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151919884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4151919884
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.4173380591
Short name T241
Test name
Test status
Simulation time 36523710 ps
CPU time 0.64 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 198212 kb
Host smart-99cced70-002f-4f10-9e7e-a3e5e76a0cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173380591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.4173380591
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.2623471741
Short name T328
Test name
Test status
Simulation time 1858337019 ps
CPU time 2.97 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 200784 kb
Host smart-5ad488c8-2357-4f34-8176-0d2ec104003a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623471741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2623471741
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3567417975
Short name T631
Test name
Test status
Simulation time 4960167405 ps
CPU time 10.76 seconds
Started Jul 11 04:56:08 PM PDT 24
Finished Jul 11 04:56:28 PM PDT 24
Peak memory 201064 kb
Host smart-8b369fcc-8327-486a-80f5-5de7a8d89114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567417975 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.3567417975
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.3621236656
Short name T178
Test name
Test status
Simulation time 259559130 ps
CPU time 0.92 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 199488 kb
Host smart-34eaf3ae-05f0-41e6-9d41-92fe656212df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621236656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.3621236656
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.4077698048
Short name T751
Test name
Test status
Simulation time 273707061 ps
CPU time 1.01 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 199920 kb
Host smart-023f694c-93b6-4e94-8c42-98bf9ec8bdeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077698048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.4077698048
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.577620775
Short name T517
Test name
Test status
Simulation time 90719159 ps
CPU time 0.73 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198548 kb
Host smart-42917db7-01d0-4a56-a118-b335d9084c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577620775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.577620775
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.37318102
Short name T188
Test name
Test status
Simulation time 90614442 ps
CPU time 0.71 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 198788 kb
Host smart-e4ce92f8-73ea-4577-b296-39f120035fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disab
le_rom_integrity_check.37318102
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4279469669
Short name T626
Test name
Test status
Simulation time 29036404 ps
CPU time 0.64 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 197008 kb
Host smart-cb927489-f299-4e3a-92f2-a47f404a722d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279469669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.4279469669
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.1409835553
Short name T456
Test name
Test status
Simulation time 604993655 ps
CPU time 1 seconds
Started Jul 11 04:56:02 PM PDT 24
Finished Jul 11 04:56:09 PM PDT 24
Peak memory 197824 kb
Host smart-5c69bf3c-edd3-4e03-9ce1-304f26976294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409835553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1409835553
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3516961423
Short name T16
Test name
Test status
Simulation time 41728062 ps
CPU time 0.69 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 197032 kb
Host smart-cf127312-7dfe-476d-96ea-555be4afc435
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516961423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3516961423
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2180536578
Short name T217
Test name
Test status
Simulation time 44732096 ps
CPU time 0.65 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 198092 kb
Host smart-f3379a5a-739b-4f5a-b16d-220eea84f38c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180536578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2180536578
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3444107042
Short name T227
Test name
Test status
Simulation time 111865531 ps
CPU time 0.7 seconds
Started Jul 11 04:56:03 PM PDT 24
Finished Jul 11 04:56:11 PM PDT 24
Peak memory 200960 kb
Host smart-10263a7c-c477-4d28-bda1-cee3d7abb5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444107042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3444107042
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.3248257003
Short name T826
Test name
Test status
Simulation time 166160208 ps
CPU time 0.86 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 198152 kb
Host smart-f9c8c783-2e13-4c14-bf39-58617f448cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248257003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.3248257003
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2103515847
Short name T596
Test name
Test status
Simulation time 74131330 ps
CPU time 0.78 seconds
Started Jul 11 04:56:08 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 198800 kb
Host smart-5ff5b17c-5822-4390-af96-069ad3fc9eee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103515847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2103515847
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1733790502
Short name T482
Test name
Test status
Simulation time 176841242 ps
CPU time 0.82 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198544 kb
Host smart-1d2c2326-aa04-4114-bfd3-93d4cd0c2e7f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733790502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.1733790502
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4123785008
Short name T784
Test name
Test status
Simulation time 784062248 ps
CPU time 3 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 200724 kb
Host smart-53324af4-2167-42bf-bc1f-c2442482079b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123785008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4123785008
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2728718547
Short name T467
Test name
Test status
Simulation time 1039682841 ps
CPU time 2.28 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:22 PM PDT 24
Peak memory 200756 kb
Host smart-0bb9aa62-9a1c-43e1-8803-0cbfed0fb3fe
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728718547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2728718547
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2708113368
Short name T131
Test name
Test status
Simulation time 171657221 ps
CPU time 0.88 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198464 kb
Host smart-3195ff69-8ac7-4945-b37b-2b63fc321aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708113368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2708113368
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.12606019
Short name T274
Test name
Test status
Simulation time 80553928 ps
CPU time 0.63 seconds
Started Jul 11 04:56:05 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 198140 kb
Host smart-d0fe6a29-4d3c-4657-9eb9-0128b25db8af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12606019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.12606019
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.1720217551
Short name T129
Test name
Test status
Simulation time 164072865 ps
CPU time 1.04 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 197900 kb
Host smart-07ffb031-c047-4298-a1ee-b5ec8b16f23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720217551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.1720217551
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.3576774443
Short name T925
Test name
Test status
Simulation time 11010045449 ps
CPU time 14.21 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:35 PM PDT 24
Peak memory 201032 kb
Host smart-deafdaba-735e-4342-9103-4e4080d1b6ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576774443 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.3576774443
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.1815451239
Short name T1000
Test name
Test status
Simulation time 225537321 ps
CPU time 0.85 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:13 PM PDT 24
Peak memory 199260 kb
Host smart-982fafca-da21-49d1-a248-25ba8bf70efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815451239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.1815451239
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.3942359796
Short name T151
Test name
Test status
Simulation time 358565134 ps
CPU time 0.77 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198188 kb
Host smart-ea407cb3-ba2f-4f1e-8426-d95bce0dd227
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942359796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3942359796
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1624367521
Short name T444
Test name
Test status
Simulation time 38004067 ps
CPU time 0.91 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:21 PM PDT 24
Peak memory 200188 kb
Host smart-0b054870-af23-4b78-b5db-56c881c0ab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624367521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1624367521
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.2407261918
Short name T801
Test name
Test status
Simulation time 79805789 ps
CPU time 0.77 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198800 kb
Host smart-1612f8d6-fbd0-4a6b-b134-43020683983a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407261918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.2407261918
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2777089286
Short name T170
Test name
Test status
Simulation time 31048540 ps
CPU time 0.6 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 197620 kb
Host smart-66642f29-398e-43dd-9f33-34d50efd7f56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777089286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2777089286
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.2386612580
Short name T331
Test name
Test status
Simulation time 332593677 ps
CPU time 0.94 seconds
Started Jul 11 04:56:08 PM PDT 24
Finished Jul 11 04:56:19 PM PDT 24
Peak memory 198032 kb
Host smart-d317c4a4-7354-41b6-94aa-605448c347da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386612580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2386612580
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.428250192
Short name T540
Test name
Test status
Simulation time 76560476 ps
CPU time 0.65 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 198000 kb
Host smart-50adaea9-39ca-4cb4-bb33-0d49ec9bc76f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428250192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.428250192
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.4098827406
Short name T211
Test name
Test status
Simulation time 74925034 ps
CPU time 0.64 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 198096 kb
Host smart-c91d68af-e7fc-4f09-8c46-23b9ef661a56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098827406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.4098827406
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3785708090
Short name T392
Test name
Test status
Simulation time 43987719 ps
CPU time 0.73 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 201068 kb
Host smart-0026cba0-e4e4-4c80-bc89-e1ba8b34e7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785708090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3785708090
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.913375033
Short name T510
Test name
Test status
Simulation time 124610652 ps
CPU time 0.92 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 198500 kb
Host smart-371b06ca-741c-4fa2-b40f-d007d16323f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913375033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wa
keup_race.913375033
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2703028707
Short name T234
Test name
Test status
Simulation time 73507019 ps
CPU time 0.98 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 199508 kb
Host smart-391afd50-112b-42a9-ac7e-e4c6d9eff5fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703028707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2703028707
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1099743159
Short name T228
Test name
Test status
Simulation time 95814424 ps
CPU time 0.96 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 209284 kb
Host smart-c2e57ca9-b1c5-46bf-b6bb-71f235ca0f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099743159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1099743159
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.495851972
Short name T152
Test name
Test status
Simulation time 163501905 ps
CPU time 0.97 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 199492 kb
Host smart-c7cde0fd-505f-4e1a-872b-063b47833e31
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495851972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_c
m_ctrl_config_regwen.495851972
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2773602972
Short name T727
Test name
Test status
Simulation time 806879482 ps
CPU time 3.25 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 200788 kb
Host smart-83564839-b872-41ea-a709-c3d988715656
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773602972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2773602972
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.311192195
Short name T555
Test name
Test status
Simulation time 1108782588 ps
CPU time 2.17 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 200840 kb
Host smart-10148009-a906-45aa-9712-074c39135030
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311192195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.311192195
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2009593804
Short name T841
Test name
Test status
Simulation time 87245352 ps
CPU time 0.97 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198968 kb
Host smart-df4f0977-3709-446d-8337-a2831fc02441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009593804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2009593804
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3578010531
Short name T905
Test name
Test status
Simulation time 88703185 ps
CPU time 0.62 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 198184 kb
Host smart-3fff5596-5ecf-43dc-b43a-2255e627e871
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578010531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3578010531
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.822429774
Short name T883
Test name
Test status
Simulation time 272385209 ps
CPU time 1.78 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:21 PM PDT 24
Peak memory 200740 kb
Host smart-26f2b161-6b6e-4f67-bc58-2116e4a5303e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822429774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.822429774
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.1951696889
Short name T589
Test name
Test status
Simulation time 7387042935 ps
CPU time 11.22 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 201092 kb
Host smart-5112a22e-28a4-42ea-b677-044baf94bb7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951696889 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.1951696889
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.1575412738
Short name T658
Test name
Test status
Simulation time 156401394 ps
CPU time 1.11 seconds
Started Jul 11 04:56:15 PM PDT 24
Finished Jul 11 04:56:27 PM PDT 24
Peak memory 198772 kb
Host smart-681f9d21-86b2-4756-b8be-844bc40696ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575412738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.1575412738
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.3683152100
Short name T773
Test name
Test status
Simulation time 49966593 ps
CPU time 0.68 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 198836 kb
Host smart-936f86a3-b7eb-4902-8f23-baf894fe8e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683152100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3683152100
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1072520163
Short name T417
Test name
Test status
Simulation time 29591315 ps
CPU time 0.64 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 198272 kb
Host smart-4a7f0720-9963-478b-95ae-ed0388e76d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072520163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1072520163
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1917456986
Short name T896
Test name
Test status
Simulation time 50315707 ps
CPU time 0.83 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 198864 kb
Host smart-bb9fcf28-2421-4a7b-8b53-cd0c8b23a230
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917456986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1917456986
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1923454026
Short name T901
Test name
Test status
Simulation time 39007662 ps
CPU time 0.62 seconds
Started Jul 11 04:56:04 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 197636 kb
Host smart-4f6a67d4-34f6-4d0a-b109-2e992845f4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923454026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1923454026
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.4121878340
Short name T381
Test name
Test status
Simulation time 1062224311 ps
CPU time 0.93 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 197788 kb
Host smart-eb3f0334-883b-49b8-a9e1-fd6b0a896d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121878340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4121878340
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.1650254764
Short name T686
Test name
Test status
Simulation time 54572796 ps
CPU time 0.67 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:21 PM PDT 24
Peak memory 197740 kb
Host smart-49f7541f-83ae-4c59-8a29-d1842da096fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650254764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.1650254764
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.2777241749
Short name T360
Test name
Test status
Simulation time 163454990 ps
CPU time 0.59 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 197780 kb
Host smart-20a60ff5-fb8b-446b-b8af-cf90f555b958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777241749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.2777241749
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.4240839023
Short name T311
Test name
Test status
Simulation time 43337781 ps
CPU time 0.7 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 201060 kb
Host smart-688f4848-c38e-4397-b605-1068e8170186
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240839023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.4240839023
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.1282869546
Short name T794
Test name
Test status
Simulation time 317364414 ps
CPU time 0.93 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:22 PM PDT 24
Peak memory 199464 kb
Host smart-c8917f0d-b4ad-4d31-996d-f716d3dd0495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282869546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.1282869546
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.22611783
Short name T617
Test name
Test status
Simulation time 42016756 ps
CPU time 0.65 seconds
Started Jul 11 04:56:13 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 198720 kb
Host smart-1809f8e9-ec92-4230-a78b-e02e6076704f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.22611783
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.199869843
Short name T827
Test name
Test status
Simulation time 124643953 ps
CPU time 0.83 seconds
Started Jul 11 04:56:08 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 209280 kb
Host smart-2cce0626-a3d0-442f-a4d7-884025d42a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199869843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.199869843
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1408224886
Short name T805
Test name
Test status
Simulation time 252767047 ps
CPU time 0.96 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 199668 kb
Host smart-fe4e662a-ed9c-40fa-abf2-e176b4c8c470
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408224886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.1408224886
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1141322225
Short name T382
Test name
Test status
Simulation time 952578337 ps
CPU time 2.49 seconds
Started Jul 11 04:56:09 PM PDT 24
Finished Jul 11 04:56:21 PM PDT 24
Peak memory 200876 kb
Host smart-907876be-c439-4be8-97aa-46fb70265a01
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141322225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1141322225
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.294546017
Short name T862
Test name
Test status
Simulation time 1338364715 ps
CPU time 2.17 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 200612 kb
Host smart-92c75168-0feb-4264-825e-0884345d5479
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294546017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.294546017
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.428943207
Short name T342
Test name
Test status
Simulation time 688099889 ps
CPU time 0.86 seconds
Started Jul 11 04:56:16 PM PDT 24
Finished Jul 11 04:56:28 PM PDT 24
Peak memory 199256 kb
Host smart-bce4991c-da30-4ff9-afa7-eec328468b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428943207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.428943207
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2614309969
Short name T547
Test name
Test status
Simulation time 31051414 ps
CPU time 0.66 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 198960 kb
Host smart-a041729d-b3b9-4c32-b8b2-b31314920879
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614309969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2614309969
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.2774406284
Short name T571
Test name
Test status
Simulation time 5574235220 ps
CPU time 3.61 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 200904 kb
Host smart-c1142ff2-b4a5-46d5-ae41-a5e227e98e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774406284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.2774406284
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.1783803563
Short name T147
Test name
Test status
Simulation time 10763768769 ps
CPU time 32 seconds
Started Jul 11 04:56:10 PM PDT 24
Finished Jul 11 04:56:51 PM PDT 24
Peak memory 201076 kb
Host smart-2cce231a-453c-4084-b2c1-bdd90fbf78ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783803563 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.1783803563
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.833402469
Short name T336
Test name
Test status
Simulation time 276694512 ps
CPU time 0.8 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 198280 kb
Host smart-50d8b0c6-1e75-4f9d-a1de-0aa54da494f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833402469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.833402469
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.3625376318
Short name T460
Test name
Test status
Simulation time 473011239 ps
CPU time 0.89 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 200640 kb
Host smart-3657f09c-e463-485f-8f95-b1d47a82d622
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625376318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.3625376318
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.27501235
Short name T888
Test name
Test status
Simulation time 40162183 ps
CPU time 0.68 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 198336 kb
Host smart-336870dd-d5a9-4491-8387-149561b31232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27501235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.27501235
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2314905723
Short name T502
Test name
Test status
Simulation time 62998221 ps
CPU time 0.88 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 198836 kb
Host smart-e52d59dd-97e6-4c98-a496-cd9a923c7ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314905723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2314905723
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1486008532
Short name T654
Test name
Test status
Simulation time 45513844 ps
CPU time 0.63 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:22 PM PDT 24
Peak memory 197024 kb
Host smart-a2101cdc-05d1-43c2-b315-889be7afb406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486008532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1486008532
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2455559180
Short name T386
Test name
Test status
Simulation time 602029349 ps
CPU time 0.96 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 197724 kb
Host smart-37814127-cd09-4f52-8e95-ec8c159b2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455559180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2455559180
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.3385790032
Short name T297
Test name
Test status
Simulation time 56591437 ps
CPU time 0.69 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 197740 kb
Host smart-5253e678-36a2-465d-8b2e-bd2cadb781a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385790032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.3385790032
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.106779853
Short name T630
Test name
Test status
Simulation time 32970098 ps
CPU time 0.64 seconds
Started Jul 11 04:56:13 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 198288 kb
Host smart-8699cd1a-e01c-4810-8c3e-ef7c5b834b9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106779853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.106779853
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2649541994
Short name T496
Test name
Test status
Simulation time 43029536 ps
CPU time 0.78 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 201016 kb
Host smart-9c72e76d-0727-4551-aa08-9188a3855f63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649541994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2649541994
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.3735402163
Short name T541
Test name
Test status
Simulation time 253336800 ps
CPU time 0.79 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:21 PM PDT 24
Peak memory 198020 kb
Host smart-b8ed867c-2ee5-4492-aa2b-39105b9072a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735402163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.3735402163
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2448835071
Short name T553
Test name
Test status
Simulation time 60325098 ps
CPU time 0.73 seconds
Started Jul 11 04:56:06 PM PDT 24
Finished Jul 11 04:56:16 PM PDT 24
Peak memory 197876 kb
Host smart-d9f19ff8-156f-4420-96a5-99730946981d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448835071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2448835071
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1697065374
Short name T956
Test name
Test status
Simulation time 104950688 ps
CPU time 0.95 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 209196 kb
Host smart-1a51352b-6da4-40a3-96ef-65c959f5a1ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697065374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1697065374
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2905778014
Short name T59
Test name
Test status
Simulation time 133733399 ps
CPU time 0.81 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 198748 kb
Host smart-ee1948fc-0ed0-4a51-87b4-5f889d7d3894
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905778014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.2905778014
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.87820272
Short name T843
Test name
Test status
Simulation time 795863583 ps
CPU time 3.01 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 200680 kb
Host smart-0825391e-50ae-443b-b917-56352ec597dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87820272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.87820272
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1695963516
Short name T361
Test name
Test status
Simulation time 804901531 ps
CPU time 2.25 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:25 PM PDT 24
Peak memory 200816 kb
Host smart-308d1cd6-49a0-41f3-87c8-1cf3655a9acc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695963516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1695963516
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.4077396626
Short name T230
Test name
Test status
Simulation time 141159877 ps
CPU time 0.84 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 198828 kb
Host smart-b3af6622-bc09-48ce-949b-a8fb86b2ff0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077396626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4077396626
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3298518205
Short name T356
Test name
Test status
Simulation time 90535852 ps
CPU time 0.64 seconds
Started Jul 11 04:56:07 PM PDT 24
Finished Jul 11 04:56:17 PM PDT 24
Peak memory 198120 kb
Host smart-8489cd19-3371-44f6-a227-2ab5d6392b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298518205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3298518205
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.2717531946
Short name T733
Test name
Test status
Simulation time 144400763 ps
CPU time 0.97 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 198480 kb
Host smart-d906e9ec-b539-40a9-a902-39fb3e5d50f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717531946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.2717531946
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.4202845002
Short name T639
Test name
Test status
Simulation time 3818816945 ps
CPU time 5.49 seconds
Started Jul 11 04:56:11 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 200924 kb
Host smart-59979f1b-1c3d-4abc-81ab-e1a3ff1daac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202845002 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.4202845002
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.1253876440
Short name T269
Test name
Test status
Simulation time 664616205 ps
CPU time 0.94 seconds
Started Jul 11 04:56:13 PM PDT 24
Finished Jul 11 04:56:25 PM PDT 24
Peak memory 199496 kb
Host smart-d4069151-e513-441c-8d34-6c8fdf154b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253876440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1253876440
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.644593694
Short name T955
Test name
Test status
Simulation time 378651312 ps
CPU time 1.17 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:29 PM PDT 24
Peak memory 200620 kb
Host smart-a85dc56b-9333-4144-a3c2-92833817b3a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644593694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.644593694
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2344546097
Short name T615
Test name
Test status
Simulation time 37145071 ps
CPU time 0.68 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 198380 kb
Host smart-43517223-ed85-4a26-b688-2972fe14416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344546097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2344546097
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2190461486
Short name T809
Test name
Test status
Simulation time 31372040 ps
CPU time 0.64 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:24 PM PDT 24
Peak memory 197716 kb
Host smart-67c8066c-509d-46a0-9260-5945d9bb810b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190461486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.2190461486
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.4095002267
Short name T169
Test name
Test status
Simulation time 601279952 ps
CPU time 0.92 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 197792 kb
Host smart-684bedc9-324b-459f-81a3-8fc6c7021910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095002267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.4095002267
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1314336926
Short name T316
Test name
Test status
Simulation time 93095085 ps
CPU time 0.61 seconds
Started Jul 11 04:55:23 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 197656 kb
Host smart-d3d448eb-9203-440a-ab3d-dd79e2c3c3a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314336926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1314336926
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2065277002
Short name T166
Test name
Test status
Simulation time 144518681 ps
CPU time 0.6 seconds
Started Jul 11 04:55:22 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 197692 kb
Host smart-1e8eee3a-e809-45d7-91fa-0965b756ac9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065277002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2065277002
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2607937415
Short name T340
Test name
Test status
Simulation time 55678782 ps
CPU time 0.71 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 201120 kb
Host smart-510ca708-3c3f-4c23-a07b-8cd8b30583e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607937415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2607937415
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.3888935394
Short name T568
Test name
Test status
Simulation time 318547928 ps
CPU time 1.37 seconds
Started Jul 11 04:55:18 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 199364 kb
Host smart-825430da-8c7b-4986-b84e-96477a05c22f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888935394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.3888935394
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1181475013
Short name T593
Test name
Test status
Simulation time 43222912 ps
CPU time 0.8 seconds
Started Jul 11 04:55:22 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 198752 kb
Host smart-e1610115-31c4-4349-8448-8c90c5f9ac95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181475013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1181475013
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3417458940
Short name T606
Test name
Test status
Simulation time 103572830 ps
CPU time 0.99 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 209172 kb
Host smart-2677382c-6e9a-444f-a49e-4bb942975fa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417458940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3417458940
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1791955520
Short name T18
Test name
Test status
Simulation time 885909528 ps
CPU time 1.43 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 217460 kb
Host smart-c460c7cd-2a25-434b-a901-e0ce2e03ad6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791955520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1791955520
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.4206191383
Short name T138
Test name
Test status
Simulation time 182637425 ps
CPU time 0.96 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 199736 kb
Host smart-344d1861-fc4b-46ef-aea7-3d0c853579d0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206191383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.4206191383
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4112016675
Short name T628
Test name
Test status
Simulation time 720029356 ps
CPU time 2.84 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 200876 kb
Host smart-5664ca37-b653-4a4b-a9c9-68b61e0728e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112016675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4112016675
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4213900502
Short name T404
Test name
Test status
Simulation time 1259404989 ps
CPU time 2.18 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 200680 kb
Host smart-ea294f30-8405-4ad1-a403-d6476f25e469
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213900502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4213900502
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2765715872
Short name T349
Test name
Test status
Simulation time 163725331 ps
CPU time 0.91 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 198976 kb
Host smart-fd1cf838-df9a-4562-8633-81fddb7ed341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765715872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2765715872
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3269857626
Short name T918
Test name
Test status
Simulation time 30579156 ps
CPU time 0.69 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 199056 kb
Host smart-7f63d510-e8e3-43dd-8094-fecf70f09073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269857626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3269857626
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.3515576965
Short name T590
Test name
Test status
Simulation time 1334681616 ps
CPU time 2.33 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:38 PM PDT 24
Peak memory 200872 kb
Host smart-17475324-32df-4129-8e1c-42b2461e7e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515576965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3515576965
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.1304114400
Short name T945
Test name
Test status
Simulation time 208698116 ps
CPU time 0.77 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 199144 kb
Host smart-8919e62b-d541-400c-a869-a6b88fa76452
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304114400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1304114400
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1197838941
Short name T643
Test name
Test status
Simulation time 125659113 ps
CPU time 1.03 seconds
Started Jul 11 04:55:22 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 199772 kb
Host smart-679e13fc-f1d2-492b-94c9-04f35ece32fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197838941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1197838941
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3258713042
Short name T438
Test name
Test status
Simulation time 33744726 ps
CPU time 0.8 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 198768 kb
Host smart-857cabc8-0bb5-4c66-8b36-e50e7c50e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258713042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3258713042
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1363185035
Short name T932
Test name
Test status
Simulation time 93838316 ps
CPU time 0.67 seconds
Started Jul 11 04:56:35 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 198408 kb
Host smart-42d68b6a-7707-444b-8af8-7234f74fa0c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363185035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1363185035
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1510234989
Short name T995
Test name
Test status
Simulation time 82559436 ps
CPU time 0.59 seconds
Started Jul 11 04:56:16 PM PDT 24
Finished Jul 11 04:56:28 PM PDT 24
Peak memory 196956 kb
Host smart-4923fa32-7571-4348-b2e8-74cab4d280b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510234989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1510234989
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2151520347
Short name T462
Test name
Test status
Simulation time 166552371 ps
CPU time 0.93 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 198008 kb
Host smart-fa8b2f40-e7d7-4e30-8f11-a73abce0ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151520347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2151520347
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2789681046
Short name T978
Test name
Test status
Simulation time 53546499 ps
CPU time 0.66 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:35 PM PDT 24
Peak memory 197764 kb
Host smart-2463ce4d-1f76-4848-9d76-d83b0e852e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789681046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2789681046
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.3958946110
Short name T598
Test name
Test status
Simulation time 24592875 ps
CPU time 0.62 seconds
Started Jul 11 04:56:15 PM PDT 24
Finished Jul 11 04:56:27 PM PDT 24
Peak memory 198032 kb
Host smart-4ba1e24c-df5a-4826-bb20-1f7cf4a11399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958946110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3958946110
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3687070843
Short name T46
Test name
Test status
Simulation time 82796375 ps
CPU time 0.71 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 201032 kb
Host smart-38f5f1dc-075e-44de-971f-133450af4b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687070843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3687070843
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.2335172627
Short name T128
Test name
Test status
Simulation time 90230731 ps
CPU time 0.64 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 198844 kb
Host smart-75d6c447-3cd6-49e6-aedb-095cfcf500c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335172627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.2335172627
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.2923672041
Short name T921
Test name
Test status
Simulation time 57327781 ps
CPU time 0.83 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198800 kb
Host smart-940da5f7-1935-4e10-9ebd-15d33006c7fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923672041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2923672041
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3857893451
Short name T266
Test name
Test status
Simulation time 168949510 ps
CPU time 0.79 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 209116 kb
Host smart-827747e3-1d05-4739-9ab7-fd4760ed1ec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857893451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3857893451
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2180336908
Short name T851
Test name
Test status
Simulation time 69394158 ps
CPU time 0.78 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 199080 kb
Host smart-06414165-d167-412f-9583-366207919f14
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180336908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.2180336908
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1303206554
Short name T713
Test name
Test status
Simulation time 986538278 ps
CPU time 1.98 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 200804 kb
Host smart-3978980e-86a3-4035-afe1-6e5c0647c1ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303206554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1303206554
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.815290637
Short name T795
Test name
Test status
Simulation time 796347218 ps
CPU time 2.75 seconds
Started Jul 11 04:56:15 PM PDT 24
Finished Jul 11 04:56:29 PM PDT 24
Peak memory 200840 kb
Host smart-492b8e38-479c-49e2-908b-71f480c1a8a0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815290637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.815290637
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3398925417
Short name T366
Test name
Test status
Simulation time 70617075 ps
CPU time 0.87 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 198792 kb
Host smart-26d4f8fc-92cb-4674-89e1-0eb7b07a9638
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398925417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3398925417
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.456092149
Short name T369
Test name
Test status
Simulation time 97708325 ps
CPU time 0.68 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198196 kb
Host smart-41924290-ee25-4392-bb90-737ab427cbf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456092149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.456092149
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.2769415516
Short name T408
Test name
Test status
Simulation time 4471792039 ps
CPU time 2.13 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 200860 kb
Host smart-cfc4ab61-6096-4476-8ea2-1a798b71756c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769415516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2769415516
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.4231698113
Short name T813
Test name
Test status
Simulation time 4301672527 ps
CPU time 7.59 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 201048 kb
Host smart-35307db7-e196-4b76-9349-009cd4c264a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231698113 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.4231698113
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.2808460317
Short name T652
Test name
Test status
Simulation time 92083271 ps
CPU time 0.65 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 197912 kb
Host smart-8196691e-b663-4c13-9384-bd9b98d1bae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808460317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2808460317
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.1533897102
Short name T293
Test name
Test status
Simulation time 247048067 ps
CPU time 1.43 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 199860 kb
Host smart-ea47e9c8-17b2-4132-a4c0-bf39d217a4c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533897102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1533897102
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.276339784
Short name T674
Test name
Test status
Simulation time 36413996 ps
CPU time 0.79 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 198680 kb
Host smart-c34a7e94-1e35-4cda-a15a-6e742a333fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276339784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.276339784
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3384295636
Short name T205
Test name
Test status
Simulation time 62022078 ps
CPU time 0.83 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 198772 kb
Host smart-cdccf83b-5e1c-4f19-a74e-da8a10450fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384295636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3384295636
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.1892908083
Short name T677
Test name
Test status
Simulation time 29323067 ps
CPU time 0.63 seconds
Started Jul 11 04:56:12 PM PDT 24
Finished Jul 11 04:56:22 PM PDT 24
Peak memory 196984 kb
Host smart-07c383f6-f41d-4591-9c4b-9b84f67df9e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892908083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.1892908083
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1173135834
Short name T692
Test name
Test status
Simulation time 951325333 ps
CPU time 0.93 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 197680 kb
Host smart-bca20a0c-9dee-4f36-8b4e-ce5ad8666ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173135834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1173135834
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.207851537
Short name T488
Test name
Test status
Simulation time 103523749 ps
CPU time 0.66 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 197684 kb
Host smart-7dd4ca9e-cdf6-4fbe-8d3e-acf1d8e4af90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207851537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.207851537
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1011241352
Short name T304
Test name
Test status
Simulation time 75917543 ps
CPU time 0.61 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 197648 kb
Host smart-e85ca040-e893-49e1-baf2-2550a88e5334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011241352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1011241352
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.380179095
Short name T762
Test name
Test status
Simulation time 51709739 ps
CPU time 0.68 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:33 PM PDT 24
Peak memory 201016 kb
Host smart-b23a5e39-f849-4c0a-b50b-375b27ca7ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380179095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.380179095
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.2992662298
Short name T281
Test name
Test status
Simulation time 161771792 ps
CPU time 0.98 seconds
Started Jul 11 04:56:15 PM PDT 24
Finished Jul 11 04:56:28 PM PDT 24
Peak memory 198208 kb
Host smart-a82a4c80-fe34-4275-a204-8f9f7a765aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992662298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.2992662298
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.4235147383
Short name T489
Test name
Test status
Simulation time 39550694 ps
CPU time 0.8 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:30 PM PDT 24
Peak memory 198856 kb
Host smart-7ca443fc-a5cf-4870-a961-08baaa29fb95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235147383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.4235147383
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3512814539
Short name T591
Test name
Test status
Simulation time 156463699 ps
CPU time 0.8 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 209220 kb
Host smart-a7c659ad-c48b-485c-b063-a41e98e26498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512814539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3512814539
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2552051791
Short name T898
Test name
Test status
Simulation time 234782809 ps
CPU time 1.05 seconds
Started Jul 11 04:56:34 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 199656 kb
Host smart-b72bfca6-15c5-44bc-8412-7dd02ac4ee48
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552051791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.2552051791
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.40343515
Short name T455
Test name
Test status
Simulation time 1247282641 ps
CPU time 1.89 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 200824 kb
Host smart-29f187af-547f-4f53-a6a5-6d1928eda2ea
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.40343515
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1645602851
Short name T616
Test name
Test status
Simulation time 67125773 ps
CPU time 0.94 seconds
Started Jul 11 04:56:16 PM PDT 24
Finished Jul 11 04:56:29 PM PDT 24
Peak memory 199356 kb
Host smart-1d2ffdc2-24cf-47c9-9814-3ec9b43a72d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645602851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1645602851
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1419600881
Short name T254
Test name
Test status
Simulation time 49844714 ps
CPU time 0.65 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 198920 kb
Host smart-fabf1d0b-43ea-4405-9dde-6cd910d3985f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419600881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1419600881
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.2895457792
Short name T538
Test name
Test status
Simulation time 1082160675 ps
CPU time 4.04 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 200760 kb
Host smart-660b13a4-a5ad-4c82-b9ae-acbde9c71ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895457792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.2895457792
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2561131684
Short name T31
Test name
Test status
Simulation time 10701446639 ps
CPU time 13.9 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 200952 kb
Host smart-3879925c-d00f-4463-a32a-d8adf333dbca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561131684 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.2561131684
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.2409661878
Short name T440
Test name
Test status
Simulation time 63156583 ps
CPU time 0.68 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 197856 kb
Host smart-3e3cf11f-e282-45c3-a53b-8459de2edd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409661878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2409661878
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.1613818328
Short name T375
Test name
Test status
Simulation time 118376811 ps
CPU time 0.77 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 198692 kb
Host smart-ddf9b585-5ba1-4fac-b3fd-3bb46cdf63f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613818328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.1613818328
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1043152616
Short name T817
Test name
Test status
Simulation time 51076508 ps
CPU time 0.98 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 199848 kb
Host smart-ae66b99c-227f-4f4e-a19d-9ac53ac5b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043152616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1043152616
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3935739570
Short name T785
Test name
Test status
Simulation time 81131577 ps
CPU time 0.72 seconds
Started Jul 11 04:56:15 PM PDT 24
Finished Jul 11 04:56:28 PM PDT 24
Peak memory 198720 kb
Host smart-24c4f75e-e402-4ca1-99d3-95e463b781eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935739570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.3935739570
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2277524122
Short name T863
Test name
Test status
Simulation time 38532358 ps
CPU time 0.63 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 196912 kb
Host smart-b7bb23c4-b3ec-4210-b6a6-117a16a1e2a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277524122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2277524122
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.984970216
Short name T163
Test name
Test status
Simulation time 164580697 ps
CPU time 0.96 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 198120 kb
Host smart-68fc5e3f-6f80-4fd0-af5b-3c4e727ac969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984970216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.984970216
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2922943896
Short name T312
Test name
Test status
Simulation time 40987061 ps
CPU time 0.66 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:30 PM PDT 24
Peak memory 197752 kb
Host smart-3708dca9-cece-4970-9df5-4cf2b7989a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922943896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2922943896
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3341059059
Short name T814
Test name
Test status
Simulation time 53572585 ps
CPU time 0.65 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 197776 kb
Host smart-70b3bb36-22c1-47bc-9f24-ebb40b89b06f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341059059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3341059059
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2009450526
Short name T518
Test name
Test status
Simulation time 46464505 ps
CPU time 0.71 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 200980 kb
Host smart-b2edbc8c-a8f4-4803-ae5b-df545f08a816
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009450526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2009450526
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.3159665979
Short name T972
Test name
Test status
Simulation time 55278512 ps
CPU time 0.74 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 197932 kb
Host smart-71fb5abf-66f3-4d6e-ab57-b25a5f8d2583
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159665979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.3159665979
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3509360642
Short name T251
Test name
Test status
Simulation time 112225574 ps
CPU time 0.82 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 198720 kb
Host smart-5e412901-6f91-474c-9c29-588783ee3879
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509360642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3509360642
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.128407603
Short name T834
Test name
Test status
Simulation time 161027052 ps
CPU time 0.76 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:30 PM PDT 24
Peak memory 209124 kb
Host smart-dbaca778-51b7-40ed-b3e6-85003a1e1fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128407603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.128407603
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.4123042332
Short name T161
Test name
Test status
Simulation time 377282099 ps
CPU time 0.96 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 199680 kb
Host smart-849ab3a0-bd19-4aac-acd5-bb7b56237c69
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123042332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.4123042332
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1755843456
Short name T200
Test name
Test status
Simulation time 821737262 ps
CPU time 2.75 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 200804 kb
Host smart-a957e8d0-aede-4153-a8fb-11a79a0fe73e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755843456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1755843456
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2219228656
Short name T158
Test name
Test status
Simulation time 1313786761 ps
CPU time 2.26 seconds
Started Jul 11 04:56:16 PM PDT 24
Finished Jul 11 04:56:30 PM PDT 24
Peak memory 200740 kb
Host smart-98495dc5-cb49-489a-bc48-b3032c3c0edd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219228656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2219228656
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3343506859
Short name T860
Test name
Test status
Simulation time 549340018 ps
CPU time 0.85 seconds
Started Jul 11 04:56:18 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 198920 kb
Host smart-a069a768-e480-4fea-a3fb-45ef804e7412
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343506859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3343506859
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1308038620
Short name T400
Test name
Test status
Simulation time 31027903 ps
CPU time 0.65 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 198288 kb
Host smart-75a27633-5e42-424d-8275-b49846d9b335
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308038620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1308038620
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.1211608762
Short name T299
Test name
Test status
Simulation time 1337431650 ps
CPU time 5.35 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 200796 kb
Host smart-6ea07afe-dc68-432a-b220-31594efa8969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211608762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.1211608762
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.1576549809
Short name T645
Test name
Test status
Simulation time 8434445781 ps
CPU time 28.67 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 200972 kb
Host smart-a8079e8c-b223-4496-b837-1166a45a183c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576549809 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.1576549809
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.2548119
Short name T430
Test name
Test status
Simulation time 251007930 ps
CPU time 1.25 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:33 PM PDT 24
Peak memory 199348 kb
Host smart-8985be00-3be7-4137-b065-99b02f8eb6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.2548119
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.1489769630
Short name T716
Test name
Test status
Simulation time 416033691 ps
CPU time 1.12 seconds
Started Jul 11 04:56:14 PM PDT 24
Finished Jul 11 04:56:27 PM PDT 24
Peak memory 200512 kb
Host smart-aaf61e48-c325-49b2-86e6-0b42eea60409
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489769630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1489769630
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.170960894
Short name T100
Test name
Test status
Simulation time 36897073 ps
CPU time 0.77 seconds
Started Jul 11 04:56:13 PM PDT 24
Finished Jul 11 04:56:25 PM PDT 24
Peak memory 198548 kb
Host smart-ef966bd5-c0b0-49cf-b300-a2b231798f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170960894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.170960894
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1338513496
Short name T174
Test name
Test status
Simulation time 47398532 ps
CPU time 0.57 seconds
Started Jul 11 04:56:19 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 197740 kb
Host smart-8deee40b-826e-40b5-aaa9-733922f54054
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338513496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1338513496
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1121889737
Short name T665
Test name
Test status
Simulation time 160232791 ps
CPU time 1.01 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 198112 kb
Host smart-8923f9aa-fe88-45a3-9539-6e0b136596a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121889737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1121889737
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.679778119
Short name T177
Test name
Test status
Simulation time 36633825 ps
CPU time 0.63 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 197108 kb
Host smart-a8a4d9ec-2fec-474b-a3df-4b30934836de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679778119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.679778119
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3931957887
Short name T164
Test name
Test status
Simulation time 71315007 ps
CPU time 0.62 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198080 kb
Host smart-d211d197-e605-42af-939e-b761c0f5b043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931957887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3931957887
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.3649988709
Short name T778
Test name
Test status
Simulation time 39447759 ps
CPU time 0.72 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 201072 kb
Host smart-ff114d9c-4811-45ba-b949-096a93ec66c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649988709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.3649988709
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.1074062896
Short name T594
Test name
Test status
Simulation time 203347591 ps
CPU time 0.73 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:33 PM PDT 24
Peak memory 198724 kb
Host smart-4857b6f5-d478-4c1e-b037-bc50fc8dd5ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074062896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.1074062896
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.3217290546
Short name T676
Test name
Test status
Simulation time 128663544 ps
CPU time 0.76 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 198796 kb
Host smart-41417305-b882-4f70-8717-00d36d002ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217290546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3217290546
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.856838422
Short name T782
Test name
Test status
Simulation time 116193612 ps
CPU time 0.92 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 209196 kb
Host smart-8e9da14f-37f5-4d80-abdd-6f2f3057cc8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856838422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.856838422
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2700799467
Short name T399
Test name
Test status
Simulation time 226673139 ps
CPU time 0.97 seconds
Started Jul 11 04:56:26 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 199424 kb
Host smart-fe816918-ebaa-4953-9f1f-42310736ed6e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700799467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.2700799467
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3383473319
Short name T792
Test name
Test status
Simulation time 848139962 ps
CPU time 3.28 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 200760 kb
Host smart-53788c9c-bb5c-4659-9aca-a6fae6084685
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383473319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3383473319
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1947877666
Short name T487
Test name
Test status
Simulation time 1320113129 ps
CPU time 2.48 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 200852 kb
Host smart-e4fa3915-f31e-4e30-9089-616ffb36f870
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947877666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1947877666
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2277459070
Short name T458
Test name
Test status
Simulation time 90458393 ps
CPU time 0.87 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198896 kb
Host smart-ad3b46fe-d0b8-46b3-a96e-3d9039323fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277459070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2277459070
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.2413335421
Short name T854
Test name
Test status
Simulation time 29270069 ps
CPU time 0.68 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:35 PM PDT 24
Peak memory 199052 kb
Host smart-c9c8c76c-0eec-400f-93e5-8273d68b5a96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413335421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2413335421
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.1139653290
Short name T815
Test name
Test status
Simulation time 1617439693 ps
CPU time 6.08 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 200888 kb
Host smart-bbd01924-86ac-4d18-9fdd-099675e2f273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139653290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.1139653290
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.4251233758
Short name T85
Test name
Test status
Simulation time 6926028034 ps
CPU time 25.09 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 200992 kb
Host smart-9670523f-294f-4de7-946b-9c80b23e99df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251233758 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.4251233758
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.2669451308
Short name T603
Test name
Test status
Simulation time 140555946 ps
CPU time 0.76 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198876 kb
Host smart-e63d4727-6bc8-4bbe-b41c-25e67d5f75ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669451308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.2669451308
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.1761712193
Short name T828
Test name
Test status
Simulation time 79753682 ps
CPU time 0.82 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:30 PM PDT 24
Peak memory 198992 kb
Host smart-f45dfe16-0f9d-4c01-a6ad-a13c23fc7e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761712193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1761712193
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2742733710
Short name T741
Test name
Test status
Simulation time 31195233 ps
CPU time 0.7 seconds
Started Jul 11 04:56:24 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 198820 kb
Host smart-90ca74cd-f93e-4b94-80f0-a3d610f1b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742733710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2742733710
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2608009245
Short name T432
Test name
Test status
Simulation time 71233198 ps
CPU time 0.79 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:32 PM PDT 24
Peak memory 198844 kb
Host smart-6d927b88-3b3d-499a-a5ac-364684194f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608009245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2608009245
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2589743408
Short name T357
Test name
Test status
Simulation time 39242896 ps
CPU time 0.59 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 197740 kb
Host smart-201e6741-fd2f-4bcd-920c-be82304e9359
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589743408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.2589743408
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.907539550
Short name T558
Test name
Test status
Simulation time 999672667 ps
CPU time 1.01 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 197812 kb
Host smart-311e22f7-d212-4363-b33e-5965928a5654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907539550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.907539550
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.353818372
Short name T574
Test name
Test status
Simulation time 46666720 ps
CPU time 0.58 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 197756 kb
Host smart-a9263e84-f634-475d-b1a0-74d931c23c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353818372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.353818372
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2166462398
Short name T874
Test name
Test status
Simulation time 67192427 ps
CPU time 0.66 seconds
Started Jul 11 04:56:26 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 197680 kb
Host smart-fa5fe141-6fa5-4753-a130-2f5b7e084baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166462398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2166462398
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3042957643
Short name T770
Test name
Test status
Simulation time 112056409 ps
CPU time 0.67 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 201080 kb
Host smart-3c030c17-1a19-4969-a6bb-b5f046062fa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042957643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3042957643
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.2386578209
Short name T513
Test name
Test status
Simulation time 281684117 ps
CPU time 0.92 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 199468 kb
Host smart-08db6dab-946c-4dd8-96bb-4eede14da902
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386578209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.2386578209
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2849768725
Short name T783
Test name
Test status
Simulation time 43257777 ps
CPU time 0.6 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 197952 kb
Host smart-3a972b28-908f-455f-ab41-2c77af64a20f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849768725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2849768725
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.247461894
Short name T383
Test name
Test status
Simulation time 278190349 ps
CPU time 0.77 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 209180 kb
Host smart-24bd21bc-78ba-4ade-8d69-7f15dba65d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247461894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.247461894
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1537471567
Short name T721
Test name
Test status
Simulation time 89049323 ps
CPU time 0.77 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 198340 kb
Host smart-7617c4a3-0ad7-4fdd-9893-e881e72bcf11
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537471567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1537471567
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.916866426
Short name T752
Test name
Test status
Simulation time 1261577457 ps
CPU time 2.41 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 201004 kb
Host smart-d3db1348-70e5-47b9-93fe-579a7357469b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916866426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.916866426
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3545544097
Short name T968
Test name
Test status
Simulation time 784810898 ps
CPU time 3.05 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:35 PM PDT 24
Peak memory 200816 kb
Host smart-1b9d2cf5-748b-4090-af39-b1fb864352a1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545544097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3545544097
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.834576036
Short name T346
Test name
Test status
Simulation time 65829997 ps
CPU time 0.93 seconds
Started Jul 11 04:56:21 PM PDT 24
Finished Jul 11 04:56:33 PM PDT 24
Peak memory 199000 kb
Host smart-d115d87d-6429-4504-adb8-25571fbedd66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834576036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_
mubi.834576036
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.134824892
Short name T853
Test name
Test status
Simulation time 44624599 ps
CPU time 0.63 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 198268 kb
Host smart-10da1c99-f191-4c85-9e8a-8f8a0d76c1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134824892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.134824892
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.682464206
Short name T35
Test name
Test status
Simulation time 1612258205 ps
CPU time 2.18 seconds
Started Jul 11 04:56:20 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 200924 kb
Host smart-fbf3e531-7b0e-4630-ad30-1577fc7adf90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682464206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.682464206
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.122554271
Short name T53
Test name
Test status
Simulation time 8540387053 ps
CPU time 21.09 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:58 PM PDT 24
Peak memory 201020 kb
Host smart-f7f2c22f-bae4-438d-8e02-832e4995c140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122554271 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.122554271
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.2947734329
Short name T277
Test name
Test status
Simulation time 170159935 ps
CPU time 1 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:40 PM PDT 24
Peak memory 199200 kb
Host smart-fff77f99-7a2f-47f8-8a01-8b755347381b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947734329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.2947734329
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.2566714668
Short name T353
Test name
Test status
Simulation time 111655516 ps
CPU time 0.7 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 198992 kb
Host smart-aa5c780a-520d-4fde-8db6-a591542ba245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566714668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2566714668
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3536168644
Short name T99
Test name
Test status
Simulation time 60534149 ps
CPU time 0.8 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 199640 kb
Host smart-9ca5e599-636d-46e2-9159-db0d0913dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536168644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3536168644
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2311084752
Short name T481
Test name
Test status
Simulation time 76273919 ps
CPU time 0.69 seconds
Started Jul 11 04:56:33 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 198868 kb
Host smart-6da169f4-64f2-4b92-8df7-bed4757c503c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311084752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2311084752
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1213857138
Short name T812
Test name
Test status
Simulation time 29815086 ps
CPU time 0.61 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 197020 kb
Host smart-1f32fbe4-de05-4cb6-8c68-ea5b1dbd9a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213857138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1213857138
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2474526427
Short name T172
Test name
Test status
Simulation time 162929757 ps
CPU time 0.96 seconds
Started Jul 11 04:56:47 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 198104 kb
Host smart-3b61275b-ebfe-4c91-ba02-5f16bf729fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474526427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2474526427
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3847146545
Short name T296
Test name
Test status
Simulation time 35261876 ps
CPU time 0.65 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 197100 kb
Host smart-4aff8103-2bbc-4e81-9c7d-09e5accd7cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847146545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3847146545
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2057544402
Short name T731
Test name
Test status
Simulation time 47579829 ps
CPU time 0.66 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 197788 kb
Host smart-3b493119-4bb8-4a47-945e-06ed51b27faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057544402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2057544402
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3450222115
Short name T505
Test name
Test status
Simulation time 51559748 ps
CPU time 0.7 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 201120 kb
Host smart-047ea6db-10e7-45d2-a340-bedbbdc9ddbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450222115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3450222115
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.1256640375
Short name T738
Test name
Test status
Simulation time 331851532 ps
CPU time 0.9 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:34 PM PDT 24
Peak memory 199472 kb
Host smart-ae9d0d1b-bcce-48dd-a293-8d83785059e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256640375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.1256640375
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2115710992
Short name T610
Test name
Test status
Simulation time 34742536 ps
CPU time 0.64 seconds
Started Jul 11 04:56:26 PM PDT 24
Finished Jul 11 04:56:38 PM PDT 24
Peak memory 197884 kb
Host smart-53ca7fdc-96f9-4aa5-9919-b9ae94639acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115710992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2115710992
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.2234245085
Short name T739
Test name
Test status
Simulation time 179142131 ps
CPU time 0.82 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:40 PM PDT 24
Peak memory 209272 kb
Host smart-b223b292-cc20-468e-bb58-23e3f732dceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234245085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2234245085
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2031794818
Short name T61
Test name
Test status
Simulation time 189516174 ps
CPU time 1.13 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 199576 kb
Host smart-05cc7e6c-0c81-4290-aaa8-a220a2d8bb00
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031794818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.2031794818
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.562006937
Short name T480
Test name
Test status
Simulation time 968002916 ps
CPU time 2.62 seconds
Started Jul 11 04:56:22 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 200700 kb
Host smart-ce9a7a40-fc2a-4bda-b4ae-10c7044f404a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562006937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.562006937
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.860997533
Short name T605
Test name
Test status
Simulation time 1046626589 ps
CPU time 2.4 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 200764 kb
Host smart-8d00984d-6d52-40b9-95ca-ec5ee98d80fe
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860997533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.860997533
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1426529890
Short name T724
Test name
Test status
Simulation time 113019148 ps
CPU time 0.87 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:40 PM PDT 24
Peak memory 198920 kb
Host smart-dff58e14-fabf-40c9-aaf7-e941fd198f9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426529890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1426529890
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2857450701
Short name T523
Test name
Test status
Simulation time 32505137 ps
CPU time 0.69 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:49 PM PDT 24
Peak memory 198984 kb
Host smart-53000c18-47ab-471a-9fc0-d7777379ff4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857450701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2857450701
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.2184480801
Short name T825
Test name
Test status
Simulation time 6559498082 ps
CPU time 3.55 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 200860 kb
Host smart-83b7188d-2f68-4518-9493-626f7656f743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184480801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2184480801
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2116344093
Short name T347
Test name
Test status
Simulation time 12224671527 ps
CPU time 17.06 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 200992 kb
Host smart-8a60af7c-9248-46a7-b591-bc0f1265ee02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116344093 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.2116344093
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.242341581
Short name T4
Test name
Test status
Simulation time 253403470 ps
CPU time 0.75 seconds
Started Jul 11 04:56:33 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 197996 kb
Host smart-a5b8fc34-bb9b-4d5a-a04b-674c0307c63d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242341581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.242341581
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.1491688462
Short name T668
Test name
Test status
Simulation time 292793668 ps
CPU time 0.96 seconds
Started Jul 11 04:56:23 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 199856 kb
Host smart-fed91010-ac2e-4967-a33c-d6423b9f5989
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491688462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1491688462
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3000599657
Short name T720
Test name
Test status
Simulation time 53242717 ps
CPU time 0.74 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 198820 kb
Host smart-43f2be80-a65d-49b6-b1cb-63531e884ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000599657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3000599657
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1297801509
Short name T629
Test name
Test status
Simulation time 46788338 ps
CPU time 0.75 seconds
Started Jul 11 04:56:42 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 198788 kb
Host smart-43d4dd16-83ec-4deb-8b38-a7f1f5750d84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297801509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.1297801509
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2065359573
Short name T160
Test name
Test status
Simulation time 29765754 ps
CPU time 0.65 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 197636 kb
Host smart-d280627c-32ec-46e2-a712-b8be8e66185b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065359573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.2065359573
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3671588429
Short name T601
Test name
Test status
Simulation time 162179664 ps
CPU time 1.01 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 197808 kb
Host smart-deac6d7f-5976-4de1-a9e6-971f3a1bcbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671588429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3671588429
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2681550568
Short name T339
Test name
Test status
Simulation time 47023218 ps
CPU time 0.62 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 197784 kb
Host smart-02d21ab9-a42d-46fd-9340-846a2c790383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681550568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2681550568
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1898122364
Short name T595
Test name
Test status
Simulation time 51775486 ps
CPU time 0.59 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 197668 kb
Host smart-77a311d0-2a98-47e1-b1b8-6b6c12429e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898122364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1898122364
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3659073866
Short name T569
Test name
Test status
Simulation time 41505112 ps
CPU time 0.73 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 201276 kb
Host smart-88c8f272-e282-4cbe-99d4-781f68d7b4bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659073866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3659073866
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.1909811767
Short name T81
Test name
Test status
Simulation time 298742388 ps
CPU time 0.93 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 199212 kb
Host smart-7c1ff102-fd64-4521-a517-addcc0c793eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909811767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.1909811767
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.2722971705
Short name T503
Test name
Test status
Simulation time 77247284 ps
CPU time 1 seconds
Started Jul 11 04:56:32 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 199760 kb
Host smart-a5cf9bd2-306a-448e-b6d1-c233029e981c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722971705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2722971705
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3980795197
Short name T431
Test name
Test status
Simulation time 106194863 ps
CPU time 0.94 seconds
Started Jul 11 04:56:44 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 209228 kb
Host smart-f01d46a9-3719-4354-9ec7-c355fcae10db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980795197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3980795197
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.221996748
Short name T745
Test name
Test status
Simulation time 233331721 ps
CPU time 0.86 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 199468 kb
Host smart-3bf6de79-062b-4827-a759-d9411911bf8b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221996748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_c
m_ctrl_config_regwen.221996748
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.601799843
Short name T947
Test name
Test status
Simulation time 808042887 ps
CPU time 3.17 seconds
Started Jul 11 04:56:28 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 200656 kb
Host smart-ae01496b-d794-4945-a5a1-03313eb654e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601799843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.601799843
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3470045806
Short name T570
Test name
Test status
Simulation time 888418859 ps
CPU time 3.13 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 200552 kb
Host smart-cc2d6baf-806d-4039-8dfb-22c93d3b3ec7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470045806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3470045806
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1374518094
Short name T224
Test name
Test status
Simulation time 88523638 ps
CPU time 0.9 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198956 kb
Host smart-6ff0cc89-349b-4196-a53b-f9ccc77a13c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374518094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1374518094
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1259267199
Short name T512
Test name
Test status
Simulation time 60947993 ps
CPU time 0.67 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 199076 kb
Host smart-602be046-c6e2-486a-97a8-88466e72e54c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259267199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1259267199
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.3612954738
Short name T522
Test name
Test status
Simulation time 1219753280 ps
CPU time 2.69 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 200644 kb
Host smart-e5ac30cc-d57d-4b03-87cf-482db0c8add6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612954738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.3612954738
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.414106844
Short name T20
Test name
Test status
Simulation time 6553738860 ps
CPU time 9.69 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 201012 kb
Host smart-080929f0-4b2c-409b-9df8-1219a238b558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414106844 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.414106844
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.2073959377
Short name T282
Test name
Test status
Simulation time 211345964 ps
CPU time 1.09 seconds
Started Jul 11 04:56:34 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 199248 kb
Host smart-2be7440a-b5d8-40d1-b76e-82289f937af0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073959377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2073959377
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.1097949460
Short name T608
Test name
Test status
Simulation time 155664107 ps
CPU time 0.78 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198916 kb
Host smart-72ee497f-aa56-497f-a1d4-93dab3ad8905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097949460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1097949460
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.1965438723
Short name T927
Test name
Test status
Simulation time 71188018 ps
CPU time 0.73 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 198520 kb
Host smart-42bd2ec3-a2cd-4e3c-a489-0bdac472d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965438723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1965438723
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1235865930
Short name T499
Test name
Test status
Simulation time 89962632 ps
CPU time 0.75 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 198804 kb
Host smart-533b2d31-994a-41f7-80c3-a4f2ade7fde8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235865930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1235865930
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.147496921
Short name T666
Test name
Test status
Simulation time 32773662 ps
CPU time 0.62 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 197612 kb
Host smart-438bfe84-e4e2-4c64-a6e2-96298f7f68b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147496921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_
malfunc.147496921
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2455453516
Short name T148
Test name
Test status
Simulation time 628314043 ps
CPU time 0.95 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 197732 kb
Host smart-6b14c1ce-6305-4c8c-8dc7-5071bdb94d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455453516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2455453516
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.481310972
Short name T464
Test name
Test status
Simulation time 56205620 ps
CPU time 0.68 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 197740 kb
Host smart-61a22fb8-15af-4486-b5b7-d20288a2061a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481310972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.481310972
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.4082728665
Short name T441
Test name
Test status
Simulation time 72459315 ps
CPU time 0.6 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 197772 kb
Host smart-8fdbcf65-4288-4e57-9473-08d0b7249734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082728665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.4082728665
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.818276054
Short name T990
Test name
Test status
Simulation time 103929784 ps
CPU time 0.65 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 198016 kb
Host smart-b499a96d-8c5d-4710-8a70-7b2b867c5d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818276054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wa
keup_race.818276054
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.4260478796
Short name T315
Test name
Test status
Simulation time 52998209 ps
CPU time 0.84 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198856 kb
Host smart-0d5925a0-9a58-4ae8-be63-8bf099db9c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260478796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.4260478796
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.139396640
Short name T984
Test name
Test status
Simulation time 116368960 ps
CPU time 0.99 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 209460 kb
Host smart-0fc6c9f8-581d-48f0-a5b5-8580e01d6783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139396640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.139396640
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1342512984
Short name T34
Test name
Test status
Simulation time 288895297 ps
CPU time 1.12 seconds
Started Jul 11 04:56:32 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 199888 kb
Host smart-fe2a4580-ed47-4b81-9f1e-0c6459c4fb4a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342512984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.1342512984
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1584459341
Short name T557
Test name
Test status
Simulation time 1505888186 ps
CPU time 1.92 seconds
Started Jul 11 04:56:27 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 200896 kb
Host smart-0b89f48e-02c5-4b5f-8d13-569f90203c87
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584459341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1584459341
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2459178647
Short name T463
Test name
Test status
Simulation time 849302308 ps
CPU time 2.73 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 200876 kb
Host smart-edf77f86-36ce-43b6-bf28-4435d011027a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459178647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2459178647
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3041820491
Short name T777
Test name
Test status
Simulation time 86627339 ps
CPU time 0.89 seconds
Started Jul 11 04:56:41 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 198856 kb
Host smart-dc58585b-5935-440f-8a60-5ef028bc6c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041820491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3041820491
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2073693578
Short name T143
Test name
Test status
Simulation time 88922587 ps
CPU time 0.67 seconds
Started Jul 11 04:56:25 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 198100 kb
Host smart-c4215cd4-6953-4e1b-a410-08fe4215eca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073693578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2073693578
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.1421254277
Short name T852
Test name
Test status
Simulation time 653465482 ps
CPU time 1.84 seconds
Started Jul 11 04:56:42 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 200876 kb
Host smart-1d33d573-ee14-45ed-abc9-c1067c719197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421254277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.1421254277
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.2999225596
Short name T355
Test name
Test status
Simulation time 4627611414 ps
CPU time 13.85 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 201016 kb
Host smart-57cec560-e60e-40aa-8936-a0649bef081c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999225596 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.2999225596
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.3901849468
Short name T255
Test name
Test status
Simulation time 164159825 ps
CPU time 0.7 seconds
Started Jul 11 04:56:47 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 198092 kb
Host smart-82aa429c-5a3b-44bc-b81d-c1bb83d8da6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901849468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.3901849468
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.929697827
Short name T885
Test name
Test status
Simulation time 336916628 ps
CPU time 1.04 seconds
Started Jul 11 04:56:29 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 200712 kb
Host smart-a508b371-f70e-47fe-a6c7-88a10eefea61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929697827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.929697827
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.812693869
Short name T525
Test name
Test status
Simulation time 23382669 ps
CPU time 0.6 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198340 kb
Host smart-70578db3-b70e-468f-81fa-8ea89bf575cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812693869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.812693869
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2575317798
Short name T858
Test name
Test status
Simulation time 72077520 ps
CPU time 0.69 seconds
Started Jul 11 04:56:44 PM PDT 24
Finished Jul 11 04:56:53 PM PDT 24
Peak memory 198372 kb
Host smart-8ebfa76c-af59-4f79-92bf-43d9641811c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575317798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2575317798
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2723569431
Short name T421
Test name
Test status
Simulation time 37520713 ps
CPU time 0.61 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 197744 kb
Host smart-2e6d2131-35d7-46c8-b463-852ad66211ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723569431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.2723569431
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.946557505
Short name T32
Test name
Test status
Simulation time 1522210667 ps
CPU time 0.98 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 197788 kb
Host smart-d8a7172d-afe8-4234-b5ea-ca714463aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946557505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.946557505
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.1000156514
Short name T703
Test name
Test status
Simulation time 185143163 ps
CPU time 0.62 seconds
Started Jul 11 04:56:36 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 197104 kb
Host smart-2232c881-7298-427e-94b9-6106372bb5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000156514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1000156514
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.1098069752
Short name T876
Test name
Test status
Simulation time 92095067 ps
CPU time 0.57 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:01 PM PDT 24
Peak memory 198024 kb
Host smart-b23a0100-b3b1-4d03-a57a-eac9a246053f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098069752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1098069752
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2898361725
Short name T47
Test name
Test status
Simulation time 52493358 ps
CPU time 0.67 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 200940 kb
Host smart-00e5a104-3f3b-410a-95d8-5312639dc44e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898361725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2898361725
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.3861372341
Short name T717
Test name
Test status
Simulation time 130736198 ps
CPU time 0.69 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 198004 kb
Host smart-9c38dd54-c87b-4f4d-821d-e278be6ffe9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861372341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.3861372341
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1322197908
Short name T276
Test name
Test status
Simulation time 65335147 ps
CPU time 0.83 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 198164 kb
Host smart-097ea058-8b2c-418c-844b-af2236b88190
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322197908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1322197908
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.192966431
Short name T93
Test name
Test status
Simulation time 105745468 ps
CPU time 0.91 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 209212 kb
Host smart-6b210159-b9f4-46c5-b6c3-b0ffa17c23ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192966431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.192966431
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1230264228
Short name T562
Test name
Test status
Simulation time 43075341 ps
CPU time 0.7 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 199376 kb
Host smart-0afc28f2-8a25-4150-a663-9898563895fe
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230264228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1230264228
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2611732707
Short name T902
Test name
Test status
Simulation time 1627415525 ps
CPU time 2.07 seconds
Started Jul 11 04:56:33 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 200736 kb
Host smart-34ca93b7-978d-4d37-8904-30b6d9e8befb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611732707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2611732707
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3289512885
Short name T37
Test name
Test status
Simulation time 837941499 ps
CPU time 3.23 seconds
Started Jul 11 04:56:35 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 200808 kb
Host smart-929de7f3-05c7-4acf-8d85-cedf5c25ad6c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289512885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3289512885
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2677702045
Short name T215
Test name
Test status
Simulation time 82412526 ps
CPU time 0.82 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 199072 kb
Host smart-67bf8454-0edb-465b-b1d9-cb8ad2d1befd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677702045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2677702045
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.1553903461
Short name T249
Test name
Test status
Simulation time 107120555 ps
CPU time 0.65 seconds
Started Jul 11 04:56:30 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 198220 kb
Host smart-78ceda29-2fa6-4216-97ef-85c3fa816d11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553903461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.1553903461
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.3100750524
Short name T564
Test name
Test status
Simulation time 1137103552 ps
CPU time 4.32 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:57:01 PM PDT 24
Peak memory 200848 kb
Host smart-52ca519c-004a-4a51-a668-d50758402f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100750524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.3100750524
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.2105798221
Short name T943
Test name
Test status
Simulation time 233095649 ps
CPU time 1.25 seconds
Started Jul 11 04:56:34 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 199332 kb
Host smart-c775480b-786b-45fb-b79a-f76ea387bb1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105798221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2105798221
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.2171730871
Short name T91
Test name
Test status
Simulation time 150950519 ps
CPU time 0.77 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 198924 kb
Host smart-2ff1f058-ead8-4f35-9c28-33f9ede009ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171730871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.2171730871
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.1776715761
Short name T994
Test name
Test status
Simulation time 34240797 ps
CPU time 0.78 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 198580 kb
Host smart-a03307c9-3e5a-490e-8512-f04ea47df5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776715761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1776715761
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.469546047
Short name T485
Test name
Test status
Simulation time 62690907 ps
CPU time 0.86 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 198804 kb
Host smart-aca26578-ad6a-4d61-8ca0-22eba69e0737
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469546047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disa
ble_rom_integrity_check.469546047
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2109827020
Short name T376
Test name
Test status
Simulation time 31085568 ps
CPU time 0.64 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 196864 kb
Host smart-ed417456-3353-4bd8-bb69-cacf2388d4ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109827020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2109827020
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1763823860
Short name T427
Test name
Test status
Simulation time 163666510 ps
CPU time 0.95 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 198036 kb
Host smart-4ea00cae-e009-4075-9ed3-ecb67d0f93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763823860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1763823860
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1428266210
Short name T30
Test name
Test status
Simulation time 57487634 ps
CPU time 0.6 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:56:42 PM PDT 24
Peak memory 197632 kb
Host smart-aa8728ca-c05a-441d-bf8e-653d81022be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428266210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1428266210
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3615957626
Short name T159
Test name
Test status
Simulation time 62751109 ps
CPU time 0.59 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:01 PM PDT 24
Peak memory 197688 kb
Host smart-ed42cc43-1a8e-49c5-943c-4c73ad84c272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615957626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3615957626
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1069798956
Short name T957
Test name
Test status
Simulation time 52272608 ps
CPU time 0.66 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 201012 kb
Host smart-248bb51c-ce74-42c9-9fce-8431103f5311
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069798956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1069798956
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.2182468934
Short name T82
Test name
Test status
Simulation time 86501613 ps
CPU time 0.75 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 197908 kb
Host smart-6fc9b72d-d5ef-47b1-94da-746c134af1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182468934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.2182468934
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.372448723
Short name T996
Test name
Test status
Simulation time 65999211 ps
CPU time 0.91 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 199556 kb
Host smart-389bdc16-f033-44a2-8d18-01fff194f929
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372448723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.372448723
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2610142154
Short name T627
Test name
Test status
Simulation time 94567930 ps
CPU time 1 seconds
Started Jul 11 04:56:44 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 209252 kb
Host smart-271e4deb-9b8b-44df-b94a-bb50c56faa58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610142154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2610142154
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.800530639
Short name T471
Test name
Test status
Simulation time 58569396 ps
CPU time 0.67 seconds
Started Jul 11 04:56:34 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 198204 kb
Host smart-5cf4be02-0aaa-4321-86e6-31900930345c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800530639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_c
m_ctrl_config_regwen.800530639
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3674289550
Short name T165
Test name
Test status
Simulation time 881296054 ps
CPU time 3.1 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 201012 kb
Host smart-4767c642-ff1b-4e88-a38b-c9c7fce26203
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674289550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3674289550
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2823373666
Short name T300
Test name
Test status
Simulation time 1243049429 ps
CPU time 2.18 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 200752 kb
Host smart-233a1ee7-a8c5-4a2e-b013-8a023ed235f5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823373666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2823373666
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3780842883
Short name T345
Test name
Test status
Simulation time 150127485 ps
CPU time 0.85 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 199028 kb
Host smart-ea5c780f-1c59-4304-88bb-ea176b2f5b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780842883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3780842883
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2985087297
Short name T572
Test name
Test status
Simulation time 32979811 ps
CPU time 0.74 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 199080 kb
Host smart-440cdc07-4ce1-41c2-bc40-6bede10157fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985087297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2985087297
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.279654176
Short name T566
Test name
Test status
Simulation time 145253359 ps
CPU time 1.39 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 200592 kb
Host smart-7afcb697-8863-42f5-bd6d-d08fa19524da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279654176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.279654176
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.2030369422
Short name T51
Test name
Test status
Simulation time 9136590163 ps
CPU time 34.96 seconds
Started Jul 11 04:56:31 PM PDT 24
Finished Jul 11 04:57:17 PM PDT 24
Peak memory 200948 kb
Host smart-1bd97cd3-9e82-4490-9031-8a52e321a2f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030369422 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.2030369422
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.3779446434
Short name T468
Test name
Test status
Simulation time 211299841 ps
CPU time 0.83 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 197924 kb
Host smart-317a0100-8a64-4d61-a765-69031ec6dfd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779446434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.3779446434
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.1970728011
Short name T935
Test name
Test status
Simulation time 59674804 ps
CPU time 0.73 seconds
Started Jul 11 04:56:35 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 198904 kb
Host smart-0a00a0a0-f8db-44c5-ad57-6032911172a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970728011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1970728011
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1502038152
Short name T308
Test name
Test status
Simulation time 51278372 ps
CPU time 0.9 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 199716 kb
Host smart-48b8ae03-7d96-4c1b-ad58-1d6142d49a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502038152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1502038152
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.869534040
Short name T583
Test name
Test status
Simulation time 71068185 ps
CPU time 0.76 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 198712 kb
Host smart-1049c7b7-f801-4b27-b436-a80f6e4c5c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869534040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.869534040
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2430634670
Short name T790
Test name
Test status
Simulation time 32162190 ps
CPU time 0.6 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:35 PM PDT 24
Peak memory 197624 kb
Host smart-154f488a-49d3-47a4-a0c2-e4f1efe8ac07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430634670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2430634670
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2782867801
Short name T506
Test name
Test status
Simulation time 562727576 ps
CPU time 0.94 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 197784 kb
Host smart-6e88cfbf-58d2-4abe-9ee4-e6c38f1395d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782867801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2782867801
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.3732219876
Short name T952
Test name
Test status
Simulation time 49436361 ps
CPU time 0.69 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 197708 kb
Host smart-660a7429-1960-4e5b-911d-72a97134711e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732219876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3732219876
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3598304033
Short name T581
Test name
Test status
Simulation time 28841642 ps
CPU time 0.62 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:39 PM PDT 24
Peak memory 198092 kb
Host smart-1160228c-753b-4372-b396-8b928a1dd804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598304033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3598304033
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.2192340090
Short name T865
Test name
Test status
Simulation time 39965483 ps
CPU time 0.7 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 201032 kb
Host smart-ca24de53-a6d9-4904-bb07-aa7b58a6eb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192340090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.2192340090
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.2300097331
Short name T313
Test name
Test status
Simulation time 211436932 ps
CPU time 0.69 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 197944 kb
Host smart-f366ddc9-9dd1-425c-8229-8fde72bca26e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300097331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.2300097331
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.4063191115
Short name T758
Test name
Test status
Simulation time 79207246 ps
CPU time 1.02 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 199612 kb
Host smart-5fe4ac28-d899-4d16-89b7-60334df1a6d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063191115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.4063191115
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2425206556
Short name T729
Test name
Test status
Simulation time 155181461 ps
CPU time 0.81 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 209412 kb
Host smart-529d5d21-fdf5-41ab-b2a9-aa79cc5b1b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425206556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2425206556
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3304405128
Short name T27
Test name
Test status
Simulation time 894271665 ps
CPU time 1.47 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 217132 kb
Host smart-7a27fc3e-1078-49f2-9730-4777fc2f3e3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304405128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3304405128
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1281807954
Short name T975
Test name
Test status
Simulation time 41395654 ps
CPU time 0.72 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 198660 kb
Host smart-d4daa832-070c-4eec-aef1-77db29a09570
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281807954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.1281807954
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3383248724
Short name T459
Test name
Test status
Simulation time 995548411 ps
CPU time 1.93 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 200708 kb
Host smart-d4e61fc0-91e5-4511-a299-ca4fb6c51a43
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383248724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3383248724
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2101556518
Short name T960
Test name
Test status
Simulation time 1322275710 ps
CPU time 2.09 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 200820 kb
Host smart-8e319c05-3112-40b5-a5b1-b752d7706bd6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101556518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2101556518
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3760923759
Short name T298
Test name
Test status
Simulation time 66177876 ps
CPU time 0.86 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 198992 kb
Host smart-578900f0-857e-4734-8c5f-7ec150920edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760923759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3760923759
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.1960104095
Short name T245
Test name
Test status
Simulation time 41310943 ps
CPU time 0.66 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 198112 kb
Host smart-8b2100f7-4026-40e7-9b83-9c80a469037f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960104095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1960104095
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3223829700
Short name T146
Test name
Test status
Simulation time 15174459068 ps
CPU time 28.18 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:56:00 PM PDT 24
Peak memory 200956 kb
Host smart-34d86de3-e8c3-43ee-aa8c-4010e9eb0af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223829700 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.3223829700
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.3171254905
Short name T669
Test name
Test status
Simulation time 197338072 ps
CPU time 0.83 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:35 PM PDT 24
Peak memory 198276 kb
Host smart-c422752e-d982-4d19-b7ab-ba8cd9e9b88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171254905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3171254905
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.3352388328
Short name T238
Test name
Test status
Simulation time 131303047 ps
CPU time 0.9 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 199008 kb
Host smart-e1c84e4f-064d-45be-8ae2-215740223b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352388328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3352388328
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1621936293
Short name T754
Test name
Test status
Simulation time 59817146 ps
CPU time 0.8 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 199668 kb
Host smart-dbff0cf7-d48a-49e6-b4e5-094f94584286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621936293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1621936293
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.967816866
Short name T804
Test name
Test status
Simulation time 77785981 ps
CPU time 0.67 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 198256 kb
Host smart-6e2d1fe7-c709-4012-985d-5fa520e2e7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967816866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.967816866
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.609278815
Short name T365
Test name
Test status
Simulation time 28619103 ps
CPU time 0.67 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:49 PM PDT 24
Peak memory 197776 kb
Host smart-1fd2fef6-76ec-4105-aa63-a300dec475ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609278815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_
malfunc.609278815
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.1984032815
Short name T257
Test name
Test status
Simulation time 49717893 ps
CPU time 0.63 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 197712 kb
Host smart-69b7d8c6-06ff-4e49-bc06-9e639cea96ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984032815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.1984032815
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2482460146
Short name T337
Test name
Test status
Simulation time 59293990 ps
CPU time 0.61 seconds
Started Jul 11 04:56:40 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 198308 kb
Host smart-9ffcecf5-02f5-4d94-8989-acf1e297c7be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482460146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2482460146
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2982429681
Short name T816
Test name
Test status
Simulation time 44398141 ps
CPU time 0.74 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 201128 kb
Host smart-60dc7a00-e841-429a-a49c-a401cd5d3c99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982429681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2982429681
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1000078546
Short name T223
Test name
Test status
Simulation time 435432703 ps
CPU time 0.81 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 198232 kb
Host smart-f296755f-5ea7-4dba-939d-a530c0178bcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000078546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.1000078546
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.258444627
Short name T659
Test name
Test status
Simulation time 81493390 ps
CPU time 0.96 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 199432 kb
Host smart-0a3882a4-c26a-4e06-b814-17770efdb943
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258444627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.258444627
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1259056207
Short name T599
Test name
Test status
Simulation time 174419615 ps
CPU time 0.86 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 209256 kb
Host smart-67c7c631-b810-4570-829e-64e2a8d3dd24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259056207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1259056207
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.3050387522
Short name T233
Test name
Test status
Simulation time 176097007 ps
CPU time 0.7 seconds
Started Jul 11 04:56:47 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 198324 kb
Host smart-a7a99e97-9f15-421b-9a8e-07ecb6135082
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050387522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.3050387522
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.317686502
Short name T307
Test name
Test status
Simulation time 788019433 ps
CPU time 2.64 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 200780 kb
Host smart-3ac8db97-84ad-4844-8f90-3f91f42ec816
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317686502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.317686502
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4077335994
Short name T961
Test name
Test status
Simulation time 811780685 ps
CPU time 3.18 seconds
Started Jul 11 04:56:39 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 200756 kb
Host smart-b8cc81b8-b90b-4fe1-bd2d-346aab6084ad
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077335994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4077335994
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4265842081
Short name T810
Test name
Test status
Simulation time 166133258 ps
CPU time 0.86 seconds
Started Jul 11 04:56:41 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 198788 kb
Host smart-5223fef7-1a5f-4724-bd76-3cbb58e05481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265842081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4265842081
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2430470988
Short name T907
Test name
Test status
Simulation time 49023296 ps
CPU time 0.67 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 198976 kb
Host smart-c66ea755-1342-4e9b-ad1d-c87b73ed692c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430470988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2430470988
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.1363043914
Short name T934
Test name
Test status
Simulation time 678466538 ps
CPU time 1.43 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 200864 kb
Host smart-37c085bb-c4d5-4dc4-8b08-fd99091c8d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363043914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.1363043914
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1765751333
Short name T49
Test name
Test status
Simulation time 8455363031 ps
CPU time 29.85 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:57:24 PM PDT 24
Peak memory 201124 kb
Host smart-98a855c5-08e7-4d5c-b6a5-5bc5cd5dec1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765751333 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.1765751333
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.3714839360
Short name T142
Test name
Test status
Simulation time 86704799 ps
CPU time 0.86 seconds
Started Jul 11 04:56:44 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 197960 kb
Host smart-2a741d18-c1f6-4af9-90b6-37491752ae2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714839360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.3714839360
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.775961318
Short name T715
Test name
Test status
Simulation time 239893060 ps
CPU time 0.95 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:58 PM PDT 24
Peak memory 199544 kb
Host smart-7209536a-fb60-46e4-87c0-50f9f5f5bb37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775961318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.775961318
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2777867098
Short name T237
Test name
Test status
Simulation time 27215421 ps
CPU time 0.71 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:52 PM PDT 24
Peak memory 198884 kb
Host smart-4a788c78-6b7a-45c2-95a3-a41a32402f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777867098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2777867098
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.2644080181
Short name T185
Test name
Test status
Simulation time 88211759 ps
CPU time 0.73 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 198836 kb
Host smart-ab08973e-4b04-403d-871f-2b3dd2a9e172
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644080181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.2644080181
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.4119695629
Short name T11
Test name
Test status
Simulation time 30917285 ps
CPU time 0.63 seconds
Started Jul 11 04:56:51 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 197712 kb
Host smart-4a1967e6-b4ae-44e8-82d1-d025b39cbd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119695629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.4119695629
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1861610506
Short name T822
Test name
Test status
Simulation time 847055255 ps
CPU time 0.98 seconds
Started Jul 11 04:56:42 PM PDT 24
Finished Jul 11 04:56:51 PM PDT 24
Peak memory 197828 kb
Host smart-59d32f8a-abb2-43bb-bfd2-98db5b7e5d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861610506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1861610506
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1868491157
Short name T144
Test name
Test status
Simulation time 21918609 ps
CPU time 0.62 seconds
Started Jul 11 04:56:51 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 197824 kb
Host smart-6acc6375-5555-41ab-8a29-242bbc6cd482
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868491157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1868491157
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.4042739031
Short name T301
Test name
Test status
Simulation time 52668227 ps
CPU time 0.61 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 198036 kb
Host smart-80f8ce10-27f3-40ca-b73e-ff2cfaef3da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042739031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.4042739031
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.645890037
Short name T779
Test name
Test status
Simulation time 51269069 ps
CPU time 0.68 seconds
Started Jul 11 04:56:55 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 201012 kb
Host smart-ab5ebd86-479c-46f7-8099-1f2b924fc64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645890037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.645890037
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.3278735984
Short name T824
Test name
Test status
Simulation time 326686569 ps
CPU time 1.15 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 199332 kb
Host smart-3e6f2dd6-7658-40dc-a0af-ba4d415404cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278735984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.3278735984
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.589662869
Short name T576
Test name
Test status
Simulation time 81819335 ps
CPU time 0.73 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 198800 kb
Host smart-d0feef75-cc0a-411e-a016-a25e5c2c790d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589662869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.589662869
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.3410322315
Short name T765
Test name
Test status
Simulation time 110280073 ps
CPU time 0.98 seconds
Started Jul 11 04:56:41 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 209092 kb
Host smart-ddbd0109-b4f8-4568-8212-c902f5038cb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410322315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3410322315
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1214399686
Short name T913
Test name
Test status
Simulation time 292963559 ps
CPU time 1.11 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 199656 kb
Host smart-d289f688-72c0-46f5-8523-b863fac20a06
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214399686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.1214399686
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2686947733
Short name T625
Test name
Test status
Simulation time 1270871851 ps
CPU time 2.36 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:53 PM PDT 24
Peak memory 200640 kb
Host smart-0785d79d-4fa3-4cef-9ee2-38c9e28ef9eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686947733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2686947733
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3009704122
Short name T545
Test name
Test status
Simulation time 1090582812 ps
CPU time 2.68 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 200768 kb
Host smart-82000cf4-ff16-4add-a653-171791d141e7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009704122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3009704122
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.748068050
Short name T635
Test name
Test status
Simulation time 299588760 ps
CPU time 0.87 seconds
Started Jul 11 04:56:42 PM PDT 24
Finished Jul 11 04:56:51 PM PDT 24
Peak memory 198904 kb
Host smart-265f40a6-d53a-452a-846e-96f6ee503bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748068050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_
mubi.748068050
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3189717521
Short name T774
Test name
Test status
Simulation time 34224351 ps
CPU time 0.7 seconds
Started Jul 11 04:56:38 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 198108 kb
Host smart-fbb60633-06fa-4c3e-845d-8727e1d58f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189717521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3189717521
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.154125396
Short name T749
Test name
Test status
Simulation time 1435668984 ps
CPU time 1.7 seconds
Started Jul 11 04:56:46 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 200700 kb
Host smart-6d1347cb-f833-464f-94f8-44bc9d4bcb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154125396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.154125396
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.1481938407
Short name T743
Test name
Test status
Simulation time 5464359859 ps
CPU time 20.17 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 200996 kb
Host smart-390659ff-76fe-4537-a076-870817296a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481938407 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.1481938407
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.2890376785
Short name T442
Test name
Test status
Simulation time 92268085 ps
CPU time 0.71 seconds
Started Jul 11 04:56:40 PM PDT 24
Finished Jul 11 04:56:49 PM PDT 24
Peak memory 197888 kb
Host smart-26b73202-4f4b-440e-a91a-0d5d09f61a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890376785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2890376785
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.3237377924
Short name T529
Test name
Test status
Simulation time 327908253 ps
CPU time 1.43 seconds
Started Jul 11 04:56:37 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 200700 kb
Host smart-b0a4c68b-bd48-403e-8ef0-bab25814a686
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237377924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3237377924
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3519111672
Short name T980
Test name
Test status
Simulation time 21933222 ps
CPU time 0.74 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 199076 kb
Host smart-0aa48ce5-9a01-461b-bddc-d3fc3071fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519111672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3519111672
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2354549572
Short name T821
Test name
Test status
Simulation time 297442670 ps
CPU time 0.67 seconds
Started Jul 11 04:56:55 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 198784 kb
Host smart-312192b9-6696-46cf-bc20-f4067097bf1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354549572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.2354549572
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.965036681
Short name T746
Test name
Test status
Simulation time 38017292 ps
CPU time 0.59 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 197648 kb
Host smart-6691da19-4201-4fc5-af50-e96600a721ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965036681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.965036681
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2172072048
Short name T33
Test name
Test status
Simulation time 161199131 ps
CPU time 0.97 seconds
Started Jul 11 04:56:47 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 198348 kb
Host smart-dfc49d8c-5420-435c-86c9-1817fb0c0cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172072048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2172072048
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3973845552
Short name T390
Test name
Test status
Simulation time 43135562 ps
CPU time 0.71 seconds
Started Jul 11 04:56:43 PM PDT 24
Finished Jul 11 04:56:51 PM PDT 24
Peak memory 196996 kb
Host smart-115da290-4711-4722-b832-1c3597e907e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973845552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3973845552
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1148547318
Short name T845
Test name
Test status
Simulation time 61383086 ps
CPU time 0.58 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 197792 kb
Host smart-0bf80a00-f539-4a7b-b780-f3f80c92cb18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148547318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1148547318
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.1538427691
Short name T633
Test name
Test status
Simulation time 72694424 ps
CPU time 0.68 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 200884 kb
Host smart-768e4a4f-a2c3-4137-a9a7-6df9e093b337
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538427691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.1538427691
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.1797270149
Short name T83
Test name
Test status
Simulation time 133248699 ps
CPU time 0.92 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 199352 kb
Host smart-ac093a01-b82a-466b-9a8e-e761f7419a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797270149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.1797270149
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.3266994834
Short name T379
Test name
Test status
Simulation time 88155458 ps
CPU time 0.9 seconds
Started Jul 11 04:56:45 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 199564 kb
Host smart-b8ad5a85-2c02-45ec-9ff1-4b674ca14b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266994834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3266994834
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.3689928676
Short name T155
Test name
Test status
Simulation time 92484495 ps
CPU time 1.11 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 209220 kb
Host smart-797c46a7-aa39-4e16-89ad-a6036c97c449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689928676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.3689928676
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.4288859134
Short name T232
Test name
Test status
Simulation time 150138703 ps
CPU time 0.75 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:01 PM PDT 24
Peak memory 199104 kb
Host smart-9b7ff0a8-65bd-42e6-9865-1333e2dc3f23
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288859134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.4288859134
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2837368300
Short name T501
Test name
Test status
Simulation time 2729521837 ps
CPU time 2.04 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 200824 kb
Host smart-f747be34-f278-42f0-b43f-018037df5728
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837368300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2837368300
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1037840440
Short name T239
Test name
Test status
Simulation time 827746244 ps
CPU time 3.27 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 200884 kb
Host smart-45773243-f9bf-4106-8acb-0082c4abc321
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037840440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1037840440
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.4185231499
Short name T314
Test name
Test status
Simulation time 74609822 ps
CPU time 0.91 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 198980 kb
Host smart-084be2bf-606a-402c-93d9-d8ea67e14071
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185231499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4185231499
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3530488756
Short name T218
Test name
Test status
Simulation time 56764858 ps
CPU time 0.63 seconds
Started Jul 11 04:56:47 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 198112 kb
Host smart-4110fa92-4ca2-439a-aa45-510d69c12807
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530488756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3530488756
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.1538387900
Short name T582
Test name
Test status
Simulation time 2311582715 ps
CPU time 6.24 seconds
Started Jul 11 04:56:57 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 200960 kb
Host smart-e2a709b2-5321-407d-897d-754a1865e607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538387900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.1538387900
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.85448568
Short name T56
Test name
Test status
Simulation time 6405433821 ps
CPU time 10.02 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:11 PM PDT 24
Peak memory 201072 kb
Host smart-02fdb9e7-87de-42a8-b42d-8716a262cdf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85448568 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.85448568
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3949205338
Short name T920
Test name
Test status
Simulation time 224227863 ps
CPU time 1.12 seconds
Started Jul 11 04:56:59 PM PDT 24
Finished Jul 11 04:57:07 PM PDT 24
Peak memory 199304 kb
Host smart-305be5b9-3b9a-487a-93c4-8b4d5281c843
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949205338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3949205338
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.2991120223
Short name T971
Test name
Test status
Simulation time 354928873 ps
CPU time 1.25 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 200640 kb
Host smart-bc5e5074-ea87-4983-acc9-81145afbba06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991120223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2991120223
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.2407921603
Short name T97
Test name
Test status
Simulation time 123882816 ps
CPU time 0.89 seconds
Started Jul 11 04:57:04 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 199620 kb
Host smart-1396d639-5b9e-45fd-8857-11be47f76c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407921603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2407921603
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.470880349
Short name T176
Test name
Test status
Simulation time 56959483 ps
CPU time 0.88 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 198788 kb
Host smart-8c72519b-c788-48ab-bedd-f2c7545ce435
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470880349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disa
ble_rom_integrity_check.470880349
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1267474367
Short name T771
Test name
Test status
Simulation time 29035646 ps
CPU time 0.69 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:01 PM PDT 24
Peak memory 197636 kb
Host smart-6a2b5a34-e957-4416-b5a1-40b3d3cc5ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267474367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.1267474367
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.4169558850
Short name T844
Test name
Test status
Simulation time 167546637 ps
CPU time 0.98 seconds
Started Jul 11 04:56:56 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 197756 kb
Host smart-45db61be-b66f-4b88-8f55-c37b3d74464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169558850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.4169558850
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3783110009
Short name T728
Test name
Test status
Simulation time 62400878 ps
CPU time 0.8 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 197704 kb
Host smart-8ff8f0d9-7b8f-4739-95d0-84bfcaa0b4f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783110009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3783110009
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.942500189
Short name T219
Test name
Test status
Simulation time 22418685 ps
CPU time 0.6 seconds
Started Jul 11 04:56:55 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 197768 kb
Host smart-8cc67b84-d36b-406a-b57a-552457358045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942500189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.942500189
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3716717752
Short name T388
Test name
Test status
Simulation time 44182326 ps
CPU time 0.76 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 200940 kb
Host smart-9407aa58-815d-4ab9-8893-b87391d35622
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716717752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3716717752
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.3763845924
Short name T612
Test name
Test status
Simulation time 287732099 ps
CPU time 1.33 seconds
Started Jul 11 04:56:51 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 199444 kb
Host smart-66dec0f4-ee30-485c-a9b1-7b172364da89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763845924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.3763845924
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2260401902
Short name T554
Test name
Test status
Simulation time 75083882 ps
CPU time 1.02 seconds
Started Jul 11 04:59:48 PM PDT 24
Finished Jul 11 04:59:51 PM PDT 24
Peak memory 199360 kb
Host smart-1ee8216b-1e0e-4a20-9bd5-72962f2b2118
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260401902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2260401902
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.3926473884
Short name T832
Test name
Test status
Simulation time 97640462 ps
CPU time 1.02 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 209260 kb
Host smart-44566659-b643-493a-8a6b-3c00c10fcc89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926473884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3926473884
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.3956059453
Short name T830
Test name
Test status
Simulation time 183926582 ps
CPU time 1.13 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 199748 kb
Host smart-d29936d9-f118-4507-a11f-38c53054e28e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956059453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.3956059453
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1171538282
Short name T811
Test name
Test status
Simulation time 928499639 ps
CPU time 3.01 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 200824 kb
Host smart-c984c994-4fb7-4644-82f3-c3b16d0e1138
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171538282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1171538282
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2740116843
Short name T183
Test name
Test status
Simulation time 1516985020 ps
CPU time 1.81 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 200528 kb
Host smart-e48d36ef-1d36-4996-b648-a2e9178de233
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740116843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2740116843
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2217128744
Short name T368
Test name
Test status
Simulation time 135288271 ps
CPU time 0.83 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 198904 kb
Host smart-ea1a6db2-3658-49ce-a721-f0cc16e4be24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217128744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2217128744
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2878801886
Short name T533
Test name
Test status
Simulation time 37240645 ps
CPU time 0.7 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:05 PM PDT 24
Peak memory 199072 kb
Host smart-757cc23d-557b-45f2-aa05-2e6a874d4190
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878801886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2878801886
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.466985505
Short name T94
Test name
Test status
Simulation time 5966980503 ps
CPU time 3.36 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:57:00 PM PDT 24
Peak memory 200944 kb
Host smart-e1544c8d-3268-48d8-85cd-1ba60df6c0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466985505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.466985505
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1558693882
Short name T706
Test name
Test status
Simulation time 4712180789 ps
CPU time 11.61 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:57:08 PM PDT 24
Peak memory 201072 kb
Host smart-f58bed77-e2c9-4df5-bf01-7d79423c7e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558693882 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1558693882
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.1022359240
Short name T41
Test name
Test status
Simulation time 296688885 ps
CPU time 1 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 199408 kb
Host smart-aa79bdd1-2430-429d-aca2-84a4c2447cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022359240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.1022359240
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.2402332075
Short name T309
Test name
Test status
Simulation time 73764596 ps
CPU time 0.74 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 198672 kb
Host smart-cbe9da29-57e5-4eeb-bbf3-5f898091c795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402332075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.2402332075
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1430085647
Short name T423
Test name
Test status
Simulation time 100207551 ps
CPU time 0.81 seconds
Started Jul 11 04:56:48 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 199840 kb
Host smart-21be49bf-de7a-4474-a0eb-1dd373d4cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430085647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1430085647
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.323071645
Short name T933
Test name
Test status
Simulation time 46473002 ps
CPU time 0.78 seconds
Started Jul 11 04:56:57 PM PDT 24
Finished Jul 11 04:57:05 PM PDT 24
Peak memory 198872 kb
Host smart-e1128231-026c-4a37-a8d0-dedb6b27a0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323071645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.323071645
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.362885445
Short name T180
Test name
Test status
Simulation time 30133499 ps
CPU time 0.67 seconds
Started Jul 11 04:56:57 PM PDT 24
Finished Jul 11 04:57:05 PM PDT 24
Peak memory 197716 kb
Host smart-17e26004-ca03-4ada-bba4-46fe296467c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362885445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_
malfunc.362885445
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2882613968
Short name T348
Test name
Test status
Simulation time 164845140 ps
CPU time 0.96 seconds
Started Jul 11 05:33:32 PM PDT 24
Finished Jul 11 05:33:36 PM PDT 24
Peak memory 197824 kb
Host smart-19493ebd-e577-4032-b7d7-d89329692bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882613968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2882613968
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.361622351
Short name T284
Test name
Test status
Simulation time 112230081 ps
CPU time 0.66 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:08 PM PDT 24
Peak memory 197716 kb
Host smart-c603a12a-6c3c-4cb1-ac1a-509c1470f87b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361622351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.361622351
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2600835923
Short name T882
Test name
Test status
Simulation time 236053647 ps
CPU time 0.61 seconds
Started Jul 11 05:19:38 PM PDT 24
Finished Jul 11 05:19:41 PM PDT 24
Peak memory 197744 kb
Host smart-a4c9ee5d-b5a4-40fc-80fb-883992603afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600835923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2600835923
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2535511993
Short name T799
Test name
Test status
Simulation time 38832206 ps
CPU time 0.74 seconds
Started Jul 11 05:45:03 PM PDT 24
Finished Jul 11 05:45:05 PM PDT 24
Peak memory 201072 kb
Host smart-b112a035-4a3b-41b3-8385-b6fe9b044e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535511993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2535511993
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.2828078364
Short name T857
Test name
Test status
Simulation time 356567355 ps
CPU time 0.93 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 199416 kb
Host smart-1b189c5b-48e7-45d7-aa8c-8b31c36950f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828078364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.2828078364
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1714410286
Short name T702
Test name
Test status
Simulation time 263024826 ps
CPU time 0.87 seconds
Started Jul 11 05:17:39 PM PDT 24
Finished Jul 11 05:17:41 PM PDT 24
Peak memory 199352 kb
Host smart-2509be05-a3a4-49db-bc2c-bed158c8e165
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714410286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1714410286
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1603144928
Short name T763
Test name
Test status
Simulation time 170954976 ps
CPU time 0.78 seconds
Started Jul 11 05:12:20 PM PDT 24
Finished Jul 11 05:12:22 PM PDT 24
Peak memory 209092 kb
Host smart-3519ffd2-1c45-415c-b634-fa971f0a6055
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603144928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1603144928
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.518200289
Short name T448
Test name
Test status
Simulation time 306869550 ps
CPU time 1.33 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:17 PM PDT 24
Peak memory 200532 kb
Host smart-251d3a42-5b12-4e28-a072-5aba36f35227
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518200289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_c
m_ctrl_config_regwen.518200289
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2651589891
Short name T350
Test name
Test status
Simulation time 961689542 ps
CPU time 2.92 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 201076 kb
Host smart-cb156eeb-d064-4880-8897-f8a231fdb704
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651589891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2651589891
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1511317857
Short name T209
Test name
Test status
Simulation time 1097764329 ps
CPU time 2.07 seconds
Started Jul 11 05:13:34 PM PDT 24
Finished Jul 11 05:13:38 PM PDT 24
Peak memory 200792 kb
Host smart-6b6f95af-2e5e-410d-8abb-3a01ff3303b5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511317857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1511317857
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1926206582
Short name T36
Test name
Test status
Simulation time 102444348 ps
CPU time 0.95 seconds
Started Jul 11 04:57:46 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 199036 kb
Host smart-93d11793-dc12-4b5b-a1f9-9ab5542759a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926206582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1926206582
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2371504267
Short name T567
Test name
Test status
Simulation time 32709040 ps
CPU time 0.7 seconds
Started Jul 11 04:56:50 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 199308 kb
Host smart-0f5940b7-786a-46d4-a2b5-66c2221245d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371504267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2371504267
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.2051075803
Short name T98
Test name
Test status
Simulation time 2382891610 ps
CPU time 7.98 seconds
Started Jul 11 04:56:52 PM PDT 24
Finished Jul 11 04:57:08 PM PDT 24
Peak memory 200952 kb
Host smart-7795adcc-392e-4673-8ac8-68269170d499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051075803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.2051075803
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.4104818799
Short name T604
Test name
Test status
Simulation time 4337772893 ps
CPU time 6.6 seconds
Started Jul 11 04:57:07 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 201024 kb
Host smart-317d4f3b-c4e7-4937-8fad-9bf1f552e703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104818799 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.4104818799
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.342974748
Short name T433
Test name
Test status
Simulation time 117905035 ps
CPU time 0.91 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 198192 kb
Host smart-747d5715-46bd-4ba2-b761-85c8bfb6df2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342974748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.342974748
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.2448724925
Short name T472
Test name
Test status
Simulation time 78700189 ps
CPU time 0.84 seconds
Started Jul 11 05:17:15 PM PDT 24
Finished Jul 11 05:17:17 PM PDT 24
Peak memory 198980 kb
Host smart-e4fd5cb1-de31-4df0-ac65-a618844b2d27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448724925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2448724925
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3720195662
Short name T500
Test name
Test status
Simulation time 28133410 ps
CPU time 0.88 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:16 PM PDT 24
Peak memory 200428 kb
Host smart-d4608618-1cfb-4837-9cfd-d67f8367d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720195662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3720195662
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2367501350
Short name T684
Test name
Test status
Simulation time 54810813 ps
CPU time 0.85 seconds
Started Jul 11 04:57:01 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 198876 kb
Host smart-4e71c4c8-6d5e-401c-a297-b983d8b098f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367501350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2367501350
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.140807234
Short name T289
Test name
Test status
Simulation time 33164018 ps
CPU time 0.61 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:05 PM PDT 24
Peak memory 197020 kb
Host smart-e0c073c2-ad67-4094-905c-f7e944c6f0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140807234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.140807234
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2801469934
Short name T563
Test name
Test status
Simulation time 693427255 ps
CPU time 0.95 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 197776 kb
Host smart-580f6a1e-9d43-40ef-b9bd-2e6a924b23be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801469934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2801469934
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1941772746
Short name T531
Test name
Test status
Simulation time 66972409 ps
CPU time 0.61 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 197068 kb
Host smart-db3312d3-30bf-415b-bc22-a95e64d0c78b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941772746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1941772746
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1322333867
Short name T258
Test name
Test status
Simulation time 56287706 ps
CPU time 0.64 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 197728 kb
Host smart-3443bf6b-95ad-4d69-bd79-9c4abc60922d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322333867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1322333867
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3149674501
Short name T647
Test name
Test status
Simulation time 74239532 ps
CPU time 0.68 seconds
Started Jul 11 04:56:56 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 201064 kb
Host smart-bf40b458-3ea1-48c0-91e2-fcb2dd136c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149674501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3149674501
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.1895203406
Short name T973
Test name
Test status
Simulation time 232745556 ps
CPU time 0.81 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 198204 kb
Host smart-a9eaef91-2443-4deb-97ea-35d531471286
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895203406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.1895203406
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.4081686557
Short name T638
Test name
Test status
Simulation time 65976876 ps
CPU time 0.86 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 199452 kb
Host smart-c28ef680-9b33-4e77-b008-f93155cb341c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081686557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.4081686557
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.581171255
Short name T364
Test name
Test status
Simulation time 148500986 ps
CPU time 0.78 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 209180 kb
Host smart-bb3704b1-7e3c-41ec-8d7e-913b119bf37c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581171255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.581171255
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1972519831
Short name T302
Test name
Test status
Simulation time 198479472 ps
CPU time 1.09 seconds
Started Jul 11 04:56:56 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 199564 kb
Host smart-5f79f846-3ddd-438c-bdfc-3172b239e692
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972519831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.1972519831
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2562916472
Short name T908
Test name
Test status
Simulation time 951801899 ps
CPU time 2.54 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 200672 kb
Host smart-51b2f327-9d70-4008-9f10-6844e19ae8a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562916472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2562916472
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3159212563
Short name T229
Test name
Test status
Simulation time 747363406 ps
CPU time 3.05 seconds
Started Jul 11 04:57:01 PM PDT 24
Finished Jul 11 04:57:11 PM PDT 24
Peak memory 200844 kb
Host smart-4ca603b2-5c91-4790-9621-448bf615dbd4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159212563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3159212563
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.203654656
Short name T504
Test name
Test status
Simulation time 89124547 ps
CPU time 0.88 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 198908 kb
Host smart-b4542139-8979-4c70-8950-bba892017b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203654656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.203654656
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1830265414
Short name T419
Test name
Test status
Simulation time 29940629 ps
CPU time 0.72 seconds
Started Jul 11 04:56:55 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 198996 kb
Host smart-e6a6dae3-7ed5-4490-8b45-47acc3c23036
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830265414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1830265414
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.1159846480
Short name T919
Test name
Test status
Simulation time 1224833638 ps
CPU time 3.86 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 200880 kb
Host smart-21b45e16-f77b-4e5e-8d69-ae9ac263f81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159846480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.1159846480
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.2514903375
Short name T21
Test name
Test status
Simulation time 6202930175 ps
CPU time 17.87 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 201008 kb
Host smart-37aad9f8-ebe8-465c-aa6f-32cc9b833db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514903375 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.2514903375
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.2405989051
Short name T236
Test name
Test status
Simulation time 172083743 ps
CPU time 0.76 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 198808 kb
Host smart-57a4e159-4aa1-41a1-aab6-74a33a09b97a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405989051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2405989051
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.2374033377
Short name T705
Test name
Test status
Simulation time 158077610 ps
CPU time 0.78 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:11 PM PDT 24
Peak memory 198204 kb
Host smart-e31a981a-697f-47d0-a91d-51bb03a9e5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374033377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2374033377
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.1412755483
Short name T963
Test name
Test status
Simulation time 80639123 ps
CPU time 1 seconds
Started Jul 11 04:56:55 PM PDT 24
Finished Jul 11 04:57:03 PM PDT 24
Peak memory 200220 kb
Host smart-0cc5b96e-e2a4-460c-862a-2615f6d633ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412755483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.1412755483
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1145776918
Short name T696
Test name
Test status
Simulation time 60075662 ps
CPU time 0.82 seconds
Started Jul 11 04:57:07 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 198696 kb
Host smart-e59ac6a7-9070-4036-bdb0-bc7e378d3354
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145776918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1145776918
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3057168147
Short name T497
Test name
Test status
Simulation time 39050373 ps
CPU time 0.61 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:16 PM PDT 24
Peak memory 197008 kb
Host smart-945b8ec2-9a31-4ca7-bd86-276e26031c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057168147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3057168147
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.1470507958
Short name T465
Test name
Test status
Simulation time 165340745 ps
CPU time 0.94 seconds
Started Jul 11 04:57:07 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 197700 kb
Host smart-0b1239cb-b11c-41a3-87c7-1aaf1f443d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470507958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1470507958
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.1264060081
Short name T420
Test name
Test status
Simulation time 45941856 ps
CPU time 0.59 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 196968 kb
Host smart-b88d906a-b06f-42a9-a828-c307e3fe04f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264060081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1264060081
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.1103472023
Short name T866
Test name
Test status
Simulation time 27620858 ps
CPU time 0.66 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 198092 kb
Host smart-2db7769a-8e1f-4971-a884-f2422d830e54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103472023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.1103472023
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.241655003
Short name T680
Test name
Test status
Simulation time 45282166 ps
CPU time 0.72 seconds
Started Jul 11 04:57:01 PM PDT 24
Finished Jul 11 04:57:08 PM PDT 24
Peak memory 201120 kb
Host smart-c8206b14-4976-46fd-88c0-87c8a9d1c97a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241655003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invali
d.241655003
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.1270073226
Short name T341
Test name
Test status
Simulation time 192324893 ps
CPU time 0.95 seconds
Started Jul 11 04:56:53 PM PDT 24
Finished Jul 11 04:57:02 PM PDT 24
Peak memory 199332 kb
Host smart-05a17429-780c-4eff-ac91-78726f73b7cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270073226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.1270073226
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2031404920
Short name T835
Test name
Test status
Simulation time 59106111 ps
CPU time 0.63 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 198832 kb
Host smart-1f3f6c11-a374-4e9e-9f6b-d811e35ca372
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031404920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2031404920
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1672816756
Short name T222
Test name
Test status
Simulation time 119775189 ps
CPU time 0.81 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:16 PM PDT 24
Peak memory 209072 kb
Host smart-f3c24ac2-4c46-4280-ae42-0abb09f987e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672816756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1672816756
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.4178754085
Short name T740
Test name
Test status
Simulation time 176528838 ps
CPU time 0.77 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 198816 kb
Host smart-c32803e2-9327-4e07-b70d-5d4ab91757b4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178754085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.4178754085
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4241261350
Short name T691
Test name
Test status
Simulation time 1206074823 ps
CPU time 2.3 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 200688 kb
Host smart-cbc70c9e-dc7a-46af-a892-8cfa27d5a7fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241261350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4241261350
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172386108
Short name T323
Test name
Test status
Simulation time 1026805862 ps
CPU time 2.01 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 200768 kb
Host smart-c3b602f7-ef02-4d61-af28-76af00e47937
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172386108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172386108
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3716508218
Short name T401
Test name
Test status
Simulation time 182652133 ps
CPU time 0.89 seconds
Started Jul 11 04:56:56 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 199240 kb
Host smart-797c7deb-be0e-40bb-8fbb-6f7570292ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716508218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3716508218
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3000615707
Short name T7
Test name
Test status
Simulation time 47979032 ps
CPU time 0.66 seconds
Started Jul 11 04:56:56 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 198960 kb
Host smart-1f8a975a-e337-401e-ac2f-87c9925ce240
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000615707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3000615707
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.4220584756
Short name T6
Test name
Test status
Simulation time 1235092366 ps
CPU time 2.04 seconds
Started Jul 11 04:56:54 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 200840 kb
Host smart-03f20527-a675-4ebf-941f-afcf232b976e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220584756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.4220584756
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2315429724
Short name T54
Test name
Test status
Simulation time 5558703616 ps
CPU time 19.89 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 201052 kb
Host smart-5c51c316-4c6f-417f-af53-ebefdbaf0edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315429724 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.2315429724
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.4161647977
Short name T90
Test name
Test status
Simulation time 254444017 ps
CPU time 0.8 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 197996 kb
Host smart-99872316-b744-47c1-b5f8-fc124bfc22ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161647977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.4161647977
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.535496976
Short name T903
Test name
Test status
Simulation time 311794479 ps
CPU time 1.57 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:17 PM PDT 24
Peak memory 200628 kb
Host smart-4fe97529-6117-40de-8a6c-966a1b1e06a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535496976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.535496976
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.2623500611
Short name T95
Test name
Test status
Simulation time 29923281 ps
CPU time 0.99 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 200620 kb
Host smart-5847c2d0-d2d0-4140-be5a-465bdfb57992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623500611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2623500611
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1704478472
Short name T537
Test name
Test status
Simulation time 56825787 ps
CPU time 0.86 seconds
Started Jul 11 04:56:59 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 198780 kb
Host smart-07eef138-df33-4a7c-bbf3-3dbd88f061c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704478472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.1704478472
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3164747470
Short name T412
Test name
Test status
Simulation time 31371286 ps
CPU time 0.62 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 197716 kb
Host smart-0d498e68-8f5b-4dc9-bbeb-95dea7fdf603
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164747470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.3164747470
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.4051657327
Short name T171
Test name
Test status
Simulation time 596970208 ps
CPU time 0.92 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 198020 kb
Host smart-a0f7c623-4893-4e64-b1c3-2337b3f9eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051657327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.4051657327
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.169791480
Short name T439
Test name
Test status
Simulation time 71622627 ps
CPU time 0.67 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:16 PM PDT 24
Peak memory 197028 kb
Host smart-ef68e7d5-5b2f-42ad-a0e1-b28122a74098
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169791480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.169791480
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2533359932
Short name T179
Test name
Test status
Simulation time 44253589 ps
CPU time 0.61 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 197708 kb
Host smart-c68e277e-4e85-4e47-bb75-e08e27e2be93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533359932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2533359932
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.2133338909
Short name T764
Test name
Test status
Simulation time 50630215 ps
CPU time 0.69 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 200852 kb
Host smart-4bc89f74-09f9-496a-a8a9-dc935d75d334
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133338909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.2133338909
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.1770575315
Short name T322
Test name
Test status
Simulation time 202705000 ps
CPU time 1.07 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 199308 kb
Host smart-d9eefe53-3dba-4193-b178-1d69979a220f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770575315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.1770575315
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.533980213
Short name T714
Test name
Test status
Simulation time 66025872 ps
CPU time 0.94 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 199520 kb
Host smart-e64b37de-29ea-46bf-8380-272bcc40bc03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533980213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.533980213
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.4188905227
Short name T930
Test name
Test status
Simulation time 112466759 ps
CPU time 1.04 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:24 PM PDT 24
Peak memory 209212 kb
Host smart-a15d8bf4-2809-4fff-a991-7fbbcde9d7b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188905227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4188905227
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3660819597
Short name T534
Test name
Test status
Simulation time 230879461 ps
CPU time 0.88 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:05 PM PDT 24
Peak memory 199752 kb
Host smart-1b989f34-a4a6-4fd2-82b0-c063531c9600
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660819597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.3660819597
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.491489578
Short name T931
Test name
Test status
Simulation time 845269140 ps
CPU time 3.24 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 200684 kb
Host smart-60f5417d-d43c-45ce-b3cd-1946438b6996
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491489578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.491489578
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.695856753
Short name T453
Test name
Test status
Simulation time 1323768759 ps
CPU time 2.3 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 200712 kb
Host smart-4ed56fb4-9002-4ceb-95c5-5a08647f8799
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695856753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.695856753
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.4218254708
Short name T735
Test name
Test status
Simulation time 76968457 ps
CPU time 1.06 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 199068 kb
Host smart-56233260-cfab-4e4f-b36e-18bc1277284d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218254708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4218254708
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.2680767628
Short name T1001
Test name
Test status
Simulation time 55892685 ps
CPU time 0.64 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 198148 kb
Host smart-2c422a91-2b29-47f7-8757-865bab9378a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680767628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2680767628
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.2589106483
Short name T526
Test name
Test status
Simulation time 2137285905 ps
CPU time 4.81 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 200884 kb
Host smart-742def9b-a5bb-498a-85b4-031cefc9a2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589106483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2589106483
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3886832909
Short name T52
Test name
Test status
Simulation time 6717056079 ps
CPU time 19.51 seconds
Started Jul 11 04:57:11 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 201044 kb
Host smart-5ffb7139-6023-4f05-9801-71f5ddc2c5ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886832909 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.3886832909
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.2079586590
Short name T768
Test name
Test status
Simulation time 308789010 ps
CPU time 1.08 seconds
Started Jul 11 04:56:58 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 199476 kb
Host smart-1e99f340-ca5c-48fd-9c7c-5a5cd8addfe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079586590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2079586590
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.1941892952
Short name T294
Test name
Test status
Simulation time 151604509 ps
CPU time 1.18 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 199700 kb
Host smart-4681fa0b-0fd3-4742-b198-828e0c8c1fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941892952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1941892952
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1649682598
Short name T607
Test name
Test status
Simulation time 43632340 ps
CPU time 0.88 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:07 PM PDT 24
Peak memory 199808 kb
Host smart-95d7af25-6344-4f62-9646-86603d6e0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649682598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1649682598
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2508946501
Short name T609
Test name
Test status
Simulation time 81581948 ps
CPU time 0.72 seconds
Started Jul 11 04:57:09 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 197860 kb
Host smart-081747d2-fb9d-4b01-96a0-0f1264143bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508946501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2508946501
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3666991367
Short name T477
Test name
Test status
Simulation time 29997100 ps
CPU time 0.66 seconds
Started Jul 11 04:57:09 PM PDT 24
Finished Jul 11 04:57:17 PM PDT 24
Peak memory 196164 kb
Host smart-8f1cf431-d5b7-4b28-9134-54c0a4ad7a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666991367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3666991367
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.632020768
Short name T327
Test name
Test status
Simulation time 279212915 ps
CPU time 0.98 seconds
Started Jul 11 04:57:11 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 198004 kb
Host smart-59b79899-f891-4879-8d1d-c2efeb28696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632020768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.632020768
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.1951712674
Short name T693
Test name
Test status
Simulation time 58513198 ps
CPU time 0.6 seconds
Started Jul 11 04:58:23 PM PDT 24
Finished Jul 11 04:58:35 PM PDT 24
Peak memory 197776 kb
Host smart-36720694-aec1-4f1b-8ebb-8a39cd438695
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951712674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1951712674
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.957045369
Short name T261
Test name
Test status
Simulation time 48614627 ps
CPU time 0.63 seconds
Started Jul 11 04:56:59 PM PDT 24
Finished Jul 11 04:57:06 PM PDT 24
Peak memory 197772 kb
Host smart-4b6d1a2a-796e-4fd9-a1f2-ca33a2686fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957045369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.957045369
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3708027043
Short name T622
Test name
Test status
Simulation time 78158869 ps
CPU time 0.75 seconds
Started Jul 11 04:57:15 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 201048 kb
Host smart-a8f91459-93a6-49b0-9303-071d7aad620b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708027043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3708027043
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.1303992049
Short name T437
Test name
Test status
Simulation time 51644145 ps
CPU time 0.75 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 198004 kb
Host smart-e5e51220-abad-4d77-9b5e-8166f6217244
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303992049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.1303992049
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.368906423
Short name T265
Test name
Test status
Simulation time 148891954 ps
CPU time 0.79 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 199324 kb
Host smart-c22c09af-8770-4859-9f1a-6dbc95b5c458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368906423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.368906423
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.4045338289
Short name T690
Test name
Test status
Simulation time 103697966 ps
CPU time 0.92 seconds
Started Jul 11 04:57:07 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 209176 kb
Host smart-fbd17ff5-c2dd-4232-8767-2263b554b8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045338289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.4045338289
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.1469326299
Short name T226
Test name
Test status
Simulation time 196704883 ps
CPU time 0.77 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 198260 kb
Host smart-c262d4aa-0c4e-4175-82a6-00d059ab7691
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469326299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.1469326299
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3545082261
Short name T317
Test name
Test status
Simulation time 801415841 ps
CPU time 2.86 seconds
Started Jul 11 04:56:59 PM PDT 24
Finished Jul 11 04:57:08 PM PDT 24
Peak memory 200808 kb
Host smart-7298de46-3e40-493a-8f2d-89c58e566eab
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545082261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3545082261
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2399095821
Short name T449
Test name
Test status
Simulation time 1014361420 ps
CPU time 2.1 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 200824 kb
Host smart-7a778c78-944d-4769-aa4c-34e802c22812
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399095821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2399095821
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3264719890
Short name T872
Test name
Test status
Simulation time 68551004 ps
CPU time 0.97 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 199048 kb
Host smart-21e873e0-8205-4d6a-b422-1c6d403e2980
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264719890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3264719890
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.1202292902
Short name T546
Test name
Test status
Simulation time 32286970 ps
CPU time 0.67 seconds
Started Jul 11 04:57:00 PM PDT 24
Finished Jul 11 04:57:07 PM PDT 24
Peak memory 199060 kb
Host smart-bd400731-12d2-4eb4-a5f6-dde75eeea5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202292902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1202292902
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.4222871536
Short name T587
Test name
Test status
Simulation time 1423885388 ps
CPU time 3.55 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 200892 kb
Host smart-4a61ff44-7256-4fa9-867c-7d05969d4bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222871536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.4222871536
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.4056905713
Short name T135
Test name
Test status
Simulation time 5283984995 ps
CPU time 16.14 seconds
Started Jul 11 04:57:17 PM PDT 24
Finished Jul 11 04:57:41 PM PDT 24
Peak memory 201296 kb
Host smart-8c8ce8d5-5716-44c6-8cd5-b531e3b84bc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056905713 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.4056905713
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.1763565433
Short name T775
Test name
Test status
Simulation time 360532609 ps
CPU time 0.85 seconds
Started Jul 11 04:57:02 PM PDT 24
Finished Jul 11 04:57:09 PM PDT 24
Peak memory 199268 kb
Host smart-f757720f-6122-4b30-9da6-338c4e84e552
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763565433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.1763565433
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1961359641
Short name T290
Test name
Test status
Simulation time 148400908 ps
CPU time 0.75 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 198928 kb
Host smart-5f8ae782-0a46-4c24-b68e-87dbcbb8614d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961359641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1961359641
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3251339757
Short name T384
Test name
Test status
Simulation time 23655661 ps
CPU time 0.76 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 198900 kb
Host smart-5ec499c8-73a0-4774-afb8-002f8836723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251339757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3251339757
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.4103181698
Short name T203
Test name
Test status
Simulation time 94545726 ps
CPU time 0.66 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 198348 kb
Host smart-379b02ea-4113-4437-b0fc-e71c9cfb2f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103181698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.4103181698
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.1666658245
Short name T895
Test name
Test status
Simulation time 32629263 ps
CPU time 0.59 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:18 PM PDT 24
Peak memory 197716 kb
Host smart-74e12756-4932-40f3-9f42-c77a72c073b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666658245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.1666658245
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2163506872
Short name T689
Test name
Test status
Simulation time 1899595925 ps
CPU time 0.99 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 197780 kb
Host smart-4f43fefc-c461-4ca6-b501-bd67cf987e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163506872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2163506872
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.58200230
Short name T149
Test name
Test status
Simulation time 67322489 ps
CPU time 0.62 seconds
Started Jul 11 04:57:07 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 197828 kb
Host smart-37a13c59-0b91-4606-a440-726d88ab43da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58200230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.58200230
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.924066656
Short name T950
Test name
Test status
Simulation time 53336465 ps
CPU time 0.67 seconds
Started Jul 11 04:57:17 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 197972 kb
Host smart-1b2c07d1-88ff-41e3-994a-a04d9f8f07a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924066656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.924066656
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.932159625
Short name T966
Test name
Test status
Simulation time 78126525 ps
CPU time 0.68 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 200948 kb
Host smart-277c0878-c2a0-4f83-a86f-49b46cd79d85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932159625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invali
d.932159625
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.1764705825
Short name T40
Test name
Test status
Simulation time 74707114 ps
CPU time 0.68 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 198004 kb
Host smart-ffd15449-26d6-4798-8b2f-b641e22a4a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764705825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.1764705825
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1007150652
Short name T39
Test name
Test status
Simulation time 69687712 ps
CPU time 0.75 seconds
Started Jul 11 04:57:17 PM PDT 24
Finished Jul 11 04:57:24 PM PDT 24
Peak memory 198688 kb
Host smart-d9c94e81-2e70-4b34-8236-9546e72f2d6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007150652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1007150652
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.102462361
Short name T803
Test name
Test status
Simulation time 120489549 ps
CPU time 0.94 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 209196 kb
Host smart-671a2bee-921e-48bd-9f83-ac494c46f085
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102462361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.102462361
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3385296459
Short name T286
Test name
Test status
Simulation time 442229885 ps
CPU time 1 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:31 PM PDT 24
Peak memory 199840 kb
Host smart-b38f50f7-33ac-4928-945d-c98ee54096ca
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385296459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.3385296459
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.999222874
Short name T838
Test name
Test status
Simulation time 749498365 ps
CPU time 2.83 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 200812 kb
Host smart-29355ec8-c296-4dab-ab67-7883e314d3b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999222874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.999222874
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1405996136
Short name T214
Test name
Test status
Simulation time 761924579 ps
CPU time 3.18 seconds
Started Jul 11 04:57:05 PM PDT 24
Finished Jul 11 04:57:16 PM PDT 24
Peak memory 200848 kb
Host smart-418f655b-e404-44bf-ba80-378645ad19bd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405996136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1405996136
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2240886844
Short name T849
Test name
Test status
Simulation time 97210514 ps
CPU time 0.9 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:10 PM PDT 24
Peak memory 198948 kb
Host smart-8838116f-a291-457f-898e-03a73fabc637
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240886844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2240886844
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.3021413931
Short name T904
Test name
Test status
Simulation time 58557317 ps
CPU time 0.65 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 198160 kb
Host smart-da06de64-a6c4-4ea0-8fa0-53a8ded6d678
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021413931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3021413931
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.1584795960
Short name T475
Test name
Test status
Simulation time 296643456 ps
CPU time 0.95 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:31 PM PDT 24
Peak memory 200636 kb
Host smart-9630ee23-d6f9-42b1-abe1-a279338f47ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584795960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.1584795960
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.1610262013
Short name T948
Test name
Test status
Simulation time 6093979066 ps
CPU time 8.8 seconds
Started Jul 11 04:57:04 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 201004 kb
Host smart-917db502-ef1d-4555-9ea0-7fafe57a984e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610262013 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.1610262013
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.1073461620
Short name T970
Test name
Test status
Simulation time 99384531 ps
CPU time 0.84 seconds
Started Jul 11 04:57:17 PM PDT 24
Finished Jul 11 04:57:24 PM PDT 24
Peak memory 198844 kb
Host smart-0e92cbe4-a332-4c19-9297-beb43eb6b7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073461620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1073461620
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.970061737
Short name T753
Test name
Test status
Simulation time 327210841 ps
CPU time 1.55 seconds
Started Jul 11 04:57:04 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 200532 kb
Host smart-826d380e-8131-4e3f-92a7-8c8ca3bc28b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970061737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.970061737
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2764702117
Short name T121
Test name
Test status
Simulation time 29087523 ps
CPU time 0.76 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 198608 kb
Host smart-eede8d7d-b5a6-48d3-8ddf-f27a19f7502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764702117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2764702117
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.697733752
Short name T889
Test name
Test status
Simulation time 69892163 ps
CPU time 0.71 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 198092 kb
Host smart-db9ba43b-2055-416f-b50c-e0e0bd34801e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697733752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.697733752
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1026352540
Short name T979
Test name
Test status
Simulation time 32908413 ps
CPU time 0.59 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 197732 kb
Host smart-1d24cc21-cf75-4834-95ce-702a1e99658c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026352540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1026352540
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2943608132
Short name T673
Test name
Test status
Simulation time 162590311 ps
CPU time 0.92 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 197708 kb
Host smart-d4d825fa-3f17-45c2-971f-cf9247763f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943608132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2943608132
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3101159428
Short name T1002
Test name
Test status
Simulation time 52863227 ps
CPU time 0.72 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 197000 kb
Host smart-1bca845e-e12b-45cc-bbc6-739285b4f3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101159428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3101159428
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.3346959524
Short name T344
Test name
Test status
Simulation time 51295843 ps
CPU time 0.6 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 198076 kb
Host smart-70c7f666-e444-48e0-bf28-d6cf53b264eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346959524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3346959524
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.24379371
Short name T655
Test name
Test status
Simulation time 46376536 ps
CPU time 0.72 seconds
Started Jul 11 04:55:31 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 201016 kb
Host smart-5c3d2528-0bf6-45f8-9de5-beead23e2868
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.24379371
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.2656283548
Short name T840
Test name
Test status
Simulation time 162487553 ps
CPU time 0.92 seconds
Started Jul 11 04:55:24 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 198056 kb
Host smart-98384a85-510f-4a88-8b46-fe524ca65da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656283548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.2656283548
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.4233938584
Short name T329
Test name
Test status
Simulation time 91015633 ps
CPU time 0.89 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 199520 kb
Host smart-5f803b1d-8d78-45ac-8492-2f794935e044
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233938584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.4233938584
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.957423256
Short name T944
Test name
Test status
Simulation time 167916712 ps
CPU time 0.79 seconds
Started Jul 11 04:55:28 PM PDT 24
Finished Jul 11 04:55:35 PM PDT 24
Peak memory 209164 kb
Host smart-16cadc30-cee1-495d-936e-134fd9fef3ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957423256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.957423256
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.3853598277
Short name T17
Test name
Test status
Simulation time 908327976 ps
CPU time 1.45 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 217452 kb
Host smart-f4b29373-13fa-4fd0-b45b-7d3ba7ac4355
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853598277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3853598277
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1275141761
Short name T842
Test name
Test status
Simulation time 72771770 ps
CPU time 0.75 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 198220 kb
Host smart-ee52716b-77e7-4b76-8076-7a64e5514bd3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275141761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.1275141761
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4016876683
Short name T861
Test name
Test status
Simulation time 1167940962 ps
CPU time 1.87 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 200816 kb
Host smart-bf265314-27c7-473c-89eb-d64044bd63f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016876683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4016876683
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2826167322
Short name T833
Test name
Test status
Simulation time 1024760529 ps
CPU time 2.89 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 200812 kb
Host smart-2cbec0e9-9200-4777-b9ba-f1e29c020a18
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826167322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2826167322
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3199028691
Short name T709
Test name
Test status
Simulation time 55018585 ps
CPU time 0.92 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:39 PM PDT 24
Peak memory 198900 kb
Host smart-4407c4bf-04ae-4fe0-aab1-714780cffbb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199028691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3199028691
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2998124382
Short name T425
Test name
Test status
Simulation time 63858291 ps
CPU time 0.62 seconds
Started Jul 11 04:55:25 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 198116 kb
Host smart-991e1b13-260e-4016-ae03-e994534c4e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998124382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2998124382
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.2932052654
Short name T660
Test name
Test status
Simulation time 1692020789 ps
CPU time 2.89 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 200924 kb
Host smart-fb6d4d88-67cb-46f1-97a0-faeaf82ca1a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932052654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.2932052654
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.114318714
Short name T744
Test name
Test status
Simulation time 7706673191 ps
CPU time 28.85 seconds
Started Jul 11 04:55:31 PM PDT 24
Finished Jul 11 04:56:08 PM PDT 24
Peak memory 201100 kb
Host smart-1ae692cf-0d2b-4ce8-b0ae-ab650c90afeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114318714 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.114318714
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.1102108850
Short name T367
Test name
Test status
Simulation time 141861053 ps
CPU time 0.94 seconds
Started Jul 11 04:55:26 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 198264 kb
Host smart-afff8b9b-1f2b-446b-a422-ebec2a5664f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102108850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1102108850
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.3799149554
Short name T509
Test name
Test status
Simulation time 45970532 ps
CPU time 0.66 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:39 PM PDT 24
Peak memory 198840 kb
Host smart-77908877-d985-406f-9b18-6a7962be9fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799149554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3799149554
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1130123083
Short name T409
Test name
Test status
Simulation time 49851124 ps
CPU time 0.96 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:11 PM PDT 24
Peak memory 200508 kb
Host smart-2ee9295c-3d49-453e-a113-017ee198eac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130123083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1130123083
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.650484233
Short name T43
Test name
Test status
Simulation time 60583857 ps
CPU time 0.89 seconds
Started Jul 11 04:57:16 PM PDT 24
Finished Jul 11 04:57:24 PM PDT 24
Peak memory 198708 kb
Host smart-ee5d21b7-d486-46a1-8495-478b7313a397
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650484233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disa
ble_rom_integrity_check.650484233
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2433149867
Short name T976
Test name
Test status
Simulation time 29327239 ps
CPU time 0.63 seconds
Started Jul 11 04:57:11 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 197736 kb
Host smart-2c003fc4-69a5-41dd-ae92-0459b6bade05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433149867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.2433149867
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.285640058
Short name T699
Test name
Test status
Simulation time 299752754 ps
CPU time 1 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:22 PM PDT 24
Peak memory 197544 kb
Host smart-4ba6b305-6b66-4bc5-a911-c90d70903701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285640058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.285640058
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2693965470
Short name T707
Test name
Test status
Simulation time 52901913 ps
CPU time 0.61 seconds
Started Jul 11 04:57:08 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 197692 kb
Host smart-bd5ce47d-a66b-4a45-8180-2eff422823d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693965470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2693965470
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.4136311974
Short name T210
Test name
Test status
Simulation time 43161238 ps
CPU time 0.66 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 197640 kb
Host smart-d8d9adf7-44d8-4647-bf1a-2c08c8fd27ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136311974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.4136311974
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2108547293
Short name T154
Test name
Test status
Simulation time 42383762 ps
CPU time 0.77 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 201020 kb
Host smart-7b985b6d-76b9-4e36-8a7e-d0c0e0fbf7f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108547293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2108547293
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.1816031487
Short name T270
Test name
Test status
Simulation time 210137073 ps
CPU time 1.14 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 199044 kb
Host smart-fd3d6913-8549-4699-9360-dc102d1a09d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816031487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.1816031487
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.2161103855
Short name T527
Test name
Test status
Simulation time 52500921 ps
CPU time 0.66 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 197980 kb
Host smart-de2d44b9-3cf2-4f19-aa61-4a5866a57b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161103855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.2161103855
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2430165507
Short name T560
Test name
Test status
Simulation time 116174733 ps
CPU time 0.79 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 209248 kb
Host smart-8be16177-9eed-4900-87c1-2a9cd0c4e2aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430165507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2430165507
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.142836558
Short name T759
Test name
Test status
Simulation time 45311225 ps
CPU time 0.7 seconds
Started Jul 11 04:57:12 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 198308 kb
Host smart-5c15a73a-3e38-4ccb-bc57-fa5275f575cd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142836558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_c
m_ctrl_config_regwen.142836558
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4045186971
Short name T730
Test name
Test status
Simulation time 768202069 ps
CPU time 2.83 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 200876 kb
Host smart-05333094-29ec-4af2-b00b-549bce62b85d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045186971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4045186971
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2574773991
Short name T244
Test name
Test status
Simulation time 851740923 ps
CPU time 3.15 seconds
Started Jul 11 04:57:04 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 200780 kb
Host smart-ad5e9aa7-9cb2-448b-a171-8ac276515b8c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574773991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2574773991
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2332650720
Short name T256
Test name
Test status
Simulation time 51331779 ps
CPU time 0.97 seconds
Started Jul 11 04:57:06 PM PDT 24
Finished Jul 11 04:57:15 PM PDT 24
Peak memory 199004 kb
Host smart-32fbd74c-f6a4-4c22-828c-3f830e034005
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332650720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2332650720
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.3138168902
Short name T343
Test name
Test status
Simulation time 66087811 ps
CPU time 0.65 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 198208 kb
Host smart-9b39a666-0ca2-43d1-bbb2-5e7874bc91e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138168902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3138168902
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.3028599274
Short name T588
Test name
Test status
Simulation time 920639449 ps
CPU time 1.87 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 200864 kb
Host smart-7741042b-8541-46c1-997d-7601452e2c5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028599274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.3028599274
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.3220567987
Short name T685
Test name
Test status
Simulation time 8905746476 ps
CPU time 19.15 seconds
Started Jul 11 04:57:11 PM PDT 24
Finished Jul 11 04:57:41 PM PDT 24
Peak memory 200988 kb
Host smart-f23e831b-20cd-425b-8e35-b28f91fdbdf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220567987 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.3220567987
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.4260174590
Short name T664
Test name
Test status
Simulation time 118611552 ps
CPU time 0.82 seconds
Started Jul 11 04:57:03 PM PDT 24
Finished Jul 11 04:57:11 PM PDT 24
Peak memory 198160 kb
Host smart-35b34f2c-bb5d-4d14-b69b-ac149d7fd5c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260174590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.4260174590
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.4246843158
Short name T253
Test name
Test status
Simulation time 278745958 ps
CPU time 1.11 seconds
Started Jul 11 04:57:04 PM PDT 24
Finished Jul 11 04:57:12 PM PDT 24
Peak memory 200868 kb
Host smart-50b1fcba-3003-4bc5-95fd-8d49427961c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246843158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.4246843158
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1756780396
Short name T906
Test name
Test status
Simulation time 63612221 ps
CPU time 0.9 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:22 PM PDT 24
Peak memory 200020 kb
Host smart-474a9e8f-5f66-48e3-9e25-12a41748b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756780396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1756780396
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2414555608
Short name T611
Test name
Test status
Simulation time 70139279 ps
CPU time 0.62 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:22 PM PDT 24
Peak memory 197016 kb
Host smart-9c12ce05-22b1-459a-8c9a-3d0f11f5a501
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414555608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2414555608
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.3251948193
Short name T977
Test name
Test status
Simulation time 2143650565 ps
CPU time 0.95 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 198112 kb
Host smart-3d6cb86c-95c6-4676-aca4-025fc297eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251948193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.3251948193
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3352831204
Short name T267
Test name
Test status
Simulation time 58865286 ps
CPU time 0.7 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:32 PM PDT 24
Peak memory 196924 kb
Host smart-1c44bc43-410a-469f-8b92-2e2d805ad361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352831204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3352831204
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2479382608
Short name T734
Test name
Test status
Simulation time 81983326 ps
CPU time 0.67 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 197800 kb
Host smart-7d849b59-1eef-4692-9f17-1ef05a92598b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479382608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2479382608
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2011792082
Short name T278
Test name
Test status
Simulation time 41154336 ps
CPU time 0.69 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 200788 kb
Host smart-42d956cb-8d62-40f0-8ddc-74f2e7870e6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011792082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2011792082
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.706993615
Short name T295
Test name
Test status
Simulation time 80562703 ps
CPU time 0.8 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 198760 kb
Host smart-557d4581-e8e5-4481-b08a-2d67bb685006
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706993615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wa
keup_race.706993615
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2217558222
Short name T820
Test name
Test status
Simulation time 47076627 ps
CPU time 0.8 seconds
Started Jul 11 04:57:15 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 198484 kb
Host smart-3ad547d6-cece-473a-9bc3-572713b5ba73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217558222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2217558222
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.2128922460
Short name T259
Test name
Test status
Simulation time 152829002 ps
CPU time 0.85 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 200908 kb
Host smart-4b43af38-f244-4d98-8fa1-1fd607e22fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128922460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.2128922460
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.3951928018
Short name T60
Test name
Test status
Simulation time 239619943 ps
CPU time 0.79 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 198504 kb
Host smart-a7d01492-f001-4c01-8198-d0cfdde398ac
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951928018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.3951928018
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3137467016
Short name T829
Test name
Test status
Simulation time 917511211 ps
CPU time 2.77 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 200808 kb
Host smart-8d1c69d9-1c57-432a-ab7a-c83b639a51ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137467016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3137467016
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.498878549
Short name T405
Test name
Test status
Simulation time 1242931356 ps
CPU time 2.22 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 200792 kb
Host smart-ee867ae9-60af-48ce-a051-95ac26cf7251
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498878549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.498878549
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1413807199
Short name T162
Test name
Test status
Simulation time 109411656 ps
CPU time 0.89 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:32 PM PDT 24
Peak memory 198980 kb
Host smart-79ee5a0f-a0e1-4209-84ea-1206675a42a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413807199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1413807199
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3250693860
Short name T208
Test name
Test status
Simulation time 57573985 ps
CPU time 0.66 seconds
Started Jul 11 04:57:14 PM PDT 24
Finished Jul 11 04:57:22 PM PDT 24
Peak memory 199000 kb
Host smart-ca5fc562-73f6-4a4e-ae04-0f54d63a2384
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250693860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3250693860
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.3441100807
Short name T539
Test name
Test status
Simulation time 360614049 ps
CPU time 1.72 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 200828 kb
Host smart-4cba8123-e532-483c-9d62-b2aaf29bfe32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441100807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.3441100807
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.1304668550
Short name T69
Test name
Test status
Simulation time 8364474646 ps
CPU time 25.47 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 201064 kb
Host smart-38b35ba6-c6a2-41d7-ac97-076b922cca8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304668550 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.1304668550
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.3218584041
Short name T579
Test name
Test status
Simulation time 169224395 ps
CPU time 1.1 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 198628 kb
Host smart-969f9e51-3895-4101-a17a-86fbc9accbff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218584041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.3218584041
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.399936126
Short name T372
Test name
Test status
Simulation time 341651439 ps
CPU time 1.71 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 200672 kb
Host smart-93e764ab-76d1-4d80-827c-0b527abcce93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399936126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.399936126
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.3923292048
Short name T586
Test name
Test status
Simulation time 93007093 ps
CPU time 0.81 seconds
Started Jul 11 04:57:16 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 199612 kb
Host smart-776ce397-08eb-43c2-bace-c72e754f2c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923292048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3923292048
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.540115499
Short name T793
Test name
Test status
Simulation time 89347142 ps
CPU time 0.71 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 198872 kb
Host smart-5daa52a8-c21b-403e-9dcd-083a0305df48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540115499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.540115499
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3620342121
Short name T708
Test name
Test status
Simulation time 29902808 ps
CPU time 0.64 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 196912 kb
Host smart-744beee1-2dfe-4bdb-a625-447fd4dd4d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620342121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3620342121
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.2796241928
Short name T657
Test name
Test status
Simulation time 319966099 ps
CPU time 0.94 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 198068 kb
Host smart-6ef9239c-edb2-4706-b316-7d7b1488f2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796241928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2796241928
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2059804256
Short name T891
Test name
Test status
Simulation time 35977206 ps
CPU time 0.7 seconds
Started Jul 11 04:57:27 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 197796 kb
Host smart-8eb3cb42-94d6-4c64-b7de-13320c4e1e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059804256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2059804256
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.92912990
Short name T221
Test name
Test status
Simulation time 29262380 ps
CPU time 0.63 seconds
Started Jul 11 04:57:33 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 197972 kb
Host smart-fe0c9e4a-6f52-40b9-b8b8-32af4c3c1558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92912990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.92912990
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3614893894
Short name T2
Test name
Test status
Simulation time 51524347 ps
CPU time 0.71 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 201124 kb
Host smart-a558ed2d-244b-4c50-b35e-ee3057633de1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614893894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3614893894
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.273466365
Short name T410
Test name
Test status
Simulation time 158583635 ps
CPU time 0.77 seconds
Started Jul 11 04:57:26 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 198364 kb
Host smart-c49d83ab-5c86-438b-8c9a-88a9b2e9b6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273466365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wa
keup_race.273466365
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.1215162878
Short name T466
Test name
Test status
Simulation time 41815216 ps
CPU time 0.77 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 197960 kb
Host smart-723c547b-6168-4d20-9181-5a3ad84ae99b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215162878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1215162878
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2620576757
Short name T698
Test name
Test status
Simulation time 117794678 ps
CPU time 0.87 seconds
Started Jul 11 04:57:25 PM PDT 24
Finished Jul 11 04:57:34 PM PDT 24
Peak memory 209180 kb
Host smart-739588b3-6194-44f8-b6cb-5de77d81e085
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620576757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2620576757
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2717307436
Short name T875
Test name
Test status
Simulation time 141571462 ps
CPU time 0.92 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 198736 kb
Host smart-2975d3c9-0ee8-42ea-b2f1-f95219d629df
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717307436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2717307436
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.596451157
Short name T742
Test name
Test status
Simulation time 833420909 ps
CPU time 2.86 seconds
Started Jul 11 04:57:15 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 200804 kb
Host smart-912f3edf-d529-4881-8405-3c91ae1fe40a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596451157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.596451157
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3482299386
Short name T870
Test name
Test status
Simulation time 850063218 ps
CPU time 3.44 seconds
Started Jul 11 04:57:10 PM PDT 24
Finished Jul 11 04:57:21 PM PDT 24
Peak memory 200732 kb
Host smart-cecc619a-9108-46d9-81cf-8ffd025cf7e3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482299386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3482299386
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.4001531153
Short name T614
Test name
Test status
Simulation time 118143475 ps
CPU time 0.82 seconds
Started Jul 11 04:57:13 PM PDT 24
Finished Jul 11 04:57:20 PM PDT 24
Peak memory 199016 kb
Host smart-5620e2a0-b887-4b62-9d1a-9d9fabc086cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001531153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4001531153
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.1230908976
Short name T848
Test name
Test status
Simulation time 46495735 ps
CPU time 0.68 seconds
Started Jul 11 04:57:11 PM PDT 24
Finished Jul 11 04:57:19 PM PDT 24
Peak memory 198952 kb
Host smart-c35e9aaa-ba75-4fac-a035-364c352c8a93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230908976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1230908976
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.2043005753
Short name T450
Test name
Test status
Simulation time 928520873 ps
CPU time 3.51 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 200764 kb
Host smart-6a468464-b741-42b3-b6cc-5ef4cf39ab50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043005753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2043005753
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.572939845
Short name T761
Test name
Test status
Simulation time 4457786802 ps
CPU time 12.31 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:39 PM PDT 24
Peak memory 200980 kb
Host smart-1dd59e44-1950-4de9-86c3-7067c7f6de83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572939845 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.572939845
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.1401957799
Short name T288
Test name
Test status
Simulation time 93661499 ps
CPU time 0.68 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 197896 kb
Host smart-a2258f13-9991-4c59-8e3f-49bc021fe211
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401957799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.1401957799
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.2739964006
Short name T879
Test name
Test status
Simulation time 47092290 ps
CPU time 0.63 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:27 PM PDT 24
Peak memory 198784 kb
Host smart-e99dab72-0751-4b25-957c-f21af575bf9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739964006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.2739964006
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3102108826
Short name T974
Test name
Test status
Simulation time 31693422 ps
CPU time 0.62 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 198752 kb
Host smart-029aa09a-40c2-46af-a074-7a7464b8dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102108826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3102108826
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.1790701221
Short name T780
Test name
Test status
Simulation time 90427488 ps
CPU time 0.69 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 198316 kb
Host smart-b69ceb76-6562-4d0f-9221-ef922d4c6138
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790701221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.1790701221
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1279752228
Short name T687
Test name
Test status
Simulation time 33142476 ps
CPU time 0.64 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:32 PM PDT 24
Peak memory 197944 kb
Host smart-41401771-2162-40b6-bff2-ba87aeb2e7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279752228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.1279752228
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.667313201
Short name T12
Test name
Test status
Simulation time 636861084 ps
CPU time 0.98 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 197696 kb
Host smart-1f509af1-7cd9-4dd6-8f93-c64b5800f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667313201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.667313201
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.1033647232
Short name T363
Test name
Test status
Simulation time 75153059 ps
CPU time 0.65 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 197032 kb
Host smart-897c4191-07d0-453f-88fa-e576e5b2b7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033647232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1033647232
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.415187163
Short name T279
Test name
Test status
Simulation time 61961894 ps
CPU time 0.61 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 197572 kb
Host smart-7682c1f5-10aa-4421-9b56-d876dc4eb157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415187163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.415187163
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2148026392
Short name T435
Test name
Test status
Simulation time 40982076 ps
CPU time 0.71 seconds
Started Jul 11 04:57:32 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 201068 kb
Host smart-913efcd8-820f-4c47-b07a-4e7e4f7c8e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148026392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2148026392
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.3328741518
Short name T939
Test name
Test status
Simulation time 72511987 ps
CPU time 0.71 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 198756 kb
Host smart-7ecbe1f6-bc42-4996-b514-5a38fbd5079d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328741518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.3328741518
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.806072047
Short name T748
Test name
Test status
Simulation time 53903006 ps
CPU time 0.87 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 198836 kb
Host smart-acb51ab2-aa96-4092-92fa-a0157e73c263
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806072047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.806072047
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.105105412
Short name T247
Test name
Test status
Simulation time 107489645 ps
CPU time 1.06 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 201008 kb
Host smart-807b3f6e-7892-46ae-90be-d6389ca93736
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105105412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.105105412
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1438632744
Short name T850
Test name
Test status
Simulation time 251224919 ps
CPU time 1.15 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:29 PM PDT 24
Peak memory 199668 kb
Host smart-2b2d7d40-fcd4-4312-b79e-9f0518d9cb87
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438632744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.1438632744
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3332089504
Short name T413
Test name
Test status
Simulation time 1309707280 ps
CPU time 2 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 200704 kb
Host smart-043d16b6-ba87-4c13-83ce-191e6a9d5edf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332089504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3332089504
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2223015435
Short name T385
Test name
Test status
Simulation time 923691569 ps
CPU time 1.97 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:41 PM PDT 24
Peak memory 200740 kb
Host smart-93704b96-89df-4f9b-9934-c920c6b58dce
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223015435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2223015435
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2785836311
Short name T515
Test name
Test status
Simulation time 141019687 ps
CPU time 0.9 seconds
Started Jul 11 04:57:17 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 198820 kb
Host smart-9db8275c-94b5-4807-bc2d-b3a34f54abf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785836311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2785836311
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.4010200185
Short name T877
Test name
Test status
Simulation time 58344395 ps
CPU time 0.69 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 198240 kb
Host smart-ff6255ee-9627-438b-b61e-e779e1c04d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010200185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.4010200185
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2140425869
Short name T723
Test name
Test status
Simulation time 2925902766 ps
CPU time 4.68 seconds
Started Jul 11 04:57:27 PM PDT 24
Finished Jul 11 04:57:39 PM PDT 24
Peak memory 200904 kb
Host smart-460d63fb-735f-4092-a29a-644b6b558f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140425869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2140425869
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.1462097802
Short name T646
Test name
Test status
Simulation time 312961173 ps
CPU time 0.9 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 199160 kb
Host smart-5caf2dda-80dc-4ba1-9945-835b307d2413
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462097802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1462097802
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.444325360
Short name T495
Test name
Test status
Simulation time 53615286 ps
CPU time 0.7 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 198972 kb
Host smart-a6c1f4e8-b22d-47b6-a234-2c660fcdcdeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444325360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.444325360
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.3106135904
Short name T452
Test name
Test status
Simulation time 29857025 ps
CPU time 0.88 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 199992 kb
Host smart-84b8289a-756a-4c51-996a-fa98bc2973bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106135904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3106135904
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.1681684575
Short name T24
Test name
Test status
Simulation time 64182534 ps
CPU time 0.85 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:26 PM PDT 24
Peak memory 198808 kb
Host smart-25940fd3-c594-4717-ada7-c06dbea91aee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681684575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.1681684575
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1322780468
Short name T573
Test name
Test status
Simulation time 31374482 ps
CPU time 0.63 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:39 PM PDT 24
Peak memory 197644 kb
Host smart-0c9ae61c-2544-4507-a5b8-c915edc54e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322780468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1322780468
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2995510524
Short name T486
Test name
Test status
Simulation time 167576636 ps
CPU time 1 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:51 PM PDT 24
Peak memory 197732 kb
Host smart-fbb30c1b-61c8-46cf-9073-f251930a821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995510524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2995510524
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1761517808
Short name T414
Test name
Test status
Simulation time 153513287 ps
CPU time 0.6 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 197756 kb
Host smart-251f41ab-5f27-47d5-948a-f58a68bfcba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761517808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1761517808
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2065678412
Short name T415
Test name
Test status
Simulation time 88202021 ps
CPU time 0.6 seconds
Started Jul 11 04:57:40 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 198044 kb
Host smart-d9449b53-c4bb-4392-9308-45c9b3f6539a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065678412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2065678412
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2176173207
Short name T397
Test name
Test status
Simulation time 44415788 ps
CPU time 0.75 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:51 PM PDT 24
Peak memory 200928 kb
Host smart-83c94fb7-7ccf-4d43-99c5-e07ed4f677e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176173207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2176173207
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.3984081974
Short name T991
Test name
Test status
Simulation time 151182693 ps
CPU time 1.01 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 199380 kb
Host smart-4d0e41b1-5e72-4f67-9492-8d3b03703325
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984081974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.3984081974
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3069541864
Short name T806
Test name
Test status
Simulation time 102622701 ps
CPU time 0.83 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 198520 kb
Host smart-c57d349c-5187-43ae-a3a6-bfc91b52aeb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069541864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3069541864
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3294016678
Short name T662
Test name
Test status
Simulation time 107548054 ps
CPU time 1.09 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 208192 kb
Host smart-71d75538-1fb1-4018-88cd-fff3620044d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294016678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3294016678
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.1280425252
Short name T243
Test name
Test status
Simulation time 200500302 ps
CPU time 1.32 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 199540 kb
Host smart-3da2274f-3106-4c20-8828-bfee8dd5ca31
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280425252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.1280425252
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3966036368
Short name T818
Test name
Test status
Simulation time 994038512 ps
CPU time 2.48 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 200864 kb
Host smart-3b2f0673-f009-4f2a-ac70-a7fb525f884a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966036368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3966036368
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445590958
Short name T859
Test name
Test status
Simulation time 975182184 ps
CPU time 2.5 seconds
Started Jul 11 04:57:18 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 200860 kb
Host smart-471e6a97-c1ac-4f62-9ec5-b4f6eb6814c3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445590958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.445590958
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1322693252
Short name T648
Test name
Test status
Simulation time 110344187 ps
CPU time 0.9 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:45 PM PDT 24
Peak memory 199220 kb
Host smart-652a7cce-9364-4bf5-b4e1-d2ed510a7375
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322693252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1322693252
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1632668416
Short name T982
Test name
Test status
Simulation time 53027297 ps
CPU time 0.63 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 198232 kb
Host smart-9a579fe3-9440-4f0a-8fee-03653250fde2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632668416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1632668416
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.2408979188
Short name T772
Test name
Test status
Simulation time 2088740375 ps
CPU time 6.67 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 200868 kb
Host smart-195b03c2-cb41-46d1-bbbc-8f8aeee9920e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408979188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.2408979188
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.4129476251
Short name T28
Test name
Test status
Simulation time 8219540939 ps
CPU time 26.37 seconds
Started Jul 11 04:57:32 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 200956 kb
Host smart-e598e4c4-cf83-4f21-9a1e-3ea76ab7505d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129476251 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.4129476251
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.3801362846
Short name T847
Test name
Test status
Simulation time 336360680 ps
CPU time 0.94 seconds
Started Jul 11 04:57:25 PM PDT 24
Finished Jul 11 04:57:34 PM PDT 24
Peak memory 199448 kb
Host smart-2bcc452d-f851-4a79-b46b-e515a9b8ee3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801362846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3801362846
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.2835915423
Short name T153
Test name
Test status
Simulation time 60757379 ps
CPU time 0.75 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 198692 kb
Host smart-dba0cbc3-68a4-44a5-967e-21e1b5ea62bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835915423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.2835915423
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3725170455
Short name T701
Test name
Test status
Simulation time 33241117 ps
CPU time 0.71 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 198892 kb
Host smart-398a1a49-2fb1-4b8c-a931-38d60292fb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725170455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3725170455
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3929271350
Short name T292
Test name
Test status
Simulation time 111343210 ps
CPU time 0.74 seconds
Started Jul 11 04:57:19 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 198160 kb
Host smart-1e48e98b-7ad3-4ab1-9378-c14fb2adf079
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929271350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3929271350
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.681969120
Short name T338
Test name
Test status
Simulation time 57376299 ps
CPU time 0.59 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 197032 kb
Host smart-0b1d292d-1ba3-47ab-b2b1-e6f7c1a5e4e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681969120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_
malfunc.681969120
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1453998401
Short name T846
Test name
Test status
Simulation time 2116388560 ps
CPU time 0.93 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 197808 kb
Host smart-9607691a-4471-4d57-9b32-87a22353a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453998401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1453998401
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.330268558
Short name T319
Test name
Test status
Simulation time 70814068 ps
CPU time 0.62 seconds
Started Jul 11 04:57:27 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 197740 kb
Host smart-714309de-50a0-4300-989c-c978ac41b714
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330268558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.330268558
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.3550288016
Short name T351
Test name
Test status
Simulation time 23724426 ps
CPU time 0.61 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 197560 kb
Host smart-b758c4ee-5d7e-41a2-89fa-f4259502766f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550288016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3550288016
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2449951501
Short name T519
Test name
Test status
Simulation time 39530977 ps
CPU time 0.74 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 201088 kb
Host smart-88e40258-86fd-46c4-bbcf-8e869ea643aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449951501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2449951501
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.1478196992
Short name T320
Test name
Test status
Simulation time 392185057 ps
CPU time 0.86 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 199228 kb
Host smart-4215cfb1-4664-46e4-847e-41825147fd8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478196992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.1478196992
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.172168460
Short name T136
Test name
Test status
Simulation time 76463075 ps
CPU time 0.97 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 199596 kb
Host smart-2ceba4da-3878-4775-b859-23ae2e85752e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172168460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.172168460
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2934747107
Short name T216
Test name
Test status
Simulation time 119102343 ps
CPU time 0.86 seconds
Started Jul 11 04:57:25 PM PDT 24
Finished Jul 11 04:57:34 PM PDT 24
Peak memory 209116 kb
Host smart-9add48f5-2b60-4605-b40d-bf242bec7b7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934747107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2934747107
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.1165700507
Short name T718
Test name
Test status
Simulation time 185261042 ps
CPU time 0.8 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 198856 kb
Host smart-df667277-6d48-49be-aebe-25861fdb38bf
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165700507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.1165700507
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3055030121
Short name T884
Test name
Test status
Simulation time 1215404248 ps
CPU time 2.4 seconds
Started Jul 11 04:57:23 PM PDT 24
Finished Jul 11 04:57:34 PM PDT 24
Peak memory 200724 kb
Host smart-f03e61a9-d5bc-434c-8140-0494ad255be6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055030121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3055030121
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.263584818
Short name T893
Test name
Test status
Simulation time 923971970 ps
CPU time 2.99 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 200312 kb
Host smart-d0a6e339-6a58-47a2-9170-2d0b243b0d67
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263584818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.263584818
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1802202498
Short name T757
Test name
Test status
Simulation time 131218631 ps
CPU time 0.86 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 198916 kb
Host smart-0f877c09-c30b-4012-a5e7-ab4144fae761
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802202498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1802202498
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.679868012
Short name T493
Test name
Test status
Simulation time 30741009 ps
CPU time 0.68 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 198212 kb
Host smart-1ba7c9ed-83f5-4096-a6db-d5871d585768
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679868012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.679868012
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.1812762045
Short name T831
Test name
Test status
Simulation time 431209626 ps
CPU time 1.59 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 200908 kb
Host smart-c4ded58f-c084-44aa-82d9-965d59affc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812762045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1812762045
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3458593857
Short name T125
Test name
Test status
Simulation time 4895078667 ps
CPU time 15.3 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 200480 kb
Host smart-5017debb-fd88-4569-8c06-9b2552139627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458593857 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.3458593857
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.4262042135
Short name T679
Test name
Test status
Simulation time 115940154 ps
CPU time 0.72 seconds
Started Jul 11 04:57:27 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 198832 kb
Host smart-31f73f52-4b7d-499d-a46e-7ff427e17344
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262042135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.4262042135
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1444562702
Short name T398
Test name
Test status
Simulation time 68300448 ps
CPU time 0.73 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 199004 kb
Host smart-a88859af-899d-4af4-8d2f-10111b2a5365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444562702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1444562702
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2174307098
Short name T44
Test name
Test status
Simulation time 80094954 ps
CPU time 0.74 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 04:57:46 PM PDT 24
Peak memory 198556 kb
Host smart-2e46978d-7b4a-448f-a183-f183fe19c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174307098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2174307098
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.403513819
Short name T280
Test name
Test status
Simulation time 57813987 ps
CPU time 0.82 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 198856 kb
Host smart-adeee8f8-404d-4380-9ca5-ec79992c2a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403513819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.403513819
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3847488925
Short name T559
Test name
Test status
Simulation time 33820315 ps
CPU time 0.61 seconds
Started Jul 11 04:57:46 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 197724 kb
Host smart-35f5c0d9-a97a-4940-b0d6-2e8fb654223d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847488925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.3847488925
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3526919477
Short name T156
Test name
Test status
Simulation time 2468123021 ps
CPU time 0.99 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 198168 kb
Host smart-33c39593-5442-4eee-903c-a3176f017d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526919477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3526919477
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.1714998120
Short name T396
Test name
Test status
Simulation time 80590517 ps
CPU time 0.62 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 197004 kb
Host smart-e9ff5da6-368b-4000-a8b6-4d9716d2dd60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714998120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.1714998120
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.868930388
Short name T473
Test name
Test status
Simulation time 46187557 ps
CPU time 0.62 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 196892 kb
Host smart-dc05212d-d2e0-4298-92a9-a2e922892f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868930388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.868930388
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.557663317
Short name T914
Test name
Test status
Simulation time 158334491 ps
CPU time 0.68 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 200592 kb
Host smart-cb76bef9-88e9-4131-8354-9863cdf0368e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557663317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.557663317
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.680557735
Short name T549
Test name
Test status
Simulation time 149903282 ps
CPU time 0.79 seconds
Started Jul 11 04:57:45 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 198112 kb
Host smart-4ddce8dd-874a-4a54-ad97-5d6967993bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680557735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wa
keup_race.680557735
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1427492032
Short name T649
Test name
Test status
Simulation time 25396388 ps
CPU time 0.7 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 198760 kb
Host smart-170bdd64-e131-4ba9-a7c2-0c40f0847b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427492032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1427492032
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2470785374
Short name T514
Test name
Test status
Simulation time 111403215 ps
CPU time 0.82 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 200988 kb
Host smart-cdc56c96-e048-44f0-81d9-b82ca59392c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470785374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2470785374
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.22765564
Short name T640
Test name
Test status
Simulation time 44272438 ps
CPU time 0.71 seconds
Started Jul 11 04:57:52 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 198844 kb
Host smart-863957d3-fa3a-4769-82a5-1686c50d7d14
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22765564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm
_ctrl_config_regwen.22765564
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.889477024
Short name T402
Test name
Test status
Simulation time 944285150 ps
CPU time 2.36 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 200852 kb
Host smart-3a37ea1d-a08f-4f66-a5b5-00d84fa01b62
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889477024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.889477024
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4136549994
Short name T89
Test name
Test status
Simulation time 748389883 ps
CPU time 2.7 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:49 PM PDT 24
Peak memory 200868 kb
Host smart-c80561e7-1388-49f1-8da5-ba2775bd6d32
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136549994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4136549994
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2824963761
Short name T760
Test name
Test status
Simulation time 69242279 ps
CPU time 0.95 seconds
Started Jul 11 04:57:21 PM PDT 24
Finished Jul 11 04:57:30 PM PDT 24
Peak memory 198940 kb
Host smart-71d1d558-3055-426a-83c4-01afe9d2477d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824963761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2824963761
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.4196403684
Short name T212
Test name
Test status
Simulation time 60585732 ps
CPU time 0.63 seconds
Started Jul 11 04:57:27 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 198208 kb
Host smart-d01278e5-052a-4782-9e1b-55fcc1831555
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196403684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.4196403684
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.3593185995
Short name T101
Test name
Test status
Simulation time 1683358751 ps
CPU time 6.44 seconds
Started Jul 11 04:57:31 PM PDT 24
Finished Jul 11 04:57:46 PM PDT 24
Peak memory 200876 kb
Host smart-678c0643-1b8a-40e4-850c-160a3331c4c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593185995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.3593185995
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3569720230
Short name T75
Test name
Test status
Simulation time 12815354570 ps
CPU time 38.88 seconds
Started Jul 11 04:57:35 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 201056 kb
Host smart-f9860a69-1441-401b-964a-c24f42224ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569720230 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.3569720230
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.115143884
Short name T737
Test name
Test status
Simulation time 257107873 ps
CPU time 1.31 seconds
Started Jul 11 04:57:45 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 200624 kb
Host smart-8b0785a0-0a8b-4902-be4b-6733ff1b994d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115143884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.115143884
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.3670649357
Short name T330
Test name
Test status
Simulation time 101050706 ps
CPU time 0.77 seconds
Started Jul 11 04:57:45 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 198788 kb
Host smart-1e9bd3d2-3081-469b-bd1f-d620daf3cf6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670649357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.3670649357
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.547826751
Short name T491
Test name
Test status
Simulation time 30562524 ps
CPU time 0.96 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:49 PM PDT 24
Peak memory 200452 kb
Host smart-ea2d3658-70d9-4dfa-a5e7-339014bb3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547826751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.547826751
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.733583064
Short name T184
Test name
Test status
Simulation time 118352017 ps
CPU time 0.72 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 198320 kb
Host smart-82d3f69e-7317-46aa-89ab-9fceb415f5c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733583064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disa
ble_rom_integrity_check.733583064
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.859381868
Short name T173
Test name
Test status
Simulation time 31187866 ps
CPU time 0.62 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:45 PM PDT 24
Peak memory 197684 kb
Host smart-0dc0c891-4ec5-48c4-9063-8cc3aa4c7936
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859381868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.859381868
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.432935092
Short name T700
Test name
Test status
Simulation time 1373313733 ps
CPU time 0.94 seconds
Started Jul 11 04:57:34 PM PDT 24
Finished Jul 11 04:57:42 PM PDT 24
Peak memory 197392 kb
Host smart-7ef87003-b78f-40a4-b79c-82a519be7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432935092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.432935092
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.3379241863
Short name T909
Test name
Test status
Simulation time 29208991 ps
CPU time 0.65 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 197816 kb
Host smart-bebe045d-f4d7-4614-b3a0-fde98ee1f1a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379241863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3379241863
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.49244450
Short name T490
Test name
Test status
Simulation time 49261990 ps
CPU time 0.64 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 198112 kb
Host smart-0d5e9670-3fed-48d3-9d93-0bb6199b224a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49244450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.49244450
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.4267457949
Short name T140
Test name
Test status
Simulation time 81490382 ps
CPU time 0.69 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:45 PM PDT 24
Peak memory 201004 kb
Host smart-31124868-7a70-4395-8181-07778ccb122b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267457949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.4267457949
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.3318134362
Short name T964
Test name
Test status
Simulation time 192168070 ps
CPU time 1.09 seconds
Started Jul 11 04:57:35 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 199324 kb
Host smart-945af8a9-d9c8-4a4c-975f-7e90c4c78719
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318134362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.3318134362
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.1807350022
Short name T959
Test name
Test status
Simulation time 53983698 ps
CPU time 0.9 seconds
Started Jul 11 04:57:35 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 198856 kb
Host smart-ca63c93a-8e46-40ae-b408-7c614b345b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807350022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1807350022
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.438180124
Short name T663
Test name
Test status
Simulation time 103024569 ps
CPU time 0.92 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 209136 kb
Host smart-96535fa4-663a-4571-8c64-d0cb85846de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438180124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.438180124
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1961203366
Short name T291
Test name
Test status
Simulation time 170189340 ps
CPU time 0.79 seconds
Started Jul 11 04:57:25 PM PDT 24
Finished Jul 11 04:57:34 PM PDT 24
Peak memory 198340 kb
Host smart-671437bf-02e3-4a47-aea6-ec823079a08e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961203366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.1961203366
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3775693310
Short name T9
Test name
Test status
Simulation time 822386369 ps
CPU time 2.81 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 200868 kb
Host smart-949a3fb2-94ed-4084-901b-e3ef2773ff20
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775693310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3775693310
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.518806531
Short name T371
Test name
Test status
Simulation time 1491297307 ps
CPU time 2.17 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:40 PM PDT 24
Peak memory 200800 kb
Host smart-362fb826-c50d-4b0d-a086-c1ee70c26039
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518806531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.518806531
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.621627701
Short name T656
Test name
Test status
Simulation time 75639127 ps
CPU time 0.95 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:39 PM PDT 24
Peak memory 198944 kb
Host smart-154e61ef-fbee-4581-95be-affac4098d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621627701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_
mubi.621627701
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1928955529
Short name T535
Test name
Test status
Simulation time 33651644 ps
CPU time 0.68 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 198188 kb
Host smart-5d6d9ca3-5031-4107-94dc-3231501d1224
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928955529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1928955529
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.3872084961
Short name T252
Test name
Test status
Simulation time 433394796 ps
CPU time 1.77 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:45 PM PDT 24
Peak memory 200884 kb
Host smart-59bc9caf-922f-4d4f-a18e-3ad2c94e8acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872084961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3872084961
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.351443649
Short name T126
Test name
Test status
Simulation time 8126903247 ps
CPU time 29.64 seconds
Started Jul 11 04:57:25 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 201280 kb
Host smart-8c60af85-f004-4bec-93a1-f55f3148d635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351443649 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.351443649
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.1066310446
Short name T434
Test name
Test status
Simulation time 243561729 ps
CPU time 1.16 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 199436 kb
Host smart-f0a865f6-5cd8-4b32-b116-9d5aa20086ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066310446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.1066310446
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.4277196939
Short name T800
Test name
Test status
Simulation time 132414445 ps
CPU time 0.81 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 199064 kb
Host smart-e61dd9e2-756f-4249-bf01-ea1d39bc4913
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277196939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.4277196939
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2918949776
Short name T747
Test name
Test status
Simulation time 29030379 ps
CPU time 0.94 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 200492 kb
Host smart-42a526a4-8976-4585-afa9-100b8a5783a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918949776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2918949776
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1776752159
Short name T263
Test name
Test status
Simulation time 65024456 ps
CPU time 0.77 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 198796 kb
Host smart-25f41d40-ba4f-41ab-b82e-fbf95c764be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776752159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1776752159
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1054376160
Short name T796
Test name
Test status
Simulation time 52859612 ps
CPU time 0.59 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:57:57 PM PDT 24
Peak memory 197020 kb
Host smart-3a70bc9e-7510-410c-97aa-654cd464c07c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054376160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.1054376160
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1175474091
Short name T424
Test name
Test status
Simulation time 176747701 ps
CPU time 0.96 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 197700 kb
Host smart-5f259e55-6317-4ab9-b602-98a2386bca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175474091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1175474091
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3825313026
Short name T937
Test name
Test status
Simulation time 81053199 ps
CPU time 0.6 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 196244 kb
Host smart-f783e7fc-d737-4335-acd9-d52d9d24bdb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825313026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3825313026
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3704329986
Short name T797
Test name
Test status
Simulation time 55005522 ps
CPU time 0.62 seconds
Started Jul 11 04:57:32 PM PDT 24
Finished Jul 11 04:57:41 PM PDT 24
Peak memory 197784 kb
Host smart-b28fa66a-9003-47e3-bf24-268fc2678adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704329986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3704329986
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1104638253
Short name T712
Test name
Test status
Simulation time 55741244 ps
CPU time 0.66 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 201068 kb
Host smart-7f7128fd-3c42-4c76-9b41-51df75476365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104638253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1104638253
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.1695291374
Short name T651
Test name
Test status
Simulation time 158470019 ps
CPU time 0.75 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 198128 kb
Host smart-3ffdc665-0d74-4587-8ffb-ccd0e32189c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695291374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.1695291374
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.444440994
Short name T997
Test name
Test status
Simulation time 39454127 ps
CPU time 0.69 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 198792 kb
Host smart-8ab30262-bce9-4c30-88aa-4d5dfa662941
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444440994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.444440994
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.574459139
Short name T958
Test name
Test status
Simulation time 152456269 ps
CPU time 0.81 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 209276 kb
Host smart-c730257c-47d8-4d44-b4fb-16e92fdfe7c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574459139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.574459139
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.704175291
Short name T359
Test name
Test status
Simulation time 116694780 ps
CPU time 0.69 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 198228 kb
Host smart-b22f1e7f-5ae1-4781-be8c-4a751e416f82
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704175291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_c
m_ctrl_config_regwen.704175291
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.325513606
Short name T354
Test name
Test status
Simulation time 960031319 ps
CPU time 2.46 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 200712 kb
Host smart-07a283f2-d4ce-4d70-9379-ce4bccbb8490
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325513606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.325513606
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2521659322
Short name T756
Test name
Test status
Simulation time 844131637 ps
CPU time 3.05 seconds
Started Jul 11 04:57:26 PM PDT 24
Finished Jul 11 04:57:37 PM PDT 24
Peak memory 200648 kb
Host smart-bc398409-704f-4aad-ae9d-c99d8bfe921d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521659322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2521659322
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3671339106
Short name T411
Test name
Test status
Simulation time 63845102 ps
CPU time 0.91 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 199064 kb
Host smart-98d42223-7ce7-4966-94f3-2a74cc5ad859
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671339106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3671339106
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.2972254375
Short name T334
Test name
Test status
Simulation time 43375504 ps
CPU time 0.72 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:57:37 PM PDT 24
Peak memory 198212 kb
Host smart-8c458b6d-3e29-4555-92a4-0242169d9551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972254375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.2972254375
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.1436207161
Short name T447
Test name
Test status
Simulation time 1293551436 ps
CPU time 1.6 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 200884 kb
Host smart-8f4a665d-7f0b-4872-9ee5-d28ff91ebaa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436207161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1436207161
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.675113600
Short name T145
Test name
Test status
Simulation time 8080573330 ps
CPU time 26.3 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:58 PM PDT 24
Peak memory 201080 kb
Host smart-1fb8ab67-1aab-4079-a349-ab4bfcd6f350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675113600 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.675113600
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.2049949009
Short name T377
Test name
Test status
Simulation time 194923338 ps
CPU time 0.87 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 199392 kb
Host smart-900cac48-2bb8-4b81-930d-e503aaafb97e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049949009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2049949009
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.912713260
Short name T283
Test name
Test status
Simulation time 102788542 ps
CPU time 0.7 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 198716 kb
Host smart-b9a51694-7e3a-4873-abb4-7cc5216f1e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912713260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.912713260
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.3584150498
Short name T987
Test name
Test status
Simulation time 51163118 ps
CPU time 0.93 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 200128 kb
Host smart-ea747733-955b-4f90-b61f-ef32b3312504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584150498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.3584150498
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2807113829
Short name T23
Test name
Test status
Simulation time 60800034 ps
CPU time 0.79 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:57:57 PM PDT 24
Peak memory 198808 kb
Host smart-1cc52191-dc47-479b-999c-fa6e137de2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807113829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2807113829
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1118658051
Short name T395
Test name
Test status
Simulation time 30267553 ps
CPU time 0.64 seconds
Started Jul 11 04:57:26 PM PDT 24
Finished Jul 11 04:57:35 PM PDT 24
Peak memory 197736 kb
Host smart-a2d8f8a5-af29-483d-86de-67fdebbcdc1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118658051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1118658051
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.700762832
Short name T370
Test name
Test status
Simulation time 359267380 ps
CPU time 0.92 seconds
Started Jul 11 04:57:53 PM PDT 24
Finished Jul 11 04:58:03 PM PDT 24
Peak memory 198112 kb
Host smart-dc8eaac4-7557-44ca-868c-3be2ed75fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700762832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.700762832
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.122398557
Short name T543
Test name
Test status
Simulation time 47111295 ps
CPU time 0.73 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:57:37 PM PDT 24
Peak memory 197804 kb
Host smart-776bea1c-6585-4520-a4df-b621f6257c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122398557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.122398557
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.419320670
Short name T953
Test name
Test status
Simulation time 80358702 ps
CPU time 0.6 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 197988 kb
Host smart-a990e58c-a48e-4cbf-b82b-9bb4cfc4bcad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419320670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.419320670
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.995110420
Short name T871
Test name
Test status
Simulation time 74638637 ps
CPU time 0.68 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 200940 kb
Host smart-d022a539-a18a-4316-9492-698c802ed28e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995110420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invali
d.995110420
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.184409060
Short name T788
Test name
Test status
Simulation time 424597194 ps
CPU time 0.95 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:57:57 PM PDT 24
Peak memory 199296 kb
Host smart-9e93c9ea-4812-4496-9214-0df5f2b597f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184409060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wa
keup_race.184409060
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2380828241
Short name T750
Test name
Test status
Simulation time 29200535 ps
CPU time 0.63 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 198832 kb
Host smart-f33b87b0-9df2-4414-ab2e-210d3c677dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380828241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2380828241
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2842131716
Short name T650
Test name
Test status
Simulation time 106368677 ps
CPU time 0.92 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 208484 kb
Host smart-00dd94e3-92e8-4989-b961-bfbcb433f6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842131716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2842131716
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.643228848
Short name T508
Test name
Test status
Simulation time 208446155 ps
CPU time 1.12 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 200484 kb
Host smart-ff30889b-a206-4c49-a9b8-5b14c5114c31
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643228848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_c
m_ctrl_config_regwen.643228848
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.357090690
Short name T470
Test name
Test status
Simulation time 767380405 ps
CPU time 2.73 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:46 PM PDT 24
Peak memory 200572 kb
Host smart-4d03c138-06b4-4a14-9f7d-d99db8eb3822
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357090690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.357090690
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1193946886
Short name T520
Test name
Test status
Simulation time 856126818 ps
CPU time 2.39 seconds
Started Jul 11 04:57:22 PM PDT 24
Finished Jul 11 04:57:33 PM PDT 24
Peak memory 200796 kb
Host smart-d8d207e1-f38a-40fe-9b6f-c32b8572cf68
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193946886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1193946886
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.4068805040
Short name T755
Test name
Test status
Simulation time 86637780 ps
CPU time 0.83 seconds
Started Jul 11 04:57:28 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 198916 kb
Host smart-bd02df1a-820e-47a3-9dec-25cd6b610c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068805040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4068805040
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2422638679
Short name T150
Test name
Test status
Simulation time 65119022 ps
CPU time 0.64 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 198144 kb
Host smart-0e18fcc2-4680-4269-b2e0-c7ce71d23a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422638679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2422638679
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.2828906624
Short name T789
Test name
Test status
Simulation time 3013584314 ps
CPU time 2.12 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:58 PM PDT 24
Peak memory 200940 kb
Host smart-aa2c82ec-4d47-4f0b-a254-330f67a234f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828906624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2828906624
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.1509744310
Short name T132
Test name
Test status
Simulation time 6722938030 ps
CPU time 21.07 seconds
Started Jul 11 04:57:26 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 201008 kb
Host smart-57810ddd-c845-49a7-8dd1-6d8ad24eee47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509744310 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.1509744310
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.3137276447
Short name T641
Test name
Test status
Simulation time 269742394 ps
CPU time 1.06 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:57:38 PM PDT 24
Peak memory 199220 kb
Host smart-fb43f023-98ba-4a07-aac5-99cbaae351fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137276447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.3137276447
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.241215876
Short name T936
Test name
Test status
Simulation time 60828376 ps
CPU time 0.68 seconds
Started Jul 11 04:57:24 PM PDT 24
Finished Jul 11 04:57:32 PM PDT 24
Peak memory 198016 kb
Host smart-4ccce34a-7142-4f40-ab85-097cd757b80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241215876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.241215876
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.4096357040
Short name T333
Test name
Test status
Simulation time 106504677 ps
CPU time 0.79 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 199784 kb
Host smart-9138ec87-8544-4976-9210-8110af364e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096357040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.4096357040
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3127903081
Short name T670
Test name
Test status
Simulation time 171228912 ps
CPU time 0.7 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 198340 kb
Host smart-d4c5912a-c8d7-4df1-9664-70798e988b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127903081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.3127903081
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2962623946
Short name T880
Test name
Test status
Simulation time 29440969 ps
CPU time 0.63 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 197732 kb
Host smart-4f915884-cafe-4778-82c3-0ac34f09f5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962623946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.2962623946
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2010385536
Short name T787
Test name
Test status
Simulation time 319871278 ps
CPU time 0.97 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 197756 kb
Host smart-f8b79a34-f515-41f3-a944-690bc7b24d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010385536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2010385536
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3480643909
Short name T619
Test name
Test status
Simulation time 59894507 ps
CPU time 0.59 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 197720 kb
Host smart-08a4dddd-8a6f-436a-9353-bd9366639fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480643909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3480643909
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1706820299
Short name T443
Test name
Test status
Simulation time 68585672 ps
CPU time 0.59 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 197780 kb
Host smart-e1dc493d-11a1-40b0-9529-744dfb021019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706820299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1706820299
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.338629563
Short name T584
Test name
Test status
Simulation time 197251389 ps
CPU time 0.72 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 200952 kb
Host smart-002c5f2b-ac6b-4186-9113-9ffbdacf7695
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338629563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.338629563
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.1578723659
Short name T88
Test name
Test status
Simulation time 345541493 ps
CPU time 1.01 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:38 PM PDT 24
Peak memory 199488 kb
Host smart-a76a1ecb-323d-437e-97d9-bd9daa20f45f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578723659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.1578723659
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.856118139
Short name T682
Test name
Test status
Simulation time 263539364 ps
CPU time 0.81 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 198684 kb
Host smart-05177124-8f22-49ad-a08e-334d36bf90be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856118139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.856118139
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1490371349
Short name T260
Test name
Test status
Simulation time 227917304 ps
CPU time 0.78 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 209216 kb
Host smart-8ce97fb5-9ee7-4508-a700-afb2980e89d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490371349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1490371349
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3019365422
Short name T403
Test name
Test status
Simulation time 208059569 ps
CPU time 0.79 seconds
Started Jul 11 04:55:27 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 198172 kb
Host smart-e189ae15-1b1e-47a2-ba7e-fc8327e97414
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019365422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.3019365422
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2371883444
Short name T478
Test name
Test status
Simulation time 1195128306 ps
CPU time 2.12 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 200696 kb
Host smart-88ae5920-e52e-4dd5-87ca-4674b42b6b2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371883444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2371883444
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3652622339
Short name T287
Test name
Test status
Simulation time 1743450476 ps
CPU time 2.18 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 200772 kb
Host smart-65ece48a-7437-4f09-aa6a-6217f9ec8097
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652622339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3652622339
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3905763767
Short name T394
Test name
Test status
Simulation time 65485827 ps
CPU time 0.92 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 198804 kb
Host smart-093730c4-5662-48d6-bcb8-96a50ca8ccf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905763767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3905763767
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1316744636
Short name T969
Test name
Test status
Simulation time 30098795 ps
CPU time 0.67 seconds
Started Jul 11 04:55:31 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 198196 kb
Host smart-5b760957-832f-4197-992e-0c83543a31d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316744636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1316744636
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.1277827294
Short name T580
Test name
Test status
Simulation time 801550357 ps
CPU time 2.96 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:45 PM PDT 24
Peak memory 200912 kb
Host smart-10a62f9a-f8ca-4cba-a728-c943602f7465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277827294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.1277827294
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1268057224
Short name T84
Test name
Test status
Simulation time 9833037778 ps
CPU time 23.61 seconds
Started Jul 11 04:55:31 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 201104 kb
Host smart-db372d8f-8258-4747-a98b-b70f5b76b748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268057224 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.1268057224
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.2971998759
Short name T981
Test name
Test status
Simulation time 51566913 ps
CPU time 0.74 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 197744 kb
Host smart-36ae423b-9722-4098-9310-6647701733f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971998759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.2971998759
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.2833276807
Short name T321
Test name
Test status
Simulation time 194683005 ps
CPU time 1.16 seconds
Started Jul 11 04:55:30 PM PDT 24
Finished Jul 11 04:55:38 PM PDT 24
Peak memory 199456 kb
Host smart-494b6d9f-64bc-4f99-ba79-c47bb1c11e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833276807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.2833276807
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3675541053
Short name T389
Test name
Test status
Simulation time 30891796 ps
CPU time 0.79 seconds
Started Jul 11 04:55:31 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 198484 kb
Host smart-ed7b1986-0169-456c-93b5-1a3741d6b9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675541053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3675541053
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1372878200
Short name T326
Test name
Test status
Simulation time 69227885 ps
CPU time 0.67 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 198188 kb
Host smart-16ed8716-55b5-453a-acc3-5e2df4d95e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372878200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1372878200
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2288019675
Short name T181
Test name
Test status
Simulation time 28402749 ps
CPU time 0.63 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 197724 kb
Host smart-88df8bd9-9bae-446d-a570-ba5bfc54f090
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288019675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2288019675
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.331253053
Short name T335
Test name
Test status
Simulation time 313961646 ps
CPU time 0.97 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 197836 kb
Host smart-57eab071-4a70-45c3-8f3f-aad38fbae1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331253053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.331253053
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.193242845
Short name T694
Test name
Test status
Simulation time 34997017 ps
CPU time 0.62 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 197756 kb
Host smart-9e87130f-8d77-4f63-8593-655875dad385
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193242845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.193242845
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1968044819
Short name T42
Test name
Test status
Simulation time 43857898 ps
CPU time 0.67 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 197752 kb
Host smart-31ef9f80-1045-41d3-866c-c1572d3d42cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968044819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1968044819
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1749325088
Short name T139
Test name
Test status
Simulation time 42312743 ps
CPU time 0.71 seconds
Started Jul 11 04:55:48 PM PDT 24
Finished Jul 11 04:55:55 PM PDT 24
Peak memory 201084 kb
Host smart-86100201-b0f0-45ac-8212-a44090548bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749325088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1749325088
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1472796194
Short name T791
Test name
Test status
Simulation time 151821654 ps
CPU time 1 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 198216 kb
Host smart-0fd54f2a-45e2-43cb-a757-cca717419033
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472796194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.1472796194
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1478379705
Short name T781
Test name
Test status
Simulation time 67105287 ps
CPU time 0.93 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 199872 kb
Host smart-03cd1166-0a58-4cc3-84b7-8b3e72976a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478379705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1478379705
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.250451835
Short name T671
Test name
Test status
Simulation time 213979740 ps
CPU time 0.83 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 209200 kb
Host smart-72059d6e-80b0-4368-bcc8-fc44db2886f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250451835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.250451835
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1573776555
Short name T86
Test name
Test status
Simulation time 245938088 ps
CPU time 0.85 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 199504 kb
Host smart-648ffb0f-d8a4-40bb-b298-7448eac48889
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573776555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.1573776555
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3179610285
Short name T186
Test name
Test status
Simulation time 1220618576 ps
CPU time 2.29 seconds
Started Jul 11 04:55:29 PM PDT 24
Finished Jul 11 04:55:38 PM PDT 24
Peak memory 200620 kb
Host smart-649c4379-d4a3-4f7a-9dc0-c625d024e65f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179610285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3179610285
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1714850658
Short name T182
Test name
Test status
Simulation time 1112660853 ps
CPU time 2.06 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 200768 kb
Host smart-a30e76b8-a40b-4a8f-888b-a5b8f7c6a575
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714850658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1714850658
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4037787098
Short name T881
Test name
Test status
Simulation time 142034277 ps
CPU time 0.82 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 198896 kb
Host smart-e834ef83-5d52-443e-9cb8-cf95eeb841df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037787098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4037787098
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3617788183
Short name T380
Test name
Test status
Simulation time 52910119 ps
CPU time 0.64 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 198236 kb
Host smart-0202a1a4-52e1-4f20-851f-89625d9a9466
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617788183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3617788183
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.3260104068
Short name T325
Test name
Test status
Simulation time 3344345595 ps
CPU time 4.44 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 200976 kb
Host smart-bdc2f301-9fc0-4a32-9c4c-ab2c246740f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260104068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3260104068
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.845673657
Short name T127
Test name
Test status
Simulation time 5024584051 ps
CPU time 7.2 seconds
Started Jul 11 04:55:38 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 201052 kb
Host smart-a0f74a56-39e0-4dae-90d5-2222a3dd5d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845673657 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.845673657
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.4028666685
Short name T225
Test name
Test status
Simulation time 220609730 ps
CPU time 1.15 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 199240 kb
Host smart-41ece339-de3e-4778-b739-13518ae0a24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028666685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.4028666685
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.241734868
Short name T273
Test name
Test status
Simulation time 326981819 ps
CPU time 1.44 seconds
Started Jul 11 04:55:58 PM PDT 24
Finished Jul 11 04:56:04 PM PDT 24
Peak memory 200596 kb
Host smart-38c941c9-d880-44dc-8463-080756c45d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241734868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.241734868
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2040176672
Short name T418
Test name
Test status
Simulation time 144567909 ps
CPU time 0.87 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 199744 kb
Host smart-31165807-16aa-4ab7-bb64-e96234b3b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040176672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2040176672
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3852398271
Short name T808
Test name
Test status
Simulation time 56598463 ps
CPU time 0.82 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 198864 kb
Host smart-dd62bb87-a43f-4ec7-9990-c31511575126
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852398271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.3852398271
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.4056536568
Short name T915
Test name
Test status
Simulation time 59597022 ps
CPU time 0.59 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 197628 kb
Host smart-a7c1ed6c-42a6-4dae-92a3-60c53e58cafa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056536568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.4056536568
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.1976576673
Short name T988
Test name
Test status
Simulation time 609310043 ps
CPU time 0.97 seconds
Started Jul 11 04:55:42 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 198120 kb
Host smart-95e837ad-61e5-46e5-b2c7-5abc7c0623ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976576673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1976576673
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.4036583091
Short name T911
Test name
Test status
Simulation time 55016908 ps
CPU time 0.63 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 197100 kb
Host smart-543fcc74-7320-4ed3-876b-c38b12ff5053
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036583091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.4036583091
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.2223012209
Short name T275
Test name
Test status
Simulation time 36919953 ps
CPU time 0.63 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 197664 kb
Host smart-3552ec7c-4d42-41bf-9142-1f3786e27fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223012209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2223012209
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1411484510
Short name T719
Test name
Test status
Simulation time 47980918 ps
CPU time 0.7 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 200676 kb
Host smart-f1a815f1-d695-42a1-9c3d-1a1ecc3bfe93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411484510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1411484510
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.2746434274
Short name T681
Test name
Test status
Simulation time 172118106 ps
CPU time 0.72 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 197888 kb
Host smart-5322c503-5507-420b-a366-286e6fc01787
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746434274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.2746434274
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.695455171
Short name T620
Test name
Test status
Simulation time 99001974 ps
CPU time 0.77 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 198716 kb
Host smart-8018d683-9863-467d-ab83-351166409293
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695455171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.695455171
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3028784804
Short name T524
Test name
Test status
Simulation time 107021893 ps
CPU time 1.09 seconds
Started Jul 11 04:55:43 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 209400 kb
Host smart-7bb50978-b899-4bc0-80c3-0ab371bacb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028784804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3028784804
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2411582656
Short name T575
Test name
Test status
Simulation time 345816887 ps
CPU time 1.03 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 199652 kb
Host smart-514a33cf-ead9-4ad4-8354-52099ac17c56
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411582656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.2411582656
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.672099711
Short name T864
Test name
Test status
Simulation time 727110151 ps
CPU time 2.76 seconds
Started Jul 11 04:55:47 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 200732 kb
Host smart-0cf75157-1f5b-4988-98cd-fb0f119780ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672099711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.672099711
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.115040621
Short name T426
Test name
Test status
Simulation time 819665060 ps
CPU time 3.33 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 200816 kb
Host smart-8eed5fb7-a20e-4ca3-b793-c4548997e49b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115040621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.115040621
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2026402858
Short name T951
Test name
Test status
Simulation time 74256048 ps
CPU time 0.93 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 199244 kb
Host smart-754a5f12-c633-44d3-82bc-1e6a1a2f70fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026402858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2026402858
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.608588724
Short name T474
Test name
Test status
Simulation time 33888910 ps
CPU time 0.69 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:45 PM PDT 24
Peak memory 198944 kb
Host smart-e83cfee2-5cdf-4d26-9ab9-55356d2ccfc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608588724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.608588724
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.2886970565
Short name T565
Test name
Test status
Simulation time 108633592 ps
CPU time 0.95 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 200512 kb
Host smart-eb532680-f210-48c7-8a7e-4347fcc1e3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886970565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.2886970565
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.643605926
Short name T358
Test name
Test status
Simulation time 6513873912 ps
CPU time 21.97 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:56:06 PM PDT 24
Peak memory 201064 kb
Host smart-af11e442-8047-4fd8-868b-c27fac4deada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643605926 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.643605926
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.3101372622
Short name T965
Test name
Test status
Simulation time 238842753 ps
CPU time 1.19 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 199264 kb
Host smart-4a011811-ff9b-467a-83c2-f7909b3f9459
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101372622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.3101372622
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.2073340731
Short name T79
Test name
Test status
Simulation time 120342923 ps
CPU time 0.74 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 198952 kb
Host smart-00ef9b24-38a5-4d72-825e-d70ef0a112b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073340731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2073340731
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.40892016
Short name T892
Test name
Test status
Simulation time 47694959 ps
CPU time 0.77 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 199788 kb
Host smart-b9c641c6-bf2a-4589-bb2b-4c95589bfe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40892016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.40892016
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1147123909
Short name T391
Test name
Test status
Simulation time 79043314 ps
CPU time 0.67 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 198252 kb
Host smart-a26ab1ad-9ec8-4180-801f-b063d7233568
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147123909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1147123909
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3138499562
Short name T175
Test name
Test status
Simulation time 29276609 ps
CPU time 0.65 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 197724 kb
Host smart-aa58d104-c7d3-4947-9e64-35210d4d6a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138499562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3138499562
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2300206433
Short name T726
Test name
Test status
Simulation time 160119642 ps
CPU time 0.97 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 198116 kb
Host smart-6558842c-9d62-410f-bf8c-ea93efcfe7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300206433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2300206433
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2538693229
Short name T15
Test name
Test status
Simulation time 29403043 ps
CPU time 0.64 seconds
Started Jul 11 04:55:43 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 197696 kb
Host smart-5d8cd12e-828e-4570-8e06-765016ffdffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538693229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2538693229
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.4171895909
Short name T807
Test name
Test status
Simulation time 86333336 ps
CPU time 0.65 seconds
Started Jul 11 04:55:43 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 197696 kb
Host smart-d5b462a0-104f-4f23-9c3d-6ad4e0a15f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171895909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.4171895909
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3179016478
Short name T986
Test name
Test status
Simulation time 89311698 ps
CPU time 0.69 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 201068 kb
Host smart-3e71dd1b-6ee6-48d8-aa4d-89ef80ba5136
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179016478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.3179016478
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.3841108550
Short name T268
Test name
Test status
Simulation time 356517041 ps
CPU time 0.96 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 199404 kb
Host smart-25cd69f0-9280-4b31-8037-2780373417d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841108550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.3841108550
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.3833598118
Short name T989
Test name
Test status
Simulation time 77187629 ps
CPU time 0.72 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 198792 kb
Host smart-090b89a6-18e6-4126-b50b-3ceac2d6d0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833598118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.3833598118
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.4259274519
Short name T897
Test name
Test status
Simulation time 179129609 ps
CPU time 0.85 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 209276 kb
Host smart-71343f8e-6374-49b7-a268-9075985bf838
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259274519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.4259274519
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3446206382
Short name T632
Test name
Test status
Simulation time 371322167 ps
CPU time 0.91 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 199748 kb
Host smart-2ae6bb48-0621-4ed8-9122-e53df5ea5484
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446206382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.3446206382
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3945700907
Short name T725
Test name
Test status
Simulation time 1155682763 ps
CPU time 2.26 seconds
Started Jul 11 04:55:33 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 200880 kb
Host smart-c3673b62-7343-4326-8ec1-158d1a776af7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945700907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3945700907
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.91656023
Short name T786
Test name
Test status
Simulation time 1020304689 ps
CPU time 2.56 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 200372 kb
Host smart-33031aef-c255-49ba-9649-4f33c5eddb9a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91656023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.91656023
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1822245738
Short name T416
Test name
Test status
Simulation time 75839744 ps
CPU time 0.98 seconds
Started Jul 11 04:55:42 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 198912 kb
Host smart-619a34a1-26bb-4145-8d9b-24cd368b6cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822245738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1822245738
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1263420630
Short name T318
Test name
Test status
Simulation time 64619080 ps
CPU time 0.65 seconds
Started Jul 11 04:55:44 PM PDT 24
Finished Jul 11 04:55:53 PM PDT 24
Peak memory 197988 kb
Host smart-f71f2111-aee3-4c0a-8540-793f74c244bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263420630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1263420630
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.1187020823
Short name T29
Test name
Test status
Simulation time 415848364 ps
CPU time 1.97 seconds
Started Jul 11 04:55:38 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 201080 kb
Host smart-e5150d22-d401-482e-a08a-d7beac0b648d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187020823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1187020823
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.3159317673
Short name T124
Test name
Test status
Simulation time 25744788739 ps
CPU time 11.52 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 200960 kb
Host smart-42934474-e14d-46b1-92d5-3d2f2669ecf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159317673 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.3159317673
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.4093608833
Short name T387
Test name
Test status
Simulation time 259107666 ps
CPU time 1.09 seconds
Started Jul 11 04:55:36 PM PDT 24
Finished Jul 11 04:55:45 PM PDT 24
Peak memory 199236 kb
Host smart-0efcb9a4-5fd9-4b0b-8650-c0f4dd421fc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093608833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.4093608833
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.3027631643
Short name T80
Test name
Test status
Simulation time 214501282 ps
CPU time 0.96 seconds
Started Jul 11 04:55:32 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 199980 kb
Host smart-95b62dae-3a35-4093-8cfd-74d5757d537c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027631643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3027631643
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3868073658
Short name T264
Test name
Test status
Simulation time 49911887 ps
CPU time 0.62 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 198244 kb
Host smart-74b53d3d-9335-4f15-8193-f90d2f7f8fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868073658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3868073658
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.1659564449
Short name T962
Test name
Test status
Simulation time 65567109 ps
CPU time 0.92 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 198808 kb
Host smart-63896833-1948-4756-8075-6397338154a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659564449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.1659564449
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3617728826
Short name T429
Test name
Test status
Simulation time 39359178 ps
CPU time 0.59 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 197740 kb
Host smart-2f3d4b74-c770-4e17-9c94-588714cdbba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617728826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3617728826
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2530000883
Short name T521
Test name
Test status
Simulation time 284652446 ps
CPU time 1.05 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 197804 kb
Host smart-fa3c3b62-aa9d-4f41-b963-9848b6de9ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530000883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2530000883
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2488274560
Short name T926
Test name
Test status
Simulation time 62909416 ps
CPU time 0.65 seconds
Started Jul 11 04:55:39 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 197804 kb
Host smart-55518d36-961c-4b75-8ebb-db4769bf2594
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488274560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2488274560
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.642021212
Short name T597
Test name
Test status
Simulation time 45630780 ps
CPU time 0.66 seconds
Started Jul 11 04:55:52 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 197664 kb
Host smart-0c4d8b13-c4e8-4385-9a2b-107b666ceb26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642021212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.642021212
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1678277591
Short name T577
Test name
Test status
Simulation time 45213746 ps
CPU time 0.79 seconds
Started Jul 11 04:55:53 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 201316 kb
Host smart-5279c26a-79fb-4f38-ab77-bc1561cd576f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678277591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.1678277591
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.1209220252
Short name T324
Test name
Test status
Simulation time 419675950 ps
CPU time 1.07 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 199360 kb
Host smart-9b5140f5-345f-4816-b2ad-7423d902b6a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209220252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.1209220252
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.835311846
Short name T776
Test name
Test status
Simulation time 43599152 ps
CPU time 0.78 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 198692 kb
Host smart-0525536a-5118-4572-8fe1-8e94eaaf2b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835311846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.835311846
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.16841485
Short name T483
Test name
Test status
Simulation time 110822930 ps
CPU time 1 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 209104 kb
Host smart-4e505cae-097b-47f8-847c-56c8cb42e620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16841485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.16841485
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.4058483446
Short name T618
Test name
Test status
Simulation time 80470683 ps
CPU time 0.77 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 198760 kb
Host smart-d19920aa-95fd-4ca6-9b3a-48770da245c5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058483446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.4058483446
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50771020
Short name T407
Test name
Test status
Simulation time 887842652 ps
CPU time 3.34 seconds
Started Jul 11 04:55:35 PM PDT 24
Finished Jul 11 04:55:47 PM PDT 24
Peak memory 200728 kb
Host smart-53e0034a-e525-4f28-99b9-b1e1867619e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50771020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50771020
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.279561770
Short name T855
Test name
Test status
Simulation time 898375442 ps
CPU time 2.51 seconds
Started Jul 11 04:55:46 PM PDT 24
Finished Jul 11 04:55:56 PM PDT 24
Peak memory 200776 kb
Host smart-904d1d32-4550-4879-add1-cdb6f1e51956
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279561770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.279561770
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2340772932
Short name T946
Test name
Test status
Simulation time 54075477 ps
CPU time 0.9 seconds
Started Jul 11 04:55:50 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 198816 kb
Host smart-efe92c2e-a4c5-494f-a275-6e4cfe5ca85d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340772932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2340772932
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.291306184
Short name T8
Test name
Test status
Simulation time 47781257 ps
CPU time 0.64 seconds
Started Jul 11 04:55:41 PM PDT 24
Finished Jul 11 04:55:51 PM PDT 24
Peak memory 199060 kb
Host smart-d9391a65-27b2-4c06-9ec5-e456621c44d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291306184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.291306184
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.835928418
Short name T451
Test name
Test status
Simulation time 3378040248 ps
CPU time 2.4 seconds
Started Jul 11 04:55:49 PM PDT 24
Finished Jul 11 04:55:58 PM PDT 24
Peak memory 200940 kb
Host smart-2f227149-2831-455b-8ef2-15b74adec1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835928418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.835928418
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1967982123
Short name T624
Test name
Test status
Simulation time 2510941929 ps
CPU time 10.39 seconds
Started Jul 11 04:55:40 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 201100 kb
Host smart-85396c88-2bd7-4a34-a6cd-0eed735cb8a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967982123 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.1967982123
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.3150478456
Short name T310
Test name
Test status
Simulation time 258719288 ps
CPU time 1.03 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 199532 kb
Host smart-a97e09ef-b4f3-4491-be69-dadbeda2d660
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150478456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.3150478456
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.575379089
Short name T272
Test name
Test status
Simulation time 64428865 ps
CPU time 0.62 seconds
Started Jul 11 04:55:37 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 197952 kb
Host smart-922974c2-048e-4180-82d9-57d55d60b5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575379089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.575379089
Directory /workspace/9.pwrmgr_wakeup_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%