Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31931

1

T1

46

T3

8

T4

93

auto[1]

30662

1

T1

54

T3

20

T4

90

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32174

1

T1

40

T3

18

T4

91

auto[1]

30419

1

T1

60

T3

10

T4

92

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30724

1

T1

60

T3

14

T4

87

auto[1]

31869

1

T1

40

T3

14

T4

96

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35332

1

T1

50

T3

14

T4

101

auto[1]

27261

1

T1

50

T3

14

T4

82

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30796

1

T1

46

T3

18

T4

87

auto[1]

31797

1

T1

54

T3

10

T4

96

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31951

1

T1

56

T3

16

T4

98

auto[1]

30642

1

T1

44

T3

12

T4

85

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1173

1

T1

2

T4

6

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

906

1

T1

2

T4

5

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1052

1

T4

3

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

818

1

T4

3

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1050

1

T1

1

T4

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

804

1

T1

1

T4

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1720

1

T1

2

T4

6

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1459

1

T1

2

T4

4

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1093

1

T4

3

T7

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

865

1

T4

2

T7

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1067

1

T1

1

T4

5

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

835

1

T1

1

T4

5

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1092

1

T1

2

T3

1

T4

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

829

1

T1

2

T3

1

T4

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1126

1

T10

1

T26

1

T32

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

839

1

T10

1

T26

1

T32

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1082

1

T4

2

T7

1

T26

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

834

1

T4

2

T7

1

T26

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1103

1

T1

2

T3

1

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

836

1

T1

2

T3

1

T4

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1027

1

T1

4

T3

1

T4

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

793

1

T1

4

T3

1

T4

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1113

1

T4

5

T7

1

T26

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

847

1

T4

4

T26

1

T32

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1052

1

T1

4

T4

4

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

797

1

T1

4

T4

4

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1058

1

T1

1

T3

1

T4

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T1

1

T3

1

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1099

1

T1

1

T4

3

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

850

1

T1

1

T4

2

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1082

1

T1

3

T4

3

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

824

1

T1

3

T4

2

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1121

1

T1

5

T4

3

T13

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

867

1

T1

5

T4

3

T26

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1063

1

T3

3

T4

3

T13

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

808

1

T3

3

T4

2

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1050

1

T1

2

T3

1

T4

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

803

1

T1

2

T3

1

T4

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1071

1

T1

1

T4

3

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

827

1

T1

1

T4

2

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1127

1

T1

1

T3

3

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

848

1

T1

1

T3

3

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1112

1

T4

5

T7

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

834

1

T4

2

T7

1

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1137

1

T1

2

T3

1

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

909

1

T1

2

T3

1

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1054

1

T1

1

T4

3

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

815

1

T1

1

T4

3

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1055

1

T1

3

T4

2

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

817

1

T1

3

T4

1

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1117

1

T1

1

T3

1

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

853

1

T1

1

T3

1

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1094

1

T1

1

T4

4

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

846

1

T1

1

T4

3

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1097

1

T1

4

T3

1

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

845

1

T1

4

T3

1

T4

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1089

1

T1

1

T4

2

T7

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

839

1

T1

1

T4

1

T7

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1062

1

T1

2

T4

3

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

807

1

T1

2

T4

2

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1002

1

T1

1

T4

5

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

774

1

T1

1

T4

4

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1092

1

T1

2

T4

6

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

827

1

T1

2

T4

6

T26

2