Group : pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 3 0 3 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
esc_reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 3 0 3 100.00 100 1 1 0


Summary for Variable esc_reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for esc_reset_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42252 1 T1 79 T2 2 T3 14
auto[1] 3677 1 T2 3 T4 2 T5 1


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18792 1 T1 29 T2 5 T4 43
auto[1] 27137 1 T1 50 T3 14 T4 82


Summary for Cross reset_cross

Samples crossed: esc_reset_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
esc_reset_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 15115 1 T1 29 T2 2 T4 41
auto[0] auto[1] 27137 1 T1 50 T3 14 T4 82
auto[1] auto[0] 3677 1 T2 3 T4 2 T5 1


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%