Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32294 1 T2 20 T4 770 T6 5
auto[1] 31037 1 T2 20 T4 904 T7 14


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32194 1 T2 18 T4 890 T6 2
auto[1] 31137 1 T2 22 T4 784 T6 3


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31051 1 T2 30 T4 814 T6 2
auto[1] 32280 1 T2 10 T4 860 T6 3


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35650 1 T2 20 T4 927 T6 5
auto[1] 27681 1 T2 20 T4 747 T7 18


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31095 1 T2 20 T4 821 T6 2
auto[1] 32236 1 T2 20 T4 853 T6 3


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32076 1 T2 14 T4 784 T6 2
auto[1] 31255 1 T2 26 T4 890 T6 3


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1061 1 T2 2 T4 22 T38 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 812 1 T2 2 T4 17 T25 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1013 1 T4 38 T20 6 T24 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 772 1 T4 30 T20 4 T24 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1055 1 T4 24 T56 2 T22 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 842 1 T4 21 T56 2 T22 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1769 1 T4 42 T6 1 T22 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1519 1 T4 36 T22 2 T23 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1116 1 T2 2 T4 21 T7 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 864 1 T2 2 T4 17 T7 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1087 1 T2 1 T4 38 T7 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 836 1 T2 1 T4 33 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1049 1 T2 1 T4 26 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 792 1 T2 1 T4 18 T7 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1119 1 T4 37 T6 1 T37 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 909 1 T4 27 T37 1 T23 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1218 1 T4 24 T6 1 T7 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 950 1 T4 18 T7 1 T25 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1068 1 T4 17 T7 2 T22 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 813 1 T4 12 T7 2 T22 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1151 1 T2 1 T4 16 T25 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 894 1 T2 1 T4 12 T25 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1076 1 T4 26 T22 1 T37 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 824 1 T4 17 T22 1 T37 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1044 1 T2 1 T4 33 T6 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 803 1 T2 1 T4 28 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1110 1 T4 17 T25 1 T22 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 833 1 T4 13 T25 1 T22 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1094 1 T2 1 T4 28 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 854 1 T2 1 T4 23 T7 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1096 1 T2 1 T4 22 T6 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 851 1 T2 1 T4 17 T7 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1121 1 T4 32 T7 1 T38 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 872 1 T4 30 T7 1 T38 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1108 1 T4 21 T25 1 T22 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 833 1 T4 18 T25 1 T22 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1013 1 T2 1 T4 24 T7 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 790 1 T2 1 T4 20 T7 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1048 1 T2 1 T4 28 T56 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 813 1 T2 1 T4 22 T56 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1121 1 T4 39 T22 2 T84 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 899 1 T4 36 T22 2 T84 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1160 1 T2 1 T4 33 T7 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 887 1 T2 1 T4 26 T7 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1114 1 T4 34 T7 1 T25 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 858 1 T4 28 T7 1 T25 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1098 1 T4 31 T22 3 T20 13
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 844 1 T4 21 T22 3 T20 10
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1044 1 T2 1 T4 26 T25 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 808 1 T2 1 T4 20 T25 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1131 1 T4 25 T38 1 T56 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 885 1 T4 22 T56 3 T22 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1098 1 T2 1 T4 40 T7 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 833 1 T2 1 T4 31 T7 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1038 1 T4 29 T7 1 T22 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 804 1 T4 24 T7 1 T22 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1087 1 T2 2 T4 28 T25 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 831 1 T2 2 T4 24 T25 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1086 1 T4 35 T13 1 T56 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 822 1 T4 28 T56 1 T22 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1119 1 T2 2 T4 29 T13 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 844 1 T2 2 T4 25 T22 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1138 1 T2 1 T4 42 T25 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 890 1 T2 1 T4 33 T25 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%