Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35342 1 T2 599 T4 6 T6 7
auto[1] 33474 1 T2 552 T4 10 T6 6


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35165 1 T2 619 T4 10 T6 6
auto[1] 33651 1 T2 532 T4 6 T6 7


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33488 1 T2 555 T4 12 T6 8
auto[1] 35328 1 T2 596 T4 4 T6 5


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 38872 1 T2 666 T4 8 T6 13
auto[1] 29944 1 T2 485 T4 8 T8 50


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33525 1 T2 590 T4 14 T6 9
auto[1] 35291 1 T2 561 T4 2 T6 4


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35176 1 T2 587 T4 2 T6 8
auto[1] 33640 1 T2 564 T4 14 T6 5


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1224 1 T2 19 T9 4 T12 9
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 921 1 T2 14 T9 4 T12 6
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1287 1 T2 24 T9 2 T33 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 1001 1 T2 16 T9 2 T33 4
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1161 1 T2 22 T8 2 T9 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 889 1 T2 17 T8 2 T9 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1928 1 T2 36 T9 1 T36 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1641 1 T2 28 T9 1 T36 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1182 1 T2 22 T8 2 T9 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 921 1 T2 16 T8 2 T9 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1172 1 T2 28 T4 1 T8 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 930 1 T2 23 T4 1 T8 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1215 1 T2 23 T6 1 T8 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 941 1 T2 15 T8 2 T9 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1232 1 T2 16 T8 1 T9 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 958 1 T2 12 T8 1 T9 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1164 1 T2 19 T4 1 T6 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 881 1 T2 14 T4 1 T8 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1186 1 T2 23 T6 2 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 909 1 T2 15 T8 1 T9 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1169 1 T2 15 T9 2 T33 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 904 1 T2 12 T9 2 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1215 1 T2 21 T6 1 T8 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 943 1 T2 15 T8 3 T9 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1131 1 T2 13 T4 1 T6 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 855 1 T2 11 T4 1 T8 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1182 1 T2 22 T6 1 T8 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 889 1 T2 16 T8 2 T9 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1219 1 T2 25 T8 1 T33 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 925 1 T2 15 T8 1 T33 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1216 1 T2 17 T8 1 T9 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 951 1 T2 15 T8 1 T9 3
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1167 1 T2 23 T6 2 T8 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 884 1 T2 20 T8 2 T9 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1177 1 T2 18 T8 3 T9 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 881 1 T2 14 T8 3 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1151 1 T2 25 T6 1 T8 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 884 1 T2 17 T8 1 T9 3
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1180 1 T2 14 T8 4 T9 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 913 1 T2 11 T8 4 T9 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1156 1 T2 27 T4 2 T6 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 888 1 T2 19 T4 2 T8 4
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1229 1 T2 21 T4 1 T6 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 898 1 T2 16 T4 1 T8 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1180 1 T2 25 T4 1 T8 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 934 1 T2 16 T4 1 T8 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1162 1 T2 15 T8 3 T9 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 878 1 T2 7 T8 3 T9 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1206 1 T2 13 T8 3 T9 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 917 1 T2 10 T8 3 T9 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1181 1 T2 29 T8 1 T33 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 869 1 T2 21 T8 1 T33 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1231 1 T2 16 T6 1 T8 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 955 1 T2 10 T8 1 T9 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1229 1 T2 21 T9 2 T33 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 928 1 T2 15 T9 2 T33 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1226 1 T2 14 T4 1 T8 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 937 1 T2 14 T4 1 T8 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1174 1 T2 23 T8 1 T9 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 900 1 T2 13 T8 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1157 1 T2 19 T9 2 T33 3
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 913 1 T2 15 T9 2 T33 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1183 1 T2 18 T8 3 T9 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 906 1 T2 13 T8 3 T9 2

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