Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33348

1

T1

18

T2

14

T4

8

auto[1]

32415

1

T1

12

T2

12

T4

24

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34156

1

T1

20

T2

10

T4

18

auto[1]

31607

1

T1

10

T2

16

T4

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32173

1

T1

14

T2

10

T4

16

auto[1]

33590

1

T1

16

T2

16

T4

16

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36666

1

T1

15

T2

13

T4

16

auto[1]

29097

1

T1

15

T2

13

T4

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32030

1

T1

16

T2

12

T4

22

auto[1]

33733

1

T1

14

T2

14

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33777

1

T1

20

T2

14

T4

18

auto[1]

31986

1

T1

10

T2

12

T4

14

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1097

1

T1

1

T8

4

T14

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

851

1

T1

1

T8

4

T14

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1163

1

T1

2

T2

1

T8

15

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

909

1

T1

2

T2

1

T8

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1132

1

T2

1

T4

1

T8

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

896

1

T2

1

T4

1

T8

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1829

1

T5

1

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1618

1

T5

1

T6

1

T8

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1149

1

T8

18

T14

4

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

906

1

T8

15

T14

4

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1089

1

T1

1

T7

2

T8

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

841

1

T1

1

T8

7

T14

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1093

1

T1

1

T8

6

T23

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

875

1

T1

1

T8

3

T23

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1159

1

T4

1

T8

12

T14

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

933

1

T4

1

T8

8

T14

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T2

1

T4

1

T8

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

866

1

T2

1

T4

1

T8

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1081

1

T8

10

T14

2

T16

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

838

1

T8

7

T14

2

T16

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1174

1

T1

1

T8

10

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

913

1

T1

1

T8

6

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1105

1

T1

2

T2

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

854

1

T1

2

T2

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1134

1

T7

1

T8

11

T14

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

897

1

T8

5

T14

3

T23

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1086

1

T2

1

T4

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

856

1

T2

1

T4

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1084

1

T1

1

T2

1

T8

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

862

1

T1

1

T2

1

T8

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1130

1

T2

1

T8

6

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

856

1

T2

1

T8

4

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1209

1

T1

3

T4

2

T8

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

972

1

T1

3

T4

2

T8

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1112

1

T2

1

T4

1

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

888

1

T2

1

T4

1

T8

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1180

1

T2

1

T7

1

T8

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

936

1

T2

1

T8

10

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1152

1

T1

1

T8

8

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

898

1

T1

1

T8

7

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1118

1

T4

1

T8

10

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

890

1

T4

1

T8

8

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1197

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

970

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1185

1

T4

1

T7

1

T8

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

917

1

T4

1

T8

4

T23

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1108

1

T4

1

T8

14

T23

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

884

1

T4

1

T8

11

T23

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1059

1

T2

1

T4

1

T8

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

834

1

T2

1

T4

1

T8

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1134

1

T4

2

T8

9

T14

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

906

1

T4

2

T8

8

T14

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1107

1

T4

1

T8

5

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

873

1

T4

1

T8

3

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1178

1

T8

9

T14

3

T23

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

941

1

T8

9

T14

3

T23

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1077

1

T8

7

T14

1

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

850

1

T8

4

T14

1

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1116

1

T4

1

T8

17

T14

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

863

1

T4

1

T8

13

T14

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1090

1

T8

6

T14

2

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

875

1

T8

1

T14

2

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1067

1

T1

1

T2

2

T8

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

829

1

T1

1

T2

2

T8

4