Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32673

1

T2

2

T5

80

T6

2

auto[1]

31915

1

T2

8

T5

64

T7

26

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33176

1

T2

2

T5

64

T6

2

auto[1]

31412

1

T2

8

T5

80

T7

16

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31437

1

T2

8

T5

63

T7

16

auto[1]

33151

1

T2

2

T5

81

T6

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35975

1

T2

5

T5

92

T6

1

auto[1]

28613

1

T2

5

T5

52

T6

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31564

1

T2

6

T5

50

T7

14

auto[1]

33024

1

T2

4

T5

94

T6

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33226

1

T2

2

T5

76

T6

2

auto[1]

31362

1

T2

8

T5

68

T7

26

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1140

1

T5

3

T9

8

T13

17

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

893

1

T5

1

T9

2

T13

12

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1089

1

T5

3

T8

1

T9

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

878

1

T5

2

T8

1

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1132

1

T5

2

T7

1

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

909

1

T5

1

T7

1

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1819

1

T5

2

T6

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1596

1

T5

2

T6

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1085

1

T5

1

T7

2

T9

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

882

1

T7

2

T9

6

T13

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1109

1

T5

4

T7

1

T9

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

863

1

T5

2

T7

1

T9

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1054

1

T5

6

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

823

1

T5

3

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1073

1

T5

2

T7

1

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

841

1

T5

1

T7

1

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1054

1

T5

4

T8

3

T9

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

848

1

T5

1

T8

3

T9

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1054

1

T5

2

T8

1

T9

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

834

1

T5

1

T8

1

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1095

1

T5

3

T8

1

T9

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

866

1

T5

1

T8

1

T9

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1130

1

T5

8

T8

1

T9

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

893

1

T5

6

T8

1

T9

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1053

1

T2

1

T5

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

829

1

T2

1

T5

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1038

1

T5

2

T8

1

T9

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

827

1

T5

1

T8

1

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1118

1

T5

3

T8

1

T9

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

885

1

T5

2

T8

1

T9

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1105

1

T5

5

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

858

1

T5

4

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1171

1

T5

2

T8

2

T9

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

898

1

T8

2

T9

7

T13

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1163

1

T5

1

T8

2

T9

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

933

1

T8

2

T9

6

T13

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1049

1

T5

5

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

829

1

T5

2

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1105

1

T5

4

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

881

1

T5

3

T7

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1069

1

T5

2

T8

3

T9

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

845

1

T5

1

T8

3

T9

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1114

1

T2

1

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

867

1

T2

1

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1132

1

T5

2

T7

1

T9

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

909

1

T5

1

T7

1

T9

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1123

1

T5

2

T7

2

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

902

1

T5

2

T7

2

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1066

1

T2

1

T5

4

T8

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

844

1

T2

1

T5

2

T8

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1150

1

T5

1

T7

1

T9

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

899

1

T7

1

T9

10

T13

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1095

1

T5

3

T7

1

T9

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

885

1

T5

2

T7

1

T9

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1139

1

T5

3

T7

2

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

889

1

T5

2

T7

2

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1163

1

T5

2

T7

1

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

934

1

T7

1

T8

3

T9

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1109

1

T5

2

T7

1

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

863

1

T5

2

T7

1

T8

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1053

1

T2

2

T5

1

T8

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

829

1

T2

2

T5

1

T8

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1126

1

T5

6

T7

1

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

881

1

T5

4

T7

1

T8

1