Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31773

1

T4

5

T6

10

T8

18

auto[1]

30514

1

T4

1

T6

9

T8

14

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31941

1

T6

14

T8

12

T13

250

auto[1]

30346

1

T4

6

T6

5

T8

20

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30543

1

T4

3

T6

4

T8

16

auto[1]

31744

1

T4

3

T6

15

T8

16

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35337

1

T4

4

T6

11

T8

16

auto[1]

26950

1

T4

2

T6

8

T8

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30680

1

T4

3

T6

9

T8

16

auto[1]

31607

1

T4

3

T6

10

T8

16

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31898

1

T4

3

T6

12

T8

18

auto[1]

30389

1

T4

3

T6

7

T8

14

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1065

1

T8

1

T13

5

T36

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

817

1

T8

1

T13

4

T36

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1087

1

T6

2

T8

1

T13

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

824

1

T6

2

T8

1

T13

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1103

1

T6

1

T13

8

T36

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

847

1

T13

6

T36

1

T21

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1799

1

T6

1

T13

19

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1539

1

T6

1

T13

14

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1013

1

T8

1

T13

12

T21

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

749

1

T8

1

T13

8

T21

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1051

1

T6

1

T8

1

T13

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

823

1

T6

1

T8

1

T13

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1083

1

T13

9

T36

1

T21

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

843

1

T13

6

T36

1

T21

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1070

1

T13

8

T21

3

T22

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

805

1

T13

1

T21

3

T22

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1100

1

T13

6

T21

1

T14

23

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

808

1

T13

1

T21

1

T14

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T4

1

T13

4

T36

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

803

1

T4

1

T13

2

T36

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1076

1

T8

3

T13

14

T21

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

805

1

T8

3

T13

8

T21

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1114

1

T6

1

T8

1

T13

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

827

1

T8

1

T13

5

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1090

1

T13

6

T36

1

T21

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

832

1

T13

2

T36

1

T21

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1080

1

T4

1

T8

1

T13

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

791

1

T8

1

T13

7

T21

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1122

1

T4

1

T13

10

T22

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

847

1

T4

1

T13

6

T22

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1082

1

T13

7

T36

1

T22

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

805

1

T13

5

T36

1

T22

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1104

1

T13

14

T36

1

T22

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

841

1

T13

8

T36

1

T22

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1129

1

T13

11

T36

1

T21

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

869

1

T13

7

T36

1

T21

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1061

1

T8

1

T13

5

T14

18

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

815

1

T8

1

T13

4

T14

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1059

1

T6

1

T13

11

T36

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

809

1

T6

1

T13

6

T36

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1125

1

T6

1

T13

11

T21

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

840

1

T13

4

T21

2

T14

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1115

1

T13

15

T57

2

T22

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

855

1

T13

11

T57

1

T22

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1079

1

T13

10

T21

1

T22

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

808

1

T13

4

T21

1

T22

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1086

1

T6

1

T8

1

T13

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

828

1

T6

1

T8

1

T36

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1105

1

T13

8

T21

4

T22

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

845

1

T13

6

T21

4

T22

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1094

1

T6

1

T13

6

T21

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

845

1

T6

1

T13

4

T21

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1070

1

T4

1

T8

1

T13

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

820

1

T8

1

T13

4

T21

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1004

1

T8

1

T13

9

T21

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

741

1

T8

1

T13

6

T21

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1128

1

T8

1

T13

9

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

865

1

T8

1

T13

6

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1086

1

T8

2

T13

3

T21

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

828

1

T8

2

T21

3

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1055

1

T6

1

T13

7

T21

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

782

1

T6

1

T13

5

T21

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1029

1

T13

5

T21

1

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

794

1

T13

5

T21

1

T22

1