Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31672

1

T4

4

T5

46

T9

1

auto[1]

30677

1

T4

2

T5

54

T9

5

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31923

1

T4

4

T5

46

T11

2

auto[1]

30426

1

T4

2

T5

54

T9

6

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30565

1

T4

4

T5

44

T9

2

auto[1]

31784

1

T4

2

T5

56

T9

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35043

1

T4

4

T5

50

T9

4

auto[1]

27306

1

T4

2

T5

50

T9

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30541

1

T4

4

T5

48

T9

6

auto[1]

31808

1

T4

2

T5

52

T11

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31866

1

T4

3

T5

44

T9

3

auto[1]

30483

1

T4

3

T5

56

T9

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1066

1

T12

7

T15

1

T54

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

836

1

T12

7

T15

1

T54

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1086

1

T5

1

T12

1

T27

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

842

1

T5

1

T12

1

T27

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1064

1

T4

1

T5

1

T12

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

828

1

T5

1

T12

2

T15

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1812

1

T12

1

T15

3

T16

25

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1536

1

T12

1

T15

3

T16

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1087

1

T5

2

T12

2

T15

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

847

1

T5

2

T12

2

T15

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1064

1

T5

3

T12

1

T15

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

847

1

T5

3

T12

1

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1040

1

T4

1

T5

3

T12

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

795

1

T5

3

T12

2

T15

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1023

1

T5

2

T12

2

T55

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

814

1

T5

2

T12

2

T55

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1084

1

T15

3

T55

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

842

1

T15

2

T55

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1038

1

T5

3

T9

1

T12

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

782

1

T5

3

T12

5

T15

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1065

1

T5

2

T11

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

836

1

T5

2

T11

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1071

1

T5

3

T15

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

829

1

T5

3

T15

1

T27

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1031

1

T5

1

T12

1

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

785

1

T5

1

T12

1

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1094

1

T4

1

T5

1

T15

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

864

1

T4

1

T5

1

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1059

1

T5

1

T12

2

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

826

1

T5

1

T12

2

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1058

1

T12

1

T15

2

T54

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

821

1

T12

1

T15

2

T27

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1062

1

T4

1

T5

1

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

827

1

T4

1

T5

1

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1042

1

T5

2

T11

1

T12

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

828

1

T5

2

T11

1

T12

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1087

1

T5

1

T12

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

832

1

T5

1

T12

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1077

1

T5

3

T12

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

830

1

T5

3

T12

1

T15

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1147

1

T12

2

T15

2

T16

18

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

872

1

T12

2

T15

2

T16

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1071

1

T15

3

T27

2

T59

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

834

1

T15

3

T27

2

T16

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1088

1

T5

2

T12

4

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

834

1

T5

2

T12

4

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1070

1

T5

2

T12

2

T27

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

835

1

T5

2

T12

2

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1106

1

T5

3

T12

2

T15

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

869

1

T5

3

T12

2

T15

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T5

1

T9

1

T12

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

822

1

T5

1

T9

1

T12

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1057

1

T12

1

T15

3

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

831

1

T12

1

T15

3

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1082

1

T5

1

T15

2

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

824

1

T5

1

T15

2

T27

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1093

1

T5

4

T9

1

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

845

1

T5

4

T9

1

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1051

1

T5

2

T9

1

T12

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

804

1

T5

2

T12

3

T15

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1091

1

T5

1

T27

4

T59

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

833

1

T5

1

T27

4

T59

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1104

1

T5

4

T15

2

T55

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

856

1

T5

4

T15

1

T55

1