Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33360

1

T2

4

T3

16

T4

18

auto[1]

32507

1

T2

2

T3

6

T4

22

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33471

1

T2

5

T3

14

T4

20

auto[1]

32396

1

T2

1

T3

8

T4

20

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32146

1

T2

1

T3

8

T4

30

auto[1]

33721

1

T2

5

T3

14

T4

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36765

1

T2

4

T3

11

T4

20

auto[1]

29102

1

T2

2

T3

11

T4

20

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32151

1

T2

3

T3

10

T4

22

auto[1]

33716

1

T2

3

T3

12

T4

18

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33627

1

T2

3

T3

10

T4

20

auto[1]

32240

1

T2

3

T3

12

T4

20

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1092

1

T4

2

T7

1

T12

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

843

1

T4

2

T7

1

T12

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1089

1

T4

2

T5

1

T55

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

864

1

T4

2

T5

1

T55

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1109

1

T4

1

T12

8

T14

26

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

870

1

T4

1

T12

8

T14

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1832

1

T2

1

T3

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1599

1

T3

1

T7

1

T12

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1114

1

T3

2

T4

1

T12

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

877

1

T3

2

T4

1

T12

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1108

1

T2

1

T12

11

T14

18

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

902

1

T2

1

T12

9

T14

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1166

1

T3

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

915

1

T3

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1126

1

T3

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

880

1

T3

1

T5

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1103

1

T3

1

T4

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

876

1

T3

1

T4

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1099

1

T12

5

T82

1

T14

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

867

1

T12

5

T82

1

T14

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1101

1

T5

1

T12

6

T14

30

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

848

1

T5

1

T12

5

T14

19

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1139

1

T3

2

T5

1

T12

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

892

1

T3

2

T5

1

T12

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1109

1

T2

1

T4

2

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

870

1

T4

2

T7

2

T12

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1130

1

T12

9

T82

2

T83

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

890

1

T12

8

T82

2

T83

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1084

1

T43

1

T12

12

T14

23

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

848

1

T43

1

T12

9

T14

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1192

1

T5

1

T7

1

T12

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

926

1

T5

1

T7

1

T12

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1095

1

T5

2

T7

2

T12

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

859

1

T5

2

T7

2

T12

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1159

1

T3

1

T5

1

T12

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

926

1

T3

1

T5

1

T12

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1129

1

T4

1

T7

1

T55

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

899

1

T4

1

T7

1

T55

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1138

1

T2

1

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

887

1

T2

1

T7

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1149

1

T4

1

T7

1

T55

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

913

1

T4

1

T7

1

T55

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1090

1

T5

2

T7

2

T12

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

841

1

T5

2

T7

2

T12

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1124

1

T4

2

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

900

1

T4

2

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1108

1

T3

1

T55

1

T12

15

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

868

1

T3

1

T55

1

T12

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1214

1

T5

1

T12

12

T82

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

989

1

T5

1

T12

11

T82

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1148

1

T4

1

T8

1

T55

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

913

1

T4

1

T8

1

T12

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1119

1

T4

2

T12

16

T83

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

890

1

T4

2

T12

13

T83

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1146

1

T8

1

T12

10

T14

20

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

893

1

T8

1

T12

10

T14

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1128

1

T55

1

T12

15

T83

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

901

1

T55

1

T12

12

T83

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1135

1

T3

1

T4

1

T5

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

858

1

T3

1

T4

1

T5

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1127

1

T4

2

T5

1

T12

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

885

1

T4

2

T5

1

T12

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1163

1

T4

1

T43

1

T12

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

913

1

T4

1

T43

1

T12

6