Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33510

1

T1

2

T2

66

T4

4

auto[1]

31930

1

T1

4

T2

88

T4

11

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33565

1

T1

3

T2

64

T4

7

auto[1]

31875

1

T1

3

T2

90

T4

8

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32108

1

T1

5

T2

73

T4

7

auto[1]

33332

1

T1

1

T2

81

T4

8

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36639

1

T1

4

T2

79

T4

15

auto[1]

28801

1

T1

2

T2

75

T5

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31874

1

T1

3

T2

88

T4

9

auto[1]

33566

1

T1

3

T2

66

T4

6

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33092

1

T1

2

T2

77

T4

8

auto[1]

32348

1

T1

4

T2

77

T4

7

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1115

1

T2

2

T4

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

878

1

T2

2

T13

2

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1183

1

T7

1

T9

2

T13

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

949

1

T9

2

T13

3

T57

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1160

1

T2

3

T13

3

T23

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

920

1

T2

3

T13

3

T23

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1851

1

T2

1

T13

4

T23

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1595

1

T2

1

T13

4

T23

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1142

1

T2

3

T13

4

T41

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

916

1

T2

3

T13

4

T81

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1104

1

T2

3

T13

3

T23

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

855

1

T2

2

T13

3

T23

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1137

1

T2

1

T13

1

T23

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

871

1

T2

1

T13

1

T23

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1106

1

T2

1

T13

3

T23

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

876

1

T2

1

T13

3

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1117

1

T2

5

T13

3

T23

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

893

1

T2

5

T13

3

T23

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1087

1

T2

1

T4

1

T13

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

847

1

T2

1

T13

3

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1108

1

T1

1

T13

2

T23

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

877

1

T1

1

T13

2

T23

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1112

1

T2

4

T9

2

T13

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

858

1

T2

3

T9

2

T13

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1117

1

T2

2

T10

1

T13

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

870

1

T2

2

T10

1

T13

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1167

1

T2

2

T13

2

T23

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

875

1

T2

2

T13

2

T23

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1130

1

T2

3

T4

2

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

880

1

T2

3

T13

5

T81

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1080

1

T2

3

T9

1

T13

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

834

1

T2

3

T9

1

T13

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1066

1

T2

4

T5

1

T13

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

828

1

T2

4

T13

5

T23

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1071

1

T2

2

T4

3

T9

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

842

1

T2

2

T9

3

T13

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1092

1

T2

2

T4

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

865

1

T2

2

T9

1

T13

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1069

1

T2

1

T10

1

T13

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

826

1

T2

1

T10

1

T13

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1137

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

915

1

T1

1

T2

1

T13

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1102

1

T2

5

T5

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

881

1

T2

4

T9

1

T13

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1177

1

T2

2

T4

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

926

1

T2

2

T9

1

T13

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1187

1

T1

1

T2

2

T13

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

923

1

T2

2

T13

3

T23

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1075

1

T2

2

T13

3

T23

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

826

1

T2

2

T13

3

T23

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1088

1

T2

8

T4

1

T13

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

860

1

T2

8

T13

2

T23

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1101

1

T2

3

T9

1

T13

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

867

1

T2

3

T9

1

T13

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1157

1

T2

1

T4

1

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

909

1

T2

1

T9

1

T13

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1136

1

T1

1

T4

1

T5

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

867

1

T5

2

T13

8

T23

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1157

1

T2

5

T4

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

908

1

T2

5

T7

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1181

1

T2

4

T7

1

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

918

1

T2

3

T7

1

T13

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1127

1

T2

3

T4

1

T13

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

846

1

T2

3

T13

2

T23

2