Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 98.23 96.15 99.44 96.00 96.18 100.00 95.91


Total test records in report: 739
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T194 /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2323109085 Jul 23 06:17:22 PM PDT 24 Jul 23 06:17:26 PM PDT 24 45799709 ps
T564 /workspace/coverage/default/40.pwrmgr_reset_invalid.3934337698 Jul 23 06:18:42 PM PDT 24 Jul 23 06:18:45 PM PDT 24 143755068 ps
T565 /workspace/coverage/default/12.pwrmgr_escalation_timeout.3929836390 Jul 23 06:17:10 PM PDT 24 Jul 23 06:17:12 PM PDT 24 1259145666 ps
T566 /workspace/coverage/default/5.pwrmgr_smoke.832646086 Jul 23 06:16:39 PM PDT 24 Jul 23 06:16:41 PM PDT 24 192243667 ps
T567 /workspace/coverage/default/37.pwrmgr_escalation_timeout.855040769 Jul 23 06:18:32 PM PDT 24 Jul 23 06:18:35 PM PDT 24 159033278 ps
T568 /workspace/coverage/default/39.pwrmgr_reset_invalid.245483646 Jul 23 06:18:36 PM PDT 24 Jul 23 06:18:38 PM PDT 24 366655147 ps
T569 /workspace/coverage/default/32.pwrmgr_reset.1080898894 Jul 23 06:18:16 PM PDT 24 Jul 23 06:18:21 PM PDT 24 63309754 ps
T570 /workspace/coverage/default/2.pwrmgr_glitch.1580226272 Jul 23 06:16:33 PM PDT 24 Jul 23 06:16:38 PM PDT 24 121925244 ps
T571 /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1052599835 Jul 23 06:18:54 PM PDT 24 Jul 23 06:19:01 PM PDT 24 83881342 ps
T163 /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3252922598 Jul 23 06:18:23 PM PDT 24 Jul 23 06:18:28 PM PDT 24 42937538 ps
T572 /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1354479492 Jul 23 06:18:58 PM PDT 24 Jul 23 06:19:07 PM PDT 24 41820903 ps
T573 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1108197073 Jul 23 06:18:18 PM PDT 24 Jul 23 06:18:23 PM PDT 24 81503032 ps
T574 /workspace/coverage/default/45.pwrmgr_reset.386407230 Jul 23 06:19:00 PM PDT 24 Jul 23 06:19:10 PM PDT 24 73825138 ps
T575 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.1159363028 Jul 23 06:17:54 PM PDT 24 Jul 23 06:17:58 PM PDT 24 74801865 ps
T576 /workspace/coverage/default/28.pwrmgr_global_esc.828841470 Jul 23 06:18:07 PM PDT 24 Jul 23 06:18:10 PM PDT 24 43274702 ps
T162 /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2811855708 Jul 23 06:16:20 PM PDT 24 Jul 23 06:16:22 PM PDT 24 54344139 ps
T201 /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3202559078 Jul 23 06:16:36 PM PDT 24 Jul 23 06:16:40 PM PDT 24 64810132 ps
T577 /workspace/coverage/default/16.pwrmgr_glitch.850466082 Jul 23 06:17:28 PM PDT 24 Jul 23 06:17:32 PM PDT 24 47746517 ps
T578 /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.308338854 Jul 23 06:17:06 PM PDT 24 Jul 23 06:17:08 PM PDT 24 70551648 ps
T579 /workspace/coverage/default/40.pwrmgr_smoke.2457731984 Jul 23 06:18:36 PM PDT 24 Jul 23 06:18:38 PM PDT 24 38968529 ps
T580 /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.4256161777 Jul 23 06:17:28 PM PDT 24 Jul 23 06:17:32 PM PDT 24 66092146 ps
T581 /workspace/coverage/default/5.pwrmgr_aborted_low_power.301205066 Jul 23 06:16:48 PM PDT 24 Jul 23 06:16:51 PM PDT 24 89354234 ps
T203 /workspace/coverage/default/43.pwrmgr_wakeup.2271844394 Jul 23 06:18:52 PM PDT 24 Jul 23 06:18:58 PM PDT 24 69624755 ps
T582 /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3319583535 Jul 23 06:17:00 PM PDT 24 Jul 23 06:17:03 PM PDT 24 58279350 ps
T583 /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.856214619 Jul 23 06:16:33 PM PDT 24 Jul 23 06:16:37 PM PDT 24 203218065 ps
T189 /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3791621351 Jul 23 06:16:59 PM PDT 24 Jul 23 06:17:01 PM PDT 24 56579973 ps
T584 /workspace/coverage/default/9.pwrmgr_global_esc.2766660065 Jul 23 06:16:55 PM PDT 24 Jul 23 06:16:58 PM PDT 24 70556779 ps
T585 /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2376041554 Jul 23 06:18:30 PM PDT 24 Jul 23 06:18:33 PM PDT 24 71711543 ps
T586 /workspace/coverage/default/5.pwrmgr_reset_invalid.1522792967 Jul 23 06:16:44 PM PDT 24 Jul 23 06:16:46 PM PDT 24 112065501 ps
T197 /workspace/coverage/default/13.pwrmgr_stress_all.2872978534 Jul 23 06:17:16 PM PDT 24 Jul 23 06:17:18 PM PDT 24 286964051 ps
T587 /workspace/coverage/default/41.pwrmgr_reset.2184371831 Jul 23 06:18:41 PM PDT 24 Jul 23 06:18:43 PM PDT 24 170454483 ps
T588 /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.4294677797 Jul 23 06:16:47 PM PDT 24 Jul 23 06:16:49 PM PDT 24 176924774 ps
T589 /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.452310631 Jul 23 06:16:54 PM PDT 24 Jul 23 06:16:57 PM PDT 24 38460048 ps
T590 /workspace/coverage/default/33.pwrmgr_aborted_low_power.3550496704 Jul 23 06:18:19 PM PDT 24 Jul 23 06:18:23 PM PDT 24 55092213 ps
T591 /workspace/coverage/default/8.pwrmgr_reset.2396062572 Jul 23 06:16:48 PM PDT 24 Jul 23 06:16:51 PM PDT 24 52459318 ps
T592 /workspace/coverage/default/7.pwrmgr_global_esc.179629709 Jul 23 06:16:53 PM PDT 24 Jul 23 06:16:55 PM PDT 24 30053636 ps
T593 /workspace/coverage/default/44.pwrmgr_reset.1139413138 Jul 23 06:19:00 PM PDT 24 Jul 23 06:19:10 PM PDT 24 44022557 ps
T594 /workspace/coverage/default/1.pwrmgr_aborted_low_power.1355301231 Jul 23 06:16:24 PM PDT 24 Jul 23 06:16:26 PM PDT 24 30820116 ps
T595 /workspace/coverage/default/31.pwrmgr_aborted_low_power.3163567367 Jul 23 06:18:13 PM PDT 24 Jul 23 06:18:17 PM PDT 24 93595476 ps
T596 /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.3139901729 Jul 23 06:18:15 PM PDT 24 Jul 23 06:18:19 PM PDT 24 88410444 ps
T597 /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1717225080 Jul 23 06:16:25 PM PDT 24 Jul 23 06:16:28 PM PDT 24 73108051 ps
T598 /workspace/coverage/default/11.pwrmgr_aborted_low_power.2852899155 Jul 23 06:17:01 PM PDT 24 Jul 23 06:17:04 PM PDT 24 120548910 ps
T599 /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2387403191 Jul 23 06:17:01 PM PDT 24 Jul 23 06:17:04 PM PDT 24 60272365 ps
T600 /workspace/coverage/default/3.pwrmgr_glitch.2853358102 Jul 23 06:16:33 PM PDT 24 Jul 23 06:16:37 PM PDT 24 40941637 ps
T601 /workspace/coverage/default/34.pwrmgr_escalation_timeout.1726441993 Jul 23 06:18:22 PM PDT 24 Jul 23 06:18:27 PM PDT 24 170181573 ps
T602 /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.4220850902 Jul 23 06:16:51 PM PDT 24 Jul 23 06:16:53 PM PDT 24 61846439 ps
T603 /workspace/coverage/default/42.pwrmgr_reset.348069629 Jul 23 06:18:48 PM PDT 24 Jul 23 06:18:50 PM PDT 24 33649650 ps
T604 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3213146611 Jul 23 06:16:54 PM PDT 24 Jul 23 06:16:57 PM PDT 24 38598902 ps
T605 /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1695244182 Jul 23 06:18:11 PM PDT 24 Jul 23 06:18:14 PM PDT 24 91177523 ps
T606 /workspace/coverage/default/32.pwrmgr_escalation_timeout.2213234354 Jul 23 06:18:14 PM PDT 24 Jul 23 06:18:18 PM PDT 24 324756803 ps
T607 /workspace/coverage/default/35.pwrmgr_reset.3013967464 Jul 23 06:18:23 PM PDT 24 Jul 23 06:18:27 PM PDT 24 21705796 ps
T608 /workspace/coverage/default/12.pwrmgr_aborted_low_power.596746941 Jul 23 06:17:09 PM PDT 24 Jul 23 06:17:11 PM PDT 24 33620071 ps
T609 /workspace/coverage/default/47.pwrmgr_smoke.528111889 Jul 23 06:19:01 PM PDT 24 Jul 23 06:19:10 PM PDT 24 52631408 ps
T610 /workspace/coverage/default/24.pwrmgr_global_esc.2977852191 Jul 23 06:17:53 PM PDT 24 Jul 23 06:17:57 PM PDT 24 27599668 ps
T611 /workspace/coverage/default/43.pwrmgr_reset.1581627829 Jul 23 06:18:49 PM PDT 24 Jul 23 06:18:52 PM PDT 24 49529160 ps
T612 /workspace/coverage/default/48.pwrmgr_escalation_timeout.3826807668 Jul 23 06:19:00 PM PDT 24 Jul 23 06:19:09 PM PDT 24 633141902 ps
T613 /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1036646458 Jul 23 06:18:52 PM PDT 24 Jul 23 06:18:57 PM PDT 24 63334462 ps
T614 /workspace/coverage/default/5.pwrmgr_glitch.3022402533 Jul 23 06:16:42 PM PDT 24 Jul 23 06:16:44 PM PDT 24 50670000 ps
T615 /workspace/coverage/default/23.pwrmgr_escalation_timeout.3261051769 Jul 23 06:17:42 PM PDT 24 Jul 23 06:17:46 PM PDT 24 609692810 ps
T616 /workspace/coverage/default/37.pwrmgr_reset.945681718 Jul 23 06:18:24 PM PDT 24 Jul 23 06:18:28 PM PDT 24 47094539 ps
T617 /workspace/coverage/default/9.pwrmgr_escalation_timeout.975287206 Jul 23 06:16:54 PM PDT 24 Jul 23 06:16:57 PM PDT 24 995734948 ps
T618 /workspace/coverage/default/36.pwrmgr_smoke.913787141 Jul 23 06:18:25 PM PDT 24 Jul 23 06:18:30 PM PDT 24 34388306 ps
T619 /workspace/coverage/default/43.pwrmgr_glitch.3116775765 Jul 23 06:18:54 PM PDT 24 Jul 23 06:19:01 PM PDT 24 73254669 ps
T620 /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3558326449 Jul 23 06:18:56 PM PDT 24 Jul 23 06:19:04 PM PDT 24 180507759 ps
T621 /workspace/coverage/default/48.pwrmgr_smoke.3993343825 Jul 23 06:19:05 PM PDT 24 Jul 23 06:19:13 PM PDT 24 37064170 ps
T622 /workspace/coverage/default/14.pwrmgr_smoke.1139448853 Jul 23 06:17:09 PM PDT 24 Jul 23 06:17:12 PM PDT 24 33871353 ps
T623 /workspace/coverage/default/28.pwrmgr_escalation_timeout.3176571212 Jul 23 06:18:08 PM PDT 24 Jul 23 06:18:11 PM PDT 24 801678060 ps
T624 /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.167834077 Jul 23 06:17:41 PM PDT 24 Jul 23 06:17:45 PM PDT 24 58790126 ps
T625 /workspace/coverage/default/21.pwrmgr_reset.1981666237 Jul 23 06:17:36 PM PDT 24 Jul 23 06:17:40 PM PDT 24 84563257 ps
T626 /workspace/coverage/default/45.pwrmgr_reset_invalid.3877759813 Jul 23 06:18:55 PM PDT 24 Jul 23 06:19:02 PM PDT 24 151243195 ps
T627 /workspace/coverage/default/44.pwrmgr_global_esc.2024114087 Jul 23 06:19:00 PM PDT 24 Jul 23 06:19:09 PM PDT 24 39655244 ps
T48 /workspace/coverage/default/1.pwrmgr_wakeup_reset.2088408638 Jul 23 06:16:22 PM PDT 24 Jul 23 06:16:24 PM PDT 24 73333295 ps
T628 /workspace/coverage/default/43.pwrmgr_reset_invalid.2582303628 Jul 23 06:18:55 PM PDT 24 Jul 23 06:19:03 PM PDT 24 131746131 ps
T629 /workspace/coverage/default/6.pwrmgr_escalation_timeout.533287337 Jul 23 06:16:52 PM PDT 24 Jul 23 06:16:54 PM PDT 24 157766744 ps
T61 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3839160282 Jul 23 06:16:08 PM PDT 24 Jul 23 06:16:10 PM PDT 24 53606565 ps
T70 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.845912852 Jul 23 06:16:22 PM PDT 24 Jul 23 06:16:24 PM PDT 24 24240948 ps
T62 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2721413216 Jul 23 06:15:54 PM PDT 24 Jul 23 06:15:55 PM PDT 24 35123352 ps
T71 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3905542456 Jul 23 06:16:01 PM PDT 24 Jul 23 06:16:02 PM PDT 24 17027440 ps
T23 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2711080539 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:46 PM PDT 24 365889684 ps
T24 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2039273262 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:48 PM PDT 24 80631264 ps
T25 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.473507287 Jul 23 06:15:39 PM PDT 24 Jul 23 06:15:41 PM PDT 24 82813095 ps
T115 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3837354586 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:12 PM PDT 24 18939626 ps
T58 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2413621564 Jul 23 06:15:58 PM PDT 24 Jul 23 06:16:00 PM PDT 24 284574245 ps
T59 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3047771016 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 186948913 ps
T116 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1049211896 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:52 PM PDT 24 22726328 ps
T117 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3830359882 Jul 23 06:15:51 PM PDT 24 Jul 23 06:15:54 PM PDT 24 121378739 ps
T72 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.864122393 Jul 23 06:15:54 PM PDT 24 Jul 23 06:15:55 PM PDT 24 53219599 ps
T57 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3662190365 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:12 PM PDT 24 34292899 ps
T149 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3246155597 Jul 23 06:15:56 PM PDT 24 Jul 23 06:15:57 PM PDT 24 25077209 ps
T104 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2741805295 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:53 PM PDT 24 47062482 ps
T118 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.215197627 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 65742954 ps
T630 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.349395144 Jul 23 06:15:40 PM PDT 24 Jul 23 06:15:43 PM PDT 24 115249509 ps
T60 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1490058554 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:11 PM PDT 24 25931631 ps
T75 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.579239225 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:14 PM PDT 24 39033139 ps
T631 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.4083018258 Jul 23 06:16:01 PM PDT 24 Jul 23 06:16:02 PM PDT 24 56478727 ps
T105 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.747473899 Jul 23 06:15:43 PM PDT 24 Jul 23 06:15:45 PM PDT 24 61979332 ps
T79 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2943230222 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:46 PM PDT 24 122676572 ps
T119 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.271201382 Jul 23 06:16:06 PM PDT 24 Jul 23 06:16:07 PM PDT 24 29709107 ps
T76 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3637960699 Jul 23 06:15:39 PM PDT 24 Jul 23 06:15:41 PM PDT 24 128930180 ps
T67 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1877873768 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:55 PM PDT 24 97470383 ps
T120 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3632641082 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:48 PM PDT 24 27897625 ps
T77 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1826849564 Jul 23 06:16:03 PM PDT 24 Jul 23 06:16:04 PM PDT 24 52334661 ps
T68 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2237044310 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:07 PM PDT 24 198673135 ps
T150 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2450548881 Jul 23 06:15:39 PM PDT 24 Jul 23 06:15:41 PM PDT 24 26187479 ps
T121 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1080263556 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:11 PM PDT 24 105583267 ps
T632 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2252963628 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 50145221 ps
T151 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.895156949 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:19 PM PDT 24 17481808 ps
T69 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.141302512 Jul 23 06:16:04 PM PDT 24 Jul 23 06:16:07 PM PDT 24 145395179 ps
T633 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1956213447 Jul 23 06:15:40 PM PDT 24 Jul 23 06:15:43 PM PDT 24 442919585 ps
T634 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3391024525 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:12 PM PDT 24 540990758 ps
T130 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2570567205 Jul 23 06:15:53 PM PDT 24 Jul 23 06:15:55 PM PDT 24 115673651 ps
T152 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3926600399 Jul 23 06:15:47 PM PDT 24 Jul 23 06:15:51 PM PDT 24 16906891 ps
T131 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1832452044 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:48 PM PDT 24 78213931 ps
T80 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3833097557 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:12 PM PDT 24 912209108 ps
T122 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.490010110 Jul 23 06:16:08 PM PDT 24 Jul 23 06:16:10 PM PDT 24 33426371 ps
T635 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3512786840 Jul 23 06:15:50 PM PDT 24 Jul 23 06:15:53 PM PDT 24 144100946 ps
T636 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2210442677 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:19 PM PDT 24 53774425 ps
T637 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3437144240 Jul 23 06:15:36 PM PDT 24 Jul 23 06:15:38 PM PDT 24 33831793 ps
T106 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.104449868 Jul 23 06:15:36 PM PDT 24 Jul 23 06:15:38 PM PDT 24 51502901 ps
T638 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.871241311 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:07 PM PDT 24 113167381 ps
T78 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1805856045 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:50 PM PDT 24 393475489 ps
T639 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.644335604 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:54 PM PDT 24 107035443 ps
T640 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2315160471 Jul 23 06:15:39 PM PDT 24 Jul 23 06:15:42 PM PDT 24 81678691 ps
T641 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3962178938 Jul 23 06:16:13 PM PDT 24 Jul 23 06:16:15 PM PDT 24 20615296 ps
T132 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3724521328 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:52 PM PDT 24 69513110 ps
T642 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1374485641 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:52 PM PDT 24 66997949 ps
T643 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3044887700 Jul 23 06:15:51 PM PDT 24 Jul 23 06:15:54 PM PDT 24 132896786 ps
T644 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1402219537 Jul 23 06:16:15 PM PDT 24 Jul 23 06:16:17 PM PDT 24 20453284 ps
T645 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4223285753 Jul 23 06:15:37 PM PDT 24 Jul 23 06:15:39 PM PDT 24 170402991 ps
T646 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2174519261 Jul 23 06:15:55 PM PDT 24 Jul 23 06:15:58 PM PDT 24 72745416 ps
T133 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1747061296 Jul 23 06:16:00 PM PDT 24 Jul 23 06:16:01 PM PDT 24 79872989 ps
T134 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2894822729 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:53 PM PDT 24 268925736 ps
T647 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.48027724 Jul 23 06:16:03 PM PDT 24 Jul 23 06:16:04 PM PDT 24 25699075 ps
T648 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3275105333 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 153539721 ps
T649 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2550375622 Jul 23 06:15:54 PM PDT 24 Jul 23 06:15:56 PM PDT 24 132376438 ps
T650 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1698415387 Jul 23 06:16:19 PM PDT 24 Jul 23 06:16:20 PM PDT 24 21533270 ps
T651 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3124828627 Jul 23 06:16:16 PM PDT 24 Jul 23 06:16:18 PM PDT 24 144932480 ps
T652 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1503550368 Jul 23 06:15:40 PM PDT 24 Jul 23 06:15:42 PM PDT 24 38496493 ps
T113 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.264551508 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:53 PM PDT 24 1055661679 ps
T653 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.4256463158 Jul 23 06:16:07 PM PDT 24 Jul 23 06:16:09 PM PDT 24 36346231 ps
T654 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2066052957 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:50 PM PDT 24 19317236 ps
T655 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.697490385 Jul 23 06:15:59 PM PDT 24 Jul 23 06:16:01 PM PDT 24 150353573 ps
T656 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1949899504 Jul 23 06:16:03 PM PDT 24 Jul 23 06:16:04 PM PDT 24 18014643 ps
T135 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.345088438 Jul 23 06:15:38 PM PDT 24 Jul 23 06:15:39 PM PDT 24 84249757 ps
T136 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1510091100 Jul 23 06:16:08 PM PDT 24 Jul 23 06:16:10 PM PDT 24 58399112 ps
T657 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2970400468 Jul 23 06:15:37 PM PDT 24 Jul 23 06:15:40 PM PDT 24 580797360 ps
T658 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3664750772 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:07 PM PDT 24 27336785 ps
T659 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.2441719631 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:52 PM PDT 24 19870041 ps
T660 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.957401903 Jul 23 06:16:00 PM PDT 24 Jul 23 06:16:03 PM PDT 24 56606004 ps
T661 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2354626543 Jul 23 06:15:47 PM PDT 24 Jul 23 06:15:51 PM PDT 24 31933040 ps
T662 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.779334173 Jul 23 06:15:43 PM PDT 24 Jul 23 06:15:44 PM PDT 24 42896357 ps
T663 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2154990189 Jul 23 06:15:51 PM PDT 24 Jul 23 06:15:55 PM PDT 24 282137677 ps
T664 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2520677136 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:45 PM PDT 24 25593453 ps
T665 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3421221121 Jul 23 06:16:16 PM PDT 24 Jul 23 06:16:18 PM PDT 24 32996057 ps
T666 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.163053272 Jul 23 06:15:47 PM PDT 24 Jul 23 06:15:51 PM PDT 24 41368601 ps
T667 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3466082340 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:19 PM PDT 24 45995565 ps
T668 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1640039507 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:51 PM PDT 24 118315669 ps
T669 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.735168707 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:19 PM PDT 24 18950984 ps
T670 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2407241897 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:53 PM PDT 24 140419884 ps
T671 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1925335714 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:18 PM PDT 24 66992546 ps
T672 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3389034671 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:52 PM PDT 24 78772204 ps
T673 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1765525431 Jul 23 06:16:16 PM PDT 24 Jul 23 06:16:18 PM PDT 24 22068579 ps
T674 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4275255451 Jul 23 06:15:43 PM PDT 24 Jul 23 06:15:46 PM PDT 24 43958149 ps
T675 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4031002655 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:11 PM PDT 24 40640484 ps
T676 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1072724866 Jul 23 06:16:19 PM PDT 24 Jul 23 06:16:20 PM PDT 24 89930142 ps
T677 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3734902264 Jul 23 06:16:41 PM PDT 24 Jul 23 06:16:42 PM PDT 24 45795238 ps
T107 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2236395587 Jul 23 06:15:39 PM PDT 24 Jul 23 06:15:41 PM PDT 24 74193921 ps
T81 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2412563009 Jul 23 06:16:07 PM PDT 24 Jul 23 06:16:10 PM PDT 24 237213005 ps
T678 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.556966478 Jul 23 06:15:47 PM PDT 24 Jul 23 06:15:51 PM PDT 24 93901710 ps
T679 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2474218014 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:12 PM PDT 24 135021707 ps
T680 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4072288391 Jul 23 06:15:54 PM PDT 24 Jul 23 06:15:56 PM PDT 24 19284031 ps
T681 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.4234782891 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:19 PM PDT 24 23018866 ps
T682 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1557697009 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:12 PM PDT 24 232340462 ps
T683 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.335318199 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:07 PM PDT 24 18333260 ps
T684 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1798795245 Jul 23 06:16:17 PM PDT 24 Jul 23 06:16:18 PM PDT 24 150559888 ps
T685 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3103449217 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:13 PM PDT 24 34131010 ps
T686 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.650371368 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:49 PM PDT 24 17307322 ps
T687 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1734539139 Jul 23 06:16:15 PM PDT 24 Jul 23 06:16:16 PM PDT 24 44029861 ps
T73 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3788288057 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 187485395 ps
T688 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2145635841 Jul 23 06:16:15 PM PDT 24 Jul 23 06:16:16 PM PDT 24 20306823 ps
T689 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3182850532 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:11 PM PDT 24 20027366 ps
T690 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3406687544 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:48 PM PDT 24 16082613 ps
T691 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3026833191 Jul 23 06:16:04 PM PDT 24 Jul 23 06:16:06 PM PDT 24 53723845 ps
T692 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.487518173 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:11 PM PDT 24 48862011 ps
T108 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2316799146 Jul 23 06:15:43 PM PDT 24 Jul 23 06:15:45 PM PDT 24 31987686 ps
T693 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3632074811 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:47 PM PDT 24 24024082 ps
T694 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.624479597 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:14 PM PDT 24 88243756 ps
T695 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2063975500 Jul 23 06:16:16 PM PDT 24 Jul 23 06:16:18 PM PDT 24 23251656 ps
T696 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1435143630 Jul 23 06:16:07 PM PDT 24 Jul 23 06:16:09 PM PDT 24 18568785 ps
T697 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3185786108 Jul 23 06:16:00 PM PDT 24 Jul 23 06:16:03 PM PDT 24 1551621445 ps
T698 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.185022129 Jul 23 06:16:01 PM PDT 24 Jul 23 06:16:03 PM PDT 24 286143943 ps
T699 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2080696807 Jul 23 06:15:55 PM PDT 24 Jul 23 06:15:58 PM PDT 24 54383723 ps
T700 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.702564504 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:53 PM PDT 24 96978302 ps
T74 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2142888585 Jul 23 06:16:09 PM PDT 24 Jul 23 06:16:13 PM PDT 24 1608794240 ps
T147 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1649127488 Jul 23 06:16:00 PM PDT 24 Jul 23 06:16:02 PM PDT 24 215240117 ps
T701 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1067944970 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:13 PM PDT 24 105000079 ps
T702 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1933519348 Jul 23 06:15:36 PM PDT 24 Jul 23 06:15:39 PM PDT 24 53789493 ps
T703 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3175834416 Jul 23 06:16:08 PM PDT 24 Jul 23 06:16:11 PM PDT 24 40993257 ps
T704 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3468243815 Jul 23 06:15:54 PM PDT 24 Jul 23 06:15:56 PM PDT 24 37231822 ps
T705 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2874058781 Jul 23 06:16:14 PM PDT 24 Jul 23 06:16:16 PM PDT 24 19871459 ps
T109 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3555783065 Jul 23 06:15:43 PM PDT 24 Jul 23 06:15:45 PM PDT 24 28983348 ps
T706 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3343579584 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:53 PM PDT 24 174342657 ps
T707 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.269243955 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:48 PM PDT 24 19091224 ps
T708 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3376059341 Jul 23 06:16:01 PM PDT 24 Jul 23 06:16:03 PM PDT 24 50312693 ps
T709 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2789301716 Jul 23 06:15:47 PM PDT 24 Jul 23 06:15:51 PM PDT 24 639561912 ps
T710 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3371013482 Jul 23 06:16:07 PM PDT 24 Jul 23 06:16:09 PM PDT 24 42423546 ps
T711 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.681133360 Jul 23 06:16:25 PM PDT 24 Jul 23 06:16:28 PM PDT 24 20097752 ps
T712 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2597259223 Jul 23 06:16:14 PM PDT 24 Jul 23 06:16:16 PM PDT 24 19281203 ps
T713 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.1723762971 Jul 23 06:16:15 PM PDT 24 Jul 23 06:16:17 PM PDT 24 18441694 ps
T714 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3924252168 Jul 23 06:16:12 PM PDT 24 Jul 23 06:16:14 PM PDT 24 46544705 ps
T715 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.881885537 Jul 23 06:16:15 PM PDT 24 Jul 23 06:16:16 PM PDT 24 89356504 ps
T716 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3687037667 Jul 23 06:15:36 PM PDT 24 Jul 23 06:15:38 PM PDT 24 17812213 ps
T717 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1118996611 Jul 23 06:15:45 PM PDT 24 Jul 23 06:15:50 PM PDT 24 350226612 ps
T718 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3027928850 Jul 23 06:15:40 PM PDT 24 Jul 23 06:15:42 PM PDT 24 21577163 ps
T719 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.260061909 Jul 23 06:15:55 PM PDT 24 Jul 23 06:15:57 PM PDT 24 67877097 ps
T720 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3813681176 Jul 23 06:16:22 PM PDT 24 Jul 23 06:16:24 PM PDT 24 20256795 ps
T721 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4290663233 Jul 23 06:15:59 PM PDT 24 Jul 23 06:16:01 PM PDT 24 282669107 ps
T722 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1256936844 Jul 23 06:15:44 PM PDT 24 Jul 23 06:15:46 PM PDT 24 47032246 ps
T723 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1562207968 Jul 23 06:15:57 PM PDT 24 Jul 23 06:15:59 PM PDT 24 30447289 ps
T724 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3491961184 Jul 23 06:15:53 PM PDT 24 Jul 23 06:15:55 PM PDT 24 51935238 ps
T725 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3791447116 Jul 23 06:15:58 PM PDT 24 Jul 23 06:16:00 PM PDT 24 62803093 ps
T726 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3184601499 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:50 PM PDT 24 47769936 ps
T727 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3692510040 Jul 23 06:16:16 PM PDT 24 Jul 23 06:16:17 PM PDT 24 135481003 ps
T728 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3950907036 Jul 23 06:16:14 PM PDT 24 Jul 23 06:16:16 PM PDT 24 47657515 ps
T729 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.311420942 Jul 23 06:16:12 PM PDT 24 Jul 23 06:16:15 PM PDT 24 65222145 ps
T730 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3903243073 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:50 PM PDT 24 30512032 ps
T110 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3361283259 Jul 23 06:15:49 PM PDT 24 Jul 23 06:15:53 PM PDT 24 53883630 ps
T111 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3957832481 Jul 23 06:16:06 PM PDT 24 Jul 23 06:16:07 PM PDT 24 17876295 ps
T731 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.792973210 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:13 PM PDT 24 18879276 ps
T732 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.807739188 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:14 PM PDT 24 30459437 ps
T112 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2802441872 Jul 23 06:15:41 PM PDT 24 Jul 23 06:15:43 PM PDT 24 26438886 ps
T114 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.166969150 Jul 23 06:15:58 PM PDT 24 Jul 23 06:15:59 PM PDT 24 51718786 ps
T733 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.262766418 Jul 23 06:16:10 PM PDT 24 Jul 23 06:16:12 PM PDT 24 107956525 ps
T734 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.107088248 Jul 23 06:16:11 PM PDT 24 Jul 23 06:16:13 PM PDT 24 26635556 ps
T735 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3248563454 Jul 23 06:15:46 PM PDT 24 Jul 23 06:15:51 PM PDT 24 128808596 ps
T736 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.512778600 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:08 PM PDT 24 71404840 ps
T737 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.442487774 Jul 23 06:15:51 PM PDT 24 Jul 23 06:15:54 PM PDT 24 61776818 ps
T738 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3990513704 Jul 23 06:16:05 PM PDT 24 Jul 23 06:16:07 PM PDT 24 68984481 ps
T739 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4254208665 Jul 23 06:15:48 PM PDT 24 Jul 23 06:15:52 PM PDT 24 50552268 ps

Test location /workspace/coverage/default/37.pwrmgr_smoke.408835066
Short name T8
Test name
Test status
Simulation time 36552187 ps
CPU time 0.66 seconds
Started Jul 23 06:18:26 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 199944 kb
Host smart-a5e86c29-0649-403c-889a-dcb747b26d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408835066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.408835066
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.90873607
Short name T6
Test name
Test status
Simulation time 154852169 ps
CPU time 0.86 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 210128 kb
Host smart-e1110bbf-18a5-4ea6-aafb-d998e6680fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90873607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.90873607
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3777874699
Short name T14
Test name
Test status
Simulation time 73924113 ps
CPU time 0.93 seconds
Started Jul 23 06:17:52 PM PDT 24
Finished Jul 23 06:17:56 PM PDT 24
Peak memory 200900 kb
Host smart-930d674f-90e1-4473-b618-8789ce43936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777874699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3777874699
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3047771016
Short name T59
Test name
Test status
Simulation time 186948913 ps
CPU time 1.56 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 200652 kb
Host smart-8e4df9b3-4f5d-4eec-9dcd-fd760e4bc184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047771016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3047771016
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2023294857
Short name T20
Test name
Test status
Simulation time 334932941 ps
CPU time 1.45 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:30 PM PDT 24
Peak memory 217312 kb
Host smart-b460f6ec-0262-4fda-a7b0-00a7673d4a70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023294857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2023294857
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1000715236
Short name T16
Test name
Test status
Simulation time 76827858 ps
CPU time 0.66 seconds
Started Jul 23 06:18:28 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 201948 kb
Host smart-9ec2375f-3e61-4289-bca4-3ba1b8aeee5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000715236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1000715236
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.3669080665
Short name T13
Test name
Test status
Simulation time 62393818 ps
CPU time 0.83 seconds
Started Jul 23 06:17:08 PM PDT 24
Finished Jul 23 06:17:10 PM PDT 24
Peak memory 198964 kb
Host smart-6a38a97a-cdfe-4490-8c86-27d040fc3bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669080665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.3669080665
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1841771568
Short name T42
Test name
Test status
Simulation time 83718333 ps
CPU time 0.64 seconds
Started Jul 23 06:17:16 PM PDT 24
Finished Jul 23 06:17:18 PM PDT 24
Peak memory 199088 kb
Host smart-366cae1f-e53e-4b51-ae14-db021eae4c59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841771568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1841771568
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.2206716446
Short name T204
Test name
Test status
Simulation time 95547568 ps
CPU time 1.01 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:00 PM PDT 24
Peak memory 210136 kb
Host smart-9831a552-9621-4d5b-9da7-162dfebce11b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206716446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2206716446
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.473507287
Short name T25
Test name
Test status
Simulation time 82813095 ps
CPU time 1.1 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:41 PM PDT 24
Peak memory 200972 kb
Host smart-d56f1b58-3031-4ede-b376-3f7925968f66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473507287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.473507287
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.452440646
Short name T45
Test name
Test status
Simulation time 49379109 ps
CPU time 0.83 seconds
Started Jul 23 06:18:47 PM PDT 24
Finished Jul 23 06:18:49 PM PDT 24
Peak memory 200084 kb
Host smart-d9c9c328-5a79-439b-a9dd-5e36242e557d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452440646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.452440646
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3905542456
Short name T71
Test name
Test status
Simulation time 17027440 ps
CPU time 0.65 seconds
Started Jul 23 06:16:01 PM PDT 24
Finished Jul 23 06:16:02 PM PDT 24
Peak memory 195476 kb
Host smart-2eefac34-9a17-44a1-85d5-122731cf2e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905542456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3905542456
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.3602626990
Short name T26
Test name
Test status
Simulation time 45903691 ps
CPU time 0.65 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 198708 kb
Host smart-5a6b3eba-169c-44f0-9da9-63cc9ca7a9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602626990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3602626990
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.104449868
Short name T106
Test name
Test status
Simulation time 51502901 ps
CPU time 0.65 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:38 PM PDT 24
Peak memory 195604 kb
Host smart-708ced69-c426-4b34-9e01-9f39968a81d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104449868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.104449868
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.996377074
Short name T1
Test name
Test status
Simulation time 612707537 ps
CPU time 0.94 seconds
Started Jul 23 06:17:08 PM PDT 24
Finished Jul 23 06:17:11 PM PDT 24
Peak memory 198576 kb
Host smart-3c66ffc2-ed49-4992-9bfa-9fb2b470dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996377074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.996377074
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3502331231
Short name T15
Test name
Test status
Simulation time 99931351 ps
CPU time 0.79 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 199536 kb
Host smart-f5f5e0a6-07dc-4408-a85a-b19f9282f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502331231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3502331231
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.2593848928
Short name T188
Test name
Test status
Simulation time 395280132 ps
CPU time 0.83 seconds
Started Jul 23 06:18:44 PM PDT 24
Finished Jul 23 06:18:46 PM PDT 24
Peak memory 199756 kb
Host smart-a973e353-8d82-4371-af38-92737a618c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593848928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.2593848928
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.640396639
Short name T143
Test name
Test status
Simulation time 82236481 ps
CPU time 0.68 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 199684 kb
Host smart-5ab94861-bbf9-4fe3-bfaf-08cddde2d6eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640396639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.640396639
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2315160471
Short name T640
Test name
Test status
Simulation time 81678691 ps
CPU time 1.82 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 198004 kb
Host smart-89c5d6c7-4deb-454e-ac6f-488d3d396a47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315160471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2315160471
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1121540374
Short name T192
Test name
Test status
Simulation time 43262655 ps
CPU time 0.75 seconds
Started Jul 23 06:18:10 PM PDT 24
Finished Jul 23 06:18:13 PM PDT 24
Peak memory 202008 kb
Host smart-0d461409-0e86-4286-b89c-4c566f5cf795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121540374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1121540374
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1823500155
Short name T154
Test name
Test status
Simulation time 65919395 ps
CPU time 0.72 seconds
Started Jul 23 06:18:38 PM PDT 24
Finished Jul 23 06:18:40 PM PDT 24
Peak memory 199140 kb
Host smart-3250ebd7-bad6-4fca-b45e-2d4df6c38e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823500155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.1823500155
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.2088408638
Short name T48
Test name
Test status
Simulation time 73333295 ps
CPU time 0.64 seconds
Started Jul 23 06:16:22 PM PDT 24
Finished Jul 23 06:16:24 PM PDT 24
Peak memory 199332 kb
Host smart-dfbaf523-5f83-4a80-b630-5c66b71e63b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088408638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2088408638
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.4181435256
Short name T172
Test name
Test status
Simulation time 46043350 ps
CPU time 0.73 seconds
Started Jul 23 06:17:51 PM PDT 24
Finished Jul 23 06:17:53 PM PDT 24
Peak memory 201924 kb
Host smart-eb366200-6bd7-4203-ba50-d2e97e3e8da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181435256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.4181435256
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.885270693
Short name T49
Test name
Test status
Simulation time 34145814 ps
CPU time 0.7 seconds
Started Jul 23 06:18:48 PM PDT 24
Finished Jul 23 06:18:50 PM PDT 24
Peak memory 198864 kb
Host smart-149be4dc-53af-4e9a-b736-ec4837c857cd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885270693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_c
m_ctrl_config_regwen.885270693
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2803489993
Short name T187
Test name
Test status
Simulation time 217426023 ps
CPU time 0.66 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:31 PM PDT 24
Peak memory 201880 kb
Host smart-c9225bc3-3efb-4146-840c-e563b065fdb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803489993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2803489993
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2157299161
Short name T33
Test name
Test status
Simulation time 93841222 ps
CPU time 1.1 seconds
Started Jul 23 06:17:05 PM PDT 24
Finished Jul 23 06:17:08 PM PDT 24
Peak memory 210100 kb
Host smart-3083ebaa-0cef-40d4-a709-4efca3f48bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157299161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2157299161
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3356059272
Short name T159
Test name
Test status
Simulation time 50221416 ps
CPU time 0.77 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:16 PM PDT 24
Peak memory 199660 kb
Host smart-fd0f2bdc-b661-4fa0-95bb-aa3b44c28c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356059272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3356059272
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.20818194
Short name T178
Test name
Test status
Simulation time 70295286 ps
CPU time 0.74 seconds
Started Jul 23 06:16:55 PM PDT 24
Finished Jul 23 06:16:58 PM PDT 24
Peak memory 202004 kb
Host smart-9bd6180f-03e3-487c-b174-465c9b9b3f03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20818194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.20818194
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1596596676
Short name T47
Test name
Test status
Simulation time 78477507 ps
CPU time 0.69 seconds
Started Jul 23 06:16:37 PM PDT 24
Finished Jul 23 06:16:40 PM PDT 24
Peak memory 199716 kb
Host smart-882ac2a5-0739-411b-8668-d405e43d5057
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596596676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.1596596676
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.845912852
Short name T70
Test name
Test status
Simulation time 24240948 ps
CPU time 0.6 seconds
Started Jul 23 06:16:22 PM PDT 24
Finished Jul 23 06:16:24 PM PDT 24
Peak memory 195548 kb
Host smart-5515025d-991d-442d-97d0-faaadc02899d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845912852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.845912852
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2387403191
Short name T599
Test name
Test status
Simulation time 60272365 ps
CPU time 0.8 seconds
Started Jul 23 06:17:01 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 198956 kb
Host smart-a68d08f8-73b8-4b18-b23f-701bb4fbc2a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387403191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2387403191
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2323109085
Short name T194
Test name
Test status
Simulation time 45799709 ps
CPU time 0.74 seconds
Started Jul 23 06:17:22 PM PDT 24
Finished Jul 23 06:17:26 PM PDT 24
Peak memory 201932 kb
Host smart-837c23da-ba2d-4224-9197-061829ad4787
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323109085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2323109085
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.784822796
Short name T164
Test name
Test status
Simulation time 45967957 ps
CPU time 0.71 seconds
Started Jul 23 06:17:51 PM PDT 24
Finished Jul 23 06:17:54 PM PDT 24
Peak memory 201976 kb
Host smart-56adf32b-4eb9-49cd-a367-ede68e3b382d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784822796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invali
d.784822796
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1649127488
Short name T147
Test name
Test status
Simulation time 215240117 ps
CPU time 1.54 seconds
Started Jul 23 06:16:00 PM PDT 24
Finished Jul 23 06:16:02 PM PDT 24
Peak memory 195880 kb
Host smart-b0dd56f6-d6e4-4be7-bd2f-b58cae19ef71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649127488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1649127488
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2721413216
Short name T62
Test name
Test status
Simulation time 35123352 ps
CPU time 0.67 seconds
Started Jul 23 06:15:54 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 197764 kb
Host smart-e19fe9cb-2528-413c-855b-0fa5cbde265b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721413216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2721413216
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1507893641
Short name T29
Test name
Test status
Simulation time 648544022 ps
CPU time 1.85 seconds
Started Jul 23 06:16:19 PM PDT 24
Finished Jul 23 06:16:22 PM PDT 24
Peak memory 217332 kb
Host smart-4f33dcc0-0852-4b24-8e62-e968ee73e47c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507893641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1507893641
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.1686019075
Short name T320
Test name
Test status
Simulation time 49125405 ps
CPU time 0.66 seconds
Started Jul 23 06:16:28 PM PDT 24
Finished Jul 23 06:16:33 PM PDT 24
Peak memory 199132 kb
Host smart-6db883ce-0e78-4c13-be98-ac5983b07335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686019075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.1686019075
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.206741637
Short name T146
Test name
Test status
Simulation time 84967992 ps
CPU time 0.63 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:22 PM PDT 24
Peak memory 198848 kb
Host smart-ba524d8c-d928-434d-bb34-4e7a344cbe41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206741637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wak
eup_race.206741637
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3273477744
Short name T86
Test name
Test status
Simulation time 28569394 ps
CPU time 0.66 seconds
Started Jul 23 06:17:14 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 199928 kb
Host smart-73512a44-125b-4799-b304-e954988e32ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273477744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3273477744
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.758950795
Short name T158
Test name
Test status
Simulation time 62772950 ps
CPU time 0.73 seconds
Started Jul 23 06:17:11 PM PDT 24
Finished Jul 23 06:17:13 PM PDT 24
Peak memory 199696 kb
Host smart-d24e7da3-5919-43e2-9359-dcd5b4f99722
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758950795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.758950795
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3816394136
Short name T196
Test name
Test status
Simulation time 43222742 ps
CPU time 0.75 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 201980 kb
Host smart-5c316419-eb6e-44b1-a78d-d62ab79551d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816394136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3816394136
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.953136749
Short name T169
Test name
Test status
Simulation time 63686484 ps
CPU time 0.67 seconds
Started Jul 23 06:17:43 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 201964 kb
Host smart-f99ccd3f-b518-45d4-a3cf-ec72c99dd8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953136749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.953136749
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2086390049
Short name T176
Test name
Test status
Simulation time 82366172 ps
CPU time 0.69 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 201804 kb
Host smart-813a5b82-92ba-4794-8d23-68bc592783ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086390049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2086390049
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2180455776
Short name T27
Test name
Test status
Simulation time 46981281 ps
CPU time 0.71 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:44 PM PDT 24
Peak memory 199652 kb
Host smart-e4a26537-d1d3-4c0b-afa3-59e3797ee808
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180455776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2180455776
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.2271844394
Short name T203
Test name
Test status
Simulation time 69624755 ps
CPU time 0.62 seconds
Started Jul 23 06:18:52 PM PDT 24
Finished Jul 23 06:18:58 PM PDT 24
Peak memory 199708 kb
Host smart-fadfd6da-3fab-4f2e-ba05-f6be07ae791b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271844394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.2271844394
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1933519348
Short name T702
Test name
Test status
Simulation time 53789493 ps
CPU time 1.45 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:39 PM PDT 24
Peak memory 198596 kb
Host smart-eb5352b2-8131-4a6e-931e-6d8a055488d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933519348 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1933519348
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2818425040
Short name T19
Test name
Test status
Simulation time 93288384 ps
CPU time 0.63 seconds
Started Jul 23 06:16:59 PM PDT 24
Finished Jul 23 06:17:01 PM PDT 24
Peak memory 197920 kb
Host smart-483b5bd6-e5da-4ce4-81e6-b360868ff91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818425040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2818425040
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2236395587
Short name T107
Test name
Test status
Simulation time 74193921 ps
CPU time 0.8 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:41 PM PDT 24
Peak memory 195448 kb
Host smart-5602257e-5fa6-446b-a077-0698c4d214d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236395587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
236395587
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.349395144
Short name T630
Test name
Test status
Simulation time 115249509 ps
CPU time 1.97 seconds
Started Jul 23 06:15:40 PM PDT 24
Finished Jul 23 06:15:43 PM PDT 24
Peak memory 195592 kb
Host smart-964e5e75-0199-4165-a37b-d1b6c7d87648
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349395144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.349395144
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3687037667
Short name T716
Test name
Test status
Simulation time 17812213 ps
CPU time 0.67 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:38 PM PDT 24
Peak memory 197724 kb
Host smart-dadfdd82-97b0-4402-8f06-aed3231af184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687037667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3687037667
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1503550368
Short name T652
Test name
Test status
Simulation time 38496493 ps
CPU time 0.61 seconds
Started Jul 23 06:15:40 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 195448 kb
Host smart-fc3f1644-179e-4de7-aa8c-8970a91903f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503550368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1503550368
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.345088438
Short name T135
Test name
Test status
Simulation time 84249757 ps
CPU time 0.74 seconds
Started Jul 23 06:15:38 PM PDT 24
Finished Jul 23 06:15:39 PM PDT 24
Peak memory 197792 kb
Host smart-69856f9e-2509-4bbb-98ef-b41477303b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345088438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.345088438
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4223285753
Short name T645
Test name
Test status
Simulation time 170402991 ps
CPU time 1.53 seconds
Started Jul 23 06:15:37 PM PDT 24
Finished Jul 23 06:15:39 PM PDT 24
Peak memory 200828 kb
Host smart-7d1fc1e1-8d9c-4be1-846c-3d65684fdc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223285753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.4223285753
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2802441872
Short name T112
Test name
Test status
Simulation time 26438886 ps
CPU time 0.94 seconds
Started Jul 23 06:15:41 PM PDT 24
Finished Jul 23 06:15:43 PM PDT 24
Peak memory 195440 kb
Host smart-2490bac8-4850-4b94-8257-c1ff847241f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802441872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.2
802441872
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2970400468
Short name T657
Test name
Test status
Simulation time 580797360 ps
CPU time 1.95 seconds
Started Jul 23 06:15:37 PM PDT 24
Finished Jul 23 06:15:40 PM PDT 24
Peak memory 195728 kb
Host smart-58ed7160-56b4-4af9-9d3f-deca06619d8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970400468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
970400468
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3637960699
Short name T76
Test name
Test status
Simulation time 128930180 ps
CPU time 0.67 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:41 PM PDT 24
Peak memory 198712 kb
Host smart-82e19675-4734-4cdf-9c5b-2eb7aabe888e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637960699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
637960699
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1832452044
Short name T131
Test name
Test status
Simulation time 78213931 ps
CPU time 0.79 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:48 PM PDT 24
Peak memory 195756 kb
Host smart-93e2b916-6d52-404c-b2e9-672e85b9388f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832452044 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1832452044
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3437144240
Short name T637
Test name
Test status
Simulation time 33831793 ps
CPU time 0.71 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:38 PM PDT 24
Peak memory 195624 kb
Host smart-6c38e38a-1f27-4510-a9be-0a3536f15709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437144240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3437144240
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2450548881
Short name T150
Test name
Test status
Simulation time 26187479 ps
CPU time 0.64 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:41 PM PDT 24
Peak memory 195444 kb
Host smart-04b526ba-f052-4bc0-8ac5-cb4351a6a33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450548881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2450548881
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3027928850
Short name T718
Test name
Test status
Simulation time 21577163 ps
CPU time 0.75 seconds
Started Jul 23 06:15:40 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 195584 kb
Host smart-de100bc8-d384-4530-8b82-2d096c995164
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027928850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3027928850
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1956213447
Short name T633
Test name
Test status
Simulation time 442919585 ps
CPU time 1.49 seconds
Started Jul 23 06:15:40 PM PDT 24
Finished Jul 23 06:15:43 PM PDT 24
Peak memory 195868 kb
Host smart-ac074d19-301b-4839-8710-9318d4ea9398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956213447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1956213447
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3468243815
Short name T704
Test name
Test status
Simulation time 37231822 ps
CPU time 0.73 seconds
Started Jul 23 06:15:54 PM PDT 24
Finished Jul 23 06:15:56 PM PDT 24
Peak memory 195688 kb
Host smart-d425c0bb-a669-4768-a40d-17144189bb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468243815 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.3468243815
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.864122393
Short name T72
Test name
Test status
Simulation time 53219599 ps
CPU time 0.61 seconds
Started Jul 23 06:15:54 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 195456 kb
Host smart-04261a8e-21be-41f0-8076-8a8e1ad24aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864122393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.864122393
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4072288391
Short name T680
Test name
Test status
Simulation time 19284031 ps
CPU time 0.74 seconds
Started Jul 23 06:15:54 PM PDT 24
Finished Jul 23 06:15:56 PM PDT 24
Peak memory 197868 kb
Host smart-59d63aa1-129c-4884-80a0-509006bbc6f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072288391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.4072288391
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1562207968
Short name T723
Test name
Test status
Simulation time 30447289 ps
CPU time 1.39 seconds
Started Jul 23 06:15:57 PM PDT 24
Finished Jul 23 06:15:59 PM PDT 24
Peak memory 196880 kb
Host smart-5ddb490f-b85c-438d-9824-d5e194d7010f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562207968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1562207968
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2413621564
Short name T58
Test name
Test status
Simulation time 284574245 ps
CPU time 1.59 seconds
Started Jul 23 06:15:58 PM PDT 24
Finished Jul 23 06:16:00 PM PDT 24
Peak memory 195868 kb
Host smart-b89cd897-8cd4-4676-9239-fe42345fafb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413621564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2413621564
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.957401903
Short name T660
Test name
Test status
Simulation time 56606004 ps
CPU time 1.19 seconds
Started Jul 23 06:16:00 PM PDT 24
Finished Jul 23 06:16:03 PM PDT 24
Peak memory 195720 kb
Host smart-b096dfbc-7f1c-4171-8ec1-002b5f1834e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957401903 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.957401903
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3376059341
Short name T708
Test name
Test status
Simulation time 50312693 ps
CPU time 0.68 seconds
Started Jul 23 06:16:01 PM PDT 24
Finished Jul 23 06:16:03 PM PDT 24
Peak memory 197772 kb
Host smart-1763ef8a-8c20-4928-b08f-f2ac59c4e74c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376059341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3376059341
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1949899504
Short name T656
Test name
Test status
Simulation time 18014643 ps
CPU time 0.62 seconds
Started Jul 23 06:16:03 PM PDT 24
Finished Jul 23 06:16:04 PM PDT 24
Peak memory 195512 kb
Host smart-1d59ccf0-61cd-405e-b870-f35b360aa1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949899504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1949899504
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.697490385
Short name T655
Test name
Test status
Simulation time 150353573 ps
CPU time 0.75 seconds
Started Jul 23 06:15:59 PM PDT 24
Finished Jul 23 06:16:01 PM PDT 24
Peak memory 197808 kb
Host smart-a77c1189-8681-4809-8b4f-f3bfae882561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697490385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sa
me_csr_outstanding.697490385
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3185786108
Short name T697
Test name
Test status
Simulation time 1551621445 ps
CPU time 1.7 seconds
Started Jul 23 06:16:00 PM PDT 24
Finished Jul 23 06:16:03 PM PDT 24
Peak memory 196932 kb
Host smart-977e8b7b-f7e5-472b-8294-0a6b9f311fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185786108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3185786108
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1826849564
Short name T77
Test name
Test status
Simulation time 52334661 ps
CPU time 0.74 seconds
Started Jul 23 06:16:03 PM PDT 24
Finished Jul 23 06:16:04 PM PDT 24
Peak memory 195756 kb
Host smart-53c3eb29-3e71-4ef4-a9a9-ba8916d73137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826849564 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1826849564
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.4083018258
Short name T631
Test name
Test status
Simulation time 56478727 ps
CPU time 0.68 seconds
Started Jul 23 06:16:01 PM PDT 24
Finished Jul 23 06:16:02 PM PDT 24
Peak memory 198716 kb
Host smart-fd3dc47d-585a-417f-b246-61564cef5dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083018258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.4083018258
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1747061296
Short name T133
Test name
Test status
Simulation time 79872989 ps
CPU time 0.72 seconds
Started Jul 23 06:16:00 PM PDT 24
Finished Jul 23 06:16:01 PM PDT 24
Peak memory 198868 kb
Host smart-a31b4fa4-061f-435e-8205-33706a21515b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747061296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.1747061296
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.185022129
Short name T698
Test name
Test status
Simulation time 286143943 ps
CPU time 1.69 seconds
Started Jul 23 06:16:01 PM PDT 24
Finished Jul 23 06:16:03 PM PDT 24
Peak memory 196868 kb
Host smart-13cc61a3-7221-4826-8eb2-c2a1f09d0568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185022129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.185022129
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4290663233
Short name T721
Test name
Test status
Simulation time 282669107 ps
CPU time 1.12 seconds
Started Jul 23 06:15:59 PM PDT 24
Finished Jul 23 06:16:01 PM PDT 24
Peak memory 200876 kb
Host smart-82aa4ca6-9e59-403c-867d-76d1bc97ce3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290663233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.4290663233
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.4256463158
Short name T653
Test name
Test status
Simulation time 36346231 ps
CPU time 0.76 seconds
Started Jul 23 06:16:07 PM PDT 24
Finished Jul 23 06:16:09 PM PDT 24
Peak memory 195700 kb
Host smart-2e79b07b-ac1b-4000-9595-4bd6e3a57447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256463158 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.4256463158
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3957832481
Short name T111
Test name
Test status
Simulation time 17876295 ps
CPU time 0.7 seconds
Started Jul 23 06:16:06 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 196752 kb
Host smart-641df02d-40bf-4eda-b10a-6a1bab9604a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957832481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3957832481
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.48027724
Short name T647
Test name
Test status
Simulation time 25699075 ps
CPU time 0.59 seconds
Started Jul 23 06:16:03 PM PDT 24
Finished Jul 23 06:16:04 PM PDT 24
Peak memory 195444 kb
Host smart-6ef0ea24-cb2f-4d0f-92cd-7419a1e96080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48027724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.48027724
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3371013482
Short name T710
Test name
Test status
Simulation time 42423546 ps
CPU time 0.85 seconds
Started Jul 23 06:16:07 PM PDT 24
Finished Jul 23 06:16:09 PM PDT 24
Peak memory 198984 kb
Host smart-97bb4f7a-afeb-46bb-a318-a0696450df25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371013482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3371013482
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.141302512
Short name T69
Test name
Test status
Simulation time 145395179 ps
CPU time 2.07 seconds
Started Jul 23 06:16:04 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 197960 kb
Host smart-984509b1-5002-4cfd-9870-6137af611cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141302512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.141302512
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3391024525
Short name T634
Test name
Test status
Simulation time 540990758 ps
CPU time 0.99 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195596 kb
Host smart-d0818ec3-7f89-4426-a5da-8927b6107f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391024525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3391024525
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.871241311
Short name T638
Test name
Test status
Simulation time 113167381 ps
CPU time 0.85 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 195664 kb
Host smart-b1129ed7-1a11-48b5-8bdb-99534df28f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871241311 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.871241311
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1510091100
Short name T136
Test name
Test status
Simulation time 58399112 ps
CPU time 0.66 seconds
Started Jul 23 06:16:08 PM PDT 24
Finished Jul 23 06:16:10 PM PDT 24
Peak memory 197712 kb
Host smart-5e9071dd-6462-4985-971d-a011f42d484b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510091100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1510091100
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.487518173
Short name T692
Test name
Test status
Simulation time 48862011 ps
CPU time 0.59 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 195560 kb
Host smart-c6f95cb6-b06d-476d-a370-002e7a726b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487518173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.487518173
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.490010110
Short name T122
Test name
Test status
Simulation time 33426371 ps
CPU time 0.7 seconds
Started Jul 23 06:16:08 PM PDT 24
Finished Jul 23 06:16:10 PM PDT 24
Peak memory 195556 kb
Host smart-aa1f2e77-85cf-46c2-aa6a-5d5c0e5f8826
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490010110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.490010110
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3662190365
Short name T57
Test name
Test status
Simulation time 34292899 ps
CPU time 1.4 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195980 kb
Host smart-6e22c5e1-9489-4ac7-97bc-9f6a356a6945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662190365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3662190365
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2412563009
Short name T81
Test name
Test status
Simulation time 237213005 ps
CPU time 1.66 seconds
Started Jul 23 06:16:07 PM PDT 24
Finished Jul 23 06:16:10 PM PDT 24
Peak memory 200840 kb
Host smart-8c63a010-1565-42d4-be46-94a1d46e67a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412563009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.2412563009
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2237044310
Short name T68
Test name
Test status
Simulation time 198673135 ps
CPU time 1.21 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 197564 kb
Host smart-4fb8eee6-631f-436b-a2b0-96edb29651ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237044310 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2237044310
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3839160282
Short name T61
Test name
Test status
Simulation time 53606565 ps
CPU time 0.66 seconds
Started Jul 23 06:16:08 PM PDT 24
Finished Jul 23 06:16:10 PM PDT 24
Peak memory 197752 kb
Host smart-e28fbcdd-2590-41f4-b5a2-1e061ce50045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839160282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3839160282
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1435143630
Short name T696
Test name
Test status
Simulation time 18568785 ps
CPU time 0.66 seconds
Started Jul 23 06:16:07 PM PDT 24
Finished Jul 23 06:16:09 PM PDT 24
Peak memory 195236 kb
Host smart-314e335b-33f5-4d34-88bb-31009a9b5f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435143630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1435143630
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1080263556
Short name T121
Test name
Test status
Simulation time 105583267 ps
CPU time 0.82 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 195516 kb
Host smart-3050346d-86e4-4701-afa0-f95de77412c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080263556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1080263556
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.512778600
Short name T736
Test name
Test status
Simulation time 71404840 ps
CPU time 1.57 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:08 PM PDT 24
Peak memory 195948 kb
Host smart-b2c4b070-8733-4345-b7dc-5623e15385ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512778600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.512778600
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3026833191
Short name T691
Test name
Test status
Simulation time 53723845 ps
CPU time 0.97 seconds
Started Jul 23 06:16:04 PM PDT 24
Finished Jul 23 06:16:06 PM PDT 24
Peak memory 195748 kb
Host smart-935b2b9d-3ffd-4712-ab33-e59e089da50e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026833191 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3026833191
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.335318199
Short name T683
Test name
Test status
Simulation time 18333260 ps
CPU time 0.72 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 197796 kb
Host smart-07ada493-941b-4723-b841-ea4f2b0257af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335318199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.335318199
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3664750772
Short name T658
Test name
Test status
Simulation time 27336785 ps
CPU time 0.61 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 195540 kb
Host smart-78477bac-11c3-4369-bdb8-b5410c3cef39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664750772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3664750772
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.271201382
Short name T119
Test name
Test status
Simulation time 29709107 ps
CPU time 0.9 seconds
Started Jul 23 06:16:06 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 200144 kb
Host smart-db09cb9c-5541-4567-8a7a-4186551c6a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271201382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.271201382
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3275105333
Short name T648
Test name
Test status
Simulation time 153539721 ps
CPU time 1.88 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 197256 kb
Host smart-a110b844-1e57-476d-9b75-162cb601fa14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275105333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3275105333
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3833097557
Short name T80
Test name
Test status
Simulation time 912209108 ps
CPU time 1.09 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195872 kb
Host smart-db4024ee-fb82-47d8-ae46-264e559aabf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833097557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3833097557
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3924252168
Short name T714
Test name
Test status
Simulation time 46544705 ps
CPU time 0.88 seconds
Started Jul 23 06:16:12 PM PDT 24
Finished Jul 23 06:16:14 PM PDT 24
Peak memory 195732 kb
Host smart-80d19888-0e4f-4d73-9c61-4a656f75adfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924252168 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3924252168
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.807739188
Short name T732
Test name
Test status
Simulation time 30459437 ps
CPU time 0.64 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:14 PM PDT 24
Peak memory 195576 kb
Host smart-13666a2c-9324-4c79-865f-c9560103807b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807739188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.807739188
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3990513704
Short name T738
Test name
Test status
Simulation time 68984481 ps
CPU time 0.64 seconds
Started Jul 23 06:16:05 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 195440 kb
Host smart-3fe1db4d-6464-4b41-9dd3-7d51f9efb02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990513704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3990513704
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1067944970
Short name T701
Test name
Test status
Simulation time 105000079 ps
CPU time 0.74 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 197836 kb
Host smart-901ef76e-2391-47dd-9f97-1a189dc9dd3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067944970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.1067944970
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3175834416
Short name T703
Test name
Test status
Simulation time 40993257 ps
CPU time 1.77 seconds
Started Jul 23 06:16:08 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 196852 kb
Host smart-320cb79e-b805-469f-affc-874ec8f024e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175834416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3175834416
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2142888585
Short name T74
Test name
Test status
Simulation time 1608794240 ps
CPU time 1.75 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 195844 kb
Host smart-90d09cd2-e3fd-4fcb-b774-940770481d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142888585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.2142888585
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.579239225
Short name T75
Test name
Test status
Simulation time 39033139 ps
CPU time 0.76 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:14 PM PDT 24
Peak memory 195752 kb
Host smart-194d0b10-f02e-44ff-bf6f-5e0a90100957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579239225 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.579239225
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2252963628
Short name T632
Test name
Test status
Simulation time 50145221 ps
CPU time 0.63 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 195640 kb
Host smart-a9e7d9c9-c1b9-46c2-b1c5-c19800638b97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252963628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2252963628
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3182850532
Short name T689
Test name
Test status
Simulation time 20027366 ps
CPU time 0.62 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 195516 kb
Host smart-5fba8439-9bbb-4dd4-9e7e-569e1814c87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182850532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3182850532
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.215197627
Short name T118
Test name
Test status
Simulation time 65742954 ps
CPU time 0.71 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 197800 kb
Host smart-a7120219-f81a-4906-acad-9a1a5c182907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215197627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.215197627
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.311420942
Short name T729
Test name
Test status
Simulation time 65222145 ps
CPU time 1.47 seconds
Started Jul 23 06:16:12 PM PDT 24
Finished Jul 23 06:16:15 PM PDT 24
Peak memory 197160 kb
Host smart-cda12bee-b254-424b-a949-3f8c8efaf444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311420942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.311420942
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2474218014
Short name T679
Test name
Test status
Simulation time 135021707 ps
CPU time 1.14 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 200852 kb
Host smart-e31c10e1-5aa4-4a74-a972-1584d602fd15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474218014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.2474218014
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.624479597
Short name T694
Test name
Test status
Simulation time 88243756 ps
CPU time 0.79 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:14 PM PDT 24
Peak memory 195744 kb
Host smart-caab2f6b-e15e-4ecb-8639-c7ce2eb4b1db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624479597 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.624479597
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3837354586
Short name T115
Test name
Test status
Simulation time 18939626 ps
CPU time 0.63 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195552 kb
Host smart-ba480437-9645-4ed9-b000-40aa351bb474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837354586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3837354586
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4031002655
Short name T675
Test name
Test status
Simulation time 40640484 ps
CPU time 0.62 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 195544 kb
Host smart-df574011-a7cb-4609-a726-ace3036298e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031002655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4031002655
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3103449217
Short name T685
Test name
Test status
Simulation time 34131010 ps
CPU time 0.82 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 195584 kb
Host smart-86d3460b-c2c2-4fd7-b9f0-ba0e080d18b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103449217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3103449217
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1490058554
Short name T60
Test name
Test status
Simulation time 25931631 ps
CPU time 1.05 seconds
Started Jul 23 06:16:09 PM PDT 24
Finished Jul 23 06:16:11 PM PDT 24
Peak memory 196660 kb
Host smart-69179fcc-cbf2-4311-9fe5-e700991cce79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490058554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1490058554
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3788288057
Short name T73
Test name
Test status
Simulation time 187485395 ps
CPU time 1.65 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 201084 kb
Host smart-4d9a5ba7-9db4-4a2b-93f1-c96ae5567e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788288057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3788288057
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.747473899
Short name T105
Test name
Test status
Simulation time 61979332 ps
CPU time 0.75 seconds
Started Jul 23 06:15:43 PM PDT 24
Finished Jul 23 06:15:45 PM PDT 24
Peak memory 197860 kb
Host smart-c1b73d82-dd98-4d11-a52f-7aeba5befcee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747473899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.747473899
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4275255451
Short name T674
Test name
Test status
Simulation time 43958149 ps
CPU time 1.73 seconds
Started Jul 23 06:15:43 PM PDT 24
Finished Jul 23 06:15:46 PM PDT 24
Peak memory 199368 kb
Host smart-0776a210-a1a2-427e-81c1-c1fe5b826a42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275255451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.4
275255451
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2316799146
Short name T108
Test name
Test status
Simulation time 31987686 ps
CPU time 0.7 seconds
Started Jul 23 06:15:43 PM PDT 24
Finished Jul 23 06:15:45 PM PDT 24
Peak memory 195604 kb
Host smart-bedffb21-e440-485d-bb3d-319aa7382e54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316799146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
316799146
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.779334173
Short name T662
Test name
Test status
Simulation time 42896357 ps
CPU time 1.01 seconds
Started Jul 23 06:15:43 PM PDT 24
Finished Jul 23 06:15:44 PM PDT 24
Peak memory 196640 kb
Host smart-2cfb4698-f8e0-45c0-9499-7a2e9d501d35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779334173 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.779334173
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.650371368
Short name T686
Test name
Test status
Simulation time 17307322 ps
CPU time 0.63 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:49 PM PDT 24
Peak memory 195548 kb
Host smart-ac4c35e4-bdaf-40c9-ba00-808cca73f6fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650371368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.650371368
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3406687544
Short name T690
Test name
Test status
Simulation time 16082613 ps
CPU time 0.61 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:48 PM PDT 24
Peak memory 195492 kb
Host smart-b6a59c66-f95c-4550-91fb-cd2573608306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406687544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3406687544
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2066052957
Short name T654
Test name
Test status
Simulation time 19317236 ps
CPU time 0.73 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:50 PM PDT 24
Peak memory 195584 kb
Host smart-7bab43d4-c145-4600-b838-5d9f667931f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066052957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2066052957
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3248563454
Short name T735
Test name
Test status
Simulation time 128808596 ps
CPU time 1.57 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 196784 kb
Host smart-03d95cc6-babd-4623-83c5-9d31e8e63eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248563454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3248563454
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2943230222
Short name T79
Test name
Test status
Simulation time 122676572 ps
CPU time 1.11 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:46 PM PDT 24
Peak memory 195864 kb
Host smart-3030c6c1-e8ed-4173-ab75-c3efc78f3ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943230222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.2943230222
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.792973210
Short name T731
Test name
Test status
Simulation time 18879276 ps
CPU time 0.63 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 195528 kb
Host smart-bee289f4-615e-40f0-b0a1-b190636b9206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792973210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.792973210
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.107088248
Short name T734
Test name
Test status
Simulation time 26635556 ps
CPU time 0.61 seconds
Started Jul 23 06:16:11 PM PDT 24
Finished Jul 23 06:16:13 PM PDT 24
Peak memory 195560 kb
Host smart-18a43332-8641-4941-9094-722f913547db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107088248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.107088248
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.262766418
Short name T733
Test name
Test status
Simulation time 107956525 ps
CPU time 0.6 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195520 kb
Host smart-62e1d547-51fc-4476-82a3-1957cb41ca92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262766418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.262766418
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1557697009
Short name T682
Test name
Test status
Simulation time 232340462 ps
CPU time 0.61 seconds
Started Jul 23 06:16:10 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 195532 kb
Host smart-d34c0f94-de30-4440-8358-bbce6aff8908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557697009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1557697009
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2063975500
Short name T695
Test name
Test status
Simulation time 23251656 ps
CPU time 0.6 seconds
Started Jul 23 06:16:16 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195512 kb
Host smart-cd8569d0-9326-4e28-aa58-180053fdaea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063975500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2063975500
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3962178938
Short name T641
Test name
Test status
Simulation time 20615296 ps
CPU time 0.63 seconds
Started Jul 23 06:16:13 PM PDT 24
Finished Jul 23 06:16:15 PM PDT 24
Peak memory 195524 kb
Host smart-f87a82d7-4e4f-449f-af25-ec62ca5d4421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962178938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3962178938
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3950907036
Short name T728
Test name
Test status
Simulation time 47657515 ps
CPU time 0.58 seconds
Started Jul 23 06:16:14 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195516 kb
Host smart-f7bee84c-efa1-4bd3-8cc3-b25322d3afc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950907036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3950907036
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3421221121
Short name T665
Test name
Test status
Simulation time 32996057 ps
CPU time 0.61 seconds
Started Jul 23 06:16:16 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195472 kb
Host smart-15c8f7ff-4529-4560-92e5-fd28b6f06980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421221121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3421221121
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.1723762971
Short name T713
Test name
Test status
Simulation time 18441694 ps
CPU time 0.63 seconds
Started Jul 23 06:16:15 PM PDT 24
Finished Jul 23 06:16:17 PM PDT 24
Peak memory 195456 kb
Host smart-d86981d9-b8c4-46b6-ba41-862f8307a797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723762971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.1723762971
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.881885537
Short name T715
Test name
Test status
Simulation time 89356504 ps
CPU time 0.62 seconds
Started Jul 23 06:16:15 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195536 kb
Host smart-6e602167-27be-446b-acae-5f227c5260ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881885537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.881885537
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3903243073
Short name T730
Test name
Test status
Simulation time 30512032 ps
CPU time 0.75 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:50 PM PDT 24
Peak memory 197784 kb
Host smart-ae1979ea-7b00-48a1-85cb-7a56b2bb531a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903243073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
903243073
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.264551508
Short name T113
Test name
Test status
Simulation time 1055661679 ps
CPU time 3.38 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 195640 kb
Host smart-3927c059-3285-411c-ace3-d2f4de2f472c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264551508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.264551508
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2520677136
Short name T664
Test name
Test status
Simulation time 25593453 ps
CPU time 0.65 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:45 PM PDT 24
Peak memory 198220 kb
Host smart-2164610e-ff0d-4064-82c0-85cba1783fbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520677136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
520677136
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.556966478
Short name T678
Test name
Test status
Simulation time 93901710 ps
CPU time 0.9 seconds
Started Jul 23 06:15:47 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 195732 kb
Host smart-1c045bf2-a3b7-4834-a5b2-2495e2353323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556966478 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.556966478
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3632074811
Short name T693
Test name
Test status
Simulation time 24024082 ps
CPU time 0.76 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:47 PM PDT 24
Peak memory 197772 kb
Host smart-8bd905e7-d5b2-4632-a0fc-53d02b8091fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632074811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3632074811
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2354626543
Short name T661
Test name
Test status
Simulation time 31933040 ps
CPU time 0.61 seconds
Started Jul 23 06:15:47 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 195488 kb
Host smart-f18c3136-b3f3-4db0-b933-5da09a87384d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354626543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.2354626543
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3632641082
Short name T120
Test name
Test status
Simulation time 27897625 ps
CPU time 0.86 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:48 PM PDT 24
Peak memory 199144 kb
Host smart-4209de2e-baad-45aa-8c1b-e0836708a5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632641082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3632641082
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1118996611
Short name T717
Test name
Test status
Simulation time 350226612 ps
CPU time 1.98 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:50 PM PDT 24
Peak memory 198208 kb
Host smart-5aa825f2-903f-4252-9cfb-f8219b76edeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118996611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1118996611
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2711080539
Short name T23
Test name
Test status
Simulation time 365889684 ps
CPU time 1.52 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:46 PM PDT 24
Peak memory 201112 kb
Host smart-b6e96b62-77af-4a94-b8e6-00e65b925036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711080539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2711080539
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1798795245
Short name T684
Test name
Test status
Simulation time 150559888 ps
CPU time 0.61 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195480 kb
Host smart-6d15590f-1463-4b7e-8dc0-4efa5228ca2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798795245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1798795245
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1925335714
Short name T671
Test name
Test status
Simulation time 66992546 ps
CPU time 0.62 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195552 kb
Host smart-92c93cb5-45b8-4a0b-9403-19b989d5b3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925335714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1925335714
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.895156949
Short name T151
Test name
Test status
Simulation time 17481808 ps
CPU time 0.62 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:19 PM PDT 24
Peak memory 195504 kb
Host smart-800c6d24-fd0a-42a9-abf2-6a0ef26dd5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895156949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.895156949
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2210442677
Short name T636
Test name
Test status
Simulation time 53774425 ps
CPU time 0.6 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:19 PM PDT 24
Peak memory 195504 kb
Host smart-b4a93000-c13e-4ca2-aefb-e0ed419c64f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210442677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2210442677
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3692510040
Short name T727
Test name
Test status
Simulation time 135481003 ps
CPU time 0.61 seconds
Started Jul 23 06:16:16 PM PDT 24
Finished Jul 23 06:16:17 PM PDT 24
Peak memory 195548 kb
Host smart-38d828cd-8d20-4be0-bf05-15dfd6ecd229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692510040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3692510040
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1734539139
Short name T687
Test name
Test status
Simulation time 44029861 ps
CPU time 0.59 seconds
Started Jul 23 06:16:15 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195556 kb
Host smart-a59cf2a8-a84a-46f4-850e-4a50a86b0f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734539139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1734539139
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.4234782891
Short name T681
Test name
Test status
Simulation time 23018866 ps
CPU time 0.61 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:19 PM PDT 24
Peak memory 195472 kb
Host smart-029bce75-a87b-4883-bbc0-bacf6c2d5701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234782891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.4234782891
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.735168707
Short name T669
Test name
Test status
Simulation time 18950984 ps
CPU time 0.66 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:19 PM PDT 24
Peak memory 195540 kb
Host smart-c07c2648-f90d-4670-b5a5-7bf69269e3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735168707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.735168707
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2597259223
Short name T712
Test name
Test status
Simulation time 19281203 ps
CPU time 0.64 seconds
Started Jul 23 06:16:14 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195556 kb
Host smart-c65357ad-1245-4c85-835b-504f780faffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597259223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2597259223
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2145635841
Short name T688
Test name
Test status
Simulation time 20306823 ps
CPU time 0.62 seconds
Started Jul 23 06:16:15 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195564 kb
Host smart-93d4b004-c4e8-4500-8d37-67b16c8b16b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145635841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2145635841
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3555783065
Short name T109
Test name
Test status
Simulation time 28983348 ps
CPU time 0.77 seconds
Started Jul 23 06:15:43 PM PDT 24
Finished Jul 23 06:15:45 PM PDT 24
Peak memory 197776 kb
Host smart-5fbc1f2d-baaa-4088-a3e5-397478b674a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555783065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3
555783065
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1640039507
Short name T668
Test name
Test status
Simulation time 118315669 ps
CPU time 2.8 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 199496 kb
Host smart-6b702741-5ec8-4544-a2ec-27b8ac5de7f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640039507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
640039507
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.163053272
Short name T666
Test name
Test status
Simulation time 41368601 ps
CPU time 0.68 seconds
Started Jul 23 06:15:47 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 195568 kb
Host smart-92da60b2-bfc8-459d-be7a-67875c0a7af8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163053272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.163053272
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1256936844
Short name T722
Test name
Test status
Simulation time 47032246 ps
CPU time 0.98 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:46 PM PDT 24
Peak memory 196648 kb
Host smart-9b6c9204-f588-4905-be5b-b4d9930af1aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256936844 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1256936844
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.269243955
Short name T707
Test name
Test status
Simulation time 19091224 ps
CPU time 0.61 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:48 PM PDT 24
Peak memory 195608 kb
Host smart-bc1875bb-0231-4f6a-a8db-26540a21ffc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269243955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.269243955
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3184601499
Short name T726
Test name
Test status
Simulation time 47769936 ps
CPU time 0.62 seconds
Started Jul 23 06:15:46 PM PDT 24
Finished Jul 23 06:15:50 PM PDT 24
Peak memory 195460 kb
Host smart-505017ec-1bdb-4316-b63a-aebb57268eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184601499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3184601499
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1049211896
Short name T116
Test name
Test status
Simulation time 22726328 ps
CPU time 0.73 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195560 kb
Host smart-d8199e2a-b920-4783-a702-bcd7b5a9fc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049211896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1049211896
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2039273262
Short name T24
Test name
Test status
Simulation time 80631264 ps
CPU time 1.92 seconds
Started Jul 23 06:15:44 PM PDT 24
Finished Jul 23 06:15:48 PM PDT 24
Peak memory 196028 kb
Host smart-ae86dad3-e66b-449b-89a1-d4084712bba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039273262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2039273262
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1805856045
Short name T78
Test name
Test status
Simulation time 393475489 ps
CPU time 1.68 seconds
Started Jul 23 06:15:45 PM PDT 24
Finished Jul 23 06:15:50 PM PDT 24
Peak memory 195844 kb
Host smart-4f0a804a-62ec-46cb-8632-7cead68fc055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805856045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1805856045
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2874058781
Short name T705
Test name
Test status
Simulation time 19871459 ps
CPU time 0.64 seconds
Started Jul 23 06:16:14 PM PDT 24
Finished Jul 23 06:16:16 PM PDT 24
Peak memory 195520 kb
Host smart-d9de1d92-5610-413f-9cd1-e0cb5bbccfc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874058781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2874058781
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1765525431
Short name T673
Test name
Test status
Simulation time 22068579 ps
CPU time 0.65 seconds
Started Jul 23 06:16:16 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195524 kb
Host smart-89a3f786-7226-459c-a89f-df88bcd35dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765525431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1765525431
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3466082340
Short name T667
Test name
Test status
Simulation time 45995565 ps
CPU time 0.67 seconds
Started Jul 23 06:16:17 PM PDT 24
Finished Jul 23 06:16:19 PM PDT 24
Peak memory 195516 kb
Host smart-199c818b-7c33-4ff9-9e56-5e281a728197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466082340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3466082340
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3124828627
Short name T651
Test name
Test status
Simulation time 144932480 ps
CPU time 0.61 seconds
Started Jul 23 06:16:16 PM PDT 24
Finished Jul 23 06:16:18 PM PDT 24
Peak memory 195520 kb
Host smart-b44ccc24-ea50-4568-8bd5-bf67b71117be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124828627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.3124828627
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1402219537
Short name T644
Test name
Test status
Simulation time 20453284 ps
CPU time 0.64 seconds
Started Jul 23 06:16:15 PM PDT 24
Finished Jul 23 06:16:17 PM PDT 24
Peak memory 195536 kb
Host smart-ef421af4-0fab-4672-a7ff-a913af8c105c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402219537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1402219537
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3813681176
Short name T720
Test name
Test status
Simulation time 20256795 ps
CPU time 0.65 seconds
Started Jul 23 06:16:22 PM PDT 24
Finished Jul 23 06:16:24 PM PDT 24
Peak memory 195552 kb
Host smart-b7297337-0e48-42be-8e9f-465b90d6f77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813681176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3813681176
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1072724866
Short name T676
Test name
Test status
Simulation time 89930142 ps
CPU time 0.64 seconds
Started Jul 23 06:16:19 PM PDT 24
Finished Jul 23 06:16:20 PM PDT 24
Peak memory 195448 kb
Host smart-5f719541-2e39-4722-8759-ecbe2d7378f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072724866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1072724866
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.681133360
Short name T711
Test name
Test status
Simulation time 20097752 ps
CPU time 0.6 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:28 PM PDT 24
Peak memory 195516 kb
Host smart-067af1fe-e97b-4a5a-b9ed-a155da263ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681133360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.681133360
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1698415387
Short name T650
Test name
Test status
Simulation time 21533270 ps
CPU time 0.64 seconds
Started Jul 23 06:16:19 PM PDT 24
Finished Jul 23 06:16:20 PM PDT 24
Peak memory 195508 kb
Host smart-f903c9a8-3568-44f0-ab9f-ce4fee9894ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698415387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1698415387
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3734902264
Short name T677
Test name
Test status
Simulation time 45795238 ps
CPU time 0.71 seconds
Started Jul 23 06:16:41 PM PDT 24
Finished Jul 23 06:16:42 PM PDT 24
Peak memory 200968 kb
Host smart-e8e15e26-3b47-470d-8ed0-5cd325112604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734902264 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3734902264
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.2441719631
Short name T659
Test name
Test status
Simulation time 19870041 ps
CPU time 0.64 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195616 kb
Host smart-810ee6f8-f318-4dbf-a3b3-30f37c0a6ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441719631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2441719631
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4254208665
Short name T739
Test name
Test status
Simulation time 50552268 ps
CPU time 0.62 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195460 kb
Host smart-02fdc58d-49ad-4e88-a687-3d27283c5264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254208665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.4254208665
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1374485641
Short name T642
Test name
Test status
Simulation time 66997949 ps
CPU time 0.92 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195584 kb
Host smart-a22f8032-ddee-40fb-b71f-1bb2b959592d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374485641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.1374485641
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2407241897
Short name T670
Test name
Test status
Simulation time 140419884 ps
CPU time 1.63 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 201168 kb
Host smart-1290bb64-163f-4261-b967-3e82ed8f9e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407241897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2407241897
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2894822729
Short name T134
Test name
Test status
Simulation time 268925736 ps
CPU time 1.5 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 201128 kb
Host smart-97025f40-d3b8-4b42-a33e-0b17b7ebe45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894822729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2894822729
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3044887700
Short name T643
Test name
Test status
Simulation time 132896786 ps
CPU time 1.05 seconds
Started Jul 23 06:15:51 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 195688 kb
Host smart-af575077-ee90-4cc2-a41c-162525e32c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044887700 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.3044887700
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2741805295
Short name T104
Test name
Test status
Simulation time 47062482 ps
CPU time 0.65 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 195600 kb
Host smart-28bee15c-1b80-467c-ae05-9d272a3569e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741805295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2741805295
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3491961184
Short name T724
Test name
Test status
Simulation time 51935238 ps
CPU time 0.65 seconds
Started Jul 23 06:15:53 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 195520 kb
Host smart-cc3e80f9-ba03-49f4-9c4e-83ba3735f457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491961184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3491961184
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3389034671
Short name T672
Test name
Test status
Simulation time 78772204 ps
CPU time 0.75 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195572 kb
Host smart-c8ddc7fb-9336-44a5-8101-4d6c75aa0c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389034671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.3389034671
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.644335604
Short name T639
Test name
Test status
Simulation time 107035443 ps
CPU time 1.49 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 196852 kb
Host smart-412733c5-9bde-400b-8e5c-74f51af8d3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644335604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.644335604
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.702564504
Short name T700
Test name
Test status
Simulation time 96978302 ps
CPU time 1.13 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 195800 kb
Host smart-8b749f21-7dc0-415d-8c33-5aa8097470cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702564504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.
702564504
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.442487774
Short name T737
Test name
Test status
Simulation time 61776818 ps
CPU time 1.03 seconds
Started Jul 23 06:15:51 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 195772 kb
Host smart-ec457791-4f7d-4cf5-86dc-e62b7d2ee95a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442487774 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.442487774
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3724521328
Short name T132
Test name
Test status
Simulation time 69513110 ps
CPU time 0.63 seconds
Started Jul 23 06:15:48 PM PDT 24
Finished Jul 23 06:15:52 PM PDT 24
Peak memory 195540 kb
Host smart-47ddd899-a08d-4bfe-8636-6583d1a50aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724521328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3724521328
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3512786840
Short name T635
Test name
Test status
Simulation time 144100946 ps
CPU time 0.62 seconds
Started Jul 23 06:15:50 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 195556 kb
Host smart-646893c7-252c-49f5-b132-d8710722849f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512786840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3512786840
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3791447116
Short name T725
Test name
Test status
Simulation time 62803093 ps
CPU time 0.88 seconds
Started Jul 23 06:15:58 PM PDT 24
Finished Jul 23 06:16:00 PM PDT 24
Peak memory 198808 kb
Host smart-8328e956-2e77-41ee-a597-2a64989154eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791447116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.3791447116
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2154990189
Short name T663
Test name
Test status
Simulation time 282137677 ps
CPU time 1.65 seconds
Started Jul 23 06:15:51 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 196848 kb
Host smart-183ded5a-1e73-42d2-9c71-22e0b1748f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154990189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2154990189
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2789301716
Short name T709
Test name
Test status
Simulation time 639561912 ps
CPU time 1.09 seconds
Started Jul 23 06:15:47 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 195676 kb
Host smart-2bdf1270-6dc2-4886-975a-ac404ba18b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789301716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2789301716
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2080696807
Short name T699
Test name
Test status
Simulation time 54383723 ps
CPU time 1.44 seconds
Started Jul 23 06:15:55 PM PDT 24
Finished Jul 23 06:15:58 PM PDT 24
Peak memory 201216 kb
Host smart-c73549c3-df42-460d-ac7e-b719d560c92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080696807 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2080696807
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3361283259
Short name T110
Test name
Test status
Simulation time 53883630 ps
CPU time 0.64 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 197796 kb
Host smart-8c05dc44-b83f-465f-ba6f-28ce8fa84287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361283259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3361283259
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3926600399
Short name T152
Test name
Test status
Simulation time 16906891 ps
CPU time 0.62 seconds
Started Jul 23 06:15:47 PM PDT 24
Finished Jul 23 06:15:51 PM PDT 24
Peak memory 195544 kb
Host smart-c8399882-a0b1-457e-aa57-f0eaeab0f3d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926600399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3926600399
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3830359882
Short name T117
Test name
Test status
Simulation time 121378739 ps
CPU time 0.87 seconds
Started Jul 23 06:15:51 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 200352 kb
Host smart-664d0370-67fd-4473-b031-55c448f84be4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830359882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.3830359882
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1877873768
Short name T67
Test name
Test status
Simulation time 97470383 ps
CPU time 2.48 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 196900 kb
Host smart-520ac9f5-8d28-4920-98fd-320a2806b26e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877873768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1877873768
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3343579584
Short name T706
Test name
Test status
Simulation time 174342657 ps
CPU time 1.11 seconds
Started Jul 23 06:15:49 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 200824 kb
Host smart-d6092bf7-130f-4dcb-b3de-cf9c2da4641d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343579584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.3343579584
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.260061909
Short name T719
Test name
Test status
Simulation time 67877097 ps
CPU time 1.5 seconds
Started Jul 23 06:15:55 PM PDT 24
Finished Jul 23 06:15:57 PM PDT 24
Peak memory 199188 kb
Host smart-c254a8a3-906f-4b9f-9e24-2230e603b547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260061909 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.260061909
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.166969150
Short name T114
Test name
Test status
Simulation time 51718786 ps
CPU time 0.63 seconds
Started Jul 23 06:15:58 PM PDT 24
Finished Jul 23 06:15:59 PM PDT 24
Peak memory 197760 kb
Host smart-7d32ceb2-512f-4fc3-9bea-0b0b32ed60a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166969150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.166969150
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3246155597
Short name T149
Test name
Test status
Simulation time 25077209 ps
CPU time 0.61 seconds
Started Jul 23 06:15:56 PM PDT 24
Finished Jul 23 06:15:57 PM PDT 24
Peak memory 195480 kb
Host smart-0fffb684-1ea6-4b1a-84c9-283e14e7723a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246155597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3246155597
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2550375622
Short name T649
Test name
Test status
Simulation time 132376438 ps
CPU time 0.74 seconds
Started Jul 23 06:15:54 PM PDT 24
Finished Jul 23 06:15:56 PM PDT 24
Peak memory 195560 kb
Host smart-ab920067-0b0a-4707-abcf-83990dd791f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550375622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2550375622
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2174519261
Short name T646
Test name
Test status
Simulation time 72745416 ps
CPU time 1.74 seconds
Started Jul 23 06:15:55 PM PDT 24
Finished Jul 23 06:15:58 PM PDT 24
Peak memory 196864 kb
Host smart-e38ddf82-3b71-4502-940f-d2728989191b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174519261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2174519261
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2570567205
Short name T130
Test name
Test status
Simulation time 115673651 ps
CPU time 1.12 seconds
Started Jul 23 06:15:53 PM PDT 24
Finished Jul 23 06:15:55 PM PDT 24
Peak memory 200916 kb
Host smart-7ac2df99-da1a-425c-9214-e7e6181b53c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570567205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2570567205
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1298779370
Short name T155
Test name
Test status
Simulation time 77614009 ps
CPU time 0.65 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:21 PM PDT 24
Peak memory 198868 kb
Host smart-727eb0a6-804c-4073-815f-0a518ca0beed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298779370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1298779370
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1782268190
Short name T355
Test name
Test status
Simulation time 39209425 ps
CPU time 0.57 seconds
Started Jul 23 06:16:28 PM PDT 24
Finished Jul 23 06:16:33 PM PDT 24
Peak memory 198532 kb
Host smart-51696d42-41d0-4e05-a051-e8e7fd6b09c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782268190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1782268190
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.2060388331
Short name T392
Test name
Test status
Simulation time 158827072 ps
CPU time 0.92 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:28 PM PDT 24
Peak memory 198672 kb
Host smart-e1d94175-6953-4b55-b35e-e721a5c3ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060388331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.2060388331
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.2306773902
Short name T271
Test name
Test status
Simulation time 34250007 ps
CPU time 0.6 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:21 PM PDT 24
Peak memory 198604 kb
Host smart-f078b5ad-66e9-4f3b-a3f9-195344df2e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306773902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.2306773902
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3215107614
Short name T255
Test name
Test status
Simulation time 47968116 ps
CPU time 0.62 seconds
Started Jul 23 06:16:21 PM PDT 24
Finished Jul 23 06:16:23 PM PDT 24
Peak memory 198652 kb
Host smart-3e0deea9-de27-4bb0-9e88-0bb9cc3fec8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215107614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3215107614
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2811855708
Short name T162
Test name
Test status
Simulation time 54344139 ps
CPU time 0.67 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:22 PM PDT 24
Peak memory 201816 kb
Host smart-d850cc53-a283-4cf2-a7e9-4901dff481b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811855708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2811855708
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.2181857725
Short name T145
Test name
Test status
Simulation time 84430288 ps
CPU time 0.67 seconds
Started Jul 23 06:16:24 PM PDT 24
Finished Jul 23 06:16:26 PM PDT 24
Peak memory 198792 kb
Host smart-b776f97d-9001-42f4-90ac-9e8385dbd050
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181857725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.2181857725
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3545993084
Short name T420
Test name
Test status
Simulation time 113855509 ps
CPU time 0.73 seconds
Started Jul 23 06:16:19 PM PDT 24
Finished Jul 23 06:16:20 PM PDT 24
Peak memory 199732 kb
Host smart-d1f75654-dd87-4afd-89d4-e60a3d09094d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545993084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3545993084
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.505099643
Short name T207
Test name
Test status
Simulation time 103044615 ps
CPU time 1.01 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:28 PM PDT 24
Peak memory 210092 kb
Host smart-f15e53e7-8b77-491d-9f5d-22d04f63d802
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505099643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.505099643
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3247862710
Short name T356
Test name
Test status
Simulation time 114235426 ps
CPU time 0.8 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:22 PM PDT 24
Peak memory 200108 kb
Host smart-4ee7388a-ca93-4de0-a04e-60df24b68ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247862710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3247862710
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.3798639727
Short name T562
Test name
Test status
Simulation time 183709574 ps
CPU time 0.6 seconds
Started Jul 23 06:16:28 PM PDT 24
Finished Jul 23 06:16:33 PM PDT 24
Peak memory 198976 kb
Host smart-010ae741-d588-435e-9774-6adb83363207
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798639727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3798639727
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1355301231
Short name T594
Test name
Test status
Simulation time 30820116 ps
CPU time 0.76 seconds
Started Jul 23 06:16:24 PM PDT 24
Finished Jul 23 06:16:26 PM PDT 24
Peak memory 199368 kb
Host smart-22230ad3-6498-4da0-843e-457be123850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355301231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1355301231
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1717225080
Short name T597
Test name
Test status
Simulation time 73108051 ps
CPU time 0.66 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:28 PM PDT 24
Peak memory 199636 kb
Host smart-728d8087-0f2f-40ee-8090-8c47127590fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717225080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1717225080
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2547230965
Short name T341
Test name
Test status
Simulation time 58920587 ps
CPU time 0.59 seconds
Started Jul 23 06:16:27 PM PDT 24
Finished Jul 23 06:16:31 PM PDT 24
Peak memory 198532 kb
Host smart-65c171d1-157a-453c-900f-ee5b4e0a8288
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547230965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.2547230965
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.3178621602
Short name T411
Test name
Test status
Simulation time 801091196 ps
CPU time 0.95 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:30 PM PDT 24
Peak memory 198624 kb
Host smart-24e44263-de88-4fc3-a7be-09a0a0b0d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178621602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3178621602
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3325824360
Short name T544
Test name
Test status
Simulation time 72907261 ps
CPU time 0.63 seconds
Started Jul 23 06:16:27 PM PDT 24
Finished Jul 23 06:16:31 PM PDT 24
Peak memory 198628 kb
Host smart-8025c2f3-26d2-4253-a579-ad256d75bd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325824360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3325824360
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.10829525
Short name T300
Test name
Test status
Simulation time 24264519 ps
CPU time 0.65 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:31 PM PDT 24
Peak memory 198952 kb
Host smart-69a18a54-9d91-4627-90fd-1c3a938ee327
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.10829525
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1559474450
Short name T241
Test name
Test status
Simulation time 62824260 ps
CPU time 0.63 seconds
Started Jul 23 06:16:28 PM PDT 24
Finished Jul 23 06:16:33 PM PDT 24
Peak memory 198688 kb
Host smart-bb7026b0-cc13-42b9-9a85-7ef6bc2c03b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559474450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1559474450
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.997355855
Short name T380
Test name
Test status
Simulation time 94868248 ps
CPU time 1.05 seconds
Started Jul 23 06:16:27 PM PDT 24
Finished Jul 23 06:16:32 PM PDT 24
Peak memory 210096 kb
Host smart-1c05a1f0-ebc7-4741-86f3-2f425511c6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997355855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.997355855
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1338968110
Short name T343
Test name
Test status
Simulation time 154882117 ps
CPU time 0.7 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:30 PM PDT 24
Peak memory 198608 kb
Host smart-d7fcf38a-fe26-4d95-b31d-54ac721f2249
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338968110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1338968110
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3568705364
Short name T554
Test name
Test status
Simulation time 31699497 ps
CPU time 0.67 seconds
Started Jul 23 06:16:20 PM PDT 24
Finished Jul 23 06:16:22 PM PDT 24
Peak memory 199080 kb
Host smart-79f1b2fc-2cc2-4d71-a0e3-a45715dd4924
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568705364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3568705364
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2452163659
Short name T467
Test name
Test status
Simulation time 24729132 ps
CPU time 0.91 seconds
Started Jul 23 06:17:00 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 200928 kb
Host smart-7bc70abc-21aa-4b77-9ab3-d59dd216649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452163659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2452163659
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.130852557
Short name T551
Test name
Test status
Simulation time 29413082 ps
CPU time 0.64 seconds
Started Jul 23 06:16:59 PM PDT 24
Finished Jul 23 06:17:01 PM PDT 24
Peak memory 198592 kb
Host smart-a079355f-f8eb-4205-9b37-813ed897de8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130852557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_
malfunc.130852557
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3312367350
Short name T253
Test name
Test status
Simulation time 324309040 ps
CPU time 1.03 seconds
Started Jul 23 06:17:00 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 198976 kb
Host smart-ef454171-e727-445e-978d-d120847379ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312367350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3312367350
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.4031679511
Short name T299
Test name
Test status
Simulation time 105586934 ps
CPU time 0.61 seconds
Started Jul 23 06:17:01 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 198656 kb
Host smart-d0d0c810-e69a-4e50-a1be-adeef53df56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031679511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.4031679511
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3791621351
Short name T189
Test name
Test status
Simulation time 56579973 ps
CPU time 0.7 seconds
Started Jul 23 06:16:59 PM PDT 24
Finished Jul 23 06:17:01 PM PDT 24
Peak memory 201952 kb
Host smart-a3d4b5c8-d66d-4d89-836d-84c4ef115cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791621351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3791621351
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2318450249
Short name T557
Test name
Test status
Simulation time 92889227 ps
CPU time 0.85 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 199088 kb
Host smart-797dd41e-0c17-4158-9cf4-7e90f011fd16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318450249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2318450249
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2034812284
Short name T470
Test name
Test status
Simulation time 111345337 ps
CPU time 0.94 seconds
Started Jul 23 06:16:59 PM PDT 24
Finished Jul 23 06:17:02 PM PDT 24
Peak memory 210080 kb
Host smart-ae6ecf9c-f9b5-4b0a-a4af-79fb6a36a616
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034812284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2034812284
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1516788111
Short name T334
Test name
Test status
Simulation time 86462286 ps
CPU time 0.75 seconds
Started Jul 23 06:17:02 PM PDT 24
Finished Jul 23 06:17:05 PM PDT 24
Peak memory 198676 kb
Host smart-7bf22136-2803-4c54-ab11-4852d7c35150
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516788111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1516788111
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2895572935
Short name T496
Test name
Test status
Simulation time 28946566 ps
CPU time 0.69 seconds
Started Jul 23 06:16:55 PM PDT 24
Finished Jul 23 06:16:58 PM PDT 24
Peak memory 199932 kb
Host smart-aa8594c6-8c27-4549-b9a4-d0cbd0bbc419
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895572935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2895572935
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2852899155
Short name T598
Test name
Test status
Simulation time 120548910 ps
CPU time 0.78 seconds
Started Jul 23 06:17:01 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 199380 kb
Host smart-e1c40743-bbd5-4dee-9d3d-028fffb74dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852899155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2852899155
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.308338854
Short name T578
Test name
Test status
Simulation time 70551648 ps
CPU time 0.76 seconds
Started Jul 23 06:17:06 PM PDT 24
Finished Jul 23 06:17:08 PM PDT 24
Peak memory 199712 kb
Host smart-c90fdc90-2d9d-422d-9ea6-46eecce38659
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308338854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.308338854
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3319583535
Short name T582
Test name
Test status
Simulation time 58279350 ps
CPU time 0.57 seconds
Started Jul 23 06:17:00 PM PDT 24
Finished Jul 23 06:17:03 PM PDT 24
Peak memory 197868 kb
Host smart-4e0de1f8-f4f1-4f4d-8779-33553ed4ca5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319583535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3319583535
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2957054522
Short name T210
Test name
Test status
Simulation time 32493706 ps
CPU time 0.64 seconds
Started Jul 23 06:17:09 PM PDT 24
Finished Jul 23 06:17:11 PM PDT 24
Peak memory 198512 kb
Host smart-3672305f-80b0-4a4e-aa93-fb1a830bd30b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957054522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2957054522
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.106967808
Short name T446
Test name
Test status
Simulation time 50453093 ps
CPU time 0.62 seconds
Started Jul 23 06:17:08 PM PDT 24
Finished Jul 23 06:17:10 PM PDT 24
Peak memory 198548 kb
Host smart-80b621d3-dd07-4d06-b399-052d686a67c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106967808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.106967808
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.774666293
Short name T177
Test name
Test status
Simulation time 77455448 ps
CPU time 0.65 seconds
Started Jul 23 06:17:12 PM PDT 24
Finished Jul 23 06:17:15 PM PDT 24
Peak memory 201988 kb
Host smart-b764693d-7cef-4267-9ba7-26a2fb99370f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774666293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.774666293
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.85653633
Short name T459
Test name
Test status
Simulation time 108862958 ps
CPU time 0.81 seconds
Started Jul 23 06:16:59 PM PDT 24
Finished Jul 23 06:17:02 PM PDT 24
Peak memory 199672 kb
Host smart-983914e2-ffb5-49c7-bec0-ad173ebe5aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85653633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.85653633
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2899047364
Short name T148
Test name
Test status
Simulation time 73044894 ps
CPU time 0.79 seconds
Started Jul 23 06:17:03 PM PDT 24
Finished Jul 23 06:17:05 PM PDT 24
Peak memory 198748 kb
Host smart-f31344aa-8b18-4109-b8c9-19abc09971fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899047364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2899047364
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.557818423
Short name T434
Test name
Test status
Simulation time 46934529 ps
CPU time 0.64 seconds
Started Jul 23 06:17:00 PM PDT 24
Finished Jul 23 06:17:03 PM PDT 24
Peak memory 199944 kb
Host smart-4efaab74-e194-4274-9b10-e5cbbe2070ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557818423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.557818423
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.596746941
Short name T608
Test name
Test status
Simulation time 33620071 ps
CPU time 0.75 seconds
Started Jul 23 06:17:09 PM PDT 24
Finished Jul 23 06:17:11 PM PDT 24
Peak memory 199376 kb
Host smart-bce5a36e-1036-4b80-b7c7-afe766d86ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596746941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.596746941
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2861041986
Short name T453
Test name
Test status
Simulation time 76328801 ps
CPU time 0.65 seconds
Started Jul 23 06:17:13 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 198952 kb
Host smart-fcab089b-5711-4200-acc3-e834a8b8983f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861041986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2861041986
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1179803016
Short name T290
Test name
Test status
Simulation time 50115020 ps
CPU time 0.6 seconds
Started Jul 23 06:17:06 PM PDT 24
Finished Jul 23 06:17:08 PM PDT 24
Peak memory 197904 kb
Host smart-2dfdb243-63aa-4562-bb10-d42c24423d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179803016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1179803016
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3929836390
Short name T565
Test name
Test status
Simulation time 1259145666 ps
CPU time 0.95 seconds
Started Jul 23 06:17:10 PM PDT 24
Finished Jul 23 06:17:12 PM PDT 24
Peak memory 198652 kb
Host smart-068c6370-996b-445f-b967-b71de46abf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929836390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3929836390
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.3293220791
Short name T447
Test name
Test status
Simulation time 54058144 ps
CPU time 0.63 seconds
Started Jul 23 06:17:04 PM PDT 24
Finished Jul 23 06:17:06 PM PDT 24
Peak memory 198628 kb
Host smart-da748891-01f0-4bd4-a035-4e3ddf998760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293220791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3293220791
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.2185285255
Short name T399
Test name
Test status
Simulation time 45509695 ps
CPU time 0.65 seconds
Started Jul 23 06:17:08 PM PDT 24
Finished Jul 23 06:17:10 PM PDT 24
Peak memory 198876 kb
Host smart-4252f433-15d9-4794-b543-8c210d3ed132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185285255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2185285255
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.1626570803
Short name T180
Test name
Test status
Simulation time 70690447 ps
CPU time 0.72 seconds
Started Jul 23 06:17:09 PM PDT 24
Finished Jul 23 06:17:12 PM PDT 24
Peak memory 201900 kb
Host smart-09d17de9-5ccb-438f-a03c-cc95366d4b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626570803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.1626570803
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.288936507
Short name T375
Test name
Test status
Simulation time 142951441 ps
CPU time 0.87 seconds
Started Jul 23 06:17:07 PM PDT 24
Finished Jul 23 06:17:09 PM PDT 24
Peak memory 199012 kb
Host smart-93875bc2-fe8f-448a-abf5-b80e44012abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288936507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.288936507
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2071130134
Short name T307
Test name
Test status
Simulation time 400815530 ps
CPU time 0.8 seconds
Started Jul 23 06:17:04 PM PDT 24
Finished Jul 23 06:17:07 PM PDT 24
Peak memory 210068 kb
Host smart-2ce3c333-0c97-4b4d-8e8c-10bdf1cf7084
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071130134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2071130134
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.331573923
Short name T408
Test name
Test status
Simulation time 142162266 ps
CPU time 0.7 seconds
Started Jul 23 06:17:08 PM PDT 24
Finished Jul 23 06:17:10 PM PDT 24
Peak memory 198800 kb
Host smart-d4981a01-74ef-43a4-9ab9-adad5ff613e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331573923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.331573923
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1375179321
Short name T462
Test name
Test status
Simulation time 15797227 ps
CPU time 0.65 seconds
Started Jul 23 06:17:11 PM PDT 24
Finished Jul 23 06:17:14 PM PDT 24
Peak memory 199716 kb
Host smart-dd94e676-7c54-4b59-a6d0-fbda593818e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375179321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1375179321
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3814825138
Short name T222
Test name
Test status
Simulation time 31139093 ps
CPU time 0.65 seconds
Started Jul 23 06:17:12 PM PDT 24
Finished Jul 23 06:17:15 PM PDT 24
Peak memory 198596 kb
Host smart-5ce6c663-df24-4942-9c68-1e764d6a340a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814825138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3814825138
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2039885467
Short name T347
Test name
Test status
Simulation time 165089687 ps
CPU time 0.98 seconds
Started Jul 23 06:17:12 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 198944 kb
Host smart-f338defd-63b9-40a6-ab8d-1a0d224de1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039885467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2039885467
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.409704287
Short name T275
Test name
Test status
Simulation time 296801465 ps
CPU time 0.62 seconds
Started Jul 23 06:17:13 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 198668 kb
Host smart-8d710634-449d-4a47-93ac-be03c25cfb3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409704287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.409704287
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2694112865
Short name T499
Test name
Test status
Simulation time 35869489 ps
CPU time 0.63 seconds
Started Jul 23 06:17:14 PM PDT 24
Finished Jul 23 06:17:17 PM PDT 24
Peak memory 198948 kb
Host smart-b7c50e28-09ae-43d1-93eb-14936dd0823a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694112865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2694112865
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.797527534
Short name T56
Test name
Test status
Simulation time 126091658 ps
CPU time 0.67 seconds
Started Jul 23 06:17:17 PM PDT 24
Finished Jul 23 06:17:19 PM PDT 24
Peak memory 201932 kb
Host smart-088bed85-7fab-438f-8e84-e5f3154dc0e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797527534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invali
d.797527534
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.4027827041
Short name T492
Test name
Test status
Simulation time 169219215 ps
CPU time 0.66 seconds
Started Jul 23 06:17:11 PM PDT 24
Finished Jul 23 06:17:14 PM PDT 24
Peak memory 199688 kb
Host smart-2902dd34-e2e3-492b-b263-675a36a1d5d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027827041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.4027827041
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.482140786
Short name T518
Test name
Test status
Simulation time 99184176 ps
CPU time 0.9 seconds
Started Jul 23 06:17:13 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 210068 kb
Host smart-4c95c4d9-a963-4e38-b02b-e44ba2bef67a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482140786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.482140786
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2053982836
Short name T488
Test name
Test status
Simulation time 63165995 ps
CPU time 0.88 seconds
Started Jul 23 06:17:11 PM PDT 24
Finished Jul 23 06:17:15 PM PDT 24
Peak memory 198660 kb
Host smart-2a0019b0-49c3-4039-91fb-38cff883024b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053982836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2053982836
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2224725355
Short name T252
Test name
Test status
Simulation time 30915381 ps
CPU time 0.64 seconds
Started Jul 23 06:17:09 PM PDT 24
Finished Jul 23 06:17:12 PM PDT 24
Peak memory 199940 kb
Host smart-4c45a376-98ed-4af7-a32e-784ffa7274d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224725355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2224725355
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.2872978534
Short name T197
Test name
Test status
Simulation time 286964051 ps
CPU time 0.81 seconds
Started Jul 23 06:17:16 PM PDT 24
Finished Jul 23 06:17:18 PM PDT 24
Peak memory 200144 kb
Host smart-31db7f6d-e691-4efd-a520-3e631c8256ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872978534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2872978534
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2695587135
Short name T424
Test name
Test status
Simulation time 153921897 ps
CPU time 0.66 seconds
Started Jul 23 06:17:14 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 199124 kb
Host smart-80df0a31-7bbd-4862-8218-22027ad6e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695587135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2695587135
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1996742553
Short name T36
Test name
Test status
Simulation time 68606896 ps
CPU time 0.73 seconds
Started Jul 23 06:17:19 PM PDT 24
Finished Jul 23 06:17:22 PM PDT 24
Peak memory 199044 kb
Host smart-008b4731-2428-4fd9-9c9a-70d37019885a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996742553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1996742553
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.317200214
Short name T138
Test name
Test status
Simulation time 35123590 ps
CPU time 0.64 seconds
Started Jul 23 06:17:10 PM PDT 24
Finished Jul 23 06:17:13 PM PDT 24
Peak memory 197836 kb
Host smart-331b07bb-3e4d-44d5-8268-4f49fe5bcc5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317200214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_
malfunc.317200214
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.982392573
Short name T491
Test name
Test status
Simulation time 309170056 ps
CPU time 1 seconds
Started Jul 23 06:17:19 PM PDT 24
Finished Jul 23 06:17:22 PM PDT 24
Peak memory 198556 kb
Host smart-0ad1dbaf-fcf0-47d4-9fe3-d8115e390bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982392573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.982392573
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2857800505
Short name T548
Test name
Test status
Simulation time 32918237 ps
CPU time 0.63 seconds
Started Jul 23 06:17:19 PM PDT 24
Finished Jul 23 06:17:22 PM PDT 24
Peak memory 198576 kb
Host smart-4c433843-d0d3-461a-9ef7-508c895ed582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857800505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2857800505
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1540502679
Short name T224
Test name
Test status
Simulation time 45361036 ps
CPU time 0.67 seconds
Started Jul 23 06:17:18 PM PDT 24
Finished Jul 23 06:17:21 PM PDT 24
Peak memory 198828 kb
Host smart-cc68e44b-b6a2-4213-9506-5a32d4d1623a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540502679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1540502679
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.147451294
Short name T184
Test name
Test status
Simulation time 44634007 ps
CPU time 0.7 seconds
Started Jul 23 06:17:19 PM PDT 24
Finished Jul 23 06:17:21 PM PDT 24
Peak memory 201964 kb
Host smart-d9719037-924d-4160-8f66-287b956fa6eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147451294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invali
d.147451294
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1486362559
Short name T246
Test name
Test status
Simulation time 53022667 ps
CPU time 0.79 seconds
Started Jul 23 06:17:12 PM PDT 24
Finished Jul 23 06:17:15 PM PDT 24
Peak memory 199676 kb
Host smart-1b1c46fb-b688-4494-96e9-a6831836a520
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486362559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1486362559
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3464778772
Short name T35
Test name
Test status
Simulation time 114084525 ps
CPU time 0.93 seconds
Started Jul 23 06:17:20 PM PDT 24
Finished Jul 23 06:17:23 PM PDT 24
Peak memory 210132 kb
Host smart-3bec6215-00b7-423f-b4b1-1f4cce7cc6f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464778772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3464778772
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.159115380
Short name T83
Test name
Test status
Simulation time 61356335 ps
CPU time 0.81 seconds
Started Jul 23 06:17:13 PM PDT 24
Finished Jul 23 06:17:16 PM PDT 24
Peak memory 198656 kb
Host smart-2ebc3320-c124-42e6-84b9-68aeb3bc3cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159115380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.159115380
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1139448853
Short name T622
Test name
Test status
Simulation time 33871353 ps
CPU time 0.65 seconds
Started Jul 23 06:17:09 PM PDT 24
Finished Jul 23 06:17:12 PM PDT 24
Peak memory 199940 kb
Host smart-23053da2-41d2-4842-8b86-e702b9c171da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139448853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1139448853
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.843962251
Short name T502
Test name
Test status
Simulation time 35635220 ps
CPU time 0.78 seconds
Started Jul 23 06:17:17 PM PDT 24
Finished Jul 23 06:17:20 PM PDT 24
Peak memory 199392 kb
Host smart-ee1aa624-a8d7-462c-9802-650b532162af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843962251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.843962251
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2301659597
Short name T274
Test name
Test status
Simulation time 32057760 ps
CPU time 0.63 seconds
Started Jul 23 06:17:22 PM PDT 24
Finished Jul 23 06:17:25 PM PDT 24
Peak memory 198560 kb
Host smart-e2737716-9afc-40bd-b045-09ad4df8e344
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301659597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2301659597
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.23062450
Short name T503
Test name
Test status
Simulation time 716616880 ps
CPU time 0.96 seconds
Started Jul 23 06:17:22 PM PDT 24
Finished Jul 23 06:17:25 PM PDT 24
Peak memory 198608 kb
Host smart-2f2f0137-f218-4742-a2a3-efd6286296ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23062450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.23062450
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2143811994
Short name T291
Test name
Test status
Simulation time 81158459 ps
CPU time 0.63 seconds
Started Jul 23 06:17:24 PM PDT 24
Finished Jul 23 06:17:27 PM PDT 24
Peak memory 198652 kb
Host smart-ee4841dc-ab8e-482f-9a9b-f4ad448b135b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143811994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2143811994
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1868053902
Short name T314
Test name
Test status
Simulation time 42144341 ps
CPU time 0.59 seconds
Started Jul 23 06:17:18 PM PDT 24
Finished Jul 23 06:17:21 PM PDT 24
Peak memory 198584 kb
Host smart-7b70a5fe-6fa9-46ed-adb3-2788116b7276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868053902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1868053902
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.691451269
Short name T397
Test name
Test status
Simulation time 99592627 ps
CPU time 0.73 seconds
Started Jul 23 06:17:19 PM PDT 24
Finished Jul 23 06:17:22 PM PDT 24
Peak memory 199664 kb
Host smart-7d5bea07-08ae-4d6b-9360-32efc3d0c15e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691451269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.691451269
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.3406266617
Short name T541
Test name
Test status
Simulation time 115063687 ps
CPU time 0.9 seconds
Started Jul 23 06:17:20 PM PDT 24
Finished Jul 23 06:17:23 PM PDT 24
Peak memory 210152 kb
Host smart-a0564565-e092-484b-91a3-39c9f0a81444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406266617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.3406266617
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.923682616
Short name T461
Test name
Test status
Simulation time 65298055 ps
CPU time 0.76 seconds
Started Jul 23 06:17:21 PM PDT 24
Finished Jul 23 06:17:24 PM PDT 24
Peak memory 198620 kb
Host smart-32f65dbd-1f6c-4867-9f55-3eda20edcedb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923682616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.923682616
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.285177937
Short name T371
Test name
Test status
Simulation time 35888824 ps
CPU time 0.64 seconds
Started Jul 23 06:17:18 PM PDT 24
Finished Jul 23 06:17:21 PM PDT 24
Peak memory 198960 kb
Host smart-520ec206-d905-46d3-93f2-e3efefd7a66d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285177937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.285177937
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.539864069
Short name T403
Test name
Test status
Simulation time 53721328 ps
CPU time 0.72 seconds
Started Jul 23 06:17:20 PM PDT 24
Finished Jul 23 06:17:23 PM PDT 24
Peak memory 199728 kb
Host smart-71329f65-e754-4182-a100-e62b4e9a749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539864069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.539864069
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4226271227
Short name T555
Test name
Test status
Simulation time 36304010 ps
CPU time 0.58 seconds
Started Jul 23 06:17:18 PM PDT 24
Finished Jul 23 06:17:20 PM PDT 24
Peak memory 197896 kb
Host smart-82bb833e-06a6-4e19-bef1-43490066c11a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226271227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.4226271227
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.2406942110
Short name T323
Test name
Test status
Simulation time 624240204 ps
CPU time 0.95 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 198660 kb
Host smart-8aa7b096-8ceb-4f6f-bd98-4dcc4edcd57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406942110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.2406942110
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.850466082
Short name T577
Test name
Test status
Simulation time 47746517 ps
CPU time 0.69 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 197848 kb
Host smart-070ab6a9-6eb3-4470-955a-897119d5c9e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850466082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.850466082
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.19567145
Short name T229
Test name
Test status
Simulation time 25649637 ps
CPU time 0.63 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 198632 kb
Host smart-647ce89e-998f-455e-887e-05801b0c44c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.19567145
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.4198120111
Short name T90
Test name
Test status
Simulation time 161792933 ps
CPU time 0.68 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 201912 kb
Host smart-dc4b2f02-8e07-4a09-b959-6b33dceebfe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198120111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.4198120111
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1366889272
Short name T417
Test name
Test status
Simulation time 72326651 ps
CPU time 0.71 seconds
Started Jul 23 06:17:23 PM PDT 24
Finished Jul 23 06:17:26 PM PDT 24
Peak memory 198680 kb
Host smart-4ca39d43-e6ed-4bb4-839d-045eed6df6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366889272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1366889272
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1652597833
Short name T332
Test name
Test status
Simulation time 75496975 ps
CPU time 0.79 seconds
Started Jul 23 06:17:17 PM PDT 24
Finished Jul 23 06:17:19 PM PDT 24
Peak memory 198660 kb
Host smart-304a6306-c53c-413a-9e0b-26249c5a0c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652597833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1652597833
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.218843765
Short name T288
Test name
Test status
Simulation time 43044802 ps
CPU time 0.66 seconds
Started Jul 23 06:17:20 PM PDT 24
Finished Jul 23 06:17:23 PM PDT 24
Peak memory 199108 kb
Host smart-5bafc678-715b-4b37-8bfe-1dcd5ef9f340
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218843765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.218843765
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.870577168
Short name T171
Test name
Test status
Simulation time 142276208 ps
CPU time 0.92 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:35 PM PDT 24
Peak memory 201160 kb
Host smart-908cd373-2d79-42ca-be42-c74b87e5fa01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870577168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.870577168
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2517572073
Short name T124
Test name
Test status
Simulation time 125770109 ps
CPU time 0.71 seconds
Started Jul 23 06:17:27 PM PDT 24
Finished Jul 23 06:17:31 PM PDT 24
Peak memory 199252 kb
Host smart-9d9c76b8-2e10-438f-8a02-f3589b85252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517572073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2517572073
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.4256161777
Short name T580
Test name
Test status
Simulation time 66092146 ps
CPU time 0.82 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 199648 kb
Host smart-3b06cb68-9b0c-4660-a3c9-5eb4c90c1b6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256161777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.4256161777
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3166999411
Short name T295
Test name
Test status
Simulation time 56418220 ps
CPU time 0.57 seconds
Started Jul 23 06:17:24 PM PDT 24
Finished Jul 23 06:17:27 PM PDT 24
Peak memory 198580 kb
Host smart-ba79c681-082d-4557-997f-3acbf02949c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166999411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3166999411
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.2557011696
Short name T479
Test name
Test status
Simulation time 879558183 ps
CPU time 0.92 seconds
Started Jul 23 06:17:26 PM PDT 24
Finished Jul 23 06:17:31 PM PDT 24
Peak memory 198988 kb
Host smart-21da85c7-a4ff-4345-9db6-95f239c2cc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557011696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2557011696
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2618954442
Short name T329
Test name
Test status
Simulation time 40254548 ps
CPU time 0.63 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:33 PM PDT 24
Peak memory 198596 kb
Host smart-71dc96e2-f602-4fc2-b502-a4bde7c80af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618954442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2618954442
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3718289216
Short name T516
Test name
Test status
Simulation time 64131854 ps
CPU time 0.61 seconds
Started Jul 23 06:17:26 PM PDT 24
Finished Jul 23 06:17:30 PM PDT 24
Peak memory 198644 kb
Host smart-aee4c080-49c1-47e2-bcc5-dcfe6ed33129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718289216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3718289216
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3414936181
Short name T533
Test name
Test status
Simulation time 58068892 ps
CPU time 0.71 seconds
Started Jul 23 06:17:27 PM PDT 24
Finished Jul 23 06:17:31 PM PDT 24
Peak memory 201928 kb
Host smart-731f5769-da1b-4ce8-a87e-c3626ff10087
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414936181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3414936181
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2794823272
Short name T469
Test name
Test status
Simulation time 99963817 ps
CPU time 0.92 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 199668 kb
Host smart-dc1bda51-d4a0-412b-b0a5-2e31f9dfb554
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794823272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2794823272
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2705970596
Short name T418
Test name
Test status
Simulation time 117358748 ps
CPU time 0.93 seconds
Started Jul 23 06:17:26 PM PDT 24
Finished Jul 23 06:17:31 PM PDT 24
Peak memory 210056 kb
Host smart-a0650e61-85d8-4546-a6c7-f4dda2f786df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705970596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2705970596
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.169450992
Short name T423
Test name
Test status
Simulation time 69038893 ps
CPU time 0.87 seconds
Started Jul 23 06:17:29 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 199784 kb
Host smart-4234de11-c6e4-4e1f-8d4b-fc2f1faa560d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169450992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_
mubi.169450992
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3438679261
Short name T88
Test name
Test status
Simulation time 38292563 ps
CPU time 0.66 seconds
Started Jul 23 06:17:27 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 199108 kb
Host smart-1341808b-4f4b-45fe-9350-aacc4a94d25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438679261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3438679261
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.2106461492
Short name T547
Test name
Test status
Simulation time 65380349 ps
CPU time 0.88 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:33 PM PDT 24
Peak memory 200844 kb
Host smart-05839d7d-c240-4f60-a110-f357704fdc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106461492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.2106461492
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.4097756403
Short name T140
Test name
Test status
Simulation time 45530340 ps
CPU time 0.75 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 199652 kb
Host smart-e0fd145b-982b-4a74-b2c6-6ecec032555f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097756403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.4097756403
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3137234655
Short name T484
Test name
Test status
Simulation time 35320550 ps
CPU time 0.58 seconds
Started Jul 23 06:17:40 PM PDT 24
Finished Jul 23 06:17:43 PM PDT 24
Peak memory 198496 kb
Host smart-4395c94e-fcf7-4f1e-b6ef-3dd65ca4d9a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137234655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.3137234655
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.1821888292
Short name T249
Test name
Test status
Simulation time 158932660 ps
CPU time 0.96 seconds
Started Jul 23 06:17:31 PM PDT 24
Finished Jul 23 06:17:35 PM PDT 24
Peak memory 198948 kb
Host smart-06a979f5-61d2-46a4-9b64-ea5440f2195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821888292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.1821888292
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2717414352
Short name T457
Test name
Test status
Simulation time 22458570 ps
CPU time 0.62 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:32 PM PDT 24
Peak memory 198660 kb
Host smart-b0c5e9eb-4a33-4811-aad0-0d855fe03b7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717414352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2717414352
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1374557310
Short name T44
Test name
Test status
Simulation time 50384698 ps
CPU time 0.68 seconds
Started Jul 23 06:17:29 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 198932 kb
Host smart-f2963c44-a125-4387-8c75-4f2fd5a5556e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374557310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1374557310
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.2038080171
Short name T174
Test name
Test status
Simulation time 47364919 ps
CPU time 0.74 seconds
Started Jul 23 06:17:32 PM PDT 24
Finished Jul 23 06:17:36 PM PDT 24
Peak memory 201960 kb
Host smart-e7c5878b-c148-4c33-849d-e8f12bbc5a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038080171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.2038080171
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.2569594465
Short name T506
Test name
Test status
Simulation time 66764064 ps
CPU time 0.89 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:35 PM PDT 24
Peak memory 199712 kb
Host smart-1afd395d-fd47-40f5-889d-aafa6d4b7ae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569594465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2569594465
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2866284902
Short name T412
Test name
Test status
Simulation time 159016044 ps
CPU time 0.81 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:33 PM PDT 24
Peak memory 210312 kb
Host smart-f8bef61f-b5eb-4e15-9dd0-3b214ff5ba07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866284902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2866284902
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.155000822
Short name T463
Test name
Test status
Simulation time 93869234 ps
CPU time 0.92 seconds
Started Jul 23 06:17:32 PM PDT 24
Finished Jul 23 06:17:36 PM PDT 24
Peak memory 199884 kb
Host smart-7804fdba-fefe-426c-8472-c843224e8291
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155000822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.155000822
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.173825845
Short name T497
Test name
Test status
Simulation time 30959119 ps
CPU time 0.7 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:35 PM PDT 24
Peak memory 199860 kb
Host smart-4e8ec404-4a88-48b3-ad4b-797b9b7d46d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173825845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.173825845
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.70132323
Short name T101
Test name
Test status
Simulation time 51327550 ps
CPU time 0.98 seconds
Started Jul 23 06:17:29 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 200716 kb
Host smart-a67ca0b1-033d-424a-acd2-5dd73c1e68e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70132323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.70132323
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.926238197
Short name T345
Test name
Test status
Simulation time 91456050 ps
CPU time 0.69 seconds
Started Jul 23 06:17:29 PM PDT 24
Finished Jul 23 06:17:33 PM PDT 24
Peak memory 198832 kb
Host smart-fb004e17-287e-4502-9faf-bfe1edf6aedf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926238197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disa
ble_rom_integrity_check.926238197
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2071287881
Short name T37
Test name
Test status
Simulation time 27936565 ps
CPU time 0.63 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 198620 kb
Host smart-34185216-749d-489c-977c-dbee2dde1e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071287881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2071287881
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2981566746
Short name T96
Test name
Test status
Simulation time 624528988 ps
CPU time 0.97 seconds
Started Jul 23 06:17:40 PM PDT 24
Finished Jul 23 06:17:44 PM PDT 24
Peak memory 198580 kb
Host smart-6bc0740d-eee7-4ccd-ab5a-09e680084e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981566746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2981566746
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2223807320
Short name T339
Test name
Test status
Simulation time 29674668 ps
CPU time 0.63 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 198748 kb
Host smart-e1143c88-123e-408a-b27a-a58f40c1b61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223807320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2223807320
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.2863660381
Short name T327
Test name
Test status
Simulation time 74135120 ps
CPU time 0.6 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 198576 kb
Host smart-9f0ef5c2-94b8-49ac-ae30-e58e314070d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863660381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2863660381
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.4248715516
Short name T358
Test name
Test status
Simulation time 40017064 ps
CPU time 0.76 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 201876 kb
Host smart-b1d2f4a2-2c1c-451d-a338-3f02350dfcbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248715516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.4248715516
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.165908176
Short name T364
Test name
Test status
Simulation time 53964759 ps
CPU time 0.8 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 198932 kb
Host smart-e9824276-9cc1-4664-9158-e04170668509
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165908176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.165908176
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3040504149
Short name T361
Test name
Test status
Simulation time 141736268 ps
CPU time 0.81 seconds
Started Jul 23 06:17:32 PM PDT 24
Finished Jul 23 06:17:36 PM PDT 24
Peak memory 210116 kb
Host smart-a8b78e35-97c0-4a52-b373-c2ac78f37aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040504149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3040504149
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2891203509
Short name T485
Test name
Test status
Simulation time 65371912 ps
CPU time 0.81 seconds
Started Jul 23 06:17:40 PM PDT 24
Finished Jul 23 06:17:43 PM PDT 24
Peak memory 198640 kb
Host smart-c4ff7141-0883-47f4-9d20-d657a2aa2a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891203509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2891203509
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.2271930086
Short name T228
Test name
Test status
Simulation time 31847661 ps
CPU time 0.71 seconds
Started Jul 23 06:17:28 PM PDT 24
Finished Jul 23 06:17:33 PM PDT 24
Peak memory 199944 kb
Host smart-fb1ed2f9-90df-4483-aebb-36dcd55d2507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271930086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.2271930086
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.3833252350
Short name T17
Test name
Test status
Simulation time 79717173 ps
CPU time 0.79 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:30 PM PDT 24
Peak memory 199444 kb
Host smart-80cc27e8-4bf8-41e1-b4ae-255325197389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833252350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.3833252350
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.125762819
Short name T31
Test name
Test status
Simulation time 128230750 ps
CPU time 0.66 seconds
Started Jul 23 06:16:32 PM PDT 24
Finished Jul 23 06:16:36 PM PDT 24
Peak memory 198984 kb
Host smart-8f5bb360-be4a-42c1-8554-de8aebf567f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125762819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disab
le_rom_integrity_check.125762819
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1141883337
Short name T452
Test name
Test status
Simulation time 38621798 ps
CPU time 0.61 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:28 PM PDT 24
Peak memory 198636 kb
Host smart-66c3b282-bec8-4806-8a88-443917d154cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141883337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1141883337
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3544792160
Short name T520
Test name
Test status
Simulation time 168599594 ps
CPU time 0.98 seconds
Started Jul 23 06:16:34 PM PDT 24
Finished Jul 23 06:16:39 PM PDT 24
Peak memory 198644 kb
Host smart-dd0820f5-1336-42b2-9a41-18bbed0d9cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544792160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3544792160
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1580226272
Short name T570
Test name
Test status
Simulation time 121925244 ps
CPU time 0.61 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:38 PM PDT 24
Peak memory 198632 kb
Host smart-ca906d0d-21c8-4b02-92cb-41d2cb1ecc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580226272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1580226272
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.636389115
Short name T218
Test name
Test status
Simulation time 53854466 ps
CPU time 0.64 seconds
Started Jul 23 06:16:32 PM PDT 24
Finished Jul 23 06:16:36 PM PDT 24
Peak memory 198628 kb
Host smart-e451e6f8-e988-458e-8866-464f1deaea6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636389115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.636389115
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1851008887
Short name T444
Test name
Test status
Simulation time 67698082 ps
CPU time 0.65 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 201988 kb
Host smart-95dfb209-b8fd-472e-bcf3-603872eae329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851008887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1851008887
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2091097900
Short name T269
Test name
Test status
Simulation time 154294335 ps
CPU time 0.73 seconds
Started Jul 23 06:16:26 PM PDT 24
Finished Jul 23 06:16:30 PM PDT 24
Peak memory 198936 kb
Host smart-f4e29243-bf71-4fe2-8c79-e8d780a2ad57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091097900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2091097900
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3078986426
Short name T212
Test name
Test status
Simulation time 116129543 ps
CPU time 0.96 seconds
Started Jul 23 06:16:30 PM PDT 24
Finished Jul 23 06:16:34 PM PDT 24
Peak memory 210068 kb
Host smart-120af375-815c-4cee-854e-3c9fd5265f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078986426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3078986426
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1629499731
Short name T22
Test name
Test status
Simulation time 528365522 ps
CPU time 1.13 seconds
Started Jul 23 06:16:31 PM PDT 24
Finished Jul 23 06:16:36 PM PDT 24
Peak memory 217364 kb
Host smart-6a8bed38-8f04-4149-b4a6-8bd1f0126b56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629499731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1629499731
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1950452216
Short name T128
Test name
Test status
Simulation time 93158055 ps
CPU time 0.73 seconds
Started Jul 23 06:16:27 PM PDT 24
Finished Jul 23 06:16:32 PM PDT 24
Peak memory 198744 kb
Host smart-50016f98-861d-4d8c-8ef7-570a4718faa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950452216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1950452216
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.702977184
Short name T369
Test name
Test status
Simulation time 48361853 ps
CPU time 0.63 seconds
Started Jul 23 06:16:25 PM PDT 24
Finished Jul 23 06:16:29 PM PDT 24
Peak memory 199932 kb
Host smart-96d5b59b-2de2-466b-9e20-4788598ab16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702977184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.702977184
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1969342754
Short name T522
Test name
Test status
Simulation time 25040981 ps
CPU time 0.62 seconds
Started Jul 23 06:17:35 PM PDT 24
Finished Jul 23 06:17:38 PM PDT 24
Peak memory 199080 kb
Host smart-30e94106-240f-45d5-a9f8-1052912bcb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969342754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1969342754
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.176768596
Short name T458
Test name
Test status
Simulation time 48844378 ps
CPU time 0.82 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 199764 kb
Host smart-a1fe6470-bf34-4e86-a1f9-6dc3fa947bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176768596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.176768596
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2598827639
Short name T550
Test name
Test status
Simulation time 31850041 ps
CPU time 0.65 seconds
Started Jul 23 06:17:39 PM PDT 24
Finished Jul 23 06:17:42 PM PDT 24
Peak memory 198492 kb
Host smart-769950dc-c285-4e38-be54-dbf8b568b365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598827639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2598827639
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.4022345687
Short name T400
Test name
Test status
Simulation time 316628825 ps
CPU time 0.97 seconds
Started Jul 23 06:17:38 PM PDT 24
Finished Jul 23 06:17:41 PM PDT 24
Peak memory 198952 kb
Host smart-22f60bf7-f3aa-40ef-9be2-355f76d091e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022345687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.4022345687
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.3134518073
Short name T294
Test name
Test status
Simulation time 39942628 ps
CPU time 0.59 seconds
Started Jul 23 06:17:34 PM PDT 24
Finished Jul 23 06:17:38 PM PDT 24
Peak memory 198644 kb
Host smart-439b76ef-5c85-4015-91ff-94cf775e67ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134518073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3134518073
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.3500289529
Short name T265
Test name
Test status
Simulation time 35524191 ps
CPU time 0.63 seconds
Started Jul 23 06:17:39 PM PDT 24
Finished Jul 23 06:17:42 PM PDT 24
Peak memory 198724 kb
Host smart-41290925-ec63-4d40-83fb-762fc976e133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500289529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3500289529
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.980863378
Short name T264
Test name
Test status
Simulation time 92259388 ps
CPU time 0.74 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 198884 kb
Host smart-3115ad0f-696a-46d0-8a35-f1ca815bd475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980863378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.980863378
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1612192428
Short name T95
Test name
Test status
Simulation time 161812182 ps
CPU time 0.88 seconds
Started Jul 23 06:17:35 PM PDT 24
Finished Jul 23 06:17:38 PM PDT 24
Peak memory 210044 kb
Host smart-36ba8372-fd85-488a-ac54-c181614a94fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612192428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1612192428
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.4224075154
Short name T468
Test name
Test status
Simulation time 119504335 ps
CPU time 0.76 seconds
Started Jul 23 06:17:34 PM PDT 24
Finished Jul 23 06:17:38 PM PDT 24
Peak memory 198800 kb
Host smart-9323066b-3852-49a8-ab8b-b55709d31f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224075154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4224075154
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.4140299125
Short name T393
Test name
Test status
Simulation time 72482182 ps
CPU time 0.64 seconds
Started Jul 23 06:17:30 PM PDT 24
Finished Jul 23 06:17:34 PM PDT 24
Peak memory 199000 kb
Host smart-ff5f460a-4ee6-4d50-a923-8e2cc3105c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140299125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.4140299125
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.3177843730
Short name T331
Test name
Test status
Simulation time 137149489 ps
CPU time 0.85 seconds
Started Jul 23 06:17:38 PM PDT 24
Finished Jul 23 06:17:41 PM PDT 24
Peak memory 200608 kb
Host smart-4a8750f9-10f4-4336-a1bb-0ce3c67d3080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177843730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3177843730
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3851342786
Short name T389
Test name
Test status
Simulation time 65978304 ps
CPU time 0.84 seconds
Started Jul 23 06:17:35 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 200496 kb
Host smart-e853a42f-2b8d-434e-a9cd-73b5d004580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851342786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3851342786
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3807737486
Short name T422
Test name
Test status
Simulation time 50867497 ps
CPU time 0.71 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:40 PM PDT 24
Peak memory 199124 kb
Host smart-cc7017d5-e85e-4fb5-b686-afaeccd12bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807737486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3807737486
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.4286387851
Short name T549
Test name
Test status
Simulation time 32958893 ps
CPU time 0.6 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:40 PM PDT 24
Peak memory 198608 kb
Host smart-7528974c-216a-4a0e-a249-dbe386291f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286387851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.4286387851
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.2750849747
Short name T287
Test name
Test status
Simulation time 599147895 ps
CPU time 0.96 seconds
Started Jul 23 06:17:39 PM PDT 24
Finished Jul 23 06:17:42 PM PDT 24
Peak memory 198600 kb
Host smart-96fe3abb-b96a-4683-90a9-6fda4986a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750849747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2750849747
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2476795527
Short name T365
Test name
Test status
Simulation time 43919522 ps
CPU time 0.68 seconds
Started Jul 23 06:17:39 PM PDT 24
Finished Jul 23 06:17:42 PM PDT 24
Peak memory 197920 kb
Host smart-dd13cb1d-92f8-4330-b7e4-ef181e7bbb2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476795527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2476795527
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3275499866
Short name T221
Test name
Test status
Simulation time 112386076 ps
CPU time 0.62 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 198656 kb
Host smart-0f0d6512-886f-4a04-83a6-dfb1ad4b76a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275499866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3275499866
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.2070115625
Short name T193
Test name
Test status
Simulation time 46380947 ps
CPU time 0.69 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 201940 kb
Host smart-2e8e4d7e-b660-4bcb-9689-32bc4fe3f334
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070115625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.2070115625
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.1981666237
Short name T625
Test name
Test status
Simulation time 84563257 ps
CPU time 0.89 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:40 PM PDT 24
Peak memory 199684 kb
Host smart-8de11d86-33a6-40d9-8e15-f97533552901
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981666237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.1981666237
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1935949295
Short name T431
Test name
Test status
Simulation time 116570883 ps
CPU time 0.83 seconds
Started Jul 23 06:17:35 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 210176 kb
Host smart-a7795c4b-6fb3-4c03-90b8-360c5d61a02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935949295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1935949295
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2672902374
Short name T406
Test name
Test status
Simulation time 51257806 ps
CPU time 0.77 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:40 PM PDT 24
Peak memory 198740 kb
Host smart-87c5ae31-e511-49ff-9358-0ac76bd8fd14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672902374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2672902374
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.415055858
Short name T349
Test name
Test status
Simulation time 42503587 ps
CPU time 0.66 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 199104 kb
Host smart-1e829d42-3309-4a3b-b2ef-a29022ad9968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415055858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.415055858
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.2256307055
Short name T125
Test name
Test status
Simulation time 66024548 ps
CPU time 0.91 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 201300 kb
Host smart-6a5f653e-4760-40ef-82f7-ceb77a74908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256307055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2256307055
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1515563037
Short name T157
Test name
Test status
Simulation time 52628928 ps
CPU time 0.78 seconds
Started Jul 23 06:17:43 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 199728 kb
Host smart-73af1142-ff3e-4039-8fa2-528da0e5abc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515563037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1515563037
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2387707028
Short name T305
Test name
Test status
Simulation time 30896551 ps
CPU time 0.65 seconds
Started Jul 23 06:17:40 PM PDT 24
Finished Jul 23 06:17:43 PM PDT 24
Peak memory 197896 kb
Host smart-b7f1225a-85bc-470e-a41d-09eaff187910
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387707028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2387707028
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.1354705574
Short name T478
Test name
Test status
Simulation time 623365814 ps
CPU time 0.94 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 198652 kb
Host smart-2c162882-8eda-4902-a59e-1d86ca3f0a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354705574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.1354705574
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.3283055254
Short name T362
Test name
Test status
Simulation time 23648432 ps
CPU time 0.69 seconds
Started Jul 23 06:17:40 PM PDT 24
Finished Jul 23 06:17:44 PM PDT 24
Peak memory 198688 kb
Host smart-1078855b-32cd-4fe6-8a6a-56dc1ee25f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283055254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3283055254
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3908737934
Short name T337
Test name
Test status
Simulation time 59101337 ps
CPU time 0.6 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 198540 kb
Host smart-8b355b66-737c-425e-89bc-06f4397b39ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908737934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3908737934
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3700655920
Short name T410
Test name
Test status
Simulation time 108720920 ps
CPU time 0.78 seconds
Started Jul 23 06:17:35 PM PDT 24
Finished Jul 23 06:17:38 PM PDT 24
Peak memory 199696 kb
Host smart-29e8cebc-c0d7-48c6-9afd-a5a5f58c682e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700655920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3700655920
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.1776721909
Short name T304
Test name
Test status
Simulation time 138898237 ps
CPU time 0.8 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 210016 kb
Host smart-9d314f18-b686-4b15-a3f7-08f9e8f92258
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776721909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1776721909
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.167834077
Short name T624
Test name
Test status
Simulation time 58790126 ps
CPU time 0.82 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 198680 kb
Host smart-0e9d49e2-7fc1-4d2e-90cc-6f3906c2f93a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167834077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.167834077
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1910882560
Short name T402
Test name
Test status
Simulation time 37168946 ps
CPU time 0.65 seconds
Started Jul 23 06:17:36 PM PDT 24
Finished Jul 23 06:17:39 PM PDT 24
Peak memory 199916 kb
Host smart-1cce249d-55f5-4722-88f6-be0308f05024
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910882560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1910882560
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.736733426
Short name T55
Test name
Test status
Simulation time 49798696 ps
CPU time 0.82 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 199336 kb
Host smart-d1b9aa37-49d2-4991-bb4d-48a3bed08477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736733426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.736733426
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.4026843626
Short name T439
Test name
Test status
Simulation time 34665819 ps
CPU time 0.74 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 199148 kb
Host smart-5344ed8f-5123-42ca-be20-883782cef925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026843626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.4026843626
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.4195015350
Short name T200
Test name
Test status
Simulation time 53370156 ps
CPU time 0.69 seconds
Started Jul 23 06:17:39 PM PDT 24
Finished Jul 23 06:17:42 PM PDT 24
Peak memory 199744 kb
Host smart-0fa3c8d8-f339-4fe8-bbfd-b5427a008531
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195015350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.4195015350
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1457309230
Short name T542
Test name
Test status
Simulation time 111367610 ps
CPU time 0.59 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:44 PM PDT 24
Peak memory 197864 kb
Host smart-6cabf747-1e96-497e-bc42-a59523e39579
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457309230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1457309230
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3261051769
Short name T615
Test name
Test status
Simulation time 609692810 ps
CPU time 0.96 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 198952 kb
Host smart-3657ef39-54ec-495d-8a20-3a20f8012d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261051769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3261051769
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.3961031986
Short name T209
Test name
Test status
Simulation time 51015140 ps
CPU time 0.65 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 198668 kb
Host smart-fd6008f3-0575-43ce-833e-b88922a40653
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961031986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.3961031986
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3835061936
Short name T366
Test name
Test status
Simulation time 37319498 ps
CPU time 0.63 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 198644 kb
Host smart-6adb76cb-6365-4e97-a3d5-ae766101e6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835061936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3835061936
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.3716995885
Short name T309
Test name
Test status
Simulation time 84346046 ps
CPU time 0.71 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 199680 kb
Host smart-98311d91-09d0-4cea-b0c9-55e9d6078e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716995885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3716995885
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3967905681
Short name T500
Test name
Test status
Simulation time 110320982 ps
CPU time 0.93 seconds
Started Jul 23 06:17:51 PM PDT 24
Finished Jul 23 06:17:53 PM PDT 24
Peak memory 201880 kb
Host smart-7f124dd4-81fa-484a-bf99-3dcbabbe565f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967905681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3967905681
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2221586749
Short name T313
Test name
Test status
Simulation time 65703605 ps
CPU time 0.9 seconds
Started Jul 23 06:17:42 PM PDT 24
Finished Jul 23 06:17:46 PM PDT 24
Peak memory 199688 kb
Host smart-4c36a88b-6291-4fb0-9070-f3e98554ebb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221586749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2221586749
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.976032159
Short name T65
Test name
Test status
Simulation time 56664137 ps
CPU time 0.63 seconds
Started Jul 23 06:17:41 PM PDT 24
Finished Jul 23 06:17:45 PM PDT 24
Peak memory 199848 kb
Host smart-5097938f-884e-47a6-831a-feefabad0064
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976032159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.976032159
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.1202272114
Short name T98
Test name
Test status
Simulation time 32774474 ps
CPU time 1.1 seconds
Started Jul 23 06:17:50 PM PDT 24
Finished Jul 23 06:17:53 PM PDT 24
Peak memory 201504 kb
Host smart-07c6ada9-b749-480c-840b-fd5b5eeeb3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202272114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1202272114
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2420778582
Short name T413
Test name
Test status
Simulation time 61234055 ps
CPU time 0.86 seconds
Started Jul 23 06:17:51 PM PDT 24
Finished Jul 23 06:17:55 PM PDT 24
Peak memory 199672 kb
Host smart-c2535a23-7138-4bfc-b6ab-5fa9bf101dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420778582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2420778582
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.1953182939
Short name T451
Test name
Test status
Simulation time 32329299 ps
CPU time 0.62 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 198540 kb
Host smart-e17477b1-2182-40bc-9748-b6cf40fbae5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953182939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.1953182939
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.632021056
Short name T292
Test name
Test status
Simulation time 299840993 ps
CPU time 0.93 seconds
Started Jul 23 06:17:50 PM PDT 24
Finished Jul 23 06:17:53 PM PDT 24
Peak memory 198968 kb
Host smart-ce489ea1-69f5-4b39-8582-a23caadf2ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632021056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.632021056
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3646816047
Short name T473
Test name
Test status
Simulation time 63226566 ps
CPU time 0.74 seconds
Started Jul 23 06:17:51 PM PDT 24
Finished Jul 23 06:17:54 PM PDT 24
Peak memory 198532 kb
Host smart-932798c7-534a-4e0b-b896-ea4cf70bbed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646816047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3646816047
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2977852191
Short name T610
Test name
Test status
Simulation time 27599668 ps
CPU time 0.63 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 198924 kb
Host smart-d6d832e9-cea1-4ce8-a6af-1e02b82c3b30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977852191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2977852191
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.3896199109
Short name T257
Test name
Test status
Simulation time 56079809 ps
CPU time 0.72 seconds
Started Jul 23 06:17:49 PM PDT 24
Finished Jul 23 06:17:52 PM PDT 24
Peak memory 199640 kb
Host smart-d633a6fc-eccc-458f-ae11-8bb74b80e815
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896199109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3896199109
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2635303071
Short name T440
Test name
Test status
Simulation time 105970525 ps
CPU time 0.96 seconds
Started Jul 23 06:17:49 PM PDT 24
Finished Jul 23 06:17:52 PM PDT 24
Peak memory 210080 kb
Host smart-d42f8c22-9484-41db-b125-8fe3b434cc81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635303071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2635303071
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.259126317
Short name T407
Test name
Test status
Simulation time 64925322 ps
CPU time 0.85 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 198460 kb
Host smart-198f9287-d688-4d0d-8205-8d0477d003bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259126317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_
mubi.259126317
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2808904523
Short name T386
Test name
Test status
Simulation time 44449286 ps
CPU time 0.67 seconds
Started Jul 23 06:17:50 PM PDT 24
Finished Jul 23 06:17:52 PM PDT 24
Peak memory 199072 kb
Host smart-0616352d-c0fc-4f72-a309-c065b71a101a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808904523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2808904523
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3923661921
Short name T501
Test name
Test status
Simulation time 58454616 ps
CPU time 0.84 seconds
Started Jul 23 06:17:57 PM PDT 24
Finished Jul 23 06:18:00 PM PDT 24
Peak memory 199668 kb
Host smart-0e49905e-5298-47e2-8523-98ad12199427
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923661921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3923661921
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.827872400
Short name T216
Test name
Test status
Simulation time 29382292 ps
CPU time 0.62 seconds
Started Jul 23 06:17:56 PM PDT 24
Finished Jul 23 06:17:59 PM PDT 24
Peak memory 197868 kb
Host smart-99ec2312-e84b-4ee3-82da-515a7ca24da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827872400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.827872400
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3023313491
Short name T559
Test name
Test status
Simulation time 633570255 ps
CPU time 1.04 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 198608 kb
Host smart-9aa68a39-2285-4d27-b907-f12d431f2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023313491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3023313491
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3101877925
Short name T360
Test name
Test status
Simulation time 102063933 ps
CPU time 0.63 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 197980 kb
Host smart-d3a3b6ed-8497-4f07-8c42-3726a732c9d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101877925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3101877925
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.947486378
Short name T205
Test name
Test status
Simulation time 67289448 ps
CPU time 0.63 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:56 PM PDT 24
Peak memory 198676 kb
Host smart-a8f9fcca-4488-4941-8ba2-291c19fcb201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947486378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.947486378
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.1159363028
Short name T575
Test name
Test status
Simulation time 74801865 ps
CPU time 0.72 seconds
Started Jul 23 06:17:54 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 201952 kb
Host smart-20f3b729-5d5d-4a5d-af47-a0b72f0d12d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159363028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.1159363028
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2490842485
Short name T534
Test name
Test status
Simulation time 63285243 ps
CPU time 0.87 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:57 PM PDT 24
Peak memory 199676 kb
Host smart-9358a283-5343-4d03-8951-d48d4db862fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490842485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2490842485
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3160204619
Short name T436
Test name
Test status
Simulation time 111107448 ps
CPU time 0.94 seconds
Started Jul 23 06:17:54 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 201816 kb
Host smart-4312ec42-9cbe-466d-8147-1d0ddee9f9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160204619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3160204619
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2905170316
Short name T351
Test name
Test status
Simulation time 128127405 ps
CPU time 0.73 seconds
Started Jul 23 06:17:55 PM PDT 24
Finished Jul 23 06:17:59 PM PDT 24
Peak memory 198652 kb
Host smart-9399fb39-5de4-4af9-a0a5-b5d5983f816f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905170316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2905170316
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.217197539
Short name T259
Test name
Test status
Simulation time 34567563 ps
CPU time 0.67 seconds
Started Jul 23 06:17:50 PM PDT 24
Finished Jul 23 06:17:52 PM PDT 24
Peak memory 199036 kb
Host smart-bd7b77b2-aae4-4ce1-b5b2-981d7e9c378a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217197539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.217197539
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.936845311
Short name T99
Test name
Test status
Simulation time 245329383 ps
CPU time 0.79 seconds
Started Jul 23 06:17:56 PM PDT 24
Finished Jul 23 06:18:00 PM PDT 24
Peak memory 200588 kb
Host smart-6cbb7f94-327b-4aa5-bec2-fd235d39a846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936845311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.936845311
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.683317314
Short name T495
Test name
Test status
Simulation time 61484009 ps
CPU time 0.82 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 199676 kb
Host smart-fa7b8759-e053-458f-8896-79e62ad70928
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683317314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disa
ble_rom_integrity_check.683317314
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1473931368
Short name T367
Test name
Test status
Simulation time 29048127 ps
CPU time 0.64 seconds
Started Jul 23 06:17:56 PM PDT 24
Finished Jul 23 06:17:59 PM PDT 24
Peak memory 198564 kb
Host smart-a4fd0df0-56e0-467f-af37-db6c8ccd3acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473931368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1473931368
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3447190817
Short name T245
Test name
Test status
Simulation time 1082985001 ps
CPU time 0.97 seconds
Started Jul 23 06:17:54 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 198960 kb
Host smart-dde9d862-a0d1-4a90-b3b4-e930151adf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447190817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3447190817
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.1107791982
Short name T312
Test name
Test status
Simulation time 51964154 ps
CPU time 0.61 seconds
Started Jul 23 06:17:58 PM PDT 24
Finished Jul 23 06:18:00 PM PDT 24
Peak memory 198644 kb
Host smart-95c92e94-cd3a-482d-b46b-5941a774db03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107791982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1107791982
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1828035856
Short name T377
Test name
Test status
Simulation time 65145206 ps
CPU time 0.62 seconds
Started Jul 23 06:17:54 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 198564 kb
Host smart-36389e58-5b5a-4656-9758-64d5d4bb5ab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828035856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1828035856
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3336950480
Short name T160
Test name
Test status
Simulation time 73409848 ps
CPU time 0.73 seconds
Started Jul 23 06:18:00 PM PDT 24
Finished Jul 23 06:18:02 PM PDT 24
Peak memory 201984 kb
Host smart-99972937-567b-47da-a77e-177f2607a414
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336950480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3336950480
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.1901411718
Short name T278
Test name
Test status
Simulation time 77344524 ps
CPU time 0.89 seconds
Started Jul 23 06:17:52 PM PDT 24
Finished Jul 23 06:17:55 PM PDT 24
Peak memory 199636 kb
Host smart-bc3612d2-e399-432d-9dd8-9fe0e2a32276
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901411718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1901411718
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1685450223
Short name T311
Test name
Test status
Simulation time 158597040 ps
CPU time 0.8 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:58 PM PDT 24
Peak memory 201856 kb
Host smart-4aa570ec-f473-409c-b74a-42d211d267bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685450223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1685450223
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.842973156
Short name T553
Test name
Test status
Simulation time 51073475 ps
CPU time 0.79 seconds
Started Jul 23 06:17:53 PM PDT 24
Finished Jul 23 06:17:56 PM PDT 24
Peak memory 198592 kb
Host smart-4883d17e-517f-4b38-88a1-79403adaf7f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842973156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.842973156
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3351527482
Short name T12
Test name
Test status
Simulation time 52737646 ps
CPU time 0.64 seconds
Started Jul 23 06:17:56 PM PDT 24
Finished Jul 23 06:18:00 PM PDT 24
Peak memory 199916 kb
Host smart-2256977a-a4e2-43df-9837-c126be72a8a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351527482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3351527482
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3903754962
Short name T401
Test name
Test status
Simulation time 48416974 ps
CPU time 0.75 seconds
Started Jul 23 06:18:03 PM PDT 24
Finished Jul 23 06:18:04 PM PDT 24
Peak memory 199468 kb
Host smart-6da6157d-a1bb-4313-81fa-80db754dea8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903754962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3903754962
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1205471557
Short name T141
Test name
Test status
Simulation time 62477480 ps
CPU time 0.84 seconds
Started Jul 23 06:18:06 PM PDT 24
Finished Jul 23 06:18:08 PM PDT 24
Peak memory 199576 kb
Host smart-bbeaeff5-c383-493b-a349-5d8905255d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205471557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1205471557
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2717867903
Short name T563
Test name
Test status
Simulation time 28965220 ps
CPU time 0.66 seconds
Started Jul 23 06:18:00 PM PDT 24
Finished Jul 23 06:18:03 PM PDT 24
Peak memory 198544 kb
Host smart-d8007521-55cf-47da-86db-20542eab96f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717867903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2717867903
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1876302111
Short name T498
Test name
Test status
Simulation time 159540772 ps
CPU time 1 seconds
Started Jul 23 06:18:02 PM PDT 24
Finished Jul 23 06:18:05 PM PDT 24
Peak memory 198956 kb
Host smart-ea12d7a4-d41c-4b2c-8a5c-29c04af2d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876302111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1876302111
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3922709705
Short name T363
Test name
Test status
Simulation time 64609471 ps
CPU time 0.62 seconds
Started Jul 23 06:17:59 PM PDT 24
Finished Jul 23 06:18:01 PM PDT 24
Peak memory 198808 kb
Host smart-81587c9f-0c6c-41e3-9e36-b80634bc547f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922709705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3922709705
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1919551749
Short name T374
Test name
Test status
Simulation time 76720761 ps
CPU time 0.61 seconds
Started Jul 23 06:18:01 PM PDT 24
Finished Jul 23 06:18:03 PM PDT 24
Peak memory 198560 kb
Host smart-ff773268-c8d5-4a43-a467-020bfbaaf785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919551749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1919551749
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3544834297
Short name T183
Test name
Test status
Simulation time 45250456 ps
CPU time 0.74 seconds
Started Jul 23 06:18:01 PM PDT 24
Finished Jul 23 06:18:03 PM PDT 24
Peak memory 201952 kb
Host smart-454f52a5-7b52-44ef-9104-753275f6118e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544834297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3544834297
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.2746844234
Short name T390
Test name
Test status
Simulation time 129941725 ps
CPU time 0.74 seconds
Started Jul 23 06:17:59 PM PDT 24
Finished Jul 23 06:18:01 PM PDT 24
Peak memory 199168 kb
Host smart-d9dd5510-4ac3-4b0a-8ba0-9290c02ee8d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746844234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2746844234
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.4162880665
Short name T266
Test name
Test status
Simulation time 194300302 ps
CPU time 0.84 seconds
Started Jul 23 06:18:00 PM PDT 24
Finished Jul 23 06:18:03 PM PDT 24
Peak memory 210076 kb
Host smart-c003d2d3-8659-4cb8-9ece-420618679eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162880665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.4162880665
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2663425135
Short name T515
Test name
Test status
Simulation time 58526342 ps
CPU time 0.85 seconds
Started Jul 23 06:18:01 PM PDT 24
Finished Jul 23 06:18:04 PM PDT 24
Peak memory 198596 kb
Host smart-cdca370d-271f-46da-b3d5-527a6447d0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663425135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2663425135
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2696059126
Short name T325
Test name
Test status
Simulation time 40128875 ps
CPU time 0.64 seconds
Started Jul 23 06:18:05 PM PDT 24
Finished Jul 23 06:18:06 PM PDT 24
Peak memory 199028 kb
Host smart-852f59e1-dd29-4271-9b88-9839ccc7ec35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696059126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2696059126
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2098208469
Short name T512
Test name
Test status
Simulation time 69651688 ps
CPU time 0.69 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 199304 kb
Host smart-8dadd197-d1f1-4171-b78d-175f9f4c294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098208469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2098208469
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1128888788
Short name T199
Test name
Test status
Simulation time 50275398 ps
CPU time 0.78 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 199776 kb
Host smart-bc85c08a-f7b7-49aa-95b0-6bfbd32d9e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128888788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.1128888788
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1565001418
Short name T536
Test name
Test status
Simulation time 45725073 ps
CPU time 0.61 seconds
Started Jul 23 06:18:07 PM PDT 24
Finished Jul 23 06:18:09 PM PDT 24
Peak memory 197900 kb
Host smart-598036f2-9e39-440f-ae2f-02ea24c05e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565001418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1565001418
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3176571212
Short name T623
Test name
Test status
Simulation time 801678060 ps
CPU time 0.99 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:11 PM PDT 24
Peak memory 198832 kb
Host smart-805cb41d-b664-4cde-9c33-f63389ecab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176571212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3176571212
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2960611746
Short name T260
Test name
Test status
Simulation time 54197679 ps
CPU time 0.71 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198532 kb
Host smart-b938afbc-caa3-4d35-b1e5-558616400f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960611746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2960611746
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.828841470
Short name T576
Test name
Test status
Simulation time 43274702 ps
CPU time 0.62 seconds
Started Jul 23 06:18:07 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 198644 kb
Host smart-5e6579f8-0607-481a-9afb-3decaa70aef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828841470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.828841470
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1252462575
Short name T165
Test name
Test status
Simulation time 59417643 ps
CPU time 0.69 seconds
Started Jul 23 06:18:05 PM PDT 24
Finished Jul 23 06:18:07 PM PDT 24
Peak memory 201880 kb
Host smart-b86785f9-a267-4091-89e1-ca0a5a5c4e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252462575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1252462575
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2209699975
Short name T34
Test name
Test status
Simulation time 108982412 ps
CPU time 0.72 seconds
Started Jul 23 06:18:06 PM PDT 24
Finished Jul 23 06:18:08 PM PDT 24
Peak memory 198908 kb
Host smart-d28bd766-5b41-405e-8b70-26a3701262e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209699975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2209699975
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.2907560278
Short name T93
Test name
Test status
Simulation time 101207559 ps
CPU time 1.12 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:11 PM PDT 24
Peak memory 210116 kb
Host smart-62ca3631-ce20-4291-b517-089a9fb71557
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907560278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.2907560278
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1948503703
Short name T206
Test name
Test status
Simulation time 143870932 ps
CPU time 0.8 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 199828 kb
Host smart-a1efd4c2-62dd-4747-b0c6-3b6ebe287849
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948503703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1948503703
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3663093035
Short name T416
Test name
Test status
Simulation time 29552104 ps
CPU time 0.73 seconds
Started Jul 23 06:18:00 PM PDT 24
Finished Jul 23 06:18:02 PM PDT 24
Peak memory 199844 kb
Host smart-30e55c96-a85a-4157-8c19-c8f581ffaf39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663093035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3663093035
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2114649557
Short name T474
Test name
Test status
Simulation time 51805556 ps
CPU time 0.8 seconds
Started Jul 23 06:18:06 PM PDT 24
Finished Jul 23 06:18:09 PM PDT 24
Peak memory 199576 kb
Host smart-90e993f3-2f19-4a89-9b2a-29d82f99fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114649557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2114649557
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2911348654
Short name T476
Test name
Test status
Simulation time 63662697 ps
CPU time 0.69 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:15 PM PDT 24
Peak memory 198964 kb
Host smart-eebabdfc-957e-4ba1-b73c-775bbf7f1c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911348654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2911348654
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3862757079
Short name T10
Test name
Test status
Simulation time 48411011 ps
CPU time 0.59 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 197740 kb
Host smart-a6e45355-935b-4d95-a45f-98751f09d4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862757079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3862757079
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.184851594
Short name T353
Test name
Test status
Simulation time 162118843 ps
CPU time 0.95 seconds
Started Jul 23 06:18:08 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 198824 kb
Host smart-bb89ca39-5113-45ef-9a73-64cc5a4fe3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184851594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.184851594
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1964835441
Short name T385
Test name
Test status
Simulation time 40995487 ps
CPU time 0.66 seconds
Started Jul 23 06:18:10 PM PDT 24
Finished Jul 23 06:18:12 PM PDT 24
Peak memory 198512 kb
Host smart-91e987c6-4470-4527-97e0-1456ab12d3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964835441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1964835441
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2761010365
Short name T508
Test name
Test status
Simulation time 38144039 ps
CPU time 0.64 seconds
Started Jul 23 06:18:06 PM PDT 24
Finished Jul 23 06:18:08 PM PDT 24
Peak memory 198876 kb
Host smart-2bd08b7b-c4f2-4736-9e50-3e8f1ccadd3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761010365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2761010365
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2297551332
Short name T243
Test name
Test status
Simulation time 55475543 ps
CPU time 0.71 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 198412 kb
Host smart-03dce40a-8ee2-45be-a0c3-a5ba518d3b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297551332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2297551332
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3764098826
Short name T514
Test name
Test status
Simulation time 94497517 ps
CPU time 1.07 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:18 PM PDT 24
Peak memory 209616 kb
Host smart-13198952-d5b9-4efe-97c2-8ed3803382c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764098826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3764098826
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1695244182
Short name T605
Test name
Test status
Simulation time 91177523 ps
CPU time 0.87 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 198712 kb
Host smart-5243521d-5470-4970-b86b-09280cd0f454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695244182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1695244182
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.3188916485
Short name T319
Test name
Test status
Simulation time 52759261 ps
CPU time 0.63 seconds
Started Jul 23 06:18:07 PM PDT 24
Finished Jul 23 06:18:10 PM PDT 24
Peak memory 199120 kb
Host smart-f08bcaa5-c59a-4c44-b8e2-8773ee0c6ff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188916485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.3188916485
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3423055640
Short name T481
Test name
Test status
Simulation time 42263274 ps
CPU time 0.89 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:38 PM PDT 24
Peak memory 200616 kb
Host smart-68003a40-e7b5-48b9-b6b1-7e9e67cb208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423055640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3423055640
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.4103733030
Short name T409
Test name
Test status
Simulation time 70488548 ps
CPU time 0.64 seconds
Started Jul 23 06:16:28 PM PDT 24
Finished Jul 23 06:16:33 PM PDT 24
Peak memory 199032 kb
Host smart-6d233abd-ceda-4130-9f7f-08be2df0976a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103733030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.4103733030
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2321747833
Short name T217
Test name
Test status
Simulation time 32690952 ps
CPU time 0.61 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 198640 kb
Host smart-35d91480-eb03-4cfe-9c61-f426ff0662d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321747833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2321747833
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.998757273
Short name T231
Test name
Test status
Simulation time 317193505 ps
CPU time 0.94 seconds
Started Jul 23 06:16:34 PM PDT 24
Finished Jul 23 06:16:39 PM PDT 24
Peak memory 198644 kb
Host smart-ec26ee0c-0368-43eb-bcb8-de82b3bba7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998757273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.998757273
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.2853358102
Short name T600
Test name
Test status
Simulation time 40941637 ps
CPU time 0.67 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 198516 kb
Host smart-61b48d5a-707c-43be-b265-d993e8ba3be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853358102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2853358102
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3228140683
Short name T394
Test name
Test status
Simulation time 26136790 ps
CPU time 0.61 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 198912 kb
Host smart-9b75dc6f-de15-4b6b-8131-1d12560ca862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228140683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3228140683
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1075411687
Short name T175
Test name
Test status
Simulation time 55955871 ps
CPU time 0.7 seconds
Started Jul 23 06:16:32 PM PDT 24
Finished Jul 23 06:16:36 PM PDT 24
Peak memory 201936 kb
Host smart-a654b0a6-38ca-4f59-95f7-994995d339c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075411687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1075411687
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1233284119
Short name T437
Test name
Test status
Simulation time 57038335 ps
CPU time 0.89 seconds
Started Jul 23 06:16:30 PM PDT 24
Finished Jul 23 06:16:35 PM PDT 24
Peak memory 199672 kb
Host smart-c73de6dc-a59c-418f-b749-0d705fb1e649
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233284119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1233284119
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3721519735
Short name T346
Test name
Test status
Simulation time 120779736 ps
CPU time 0.89 seconds
Started Jul 23 06:16:30 PM PDT 24
Finished Jul 23 06:16:34 PM PDT 24
Peak memory 210024 kb
Host smart-cb973f98-f23d-49b2-a1de-2348d645a055
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721519735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3721519735
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3029497545
Short name T21
Test name
Test status
Simulation time 500583490 ps
CPU time 1.17 seconds
Started Jul 23 06:16:30 PM PDT 24
Finished Jul 23 06:16:34 PM PDT 24
Peak memory 217376 kb
Host smart-5d4569ac-9560-4fdd-bb4c-a5c04e314d73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029497545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3029497545
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.856214619
Short name T583
Test name
Test status
Simulation time 203218065 ps
CPU time 0.77 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 199932 kb
Host smart-7f20e93f-f803-49c8-8176-21cf4646e89e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856214619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.856214619
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2573807094
Short name T443
Test name
Test status
Simulation time 58126561 ps
CPU time 0.64 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 199944 kb
Host smart-f6bec3ab-56eb-4827-be13-72eedc957eba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573807094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2573807094
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2320912652
Short name T428
Test name
Test status
Simulation time 48012158 ps
CPU time 0.92 seconds
Started Jul 23 06:18:19 PM PDT 24
Finished Jul 23 06:18:24 PM PDT 24
Peak memory 201312 kb
Host smart-6dcd12f7-60e3-46c8-8d80-54a488966a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320912652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2320912652
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.2237469828
Short name T139
Test name
Test status
Simulation time 30695899 ps
CPU time 0.63 seconds
Started Jul 23 06:18:14 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 198600 kb
Host smart-54759937-157e-4928-9f0a-cc22b6db6915
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237469828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.2237469828
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.1566010176
Short name T281
Test name
Test status
Simulation time 1073444135 ps
CPU time 0.92 seconds
Started Jul 23 06:18:10 PM PDT 24
Finished Jul 23 06:18:13 PM PDT 24
Peak memory 198968 kb
Host smart-d9f5ae9f-77ec-4825-86e4-23b4b4826a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566010176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1566010176
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.1074581222
Short name T480
Test name
Test status
Simulation time 65033234 ps
CPU time 0.66 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 197876 kb
Host smart-1d0e7062-945c-42b9-aec5-0f5e3c8c4632
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074581222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.1074581222
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.4162195662
Short name T426
Test name
Test status
Simulation time 74995866 ps
CPU time 0.71 seconds
Started Jul 23 06:18:14 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 198580 kb
Host smart-9d22a4e7-c4b8-4fc2-b8fd-efc34b06a4de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162195662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.4162195662
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2202617032
Short name T543
Test name
Test status
Simulation time 165988483 ps
CPU time 0.72 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:16 PM PDT 24
Peak memory 201972 kb
Host smart-a22cf231-a226-4297-81ef-b31ad0cc2f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202617032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2202617032
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.4267070469
Short name T442
Test name
Test status
Simulation time 80067853 ps
CPU time 0.9 seconds
Started Jul 23 06:18:15 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 199584 kb
Host smart-f3b69fad-c718-47fd-bf14-99ed495d7f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267070469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.4267070469
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2104679252
Short name T7
Test name
Test status
Simulation time 129976082 ps
CPU time 0.84 seconds
Started Jul 23 06:18:15 PM PDT 24
Finished Jul 23 06:18:20 PM PDT 24
Peak memory 210060 kb
Host smart-96a78490-e6d9-47fb-b769-716890b395f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104679252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2104679252
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4013840861
Short name T238
Test name
Test status
Simulation time 58921182 ps
CPU time 0.82 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 198704 kb
Host smart-34682350-538a-47f4-8c8e-85e9af3417ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013840861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4013840861
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3961904645
Short name T286
Test name
Test status
Simulation time 32000400 ps
CPU time 0.7 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:16 PM PDT 24
Peak memory 199920 kb
Host smart-b4a8e6a6-5356-42fb-a82b-850dbd3da79c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961904645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3961904645
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3163567367
Short name T595
Test name
Test status
Simulation time 93595476 ps
CPU time 0.84 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 200608 kb
Host smart-010cd597-9596-48b8-b675-a38fe5a91813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163567367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3163567367
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.3139901729
Short name T596
Test name
Test status
Simulation time 88410444 ps
CPU time 0.68 seconds
Started Jul 23 06:18:15 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 199664 kb
Host smart-2fa5b80a-5ee5-4654-9e64-acf69822ab23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139901729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.3139901729
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2036837320
Short name T523
Test name
Test status
Simulation time 30057419 ps
CPU time 0.61 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:18 PM PDT 24
Peak memory 197864 kb
Host smart-fd7205ac-7936-42c0-8584-469c424e11bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036837320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2036837320
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1516725449
Short name T526
Test name
Test status
Simulation time 161098954 ps
CPU time 0.98 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198668 kb
Host smart-526eb760-3754-42ae-9ee3-9435f316fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516725449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1516725449
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3519236149
Short name T18
Test name
Test status
Simulation time 37792249 ps
CPU time 0.67 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:16 PM PDT 24
Peak memory 197896 kb
Host smart-1a06fff2-49ce-4b4d-9a51-dd6ee99ca4d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519236149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3519236149
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1084852690
Short name T505
Test name
Test status
Simulation time 68236234 ps
CPU time 0.66 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:13 PM PDT 24
Peak memory 198836 kb
Host smart-c52d981f-6265-417a-a5b3-49ef10997e91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084852690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1084852690
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3877107716
Short name T529
Test name
Test status
Simulation time 45618155 ps
CPU time 0.69 seconds
Started Jul 23 06:18:15 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 202008 kb
Host smart-7cc712a3-f63a-46c4-8cc2-00ed438be935
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877107716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.3877107716
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.3044426051
Short name T179
Test name
Test status
Simulation time 80841173 ps
CPU time 0.64 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:18 PM PDT 24
Peak memory 198676 kb
Host smart-8aa52321-b416-4c72-927f-391ac3cebfc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044426051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.3044426051
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3564833588
Short name T359
Test name
Test status
Simulation time 63970178 ps
CPU time 0.85 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198956 kb
Host smart-44a365e4-13d8-4e0a-b76c-8472165adeac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564833588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3564833588
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4276303017
Short name T333
Test name
Test status
Simulation time 157184321 ps
CPU time 0.86 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 201932 kb
Host smart-59fcdcb9-14f9-4ca8-89f9-b98f9a7028e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276303017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4276303017
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.24108352
Short name T232
Test name
Test status
Simulation time 99995676 ps
CPU time 0.72 seconds
Started Jul 23 06:18:11 PM PDT 24
Finished Jul 23 06:18:14 PM PDT 24
Peak memory 198788 kb
Host smart-9dd07005-96e7-4eb0-905f-45c5ab192a5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24108352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.24108352
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3309569197
Short name T396
Test name
Test status
Simulation time 38696499 ps
CPU time 0.65 seconds
Started Jul 23 06:18:14 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 199040 kb
Host smart-d69d8ca4-906c-4338-b52d-8bb351d0a56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309569197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3309569197
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.2928110613
Short name T561
Test name
Test status
Simulation time 173982797 ps
CPU time 0.76 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 199708 kb
Host smart-e585ddad-a487-413a-90df-29275d1260a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928110613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.2928110613
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2502362164
Short name T490
Test name
Test status
Simulation time 96504241 ps
CPU time 0.84 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 200508 kb
Host smart-b261adc9-6d3d-4169-bdda-66241f4a993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502362164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2502362164
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1600064730
Short name T316
Test name
Test status
Simulation time 64974577 ps
CPU time 0.74 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 199728 kb
Host smart-ac77c677-af94-4082-9f32-7e3c0f679f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600064730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1600064730
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2845952659
Short name T489
Test name
Test status
Simulation time 32833711 ps
CPU time 0.63 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198600 kb
Host smart-ad1cc738-e06a-4c43-80b8-193f89d42d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845952659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2845952659
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2213234354
Short name T606
Test name
Test status
Simulation time 324756803 ps
CPU time 0.94 seconds
Started Jul 23 06:18:14 PM PDT 24
Finished Jul 23 06:18:18 PM PDT 24
Peak memory 198676 kb
Host smart-945ea378-9623-4497-878c-42a5301f2a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213234354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2213234354
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.934624534
Short name T3
Test name
Test status
Simulation time 46786457 ps
CPU time 0.65 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198624 kb
Host smart-e949fcb2-a733-4268-8f89-a27ef079bda6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934624534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.934624534
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3651438381
Short name T460
Test name
Test status
Simulation time 88186651 ps
CPU time 0.66 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 198628 kb
Host smart-7016e090-8f32-419c-a81b-9065cf3b4db9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651438381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3651438381
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.1689367721
Short name T185
Test name
Test status
Simulation time 44511589 ps
CPU time 0.74 seconds
Started Jul 23 06:18:21 PM PDT 24
Finished Jul 23 06:18:26 PM PDT 24
Peak memory 202036 kb
Host smart-f346e16a-963f-406c-9323-2b71e4d87a5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689367721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.1689367721
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1080898894
Short name T569
Test name
Test status
Simulation time 63309754 ps
CPU time 0.87 seconds
Started Jul 23 06:18:16 PM PDT 24
Finished Jul 23 06:18:21 PM PDT 24
Peak memory 199648 kb
Host smart-614c9499-657f-4248-99a2-887a0f7660dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080898894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1080898894
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.951604730
Short name T504
Test name
Test status
Simulation time 107998922 ps
CPU time 1.19 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 210012 kb
Host smart-4abc6bba-a404-4848-9cba-6d50f95ab33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951604730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.951604730
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2444940522
Short name T517
Test name
Test status
Simulation time 82292467 ps
CPU time 0.83 seconds
Started Jul 23 06:18:13 PM PDT 24
Finished Jul 23 06:18:17 PM PDT 24
Peak memory 200128 kb
Host smart-53a6a255-7fcd-458d-9e49-53d3dffe2d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444940522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2444940522
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.867523972
Short name T435
Test name
Test status
Simulation time 42878543 ps
CPU time 0.64 seconds
Started Jul 23 06:18:17 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 200052 kb
Host smart-e2419f10-623d-4d15-83f3-b29b32e2b650
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867523972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.867523972
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3973316408
Short name T144
Test name
Test status
Simulation time 127466903 ps
CPU time 0.71 seconds
Started Jul 23 06:18:12 PM PDT 24
Finished Jul 23 06:18:16 PM PDT 24
Peak memory 198852 kb
Host smart-efb811a7-b3da-4cd8-99a9-6775e76b994b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973316408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3973316408
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.3550496704
Short name T590
Test name
Test status
Simulation time 55092213 ps
CPU time 0.66 seconds
Started Jul 23 06:18:19 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 199112 kb
Host smart-d68b5b33-a2df-4e7c-a6f7-dadb220ea677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550496704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3550496704
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2664470786
Short name T545
Test name
Test status
Simulation time 148478060 ps
CPU time 0.66 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 198992 kb
Host smart-9a6944c6-9bd8-47c9-a33f-e904c016fb45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664470786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2664470786
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2532941448
Short name T433
Test name
Test status
Simulation time 38691042 ps
CPU time 0.58 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 198572 kb
Host smart-a23cb213-1815-4cef-a29e-54f0fbb4b919
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532941448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2532941448
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2663066751
Short name T226
Test name
Test status
Simulation time 626128075 ps
CPU time 0.98 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 198660 kb
Host smart-134f54ea-cb52-44ba-9b26-d12da4e37416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663066751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2663066751
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.637766639
Short name T239
Test name
Test status
Simulation time 82114449 ps
CPU time 0.66 seconds
Started Jul 23 06:18:14 PM PDT 24
Finished Jul 23 06:18:19 PM PDT 24
Peak memory 197892 kb
Host smart-fbc97d28-db6a-4c21-acd6-de88007f8231
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637766639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.637766639
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3200025396
Short name T427
Test name
Test status
Simulation time 178259043 ps
CPU time 0.66 seconds
Started Jul 23 06:18:17 PM PDT 24
Finished Jul 23 06:18:22 PM PDT 24
Peak memory 198644 kb
Host smart-9e134c81-230b-4c96-9d89-b80187d35194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200025396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3200025396
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.3707497180
Short name T2
Test name
Test status
Simulation time 81607035 ps
CPU time 0.77 seconds
Started Jul 23 06:18:27 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 199656 kb
Host smart-1a0961ac-c881-40fe-9b3f-93d5c28c23aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707497180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.3707497180
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.977014249
Short name T510
Test name
Test status
Simulation time 160397572 ps
CPU time 0.82 seconds
Started Jul 23 06:18:27 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 210104 kb
Host smart-15a46604-faf5-4cf1-993c-e4a4a770873b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977014249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.977014249
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2151384954
Short name T82
Test name
Test status
Simulation time 75525429 ps
CPU time 0.76 seconds
Started Jul 23 06:18:19 PM PDT 24
Finished Jul 23 06:18:25 PM PDT 24
Peak memory 198772 kb
Host smart-29b5bf71-dafa-492a-8dcf-0d6b86f1e54a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151384954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2151384954
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.165342790
Short name T268
Test name
Test status
Simulation time 28404836 ps
CPU time 0.67 seconds
Started Jul 23 06:18:17 PM PDT 24
Finished Jul 23 06:18:22 PM PDT 24
Peak memory 199032 kb
Host smart-8edbe81a-a253-406a-8857-9b3693c9c1c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165342790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.165342790
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.3711635335
Short name T326
Test name
Test status
Simulation time 254553057 ps
CPU time 0.78 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 200576 kb
Host smart-c7be59c7-c4bb-42f5-b981-0719b98e50ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711635335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.3711635335
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1779315772
Short name T28
Test name
Test status
Simulation time 59622978 ps
CPU time 0.79 seconds
Started Jul 23 06:18:17 PM PDT 24
Finished Jul 23 06:18:22 PM PDT 24
Peak memory 199672 kb
Host smart-0cfcf2f9-1154-43fb-97cf-55995be8f5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779315772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1779315772
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1768651935
Short name T338
Test name
Test status
Simulation time 33282032 ps
CPU time 0.6 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 198580 kb
Host smart-495229ab-e18f-4006-8b15-0aa2d7dd5a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768651935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1768651935
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.1726441993
Short name T601
Test name
Test status
Simulation time 170181573 ps
CPU time 1.01 seconds
Started Jul 23 06:18:22 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 198224 kb
Host smart-b0483d39-c956-47f0-b6a1-8d31db1b9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726441993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1726441993
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.2283026549
Short name T270
Test name
Test status
Simulation time 46819762 ps
CPU time 0.62 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 198684 kb
Host smart-f70da05a-ebbf-45af-b8c4-414fa64e3d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283026549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.2283026549
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3280122797
Short name T449
Test name
Test status
Simulation time 29840036 ps
CPU time 0.62 seconds
Started Jul 23 06:18:17 PM PDT 24
Finished Jul 23 06:18:22 PM PDT 24
Peak memory 198568 kb
Host smart-d2e2a0a9-9347-477c-b71f-ce5a7d3095e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280122797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3280122797
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.4214348600
Short name T161
Test name
Test status
Simulation time 42126856 ps
CPU time 0.71 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 201964 kb
Host smart-0efe3171-8410-40be-9253-a1918c12ed71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214348600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.4214348600
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3742059805
Short name T254
Test name
Test status
Simulation time 60530610 ps
CPU time 0.66 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 199672 kb
Host smart-7745e0bb-b9aa-4303-98a7-f531871a3519
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742059805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3742059805
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.2066757587
Short name T5
Test name
Test status
Simulation time 292808093 ps
CPU time 0.77 seconds
Started Jul 23 06:18:19 PM PDT 24
Finished Jul 23 06:18:24 PM PDT 24
Peak memory 210028 kb
Host smart-09f13826-e0da-43af-bd62-61f89a0f0c53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066757587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2066757587
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1108197073
Short name T573
Test name
Test status
Simulation time 81503032 ps
CPU time 0.83 seconds
Started Jul 23 06:18:18 PM PDT 24
Finished Jul 23 06:18:23 PM PDT 24
Peak memory 200136 kb
Host smart-11c91cba-e400-4051-9b09-126a55196867
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108197073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1108197073
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1766793977
Short name T280
Test name
Test status
Simulation time 30929416 ps
CPU time 0.66 seconds
Started Jul 23 06:18:27 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 199088 kb
Host smart-cb3ee6a3-fe78-4668-a8d0-a88aa9c6dcd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766793977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1766793977
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.2673142632
Short name T538
Test name
Test status
Simulation time 25064777 ps
CPU time 0.66 seconds
Started Jul 23 06:18:22 PM PDT 24
Finished Jul 23 06:18:26 PM PDT 24
Peak memory 199252 kb
Host smart-07d4848c-c96a-4f54-bcd1-fccc1098f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673142632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.2673142632
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2969390610
Short name T142
Test name
Test status
Simulation time 51929491 ps
CPU time 0.79 seconds
Started Jul 23 06:18:26 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 199652 kb
Host smart-5c8ddd57-e2b3-454e-abe6-d26c65e669b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969390610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2969390610
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3961645077
Short name T32
Test name
Test status
Simulation time 41059689 ps
CPU time 0.63 seconds
Started Jul 23 06:18:25 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 198584 kb
Host smart-86e5f238-4251-43b1-9175-cec6f7daaefa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961645077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3961645077
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.1134030719
Short name T137
Test name
Test status
Simulation time 177333361 ps
CPU time 0.99 seconds
Started Jul 23 06:18:31 PM PDT 24
Finished Jul 23 06:18:35 PM PDT 24
Peak memory 198636 kb
Host smart-96144931-afb8-4340-bd56-80fe586a2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134030719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1134030719
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3969304323
Short name T64
Test name
Test status
Simulation time 74325019 ps
CPU time 0.66 seconds
Started Jul 23 06:18:24 PM PDT 24
Finished Jul 23 06:18:28 PM PDT 24
Peak memory 198088 kb
Host smart-5d0dcf4f-bbe1-426b-b474-d3196a9bb6a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969304323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3969304323
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3008353408
Short name T92
Test name
Test status
Simulation time 62699981 ps
CPU time 0.65 seconds
Started Jul 23 06:18:31 PM PDT 24
Finished Jul 23 06:18:34 PM PDT 24
Peak memory 198604 kb
Host smart-0f1f5d4b-14d5-48dc-9340-9cf77f396296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008353408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3008353408
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.580047458
Short name T191
Test name
Test status
Simulation time 112724499 ps
CPU time 0.71 seconds
Started Jul 23 06:18:25 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 201956 kb
Host smart-4d97c14a-602e-4bdd-9c93-8dd92d48478e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580047458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.580047458
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.3013967464
Short name T607
Test name
Test status
Simulation time 21705796 ps
CPU time 0.65 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 198752 kb
Host smart-3b1ef8dd-911a-4cfe-8182-197623578f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013967464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3013967464
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.912583829
Short name T315
Test name
Test status
Simulation time 115152982 ps
CPU time 0.88 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:28 PM PDT 24
Peak memory 210120 kb
Host smart-4a370c35-da67-4dc7-b5fd-aeb5b59023c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912583829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.912583829
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.925435155
Short name T391
Test name
Test status
Simulation time 63836416 ps
CPU time 0.85 seconds
Started Jul 23 06:18:26 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 198792 kb
Host smart-62f8c607-6e0d-4726-852b-0c49332f4245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925435155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.925435155
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2156646064
Short name T296
Test name
Test status
Simulation time 29892401 ps
CPU time 0.67 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 199936 kb
Host smart-8639f596-21e9-4502-8a7c-e3f094aec173
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156646064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2156646064
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2247998734
Short name T54
Test name
Test status
Simulation time 91711146 ps
CPU time 0.85 seconds
Started Jul 23 06:18:27 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 200512 kb
Host smart-d12b11af-0600-4d29-9cf0-400b922b0606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247998734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2247998734
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1920959218
Short name T4
Test name
Test status
Simulation time 74962976 ps
CPU time 0.68 seconds
Started Jul 23 06:18:24 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 198940 kb
Host smart-f8565dca-db2e-4fd3-9c9c-481c2fc41988
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920959218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1920959218
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1872670550
Short name T372
Test name
Test status
Simulation time 29763326 ps
CPU time 0.66 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:27 PM PDT 24
Peak memory 198576 kb
Host smart-b76d3182-c47d-452b-96f6-ea99e1d1063a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872670550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.1872670550
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.1162014591
Short name T277
Test name
Test status
Simulation time 597067669 ps
CPU time 0.95 seconds
Started Jul 23 06:18:26 PM PDT 24
Finished Jul 23 06:18:31 PM PDT 24
Peak memory 198628 kb
Host smart-6022930b-47ec-4649-aa68-175f249ebc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162014591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1162014591
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3983074508
Short name T213
Test name
Test status
Simulation time 28677822 ps
CPU time 0.64 seconds
Started Jul 23 06:18:24 PM PDT 24
Finished Jul 23 06:18:29 PM PDT 24
Peak memory 198644 kb
Host smart-37e5496c-4199-4206-be5b-1608d6db01f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983074508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3983074508
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3326060559
Short name T261
Test name
Test status
Simulation time 56941106 ps
CPU time 0.64 seconds
Started Jul 23 06:18:24 PM PDT 24
Finished Jul 23 06:18:28 PM PDT 24
Peak memory 198836 kb
Host smart-ff0624c1-afd5-4ab5-8ead-33e23606720c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326060559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3326060559
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3252922598
Short name T163
Test name
Test status
Simulation time 42937538 ps
CPU time 0.75 seconds
Started Jul 23 06:18:23 PM PDT 24
Finished Jul 23 06:18:28 PM PDT 24
Peak memory 202020 kb
Host smart-6805fd9c-6bbd-4d16-bb05-508358c09cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252922598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3252922598
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2084692909
Short name T445
Test name
Test status
Simulation time 62313057 ps
CPU time 0.76 seconds
Started Jul 23 06:18:31 PM PDT 24
Finished Jul 23 06:18:34 PM PDT 24
Peak memory 199684 kb
Host smart-f8f2ffa7-a2c5-44f8-8a30-283db1ce0c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084692909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2084692909
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.795542543
Short name T211
Test name
Test status
Simulation time 154724731 ps
CPU time 0.84 seconds
Started Jul 23 06:18:28 PM PDT 24
Finished Jul 23 06:18:32 PM PDT 24
Peak memory 209976 kb
Host smart-53126c37-4556-4bc1-bf3e-db9538bf847a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795542543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.795542543
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1027925470
Short name T370
Test name
Test status
Simulation time 51543920 ps
CPU time 0.86 seconds
Started Jul 23 06:18:26 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 199476 kb
Host smart-1d11559a-2009-42d9-b703-de75652a61aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027925470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1027925470
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.913787141
Short name T618
Test name
Test status
Simulation time 34388306 ps
CPU time 0.68 seconds
Started Jul 23 06:18:25 PM PDT 24
Finished Jul 23 06:18:30 PM PDT 24
Peak memory 199928 kb
Host smart-631b0972-8119-4f4d-adea-15c4d75e0b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913787141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.913787141
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3747963588
Short name T123
Test name
Test status
Simulation time 125820840 ps
CPU time 0.88 seconds
Started Jul 23 06:18:25 PM PDT 24
Finished Jul 23 06:18:29 PM PDT 24
Peak memory 201308 kb
Host smart-7dc250aa-6ca2-4dc6-b04d-892f4955c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747963588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3747963588
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2376041554
Short name T585
Test name
Test status
Simulation time 71711543 ps
CPU time 0.7 seconds
Started Jul 23 06:18:30 PM PDT 24
Finished Jul 23 06:18:33 PM PDT 24
Peak memory 198968 kb
Host smart-00ed77a9-033e-4396-a8a7-1d5d909c9e0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376041554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2376041554
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.4270150932
Short name T267
Test name
Test status
Simulation time 31719374 ps
CPU time 0.64 seconds
Started Jul 23 06:18:38 PM PDT 24
Finished Jul 23 06:18:40 PM PDT 24
Peak memory 198632 kb
Host smart-013de8c5-7836-4808-b188-e45fc000bdea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270150932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.4270150932
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.855040769
Short name T567
Test name
Test status
Simulation time 159033278 ps
CPU time 1.09 seconds
Started Jul 23 06:18:32 PM PDT 24
Finished Jul 23 06:18:35 PM PDT 24
Peak memory 198640 kb
Host smart-8377ed2b-4d02-4a6c-b565-24d05c9f776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855040769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.855040769
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3678604330
Short name T247
Test name
Test status
Simulation time 76508224 ps
CPU time 0.64 seconds
Started Jul 23 06:18:35 PM PDT 24
Finished Jul 23 06:18:36 PM PDT 24
Peak memory 198704 kb
Host smart-e0087787-eab5-4a81-a425-900f7b27fdd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678604330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3678604330
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1684510493
Short name T263
Test name
Test status
Simulation time 39087398 ps
CPU time 0.69 seconds
Started Jul 23 06:18:31 PM PDT 24
Finished Jul 23 06:18:33 PM PDT 24
Peak memory 198568 kb
Host smart-9a635c01-91c9-4722-871e-44eea48723a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684510493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1684510493
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3689313010
Short name T166
Test name
Test status
Simulation time 42965550 ps
CPU time 0.74 seconds
Started Jul 23 06:18:29 PM PDT 24
Finished Jul 23 06:18:33 PM PDT 24
Peak memory 201980 kb
Host smart-4bab9fea-3def-43ec-95fd-51dd07d66d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689313010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3689313010
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.945681718
Short name T616
Test name
Test status
Simulation time 47094539 ps
CPU time 0.65 seconds
Started Jul 23 06:18:24 PM PDT 24
Finished Jul 23 06:18:28 PM PDT 24
Peak memory 198708 kb
Host smart-3174c160-e483-4759-937f-543b5f782b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945681718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.945681718
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.805170297
Short name T471
Test name
Test status
Simulation time 148828254 ps
CPU time 0.76 seconds
Started Jul 23 06:18:31 PM PDT 24
Finished Jul 23 06:18:34 PM PDT 24
Peak memory 210100 kb
Host smart-29634b17-a903-4bf6-8148-b46db691fdc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805170297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.805170297
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.4198142847
Short name T527
Test name
Test status
Simulation time 74330253 ps
CPU time 0.73 seconds
Started Jul 23 06:18:30 PM PDT 24
Finished Jul 23 06:18:33 PM PDT 24
Peak memory 198768 kb
Host smart-7963e26b-e2ef-4063-89c8-8cef2cc68fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198142847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4198142847
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1021073057
Short name T511
Test name
Test status
Simulation time 23705425 ps
CPU time 0.72 seconds
Started Jul 23 06:18:29 PM PDT 24
Finished Jul 23 06:18:32 PM PDT 24
Peak memory 199708 kb
Host smart-a48d21e1-6791-4e36-81aa-5faa56c707e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021073057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1021073057
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3315619566
Short name T456
Test name
Test status
Simulation time 40388689 ps
CPU time 0.59 seconds
Started Jul 23 06:18:38 PM PDT 24
Finished Jul 23 06:18:41 PM PDT 24
Peak memory 197904 kb
Host smart-70e9b283-47ac-46be-a215-53aa13c41ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315619566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3315619566
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3873304869
Short name T350
Test name
Test status
Simulation time 48907698 ps
CPU time 0.57 seconds
Started Jul 23 06:18:35 PM PDT 24
Finished Jul 23 06:18:37 PM PDT 24
Peak memory 197944 kb
Host smart-0450abf1-8bd4-4792-a9bd-5bddf59c67f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873304869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3873304869
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3507914518
Short name T552
Test name
Test status
Simulation time 25324077 ps
CPU time 0.64 seconds
Started Jul 23 06:18:35 PM PDT 24
Finished Jul 23 06:18:37 PM PDT 24
Peak memory 198956 kb
Host smart-32997149-e5a7-4891-afa9-299b37a264af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507914518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3507914518
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2650335060
Short name T186
Test name
Test status
Simulation time 73226187 ps
CPU time 0.66 seconds
Started Jul 23 06:18:37 PM PDT 24
Finished Jul 23 06:18:39 PM PDT 24
Peak memory 201988 kb
Host smart-8b173100-0ae9-4fdd-b33f-4a94c07025bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650335060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2650335060
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.1370015136
Short name T46
Test name
Test status
Simulation time 33468539 ps
CPU time 0.67 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:41 PM PDT 24
Peak memory 199096 kb
Host smart-4fe72713-4839-45bb-abba-b2c45e9193e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370015136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.1370015136
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.600459233
Short name T322
Test name
Test status
Simulation time 23735176 ps
CPU time 0.68 seconds
Started Jul 23 06:18:34 PM PDT 24
Finished Jul 23 06:18:36 PM PDT 24
Peak memory 198952 kb
Host smart-a485f611-b7bf-44b7-8768-71d7f4e2aa55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600459233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.600459233
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1145611800
Short name T330
Test name
Test status
Simulation time 108045654 ps
CPU time 0.92 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 210052 kb
Host smart-6858f07d-2bd6-4647-a623-9f867349f1bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145611800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1145611800
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.832994368
Short name T233
Test name
Test status
Simulation time 125564186 ps
CPU time 0.84 seconds
Started Jul 23 06:18:30 PM PDT 24
Finished Jul 23 06:18:33 PM PDT 24
Peak memory 199768 kb
Host smart-6f111699-72c0-4ec6-aa9f-af5313a53e4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832994368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.832994368
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3809286302
Short name T84
Test name
Test status
Simulation time 29325960 ps
CPU time 0.68 seconds
Started Jul 23 06:18:37 PM PDT 24
Finished Jul 23 06:18:40 PM PDT 24
Peak memory 199956 kb
Host smart-1b3fc343-8187-467e-82bd-6b8cb8dbd2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809286302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3809286302
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3525168361
Short name T303
Test name
Test status
Simulation time 42362818 ps
CPU time 0.91 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 200900 kb
Host smart-62e22a5a-2af4-4e8b-a01f-4844dcd3ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525168361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3525168361
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1529621785
Short name T421
Test name
Test status
Simulation time 96219219 ps
CPU time 0.64 seconds
Started Jul 23 06:18:40 PM PDT 24
Finished Jul 23 06:18:43 PM PDT 24
Peak memory 199716 kb
Host smart-a679de63-da13-43a6-8891-5493b1d209ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529621785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.1529621785
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.877242861
Short name T509
Test name
Test status
Simulation time 32250226 ps
CPU time 0.61 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:37 PM PDT 24
Peak memory 198608 kb
Host smart-7747af13-be23-47f8-8140-a9188ed12688
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877242861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.877242861
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2342639412
Short name T465
Test name
Test status
Simulation time 624704722 ps
CPU time 0.95 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 198672 kb
Host smart-c054ce27-4804-421f-be95-b66b0f6782f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342639412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2342639412
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.464260817
Short name T354
Test name
Test status
Simulation time 65352896 ps
CPU time 0.63 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 198604 kb
Host smart-24ed295e-982d-467f-baf9-b8483fc4c8b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464260817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.464260817
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.4063129779
Short name T381
Test name
Test status
Simulation time 95482244 ps
CPU time 0.64 seconds
Started Jul 23 06:18:39 PM PDT 24
Finished Jul 23 06:18:41 PM PDT 24
Peak memory 198632 kb
Host smart-77cafea8-c6c3-4270-be99-37963ae52b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063129779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.4063129779
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.2344629549
Short name T521
Test name
Test status
Simulation time 83350246 ps
CPU time 0.99 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:38 PM PDT 24
Peak memory 199688 kb
Host smart-ee452ffc-c228-4b21-8784-ac6e77f54ad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344629549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2344629549
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.245483646
Short name T568
Test name
Test status
Simulation time 366655147 ps
CPU time 0.81 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:38 PM PDT 24
Peak memory 210100 kb
Host smart-d33fcc24-0ad6-4833-b283-f711184126ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245483646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.245483646
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3440620845
Short name T475
Test name
Test status
Simulation time 51138713 ps
CPU time 0.89 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:38 PM PDT 24
Peak memory 199780 kb
Host smart-477c55ea-96b8-4aed-8f57-db9681e040e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440620845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3440620845
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1470564570
Short name T87
Test name
Test status
Simulation time 27934544 ps
CPU time 0.64 seconds
Started Jul 23 06:18:40 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 199072 kb
Host smart-51ed231c-4608-4e8a-976a-2664c07fe779
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470564570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1470564570
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.680883624
Short name T100
Test name
Test status
Simulation time 15470275 ps
CPU time 0.65 seconds
Started Jul 23 06:16:33 PM PDT 24
Finished Jul 23 06:16:37 PM PDT 24
Peak memory 199668 kb
Host smart-4ad6d4e9-7958-4b2c-9839-9c9e22e4f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680883624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.680883624
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3202559078
Short name T201
Test name
Test status
Simulation time 64810132 ps
CPU time 0.65 seconds
Started Jul 23 06:16:36 PM PDT 24
Finished Jul 23 06:16:40 PM PDT 24
Peak memory 198928 kb
Host smart-8123a447-87dd-4638-93ed-11ec78856faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202559078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3202559078
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1694725056
Short name T234
Test name
Test status
Simulation time 28724236 ps
CPU time 0.64 seconds
Started Jul 23 06:16:38 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 197892 kb
Host smart-cf9962fe-5951-48a5-9547-dbd061279001
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694725056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1694725056
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.749137554
Short name T242
Test name
Test status
Simulation time 830905842 ps
CPU time 1.02 seconds
Started Jul 23 06:16:38 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 198872 kb
Host smart-e310b002-7b91-48d4-ab1a-3ffb044359ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749137554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.749137554
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3774359875
Short name T395
Test name
Test status
Simulation time 33503325 ps
CPU time 0.68 seconds
Started Jul 23 06:16:37 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 198668 kb
Host smart-bd8c6892-f1e8-4161-a1b3-6ab92052b622
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774359875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3774359875
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.483404872
Short name T285
Test name
Test status
Simulation time 66710382 ps
CPU time 0.6 seconds
Started Jul 23 06:16:35 PM PDT 24
Finished Jul 23 06:16:39 PM PDT 24
Peak memory 198616 kb
Host smart-a2063435-bc44-482c-989f-09c10d92fca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483404872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.483404872
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.3939947085
Short name T182
Test name
Test status
Simulation time 45945259 ps
CPU time 0.75 seconds
Started Jul 23 06:16:39 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 201960 kb
Host smart-a65c90b2-1129-42f4-85aa-8474a7971c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939947085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.3939947085
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.2125743848
Short name T283
Test name
Test status
Simulation time 81152397 ps
CPU time 0.93 seconds
Started Jul 23 06:16:34 PM PDT 24
Finished Jul 23 06:16:39 PM PDT 24
Peak memory 199644 kb
Host smart-1cd2ce8f-2bdc-44db-9fe0-386c52e8cf04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125743848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.2125743848
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.493735953
Short name T293
Test name
Test status
Simulation time 288142866 ps
CPU time 0.78 seconds
Started Jul 23 06:16:37 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 210132 kb
Host smart-46070135-1573-4f77-b592-80c0ead3a072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493735953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.493735953
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.3635183973
Short name T30
Test name
Test status
Simulation time 682825571 ps
CPU time 2.07 seconds
Started Jul 23 06:16:38 PM PDT 24
Finished Jul 23 06:16:42 PM PDT 24
Peak memory 218476 kb
Host smart-81e38ee8-e322-448d-af57-b992cb1b5de0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635183973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3635183973
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.597548099
Short name T525
Test name
Test status
Simulation time 127626798 ps
CPU time 0.72 seconds
Started Jul 23 06:16:32 PM PDT 24
Finished Jul 23 06:16:36 PM PDT 24
Peak memory 198532 kb
Host smart-8b70aaa5-cf9e-4f12-bead-797e8d657f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597548099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.597548099
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1787493060
Short name T414
Test name
Test status
Simulation time 208179577 ps
CPU time 0.62 seconds
Started Jul 23 06:16:34 PM PDT 24
Finished Jul 23 06:16:39 PM PDT 24
Peak memory 199036 kb
Host smart-edf58843-dc6a-4a8a-bd05-8569ac928d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787493060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1787493060
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2302794317
Short name T531
Test name
Test status
Simulation time 21171310 ps
CPU time 0.71 seconds
Started Jul 23 06:18:37 PM PDT 24
Finished Jul 23 06:18:39 PM PDT 24
Peak memory 199672 kb
Host smart-65cdb8d9-6a38-4125-923e-6c419715e156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302794317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2302794317
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3299367148
Short name T532
Test name
Test status
Simulation time 69217105 ps
CPU time 0.81 seconds
Started Jul 23 06:18:45 PM PDT 24
Finished Jul 23 06:18:47 PM PDT 24
Peak memory 199116 kb
Host smart-19517824-8838-4a08-af0f-4228320c2756
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299367148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3299367148
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.377636060
Short name T302
Test name
Test status
Simulation time 32462525 ps
CPU time 0.61 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:38 PM PDT 24
Peak memory 197896 kb
Host smart-72c85013-e6f1-4701-881d-4d953a400c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377636060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.377636060
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.2873420493
Short name T308
Test name
Test status
Simulation time 165183088 ps
CPU time 1.01 seconds
Started Jul 23 06:18:41 PM PDT 24
Finished Jul 23 06:18:44 PM PDT 24
Peak memory 198876 kb
Host smart-d8ad8745-6c75-4b22-99a6-32c38543c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873420493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2873420493
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2614237726
Short name T262
Test name
Test status
Simulation time 57632283 ps
CPU time 0.67 seconds
Started Jul 23 06:18:47 PM PDT 24
Finished Jul 23 06:18:49 PM PDT 24
Peak memory 198700 kb
Host smart-90d11d9d-81d3-44cd-8073-2af0cd513d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614237726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2614237726
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.1015902084
Short name T352
Test name
Test status
Simulation time 59678351 ps
CPU time 0.59 seconds
Started Jul 23 06:18:41 PM PDT 24
Finished Jul 23 06:18:44 PM PDT 24
Peak memory 198952 kb
Host smart-d3cdb650-b321-48ba-9a2a-ab487207212c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015902084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1015902084
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1593832481
Short name T51
Test name
Test status
Simulation time 50747633 ps
CPU time 0.69 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:45 PM PDT 24
Peak memory 202040 kb
Host smart-20b985a8-ed25-48a3-9804-7ac6b6b92820
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593832481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1593832481
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3655989848
Short name T227
Test name
Test status
Simulation time 65463265 ps
CPU time 0.8 seconds
Started Jul 23 06:18:37 PM PDT 24
Finished Jul 23 06:18:39 PM PDT 24
Peak memory 198904 kb
Host smart-f52d7866-4b4a-4d74-bcb8-c32606c53e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655989848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3655989848
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3934337698
Short name T564
Test name
Test status
Simulation time 143755068 ps
CPU time 0.84 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:45 PM PDT 24
Peak memory 210048 kb
Host smart-5bbda70c-527b-4f86-8083-c79337b035a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934337698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3934337698
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1822274494
Short name T276
Test name
Test status
Simulation time 94320378 ps
CPU time 0.82 seconds
Started Jul 23 06:18:40 PM PDT 24
Finished Jul 23 06:18:42 PM PDT 24
Peak memory 200128 kb
Host smart-e9563748-dea7-4201-9229-adc2790f3513
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822274494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1822274494
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2457731984
Short name T579
Test name
Test status
Simulation time 38968529 ps
CPU time 0.62 seconds
Started Jul 23 06:18:36 PM PDT 24
Finished Jul 23 06:18:38 PM PDT 24
Peak memory 199104 kb
Host smart-adb28998-bec5-4ed2-b55a-f50be87c59c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457731984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2457731984
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.482284069
Short name T528
Test name
Test status
Simulation time 33075036 ps
CPU time 0.69 seconds
Started Jul 23 06:18:50 PM PDT 24
Finished Jul 23 06:18:53 PM PDT 24
Peak memory 199240 kb
Host smart-0a3d37d5-ccb9-4a33-bcbd-5d0ceea78606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482284069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.482284069
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2290702559
Short name T219
Test name
Test status
Simulation time 33200501 ps
CPU time 0.61 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:44 PM PDT 24
Peak memory 198768 kb
Host smart-d592e2d7-194d-43aa-9ae5-1b524bbdfb11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290702559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2290702559
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.530797263
Short name T214
Test name
Test status
Simulation time 1356061223 ps
CPU time 0.94 seconds
Started Jul 23 06:18:44 PM PDT 24
Finished Jul 23 06:18:46 PM PDT 24
Peak memory 198548 kb
Host smart-daa94214-83ad-4cb5-8eca-aafe97f25cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530797263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.530797263
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.612472429
Short name T236
Test name
Test status
Simulation time 37994791 ps
CPU time 0.58 seconds
Started Jul 23 06:18:41 PM PDT 24
Finished Jul 23 06:18:43 PM PDT 24
Peak memory 198568 kb
Host smart-ce0cbf25-4a0f-484e-9eba-92acfee01c34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612472429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.612472429
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2758193145
Short name T537
Test name
Test status
Simulation time 34377923 ps
CPU time 0.59 seconds
Started Jul 23 06:18:45 PM PDT 24
Finished Jul 23 06:18:46 PM PDT 24
Peak memory 198580 kb
Host smart-ca6981db-3587-4087-8dbf-ae7c25613616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758193145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2758193145
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1046267135
Short name T52
Test name
Test status
Simulation time 43571859 ps
CPU time 0.72 seconds
Started Jul 23 06:18:50 PM PDT 24
Finished Jul 23 06:18:52 PM PDT 24
Peak memory 202016 kb
Host smart-28071b5a-a82b-49df-94c1-3f72087190c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046267135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1046267135
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2184371831
Short name T587
Test name
Test status
Simulation time 170454483 ps
CPU time 0.65 seconds
Started Jul 23 06:18:41 PM PDT 24
Finished Jul 23 06:18:43 PM PDT 24
Peak memory 198860 kb
Host smart-5147335f-fbaf-4a02-8427-1f3ed3bdaf78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184371831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2184371831
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.4129489904
Short name T335
Test name
Test status
Simulation time 122541930 ps
CPU time 0.84 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:45 PM PDT 24
Peak memory 210096 kb
Host smart-d8fd5b6e-553b-405d-af2c-2575406745c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129489904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.4129489904
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2961901784
Short name T340
Test name
Test status
Simulation time 204312036 ps
CPU time 0.77 seconds
Started Jul 23 06:18:42 PM PDT 24
Finished Jul 23 06:18:45 PM PDT 24
Peak memory 198684 kb
Host smart-92e191b9-d0fb-410e-979b-05efc8ad8f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961901784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2961901784
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.1008364846
Short name T53
Test name
Test status
Simulation time 37812522 ps
CPU time 0.64 seconds
Started Jul 23 06:18:49 PM PDT 24
Finished Jul 23 06:18:52 PM PDT 24
Peak memory 199072 kb
Host smart-b3bfe75a-8e6e-4ef6-89a7-c3504b31ff9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008364846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1008364846
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.4022046673
Short name T89
Test name
Test status
Simulation time 30702918 ps
CPU time 0.94 seconds
Started Jul 23 06:18:48 PM PDT 24
Finished Jul 23 06:18:50 PM PDT 24
Peak memory 201328 kb
Host smart-9eac8a35-1b01-47d0-a916-cd9ad87789f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022046673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.4022046673
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1036646458
Short name T613
Test name
Test status
Simulation time 63334462 ps
CPU time 0.81 seconds
Started Jul 23 06:18:52 PM PDT 24
Finished Jul 23 06:18:57 PM PDT 24
Peak memory 199652 kb
Host smart-26c513bf-412c-481a-80e7-b7454bcda5cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036646458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.1036646458
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1333352166
Short name T301
Test name
Test status
Simulation time 34133313 ps
CPU time 0.58 seconds
Started Jul 23 06:18:49 PM PDT 24
Finished Jul 23 06:18:52 PM PDT 24
Peak memory 198544 kb
Host smart-2711e833-31b4-497e-b7cb-2e2971f0f77f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333352166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.1333352166
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1055566175
Short name T240
Test name
Test status
Simulation time 159572309 ps
CPU time 0.99 seconds
Started Jul 23 06:18:51 PM PDT 24
Finished Jul 23 06:18:56 PM PDT 24
Peak memory 198668 kb
Host smart-1c980a2d-712b-40aa-854e-64870e12de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055566175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1055566175
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.4080866826
Short name T129
Test name
Test status
Simulation time 46585944 ps
CPU time 0.67 seconds
Started Jul 23 06:18:50 PM PDT 24
Finished Jul 23 06:18:53 PM PDT 24
Peak memory 198624 kb
Host smart-549a10e6-3a58-46da-a8a8-01709ee6a43d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080866826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.4080866826
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2703635967
Short name T357
Test name
Test status
Simulation time 26501657 ps
CPU time 0.62 seconds
Started Jul 23 06:18:48 PM PDT 24
Finished Jul 23 06:18:50 PM PDT 24
Peak memory 198924 kb
Host smart-8bca4a54-cf65-4864-b9b4-5533d2562d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703635967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2703635967
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.1873643045
Short name T464
Test name
Test status
Simulation time 45946547 ps
CPU time 0.76 seconds
Started Jul 23 06:18:52 PM PDT 24
Finished Jul 23 06:18:57 PM PDT 24
Peak memory 202004 kb
Host smart-d3ad036c-dfbd-4192-ba36-f16664ed5ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873643045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.1873643045
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.348069629
Short name T603
Test name
Test status
Simulation time 33649650 ps
CPU time 0.61 seconds
Started Jul 23 06:18:48 PM PDT 24
Finished Jul 23 06:18:50 PM PDT 24
Peak memory 198540 kb
Host smart-a5fd4b5d-1d09-4b6f-8126-c6c095651726
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348069629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.348069629
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2281545103
Short name T237
Test name
Test status
Simulation time 123117913 ps
CPU time 0.84 seconds
Started Jul 23 06:18:53 PM PDT 24
Finished Jul 23 06:18:58 PM PDT 24
Peak memory 210108 kb
Host smart-a42f79ae-d890-4d96-9087-9b3bfc44bac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281545103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2281545103
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.3466440753
Short name T126
Test name
Test status
Simulation time 132557479 ps
CPU time 0.78 seconds
Started Jul 23 06:18:49 PM PDT 24
Finished Jul 23 06:18:51 PM PDT 24
Peak memory 198720 kb
Host smart-09f24ed6-3b3e-429c-a804-ce1d1d6ef3ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466440753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3466440753
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.2873138390
Short name T273
Test name
Test status
Simulation time 91815035 ps
CPU time 0.63 seconds
Started Jul 23 06:18:52 PM PDT 24
Finished Jul 23 06:18:56 PM PDT 24
Peak memory 199084 kb
Host smart-f5ad639f-af64-49bd-8c50-a212c939fb6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873138390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2873138390
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3308411306
Short name T376
Test name
Test status
Simulation time 80070269 ps
CPU time 0.72 seconds
Started Jul 23 06:18:49 PM PDT 24
Finished Jul 23 06:18:52 PM PDT 24
Peak memory 199208 kb
Host smart-8ea9d0e8-983e-49af-8b2b-433abba4e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308411306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3308411306
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3558326449
Short name T620
Test name
Test status
Simulation time 180507759 ps
CPU time 0.75 seconds
Started Jul 23 06:18:56 PM PDT 24
Finished Jul 23 06:19:04 PM PDT 24
Peak memory 199088 kb
Host smart-321a672a-b70a-4dc3-a109-a6f5614fd7b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558326449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.3558326449
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.580522785
Short name T279
Test name
Test status
Simulation time 39885321 ps
CPU time 0.6 seconds
Started Jul 23 06:18:47 PM PDT 24
Finished Jul 23 06:18:49 PM PDT 24
Peak memory 198568 kb
Host smart-adbb23cf-f25c-4420-9785-b8df1b12b4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580522785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.580522785
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3857668490
Short name T519
Test name
Test status
Simulation time 293559834 ps
CPU time 1.03 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 198976 kb
Host smart-d3aaf75d-1c8b-482e-8061-54ebeccdd77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857668490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3857668490
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.3116775765
Short name T619
Test name
Test status
Simulation time 73254669 ps
CPU time 0.62 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 198696 kb
Host smart-e3f3a8d0-f059-4527-a1e4-b6c4aff1b05e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116775765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3116775765
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3695422475
Short name T215
Test name
Test status
Simulation time 32680287 ps
CPU time 0.66 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 198636 kb
Host smart-f92a5e28-8b31-47a6-8a90-51d0068c1d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695422475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3695422475
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3560956581
Short name T173
Test name
Test status
Simulation time 53165349 ps
CPU time 0.69 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 201912 kb
Host smart-3f723d5e-b1ae-45bb-91ab-8ee7dec86e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560956581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3560956581
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1581627829
Short name T611
Test name
Test status
Simulation time 49529160 ps
CPU time 0.74 seconds
Started Jul 23 06:18:49 PM PDT 24
Finished Jul 23 06:18:52 PM PDT 24
Peak memory 198912 kb
Host smart-29dc3570-afc1-4a4c-b0af-5dac93484308
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581627829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1581627829
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2582303628
Short name T628
Test name
Test status
Simulation time 131746131 ps
CPU time 0.81 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:03 PM PDT 24
Peak memory 210060 kb
Host smart-ac2b97f6-adc5-4637-a76d-1112016751db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582303628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2582303628
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4098771594
Short name T535
Test name
Test status
Simulation time 73558380 ps
CPU time 0.91 seconds
Started Jul 23 06:18:50 PM PDT 24
Finished Jul 23 06:18:54 PM PDT 24
Peak memory 199760 kb
Host smart-b4039f99-ff76-4709-88bd-992d3c71d61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098771594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4098771594
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.33677505
Short name T425
Test name
Test status
Simulation time 30289290 ps
CPU time 0.69 seconds
Started Jul 23 06:18:51 PM PDT 24
Finished Jul 23 06:18:55 PM PDT 24
Peak memory 199924 kb
Host smart-7d3fa881-d8fc-496e-a7a8-091baf6d2aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.33677505
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1264958926
Short name T487
Test name
Test status
Simulation time 111963838 ps
CPU time 0.92 seconds
Started Jul 23 06:18:57 PM PDT 24
Finished Jul 23 06:19:05 PM PDT 24
Peak memory 200688 kb
Host smart-a9ab8452-31a9-4538-9b48-c990d25ef6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264958926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1264958926
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3255601260
Short name T483
Test name
Test status
Simulation time 58112238 ps
CPU time 0.76 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:00 PM PDT 24
Peak memory 199732 kb
Host smart-2937f00d-1af4-4d15-b01b-15f156009307
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255601260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3255601260
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.232069963
Short name T282
Test name
Test status
Simulation time 30397548 ps
CPU time 0.69 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 197888 kb
Host smart-fa707398-7c8e-4c1f-93c8-712485108802
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232069963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_
malfunc.232069963
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.1143415870
Short name T404
Test name
Test status
Simulation time 323920125 ps
CPU time 0.97 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:00 PM PDT 24
Peak memory 198912 kb
Host smart-0ad6341a-928a-4c10-a664-ac4d17259f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143415870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1143415870
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.3223142994
Short name T379
Test name
Test status
Simulation time 34302901 ps
CPU time 0.71 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 198584 kb
Host smart-d9befff5-f2e1-41de-b60b-58fd4ccce219
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223142994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3223142994
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2024114087
Short name T627
Test name
Test status
Simulation time 39655244 ps
CPU time 0.7 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:09 PM PDT 24
Peak memory 198644 kb
Host smart-a60d0d4c-15bf-403b-9bed-10883fb30fd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024114087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2024114087
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1679420929
Short name T168
Test name
Test status
Simulation time 46356786 ps
CPU time 0.73 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 201996 kb
Host smart-5d04e1a5-2425-41a6-9053-65832eb4caec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679420929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1679420929
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1139413138
Short name T593
Test name
Test status
Simulation time 44022557 ps
CPU time 0.77 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 199656 kb
Host smart-063affc2-a7cf-43a6-8dd7-6b7cf642b366
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139413138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1139413138
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.1223927419
Short name T50
Test name
Test status
Simulation time 148654817 ps
CPU time 0.72 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 199176 kb
Host smart-5f33005c-661c-474d-86fb-5e68a7465db6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223927419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.1223927419
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1052599835
Short name T571
Test name
Test status
Simulation time 83881342 ps
CPU time 0.87 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 199916 kb
Host smart-67c2072a-6a3b-4c25-b269-34b467fa0cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052599835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1052599835
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.2963903310
Short name T225
Test name
Test status
Simulation time 41039050 ps
CPU time 0.66 seconds
Started Jul 23 06:18:52 PM PDT 24
Finished Jul 23 06:18:57 PM PDT 24
Peak memory 199916 kb
Host smart-f8a252ea-bc3c-4190-9077-234e757ca0a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963903310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2963903310
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3346131441
Short name T102
Test name
Test status
Simulation time 23813468 ps
CPU time 0.67 seconds
Started Jul 23 06:18:54 PM PDT 24
Finished Jul 23 06:19:00 PM PDT 24
Peak memory 199120 kb
Host smart-f9f5eae5-aa66-454b-aed5-03bc2c8ad378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346131441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3346131441
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.708401373
Short name T539
Test name
Test status
Simulation time 100367203 ps
CPU time 0.65 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:09 PM PDT 24
Peak memory 198944 kb
Host smart-4b3ed0b3-970e-4337-9ee7-edb2e6dd8121
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708401373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disa
ble_rom_integrity_check.708401373
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1632749593
Short name T328
Test name
Test status
Simulation time 28519115 ps
CPU time 0.66 seconds
Started Jul 23 06:18:53 PM PDT 24
Finished Jul 23 06:18:59 PM PDT 24
Peak memory 198596 kb
Host smart-3320be04-1ca2-490f-967a-63c796f2d7b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632749593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.1632749593
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1086786403
Short name T430
Test name
Test status
Simulation time 354126655 ps
CPU time 0.98 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 198944 kb
Host smart-a42e0142-1988-4862-a148-0e1b97fb128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086786403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1086786403
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2690106986
Short name T208
Test name
Test status
Simulation time 71029151 ps
CPU time 0.6 seconds
Started Jul 23 06:18:57 PM PDT 24
Finished Jul 23 06:19:05 PM PDT 24
Peak memory 197896 kb
Host smart-63902d6f-29df-4fb6-aba6-4996357bab01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690106986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2690106986
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.3880890300
Short name T38
Test name
Test status
Simulation time 36359658 ps
CPU time 0.65 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 198908 kb
Host smart-395486a7-cf5b-4ff0-ad69-7b9826bb3b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880890300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3880890300
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.167594058
Short name T195
Test name
Test status
Simulation time 47935982 ps
CPU time 0.73 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:07 PM PDT 24
Peak memory 201976 kb
Host smart-99bdc98a-5ecf-43f8-ae22-ff2fe3a8e644
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167594058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invali
d.167594058
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.386407230
Short name T574
Test name
Test status
Simulation time 73825138 ps
CPU time 0.92 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 198960 kb
Host smart-55e4c851-f3c4-417e-9837-4e68162a9ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386407230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.386407230
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3877759813
Short name T626
Test name
Test status
Simulation time 151243195 ps
CPU time 0.84 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 210132 kb
Host smart-77d698e1-7b98-438c-b803-5a031d366541
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877759813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3877759813
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2877683266
Short name T127
Test name
Test status
Simulation time 59991308 ps
CPU time 0.79 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:02 PM PDT 24
Peak memory 198552 kb
Host smart-f9a13cbc-5f0f-436f-b67e-e451380c5181
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877683266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2877683266
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2466994762
Short name T560
Test name
Test status
Simulation time 37994494 ps
CPU time 0.66 seconds
Started Jul 23 06:18:55 PM PDT 24
Finished Jul 23 06:19:01 PM PDT 24
Peak memory 199920 kb
Host smart-efeec6f5-dc07-40a8-a12d-ed83baecb8d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466994762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2466994762
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.3807212189
Short name T97
Test name
Test status
Simulation time 126311666 ps
CPU time 0.76 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:06 PM PDT 24
Peak memory 199376 kb
Host smart-b60b7998-9024-48c0-8af7-a0a1c018140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807212189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3807212189
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.2976020759
Short name T153
Test name
Test status
Simulation time 54056638 ps
CPU time 0.82 seconds
Started Jul 23 06:18:59 PM PDT 24
Finished Jul 23 06:19:08 PM PDT 24
Peak memory 199728 kb
Host smart-5170cc2a-7a2f-451d-8478-bde92fad6011
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976020759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.2976020759
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1354479492
Short name T572
Test name
Test status
Simulation time 41820903 ps
CPU time 0.58 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:07 PM PDT 24
Peak memory 198548 kb
Host smart-93ac9053-e7fb-46d7-9e66-0c592e89af0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354479492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1354479492
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2169814280
Short name T321
Test name
Test status
Simulation time 1882674209 ps
CPU time 1 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 198320 kb
Host smart-de4c9267-2a89-4238-8d9e-36fd726a01b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169814280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2169814280
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2925359450
Short name T235
Test name
Test status
Simulation time 22814264 ps
CPU time 0.64 seconds
Started Jul 23 06:18:59 PM PDT 24
Finished Jul 23 06:19:08 PM PDT 24
Peak memory 198604 kb
Host smart-51f5592d-dcb4-442e-966f-543b6f264916
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925359450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2925359450
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.3934900193
Short name T438
Test name
Test status
Simulation time 47174624 ps
CPU time 0.67 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 198616 kb
Host smart-531f2802-f6bb-4605-84e3-eea922db1cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934900193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3934900193
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1495798737
Short name T181
Test name
Test status
Simulation time 66001117 ps
CPU time 0.68 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:14 PM PDT 24
Peak memory 201964 kb
Host smart-25989bd0-02f0-4555-8b46-1a5fccf27495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495798737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1495798737
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.4049078066
Short name T540
Test name
Test status
Simulation time 66236987 ps
CPU time 0.78 seconds
Started Jul 23 06:18:57 PM PDT 24
Finished Jul 23 06:19:05 PM PDT 24
Peak memory 199712 kb
Host smart-e0aba2e4-c8a8-48d7-853c-ad439fe51891
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049078066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.4049078066
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3599204113
Short name T482
Test name
Test status
Simulation time 119920488 ps
CPU time 0.91 seconds
Started Jul 23 06:19:01 PM PDT 24
Finished Jul 23 06:19:11 PM PDT 24
Peak memory 210136 kb
Host smart-9704c9ea-ae69-4e30-a529-5e931d132042
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599204113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3599204113
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1371418430
Short name T384
Test name
Test status
Simulation time 82183897 ps
CPU time 0.82 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:06 PM PDT 24
Peak memory 199692 kb
Host smart-d86a076d-9ce2-4efa-9b2e-091cda640cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371418430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1371418430
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.1348973523
Short name T373
Test name
Test status
Simulation time 31907162 ps
CPU time 0.64 seconds
Started Jul 23 06:18:53 PM PDT 24
Finished Jul 23 06:18:59 PM PDT 24
Peak memory 199920 kb
Host smart-352c10b1-32aa-4af8-b1e6-bf8f13fde9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348973523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.1348973523
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3404787881
Short name T493
Test name
Test status
Simulation time 117229336 ps
CPU time 0.82 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:14 PM PDT 24
Peak memory 200676 kb
Host smart-ebf8096e-6eaa-437f-99df-f69e98544da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404787881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3404787881
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.4269612737
Short name T39
Test name
Test status
Simulation time 64484114 ps
CPU time 0.71 seconds
Started Jul 23 06:19:01 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 199652 kb
Host smart-fcf6605c-056f-4bd3-9c84-28e0fb879356
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269612737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.4269612737
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3958280424
Short name T336
Test name
Test status
Simulation time 39625237 ps
CPU time 0.59 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:07 PM PDT 24
Peak memory 198540 kb
Host smart-7cdc630f-d8c5-45b7-acee-a4060192d52b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958280424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3958280424
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2806660413
Short name T472
Test name
Test status
Simulation time 160622037 ps
CPU time 1 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:09 PM PDT 24
Peak memory 198932 kb
Host smart-086a8e5a-6b97-4124-8ab5-a019f1841a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806660413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2806660413
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.2526317436
Short name T477
Test name
Test status
Simulation time 48649229 ps
CPU time 0.68 seconds
Started Jul 23 06:19:04 PM PDT 24
Finished Jul 23 06:19:12 PM PDT 24
Peak memory 198548 kb
Host smart-261e65d2-4d70-4dac-96c8-5aac87cfc871
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526317436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2526317436
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.318143984
Short name T220
Test name
Test status
Simulation time 24449828 ps
CPU time 0.62 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 198652 kb
Host smart-b2ddeb47-b5d5-44b7-90a8-37d2abe224dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318143984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.318143984
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1083684872
Short name T170
Test name
Test status
Simulation time 47399413 ps
CPU time 0.76 seconds
Started Jul 23 06:19:04 PM PDT 24
Finished Jul 23 06:19:12 PM PDT 24
Peak memory 201452 kb
Host smart-e246691b-f213-4463-8598-599fc6bf18a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083684872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1083684872
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.990190450
Short name T415
Test name
Test status
Simulation time 101317792 ps
CPU time 0.68 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 199756 kb
Host smart-dade4359-3319-4ae8-9fcc-4e4c403463ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990190450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.990190450
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.997499182
Short name T40
Test name
Test status
Simulation time 223489827 ps
CPU time 0.78 seconds
Started Jul 23 06:19:04 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 210052 kb
Host smart-493d7d43-3897-4e28-a91d-a11ae883aade
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997499182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.997499182
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.2124073982
Short name T250
Test name
Test status
Simulation time 60017168 ps
CPU time 0.89 seconds
Started Jul 23 06:19:03 PM PDT 24
Finished Jul 23 06:19:12 PM PDT 24
Peak memory 198640 kb
Host smart-af2a7fb4-c8cf-4cac-8d05-25da468c75b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124073982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2124073982
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.528111889
Short name T609
Test name
Test status
Simulation time 52631408 ps
CPU time 0.62 seconds
Started Jul 23 06:19:01 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 199952 kb
Host smart-9667c4aa-4a74-4b7b-8023-a433eaf645cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528111889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.528111889
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2536013981
Short name T398
Test name
Test status
Simulation time 47964583 ps
CPU time 0.68 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 199128 kb
Host smart-2bf19f77-a4e0-4e81-8de9-cfaf94d759d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536013981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2536013981
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.555628256
Short name T156
Test name
Test status
Simulation time 66892229 ps
CPU time 0.68 seconds
Started Jul 23 06:19:03 PM PDT 24
Finished Jul 23 06:19:12 PM PDT 24
Peak memory 199596 kb
Host smart-59d5ecc7-4c11-4949-a439-700ba074e2f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555628256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disa
ble_rom_integrity_check.555628256
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3254232453
Short name T466
Test name
Test status
Simulation time 28624532 ps
CPU time 0.64 seconds
Started Jul 23 06:19:04 PM PDT 24
Finished Jul 23 06:19:12 PM PDT 24
Peak memory 198176 kb
Host smart-70d4cc7f-6658-4c24-beb5-88c06d039e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254232453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.3254232453
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.3826807668
Short name T612
Test name
Test status
Simulation time 633141902 ps
CPU time 0.94 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:09 PM PDT 24
Peak memory 198632 kb
Host smart-6e38cf8c-00d5-49b4-8b35-5633300328e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826807668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3826807668
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.279176462
Short name T432
Test name
Test status
Simulation time 23179756 ps
CPU time 0.63 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 198060 kb
Host smart-7c3c5c4f-ff30-4b84-b049-9d2ae1bf53b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279176462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.279176462
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.4045773714
Short name T272
Test name
Test status
Simulation time 33785524 ps
CPU time 0.62 seconds
Started Jul 23 06:18:58 PM PDT 24
Finished Jul 23 06:19:06 PM PDT 24
Peak memory 198640 kb
Host smart-8e88866e-4c94-4256-b62a-288b92f3dae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045773714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.4045773714
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.192323566
Short name T190
Test name
Test status
Simulation time 70906413 ps
CPU time 0.68 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 201980 kb
Host smart-6a510a2b-7002-4a86-89b9-33f1fe3cc504
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192323566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invali
d.192323566
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1364542310
Short name T66
Test name
Test status
Simulation time 81881615 ps
CPU time 0.75 seconds
Started Jul 23 06:19:01 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 199608 kb
Host smart-f1ddc9a9-812c-41dc-bbd8-39b747d72601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364542310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1364542310
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.4249838180
Short name T298
Test name
Test status
Simulation time 154082475 ps
CPU time 0.77 seconds
Started Jul 23 06:19:04 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 210060 kb
Host smart-7e1857f9-436b-4a1c-b354-b0170ed082c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249838180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.4249838180
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3363648797
Short name T202
Test name
Test status
Simulation time 165748358 ps
CPU time 0.62 seconds
Started Jul 23 06:19:02 PM PDT 24
Finished Jul 23 06:19:11 PM PDT 24
Peak memory 199088 kb
Host smart-833f44dd-2b9f-42f9-afa1-d3c61c84b19f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363648797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.3363648797
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1773150376
Short name T256
Test name
Test status
Simulation time 65754728 ps
CPU time 0.76 seconds
Started Jul 23 06:19:00 PM PDT 24
Finished Jul 23 06:19:10 PM PDT 24
Peak memory 198640 kb
Host smart-6c8cd4a7-cae1-4093-81af-9133ca367bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773150376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1773150376
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3993343825
Short name T621
Test name
Test status
Simulation time 37064170 ps
CPU time 0.63 seconds
Started Jul 23 06:19:05 PM PDT 24
Finished Jul 23 06:19:13 PM PDT 24
Peak memory 199088 kb
Host smart-0464f68a-b041-44e4-8aaf-9a0082248c32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993343825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3993343825
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1205954986
Short name T524
Test name
Test status
Simulation time 29149376 ps
CPU time 0.88 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 200776 kb
Host smart-e1d9bc53-f540-44cf-992d-013c479599aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205954986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1205954986
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2125813000
Short name T530
Test name
Test status
Simulation time 62198860 ps
CPU time 0.79 seconds
Started Jul 23 06:19:21 PM PDT 24
Finished Jul 23 06:19:23 PM PDT 24
Peak memory 198988 kb
Host smart-0d7c20a2-d4e7-4c0b-931c-b51dc4050fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125813000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2125813000
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3530956993
Short name T297
Test name
Test status
Simulation time 39908189 ps
CPU time 0.6 seconds
Started Jul 23 06:19:22 PM PDT 24
Finished Jul 23 06:19:23 PM PDT 24
Peak memory 198548 kb
Host smart-c62c80c3-bd72-40b4-87e5-440944ffbc72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530956993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3530956993
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.2649189675
Short name T43
Test name
Test status
Simulation time 160860547 ps
CPU time 0.98 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:27 PM PDT 24
Peak memory 198620 kb
Host smart-daaa4366-a6f0-45d4-8a1b-5b62f5f8fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649189675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.2649189675
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2918288022
Short name T9
Test name
Test status
Simulation time 59710637 ps
CPU time 0.67 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 198668 kb
Host smart-70e6607e-5762-4743-9a21-5e38bb485f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918288022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2918288022
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.999737806
Short name T244
Test name
Test status
Simulation time 69286504 ps
CPU time 0.61 seconds
Started Jul 23 06:19:23 PM PDT 24
Finished Jul 23 06:19:25 PM PDT 24
Peak memory 198940 kb
Host smart-2ed4876d-0b0f-483e-bdf9-6c6b47a61738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999737806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.999737806
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.161335546
Short name T344
Test name
Test status
Simulation time 73802300 ps
CPU time 0.68 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:32 PM PDT 24
Peak memory 201888 kb
Host smart-7ef273a5-9696-4e06-8a80-05969edc16c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161335546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invali
d.161335546
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2514784325
Short name T368
Test name
Test status
Simulation time 58883931 ps
CPU time 0.71 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 198720 kb
Host smart-1a543b1f-b69b-4183-afaa-71e9209ea834
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514784325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2514784325
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2686004069
Short name T306
Test name
Test status
Simulation time 211975159 ps
CPU time 0.81 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 210104 kb
Host smart-2e15cc2e-c881-4090-ae9d-f00e7a16fa01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686004069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2686004069
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.157007170
Short name T318
Test name
Test status
Simulation time 247755631 ps
CPU time 0.84 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 199764 kb
Host smart-a19366e3-ac36-4c79-9765-75cbb60e610b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157007170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.157007170
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1209703369
Short name T258
Test name
Test status
Simulation time 33182676 ps
CPU time 0.66 seconds
Started Jul 23 06:19:22 PM PDT 24
Finished Jul 23 06:19:23 PM PDT 24
Peak memory 199880 kb
Host smart-df8471c1-9d9c-41a9-ba9a-9128819970fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209703369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1209703369
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.301205066
Short name T581
Test name
Test status
Simulation time 89354234 ps
CPU time 0.71 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 199196 kb
Host smart-777e8e79-3784-4aaf-a765-84f45b94f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301205066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.301205066
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3882356129
Short name T198
Test name
Test status
Simulation time 65852856 ps
CPU time 0.67 seconds
Started Jul 23 06:16:43 PM PDT 24
Finished Jul 23 06:16:45 PM PDT 24
Peak memory 198976 kb
Host smart-a90723f1-9179-4f15-9a01-0e97758b6718
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882356129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.3882356129
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2382084179
Short name T429
Test name
Test status
Simulation time 29534639 ps
CPU time 0.65 seconds
Started Jul 23 06:16:41 PM PDT 24
Finished Jul 23 06:16:42 PM PDT 24
Peak memory 198596 kb
Host smart-7d2957f0-2d91-463d-8754-21c47174bb3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382084179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.2382084179
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.3894344958
Short name T378
Test name
Test status
Simulation time 720499355 ps
CPU time 0.97 seconds
Started Jul 23 06:16:41 PM PDT 24
Finished Jul 23 06:16:43 PM PDT 24
Peak memory 198680 kb
Host smart-fb3fe38c-975d-4f78-b944-ca77e58b5429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894344958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3894344958
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3022402533
Short name T614
Test name
Test status
Simulation time 50670000 ps
CPU time 0.68 seconds
Started Jul 23 06:16:42 PM PDT 24
Finished Jul 23 06:16:44 PM PDT 24
Peak memory 198588 kb
Host smart-8c0a2dac-8909-4f00-88a3-7f16b948eb49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022402533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3022402533
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.698563253
Short name T317
Test name
Test status
Simulation time 250628246 ps
CPU time 0.59 seconds
Started Jul 23 06:16:42 PM PDT 24
Finished Jul 23 06:16:44 PM PDT 24
Peak memory 198644 kb
Host smart-57b9fffa-c44c-4bba-8ef0-e3eb71a5701e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698563253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.698563253
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1471347532
Short name T419
Test name
Test status
Simulation time 43296030 ps
CPU time 0.71 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 201940 kb
Host smart-538b42f5-45a7-48d9-91f2-5825e8fa2b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471347532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1471347532
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.987772007
Short name T388
Test name
Test status
Simulation time 75484843 ps
CPU time 0.83 seconds
Started Jul 23 06:16:36 PM PDT 24
Finished Jul 23 06:16:40 PM PDT 24
Peak memory 199624 kb
Host smart-0c459474-94ce-4e17-b3fd-e1884a0c7281
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987772007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.987772007
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1522792967
Short name T586
Test name
Test status
Simulation time 112065501 ps
CPU time 0.96 seconds
Started Jul 23 06:16:44 PM PDT 24
Finished Jul 23 06:16:46 PM PDT 24
Peak memory 210048 kb
Host smart-df174575-fde7-4b2e-aa00-6ea253a839b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522792967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1522792967
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1345620665
Short name T494
Test name
Test status
Simulation time 105946652 ps
CPU time 0.68 seconds
Started Jul 23 06:16:42 PM PDT 24
Finished Jul 23 06:16:44 PM PDT 24
Peak memory 198664 kb
Host smart-b5395380-1079-4014-8117-3ad277d9578c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345620665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1345620665
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.832646086
Short name T566
Test name
Test status
Simulation time 192243667 ps
CPU time 0.65 seconds
Started Jul 23 06:16:39 PM PDT 24
Finished Jul 23 06:16:41 PM PDT 24
Peak memory 198996 kb
Host smart-1a8a6a84-b705-48a0-9db0-e119e281471f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832646086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.832646086
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1341767022
Short name T454
Test name
Test status
Simulation time 40434171 ps
CPU time 0.91 seconds
Started Jul 23 06:16:44 PM PDT 24
Finished Jul 23 06:16:46 PM PDT 24
Peak memory 200804 kb
Host smart-0508fa75-47dd-4908-84a2-f997f7a22bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341767022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1341767022
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2615209413
Short name T342
Test name
Test status
Simulation time 69876814 ps
CPU time 0.66 seconds
Started Jul 23 06:16:47 PM PDT 24
Finished Jul 23 06:16:48 PM PDT 24
Peak memory 198972 kb
Host smart-0179a98b-5070-4e9d-a556-3af8a6b8a5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615209413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2615209413
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.987271294
Short name T11
Test name
Test status
Simulation time 85700898 ps
CPU time 0.56 seconds
Started Jul 23 06:16:52 PM PDT 24
Finished Jul 23 06:16:55 PM PDT 24
Peak memory 198624 kb
Host smart-a4cb38b9-6b51-4d5e-88fc-c5577a61ffe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987271294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_m
alfunc.987271294
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.533287337
Short name T629
Test name
Test status
Simulation time 157766744 ps
CPU time 0.95 seconds
Started Jul 23 06:16:52 PM PDT 24
Finished Jul 23 06:16:54 PM PDT 24
Peak memory 198672 kb
Host smart-67082719-ce21-4adb-9060-49180444642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533287337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.533287337
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.461842694
Short name T348
Test name
Test status
Simulation time 79815391 ps
CPU time 0.61 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 198684 kb
Host smart-350be85c-8f19-42f9-8400-070b076b31ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461842694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.461842694
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2312156208
Short name T251
Test name
Test status
Simulation time 73778692 ps
CPU time 0.59 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 198608 kb
Host smart-1b606da7-2927-45b6-ae94-31d52e8e6e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312156208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2312156208
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.45484271
Short name T167
Test name
Test status
Simulation time 97360808 ps
CPU time 0.66 seconds
Started Jul 23 06:16:51 PM PDT 24
Finished Jul 23 06:16:53 PM PDT 24
Peak memory 201948 kb
Host smart-5f34e5c8-46f5-496f-b0cd-e4505aef23e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45484271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.45484271
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.4013268584
Short name T248
Test name
Test status
Simulation time 49642731 ps
CPU time 0.8 seconds
Started Jul 23 06:16:44 PM PDT 24
Finished Jul 23 06:16:45 PM PDT 24
Peak memory 199064 kb
Host smart-ab61dbff-f5a3-47aa-b1a4-7bd5ad367175
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013268584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.4013268584
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1487495348
Short name T450
Test name
Test status
Simulation time 98125389 ps
CPU time 1.1 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 209976 kb
Host smart-62bbc418-d7b4-416b-bc33-0c55a5f9f984
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487495348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1487495348
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2270729337
Short name T310
Test name
Test status
Simulation time 133629327 ps
CPU time 0.84 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 200020 kb
Host smart-2863d7c5-ffe6-4bdc-93ac-8778b54c11cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270729337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2270729337
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3382713389
Short name T230
Test name
Test status
Simulation time 55308669 ps
CPU time 0.64 seconds
Started Jul 23 06:16:45 PM PDT 24
Finished Jul 23 06:16:47 PM PDT 24
Peak memory 199040 kb
Host smart-ecc0068e-8530-43a3-818a-95f66687a62f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382713389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3382713389
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.3924674963
Short name T103
Test name
Test status
Simulation time 21642961 ps
CPU time 0.74 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 199692 kb
Host smart-a1d281bf-888b-44ed-8e87-af4d19b715aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924674963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3924674963
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.4220850902
Short name T602
Test name
Test status
Simulation time 61846439 ps
CPU time 0.74 seconds
Started Jul 23 06:16:51 PM PDT 24
Finished Jul 23 06:16:53 PM PDT 24
Peak memory 199252 kb
Host smart-3c0d7987-c5f2-4b91-84b2-f2120d2c5469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220850902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.4220850902
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1577177591
Short name T382
Test name
Test status
Simulation time 31359864 ps
CPU time 0.61 seconds
Started Jul 23 06:16:47 PM PDT 24
Finished Jul 23 06:16:49 PM PDT 24
Peak memory 198592 kb
Host smart-30e512dd-b634-4873-a14d-98f3f77dae74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577177591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.1577177591
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.3271114782
Short name T63
Test name
Test status
Simulation time 305358251 ps
CPU time 1.07 seconds
Started Jul 23 06:16:52 PM PDT 24
Finished Jul 23 06:16:55 PM PDT 24
Peak memory 198856 kb
Host smart-de21721f-5eaf-4b6e-9706-c71f8cbc1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271114782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3271114782
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.2095683103
Short name T448
Test name
Test status
Simulation time 85866277 ps
CPU time 0.63 seconds
Started Jul 23 06:16:53 PM PDT 24
Finished Jul 23 06:16:56 PM PDT 24
Peak memory 198692 kb
Host smart-68c0bac2-43b7-4a30-adda-16df3638aa6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095683103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2095683103
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.179629709
Short name T592
Test name
Test status
Simulation time 30053636 ps
CPU time 0.64 seconds
Started Jul 23 06:16:53 PM PDT 24
Finished Jul 23 06:16:55 PM PDT 24
Peak memory 198860 kb
Host smart-2b4ebc2f-6241-4d9e-be41-ffb55d8c7e2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179629709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.179629709
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3392205707
Short name T387
Test name
Test status
Simulation time 51096263 ps
CPU time 0.79 seconds
Started Jul 23 06:16:52 PM PDT 24
Finished Jul 23 06:16:54 PM PDT 24
Peak memory 201928 kb
Host smart-55e65ebc-ac64-4131-acdf-37f1b9a97da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392205707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3392205707
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.3024971323
Short name T41
Test name
Test status
Simulation time 79343117 ps
CPU time 0.79 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 199668 kb
Host smart-e778cde1-b262-4c7a-a8ee-54b26b0b7760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024971323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3024971323
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3743606681
Short name T513
Test name
Test status
Simulation time 131154774 ps
CPU time 0.88 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 210056 kb
Host smart-27a937c4-b763-446a-af39-76b8d3059e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743606681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3743606681
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.4294677797
Short name T588
Test name
Test status
Simulation time 176924774 ps
CPU time 0.86 seconds
Started Jul 23 06:16:47 PM PDT 24
Finished Jul 23 06:16:49 PM PDT 24
Peak memory 199744 kb
Host smart-7b6ae456-68ad-4c91-be95-c04daa9876b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294677797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4294677797
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1581421327
Short name T85
Test name
Test status
Simulation time 29757705 ps
CPU time 0.67 seconds
Started Jul 23 06:16:49 PM PDT 24
Finished Jul 23 06:16:52 PM PDT 24
Peak memory 198980 kb
Host smart-cf2fe150-a4ab-4b1b-9e98-dd0374acf4af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581421327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1581421327
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1890786496
Short name T486
Test name
Test status
Simulation time 61056981 ps
CPU time 0.81 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 199636 kb
Host smart-b8774f1b-625d-4f45-8e6f-c4f5505bd441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890786496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1890786496
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.452310631
Short name T589
Test name
Test status
Simulation time 38460048 ps
CPU time 0.58 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 198596 kb
Host smart-278ad464-81f4-459c-80c7-11bf6311f9a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452310631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m
alfunc.452310631
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3339370567
Short name T223
Test name
Test status
Simulation time 158168354 ps
CPU time 1.05 seconds
Started Jul 23 06:16:56 PM PDT 24
Finished Jul 23 06:16:59 PM PDT 24
Peak memory 198628 kb
Host smart-a621b377-fd1f-424e-a990-b5876bc7c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339370567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3339370567
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.1447934307
Short name T91
Test name
Test status
Simulation time 37437354 ps
CPU time 0.59 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 198592 kb
Host smart-55640e4b-bda7-45d4-8f16-789e57768f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447934307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.1447934307
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.2425201869
Short name T405
Test name
Test status
Simulation time 29084823 ps
CPU time 0.62 seconds
Started Jul 23 06:16:57 PM PDT 24
Finished Jul 23 06:16:59 PM PDT 24
Peak memory 198956 kb
Host smart-588185d5-47a6-4bd7-b7db-f6ecd5eb1e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425201869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2425201869
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3213146611
Short name T604
Test name
Test status
Simulation time 38598902 ps
CPU time 0.75 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 202020 kb
Host smart-7c7a002d-e99f-4e62-a676-ced86d34c54b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213146611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.3213146611
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2396062572
Short name T591
Test name
Test status
Simulation time 52459318 ps
CPU time 0.78 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:51 PM PDT 24
Peak memory 199636 kb
Host smart-42ee5344-5c3d-45ea-966f-e67c888eb751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396062572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2396062572
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.383266819
Short name T455
Test name
Test status
Simulation time 112704433 ps
CPU time 1.17 seconds
Started Jul 23 06:16:57 PM PDT 24
Finished Jul 23 06:17:00 PM PDT 24
Peak memory 210004 kb
Host smart-7112848b-1dab-4bad-a280-9f054a6350b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383266819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.383266819
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4080662285
Short name T324
Test name
Test status
Simulation time 67740358 ps
CPU time 0.85 seconds
Started Jul 23 06:16:53 PM PDT 24
Finished Jul 23 06:16:55 PM PDT 24
Peak memory 199748 kb
Host smart-52c1f74a-a1e9-4720-9d03-b5783e222062
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080662285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4080662285
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1305388471
Short name T546
Test name
Test status
Simulation time 113679061 ps
CPU time 0.63 seconds
Started Jul 23 06:16:48 PM PDT 24
Finished Jul 23 06:16:50 PM PDT 24
Peak memory 199036 kb
Host smart-b2a1d31e-8f2d-4fd6-ae4d-3f90772008a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305388471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1305388471
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.777001760
Short name T441
Test name
Test status
Simulation time 55836161 ps
CPU time 0.75 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 199704 kb
Host smart-15f4723c-8eeb-4af2-b75a-e5a38302d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777001760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.777001760
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3806166076
Short name T383
Test name
Test status
Simulation time 63387432 ps
CPU time 0.73 seconds
Started Jul 23 06:16:56 PM PDT 24
Finished Jul 23 06:16:59 PM PDT 24
Peak memory 199320 kb
Host smart-69b17789-e829-4f0d-b6cd-e438fa2bb6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806166076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3806166076
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1722472998
Short name T94
Test name
Test status
Simulation time 30434809 ps
CPU time 0.68 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 197932 kb
Host smart-ea10b05b-5341-428e-a647-d5040ef313db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722472998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1722472998
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.975287206
Short name T617
Test name
Test status
Simulation time 995734948 ps
CPU time 0.95 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 198584 kb
Host smart-24138142-afd7-46a2-806d-b3e21e06f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975287206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.975287206
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.3608236179
Short name T284
Test name
Test status
Simulation time 49152275 ps
CPU time 0.66 seconds
Started Jul 23 06:16:55 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 198632 kb
Host smart-9e0786bf-c24c-4bdd-8e91-54cdbf206e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608236179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3608236179
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2766660065
Short name T584
Test name
Test status
Simulation time 70556779 ps
CPU time 0.66 seconds
Started Jul 23 06:16:55 PM PDT 24
Finished Jul 23 06:16:58 PM PDT 24
Peak memory 198640 kb
Host smart-946f07d1-7789-42bc-bd38-f5bb5ad6fe5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766660065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2766660065
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.923588750
Short name T507
Test name
Test status
Simulation time 47679599 ps
CPU time 0.79 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 199656 kb
Host smart-d7cb0bac-6201-4288-9fd8-ae7ef8c4152f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923588750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.923588750
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3480376524
Short name T289
Test name
Test status
Simulation time 169031891 ps
CPU time 0.82 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:56 PM PDT 24
Peak memory 210148 kb
Host smart-440cd224-35e5-4d5c-83d3-c27bfd13ada9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480376524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3480376524
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2066979390
Short name T558
Test name
Test status
Simulation time 52688592 ps
CPU time 0.85 seconds
Started Jul 23 06:16:58 PM PDT 24
Finished Jul 23 06:17:00 PM PDT 24
Peak memory 198564 kb
Host smart-c26e716a-d67e-4f9a-b98b-0b3d4b0d3dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066979390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2066979390
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3834012824
Short name T556
Test name
Test status
Simulation time 31332432 ps
CPU time 0.67 seconds
Started Jul 23 06:16:54 PM PDT 24
Finished Jul 23 06:16:57 PM PDT 24
Peak memory 199040 kb
Host smart-00d93bb8-0ce1-4eb2-827e-80b62eb80b6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834012824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3834012824
Directory /workspace/9.pwrmgr_smoke/latest
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