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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.44 98.23 96.15 99.44 96.00 96.18 100.00 96.07


Total test records in report: 737
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T560 /workspace/coverage/default/15.pwrmgr_glitch.2390681592 Jul 25 06:22:19 PM PDT 24 Jul 25 06:22:20 PM PDT 24 87180288 ps
T561 /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3983661782 Jul 25 06:21:30 PM PDT 24 Jul 25 06:21:31 PM PDT 24 52802029 ps
T562 /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1746764667 Jul 25 06:23:05 PM PDT 24 Jul 25 06:23:06 PM PDT 24 51564611 ps
T563 /workspace/coverage/default/19.pwrmgr_reset.1691748055 Jul 25 06:22:43 PM PDT 24 Jul 25 06:22:44 PM PDT 24 35122701 ps
T564 /workspace/coverage/default/31.pwrmgr_global_esc.1390378534 Jul 25 06:23:47 PM PDT 24 Jul 25 06:23:48 PM PDT 24 237104222 ps
T565 /workspace/coverage/default/11.pwrmgr_smoke.1156969003 Jul 25 06:21:59 PM PDT 24 Jul 25 06:22:00 PM PDT 24 60855694 ps
T566 /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.510231199 Jul 25 06:22:25 PM PDT 24 Jul 25 06:22:26 PM PDT 24 29446097 ps
T567 /workspace/coverage/default/45.pwrmgr_escalation_timeout.3282924129 Jul 25 06:24:41 PM PDT 24 Jul 25 06:24:42 PM PDT 24 2131083794 ps
T568 /workspace/coverage/default/31.pwrmgr_reset.3019135118 Jul 25 06:23:49 PM PDT 24 Jul 25 06:23:50 PM PDT 24 44130727 ps
T569 /workspace/coverage/default/33.pwrmgr_glitch.240470148 Jul 25 06:24:00 PM PDT 24 Jul 25 06:24:01 PM PDT 24 39951620 ps
T570 /workspace/coverage/default/16.pwrmgr_global_esc.3134868212 Jul 25 06:22:27 PM PDT 24 Jul 25 06:22:28 PM PDT 24 62551885 ps
T571 /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4188694934 Jul 25 06:24:40 PM PDT 24 Jul 25 06:24:41 PM PDT 24 60107268 ps
T159 /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.751324659 Jul 25 06:24:20 PM PDT 24 Jul 25 06:24:20 PM PDT 24 70011938 ps
T572 /workspace/coverage/default/38.pwrmgr_aborted_low_power.4217223145 Jul 25 06:24:20 PM PDT 24 Jul 25 06:24:21 PM PDT 24 19459017 ps
T573 /workspace/coverage/default/23.pwrmgr_glitch.3413021765 Jul 25 06:23:34 PM PDT 24 Jul 25 06:23:34 PM PDT 24 58782884 ps
T574 /workspace/coverage/default/7.pwrmgr_reset.4069322247 Jul 25 06:21:43 PM PDT 24 Jul 25 06:21:44 PM PDT 24 69634437 ps
T575 /workspace/coverage/default/16.pwrmgr_reset.3038267528 Jul 25 06:22:18 PM PDT 24 Jul 25 06:22:19 PM PDT 24 69336370 ps
T576 /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2417798840 Jul 25 06:24:22 PM PDT 24 Jul 25 06:24:23 PM PDT 24 71562439 ps
T577 /workspace/coverage/default/2.pwrmgr_escalation_timeout.3374703880 Jul 25 06:21:22 PM PDT 24 Jul 25 06:21:23 PM PDT 24 318559126 ps
T578 /workspace/coverage/default/7.pwrmgr_glitch.215691432 Jul 25 06:21:52 PM PDT 24 Jul 25 06:21:53 PM PDT 24 63901366 ps
T579 /workspace/coverage/default/5.pwrmgr_reset_invalid.1116531627 Jul 25 06:21:40 PM PDT 24 Jul 25 06:21:41 PM PDT 24 106252918 ps
T580 /workspace/coverage/default/19.pwrmgr_smoke.3865525159 Jul 25 06:22:43 PM PDT 24 Jul 25 06:22:45 PM PDT 24 34048257 ps
T581 /workspace/coverage/default/33.pwrmgr_smoke.1981388605 Jul 25 06:23:58 PM PDT 24 Jul 25 06:23:59 PM PDT 24 71609406 ps
T582 /workspace/coverage/default/27.pwrmgr_glitch.1488996832 Jul 25 06:23:39 PM PDT 24 Jul 25 06:23:40 PM PDT 24 45478198 ps
T583 /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.849767259 Jul 25 06:23:08 PM PDT 24 Jul 25 06:23:09 PM PDT 24 72006177 ps
T584 /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1531134472 Jul 25 06:24:19 PM PDT 24 Jul 25 06:24:20 PM PDT 24 127748080 ps
T585 /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3817578138 Jul 25 06:21:50 PM PDT 24 Jul 25 06:21:51 PM PDT 24 78882922 ps
T586 /workspace/coverage/default/25.pwrmgr_global_esc.1721462414 Jul 25 06:23:32 PM PDT 24 Jul 25 06:23:33 PM PDT 24 96662885 ps
T587 /workspace/coverage/default/26.pwrmgr_reset_invalid.3220311075 Jul 25 06:23:36 PM PDT 24 Jul 25 06:23:37 PM PDT 24 112983012 ps
T588 /workspace/coverage/default/10.pwrmgr_global_esc.2668523763 Jul 25 06:21:59 PM PDT 24 Jul 25 06:22:00 PM PDT 24 47113410 ps
T589 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1266106981 Jul 25 06:23:06 PM PDT 24 Jul 25 06:23:07 PM PDT 24 99511051 ps
T590 /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3613287547 Jul 25 06:23:35 PM PDT 24 Jul 25 06:23:36 PM PDT 24 29161863 ps
T591 /workspace/coverage/default/45.pwrmgr_reset_invalid.3123203425 Jul 25 06:24:39 PM PDT 24 Jul 25 06:24:41 PM PDT 24 116037945 ps
T592 /workspace/coverage/default/32.pwrmgr_reset_invalid.525359803 Jul 25 06:23:57 PM PDT 24 Jul 25 06:23:58 PM PDT 24 104930073 ps
T593 /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1278206702 Jul 25 06:23:59 PM PDT 24 Jul 25 06:24:00 PM PDT 24 46698054 ps
T594 /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2495147732 Jul 25 06:21:30 PM PDT 24 Jul 25 06:21:31 PM PDT 24 62574246 ps
T595 /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.200760722 Jul 25 06:22:17 PM PDT 24 Jul 25 06:22:17 PM PDT 24 31736235 ps
T596 /workspace/coverage/default/2.pwrmgr_reset_invalid.3456400537 Jul 25 06:21:23 PM PDT 24 Jul 25 06:21:24 PM PDT 24 112081278 ps
T597 /workspace/coverage/default/4.pwrmgr_smoke.2571741842 Jul 25 06:21:31 PM PDT 24 Jul 25 06:21:32 PM PDT 24 39488545 ps
T598 /workspace/coverage/default/49.pwrmgr_reset_invalid.2139641676 Jul 25 06:25:15 PM PDT 24 Jul 25 06:25:16 PM PDT 24 206164110 ps
T599 /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2542963059 Jul 25 06:22:20 PM PDT 24 Jul 25 06:22:21 PM PDT 24 158555669 ps
T600 /workspace/coverage/default/22.pwrmgr_reset_invalid.321018991 Jul 25 06:23:05 PM PDT 24 Jul 25 06:23:06 PM PDT 24 168822445 ps
T601 /workspace/coverage/default/4.pwrmgr_reset_invalid.1773510887 Jul 25 06:21:29 PM PDT 24 Jul 25 06:21:30 PM PDT 24 151604006 ps
T602 /workspace/coverage/default/17.pwrmgr_glitch.3725420748 Jul 25 06:22:25 PM PDT 24 Jul 25 06:22:26 PM PDT 24 50038092 ps
T603 /workspace/coverage/default/12.pwrmgr_glitch.970118871 Jul 25 06:22:13 PM PDT 24 Jul 25 06:22:14 PM PDT 24 33122028 ps
T604 /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3212462296 Jul 25 06:21:13 PM PDT 24 Jul 25 06:21:14 PM PDT 24 29956903 ps
T605 /workspace/coverage/default/44.pwrmgr_global_esc.1329460211 Jul 25 06:24:35 PM PDT 24 Jul 25 06:24:36 PM PDT 24 21654752 ps
T606 /workspace/coverage/default/48.pwrmgr_reset.3593440481 Jul 25 06:24:46 PM PDT 24 Jul 25 06:24:47 PM PDT 24 76195263 ps
T607 /workspace/coverage/default/32.pwrmgr_global_esc.698769445 Jul 25 06:24:07 PM PDT 24 Jul 25 06:24:08 PM PDT 24 221454758 ps
T205 /workspace/coverage/default/18.pwrmgr_wakeup.651577468 Jul 25 06:22:27 PM PDT 24 Jul 25 06:22:29 PM PDT 24 67510602 ps
T608 /workspace/coverage/default/20.pwrmgr_global_esc.920949815 Jul 25 06:22:45 PM PDT 24 Jul 25 06:22:46 PM PDT 24 56548761 ps
T609 /workspace/coverage/default/8.pwrmgr_reset_invalid.1811107471 Jul 25 06:21:52 PM PDT 24 Jul 25 06:21:53 PM PDT 24 102732859 ps
T610 /workspace/coverage/default/21.pwrmgr_glitch.2729673411 Jul 25 06:23:05 PM PDT 24 Jul 25 06:23:06 PM PDT 24 36493720 ps
T611 /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1654768430 Jul 25 06:21:57 PM PDT 24 Jul 25 06:21:58 PM PDT 24 131713424 ps
T612 /workspace/coverage/default/37.pwrmgr_lowpower_invalid.5778557 Jul 25 06:24:21 PM PDT 24 Jul 25 06:24:22 PM PDT 24 68279890 ps
T613 /workspace/coverage/default/15.pwrmgr_reset_invalid.2429413623 Jul 25 06:22:19 PM PDT 24 Jul 25 06:22:20 PM PDT 24 130547327 ps
T614 /workspace/coverage/default/25.pwrmgr_smoke.2070883735 Jul 25 06:23:35 PM PDT 24 Jul 25 06:23:36 PM PDT 24 26781533 ps
T216 /workspace/coverage/default/20.pwrmgr_lowpower_invalid.813296458 Jul 25 06:22:44 PM PDT 24 Jul 25 06:22:45 PM PDT 24 106479923 ps
T615 /workspace/coverage/default/1.pwrmgr_aborted_low_power.2709458390 Jul 25 06:21:13 PM PDT 24 Jul 25 06:21:14 PM PDT 24 46367500 ps
T616 /workspace/coverage/default/6.pwrmgr_escalation_timeout.1789941030 Jul 25 06:21:40 PM PDT 24 Jul 25 06:21:42 PM PDT 24 754732426 ps
T617 /workspace/coverage/default/38.pwrmgr_reset.2679199068 Jul 25 06:24:18 PM PDT 24 Jul 25 06:24:19 PM PDT 24 77316047 ps
T618 /workspace/coverage/default/11.pwrmgr_reset.231633645 Jul 25 06:22:17 PM PDT 24 Jul 25 06:22:18 PM PDT 24 134404853 ps
T619 /workspace/coverage/default/30.pwrmgr_global_esc.1533923644 Jul 25 06:23:45 PM PDT 24 Jul 25 06:23:45 PM PDT 24 40884095 ps
T620 /workspace/coverage/default/37.pwrmgr_aborted_low_power.1581928266 Jul 25 06:24:20 PM PDT 24 Jul 25 06:24:22 PM PDT 24 74104944 ps
T621 /workspace/coverage/default/19.pwrmgr_global_esc.773831245 Jul 25 06:22:42 PM PDT 24 Jul 25 06:22:42 PM PDT 24 62945350 ps
T174 /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.4284071086 Jul 25 06:23:36 PM PDT 24 Jul 25 06:23:37 PM PDT 24 29265624 ps
T622 /workspace/coverage/default/6.pwrmgr_reset_invalid.4050302046 Jul 25 06:21:39 PM PDT 24 Jul 25 06:21:40 PM PDT 24 109464061 ps
T623 /workspace/coverage/default/29.pwrmgr_escalation_timeout.1826913430 Jul 25 06:23:47 PM PDT 24 Jul 25 06:23:48 PM PDT 24 216177093 ps
T624 /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1826141692 Jul 25 06:24:47 PM PDT 24 Jul 25 06:24:47 PM PDT 24 29707153 ps
T625 /workspace/coverage/default/23.pwrmgr_reset_invalid.832290247 Jul 25 06:23:34 PM PDT 24 Jul 25 06:23:35 PM PDT 24 111377855 ps
T626 /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2079424701 Jul 25 06:23:05 PM PDT 24 Jul 25 06:23:06 PM PDT 24 48026707 ps
T627 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2242436453 Jul 25 06:22:11 PM PDT 24 Jul 25 06:22:12 PM PDT 24 37925643 ps
T74 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.401658504 Jul 25 06:19:08 PM PDT 24 Jul 25 06:19:09 PM PDT 24 33994668 ps
T77 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.263697112 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 54371899 ps
T68 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2727630418 Jul 25 06:19:33 PM PDT 24 Jul 25 06:19:34 PM PDT 24 29519953 ps
T69 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3580420407 Jul 25 06:19:10 PM PDT 24 Jul 25 06:19:11 PM PDT 24 154274244 ps
T22 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1402611155 Jul 25 06:19:44 PM PDT 24 Jul 25 06:19:46 PM PDT 24 234467067 ps
T175 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2205187982 Jul 25 06:20:04 PM PDT 24 Jul 25 06:20:05 PM PDT 24 22292784 ps
T23 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2181377320 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:45 PM PDT 24 288905161 ps
T132 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2986034546 Jul 25 06:19:11 PM PDT 24 Jul 25 06:19:11 PM PDT 24 35918087 ps
T133 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3115602023 Jul 25 06:19:18 PM PDT 24 Jul 25 06:19:18 PM PDT 24 25426048 ps
T134 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3562108237 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 59731986 ps
T24 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3956998677 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:32 PM PDT 24 191226532 ps
T63 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1367892256 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:33 PM PDT 24 97233299 ps
T64 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3711481790 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 40348590 ps
T65 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1676966081 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:55 PM PDT 24 40617153 ps
T101 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.431317682 Jul 25 06:20:05 PM PDT 24 Jul 25 06:20:06 PM PDT 24 114498958 ps
T66 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3934642044 Jul 25 06:19:05 PM PDT 24 Jul 25 06:19:07 PM PDT 24 528729621 ps
T135 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.375587777 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:57 PM PDT 24 26357512 ps
T75 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.4086136548 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:16 PM PDT 24 51084660 ps
T628 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3163372208 Jul 25 06:19:11 PM PDT 24 Jul 25 06:19:13 PM PDT 24 322225590 ps
T80 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2457635943 Jul 25 06:19:43 PM PDT 24 Jul 25 06:19:44 PM PDT 24 59690256 ps
T76 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3920448758 Jul 25 06:19:57 PM PDT 24 Jul 25 06:19:58 PM PDT 24 18888202 ps
T73 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1545418976 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 95748496 ps
T171 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2422967191 Jul 25 06:20:04 PM PDT 24 Jul 25 06:20:05 PM PDT 24 27068933 ps
T629 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2314674450 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:11 PM PDT 24 27100040 ps
T120 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1272926526 Jul 25 06:19:03 PM PDT 24 Jul 25 06:19:04 PM PDT 24 62858480 ps
T139 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4229509095 Jul 25 06:19:18 PM PDT 24 Jul 25 06:19:19 PM PDT 24 54647165 ps
T67 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1639344761 Jul 25 06:19:19 PM PDT 24 Jul 25 06:19:21 PM PDT 24 127000752 ps
T121 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.592205788 Jul 25 06:19:07 PM PDT 24 Jul 25 06:19:08 PM PDT 24 21294697 ps
T71 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.128813505 Jul 25 06:20:07 PM PDT 24 Jul 25 06:20:10 PM PDT 24 95974783 ps
T172 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1626966836 Jul 25 06:20:04 PM PDT 24 Jul 25 06:20:05 PM PDT 24 19330269 ps
T72 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1786313405 Jul 25 06:19:57 PM PDT 24 Jul 25 06:19:59 PM PDT 24 624453392 ps
T102 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.858763684 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:11 PM PDT 24 43121399 ps
T173 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3447030053 Jul 25 06:20:15 PM PDT 24 Jul 25 06:20:15 PM PDT 24 161093532 ps
T140 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3009777154 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:32 PM PDT 24 216839458 ps
T122 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1318002289 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 28072238 ps
T630 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2125115746 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 204518159 ps
T123 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3993348297 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:31 PM PDT 24 76478668 ps
T136 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1951120636 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 38767185 ps
T85 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.573492846 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 95124535 ps
T84 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3273608439 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 151858553 ps
T631 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.4113257942 Jul 25 06:19:32 PM PDT 24 Jul 25 06:19:33 PM PDT 24 44244065 ps
T137 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3631554093 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 27834496 ps
T632 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1552382803 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:06 PM PDT 24 15584819 ps
T633 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.4260865763 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 39696328 ps
T634 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.568147682 Jul 25 06:19:10 PM PDT 24 Jul 25 06:19:11 PM PDT 24 32850592 ps
T635 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.905594218 Jul 25 06:20:11 PM PDT 24 Jul 25 06:20:12 PM PDT 24 26997984 ps
T636 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2674744246 Jul 25 06:19:44 PM PDT 24 Jul 25 06:19:45 PM PDT 24 22380524 ps
T81 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3453048322 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:45 PM PDT 24 305693469 ps
T637 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1419244902 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 16431777 ps
T638 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3561398778 Jul 25 06:20:17 PM PDT 24 Jul 25 06:20:18 PM PDT 24 71662391 ps
T639 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1765756878 Jul 25 06:18:57 PM PDT 24 Jul 25 06:18:58 PM PDT 24 32565518 ps
T86 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2082601736 Jul 25 06:18:59 PM PDT 24 Jul 25 06:19:00 PM PDT 24 415273650 ps
T82 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.980994747 Jul 25 06:19:43 PM PDT 24 Jul 25 06:19:44 PM PDT 24 119246560 ps
T640 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4184211962 Jul 25 06:20:09 PM PDT 24 Jul 25 06:20:10 PM PDT 24 59216764 ps
T641 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1428029027 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:16 PM PDT 24 56418193 ps
T642 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3049980958 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 47405554 ps
T643 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4036101590 Jul 25 06:19:02 PM PDT 24 Jul 25 06:19:03 PM PDT 24 59879853 ps
T644 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.992089815 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:55 PM PDT 24 194345310 ps
T645 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3382840514 Jul 25 06:20:05 PM PDT 24 Jul 25 06:20:06 PM PDT 24 47057479 ps
T646 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3237761758 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 38693496 ps
T647 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2951928248 Jul 25 06:19:32 PM PDT 24 Jul 25 06:19:33 PM PDT 24 20305664 ps
T648 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1984082143 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:31 PM PDT 24 81433796 ps
T649 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1436167554 Jul 25 06:20:11 PM PDT 24 Jul 25 06:20:12 PM PDT 24 54488789 ps
T650 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1858966162 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 33388416 ps
T124 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1007097356 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:32 PM PDT 24 45434757 ps
T651 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3966955704 Jul 25 06:19:41 PM PDT 24 Jul 25 06:19:42 PM PDT 24 108919680 ps
T652 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.933217608 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 54082312 ps
T653 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3803031194 Jul 25 06:20:05 PM PDT 24 Jul 25 06:20:05 PM PDT 24 39365106 ps
T125 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.645336781 Jul 25 06:19:44 PM PDT 24 Jul 25 06:19:45 PM PDT 24 28271333 ps
T654 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.220039818 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:30 PM PDT 24 45993778 ps
T655 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2554864822 Jul 25 06:20:04 PM PDT 24 Jul 25 06:20:05 PM PDT 24 25703482 ps
T656 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2938476885 Jul 25 06:19:01 PM PDT 24 Jul 25 06:19:02 PM PDT 24 29199152 ps
T83 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.289636233 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:58 PM PDT 24 503967553 ps
T657 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2118047171 Jul 25 06:18:55 PM PDT 24 Jul 25 06:18:56 PM PDT 24 20589318 ps
T78 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3385843405 Jul 25 06:19:05 PM PDT 24 Jul 25 06:19:06 PM PDT 24 368882698 ps
T658 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.4241708910 Jul 25 06:20:15 PM PDT 24 Jul 25 06:20:16 PM PDT 24 43030944 ps
T659 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1324869356 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:11 PM PDT 24 29148255 ps
T660 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3067270056 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:32 PM PDT 24 27365271 ps
T661 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1487772943 Jul 25 06:19:53 PM PDT 24 Jul 25 06:19:54 PM PDT 24 21180386 ps
T160 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1688014277 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:58 PM PDT 24 2184699691 ps
T662 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2101494814 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:57 PM PDT 24 46534921 ps
T663 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1239186865 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 27269671 ps
T664 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1077261028 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 20741105 ps
T665 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1329591519 Jul 25 06:19:41 PM PDT 24 Jul 25 06:19:43 PM PDT 24 78831488 ps
T666 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1744793945 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:16 PM PDT 24 28318409 ps
T667 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1178325723 Jul 25 06:19:43 PM PDT 24 Jul 25 06:19:44 PM PDT 24 47622728 ps
T668 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.700151422 Jul 25 06:19:57 PM PDT 24 Jul 25 06:19:58 PM PDT 24 40407578 ps
T669 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.157786005 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:11 PM PDT 24 53330144 ps
T670 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4097645257 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:07 PM PDT 24 45139043 ps
T671 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3986879270 Jul 25 06:19:03 PM PDT 24 Jul 25 06:19:04 PM PDT 24 19248310 ps
T672 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.382149233 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:58 PM PDT 24 635072506 ps
T673 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3068412798 Jul 25 06:20:20 PM PDT 24 Jul 25 06:20:21 PM PDT 24 20662365 ps
T674 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2087905110 Jul 25 06:19:03 PM PDT 24 Jul 25 06:19:04 PM PDT 24 75827383 ps
T126 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3907161751 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 51273221 ps
T675 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.934820021 Jul 25 06:19:56 PM PDT 24 Jul 25 06:19:57 PM PDT 24 45264859 ps
T676 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.4033872584 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:43 PM PDT 24 67350558 ps
T127 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1145144393 Jul 25 06:19:03 PM PDT 24 Jul 25 06:19:04 PM PDT 24 42323750 ps
T677 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3771905441 Jul 25 06:19:12 PM PDT 24 Jul 25 06:19:14 PM PDT 24 442316412 ps
T128 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2010810521 Jul 25 06:19:04 PM PDT 24 Jul 25 06:19:06 PM PDT 24 157063489 ps
T678 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3294372869 Jul 25 06:20:03 PM PDT 24 Jul 25 06:20:04 PM PDT 24 33993741 ps
T679 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.758753886 Jul 25 06:20:17 PM PDT 24 Jul 25 06:20:17 PM PDT 24 20413476 ps
T680 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1703281653 Jul 25 06:19:57 PM PDT 24 Jul 25 06:19:58 PM PDT 24 23818791 ps
T681 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2341680328 Jul 25 06:19:21 PM PDT 24 Jul 25 06:19:25 PM PDT 24 612785533 ps
T682 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.172044981 Jul 25 06:19:43 PM PDT 24 Jul 25 06:19:44 PM PDT 24 99079199 ps
T683 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.581546879 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 20775893 ps
T684 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4124435102 Jul 25 06:19:44 PM PDT 24 Jul 25 06:19:44 PM PDT 24 22708219 ps
T685 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3399272294 Jul 25 06:19:40 PM PDT 24 Jul 25 06:19:41 PM PDT 24 19472560 ps
T686 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.436982576 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 96025077 ps
T687 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.459678913 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:31 PM PDT 24 41509249 ps
T688 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1568761460 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:32 PM PDT 24 30501664 ps
T689 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2474888500 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:54 PM PDT 24 46485418 ps
T690 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.256992141 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:07 PM PDT 24 42912801 ps
T691 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2995372846 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:43 PM PDT 24 36630313 ps
T692 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1424169337 Jul 25 06:19:21 PM PDT 24 Jul 25 06:19:22 PM PDT 24 23443631 ps
T693 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2953042099 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 99193121 ps
T129 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2877958409 Jul 25 06:19:06 PM PDT 24 Jul 25 06:19:08 PM PDT 24 45179816 ps
T694 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.255406485 Jul 25 06:19:12 PM PDT 24 Jul 25 06:19:13 PM PDT 24 46725497 ps
T695 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.369408782 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 41247863 ps
T87 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3967392754 Jul 25 06:19:58 PM PDT 24 Jul 25 06:20:00 PM PDT 24 292367794 ps
T696 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2505506897 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 54005863 ps
T697 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2018082056 Jul 25 06:20:15 PM PDT 24 Jul 25 06:20:16 PM PDT 24 100115940 ps
T698 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3444187677 Jul 25 06:19:44 PM PDT 24 Jul 25 06:19:45 PM PDT 24 40577849 ps
T699 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1720678816 Jul 25 06:19:07 PM PDT 24 Jul 25 06:19:09 PM PDT 24 644372940 ps
T700 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.829192891 Jul 25 06:20:15 PM PDT 24 Jul 25 06:20:16 PM PDT 24 48913732 ps
T701 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.3842237048 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 18836787 ps
T702 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2647333254 Jul 25 06:18:59 PM PDT 24 Jul 25 06:18:59 PM PDT 24 42354679 ps
T79 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4280211646 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:57 PM PDT 24 425334180 ps
T130 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.2450572566 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:31 PM PDT 24 20163825 ps
T703 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.934660150 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:11 PM PDT 24 22286876 ps
T704 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1975907803 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:07 PM PDT 24 78658790 ps
T705 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3497844395 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 79468098 ps
T706 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3211745157 Jul 25 06:20:05 PM PDT 24 Jul 25 06:20:06 PM PDT 24 53053488 ps
T707 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2116285368 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 32848160 ps
T708 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3234771892 Jul 25 06:19:20 PM PDT 24 Jul 25 06:19:21 PM PDT 24 57419228 ps
T709 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2114748081 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:07 PM PDT 24 119307889 ps
T710 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.503149725 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 211674371 ps
T711 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1201529334 Jul 25 06:19:57 PM PDT 24 Jul 25 06:20:00 PM PDT 24 199826393 ps
T712 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3593421908 Jul 25 06:19:06 PM PDT 24 Jul 25 06:19:06 PM PDT 24 35216414 ps
T713 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1445307681 Jul 25 06:19:04 PM PDT 24 Jul 25 06:19:06 PM PDT 24 216113235 ps
T714 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.39531065 Jul 25 06:19:02 PM PDT 24 Jul 25 06:19:05 PM PDT 24 539232971 ps
T88 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3326788748 Jul 25 06:19:11 PM PDT 24 Jul 25 06:19:13 PM PDT 24 211177211 ps
T715 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2564427766 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:57 PM PDT 24 407782759 ps
T716 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.594685946 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:56 PM PDT 24 20063929 ps
T717 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.4169550092 Jul 25 06:19:30 PM PDT 24 Jul 25 06:19:32 PM PDT 24 223557059 ps
T718 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1425534639 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:55 PM PDT 24 48351452 ps
T719 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3039194792 Jul 25 06:19:11 PM PDT 24 Jul 25 06:19:11 PM PDT 24 25743823 ps
T720 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1609225854 Jul 25 06:19:19 PM PDT 24 Jul 25 06:19:20 PM PDT 24 98551623 ps
T721 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3186950089 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:43 PM PDT 24 17993643 ps
T722 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4114446997 Jul 25 06:20:04 PM PDT 24 Jul 25 06:20:06 PM PDT 24 115539714 ps
T723 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.262751820 Jul 25 06:20:10 PM PDT 24 Jul 25 06:20:10 PM PDT 24 40389763 ps
T724 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3321174406 Jul 25 06:18:57 PM PDT 24 Jul 25 06:18:59 PM PDT 24 174711023 ps
T725 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1973460441 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:44 PM PDT 24 69747268 ps
T726 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1426122548 Jul 25 06:19:07 PM PDT 24 Jul 25 06:19:08 PM PDT 24 164307104 ps
T727 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2068037891 Jul 25 06:19:55 PM PDT 24 Jul 25 06:19:57 PM PDT 24 139360322 ps
T131 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.647133325 Jul 25 06:19:31 PM PDT 24 Jul 25 06:19:33 PM PDT 24 622396611 ps
T728 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1205896905 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:08 PM PDT 24 473290613 ps
T729 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2951559478 Jul 25 06:19:10 PM PDT 24 Jul 25 06:19:11 PM PDT 24 46712207 ps
T730 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3893913140 Jul 25 06:20:06 PM PDT 24 Jul 25 06:20:07 PM PDT 24 68845383 ps
T731 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.307123325 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:55 PM PDT 24 46686289 ps
T732 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3835504161 Jul 25 06:19:32 PM PDT 24 Jul 25 06:19:32 PM PDT 24 169597639 ps
T733 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1401963717 Jul 25 06:19:57 PM PDT 24 Jul 25 06:19:58 PM PDT 24 188343159 ps
T734 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1571957423 Jul 25 06:19:12 PM PDT 24 Jul 25 06:19:12 PM PDT 24 26721223 ps
T735 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3987429651 Jul 25 06:19:54 PM PDT 24 Jul 25 06:19:55 PM PDT 24 32421443 ps
T736 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1939047124 Jul 25 06:19:42 PM PDT 24 Jul 25 06:19:43 PM PDT 24 62522367 ps
T737 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3203826886 Jul 25 06:20:16 PM PDT 24 Jul 25 06:20:17 PM PDT 24 25685236 ps

Test location /workspace/coverage/default/48.pwrmgr_smoke.1820574910
Short name T3
Test name
Test status
Simulation time 27123055 ps
CPU time 0.67 seconds
Started Jul 25 06:24:56 PM PDT 24
Finished Jul 25 06:24:57 PM PDT 24
Peak memory 198568 kb
Host smart-99696231-73a1-4bd4-a21c-5a6331e27e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820574910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1820574910
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3877140807
Short name T8
Test name
Test status
Simulation time 103713226 ps
CPU time 1.01 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 209580 kb
Host smart-93b7f02b-2773-438a-8ee8-b67561c11f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877140807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3877140807
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.1507784613
Short name T15
Test name
Test status
Simulation time 125910866 ps
CPU time 0.87 seconds
Started Jul 25 06:24:08 PM PDT 24
Finished Jul 25 06:24:09 PM PDT 24
Peak memory 200368 kb
Host smart-1918c52c-403f-4982-a44a-3ba4f8aa57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507784613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.1507784613
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2181377320
Short name T23
Test name
Test status
Simulation time 288905161 ps
CPU time 1.74 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 201144 kb
Host smart-b155cddb-2f43-43a2-8d3e-6e261d102977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181377320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2181377320
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.3289086570
Short name T21
Test name
Test status
Simulation time 653894713 ps
CPU time 2.32 seconds
Started Jul 25 06:21:29 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 218056 kb
Host smart-0412b697-1945-44d3-9975-146f43c9a410
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289086570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3289086570
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3420126131
Short name T51
Test name
Test status
Simulation time 43613489 ps
CPU time 0.73 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:39 PM PDT 24
Peak memory 201412 kb
Host smart-7aa7e38e-6294-4b41-8b7f-b6a4bd27ff4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420126131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3420126131
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3822559653
Short name T29
Test name
Test status
Simulation time 61592393 ps
CPU time 0.7 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 199224 kb
Host smart-76dcf361-0f3a-4186-81d0-fa92aa6a3fc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822559653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3822559653
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2967328532
Short name T55
Test name
Test status
Simulation time 98342871 ps
CPU time 0.72 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 198896 kb
Host smart-90504744-c385-44a5-9a35-7a67917c43db
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967328532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.2967328532
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3934642044
Short name T66
Test name
Test status
Simulation time 528729621 ps
CPU time 2.64 seconds
Started Jul 25 06:19:05 PM PDT 24
Finished Jul 25 06:19:07 PM PDT 24
Peak memory 198072 kb
Host smart-4d872f47-d9b5-44b2-932b-265d69bbaffe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934642044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3934642044
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1099759140
Short name T62
Test name
Test status
Simulation time 94687780 ps
CPU time 0.74 seconds
Started Jul 25 06:24:22 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 198888 kb
Host smart-8e6c7d4a-9e6a-4c64-a472-b37474d2eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099759140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1099759140
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.2423426667
Short name T27
Test name
Test status
Simulation time 72823293 ps
CPU time 0.74 seconds
Started Jul 25 06:21:50 PM PDT 24
Finished Jul 25 06:21:51 PM PDT 24
Peak memory 199336 kb
Host smart-e8f9f05c-2216-42f5-81d8-651b3716ff1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423426667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.2423426667
Directory /workspace/9.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2314266267
Short name T282
Test name
Test status
Simulation time 121800755 ps
CPU time 0.8 seconds
Started Jul 25 06:21:42 PM PDT 24
Finished Jul 25 06:21:43 PM PDT 24
Peak memory 200108 kb
Host smart-9d181ea3-f895-4bfd-ba09-7c79cf784de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314266267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2314266267
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1626966836
Short name T172
Test name
Test status
Simulation time 19330269 ps
CPU time 0.67 seconds
Started Jul 25 06:20:04 PM PDT 24
Finished Jul 25 06:20:05 PM PDT 24
Peak memory 195552 kb
Host smart-af3688e6-a598-4bd5-a00e-657d980b1b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626966836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1626966836
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3827976054
Short name T91
Test name
Test status
Simulation time 41419545 ps
CPU time 0.67 seconds
Started Jul 25 06:21:14 PM PDT 24
Finished Jul 25 06:21:15 PM PDT 24
Peak memory 198568 kb
Host smart-5c4b70e2-648b-4893-a976-7d097bd28e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827976054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3827976054
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3072389986
Short name T142
Test name
Test status
Simulation time 323159815 ps
CPU time 1 seconds
Started Jul 25 06:24:57 PM PDT 24
Finished Jul 25 06:24:58 PM PDT 24
Peak memory 198176 kb
Host smart-d6cd9f58-7b4d-4de2-91f7-73398c7dce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072389986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3072389986
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3993348297
Short name T123
Test name
Test status
Simulation time 76478668 ps
CPU time 0.65 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:31 PM PDT 24
Peak memory 197776 kb
Host smart-2f1535a9-f15b-4461-a646-512d43c6e650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993348297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3993348297
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.575736001
Short name T157
Test name
Test status
Simulation time 116502828 ps
CPU time 0.77 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198584 kb
Host smart-68d856da-285d-4854-bac7-1b05e8a928f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575736001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wak
eup_race.575736001
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2027977576
Short name T176
Test name
Test status
Simulation time 58882950 ps
CPU time 0.83 seconds
Started Jul 25 06:22:13 PM PDT 24
Finished Jul 25 06:22:13 PM PDT 24
Peak memory 199216 kb
Host smart-7b799df0-8b2e-4702-ae15-e5cb7ce217ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027977576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2027977576
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.923813603
Short name T190
Test name
Test status
Simulation time 90302183 ps
CPU time 0.67 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198652 kb
Host smart-920c45a5-3277-492c-b8d6-56a9db1041ba
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923813603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_c
m_ctrl_config_regwen.923813603
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.739527568
Short name T149
Test name
Test status
Simulation time 56107788 ps
CPU time 0.79 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:46 PM PDT 24
Peak memory 198716 kb
Host smart-995bcb1b-0967-4225-a328-dfd2d6cc9cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739527568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.739527568
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.675395707
Short name T97
Test name
Test status
Simulation time 73445104 ps
CPU time 0.98 seconds
Started Jul 25 06:22:13 PM PDT 24
Finished Jul 25 06:22:14 PM PDT 24
Peak memory 199396 kb
Host smart-61d2e4a4-d058-499b-b53a-4850133687c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675395707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.675395707
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.651577468
Short name T205
Test name
Test status
Simulation time 67510602 ps
CPU time 0.9 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:29 PM PDT 24
Peak memory 199720 kb
Host smart-06d8de02-d956-496a-a728-9cbce35ae3cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651577468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.651577468
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2911976143
Short name T188
Test name
Test status
Simulation time 84094050 ps
CPU time 0.68 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 201496 kb
Host smart-1bcffe56-b64b-4cd1-b40f-c7ca1e983c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911976143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2911976143
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2885939050
Short name T31
Test name
Test status
Simulation time 46015798 ps
CPU time 0.73 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 201416 kb
Host smart-386f9c01-a2b6-4a4f-a55a-65fd19c384d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885939050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2885939050
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.980994747
Short name T82
Test name
Test status
Simulation time 119246560 ps
CPU time 1.17 seconds
Started Jul 25 06:19:43 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 197144 kb
Host smart-6486ba91-e88b-41c4-8c9c-67ead69fba19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980994747 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.980994747
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3956998677
Short name T24
Test name
Test status
Simulation time 191226532 ps
CPU time 1.71 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 201132 kb
Host smart-96ccacac-6a87-4642-b136-fff2cfe5fc91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956998677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3956998677
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2114399913
Short name T509
Test name
Test status
Simulation time 73645562 ps
CPU time 0.67 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 198512 kb
Host smart-1a4af75f-46b9-4d5d-8f8b-5f9d831a8c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114399913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2114399913
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.758797511
Short name T113
Test name
Test status
Simulation time 33568070 ps
CPU time 1.06 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 200980 kb
Host smart-a53dcff5-e2a7-4943-9025-32d3a9ea2b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758797511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.758797511
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.885474865
Short name T211
Test name
Test status
Simulation time 45025328 ps
CPU time 0.68 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 199192 kb
Host smart-c13a5b6a-ffeb-4b18-95b0-236003dc488c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885474865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.885474865
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.3894525257
Short name T107
Test name
Test status
Simulation time 81393492 ps
CPU time 0.69 seconds
Started Jul 25 06:22:20 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 201368 kb
Host smart-80f7b8ec-eda2-462a-8b2e-e6ee96e650b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894525257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.3894525257
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.113005613
Short name T200
Test name
Test status
Simulation time 52739435 ps
CPU time 0.68 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 201504 kb
Host smart-89f54b53-c899-491e-b8c5-31c199e4c25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113005613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.113005613
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1750243408
Short name T164
Test name
Test status
Simulation time 61935468 ps
CPU time 0.74 seconds
Started Jul 25 06:24:24 PM PDT 24
Finished Jul 25 06:24:25 PM PDT 24
Peak memory 198460 kb
Host smart-b4b41b23-af0a-4e87-9741-98cff027e82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750243408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.1750243408
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3782064201
Short name T206
Test name
Test status
Simulation time 68513558 ps
CPU time 0.68 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 201220 kb
Host smart-5738be9e-866c-4289-9eb8-5d315ab0abba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782064201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3782064201
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.3737198840
Short name T56
Test name
Test status
Simulation time 76807107 ps
CPU time 0.64 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198480 kb
Host smart-4b38a44e-ee28-40ae-b785-fdc336095961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737198840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.3737198840
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.807743194
Short name T18
Test name
Test status
Simulation time 37960770 ps
CPU time 0.65 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 198080 kb
Host smart-8133ecdc-b7e4-49f8-b337-9046ec6b7f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807743194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.807743194
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.500496276
Short name T187
Test name
Test status
Simulation time 41564530 ps
CPU time 0.71 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 201456 kb
Host smart-8bf53c78-458d-410a-aa1d-e89eb3cb0324
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500496276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.500496276
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2441092798
Short name T294
Test name
Test status
Simulation time 117043048 ps
CPU time 0.8 seconds
Started Jul 25 06:21:02 PM PDT 24
Finished Jul 25 06:21:03 PM PDT 24
Peak memory 199116 kb
Host smart-a2bb6fb5-b238-4def-89d0-9a7b13f3077e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441092798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2441092798
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3832442974
Short name T138
Test name
Test status
Simulation time 94863561 ps
CPU time 0.77 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 199056 kb
Host smart-dfb8d43a-1eaa-422e-a390-fc90f5c45e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832442974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3832442974
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.4279542602
Short name T167
Test name
Test status
Simulation time 69044028 ps
CPU time 0.71 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 198468 kb
Host smart-785a7cbd-6a0b-45a9-a655-6fc9725dfcd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279542602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.4279542602
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.720561148
Short name T195
Test name
Test status
Simulation time 44143637 ps
CPU time 0.73 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 201436 kb
Host smart-74b64750-cea5-42c4-a7de-b66ea7b2c03b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720561148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invali
d.720561148
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.4149984219
Short name T170
Test name
Test status
Simulation time 59755694 ps
CPU time 0.74 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198508 kb
Host smart-9cf246a7-ab9a-4d77-9aeb-8b43cb06d52d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149984219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.4149984219
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.2349302905
Short name T162
Test name
Test status
Simulation time 84020997 ps
CPU time 0.67 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 198392 kb
Host smart-c3ee28f5-5ff8-4a6a-9ea7-1572bc2f5a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349302905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.2349302905
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.565243333
Short name T193
Test name
Test status
Simulation time 43347507 ps
CPU time 0.72 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 201484 kb
Host smart-a5885d1a-cb3a-4047-a239-097333223c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565243333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invali
d.565243333
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.42099332
Short name T208
Test name
Test status
Simulation time 44537648 ps
CPU time 0.73 seconds
Started Jul 25 06:24:36 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 201468 kb
Host smart-e67014b3-81af-4d65-a9af-3168d8ec6bbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid
.42099332
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2432168531
Short name T198
Test name
Test status
Simulation time 52804996 ps
CPU time 0.68 seconds
Started Jul 25 06:25:16 PM PDT 24
Finished Jul 25 06:25:17 PM PDT 24
Peak memory 201464 kb
Host smart-012a589a-083a-49de-a03b-a76096fbb080
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432168531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2432168531
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2113897180
Short name T204
Test name
Test status
Simulation time 71167391 ps
CPU time 0.73 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:48 PM PDT 24
Peak memory 201252 kb
Host smart-b4a842be-c05e-48b0-bd96-af29dc08dbc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113897180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2113897180
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2082601736
Short name T86
Test name
Test status
Simulation time 415273650 ps
CPU time 1.62 seconds
Started Jul 25 06:18:59 PM PDT 24
Finished Jul 25 06:19:00 PM PDT 24
Peak memory 201192 kb
Host smart-1c83ace1-be07-49aa-bec7-a44165238967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082601736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.2082601736
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3453048322
Short name T81
Test name
Test status
Simulation time 305693469 ps
CPU time 2.03 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 196860 kb
Host smart-f6a420c6-d4e2-460e-8cee-073458291215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453048322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3453048322
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2938476885
Short name T656
Test name
Test status
Simulation time 29199152 ps
CPU time 0.8 seconds
Started Jul 25 06:19:01 PM PDT 24
Finished Jul 25 06:19:02 PM PDT 24
Peak memory 198140 kb
Host smart-20355d4d-c5a2-484a-8465-980116846b28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938476885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
938476885
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1720678816
Short name T699
Test name
Test status
Simulation time 644372940 ps
CPU time 2.67 seconds
Started Jul 25 06:19:07 PM PDT 24
Finished Jul 25 06:19:09 PM PDT 24
Peak memory 195772 kb
Host smart-c821a84d-8f81-44cd-af1e-052e97a2d7a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720678816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1
720678816
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2647333254
Short name T702
Test name
Test status
Simulation time 42354679 ps
CPU time 0.65 seconds
Started Jul 25 06:18:59 PM PDT 24
Finished Jul 25 06:18:59 PM PDT 24
Peak memory 198124 kb
Host smart-04a07e9a-de7e-4b96-9d6a-e0425d9f3815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647333254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
647333254
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2087905110
Short name T674
Test name
Test status
Simulation time 75827383 ps
CPU time 0.77 seconds
Started Jul 25 06:19:03 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 195824 kb
Host smart-9499ba30-bf52-49fd-ac59-2143aecff086
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087905110 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2087905110
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1765756878
Short name T639
Test name
Test status
Simulation time 32565518 ps
CPU time 0.66 seconds
Started Jul 25 06:18:57 PM PDT 24
Finished Jul 25 06:18:58 PM PDT 24
Peak memory 195624 kb
Host smart-898e2824-f87a-433e-ac0a-a66f84483644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765756878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1765756878
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2118047171
Short name T657
Test name
Test status
Simulation time 20589318 ps
CPU time 0.63 seconds
Started Jul 25 06:18:55 PM PDT 24
Finished Jul 25 06:18:56 PM PDT 24
Peak memory 195612 kb
Host smart-7f7926a7-4f41-4c6a-923e-24c88a2f3374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118047171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2118047171
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1426122548
Short name T726
Test name
Test status
Simulation time 164307104 ps
CPU time 0.97 seconds
Started Jul 25 06:19:07 PM PDT 24
Finished Jul 25 06:19:08 PM PDT 24
Peak memory 199208 kb
Host smart-8deaadf7-54c2-470e-b78f-ca292583d58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426122548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1426122548
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3321174406
Short name T724
Test name
Test status
Simulation time 174711023 ps
CPU time 1.29 seconds
Started Jul 25 06:18:57 PM PDT 24
Finished Jul 25 06:18:59 PM PDT 24
Peak memory 196896 kb
Host smart-53970d4f-a805-4308-95e8-d734b692f463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321174406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3321174406
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2877958409
Short name T129
Test name
Test status
Simulation time 45179816 ps
CPU time 1.02 seconds
Started Jul 25 06:19:06 PM PDT 24
Finished Jul 25 06:19:08 PM PDT 24
Peak memory 199156 kb
Host smart-8517d883-8ad9-46e3-8611-3049069eba95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877958409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.2
877958409
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2010810521
Short name T128
Test name
Test status
Simulation time 157063489 ps
CPU time 1.73 seconds
Started Jul 25 06:19:04 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 195716 kb
Host smart-a2bb3bd4-3bec-478f-91e8-c1cd789023b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010810521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
010810521
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1145144393
Short name T127
Test name
Test status
Simulation time 42323750 ps
CPU time 0.7 seconds
Started Jul 25 06:19:03 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 195624 kb
Host smart-7a68a922-06db-4210-a08b-f2f56b69a461
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145144393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1
145144393
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4036101590
Short name T643
Test name
Test status
Simulation time 59879853 ps
CPU time 1.06 seconds
Started Jul 25 06:19:02 PM PDT 24
Finished Jul 25 06:19:03 PM PDT 24
Peak memory 201048 kb
Host smart-c28372b3-e112-44ca-a0a3-9ea6bac1b7d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036101590 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.4036101590
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1272926526
Short name T120
Test name
Test status
Simulation time 62858480 ps
CPU time 0.64 seconds
Started Jul 25 06:19:03 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 195644 kb
Host smart-ccc24a8e-6ba9-48ad-a351-596e488b4aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272926526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1272926526
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3986879270
Short name T671
Test name
Test status
Simulation time 19248310 ps
CPU time 0.68 seconds
Started Jul 25 06:19:03 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 195572 kb
Host smart-212e0dbc-dac0-4034-8c9b-e8795fa42eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986879270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3986879270
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3593421908
Short name T712
Test name
Test status
Simulation time 35216414 ps
CPU time 0.74 seconds
Started Jul 25 06:19:06 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 197868 kb
Host smart-3a65e04a-aeef-40cc-a0fd-f7e64065a755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593421908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3593421908
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3385843405
Short name T78
Test name
Test status
Simulation time 368882698 ps
CPU time 1.5 seconds
Started Jul 25 06:19:05 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 201212 kb
Host smart-92151ef3-8589-4575-a7fe-30289573d220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385843405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3385843405
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2505506897
Short name T696
Test name
Test status
Simulation time 54005863 ps
CPU time 0.96 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195744 kb
Host smart-16b5db8d-8fff-46ea-9f50-36540f6356c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505506897 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2505506897
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3399272294
Short name T685
Test name
Test status
Simulation time 19472560 ps
CPU time 0.65 seconds
Started Jul 25 06:19:40 PM PDT 24
Finished Jul 25 06:19:41 PM PDT 24
Peak memory 197816 kb
Host smart-3223d7ce-01c8-481c-afbf-b2ede0d0015a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399272294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3399272294
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2674744246
Short name T636
Test name
Test status
Simulation time 22380524 ps
CPU time 0.65 seconds
Started Jul 25 06:19:44 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 195568 kb
Host smart-6c037d2e-e1a1-4e02-a1d4-af35cef5ff1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674744246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2674744246
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.503149725
Short name T710
Test name
Test status
Simulation time 211674371 ps
CPU time 0.75 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195632 kb
Host smart-31ae6e12-7918-4d29-993b-9161f5685580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503149725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sa
me_csr_outstanding.503149725
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1676966081
Short name T65
Test name
Test status
Simulation time 40617153 ps
CPU time 0.76 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:55 PM PDT 24
Peak memory 195760 kb
Host smart-0dee1c7a-4f41-4b63-b819-a4dce406343f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676966081 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1676966081
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3237761758
Short name T646
Test name
Test status
Simulation time 38693496 ps
CPU time 0.66 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 195716 kb
Host smart-8970d8cb-85a6-4dc6-9eda-67ccdc8f9e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237761758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3237761758
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3987429651
Short name T735
Test name
Test status
Simulation time 32421443 ps
CPU time 0.63 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:55 PM PDT 24
Peak memory 195556 kb
Host smart-eb5e5cfc-46ff-4d4a-ae6b-7aa288499a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987429651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3987429651
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3631554093
Short name T137
Test name
Test status
Simulation time 27834496 ps
CPU time 0.75 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 197908 kb
Host smart-fad2d8b9-8513-4333-be4b-0d32de55c42d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631554093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3631554093
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1939047124
Short name T736
Test name
Test status
Simulation time 62522367 ps
CPU time 1.21 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:43 PM PDT 24
Peak memory 196068 kb
Host smart-e190a2b3-cce1-4d45-be15-b061ab024795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939047124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1939047124
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1401963717
Short name T733
Test name
Test status
Simulation time 188343159 ps
CPU time 1.17 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 201024 kb
Host smart-b288c550-9a72-42e5-b44b-bf0fe75d07ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401963717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1401963717
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.700151422
Short name T668
Test name
Test status
Simulation time 40407578 ps
CPU time 0.84 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 195856 kb
Host smart-5393955c-e516-458a-aadd-3d808adda0ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700151422 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.700151422
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1318002289
Short name T122
Test name
Test status
Simulation time 28072238 ps
CPU time 0.63 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 198880 kb
Host smart-7b853c87-d1ba-41c6-9441-848da828bdb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318002289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1318002289
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2474888500
Short name T689
Test name
Test status
Simulation time 46485418 ps
CPU time 0.6 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:54 PM PDT 24
Peak memory 195560 kb
Host smart-0ba30076-3a9f-4e17-8faf-e004e4cf34cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474888500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2474888500
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2101494814
Short name T662
Test name
Test status
Simulation time 46534921 ps
CPU time 0.9 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195636 kb
Host smart-28fc1eb5-6b97-4c26-9f91-c605c91d8995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101494814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2101494814
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3497844395
Short name T705
Test name
Test status
Simulation time 79468098 ps
CPU time 1.32 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 196940 kb
Host smart-0b8bed14-febb-4fb1-9fae-4aa9dd86d5a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497844395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3497844395
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4280211646
Short name T79
Test name
Test status
Simulation time 425334180 ps
CPU time 1.49 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 201192 kb
Host smart-bcdbece2-0089-49df-98df-216f5b353e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280211646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.4280211646
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3273608439
Short name T84
Test name
Test status
Simulation time 151858553 ps
CPU time 0.95 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195768 kb
Host smart-85513591-d1db-4883-9c4b-c74d3bbf3a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273608439 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3273608439
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3907161751
Short name T126
Test name
Test status
Simulation time 51273221 ps
CPU time 0.63 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195656 kb
Host smart-c7b80de2-b494-476f-9a42-bcd7ff88646d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907161751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3907161751
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.3842237048
Short name T701
Test name
Test status
Simulation time 18836787 ps
CPU time 0.65 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 195596 kb
Host smart-c4ce5bc1-e043-4d64-bfc7-6a6a2caddf8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842237048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.3842237048
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.369408782
Short name T695
Test name
Test status
Simulation time 41247863 ps
CPU time 0.89 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 195636 kb
Host smart-3d22fb7d-ff1e-4070-b7cc-72137ea072d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369408782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sa
me_csr_outstanding.369408782
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.289636233
Short name T83
Test name
Test status
Simulation time 503967553 ps
CPU time 1.68 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 196916 kb
Host smart-af6096e7-7c42-48fb-9ad7-9808919217ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289636233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.289636233
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.382149233
Short name T672
Test name
Test status
Simulation time 635072506 ps
CPU time 1.58 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 195912 kb
Host smart-319eebc2-6c69-4e97-8682-714d06693699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382149233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err
.382149233
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2068037891
Short name T727
Test name
Test status
Simulation time 139360322 ps
CPU time 0.98 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 196712 kb
Host smart-c173a975-6cae-46fd-b734-118d26c94607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068037891 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.2068037891
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.307123325
Short name T731
Test name
Test status
Simulation time 46686289 ps
CPU time 0.61 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:55 PM PDT 24
Peak memory 197808 kb
Host smart-5ce86d6a-d520-4a2b-a832-3fe9eb8b5fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307123325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.307123325
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1858966162
Short name T650
Test name
Test status
Simulation time 33388416 ps
CPU time 0.58 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195568 kb
Host smart-4cc83e66-87e3-40fd-8b5f-0d562e4d609c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858966162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1858966162
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1951120636
Short name T136
Test name
Test status
Simulation time 38767185 ps
CPU time 0.87 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 199072 kb
Host smart-2d1f6f8e-7334-4cfe-bbbc-f7ccc813fa25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951120636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1951120636
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1201529334
Short name T711
Test name
Test status
Simulation time 199826393 ps
CPU time 2.28 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:20:00 PM PDT 24
Peak memory 197948 kb
Host smart-a57ca333-4953-46e8-b48f-e7eaaf8da233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201529334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1201529334
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.992089815
Short name T644
Test name
Test status
Simulation time 194345310 ps
CPU time 1 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:55 PM PDT 24
Peak memory 200772 kb
Host smart-23054d03-e4e3-4f8f-be57-57ec1e0da338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992089815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.992089815
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3711481790
Short name T64
Test name
Test status
Simulation time 40348590 ps
CPU time 0.83 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195792 kb
Host smart-119abe41-f944-4ef2-aeab-84c4fcf834c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711481790 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3711481790
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1487772943
Short name T661
Test name
Test status
Simulation time 21180386 ps
CPU time 0.69 seconds
Started Jul 25 06:19:53 PM PDT 24
Finished Jul 25 06:19:54 PM PDT 24
Peak memory 195700 kb
Host smart-afdb2fd9-47b5-4fd8-864a-8a5f6585f7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487772943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1487772943
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.594685946
Short name T716
Test name
Test status
Simulation time 20063929 ps
CPU time 0.61 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 195608 kb
Host smart-dd98cd27-849c-4df5-926a-a8e62cb431bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594685946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.594685946
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.263697112
Short name T77
Test name
Test status
Simulation time 54371899 ps
CPU time 0.72 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 197860 kb
Host smart-1741b53c-c67c-4721-a16d-8d9bbf8e32a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263697112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.263697112
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2564427766
Short name T715
Test name
Test status
Simulation time 407782759 ps
CPU time 1.65 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 197972 kb
Host smart-45432c33-e857-49ed-be50-b30c1b6e0cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564427766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.2564427766
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1786313405
Short name T72
Test name
Test status
Simulation time 624453392 ps
CPU time 1.65 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:19:59 PM PDT 24
Peak memory 195904 kb
Host smart-f5282786-7c51-477d-8ac5-736bf37db9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786313405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1786313405
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.933217608
Short name T652
Test name
Test status
Simulation time 54082312 ps
CPU time 1.01 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 201060 kb
Host smart-336771ab-dfa0-4d4e-98cb-02b755398b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933217608 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.933217608
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.581546879
Short name T683
Test name
Test status
Simulation time 20775893 ps
CPU time 0.7 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:56 PM PDT 24
Peak memory 198244 kb
Host smart-97a2dfd9-ff02-4c4c-8c31-b159915ec5fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581546879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.581546879
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1703281653
Short name T680
Test name
Test status
Simulation time 23818791 ps
CPU time 0.61 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 195588 kb
Host smart-58dbf1b7-3069-4e12-9232-2e8fa4174844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703281653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1703281653
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.375587777
Short name T135
Test name
Test status
Simulation time 26357512 ps
CPU time 0.72 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 195568 kb
Host smart-9f90a7c0-e7ae-44fb-ab14-3ecf101b28ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375587777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.375587777
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1425534639
Short name T718
Test name
Test status
Simulation time 48351452 ps
CPU time 1.21 seconds
Started Jul 25 06:19:54 PM PDT 24
Finished Jul 25 06:19:55 PM PDT 24
Peak memory 201076 kb
Host smart-33379da9-a3c9-4961-8d9b-93e0d063ae6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425534639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1425534639
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1688014277
Short name T160
Test name
Test status
Simulation time 2184699691 ps
CPU time 2.13 seconds
Started Jul 25 06:19:55 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 201260 kb
Host smart-c9e77160-fa94-43a5-b2c8-def374f49a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688014277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.1688014277
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.157786005
Short name T669
Test name
Test status
Simulation time 53330144 ps
CPU time 0.89 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:11 PM PDT 24
Peak memory 195696 kb
Host smart-bd830ba4-a316-4da2-9012-a12fea7e7c0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157786005 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.157786005
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1077261028
Short name T664
Test name
Test status
Simulation time 20741105 ps
CPU time 0.66 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 197760 kb
Host smart-1a4f210a-586e-4102-8bb5-68261fe9a31b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077261028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1077261028
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3920448758
Short name T76
Test name
Test status
Simulation time 18888202 ps
CPU time 0.61 seconds
Started Jul 25 06:19:57 PM PDT 24
Finished Jul 25 06:19:58 PM PDT 24
Peak memory 195596 kb
Host smart-ba459075-bd95-4257-9b57-bf5148a534a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920448758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3920448758
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4184211962
Short name T640
Test name
Test status
Simulation time 59216764 ps
CPU time 0.79 seconds
Started Jul 25 06:20:09 PM PDT 24
Finished Jul 25 06:20:10 PM PDT 24
Peak memory 195700 kb
Host smart-31d924e5-bb9f-4b31-aa00-8bdcf58a0bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184211962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.4184211962
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.934820021
Short name T675
Test name
Test status
Simulation time 45264859 ps
CPU time 1.25 seconds
Started Jul 25 06:19:56 PM PDT 24
Finished Jul 25 06:19:57 PM PDT 24
Peak memory 197672 kb
Host smart-6fdd2c91-6704-419b-9919-5dc03848ea3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934820021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.934820021
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3967392754
Short name T87
Test name
Test status
Simulation time 292367794 ps
CPU time 1.64 seconds
Started Jul 25 06:19:58 PM PDT 24
Finished Jul 25 06:20:00 PM PDT 24
Peak memory 201212 kb
Host smart-e98639f4-9e65-4cb7-8529-7271ace130d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967392754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3967392754
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2114748081
Short name T709
Test name
Test status
Simulation time 119307889 ps
CPU time 0.83 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 195772 kb
Host smart-73a044de-fb4c-410c-8bdc-f950a814ac71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114748081 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2114748081
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.934660150
Short name T703
Test name
Test status
Simulation time 22286876 ps
CPU time 0.62 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:11 PM PDT 24
Peak memory 195640 kb
Host smart-1f83aa37-84dc-4534-a65f-76c9e2c12b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934660150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.934660150
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4097645257
Short name T670
Test name
Test status
Simulation time 45139043 ps
CPU time 0.61 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 195568 kb
Host smart-914fe843-e0e4-4f86-bbfc-796a2f9b2183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097645257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.4097645257
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3893913140
Short name T730
Test name
Test status
Simulation time 68845383 ps
CPU time 0.87 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 199472 kb
Host smart-7142a0a8-b41e-4519-9626-53021c93a0a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893913140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.3893913140
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.128813505
Short name T71
Test name
Test status
Simulation time 95974783 ps
CPU time 2.64 seconds
Started Jul 25 06:20:07 PM PDT 24
Finished Jul 25 06:20:10 PM PDT 24
Peak memory 197104 kb
Host smart-50ba0917-c32f-4b62-9a55-6413551f32c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128813505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.128813505
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.431317682
Short name T101
Test name
Test status
Simulation time 114498958 ps
CPU time 1.15 seconds
Started Jul 25 06:20:05 PM PDT 24
Finished Jul 25 06:20:06 PM PDT 24
Peak memory 195916 kb
Host smart-0c774bde-3f8c-4cd6-8fdb-ed5f6094a854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431317682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.431317682
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.858763684
Short name T102
Test name
Test status
Simulation time 43121399 ps
CPU time 0.84 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:11 PM PDT 24
Peak memory 195772 kb
Host smart-73a4ad5d-b266-4480-a8f5-8110fd48a09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858763684 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.858763684
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2205187982
Short name T175
Test name
Test status
Simulation time 22292784 ps
CPU time 0.64 seconds
Started Jul 25 06:20:04 PM PDT 24
Finished Jul 25 06:20:05 PM PDT 24
Peak memory 195712 kb
Host smart-2ad42b4c-37e1-4f16-a53f-8f51284c6800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205187982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2205187982
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1436167554
Short name T649
Test name
Test status
Simulation time 54488789 ps
CPU time 0.62 seconds
Started Jul 25 06:20:11 PM PDT 24
Finished Jul 25 06:20:12 PM PDT 24
Peak memory 195488 kb
Host smart-901a1407-68be-4686-a98d-acf69bc4a7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436167554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1436167554
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.905594218
Short name T635
Test name
Test status
Simulation time 26997984 ps
CPU time 0.86 seconds
Started Jul 25 06:20:11 PM PDT 24
Finished Jul 25 06:20:12 PM PDT 24
Peak memory 195600 kb
Host smart-774bbced-bb32-4ab6-9e03-a568cd82ac3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905594218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sa
me_csr_outstanding.905594218
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1205896905
Short name T728
Test name
Test status
Simulation time 473290613 ps
CPU time 1.68 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:08 PM PDT 24
Peak memory 196972 kb
Host smart-c540c176-dd7a-42b3-b031-4ae526f6791f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205896905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1205896905
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4114446997
Short name T722
Test name
Test status
Simulation time 115539714 ps
CPU time 1.22 seconds
Started Jul 25 06:20:04 PM PDT 24
Finished Jul 25 06:20:06 PM PDT 24
Peak memory 195912 kb
Host smart-a83574ea-d868-425c-8a82-6a0349d45eed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114446997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.4114446997
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3580420407
Short name T69
Test name
Test status
Simulation time 154274244 ps
CPU time 0.99 seconds
Started Jul 25 06:19:10 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 199228 kb
Host smart-a022e82e-9a3c-4059-baf9-95a01e429c6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580420407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
580420407
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3163372208
Short name T628
Test name
Test status
Simulation time 322225590 ps
CPU time 1.98 seconds
Started Jul 25 06:19:11 PM PDT 24
Finished Jul 25 06:19:13 PM PDT 24
Peak memory 199440 kb
Host smart-6230e46b-221a-431d-b123-d7d96381883a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163372208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
163372208
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.568147682
Short name T634
Test name
Test status
Simulation time 32850592 ps
CPU time 0.75 seconds
Started Jul 25 06:19:10 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 198108 kb
Host smart-bd4121f8-2604-4a4a-be8f-53a9d9985f1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568147682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.568147682
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.255406485
Short name T694
Test name
Test status
Simulation time 46725497 ps
CPU time 1.08 seconds
Started Jul 25 06:19:12 PM PDT 24
Finished Jul 25 06:19:13 PM PDT 24
Peak memory 196744 kb
Host smart-0faa730c-3b81-45a1-a816-b6cd9f2ae736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255406485 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.255406485
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.592205788
Short name T121
Test name
Test status
Simulation time 21294697 ps
CPU time 0.68 seconds
Started Jul 25 06:19:07 PM PDT 24
Finished Jul 25 06:19:08 PM PDT 24
Peak memory 197796 kb
Host smart-70b97405-5a6d-48ba-92bc-909a9d81648b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592205788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.592205788
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2951559478
Short name T729
Test name
Test status
Simulation time 46712207 ps
CPU time 0.62 seconds
Started Jul 25 06:19:10 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 195600 kb
Host smart-063cbab0-d601-4fb4-87fb-03da9edfcb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951559478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2951559478
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1571957423
Short name T734
Test name
Test status
Simulation time 26721223 ps
CPU time 0.74 seconds
Started Jul 25 06:19:12 PM PDT 24
Finished Jul 25 06:19:12 PM PDT 24
Peak memory 197900 kb
Host smart-26e56f89-5886-4b44-8f16-fa3d01af12a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571957423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.1571957423
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.39531065
Short name T714
Test name
Test status
Simulation time 539232971 ps
CPU time 2.58 seconds
Started Jul 25 06:19:02 PM PDT 24
Finished Jul 25 06:19:05 PM PDT 24
Peak memory 197912 kb
Host smart-e0142b3a-961d-4586-813e-761c209a9ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.39531065
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1445307681
Short name T713
Test name
Test status
Simulation time 216113235 ps
CPU time 1.5 seconds
Started Jul 25 06:19:04 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 201132 kb
Host smart-1432ea75-6c8a-4fa6-86f9-0eed03c541e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445307681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1445307681
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1324869356
Short name T659
Test name
Test status
Simulation time 29148255 ps
CPU time 0.62 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:11 PM PDT 24
Peak memory 195572 kb
Host smart-dbe8db94-4366-4f06-81ca-c8b63e7c249c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324869356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1324869356
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2314674450
Short name T629
Test name
Test status
Simulation time 27100040 ps
CPU time 0.61 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:11 PM PDT 24
Peak memory 195576 kb
Host smart-d9104fb7-e31a-4dd5-9495-047aef63579b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314674450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2314674450
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2554864822
Short name T655
Test name
Test status
Simulation time 25703482 ps
CPU time 0.61 seconds
Started Jul 25 06:20:04 PM PDT 24
Finished Jul 25 06:20:05 PM PDT 24
Peak memory 195608 kb
Host smart-f5d60a40-5aa2-4e2d-8495-addbbca07075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554864822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2554864822
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2422967191
Short name T171
Test name
Test status
Simulation time 27068933 ps
CPU time 0.61 seconds
Started Jul 25 06:20:04 PM PDT 24
Finished Jul 25 06:20:05 PM PDT 24
Peak memory 195564 kb
Host smart-6768d24b-fb6f-47a3-b712-b23a2c6b8c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422967191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2422967191
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1552382803
Short name T632
Test name
Test status
Simulation time 15584819 ps
CPU time 0.6 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:06 PM PDT 24
Peak memory 195612 kb
Host smart-fdb9dcb9-bd3a-48aa-bd53-6c567ef9460d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552382803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1552382803
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3382840514
Short name T645
Test name
Test status
Simulation time 47057479 ps
CPU time 0.6 seconds
Started Jul 25 06:20:05 PM PDT 24
Finished Jul 25 06:20:06 PM PDT 24
Peak memory 195596 kb
Host smart-fedfe734-c46f-4aa8-ae4a-67661db7d15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382840514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3382840514
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3803031194
Short name T653
Test name
Test status
Simulation time 39365106 ps
CPU time 0.61 seconds
Started Jul 25 06:20:05 PM PDT 24
Finished Jul 25 06:20:05 PM PDT 24
Peak memory 195592 kb
Host smart-a1cdcf52-c68f-4b60-b0c0-33a9556ed417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803031194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3803031194
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3211745157
Short name T706
Test name
Test status
Simulation time 53053488 ps
CPU time 0.63 seconds
Started Jul 25 06:20:05 PM PDT 24
Finished Jul 25 06:20:06 PM PDT 24
Peak memory 195584 kb
Host smart-50dff082-436d-4ef0-813f-9db0883cda00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211745157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3211745157
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.256992141
Short name T690
Test name
Test status
Simulation time 42912801 ps
CPU time 0.61 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 195628 kb
Host smart-096e57c4-ad28-4e25-b44e-73ea50bdbff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256992141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.256992141
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4229509095
Short name T139
Test name
Test status
Simulation time 54647165 ps
CPU time 1.04 seconds
Started Jul 25 06:19:18 PM PDT 24
Finished Jul 25 06:19:19 PM PDT 24
Peak memory 195572 kb
Host smart-f0bf78b9-17dd-4007-9999-ed2066ef894a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229509095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.4
229509095
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2341680328
Short name T681
Test name
Test status
Simulation time 612785533 ps
CPU time 3.21 seconds
Started Jul 25 06:19:21 PM PDT 24
Finished Jul 25 06:19:25 PM PDT 24
Peak memory 195784 kb
Host smart-836f1763-b79e-48c5-8cb5-90b54c308f12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341680328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
341680328
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3039194792
Short name T719
Test name
Test status
Simulation time 25743823 ps
CPU time 0.65 seconds
Started Jul 25 06:19:11 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 198132 kb
Host smart-a2b85c4c-c401-4bcb-857a-04b3770ec9c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039194792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
039194792
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3234771892
Short name T708
Test name
Test status
Simulation time 57419228 ps
CPU time 1.07 seconds
Started Jul 25 06:19:20 PM PDT 24
Finished Jul 25 06:19:21 PM PDT 24
Peak memory 195788 kb
Host smart-aff62079-7a48-46e3-b604-6ccb6f723101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234771892 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.3234771892
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2986034546
Short name T132
Test name
Test status
Simulation time 35918087 ps
CPU time 0.63 seconds
Started Jul 25 06:19:11 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 197784 kb
Host smart-2685fe13-a916-41f0-9d81-f19cd3abe7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986034546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2986034546
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.401658504
Short name T74
Test name
Test status
Simulation time 33994668 ps
CPU time 0.62 seconds
Started Jul 25 06:19:08 PM PDT 24
Finished Jul 25 06:19:09 PM PDT 24
Peak memory 195500 kb
Host smart-3482df88-d7c3-4eb7-b1cd-c9081ec2173d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401658504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.401658504
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3115602023
Short name T133
Test name
Test status
Simulation time 25426048 ps
CPU time 0.71 seconds
Started Jul 25 06:19:18 PM PDT 24
Finished Jul 25 06:19:18 PM PDT 24
Peak memory 195636 kb
Host smart-137b02f6-717b-43ec-b2f8-33a7ad13662a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115602023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3115602023
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3771905441
Short name T677
Test name
Test status
Simulation time 442316412 ps
CPU time 2.17 seconds
Started Jul 25 06:19:12 PM PDT 24
Finished Jul 25 06:19:14 PM PDT 24
Peak memory 196908 kb
Host smart-066ef6c3-1b42-4037-94de-165a05a574b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771905441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3771905441
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3326788748
Short name T88
Test name
Test status
Simulation time 211177211 ps
CPU time 1.68 seconds
Started Jul 25 06:19:11 PM PDT 24
Finished Jul 25 06:19:13 PM PDT 24
Peak memory 200844 kb
Host smart-352f44d0-a47a-4180-9a8b-b5ebbb8a9400
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326788748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3326788748
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.262751820
Short name T723
Test name
Test status
Simulation time 40389763 ps
CPU time 0.58 seconds
Started Jul 25 06:20:10 PM PDT 24
Finished Jul 25 06:20:10 PM PDT 24
Peak memory 195576 kb
Host smart-8db56b8a-cc2f-49b1-8abe-916665a7c85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262751820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.262751820
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3294372869
Short name T678
Test name
Test status
Simulation time 33993741 ps
CPU time 0.61 seconds
Started Jul 25 06:20:03 PM PDT 24
Finished Jul 25 06:20:04 PM PDT 24
Peak memory 195568 kb
Host smart-55426365-a903-4bbc-b5bb-e170f4f1b2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294372869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3294372869
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1975907803
Short name T704
Test name
Test status
Simulation time 78658790 ps
CPU time 0.63 seconds
Started Jul 25 06:20:06 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 195632 kb
Host smart-2a250376-bced-4813-b1f6-5210f58ebe72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975907803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1975907803
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2018082056
Short name T697
Test name
Test status
Simulation time 100115940 ps
CPU time 0.62 seconds
Started Jul 25 06:20:15 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195568 kb
Host smart-f92d853f-071a-4d5d-837b-26024f4ebcea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018082056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2018082056
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.4086136548
Short name T75
Test name
Test status
Simulation time 51084660 ps
CPU time 0.64 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195584 kb
Host smart-470d2553-6e48-4c3e-b6e4-05400361dc2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086136548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.4086136548
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1428029027
Short name T641
Test name
Test status
Simulation time 56418193 ps
CPU time 0.62 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195596 kb
Host smart-1d9b83d0-8113-45a2-a1d6-183e42e7ec40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428029027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1428029027
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.829192891
Short name T700
Test name
Test status
Simulation time 48913732 ps
CPU time 0.61 seconds
Started Jul 25 06:20:15 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195588 kb
Host smart-31e942c9-ea42-436a-8e87-1eb8179d6aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829192891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.829192891
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1744793945
Short name T666
Test name
Test status
Simulation time 28318409 ps
CPU time 0.62 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195596 kb
Host smart-212b9fcd-0853-4357-a68c-32c2b095ecff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744793945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1744793945
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3049980958
Short name T642
Test name
Test status
Simulation time 47405554 ps
CPU time 0.6 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195568 kb
Host smart-5d429209-15db-4abd-807c-15090df36249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049980958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3049980958
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3203826886
Short name T737
Test name
Test status
Simulation time 25685236 ps
CPU time 0.62 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195584 kb
Host smart-ae34b84f-2218-4290-8091-c9be93e03a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203826886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3203826886
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1007097356
Short name T124
Test name
Test status
Simulation time 45434757 ps
CPU time 1.04 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 195600 kb
Host smart-1d774dee-803a-4904-a988-d81a4f129179
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007097356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
007097356
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.647133325
Short name T131
Test name
Test status
Simulation time 622396611 ps
CPU time 2.12 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:33 PM PDT 24
Peak memory 195720 kb
Host smart-0f707665-5164-46be-b567-3a00055af1f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647133325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.647133325
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3067270056
Short name T660
Test name
Test status
Simulation time 27365271 ps
CPU time 0.63 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 195644 kb
Host smart-20945c9b-cc24-44b7-a0ce-d598be9b2062
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067270056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
067270056
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1984082143
Short name T648
Test name
Test status
Simulation time 81433796 ps
CPU time 1.03 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:31 PM PDT 24
Peak memory 196752 kb
Host smart-572e769e-a992-41f0-a1e3-3a2f335b6b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984082143 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1984082143
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2951928248
Short name T647
Test name
Test status
Simulation time 20305664 ps
CPU time 0.69 seconds
Started Jul 25 06:19:32 PM PDT 24
Finished Jul 25 06:19:33 PM PDT 24
Peak memory 197812 kb
Host smart-3a9b6700-13a7-4322-b69d-cca590a230ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951928248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2951928248
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1424169337
Short name T692
Test name
Test status
Simulation time 23443631 ps
CPU time 0.65 seconds
Started Jul 25 06:19:21 PM PDT 24
Finished Jul 25 06:19:22 PM PDT 24
Peak memory 195584 kb
Host smart-f3b1ee10-32fc-4e1a-91d9-6036db94c881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424169337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1424169337
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.220039818
Short name T654
Test name
Test status
Simulation time 45993778 ps
CPU time 0.76 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:30 PM PDT 24
Peak memory 197932 kb
Host smart-965e2753-7889-49f4-abdc-97e0037771fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220039818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sam
e_csr_outstanding.220039818
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1639344761
Short name T67
Test name
Test status
Simulation time 127000752 ps
CPU time 1.71 seconds
Started Jul 25 06:19:19 PM PDT 24
Finished Jul 25 06:19:21 PM PDT 24
Peak memory 201260 kb
Host smart-1dc902ef-2247-4636-ac1d-bcd0257882b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639344761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1639344761
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1609225854
Short name T720
Test name
Test status
Simulation time 98551623 ps
CPU time 1.15 seconds
Started Jul 25 06:19:19 PM PDT 24
Finished Jul 25 06:19:20 PM PDT 24
Peak memory 200756 kb
Host smart-3cd780d0-ae6c-42fc-8e2d-a818ff3434ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609225854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1609225854
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3068412798
Short name T673
Test name
Test status
Simulation time 20662365 ps
CPU time 0.66 seconds
Started Jul 25 06:20:20 PM PDT 24
Finished Jul 25 06:20:21 PM PDT 24
Peak memory 195552 kb
Host smart-19ddc9a7-9add-430a-95df-829ce799ef56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068412798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3068412798
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2116285368
Short name T707
Test name
Test status
Simulation time 32848160 ps
CPU time 0.61 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195560 kb
Host smart-c6daa92f-b7d3-4de6-b079-df5f35563b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116285368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.2116285368
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3447030053
Short name T173
Test name
Test status
Simulation time 161093532 ps
CPU time 0.64 seconds
Started Jul 25 06:20:15 PM PDT 24
Finished Jul 25 06:20:15 PM PDT 24
Peak memory 195636 kb
Host smart-8ee41e52-865b-484e-860d-62aa85742de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447030053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3447030053
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2953042099
Short name T693
Test name
Test status
Simulation time 99193121 ps
CPU time 0.62 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195560 kb
Host smart-76c668da-b1e6-4194-b344-6349237c8ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953042099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2953042099
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.4241708910
Short name T658
Test name
Test status
Simulation time 43030944 ps
CPU time 0.6 seconds
Started Jul 25 06:20:15 PM PDT 24
Finished Jul 25 06:20:16 PM PDT 24
Peak memory 195612 kb
Host smart-6436cd78-e309-484b-8490-3f2547035a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241708910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.4241708910
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.4260865763
Short name T633
Test name
Test status
Simulation time 39696328 ps
CPU time 0.61 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195584 kb
Host smart-fbe4e40b-bda3-4e92-a69d-6129aa2c9c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260865763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.4260865763
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.436982576
Short name T686
Test name
Test status
Simulation time 96025077 ps
CPU time 0.66 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195532 kb
Host smart-b3ee9d8b-4717-43cc-ae47-7ce78e575a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436982576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.436982576
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.758753886
Short name T679
Test name
Test status
Simulation time 20413476 ps
CPU time 0.65 seconds
Started Jul 25 06:20:17 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195576 kb
Host smart-b82ae877-447c-4c27-996e-ed610c11c359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758753886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.758753886
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1419244902
Short name T637
Test name
Test status
Simulation time 16431777 ps
CPU time 0.62 seconds
Started Jul 25 06:20:16 PM PDT 24
Finished Jul 25 06:20:17 PM PDT 24
Peak memory 195572 kb
Host smart-7cfddfde-dd6a-4a30-993b-a8b9681fe89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419244902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1419244902
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3561398778
Short name T638
Test name
Test status
Simulation time 71662391 ps
CPU time 0.62 seconds
Started Jul 25 06:20:17 PM PDT 24
Finished Jul 25 06:20:18 PM PDT 24
Peak memory 195548 kb
Host smart-9e36daa4-0c12-48f4-a5e9-0145c0a3a4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561398778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3561398778
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.4113257942
Short name T631
Test name
Test status
Simulation time 44244065 ps
CPU time 0.87 seconds
Started Jul 25 06:19:32 PM PDT 24
Finished Jul 25 06:19:33 PM PDT 24
Peak memory 195780 kb
Host smart-70920746-bb0b-4436-8823-fa189e879ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113257942 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.4113257942
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.2450572566
Short name T130
Test name
Test status
Simulation time 20163825 ps
CPU time 0.67 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:31 PM PDT 24
Peak memory 197808 kb
Host smart-9a398363-a9d3-4aca-8ae1-012db7aaf82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450572566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2450572566
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3835504161
Short name T732
Test name
Test status
Simulation time 169597639 ps
CPU time 0.69 seconds
Started Jul 25 06:19:32 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 195588 kb
Host smart-134cb236-dabc-4d6f-a467-d0a8592d474e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835504161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3835504161
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2727630418
Short name T68
Test name
Test status
Simulation time 29519953 ps
CPU time 0.84 seconds
Started Jul 25 06:19:33 PM PDT 24
Finished Jul 25 06:19:34 PM PDT 24
Peak memory 195664 kb
Host smart-a5e4743d-4df5-47be-a350-083b978efc8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727630418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2727630418
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1367892256
Short name T63
Test name
Test status
Simulation time 97233299 ps
CPU time 1.37 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:33 PM PDT 24
Peak memory 196984 kb
Host smart-1d9d1d03-8b04-47d6-b2c0-a7ce81703126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367892256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1367892256
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3009777154
Short name T140
Test name
Test status
Simulation time 216839458 ps
CPU time 1.2 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 201056 kb
Host smart-d62dbe3c-9f09-4372-9d86-0cc30f9666f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009777154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3009777154
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2457635943
Short name T80
Test name
Test status
Simulation time 59690256 ps
CPU time 0.77 seconds
Started Jul 25 06:19:43 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195836 kb
Host smart-59383086-d0f4-4f56-a5de-25a4b0bc0ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457635943 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2457635943
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.459678913
Short name T687
Test name
Test status
Simulation time 41509249 ps
CPU time 0.64 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:31 PM PDT 24
Peak memory 195608 kb
Host smart-1adae792-d04a-4449-8500-29d2c52b78d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459678913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.459678913
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1568761460
Short name T688
Test name
Test status
Simulation time 30501664 ps
CPU time 0.74 seconds
Started Jul 25 06:19:31 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 197924 kb
Host smart-c92d3a61-c16e-415a-95c3-8314d0c56c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568761460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1568761460
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.4169550092
Short name T717
Test name
Test status
Simulation time 223557059 ps
CPU time 1.56 seconds
Started Jul 25 06:19:30 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 197984 kb
Host smart-cc33dc6a-27af-4f72-946a-414f9a0c4029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169550092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.4169550092
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3444187677
Short name T698
Test name
Test status
Simulation time 40577849 ps
CPU time 0.81 seconds
Started Jul 25 06:19:44 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 195768 kb
Host smart-4e553c58-8d66-43fd-96d1-baa8de411f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444187677 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.3444187677
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.645336781
Short name T125
Test name
Test status
Simulation time 28271333 ps
CPU time 0.66 seconds
Started Jul 25 06:19:44 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 197772 kb
Host smart-17dd3449-2182-48e7-9958-f27051e0a84b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645336781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.645336781
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1973460441
Short name T725
Test name
Test status
Simulation time 69747268 ps
CPU time 0.63 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195540 kb
Host smart-f22bea4f-f88f-4708-ad41-135ba2f532a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973460441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1973460441
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3562108237
Short name T134
Test name
Test status
Simulation time 59731986 ps
CPU time 0.66 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195676 kb
Host smart-c98cd176-fe0f-46dd-b44e-df35eccec5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562108237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.3562108237
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1545418976
Short name T73
Test name
Test status
Simulation time 95748496 ps
CPU time 1.38 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 197940 kb
Host smart-3d98b9e8-5345-46f4-b0d1-17a8c3b7f015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545418976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1545418976
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3966955704
Short name T651
Test name
Test status
Simulation time 108919680 ps
CPU time 1.21 seconds
Started Jul 25 06:19:41 PM PDT 24
Finished Jul 25 06:19:42 PM PDT 24
Peak memory 195900 kb
Host smart-30c13f42-a11c-43b3-807e-f5a75d920ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966955704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.3966955704
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1178325723
Short name T667
Test name
Test status
Simulation time 47622728 ps
CPU time 1.03 seconds
Started Jul 25 06:19:43 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195800 kb
Host smart-8b2b40c4-9c2b-46eb-8306-3fa30ce9b03d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178325723 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.1178325723
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4124435102
Short name T684
Test name
Test status
Simulation time 22708219 ps
CPU time 0.66 seconds
Started Jul 25 06:19:44 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 197772 kb
Host smart-72a55ab6-8223-42aa-8af9-9c4639fc6985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124435102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4124435102
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3186950089
Short name T721
Test name
Test status
Simulation time 17993643 ps
CPU time 0.63 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:43 PM PDT 24
Peak memory 195572 kb
Host smart-5f83b7c4-0ce2-4b42-90ca-486107961ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186950089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3186950089
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1239186865
Short name T663
Test name
Test status
Simulation time 27269671 ps
CPU time 0.76 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195636 kb
Host smart-93b944c2-0141-4fb3-bc8e-41def749043e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239186865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.1239186865
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1329591519
Short name T665
Test name
Test status
Simulation time 78831488 ps
CPU time 1.26 seconds
Started Jul 25 06:19:41 PM PDT 24
Finished Jul 25 06:19:43 PM PDT 24
Peak memory 196992 kb
Host smart-09664603-cb94-4a18-b265-7f802d5f17b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329591519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1329591519
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2125115746
Short name T630
Test name
Test status
Simulation time 204518159 ps
CPU time 1.09 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195892 kb
Host smart-823cb18d-94cd-40b8-88b9-211e79f1ec80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125115746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2125115746
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.172044981
Short name T682
Test name
Test status
Simulation time 99079199 ps
CPU time 0.63 seconds
Started Jul 25 06:19:43 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 195672 kb
Host smart-a1a29ae8-57b5-4378-9d5a-8facef73dd9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172044981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.172044981
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2995372846
Short name T691
Test name
Test status
Simulation time 36630313 ps
CPU time 0.58 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:43 PM PDT 24
Peak memory 195580 kb
Host smart-a37d5da5-10d3-4bd6-bc37-ed1462129ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995372846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2995372846
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.4033872584
Short name T676
Test name
Test status
Simulation time 67350558 ps
CPU time 0.69 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:43 PM PDT 24
Peak memory 195600 kb
Host smart-ae45d71d-9da2-4f47-a170-2fc20bf189dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033872584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.4033872584
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.573492846
Short name T85
Test name
Test status
Simulation time 95124535 ps
CPU time 1.96 seconds
Started Jul 25 06:19:42 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 197448 kb
Host smart-75cb0366-d2bf-4b0a-b174-b65ce85f2341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573492846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.573492846
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1402611155
Short name T22
Test name
Test status
Simulation time 234467067 ps
CPU time 1.5 seconds
Started Jul 25 06:19:44 PM PDT 24
Finished Jul 25 06:19:46 PM PDT 24
Peak memory 195904 kb
Host smart-c62bb6cf-3a7c-417d-9124-5b246988f87a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402611155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1402611155
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.261275265
Short name T117
Test name
Test status
Simulation time 24633678 ps
CPU time 0.66 seconds
Started Jul 25 06:21:05 PM PDT 24
Finished Jul 25 06:21:06 PM PDT 24
Peak memory 199260 kb
Host smart-3eeb4d1a-f81b-46a4-a3f4-705e611f34c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261275265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.261275265
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2865671423
Short name T410
Test name
Test status
Simulation time 29250867 ps
CPU time 0.66 seconds
Started Jul 25 06:21:03 PM PDT 24
Finished Jul 25 06:21:04 PM PDT 24
Peak memory 198084 kb
Host smart-2a1126bc-c238-45b0-be82-504b1742aa03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865671423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2865671423
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.1225299584
Short name T461
Test name
Test status
Simulation time 635365074 ps
CPU time 0.96 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 198172 kb
Host smart-be3e9d2a-b1f7-4059-88ef-b3ed40fae290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225299584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.1225299584
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3848712991
Short name T249
Test name
Test status
Simulation time 42584221 ps
CPU time 0.63 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 198128 kb
Host smart-e82d8b4c-7a43-4cf3-8def-1a5a78df5921
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848712991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3848712991
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3398985122
Short name T355
Test name
Test status
Simulation time 45877631 ps
CPU time 0.61 seconds
Started Jul 25 06:21:05 PM PDT 24
Finished Jul 25 06:21:05 PM PDT 24
Peak memory 198500 kb
Host smart-7863741a-32d2-4c5e-9d99-d7cdcb1438e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398985122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3398985122
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.198344852
Short name T417
Test name
Test status
Simulation time 67913624 ps
CPU time 0.89 seconds
Started Jul 25 06:21:01 PM PDT 24
Finished Jul 25 06:21:03 PM PDT 24
Peak memory 199096 kb
Host smart-385d5528-0a06-41de-b856-74c3698821c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198344852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.198344852
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.1625291177
Short name T264
Test name
Test status
Simulation time 117883569 ps
CPU time 0.92 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 209492 kb
Host smart-795851fc-9b23-4ce2-9892-88d8c1bcc29e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625291177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1625291177
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.888208418
Short name T19
Test name
Test status
Simulation time 323669433 ps
CPU time 1.43 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 216924 kb
Host smart-b81f52e8-0f40-4759-b354-2bd20cb40af6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888208418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.888208418
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2579217691
Short name T415
Test name
Test status
Simulation time 37685334 ps
CPU time 0.66 seconds
Started Jul 25 06:21:05 PM PDT 24
Finished Jul 25 06:21:06 PM PDT 24
Peak memory 199444 kb
Host smart-5dc5d04d-fa16-4f9e-a9d0-a9f15eabccf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579217691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2579217691
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.2709458390
Short name T615
Test name
Test status
Simulation time 46367500 ps
CPU time 0.98 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 200404 kb
Host smart-9d04a1fe-0203-4246-b0f4-c050137e5b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709458390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.2709458390
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.3533618599
Short name T156
Test name
Test status
Simulation time 82443367 ps
CPU time 0.69 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 198600 kb
Host smart-cc0834f1-86e0-484a-9716-7cd36876aa50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533618599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.3533618599
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3212462296
Short name T604
Test name
Test status
Simulation time 29956903 ps
CPU time 0.64 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 198072 kb
Host smart-d5ad6955-831c-4a52-88d8-a0b2ff18e799
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212462296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.3212462296
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.4228316084
Short name T402
Test name
Test status
Simulation time 315548566 ps
CPU time 1.06 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 198472 kb
Host smart-03a2eaeb-9fbb-4366-b0d5-6d85d7da3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228316084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.4228316084
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1998712
Short name T345
Test name
Test status
Simulation time 56505750 ps
CPU time 0.63 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 197412 kb
Host smart-ce9f3aff-52b7-4853-8295-70e0be3f57f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1998712
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.3742335832
Short name T505
Test name
Test status
Simulation time 44317656 ps
CPU time 0.61 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 198224 kb
Host smart-c5b85f15-a6e1-4ad2-9ed7-6345af02d070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742335832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.3742335832
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1540712293
Short name T370
Test name
Test status
Simulation time 80816100 ps
CPU time 0.69 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 201448 kb
Host smart-34e5434a-ef97-4778-9b64-c6106143625e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540712293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1540712293
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.4266320579
Short name T7
Test name
Test status
Simulation time 63714816 ps
CPU time 0.76 seconds
Started Jul 25 06:21:11 PM PDT 24
Finished Jul 25 06:21:12 PM PDT 24
Peak memory 198408 kb
Host smart-1be92657-bf1b-4577-b2ac-6ed0e0a09c38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266320579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.4266320579
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.459992247
Short name T371
Test name
Test status
Simulation time 114878500 ps
CPU time 0.85 seconds
Started Jul 25 06:21:14 PM PDT 24
Finished Jul 25 06:21:15 PM PDT 24
Peak memory 209504 kb
Host smart-fabcd923-bce7-4c59-9364-6a30f5b5bc3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459992247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.459992247
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.833224667
Short name T33
Test name
Test status
Simulation time 651244095 ps
CPU time 2.12 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:15 PM PDT 24
Peak memory 217880 kb
Host smart-b32b0f85-cdf3-4291-a1e2-4322dbb97fd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833224667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.833224667
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3641079652
Short name T552
Test name
Test status
Simulation time 57593849 ps
CPU time 0.78 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 198148 kb
Host smart-b145dbf8-394c-4632-ac3f-fd36e7db67ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641079652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3641079652
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.534892186
Short name T488
Test name
Test status
Simulation time 30690791 ps
CPU time 0.69 seconds
Started Jul 25 06:21:12 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 199420 kb
Host smart-e719ba47-ad7d-4387-a734-ce2916b78b2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534892186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.534892186
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.635662103
Short name T447
Test name
Test status
Simulation time 46436393 ps
CPU time 0.73 seconds
Started Jul 25 06:21:59 PM PDT 24
Finished Jul 25 06:22:00 PM PDT 24
Peak memory 199216 kb
Host smart-16a73123-112e-40c2-bb93-e3e65f73bcbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635662103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disa
ble_rom_integrity_check.635662103
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2247398347
Short name T541
Test name
Test status
Simulation time 38918493 ps
CPU time 0.58 seconds
Started Jul 25 06:21:59 PM PDT 24
Finished Jul 25 06:22:00 PM PDT 24
Peak memory 198080 kb
Host smart-089f5f8f-c6ad-457c-b873-5b63cfdffdbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247398347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2247398347
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.2738800007
Short name T411
Test name
Test status
Simulation time 1481253097 ps
CPU time 0.96 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 198184 kb
Host smart-e122e7f7-ab90-49e3-b5d0-060dbcf66779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738800007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2738800007
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.4097095606
Short name T369
Test name
Test status
Simulation time 111962660 ps
CPU time 0.66 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 198120 kb
Host smart-f95da8f3-34d2-41a4-a25f-02e0903b5e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097095606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.4097095606
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2668523763
Short name T588
Test name
Test status
Simulation time 47113410 ps
CPU time 0.65 seconds
Started Jul 25 06:21:59 PM PDT 24
Finished Jul 25 06:22:00 PM PDT 24
Peak memory 198168 kb
Host smart-2a463599-6c55-4683-a838-156414704726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668523763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2668523763
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.4012014462
Short name T210
Test name
Test status
Simulation time 51933357 ps
CPU time 0.69 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 201412 kb
Host smart-78f6846f-6cb3-4ec6-8b43-f7c99c3932fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012014462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.4012014462
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.3851466407
Short name T550
Test name
Test status
Simulation time 52765457 ps
CPU time 0.8 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 199208 kb
Host smart-7271e5a6-1388-4f91-aa3e-fab38bf5ea05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851466407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3851466407
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.799152769
Short name T379
Test name
Test status
Simulation time 166096024 ps
CPU time 0.8 seconds
Started Jul 25 06:21:56 PM PDT 24
Finished Jul 25 06:21:57 PM PDT 24
Peak memory 209540 kb
Host smart-ef061a99-09e0-4f2e-8f49-e00eb0b809fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799152769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.799152769
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1654768430
Short name T611
Test name
Test status
Simulation time 131713424 ps
CPU time 0.81 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 198132 kb
Host smart-0bfe8c9b-c2af-440a-9d51-c68a63cfad4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654768430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1654768430
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2368663280
Short name T280
Test name
Test status
Simulation time 48339195 ps
CPU time 0.6 seconds
Started Jul 25 06:22:16 PM PDT 24
Finished Jul 25 06:22:17 PM PDT 24
Peak memory 198472 kb
Host smart-6ae95b98-faf1-4fee-bf5d-de9b40ac177a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368663280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2368663280
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2643574493
Short name T14
Test name
Test status
Simulation time 30676729 ps
CPU time 0.8 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 198908 kb
Host smart-df2d53df-1e72-4e7d-8224-bb99f61f5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643574493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2643574493
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.200760722
Short name T595
Test name
Test status
Simulation time 31736235 ps
CPU time 0.59 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:17 PM PDT 24
Peak memory 198032 kb
Host smart-41c3ec6a-e995-410b-9859-cd83bb9f9d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200760722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_
malfunc.200760722
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1249632107
Short name T452
Test name
Test status
Simulation time 788176513 ps
CPU time 0.99 seconds
Started Jul 25 06:21:59 PM PDT 24
Finished Jul 25 06:22:00 PM PDT 24
Peak memory 198468 kb
Host smart-b4b89191-7a15-4ec8-b711-81bf5ec39f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249632107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1249632107
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2161312960
Short name T26
Test name
Test status
Simulation time 62471278 ps
CPU time 0.66 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 198124 kb
Host smart-8b44a05b-a69f-4793-a46e-5641cf67e629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161312960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2161312960
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1774947956
Short name T230
Test name
Test status
Simulation time 48857616 ps
CPU time 0.64 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 198080 kb
Host smart-107c901b-27f5-45a9-8f5d-ed82deed8cb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774947956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1774947956
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1598622305
Short name T199
Test name
Test status
Simulation time 45612016 ps
CPU time 0.7 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 201420 kb
Host smart-18d38ecd-cdbc-4656-8f5e-a7a9c8200fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598622305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1598622305
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.231633645
Short name T618
Test name
Test status
Simulation time 134404853 ps
CPU time 0.75 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 198144 kb
Host smart-23789e0b-7bd9-404d-9ac8-c77d9c9aaa57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231633645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.231633645
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2290535202
Short name T244
Test name
Test status
Simulation time 115123666 ps
CPU time 0.95 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 209520 kb
Host smart-9bdaac34-e4a2-406a-ab1d-d57d474da5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290535202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2290535202
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1467326533
Short name T219
Test name
Test status
Simulation time 62597588 ps
CPU time 0.77 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 199180 kb
Host smart-df46d79f-a6fb-4b12-bd3b-3c4f1d06dc85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467326533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1467326533
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1156969003
Short name T565
Test name
Test status
Simulation time 60855694 ps
CPU time 0.64 seconds
Started Jul 25 06:21:59 PM PDT 24
Finished Jul 25 06:22:00 PM PDT 24
Peak memory 199308 kb
Host smart-cbc61346-51c1-4652-9524-ab67c95d7607
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156969003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1156969003
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.4211094046
Short name T467
Test name
Test status
Simulation time 23378374 ps
CPU time 0.74 seconds
Started Jul 25 06:22:11 PM PDT 24
Finished Jul 25 06:22:12 PM PDT 24
Peak memory 199280 kb
Host smart-d5870e0b-527e-4dc5-8647-2db2e1fd3f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211094046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4211094046
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2242436453
Short name T627
Test name
Test status
Simulation time 37925643 ps
CPU time 0.58 seconds
Started Jul 25 06:22:11 PM PDT 24
Finished Jul 25 06:22:12 PM PDT 24
Peak memory 198104 kb
Host smart-2e4416e2-50cf-4f51-8fba-a5837295955f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242436453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.2242436453
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.195911903
Short name T253
Test name
Test status
Simulation time 329373830 ps
CPU time 0.94 seconds
Started Jul 25 06:22:14 PM PDT 24
Finished Jul 25 06:22:15 PM PDT 24
Peak memory 198164 kb
Host smart-9206fd9f-0be0-4f4e-811c-da977fb028db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195911903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.195911903
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.970118871
Short name T603
Test name
Test status
Simulation time 33122028 ps
CPU time 0.64 seconds
Started Jul 25 06:22:13 PM PDT 24
Finished Jul 25 06:22:14 PM PDT 24
Peak memory 198108 kb
Host smart-cf568928-a942-4820-941f-95438dc18a37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970118871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.970118871
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.1123633862
Short name T233
Test name
Test status
Simulation time 71066688 ps
CPU time 0.59 seconds
Started Jul 25 06:22:04 PM PDT 24
Finished Jul 25 06:22:05 PM PDT 24
Peak memory 198156 kb
Host smart-07333f84-a890-49d9-bba6-58db6425f14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123633862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1123633862
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.460722541
Short name T184
Test name
Test status
Simulation time 42931431 ps
CPU time 0.75 seconds
Started Jul 25 06:22:12 PM PDT 24
Finished Jul 25 06:22:13 PM PDT 24
Peak memory 201452 kb
Host smart-c984c244-c1b9-425c-b34d-18cb0a4e1ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460722541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.460722541
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.3696359167
Short name T226
Test name
Test status
Simulation time 169084285 ps
CPU time 0.7 seconds
Started Jul 25 06:21:57 PM PDT 24
Finished Jul 25 06:21:58 PM PDT 24
Peak memory 198428 kb
Host smart-50d888a2-37d4-4fd1-98b0-992fb93a3c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696359167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.3696359167
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2731260887
Short name T514
Test name
Test status
Simulation time 112822444 ps
CPU time 0.89 seconds
Started Jul 25 06:22:07 PM PDT 24
Finished Jul 25 06:22:08 PM PDT 24
Peak memory 209536 kb
Host smart-f81081a9-dce6-4df8-bb2a-55b744d5cfeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731260887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2731260887
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.4154301390
Short name T311
Test name
Test status
Simulation time 45986095 ps
CPU time 0.61 seconds
Started Jul 25 06:21:58 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 198600 kb
Host smart-fae2bcb9-e8e7-456f-b367-b19b3ed7cb29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154301390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.4154301390
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1331421689
Short name T500
Test name
Test status
Simulation time 29020598 ps
CPU time 0.65 seconds
Started Jul 25 06:22:14 PM PDT 24
Finished Jul 25 06:22:15 PM PDT 24
Peak memory 198620 kb
Host smart-7302bda9-2c89-4fde-a188-c989fbd1ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331421689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1331421689
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.912221010
Short name T181
Test name
Test status
Simulation time 73302058 ps
CPU time 0.65 seconds
Started Jul 25 06:22:16 PM PDT 24
Finished Jul 25 06:22:17 PM PDT 24
Peak memory 198664 kb
Host smart-9cc37b07-2703-423d-9fe5-7075170e1b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912221010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.912221010
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.4228092056
Short name T234
Test name
Test status
Simulation time 38516089 ps
CPU time 0.64 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198076 kb
Host smart-c2b136cb-2c02-4c92-ac86-e9a620e86425
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228092056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.4228092056
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2238268241
Short name T239
Test name
Test status
Simulation time 163451790 ps
CPU time 0.98 seconds
Started Jul 25 06:22:15 PM PDT 24
Finished Jul 25 06:22:16 PM PDT 24
Peak memory 198176 kb
Host smart-220338b7-edba-4d2f-ab93-d78bf5073f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238268241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2238268241
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.147147826
Short name T240
Test name
Test status
Simulation time 34843926 ps
CPU time 0.64 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198096 kb
Host smart-8d19901e-e707-41ac-b42e-606ad30a2862
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147147826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.147147826
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.489707286
Short name T362
Test name
Test status
Simulation time 31520618 ps
CPU time 0.6 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 198096 kb
Host smart-fefc7974-4660-40d7-bfb5-d6a9fce3db42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489707286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.489707286
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2539450333
Short name T201
Test name
Test status
Simulation time 68115069 ps
CPU time 0.66 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 201508 kb
Host smart-46e8e560-12f9-4603-a783-c3023e408a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539450333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2539450333
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3761415661
Short name T449
Test name
Test status
Simulation time 85685686 ps
CPU time 0.71 seconds
Started Jul 25 06:22:11 PM PDT 24
Finished Jul 25 06:22:12 PM PDT 24
Peak memory 198476 kb
Host smart-fe4e4dc8-a2ea-477e-b518-dcf39c4e1b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761415661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3761415661
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2298669394
Short name T420
Test name
Test status
Simulation time 114244187 ps
CPU time 0.99 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 209516 kb
Host smart-f2a163d1-a407-4fb1-ac86-dbe450d5fd8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298669394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2298669394
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2581537082
Short name T430
Test name
Test status
Simulation time 75906084 ps
CPU time 0.7 seconds
Started Jul 25 06:22:15 PM PDT 24
Finished Jul 25 06:22:16 PM PDT 24
Peak memory 198192 kb
Host smart-3d471993-4acd-4ff6-b5f5-54953e2e2e54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581537082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2581537082
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1918895962
Short name T356
Test name
Test status
Simulation time 49858865 ps
CPU time 0.64 seconds
Started Jul 25 06:22:12 PM PDT 24
Finished Jul 25 06:22:13 PM PDT 24
Peak memory 198564 kb
Host smart-2002ae5f-913c-4636-af7b-d3f6008a0648
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918895962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1918895962
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3072695718
Short name T152
Test name
Test status
Simulation time 65629339 ps
CPU time 0.66 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 199572 kb
Host smart-929afb9a-c5ae-463e-bc28-74d56b4441d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072695718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3072695718
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1721777733
Short name T319
Test name
Test status
Simulation time 27987003 ps
CPU time 0.61 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198072 kb
Host smart-4ca88805-3366-4622-97c6-98b2bdc6ef0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721777733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1721777733
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2020499033
Short name T141
Test name
Test status
Simulation time 3004779478 ps
CPU time 1 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 198588 kb
Host smart-6c4915fc-07e4-4059-822d-5032e5a367da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020499033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2020499033
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2655232865
Short name T305
Test name
Test status
Simulation time 43603524 ps
CPU time 0.59 seconds
Started Jul 25 06:22:16 PM PDT 24
Finished Jul 25 06:22:16 PM PDT 24
Peak memory 198164 kb
Host smart-9b0f30bb-1d7a-4c45-9c84-a9ace4f88874
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655232865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2655232865
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3546617726
Short name T383
Test name
Test status
Simulation time 62111397 ps
CPU time 0.6 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 198192 kb
Host smart-d055a8e8-72ee-4297-8050-4c8fc4e7c673
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546617726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3546617726
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1899681572
Short name T10
Test name
Test status
Simulation time 49360688 ps
CPU time 0.82 seconds
Started Jul 25 06:22:14 PM PDT 24
Finished Jul 25 06:22:15 PM PDT 24
Peak memory 198480 kb
Host smart-6be5a543-5bd7-4575-9c34-f7eba60b17fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899681572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1899681572
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3832396389
Short name T276
Test name
Test status
Simulation time 106419058 ps
CPU time 0.99 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 209568 kb
Host smart-aa87f11c-5f4e-4227-b54d-6223dd99e372
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832396389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3832396389
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2542963059
Short name T599
Test name
Test status
Simulation time 158555669 ps
CPU time 0.76 seconds
Started Jul 25 06:22:20 PM PDT 24
Finished Jul 25 06:22:21 PM PDT 24
Peak memory 198308 kb
Host smart-661d3cdb-f2b0-4aad-9802-f53e4d0c9663
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542963059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2542963059
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.780740460
Short name T39
Test name
Test status
Simulation time 53861393 ps
CPU time 0.66 seconds
Started Jul 25 06:22:16 PM PDT 24
Finished Jul 25 06:22:17 PM PDT 24
Peak memory 199432 kb
Host smart-494e704e-8c19-4104-b8f0-16ad6f879721
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780740460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.780740460
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1844067316
Short name T116
Test name
Test status
Simulation time 24585586 ps
CPU time 0.71 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198836 kb
Host smart-74cb0c31-f8b9-4083-9a73-03465b0a98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844067316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1844067316
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1269401059
Short name T524
Test name
Test status
Simulation time 57925679 ps
CPU time 0.86 seconds
Started Jul 25 06:22:19 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 199184 kb
Host smart-e59accb8-fce3-404a-b38f-ff5997a9587c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269401059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1269401059
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.901936241
Short name T444
Test name
Test status
Simulation time 34435651 ps
CPU time 0.6 seconds
Started Jul 25 06:22:14 PM PDT 24
Finished Jul 25 06:22:15 PM PDT 24
Peak memory 198096 kb
Host smart-639976f0-727e-4aad-a095-f66e7b843f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901936241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_
malfunc.901936241
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.1698409325
Short name T145
Test name
Test status
Simulation time 164467329 ps
CPU time 1 seconds
Started Jul 25 06:22:19 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 198164 kb
Host smart-7f07926b-693e-4336-a3a0-1ef13f9e14f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698409325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1698409325
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2390681592
Short name T560
Test name
Test status
Simulation time 87180288 ps
CPU time 0.6 seconds
Started Jul 25 06:22:19 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 198120 kb
Host smart-52f4135a-ee60-4be9-ab4a-4e0f86aab741
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390681592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2390681592
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3022223249
Short name T448
Test name
Test status
Simulation time 80178737 ps
CPU time 0.6 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:18 PM PDT 24
Peak memory 198172 kb
Host smart-65341be3-9d93-46cb-827d-626f62523ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022223249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3022223249
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3334671241
Short name T492
Test name
Test status
Simulation time 103733268 ps
CPU time 0.66 seconds
Started Jul 25 06:22:15 PM PDT 24
Finished Jul 25 06:22:16 PM PDT 24
Peak memory 199152 kb
Host smart-92ecfc91-3ba0-415f-955c-167c09ad2472
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334671241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3334671241
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2429413623
Short name T613
Test name
Test status
Simulation time 130547327 ps
CPU time 0.97 seconds
Started Jul 25 06:22:19 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 209460 kb
Host smart-e9a84668-9d20-453f-b0d1-bffaea0581b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429413623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2429413623
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.939063153
Short name T408
Test name
Test status
Simulation time 63336045 ps
CPU time 0.88 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198164 kb
Host smart-d865b06a-39c9-4011-bf57-50ace448e7e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939063153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.939063153
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.2855528431
Short name T284
Test name
Test status
Simulation time 32106632 ps
CPU time 0.7 seconds
Started Jul 25 06:22:17 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198476 kb
Host smart-765a1c94-d6c7-4344-afba-6111b7ee830e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855528431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.2855528431
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.213862826
Short name T454
Test name
Test status
Simulation time 30265038 ps
CPU time 0.77 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 198956 kb
Host smart-c9d68f1a-51f6-4a82-9a6c-6e0c8b39075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213862826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.213862826
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.510231199
Short name T566
Test name
Test status
Simulation time 29446097 ps
CPU time 0.64 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198088 kb
Host smart-5298e00f-3f6a-4714-b5ca-53b937a3e00e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510231199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.510231199
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.2942681236
Short name T425
Test name
Test status
Simulation time 167106362 ps
CPU time 1.02 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 198484 kb
Host smart-00d7da17-c73e-465c-904a-73f6e83d5d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942681236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.2942681236
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.2757567081
Short name T515
Test name
Test status
Simulation time 34937318 ps
CPU time 0.63 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 197388 kb
Host smart-86c0aa9f-f5e5-42d1-8a66-09a1be65699a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757567081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2757567081
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3134868212
Short name T570
Test name
Test status
Simulation time 62551885 ps
CPU time 0.63 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 198096 kb
Host smart-cc398676-0f04-48e0-9155-e09a1ea88a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134868212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3134868212
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.4013679399
Short name T549
Test name
Test status
Simulation time 44578557 ps
CPU time 0.75 seconds
Started Jul 25 06:22:29 PM PDT 24
Finished Jul 25 06:22:29 PM PDT 24
Peak memory 201416 kb
Host smart-f80c7c96-9210-4111-8a7b-5ea84d9f21e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013679399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.4013679399
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3038267528
Short name T575
Test name
Test status
Simulation time 69336370 ps
CPU time 0.74 seconds
Started Jul 25 06:22:18 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 198400 kb
Host smart-1bda426d-a2e7-4533-9853-932c8184583d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038267528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3038267528
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.360356980
Short name T326
Test name
Test status
Simulation time 175051371 ps
CPU time 0.84 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 209620 kb
Host smart-cb83a1bd-38be-4cb3-b127-8ad1f93104d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360356980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.360356980
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.4170201761
Short name T111
Test name
Test status
Simulation time 168944285 ps
CPU time 0.83 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 199292 kb
Host smart-36fea0b9-307b-4ac1-bd9d-36567205425d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170201761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4170201761
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3337614649
Short name T426
Test name
Test status
Simulation time 142381026 ps
CPU time 0.63 seconds
Started Jul 25 06:22:19 PM PDT 24
Finished Jul 25 06:22:20 PM PDT 24
Peak memory 198576 kb
Host smart-bd3954b0-fec8-451c-ba26-4cee04bd76cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337614649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3337614649
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2229222827
Short name T16
Test name
Test status
Simulation time 35682729 ps
CPU time 0.63 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198680 kb
Host smart-fa55fb45-9953-4d2a-9a6a-f35093e1b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229222827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2229222827
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2706817778
Short name T352
Test name
Test status
Simulation time 31410848 ps
CPU time 0.61 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 198092 kb
Host smart-cccec4cd-e840-4428-9c93-739a70e7a9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706817778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2706817778
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.383033735
Short name T391
Test name
Test status
Simulation time 157643557 ps
CPU time 0.94 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198172 kb
Host smart-ace8d2b9-dee7-464e-a425-ba46d66817dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383033735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.383033735
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3725420748
Short name T602
Test name
Test status
Simulation time 50038092 ps
CPU time 0.62 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198064 kb
Host smart-fe9ea29e-f9ea-49cf-9754-153560bb24e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725420748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3725420748
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.4269794415
Short name T393
Test name
Test status
Simulation time 36257357 ps
CPU time 0.65 seconds
Started Jul 25 06:22:29 PM PDT 24
Finished Jul 25 06:22:30 PM PDT 24
Peak memory 198428 kb
Host smart-8248b1ec-0c85-4630-b7d9-3e64392888ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269794415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.4269794415
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3347149624
Short name T95
Test name
Test status
Simulation time 55078451 ps
CPU time 0.71 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 201396 kb
Host smart-a559016e-085c-4b10-b807-3c415507884d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347149624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3347149624
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2096016571
Short name T304
Test name
Test status
Simulation time 61698953 ps
CPU time 0.82 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 198480 kb
Host smart-ec82b845-54b0-4682-b23a-ecd4d0ad96a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096016571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2096016571
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2857222691
Short name T34
Test name
Test status
Simulation time 461770973 ps
CPU time 0.79 seconds
Started Jul 25 06:22:26 PM PDT 24
Finished Jul 25 06:22:27 PM PDT 24
Peak memory 209604 kb
Host smart-3e825952-f2b7-453f-a219-a18013cae146
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857222691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2857222691
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2703500361
Short name T493
Test name
Test status
Simulation time 128935746 ps
CPU time 0.71 seconds
Started Jul 25 06:22:25 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 198376 kb
Host smart-27e1476a-7f24-471f-9cbb-9a599eec1a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703500361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2703500361
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.93151737
Short name T266
Test name
Test status
Simulation time 54761330 ps
CPU time 0.62 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 199432 kb
Host smart-947b66cf-8872-460b-9cd1-47dfd6b069f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93151737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.93151737
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.1110997270
Short name T54
Test name
Test status
Simulation time 64417751 ps
CPU time 0.65 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 198368 kb
Host smart-1bf8e8d5-1e49-462c-96ef-28e00fc03888
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110997270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.1110997270
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1364949778
Short name T60
Test name
Test status
Simulation time 263279583 ps
CPU time 0.81 seconds
Started Jul 25 06:22:29 PM PDT 24
Finished Jul 25 06:22:30 PM PDT 24
Peak memory 200084 kb
Host smart-702d1ffb-efe1-42c4-b944-1eb27a4219d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364949778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1364949778
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.773437919
Short name T166
Test name
Test status
Simulation time 38268141 ps
CPU time 0.74 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 199212 kb
Host smart-a4f7a6db-55d8-4e69-9164-320a96ef47dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773437919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.773437919
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1600507059
Short name T384
Test name
Test status
Simulation time 29399669 ps
CPU time 0.65 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 198124 kb
Host smart-056b7b98-d8d7-4e9e-a0ce-d39f1dc2f303
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600507059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1600507059
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.1938920440
Short name T288
Test name
Test status
Simulation time 163891305 ps
CPU time 1.02 seconds
Started Jul 25 06:22:45 PM PDT 24
Finished Jul 25 06:22:46 PM PDT 24
Peak memory 198176 kb
Host smart-d5188739-971a-400a-8941-a6f9c2e2ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938920440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.1938920440
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3777111872
Short name T489
Test name
Test status
Simulation time 49086047 ps
CPU time 0.59 seconds
Started Jul 25 06:22:42 PM PDT 24
Finished Jul 25 06:22:43 PM PDT 24
Peak memory 198188 kb
Host smart-26cc0f82-918e-4adc-b9c5-9a75df24bb93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777111872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3777111872
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.2283429806
Short name T475
Test name
Test status
Simulation time 83851872 ps
CPU time 0.71 seconds
Started Jul 25 06:22:44 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 201360 kb
Host smart-c12366ae-a41a-469a-b6b6-23bda495b7c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283429806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.2283429806
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3715716693
Short name T480
Test name
Test status
Simulation time 66020740 ps
CPU time 0.84 seconds
Started Jul 25 06:22:27 PM PDT 24
Finished Jul 25 06:22:28 PM PDT 24
Peak memory 198464 kb
Host smart-efed23b2-e7e7-4ade-9bb9-bdd2f93b7149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715716693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3715716693
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2767062189
Short name T303
Test name
Test status
Simulation time 103382003 ps
CPU time 1.09 seconds
Started Jul 25 06:22:44 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 209496 kb
Host smart-091c9b16-9d18-4d77-9347-70479c14048b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767062189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2767062189
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3781748879
Short name T495
Test name
Test status
Simulation time 53428086 ps
CPU time 0.77 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 198192 kb
Host smart-ab73e413-9847-465a-9fe8-598213e7fb06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781748879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3781748879
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3151221393
Short name T90
Test name
Test status
Simulation time 40985579 ps
CPU time 0.68 seconds
Started Jul 25 06:22:28 PM PDT 24
Finished Jul 25 06:22:29 PM PDT 24
Peak memory 199428 kb
Host smart-52182af4-0f32-4f01-a710-8f75bf50da1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151221393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3151221393
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1632365982
Short name T424
Test name
Test status
Simulation time 105621412 ps
CPU time 0.78 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 198980 kb
Host smart-36635c7e-f517-405a-b637-00e46197eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632365982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1632365982
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2141847354
Short name T163
Test name
Test status
Simulation time 81318426 ps
CPU time 0.69 seconds
Started Jul 25 06:22:44 PM PDT 24
Finished Jul 25 06:22:46 PM PDT 24
Peak memory 198548 kb
Host smart-888b86ba-3dde-4511-9ff4-6521749d883d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141847354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2141847354
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2865305036
Short name T472
Test name
Test status
Simulation time 37580136 ps
CPU time 0.6 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 198060 kb
Host smart-269724db-aa1f-4cc4-a7e6-83f5f5476860
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865305036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2865305036
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.1910277961
Short name T450
Test name
Test status
Simulation time 652282510 ps
CPU time 0.96 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 198164 kb
Host smart-47190358-9c4f-4531-a6b4-6fbbdec6ea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910277961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1910277961
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1999155826
Short name T494
Test name
Test status
Simulation time 39841765 ps
CPU time 0.64 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 198196 kb
Host smart-b9bfe2a5-614b-43cb-bd0f-3c2aaecfe794
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999155826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1999155826
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.773831245
Short name T621
Test name
Test status
Simulation time 62945350 ps
CPU time 0.6 seconds
Started Jul 25 06:22:42 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 198136 kb
Host smart-49bd246f-4920-4573-b5b9-0507575e8295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773831245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.773831245
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2190841534
Short name T94
Test name
Test status
Simulation time 71184735 ps
CPU time 0.65 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 201432 kb
Host smart-801a01af-4e3d-46de-ab85-53666b0c32d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190841534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2190841534
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1691748055
Short name T563
Test name
Test status
Simulation time 35122701 ps
CPU time 0.68 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 199156 kb
Host smart-f9de3f0e-85c9-4711-a58d-d91b86c13e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691748055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1691748055
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3368593036
Short name T476
Test name
Test status
Simulation time 178675982 ps
CPU time 0.81 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 209596 kb
Host smart-81ed11cd-ed45-41c4-9f4f-41d6bb179853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368593036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3368593036
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3416538221
Short name T501
Test name
Test status
Simulation time 180801983 ps
CPU time 0.85 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 199412 kb
Host smart-bfdb015d-c1d6-4b9f-9c29-2cfa6382e698
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416538221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3416538221
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3865525159
Short name T580
Test name
Test status
Simulation time 34048257 ps
CPU time 0.68 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 198532 kb
Host smart-5b99ab27-1400-4dfe-b2aa-f05e27334bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865525159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3865525159
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.4034306256
Short name T389
Test name
Test status
Simulation time 24213497 ps
CPU time 0.91 seconds
Started Jul 25 06:21:13 PM PDT 24
Finished Jul 25 06:21:14 PM PDT 24
Peak memory 200328 kb
Host smart-f3d46d53-e934-45c2-b724-f3a0b0c509e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034306256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.4034306256
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1695993703
Short name T421
Test name
Test status
Simulation time 62280005 ps
CPU time 0.82 seconds
Started Jul 25 06:21:20 PM PDT 24
Finished Jul 25 06:21:20 PM PDT 24
Peak memory 198512 kb
Host smart-25a00dfe-fc3b-4fb8-8cee-05ce9ba9baa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695993703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1695993703
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2784878672
Short name T318
Test name
Test status
Simulation time 29496929 ps
CPU time 0.64 seconds
Started Jul 25 06:21:23 PM PDT 24
Finished Jul 25 06:21:24 PM PDT 24
Peak memory 198056 kb
Host smart-aee65878-0d49-49a9-95f6-1c86c83b887a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784878672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.2784878672
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3374703880
Short name T577
Test name
Test status
Simulation time 318559126 ps
CPU time 0.94 seconds
Started Jul 25 06:21:22 PM PDT 24
Finished Jul 25 06:21:23 PM PDT 24
Peak memory 198464 kb
Host smart-b2b162b2-e4a3-4cd8-ad1f-0ccd5de6c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374703880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3374703880
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3770213290
Short name T528
Test name
Test status
Simulation time 34379615 ps
CPU time 0.65 seconds
Started Jul 25 06:21:24 PM PDT 24
Finished Jul 25 06:21:25 PM PDT 24
Peak memory 197384 kb
Host smart-78e9c2f8-a199-4992-8f30-eba7be2cb9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770213290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3770213290
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1402517680
Short name T483
Test name
Test status
Simulation time 22505848 ps
CPU time 0.62 seconds
Started Jul 25 06:21:21 PM PDT 24
Finished Jul 25 06:21:22 PM PDT 24
Peak memory 198156 kb
Host smart-139b591d-5fa1-4cf8-82ac-1b4cddfac54b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402517680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1402517680
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2944092203
Short name T207
Test name
Test status
Simulation time 47766677 ps
CPU time 0.7 seconds
Started Jul 25 06:21:23 PM PDT 24
Finished Jul 25 06:21:24 PM PDT 24
Peak memory 201260 kb
Host smart-7275a37c-0f9d-49dc-9d01-2c5cb5a2ce8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944092203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2944092203
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3961013794
Short name T274
Test name
Test status
Simulation time 54508710 ps
CPU time 0.87 seconds
Started Jul 25 06:21:15 PM PDT 24
Finished Jul 25 06:21:16 PM PDT 24
Peak memory 198456 kb
Host smart-91f54be2-476e-4f65-b0c3-0843f72743f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961013794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3961013794
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3456400537
Short name T596
Test name
Test status
Simulation time 112081278 ps
CPU time 0.87 seconds
Started Jul 25 06:21:23 PM PDT 24
Finished Jul 25 06:21:24 PM PDT 24
Peak memory 209576 kb
Host smart-8ce2a3da-11b4-4808-a19f-43e4eed889c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456400537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3456400537
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1329240686
Short name T32
Test name
Test status
Simulation time 355424130 ps
CPU time 1.52 seconds
Started Jul 25 06:21:24 PM PDT 24
Finished Jul 25 06:21:25 PM PDT 24
Peak memory 216932 kb
Host smart-80a0ae9c-6410-4df1-9652-73eacc3b29ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329240686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1329240686
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.857231252
Short name T400
Test name
Test status
Simulation time 59557822 ps
CPU time 0.91 seconds
Started Jul 25 06:21:23 PM PDT 24
Finished Jul 25 06:21:24 PM PDT 24
Peak memory 198000 kb
Host smart-dc6f9618-8c46-476d-a15c-17c2250ca08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857231252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.857231252
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3641759944
Short name T96
Test name
Test status
Simulation time 66510417 ps
CPU time 0.99 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 200200 kb
Host smart-788fe2cc-5f3a-4150-9a3c-0a9081aea2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641759944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3641759944
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.688829877
Short name T292
Test name
Test status
Simulation time 66203999 ps
CPU time 0.71 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 198640 kb
Host smart-7652bb90-10a2-4e11-9383-80d827213d1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688829877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.688829877
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3131861984
Short name T359
Test name
Test status
Simulation time 32046311 ps
CPU time 0.68 seconds
Started Jul 25 06:22:47 PM PDT 24
Finished Jul 25 06:22:48 PM PDT 24
Peak memory 198096 kb
Host smart-d2bd2407-f960-4fed-bb14-203fac817c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131861984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3131861984
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.466776966
Short name T540
Test name
Test status
Simulation time 603594736 ps
CPU time 1 seconds
Started Jul 25 06:22:47 PM PDT 24
Finished Jul 25 06:22:48 PM PDT 24
Peak memory 198216 kb
Host smart-6eb3da19-eb34-4e8d-a982-33e811b25525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466776966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.466776966
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.458506222
Short name T533
Test name
Test status
Simulation time 39576586 ps
CPU time 0.69 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 198092 kb
Host smart-0d75e981-e6c6-43ab-8400-d0dcf7dfa3ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458506222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.458506222
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.920949815
Short name T608
Test name
Test status
Simulation time 56548761 ps
CPU time 0.61 seconds
Started Jul 25 06:22:45 PM PDT 24
Finished Jul 25 06:22:46 PM PDT 24
Peak memory 198132 kb
Host smart-659f963d-b360-4ee8-91eb-3538a3992cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920949815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.920949815
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.813296458
Short name T216
Test name
Test status
Simulation time 106479923 ps
CPU time 0.7 seconds
Started Jul 25 06:22:44 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 201320 kb
Host smart-b8b5ceb4-2bae-442b-aad1-e729d43c3b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813296458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invali
d.813296458
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.2511205708
Short name T250
Test name
Test status
Simulation time 135058218 ps
CPU time 0.79 seconds
Started Jul 25 06:22:44 PM PDT 24
Finished Jul 25 06:22:46 PM PDT 24
Peak memory 198500 kb
Host smart-e699996d-ccf1-4cd3-a51c-c7a813ad3dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511205708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2511205708
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1620374083
Short name T265
Test name
Test status
Simulation time 159766335 ps
CPU time 0.76 seconds
Started Jul 25 06:22:41 PM PDT 24
Finished Jul 25 06:22:42 PM PDT 24
Peak memory 209548 kb
Host smart-6d5b4dd6-391f-4dd0-85b2-5cee7ab3e5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620374083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1620374083
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.164774725
Short name T413
Test name
Test status
Simulation time 63767753 ps
CPU time 0.76 seconds
Started Jul 25 06:22:42 PM PDT 24
Finished Jul 25 06:22:43 PM PDT 24
Peak memory 198148 kb
Host smart-68c3efe7-4aea-4499-908d-b3e62eb46145
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164774725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_
mubi.164774725
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.4013540873
Short name T275
Test name
Test status
Simulation time 35106110 ps
CPU time 0.64 seconds
Started Jul 25 06:22:43 PM PDT 24
Finished Jul 25 06:22:45 PM PDT 24
Peak memory 198552 kb
Host smart-4fefc2ad-c91b-4c3e-8816-c7c77a61ca67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013540873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.4013540873
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1372453654
Short name T52
Test name
Test status
Simulation time 42412281 ps
CPU time 0.62 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 198692 kb
Host smart-2f48affb-56ad-4195-806a-6f6c0632bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372453654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1372453654
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.120833014
Short name T169
Test name
Test status
Simulation time 60792822 ps
CPU time 0.74 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 199236 kb
Host smart-b7413232-ebdf-40a7-91a9-d1db7349ad21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120833014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.120833014
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3855757508
Short name T453
Test name
Test status
Simulation time 30104490 ps
CPU time 0.68 seconds
Started Jul 25 06:23:08 PM PDT 24
Finished Jul 25 06:23:09 PM PDT 24
Peak memory 198064 kb
Host smart-c491e8c8-a92e-48e6-a7a0-1e2a7c771470
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855757508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.3855757508
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.2657463789
Short name T349
Test name
Test status
Simulation time 165694846 ps
CPU time 0.99 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 198156 kb
Host smart-b2c639d6-65f2-438d-92c6-3a1218e74fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657463789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2657463789
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2729673411
Short name T610
Test name
Test status
Simulation time 36493720 ps
CPU time 0.63 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 198060 kb
Host smart-64b6fee1-531a-4104-a766-64da7602180e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729673411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2729673411
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2658503992
Short name T354
Test name
Test status
Simulation time 39786756 ps
CPU time 0.65 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 198140 kb
Host smart-2fc03de9-c82c-4f12-8e4f-30117daf5a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658503992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2658503992
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1746764667
Short name T562
Test name
Test status
Simulation time 51564611 ps
CPU time 0.67 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 201448 kb
Host smart-117395a3-cbe0-48f8-abd2-2c5af4372f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746764667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1746764667
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3907947783
Short name T534
Test name
Test status
Simulation time 52477103 ps
CPU time 0.68 seconds
Started Jul 25 06:23:03 PM PDT 24
Finished Jul 25 06:23:04 PM PDT 24
Peak memory 199160 kb
Host smart-b52d94bb-e5cb-447d-afb6-4f4272451fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907947783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3907947783
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1913238290
Short name T419
Test name
Test status
Simulation time 104483847 ps
CPU time 1.04 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 209576 kb
Host smart-296d8ceb-7c99-411f-98e4-8f0098fe72f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913238290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1913238290
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.849767259
Short name T583
Test name
Test status
Simulation time 72006177 ps
CPU time 0.7 seconds
Started Jul 25 06:23:08 PM PDT 24
Finished Jul 25 06:23:09 PM PDT 24
Peak memory 198124 kb
Host smart-4c8dd0df-cb4e-4756-9e47-926cb9f8525a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849767259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_
mubi.849767259
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1009040284
Short name T554
Test name
Test status
Simulation time 83225648 ps
CPU time 0.64 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 198572 kb
Host smart-e968ec22-6382-460b-94b9-3d17f3a45fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009040284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1009040284
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1864720039
Short name T112
Test name
Test status
Simulation time 49488075 ps
CPU time 0.67 seconds
Started Jul 25 06:23:04 PM PDT 24
Finished Jul 25 06:23:05 PM PDT 24
Peak memory 199252 kb
Host smart-3e10ad38-702c-45e6-b57e-25abc9e13038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864720039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1864720039
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1266106981
Short name T589
Test name
Test status
Simulation time 99511051 ps
CPU time 0.69 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 198468 kb
Host smart-8e4d673f-9c2e-4452-9a96-dbc77d1c26e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266106981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1266106981
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.773436488
Short name T147
Test name
Test status
Simulation time 29296320 ps
CPU time 0.68 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 198100 kb
Host smart-b738f778-a7c0-42c3-9f3d-5179306f45ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773436488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_
malfunc.773436488
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2201770537
Short name T271
Test name
Test status
Simulation time 587755609 ps
CPU time 0.98 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 198172 kb
Host smart-92676712-2003-4db0-be00-24d388688b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201770537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2201770537
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.1128592854
Short name T277
Test name
Test status
Simulation time 63185173 ps
CPU time 0.62 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 197464 kb
Host smart-7892b7bc-6ebc-41cf-ba45-683cda9d7f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128592854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.1128592854
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3963494187
Short name T1
Test name
Test status
Simulation time 32795772 ps
CPU time 0.6 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 198444 kb
Host smart-9e1268fd-d5b8-4630-99af-bd76d4fb993d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963494187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3963494187
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2079424701
Short name T626
Test name
Test status
Simulation time 48026707 ps
CPU time 0.71 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 201440 kb
Host smart-fb0975be-0e05-4456-8e06-a362cd8a5e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079424701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2079424701
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3012279645
Short name T333
Test name
Test status
Simulation time 42855796 ps
CPU time 0.76 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 199220 kb
Host smart-9e25b5fe-7811-4f16-804c-c3a2dbb24a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012279645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3012279645
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.321018991
Short name T600
Test name
Test status
Simulation time 168822445 ps
CPU time 0.82 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 209580 kb
Host smart-b6f511c5-4eda-4435-b6d1-59b09fa243c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321018991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.321018991
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1953699153
Short name T104
Test name
Test status
Simulation time 143742194 ps
CPU time 0.8 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 198156 kb
Host smart-c806bbc0-db62-418c-9095-6cbcfe798e51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953699153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1953699153
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.291016491
Short name T296
Test name
Test status
Simulation time 28583937 ps
CPU time 0.69 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 199404 kb
Host smart-6f9afbf3-ed2c-410b-82c2-cd7ced328a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291016491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.291016491
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.497794713
Short name T438
Test name
Test status
Simulation time 17590131 ps
CPU time 0.65 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 198624 kb
Host smart-0fa95197-c4dc-4627-bbc4-97a2457164c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497794713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.497794713
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3315648880
Short name T177
Test name
Test status
Simulation time 55097623 ps
CPU time 0.8 seconds
Started Jul 25 06:23:33 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 199212 kb
Host smart-f188d42f-f9b6-4d85-96bb-569956afc546
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315648880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3315648880
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.173967691
Short name T510
Test name
Test status
Simulation time 33137970 ps
CPU time 0.63 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 198104 kb
Host smart-b09c04c7-6efe-4c56-8f4e-bdad61fa167e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173967691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.173967691
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3528220688
Short name T103
Test name
Test status
Simulation time 304824165 ps
CPU time 0.95 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 198156 kb
Host smart-93ffe805-04ed-4a8b-b8ba-487613427044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528220688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3528220688
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.3413021765
Short name T573
Test name
Test status
Simulation time 58782884 ps
CPU time 0.64 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 198168 kb
Host smart-f9924dff-68c9-438a-b5da-e5abda8e39f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413021765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.3413021765
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.2149912656
Short name T527
Test name
Test status
Simulation time 77260487 ps
CPU time 0.61 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 198460 kb
Host smart-2044dc7d-27e8-41a0-be50-a49377795040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149912656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2149912656
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2315972121
Short name T471
Test name
Test status
Simulation time 127279267 ps
CPU time 0.73 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 201448 kb
Host smart-1370d27d-4206-4335-bcab-0d355b4875eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315972121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2315972121
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.4851370
Short name T380
Test name
Test status
Simulation time 52730677 ps
CPU time 0.67 seconds
Started Jul 25 06:23:05 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 198300 kb
Host smart-ed3187ee-811c-48e8-a5db-3855dc16dc21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4851370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.4851370
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.832290247
Short name T625
Test name
Test status
Simulation time 111377855 ps
CPU time 0.92 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 209580 kb
Host smart-c0371c02-07b1-4227-82ec-b481d4c4a4bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832290247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.832290247
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1995166057
Short name T547
Test name
Test status
Simulation time 87839442 ps
CPU time 0.72 seconds
Started Jul 25 06:23:07 PM PDT 24
Finished Jul 25 06:23:08 PM PDT 24
Peak memory 197868 kb
Host smart-492aef9e-f340-47e9-9d33-ccd6ec697339
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995166057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1995166057
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.2243963488
Short name T441
Test name
Test status
Simulation time 64998534 ps
CPU time 0.65 seconds
Started Jul 25 06:23:06 PM PDT 24
Finished Jul 25 06:23:07 PM PDT 24
Peak memory 199476 kb
Host smart-c3f0c434-1699-430a-b49c-ca613cadbf3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243963488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2243963488
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2774371906
Short name T544
Test name
Test status
Simulation time 118873796 ps
CPU time 0.87 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 200252 kb
Host smart-134da6fb-42d4-43ef-b068-8d862a3a553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774371906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2774371906
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1263576988
Short name T28
Test name
Test status
Simulation time 123703559 ps
CPU time 0.67 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 199204 kb
Host smart-82473aad-ec37-4baa-960a-499bcd62a581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263576988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1263576988
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.324687460
Short name T144
Test name
Test status
Simulation time 37407218 ps
CPU time 0.58 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:32 PM PDT 24
Peak memory 198056 kb
Host smart-00f7c664-eb71-4e96-b837-aae1ae53e8d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324687460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_
malfunc.324687460
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2666946304
Short name T9
Test name
Test status
Simulation time 315624961 ps
CPU time 0.93 seconds
Started Jul 25 06:23:33 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 198488 kb
Host smart-77d75872-9a96-4e12-ac1a-272cb7a4a742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666946304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2666946304
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.1151202403
Short name T228
Test name
Test status
Simulation time 56629916 ps
CPU time 0.62 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:33 PM PDT 24
Peak memory 197396 kb
Host smart-0f85eed1-d30d-4589-b155-5945392233db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151202403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.1151202403
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2340923559
Short name T310
Test name
Test status
Simulation time 50843475 ps
CPU time 0.69 seconds
Started Jul 25 06:23:33 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 198156 kb
Host smart-82fb7fc2-5159-4c3b-8b91-9e5fdd01d552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340923559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2340923559
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1483688531
Short name T191
Test name
Test status
Simulation time 45306193 ps
CPU time 0.79 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 201512 kb
Host smart-a24e74ca-f051-4b20-94c0-b49f41dd25ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483688531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1483688531
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1430851179
Short name T309
Test name
Test status
Simulation time 66359998 ps
CPU time 0.68 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 199224 kb
Host smart-8cd9691a-0cdd-4a8d-8f8b-4002baab4058
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430851179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1430851179
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.400362238
Short name T479
Test name
Test status
Simulation time 160905891 ps
CPU time 0.81 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 209568 kb
Host smart-f62509a9-902b-4e21-8fca-b0cce5acd35c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400362238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.400362238
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4123483638
Short name T439
Test name
Test status
Simulation time 61286261 ps
CPU time 0.82 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:33 PM PDT 24
Peak memory 198316 kb
Host smart-82292627-563f-4154-8db4-128eef66557e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123483638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4123483638
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3031991706
Short name T404
Test name
Test status
Simulation time 58879886 ps
CPU time 0.63 seconds
Started Jul 25 06:23:33 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 198576 kb
Host smart-a5ca2411-6469-427f-931c-fdf63d798c88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031991706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3031991706
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.287631163
Short name T331
Test name
Test status
Simulation time 47668956 ps
CPU time 0.87 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:39 PM PDT 24
Peak memory 200112 kb
Host smart-f7bffc4a-f9f1-446d-adab-c99aa6576e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287631163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.287631163
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2964264874
Short name T178
Test name
Test status
Simulation time 74510155 ps
CPU time 0.71 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 198572 kb
Host smart-b3cadf21-d772-40e8-b02c-5b6294e7264b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964264874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2964264874
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.273253153
Short name T301
Test name
Test status
Simulation time 32098819 ps
CPU time 0.6 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 198064 kb
Host smart-3eb8995f-fd03-4997-8dbf-8743e5f921cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273253153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.273253153
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.1762327920
Short name T443
Test name
Test status
Simulation time 165705591 ps
CPU time 1.03 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 198468 kb
Host smart-1c56482f-a055-4e0c-bb04-0ded50e2a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762327920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.1762327920
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2053387845
Short name T17
Test name
Test status
Simulation time 39312665 ps
CPU time 0.67 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 198184 kb
Host smart-74e51455-96af-4166-88af-bdffb4143e28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053387845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2053387845
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1721462414
Short name T586
Test name
Test status
Simulation time 96662885 ps
CPU time 0.61 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:33 PM PDT 24
Peak memory 198136 kb
Host smart-4f3d9556-ec93-4978-b8b7-c23c03cc8136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721462414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1721462414
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.4054446683
Short name T50
Test name
Test status
Simulation time 52324744 ps
CPU time 0.66 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 201480 kb
Host smart-ab24640a-2613-4146-b72c-ffb93aa0762e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054446683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.4054446683
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.263129227
Short name T497
Test name
Test status
Simulation time 195133651 ps
CPU time 0.76 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 198376 kb
Host smart-213cf70d-5581-4c6b-a256-a253c2aca171
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263129227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.263129227
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3041793920
Short name T367
Test name
Test status
Simulation time 118023906 ps
CPU time 0.91 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 209532 kb
Host smart-2bab0064-2a53-4abe-8238-165f1ffb3630
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041793920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3041793920
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2987251665
Short name T512
Test name
Test status
Simulation time 60548075 ps
CPU time 0.87 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 198256 kb
Host smart-1a30fe09-2fd8-4e49-b979-d9dcfbddb4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987251665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2987251665
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2070883735
Short name T614
Test name
Test status
Simulation time 26781533 ps
CPU time 0.69 seconds
Started Jul 25 06:23:35 PM PDT 24
Finished Jul 25 06:23:36 PM PDT 24
Peak memory 199436 kb
Host smart-9cfa2861-85d7-40b5-bff0-6286a6151875
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070883735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2070883735
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.1010242403
Short name T119
Test name
Test status
Simulation time 78536702 ps
CPU time 0.8 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:33 PM PDT 24
Peak memory 200144 kb
Host smart-351b88f0-09ea-4e7d-ba99-ee018253a81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010242403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1010242403
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2286018218
Short name T168
Test name
Test status
Simulation time 62333419 ps
CPU time 0.8 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 199144 kb
Host smart-8cc6cdc2-7b5f-4786-8ffc-3dcfeb4d04bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286018218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2286018218
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3613287547
Short name T590
Test name
Test status
Simulation time 29161863 ps
CPU time 0.62 seconds
Started Jul 25 06:23:35 PM PDT 24
Finished Jul 25 06:23:36 PM PDT 24
Peak memory 198064 kb
Host smart-f2cba636-d810-4182-ace1-0f7c4f4370b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613287547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3613287547
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1208592019
Short name T460
Test name
Test status
Simulation time 160662395 ps
CPU time 1.02 seconds
Started Jul 25 06:23:33 PM PDT 24
Finished Jul 25 06:23:34 PM PDT 24
Peak memory 198156 kb
Host smart-7cf12801-5ca4-462f-9857-7dc6ebc2c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208592019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1208592019
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2886531904
Short name T436
Test name
Test status
Simulation time 66709342 ps
CPU time 0.61 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:39 PM PDT 24
Peak memory 198164 kb
Host smart-8661e13b-0755-42bd-a5e7-95f3bd5acdc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886531904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2886531904
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1420581185
Short name T361
Test name
Test status
Simulation time 46737583 ps
CPU time 0.64 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:38 PM PDT 24
Peak memory 198176 kb
Host smart-0ac73c80-c17f-49fb-a033-24765a780544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420581185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1420581185
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3890130679
Short name T192
Test name
Test status
Simulation time 42353964 ps
CPU time 0.73 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 201472 kb
Host smart-892ed82e-0f51-49d7-ba4f-511efcd4630f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890130679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3890130679
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3517508043
Short name T45
Test name
Test status
Simulation time 75547698 ps
CPU time 0.75 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:33 PM PDT 24
Peak memory 199164 kb
Host smart-4009f04d-ea41-45da-a20a-ddad8fde7fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517508043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3517508043
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3220311075
Short name T587
Test name
Test status
Simulation time 112983012 ps
CPU time 0.91 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 209580 kb
Host smart-fb49eb1c-d4cb-4a0e-bf74-6bdbbfd510a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220311075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3220311075
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.4284071086
Short name T174
Test name
Test status
Simulation time 29265624 ps
CPU time 0.7 seconds
Started Jul 25 06:23:36 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 199188 kb
Host smart-00da8f50-c36c-4813-9908-dba7ee23a9da
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284071086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.4284071086
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2241359681
Short name T100
Test name
Test status
Simulation time 81393743 ps
CPU time 0.9 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:40 PM PDT 24
Peak memory 199276 kb
Host smart-27bf7c1f-e717-4f03-b7c5-8b10ab82a2e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241359681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2241359681
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3046990784
Short name T456
Test name
Test status
Simulation time 56220690 ps
CPU time 0.68 seconds
Started Jul 25 06:23:32 PM PDT 24
Finished Jul 25 06:23:32 PM PDT 24
Peak memory 199424 kb
Host smart-06530146-e53b-4af1-8e6a-861f3815435f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046990784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3046990784
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.271350220
Short name T485
Test name
Test status
Simulation time 47517291 ps
CPU time 0.61 seconds
Started Jul 25 06:23:38 PM PDT 24
Finished Jul 25 06:23:38 PM PDT 24
Peak memory 198672 kb
Host smart-90270a3d-3162-40ed-bc22-27d32f34b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271350220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.271350220
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2260714451
Short name T151
Test name
Test status
Simulation time 133855925 ps
CPU time 0.65 seconds
Started Jul 25 06:23:39 PM PDT 24
Finished Jul 25 06:23:40 PM PDT 24
Peak memory 198556 kb
Host smart-e77d0390-b29c-4491-862d-7f18e74b6187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260714451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.2260714451
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1255432763
Short name T535
Test name
Test status
Simulation time 29670232 ps
CPU time 0.65 seconds
Started Jul 25 06:23:37 PM PDT 24
Finished Jul 25 06:23:37 PM PDT 24
Peak memory 198112 kb
Host smart-35ab5f09-112e-4b23-a1e9-039ae4a5e559
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255432763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1255432763
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3176970033
Short name T513
Test name
Test status
Simulation time 598624692 ps
CPU time 0.98 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198156 kb
Host smart-a630b322-d8d6-468c-a3a6-d6ef290d76f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176970033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3176970033
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1488996832
Short name T582
Test name
Test status
Simulation time 45478198 ps
CPU time 0.68 seconds
Started Jul 25 06:23:39 PM PDT 24
Finished Jul 25 06:23:40 PM PDT 24
Peak memory 197448 kb
Host smart-43d30b9a-b67c-4ca6-860e-7e092bad14da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488996832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1488996832
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2557401240
Short name T545
Test name
Test status
Simulation time 227102316 ps
CPU time 0.62 seconds
Started Jul 25 06:23:39 PM PDT 24
Finished Jul 25 06:23:39 PM PDT 24
Peak memory 198148 kb
Host smart-fb1bb55b-362b-4caa-ba49-719e8d7129d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557401240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2557401240
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1453181887
Short name T203
Test name
Test status
Simulation time 51067550 ps
CPU time 0.69 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 201436 kb
Host smart-42461794-0c76-4965-a101-326efcd2327c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453181887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1453181887
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.404418865
Short name T267
Test name
Test status
Simulation time 58450043 ps
CPU time 0.64 seconds
Started Jul 25 06:23:35 PM PDT 24
Finished Jul 25 06:23:36 PM PDT 24
Peak memory 198224 kb
Host smart-531ed89f-ac38-4532-b737-abd1ad82ad3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404418865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.404418865
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2807097427
Short name T44
Test name
Test status
Simulation time 125942151 ps
CPU time 0.85 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 209520 kb
Host smart-8af362f8-efbb-41bc-8fd0-806b093bc469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807097427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2807097427
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.366209073
Short name T490
Test name
Test status
Simulation time 94446735 ps
CPU time 0.93 seconds
Started Jul 25 06:23:34 PM PDT 24
Finished Jul 25 06:23:35 PM PDT 24
Peak memory 199236 kb
Host smart-7074addb-b146-46ad-bb22-8a0846fac68c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366209073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.366209073
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.79353793
Short name T37
Test name
Test status
Simulation time 75400628 ps
CPU time 0.63 seconds
Started Jul 25 06:23:37 PM PDT 24
Finished Jul 25 06:23:38 PM PDT 24
Peak memory 198616 kb
Host smart-b61cdf52-9cb5-4c3d-9b9b-74edac363ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79353793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.79353793
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2702101205
Short name T394
Test name
Test status
Simulation time 61957854 ps
CPU time 0.89 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:43 PM PDT 24
Peak memory 200320 kb
Host smart-333ace21-847e-4973-b8e2-be1d5341c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702101205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2702101205
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.194117151
Short name T179
Test name
Test status
Simulation time 73347866 ps
CPU time 0.72 seconds
Started Jul 25 06:23:41 PM PDT 24
Finished Jul 25 06:23:42 PM PDT 24
Peak memory 198272 kb
Host smart-3420a356-64e8-4fab-978d-ef2f618803a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194117151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disa
ble_rom_integrity_check.194117151
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1459360930
Short name T465
Test name
Test status
Simulation time 38564135 ps
CPU time 0.6 seconds
Started Jul 25 06:23:40 PM PDT 24
Finished Jul 25 06:23:41 PM PDT 24
Peak memory 197352 kb
Host smart-d30481c2-4ba7-45f1-8917-75f6325ebc32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459360930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1459360930
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.826243191
Short name T252
Test name
Test status
Simulation time 161433837 ps
CPU time 1.03 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198172 kb
Host smart-1b271461-23ac-4ebb-8a88-2a227fc16a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826243191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.826243191
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.502161647
Short name T322
Test name
Test status
Simulation time 40182935 ps
CPU time 0.59 seconds
Started Jul 25 06:23:41 PM PDT 24
Finished Jul 25 06:23:41 PM PDT 24
Peak memory 197448 kb
Host smart-1ae66a37-f683-493f-a569-6d78dbe762b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502161647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.502161647
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.135520693
Short name T418
Test name
Test status
Simulation time 42601575 ps
CPU time 0.64 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:43 PM PDT 24
Peak memory 198472 kb
Host smart-8db547d9-d282-4b24-ab5f-e303d6cf5853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135520693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.135520693
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3968359584
Short name T189
Test name
Test status
Simulation time 44909291 ps
CPU time 0.74 seconds
Started Jul 25 06:23:41 PM PDT 24
Finished Jul 25 06:23:42 PM PDT 24
Peak memory 201392 kb
Host smart-5e0b67f3-f82a-4ddf-a030-bddda1a8848e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968359584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3968359584
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2752707501
Short name T217
Test name
Test status
Simulation time 55638119 ps
CPU time 0.63 seconds
Started Jul 25 06:23:39 PM PDT 24
Finished Jul 25 06:23:39 PM PDT 24
Peak memory 198276 kb
Host smart-3961d23f-f871-464b-9c20-ea3d4b15789c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752707501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2752707501
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3273695567
Short name T350
Test name
Test status
Simulation time 107423366 ps
CPU time 0.75 seconds
Started Jul 25 06:23:40 PM PDT 24
Finished Jul 25 06:23:41 PM PDT 24
Peak memory 198564 kb
Host smart-800102d6-263e-47ee-84d8-c00a0468348f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273695567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3273695567
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3084335490
Short name T220
Test name
Test status
Simulation time 115255960 ps
CPU time 0.97 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:43 PM PDT 24
Peak memory 209568 kb
Host smart-18a84783-1b6c-46e3-9bfb-af76f524eb68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084335490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3084335490
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1625939979
Short name T507
Test name
Test status
Simulation time 66551169 ps
CPU time 0.93 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 199672 kb
Host smart-865d5748-cbb5-4ff4-914e-25a77d4262dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625939979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1625939979
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.729969966
Short name T225
Test name
Test status
Simulation time 30265905 ps
CPU time 0.66 seconds
Started Jul 25 06:23:44 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 198592 kb
Host smart-3ac16351-f86d-4187-b3b9-ed6f39a7741a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729969966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.729969966
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3720407606
Short name T109
Test name
Test status
Simulation time 32392361 ps
CPU time 0.83 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198908 kb
Host smart-c1e8d0f1-04bb-461f-ae3f-825fb4216e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720407606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3720407606
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2400458963
Short name T148
Test name
Test status
Simulation time 70022112 ps
CPU time 0.69 seconds
Started Jul 25 06:23:39 PM PDT 24
Finished Jul 25 06:23:40 PM PDT 24
Peak memory 198460 kb
Host smart-4c841c5e-5f0c-4b69-b75a-e247dc068dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400458963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2400458963
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3938323306
Short name T146
Test name
Test status
Simulation time 36852942 ps
CPU time 0.61 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198076 kb
Host smart-886fd12b-2946-4f8e-9278-3d3a48a3f9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938323306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3938323306
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1826913430
Short name T623
Test name
Test status
Simulation time 216177093 ps
CPU time 1 seconds
Started Jul 25 06:23:47 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 198160 kb
Host smart-1aeb442e-94e8-47b9-918e-dc526e1a0f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826913430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1826913430
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2425212787
Short name T259
Test name
Test status
Simulation time 36442694 ps
CPU time 0.62 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198064 kb
Host smart-95007c14-830c-412c-bb76-dba19617caf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425212787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2425212787
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2976715541
Short name T42
Test name
Test status
Simulation time 23593168 ps
CPU time 0.63 seconds
Started Jul 25 06:23:44 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198456 kb
Host smart-bfbe8784-f6e1-48dc-892d-c9c0a936b728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976715541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2976715541
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.671380600
Short name T341
Test name
Test status
Simulation time 29674394 ps
CPU time 0.67 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198364 kb
Host smart-34490a55-050f-4e13-be82-1a29fc3206dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671380600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.671380600
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2214982375
Short name T342
Test name
Test status
Simulation time 341526037 ps
CPU time 0.78 seconds
Started Jul 25 06:23:43 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 209524 kb
Host smart-7e8140c9-4f47-4aa2-9748-b6e199b6920a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214982375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2214982375
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1649145015
Short name T432
Test name
Test status
Simulation time 93027406 ps
CPU time 0.83 seconds
Started Jul 25 06:23:44 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 198232 kb
Host smart-6f16aa35-8000-4f75-8fb6-e55266575870
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649145015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1649145015
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1963914600
Short name T243
Test name
Test status
Simulation time 58097700 ps
CPU time 0.65 seconds
Started Jul 25 06:23:45 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 199416 kb
Host smart-32d64158-405a-42a5-a26b-8b252cd8b83d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963914600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1963914600
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3664110175
Short name T508
Test name
Test status
Simulation time 110506059 ps
CPU time 0.78 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 200108 kb
Host smart-06af41d7-ecb6-4e1b-b79a-1b4e5637fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664110175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3664110175
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.378690614
Short name T435
Test name
Test status
Simulation time 57117779 ps
CPU time 0.67 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 199136 kb
Host smart-72b85cd4-552a-49f6-966c-b9d6ad80ccfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378690614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.378690614
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2495147732
Short name T594
Test name
Test status
Simulation time 62574246 ps
CPU time 0.59 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 198100 kb
Host smart-e9dfe676-14cd-4d4a-86ac-a66e9f19f80c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495147732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2495147732
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.1945507744
Short name T401
Test name
Test status
Simulation time 1143438581 ps
CPU time 1.04 seconds
Started Jul 25 06:21:32 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 198164 kb
Host smart-a8c4363a-0968-4d2e-bf4f-7194ab08cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945507744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1945507744
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.2720182586
Short name T499
Test name
Test status
Simulation time 44339148 ps
CPU time 0.61 seconds
Started Jul 25 06:21:33 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 198176 kb
Host smart-477ccf65-e25b-425c-a6d8-a74705291fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720182586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2720182586
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3973248887
Short name T272
Test name
Test status
Simulation time 49851394 ps
CPU time 0.66 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198432 kb
Host smart-ff26b333-9e99-4097-9c67-fe09ec4dc4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973248887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3973248887
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.3192309803
Short name T213
Test name
Test status
Simulation time 56160849 ps
CPU time 0.69 seconds
Started Jul 25 06:21:29 PM PDT 24
Finished Jul 25 06:21:30 PM PDT 24
Peak memory 201412 kb
Host smart-a51732cf-05b6-4221-af42-a0669bf46d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192309803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.3192309803
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.86002058
Short name T227
Test name
Test status
Simulation time 76883691 ps
CPU time 0.69 seconds
Started Jul 25 06:21:32 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 198248 kb
Host smart-406e99f4-0a8e-4d66-9350-e7f1d53b7897
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86002058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.86002058
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.419221092
Short name T43
Test name
Test status
Simulation time 160567533 ps
CPU time 0.82 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 209544 kb
Host smart-b1b5898c-53b2-4057-ab33-ef9a93e251d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419221092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.419221092
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3675704961
Short name T20
Test name
Test status
Simulation time 709720633 ps
CPU time 2.14 seconds
Started Jul 25 06:21:29 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 218076 kb
Host smart-a91d5172-72cf-4d5a-b90a-b09b8ff8ea46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675704961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3675704961
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1371051993
Short name T258
Test name
Test status
Simulation time 65734315 ps
CPU time 0.76 seconds
Started Jul 25 06:21:29 PM PDT 24
Finished Jul 25 06:21:30 PM PDT 24
Peak memory 198164 kb
Host smart-ceef84f1-a742-4d69-9450-21e8130a5fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371051993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1371051993
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2642435976
Short name T392
Test name
Test status
Simulation time 53951479 ps
CPU time 0.66 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 198592 kb
Host smart-bb57f6cb-3abf-442a-9a0b-add292765a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642435976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2642435976
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2166175716
Short name T473
Test name
Test status
Simulation time 25838998 ps
CPU time 0.75 seconds
Started Jul 25 06:23:50 PM PDT 24
Finished Jul 25 06:23:51 PM PDT 24
Peak memory 198688 kb
Host smart-7632a6db-b78a-452e-85a5-b3099a7c2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166175716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2166175716
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3598541675
Short name T25
Test name
Test status
Simulation time 62390057 ps
CPU time 0.66 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 199168 kb
Host smart-7b399542-14f7-475a-a059-eaad08271c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598541675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3598541675
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.4141048793
Short name T446
Test name
Test status
Simulation time 37948622 ps
CPU time 0.6 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198116 kb
Host smart-fa815518-a6f9-4d69-8291-9c9e9270226c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141048793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.4141048793
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3767859845
Short name T491
Test name
Test status
Simulation time 168312511 ps
CPU time 0.99 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 198184 kb
Host smart-519eef52-bf74-4e15-bcb3-520d971e3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767859845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3767859845
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.4029351879
Short name T556
Test name
Test status
Simulation time 42187609 ps
CPU time 0.67 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 198064 kb
Host smart-5875c4e5-fc3b-453a-9407-6085c180ef34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029351879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.4029351879
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.1533923644
Short name T619
Test name
Test status
Simulation time 40884095 ps
CPU time 0.63 seconds
Started Jul 25 06:23:45 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 198412 kb
Host smart-beaee535-da60-4ee5-8d37-86e1f6b7d20f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533923644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1533923644
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.102098785
Short name T202
Test name
Test status
Simulation time 41565230 ps
CPU time 0.74 seconds
Started Jul 25 06:23:41 PM PDT 24
Finished Jul 25 06:23:41 PM PDT 24
Peak memory 201380 kb
Host smart-2281d776-bea7-4501-8f1f-0ac23f761025
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102098785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali
d.102098785
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.855804661
Short name T386
Test name
Test status
Simulation time 74168314 ps
CPU time 0.88 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198496 kb
Host smart-a266b307-25cc-421f-bee5-55cdf6f8e4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855804661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.855804661
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2655904891
Short name T427
Test name
Test status
Simulation time 119724532 ps
CPU time 0.91 seconds
Started Jul 25 06:23:44 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 209476 kb
Host smart-8f486195-01f8-4085-8f87-b089bd92ae20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655904891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2655904891
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2410639354
Short name T317
Test name
Test status
Simulation time 52912062 ps
CPU time 0.79 seconds
Started Jul 25 06:23:41 PM PDT 24
Finished Jul 25 06:23:42 PM PDT 24
Peak memory 198196 kb
Host smart-e46e274f-19b0-4b57-87b1-a94e87e088fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410639354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2410639354
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3392777132
Short name T399
Test name
Test status
Simulation time 80314747 ps
CPU time 0.63 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198564 kb
Host smart-f2c66883-3e63-4d8d-b9c0-bcc4f3015609
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392777132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3392777132
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.859038333
Short name T38
Test name
Test status
Simulation time 43906852 ps
CPU time 0.66 seconds
Started Jul 25 06:23:44 PM PDT 24
Finished Jul 25 06:23:45 PM PDT 24
Peak memory 198320 kb
Host smart-9a7c3283-9f3a-4211-a66e-b7e28787cf64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859038333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.859038333
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3757128447
Short name T308
Test name
Test status
Simulation time 17964247 ps
CPU time 0.64 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198536 kb
Host smart-40f2ccf4-bdd5-4f82-b089-831834357035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757128447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3757128447
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1881527569
Short name T154
Test name
Test status
Simulation time 68907925 ps
CPU time 0.84 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 199124 kb
Host smart-c5f15b4b-58ab-4cad-9a87-a17506c43d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881527569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1881527569
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3628858549
Short name T455
Test name
Test status
Simulation time 31844195 ps
CPU time 0.64 seconds
Started Jul 25 06:23:42 PM PDT 24
Finished Jul 25 06:23:44 PM PDT 24
Peak memory 198072 kb
Host smart-c33a4851-767e-4d9f-bcdf-87bcdc0a139b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628858549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.3628858549
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1555397164
Short name T328
Test name
Test status
Simulation time 621216513 ps
CPU time 0.95 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198160 kb
Host smart-9ca19d0c-8552-4d98-b6c6-b2093d68c487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555397164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1555397164
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3933632226
Short name T462
Test name
Test status
Simulation time 33914026 ps
CPU time 0.65 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 198120 kb
Host smart-f485be50-5f6f-4732-8661-46e1af62509b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933632226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3933632226
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1390378534
Short name T564
Test name
Test status
Simulation time 237104222 ps
CPU time 0.63 seconds
Started Jul 25 06:23:47 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 198184 kb
Host smart-3b94ca62-7fa2-46e9-8e34-a6a01d1aa69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390378534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1390378534
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3019135118
Short name T568
Test name
Test status
Simulation time 44130727 ps
CPU time 0.77 seconds
Started Jul 25 06:23:49 PM PDT 24
Finished Jul 25 06:23:50 PM PDT 24
Peak memory 198512 kb
Host smart-fb50d38f-57f5-46ca-8171-4d9830c24b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019135118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3019135118
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1565972980
Short name T237
Test name
Test status
Simulation time 109963501 ps
CPU time 0.96 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 209552 kb
Host smart-b74d1e24-287f-40ea-956d-d248f56c3513
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565972980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1565972980
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2044255750
Short name T36
Test name
Test status
Simulation time 59915426 ps
CPU time 0.86 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 198284 kb
Host smart-0ed2f016-7334-4a68-a75e-f2783375b0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044255750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2044255750
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.1501217034
Short name T245
Test name
Test status
Simulation time 57589350 ps
CPU time 0.63 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 199348 kb
Host smart-92a9f965-0462-4213-94fa-18fe6f518f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501217034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1501217034
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.1565866912
Short name T387
Test name
Test status
Simulation time 47288406 ps
CPU time 0.72 seconds
Started Jul 25 06:23:47 PM PDT 24
Finished Jul 25 06:23:48 PM PDT 24
Peak memory 199200 kb
Host smart-c9e1fabb-b149-420d-bfd1-e263d18f8621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565866912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1565866912
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2264692137
Short name T363
Test name
Test status
Simulation time 88825023 ps
CPU time 0.67 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:46 PM PDT 24
Peak memory 198520 kb
Host smart-93cf046c-90e8-4c32-8797-66a753156b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264692137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.2264692137
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2305830624
Short name T279
Test name
Test status
Simulation time 39887883 ps
CPU time 0.62 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 198024 kb
Host smart-60a6c6f0-e651-4a39-b0ee-5adccaef6524
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305830624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2305830624
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.1817734966
Short name T2
Test name
Test status
Simulation time 156946769 ps
CPU time 1.01 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 198188 kb
Host smart-d43ca419-9de1-47d8-a99e-a72180f085af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817734966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1817734966
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.2956486425
Short name T241
Test name
Test status
Simulation time 23446566 ps
CPU time 0.64 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 197444 kb
Host smart-a2c4e866-6e28-4dea-8b19-fd0dab4f8d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956486425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2956486425
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.698769445
Short name T607
Test name
Test status
Simulation time 221454758 ps
CPU time 0.62 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 198412 kb
Host smart-3f2bf8f9-678d-419e-8c38-d455d5f4958f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698769445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.698769445
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.59836565
Short name T256
Test name
Test status
Simulation time 89851096 ps
CPU time 0.71 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 198400 kb
Host smart-a56904ba-fd79-47f9-b89c-7024ed6857f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59836565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.59836565
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.525359803
Short name T592
Test name
Test status
Simulation time 104930073 ps
CPU time 1.06 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 209540 kb
Host smart-942ad0f5-cbe5-463f-b2f9-1d65c2a4ff7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525359803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.525359803
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.1199274434
Short name T248
Test name
Test status
Simulation time 70019257 ps
CPU time 0.93 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 199216 kb
Host smart-2383d131-8246-409b-80e8-70de57b3aa52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199274434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1199274434
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2401725603
Short name T538
Test name
Test status
Simulation time 28874709 ps
CPU time 0.69 seconds
Started Jul 25 06:23:46 PM PDT 24
Finished Jul 25 06:23:47 PM PDT 24
Peak memory 199396 kb
Host smart-b541e015-140f-45ae-9a48-fd3a7764eb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401725603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2401725603
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.3530059488
Short name T340
Test name
Test status
Simulation time 18917721 ps
CPU time 0.69 seconds
Started Jul 25 06:24:00 PM PDT 24
Finished Jul 25 06:24:01 PM PDT 24
Peak memory 198640 kb
Host smart-9127e344-29bf-46b0-b940-083cc4a5cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530059488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3530059488
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3065118888
Short name T155
Test name
Test status
Simulation time 78139874 ps
CPU time 0.72 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:57 PM PDT 24
Peak memory 199184 kb
Host smart-75115f06-73b9-4c73-84f2-394756f87678
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065118888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3065118888
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1773419345
Short name T297
Test name
Test status
Simulation time 57683016 ps
CPU time 0.6 seconds
Started Jul 25 06:24:01 PM PDT 24
Finished Jul 25 06:24:01 PM PDT 24
Peak memory 197364 kb
Host smart-1360d042-5498-4431-884e-f39c18eea98f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773419345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.1773419345
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.745672043
Short name T553
Test name
Test status
Simulation time 165227065 ps
CPU time 1.02 seconds
Started Jul 25 06:23:58 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198180 kb
Host smart-930d2ec9-474c-4726-a754-36b1ce484fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745672043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.745672043
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.240470148
Short name T569
Test name
Test status
Simulation time 39951620 ps
CPU time 0.65 seconds
Started Jul 25 06:24:00 PM PDT 24
Finished Jul 25 06:24:01 PM PDT 24
Peak memory 197432 kb
Host smart-00ff2f99-cba0-429a-b5a2-570ecf341969
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240470148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.240470148
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.2154233704
Short name T321
Test name
Test status
Simulation time 48118478 ps
CPU time 0.62 seconds
Started Jul 25 06:24:08 PM PDT 24
Finished Jul 25 06:24:09 PM PDT 24
Peak memory 198124 kb
Host smart-284c4aaa-7390-4f49-ab51-c84ea16e3987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154233704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2154233704
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.2546053622
Short name T516
Test name
Test status
Simulation time 165669323 ps
CPU time 0.68 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 201468 kb
Host smart-fc73e9d4-2397-42ce-a51e-069f479e3d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546053622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.2546053622
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.97149687
Short name T222
Test name
Test status
Simulation time 32963138 ps
CPU time 0.63 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198144 kb
Host smart-255a0d8c-4c08-4c43-95fd-be7f290dc94b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97149687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.97149687
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2010487260
Short name T313
Test name
Test status
Simulation time 129571347 ps
CPU time 0.81 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 209560 kb
Host smart-15db9f06-e180-4d01-9051-90cae6d01c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010487260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2010487260
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3417651860
Short name T377
Test name
Test status
Simulation time 53140826 ps
CPU time 0.85 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:01 PM PDT 24
Peak memory 198240 kb
Host smart-60fe15de-ac65-4ff9-abae-b8733c5e5905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417651860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3417651860
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.1981388605
Short name T581
Test name
Test status
Simulation time 71609406 ps
CPU time 0.62 seconds
Started Jul 25 06:23:58 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 198560 kb
Host smart-1196060c-479d-472b-97e0-75d2f84549ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981388605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1981388605
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1668604858
Short name T49
Test name
Test status
Simulation time 45469849 ps
CPU time 0.64 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:57 PM PDT 24
Peak memory 198672 kb
Host smart-3c1e5ebd-f2c1-414b-bb85-b885d33a77ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668604858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1668604858
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1384677850
Short name T343
Test name
Test status
Simulation time 59622342 ps
CPU time 0.8 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 199104 kb
Host smart-940073dd-3ea0-4b96-a235-c83476f0155b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384677850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1384677850
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1196891225
Short name T522
Test name
Test status
Simulation time 29424986 ps
CPU time 0.66 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 197444 kb
Host smart-87aa6b64-f2bb-4f77-900e-56997196eb37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196891225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1196891225
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2097558531
Short name T451
Test name
Test status
Simulation time 692183135 ps
CPU time 1.03 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:09 PM PDT 24
Peak memory 198164 kb
Host smart-903c21ef-afe0-4d45-9d1b-66f2fcfac1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097558531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2097558531
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.4168096252
Short name T291
Test name
Test status
Simulation time 167603515 ps
CPU time 0.6 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:57 PM PDT 24
Peak memory 198116 kb
Host smart-674509d2-1a43-4f95-bfb1-4dbb73b0a991
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168096252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.4168096252
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2052218351
Short name T521
Test name
Test status
Simulation time 37334069 ps
CPU time 0.63 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198156 kb
Host smart-0963d51e-246e-489a-ad50-b8d566af1918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052218351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2052218351
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.1411944578
Short name T214
Test name
Test status
Simulation time 45598381 ps
CPU time 0.72 seconds
Started Jul 25 06:23:57 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 201472 kb
Host smart-ab79d8ca-6807-488e-bbcc-d972de5e434b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411944578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.1411944578
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.2015982681
Short name T324
Test name
Test status
Simulation time 48240848 ps
CPU time 0.7 seconds
Started Jul 25 06:23:58 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 199228 kb
Host smart-48c50e9a-870a-4b63-a026-7ce1bc60d523
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015982681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2015982681
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1273124428
Short name T287
Test name
Test status
Simulation time 109250743 ps
CPU time 0.92 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:58 PM PDT 24
Peak memory 209508 kb
Host smart-9c0df7e8-912c-4208-8693-463c3fc8fab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273124428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1273124428
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.959343046
Short name T221
Test name
Test status
Simulation time 112945628 ps
CPU time 0.81 seconds
Started Jul 25 06:23:58 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 199176 kb
Host smart-694fd179-381c-4cd4-b23a-5a0ec9f6ad9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959343046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_
mubi.959343046
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.42266364
Short name T229
Test name
Test status
Simulation time 57067489 ps
CPU time 0.64 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198584 kb
Host smart-03050481-fada-4806-8e37-bb6a22943909
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42266364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.42266364
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.192006665
Short name T406
Test name
Test status
Simulation time 25986416 ps
CPU time 0.74 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:57 PM PDT 24
Peak memory 198796 kb
Host smart-329f773b-1795-4109-8d02-fff88d1afb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192006665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.192006665
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1278206702
Short name T593
Test name
Test status
Simulation time 46698054 ps
CPU time 0.74 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198536 kb
Host smart-c501beda-2ef6-4df6-ba56-a7e90b1c6da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278206702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1278206702
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1014166989
Short name T315
Test name
Test status
Simulation time 39707734 ps
CPU time 0.6 seconds
Started Jul 25 06:24:00 PM PDT 24
Finished Jul 25 06:24:00 PM PDT 24
Peak memory 198064 kb
Host smart-3fb817b7-c149-4f75-96fa-abfbfd26c035
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014166989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.1014166989
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2806211304
Short name T270
Test name
Test status
Simulation time 319593965 ps
CPU time 1.03 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 198168 kb
Host smart-244132dd-57e3-4db9-bb29-b598e78aab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806211304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2806211304
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1165653677
Short name T306
Test name
Test status
Simulation time 69138327 ps
CPU time 0.63 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 198180 kb
Host smart-ddfaa587-8ead-4397-ac2e-ac6bafed3f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165653677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1165653677
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3755894401
Short name T283
Test name
Test status
Simulation time 50861231 ps
CPU time 0.65 seconds
Started Jul 25 06:23:58 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 198156 kb
Host smart-c46bf3bd-6ee5-45f1-b310-ccdc167700ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755894401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3755894401
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3497206914
Short name T196
Test name
Test status
Simulation time 73976406 ps
CPU time 0.7 seconds
Started Jul 25 06:24:05 PM PDT 24
Finished Jul 25 06:24:05 PM PDT 24
Peak memory 201416 kb
Host smart-b21c538c-ba24-4e70-a309-068fe20bc5cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497206914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3497206914
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1353899808
Short name T431
Test name
Test status
Simulation time 49063688 ps
CPU time 0.72 seconds
Started Jul 25 06:23:59 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 199156 kb
Host smart-0e950eab-6407-461a-b0f9-2e034315cdb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353899808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1353899808
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.3486174547
Short name T347
Test name
Test status
Simulation time 161319374 ps
CPU time 0.82 seconds
Started Jul 25 06:24:07 PM PDT 24
Finished Jul 25 06:24:08 PM PDT 24
Peak memory 209576 kb
Host smart-8c577bfe-1550-48b7-b982-d12d8fce9730
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486174547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3486174547
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3756216568
Short name T269
Test name
Test status
Simulation time 75189558 ps
CPU time 0.74 seconds
Started Jul 25 06:23:56 PM PDT 24
Finished Jul 25 06:23:57 PM PDT 24
Peak memory 197920 kb
Host smart-5cb056a4-6d5d-402a-b45f-df0d01456151
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756216568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3756216568
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1430079890
Short name T357
Test name
Test status
Simulation time 33001365 ps
CPU time 0.7 seconds
Started Jul 25 06:24:00 PM PDT 24
Finished Jul 25 06:24:01 PM PDT 24
Peak memory 199432 kb
Host smart-2b8a6db4-f94c-4811-b67d-b470b98e5e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430079890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1430079890
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2417798840
Short name T576
Test name
Test status
Simulation time 71562439 ps
CPU time 0.65 seconds
Started Jul 25 06:24:22 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 198332 kb
Host smart-ea861f24-3001-41c4-a2ae-f23f6edd8c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417798840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2417798840
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1797008765
Short name T477
Test name
Test status
Simulation time 32823425 ps
CPU time 0.58 seconds
Started Jul 25 06:24:16 PM PDT 24
Finished Jul 25 06:24:17 PM PDT 24
Peak memory 198060 kb
Host smart-dc234dfa-fe84-4174-a501-ed3401862417
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797008765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.1797008765
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.963146259
Short name T478
Test name
Test status
Simulation time 311940254 ps
CPU time 0.96 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 198152 kb
Host smart-2f8e6060-6ded-431d-a016-ac494f5b927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963146259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.963146259
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.2021544432
Short name T368
Test name
Test status
Simulation time 82975917 ps
CPU time 0.62 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 197396 kb
Host smart-5a87ee31-2412-44d8-8d49-79e4750baca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021544432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2021544432
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2030181332
Short name T255
Test name
Test status
Simulation time 71288650 ps
CPU time 0.59 seconds
Started Jul 25 06:24:17 PM PDT 24
Finished Jul 25 06:24:17 PM PDT 24
Peak memory 198492 kb
Host smart-51d46ce6-413c-4d85-ac3a-d07c5e096ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030181332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2030181332
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.83260314
Short name T268
Test name
Test status
Simulation time 160672363 ps
CPU time 0.75 seconds
Started Jul 25 06:24:06 PM PDT 24
Finished Jul 25 06:24:07 PM PDT 24
Peak memory 198420 kb
Host smart-bbf69e4b-3694-45d4-ad43-5703317a4d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83260314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.83260314
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.989890987
Short name T374
Test name
Test status
Simulation time 319232883 ps
CPU time 0.78 seconds
Started Jul 25 06:24:19 PM PDT 24
Finished Jul 25 06:24:20 PM PDT 24
Peak memory 209600 kb
Host smart-08cedb17-a1b6-47c2-8949-959adaf58b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989890987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.989890987
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1426224934
Short name T338
Test name
Test status
Simulation time 87095605 ps
CPU time 0.72 seconds
Started Jul 25 06:24:16 PM PDT 24
Finished Jul 25 06:24:17 PM PDT 24
Peak memory 198268 kb
Host smart-439f535e-d4af-4a76-a0b5-e73acce62ec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426224934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1426224934
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2071537735
Short name T437
Test name
Test status
Simulation time 54827511 ps
CPU time 0.64 seconds
Started Jul 25 06:24:06 PM PDT 24
Finished Jul 25 06:24:07 PM PDT 24
Peak memory 199424 kb
Host smart-6c35a240-6e2e-4cb9-a84a-70d6b9b3df43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071537735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2071537735
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.1581928266
Short name T620
Test name
Test status
Simulation time 74104944 ps
CPU time 0.89 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 200744 kb
Host smart-51fad27d-e71f-4c71-b1d0-ecf9b57da6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581928266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1581928266
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3001841302
Short name T182
Test name
Test status
Simulation time 52596692 ps
CPU time 0.74 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 199264 kb
Host smart-34e8a7fe-4a05-40cc-a127-b66ec87cc241
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001841302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3001841302
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.377117082
Short name T395
Test name
Test status
Simulation time 44024289 ps
CPU time 0.6 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 197364 kb
Host smart-8b93c848-080f-4c3e-ac0f-5f567a39147a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377117082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.377117082
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1945247972
Short name T504
Test name
Test status
Simulation time 326536274 ps
CPU time 0.97 seconds
Started Jul 25 06:24:24 PM PDT 24
Finished Jul 25 06:24:25 PM PDT 24
Peak memory 198468 kb
Host smart-6558b0be-0dd3-4006-a5e4-57d9413bf04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945247972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1945247972
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3657619670
Short name T262
Test name
Test status
Simulation time 32935109 ps
CPU time 0.65 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 197436 kb
Host smart-ca28e72a-900a-436a-a2d1-490bd41b4d62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657619670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3657619670
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2059608498
Short name T440
Test name
Test status
Simulation time 59697739 ps
CPU time 0.61 seconds
Started Jul 25 06:24:24 PM PDT 24
Finished Jul 25 06:24:24 PM PDT 24
Peak memory 198120 kb
Host smart-b3078b69-521c-4232-8af2-a53915cc850d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059608498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2059608498
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.5778557
Short name T612
Test name
Test status
Simulation time 68279890 ps
CPU time 0.68 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 201444 kb
Host smart-96c41d74-cbbf-4839-99b0-1d2d98111979
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5778557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.5778557
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.726400625
Short name T531
Test name
Test status
Simulation time 154319078 ps
CPU time 0.69 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 198384 kb
Host smart-76715938-898f-432b-b820-df520eb7d090
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726400625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.726400625
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1321293230
Short name T532
Test name
Test status
Simulation time 99125157 ps
CPU time 0.93 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 209564 kb
Host smart-f07a94a3-03e1-4280-a598-a34db8d13fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321293230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1321293230
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1531134472
Short name T584
Test name
Test status
Simulation time 127748080 ps
CPU time 0.88 seconds
Started Jul 25 06:24:19 PM PDT 24
Finished Jul 25 06:24:20 PM PDT 24
Peak memory 199252 kb
Host smart-81218db6-01ce-44c6-962d-b3f38107e324
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531134472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1531134472
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1351861238
Short name T30
Test name
Test status
Simulation time 30584077 ps
CPU time 0.7 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 198580 kb
Host smart-05e7c742-b05d-471d-b00d-0226c82d35da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351861238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1351861238
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.4217223145
Short name T572
Test name
Test status
Simulation time 19459017 ps
CPU time 0.69 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 199240 kb
Host smart-66c8bc68-8ad8-47ae-a4e2-f3b385abf877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217223145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.4217223145
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1929123585
Short name T390
Test name
Test status
Simulation time 41484706 ps
CPU time 0.58 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:20 PM PDT 24
Peak memory 198056 kb
Host smart-2de0a65d-6488-451a-ab97-5b9d24232b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929123585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1929123585
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.2866314695
Short name T312
Test name
Test status
Simulation time 609800786 ps
CPU time 1.01 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 198184 kb
Host smart-797167f0-2c37-4028-b242-d9ee27f98747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866314695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2866314695
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2206080381
Short name T316
Test name
Test status
Simulation time 42009825 ps
CPU time 0.62 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 197420 kb
Host smart-354f44d8-de52-4d11-914a-a652bf98f6cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206080381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2206080381
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2398901235
Short name T263
Test name
Test status
Simulation time 59959443 ps
CPU time 0.7 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 198128 kb
Host smart-86ce6e76-85c3-423e-b9d6-b8ff80c88825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398901235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2398901235
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2916300541
Short name T158
Test name
Test status
Simulation time 50611645 ps
CPU time 0.77 seconds
Started Jul 25 06:24:17 PM PDT 24
Finished Jul 25 06:24:18 PM PDT 24
Peak memory 198624 kb
Host smart-9c98a128-738a-4681-b226-d94d8badafb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916300541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.2916300541
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.2679199068
Short name T617
Test name
Test status
Simulation time 77316047 ps
CPU time 0.94 seconds
Started Jul 25 06:24:18 PM PDT 24
Finished Jul 25 06:24:19 PM PDT 24
Peak memory 198520 kb
Host smart-dc6fe953-8288-4d2c-97aa-4aa266a5f947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679199068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2679199068
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3342971908
Short name T12
Test name
Test status
Simulation time 28908076 ps
CPU time 0.65 seconds
Started Jul 25 06:24:18 PM PDT 24
Finished Jul 25 06:24:19 PM PDT 24
Peak memory 198660 kb
Host smart-0b00e33f-cf00-4712-bc18-22bdb3020894
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342971908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.3342971908
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2278492227
Short name T257
Test name
Test status
Simulation time 59388366 ps
CPU time 0.92 seconds
Started Jul 25 06:24:19 PM PDT 24
Finished Jul 25 06:24:20 PM PDT 24
Peak memory 199552 kb
Host smart-4b8814d8-c26c-4397-a45d-8bbadecd49dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278492227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2278492227
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.1468094998
Short name T468
Test name
Test status
Simulation time 39448262 ps
CPU time 0.69 seconds
Started Jul 25 06:24:19 PM PDT 24
Finished Jul 25 06:24:19 PM PDT 24
Peak memory 199424 kb
Host smart-302cbcca-9fee-4d29-9ee2-80f1ae5442e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468094998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1468094998
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.241319674
Short name T382
Test name
Test status
Simulation time 72961285 ps
CPU time 0.71 seconds
Started Jul 25 06:24:30 PM PDT 24
Finished Jul 25 06:24:31 PM PDT 24
Peak memory 198584 kb
Host smart-1533abb3-5b57-4e39-acfb-592235f53dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241319674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disa
ble_rom_integrity_check.241319674
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.349688259
Short name T330
Test name
Test status
Simulation time 31066900 ps
CPU time 0.65 seconds
Started Jul 25 06:24:23 PM PDT 24
Finished Jul 25 06:24:24 PM PDT 24
Peak memory 198072 kb
Host smart-2acbb5aa-d29a-49e3-a08e-9ede5832ca96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349688259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.349688259
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.471565423
Short name T348
Test name
Test status
Simulation time 165960048 ps
CPU time 0.96 seconds
Started Jul 25 06:24:22 PM PDT 24
Finished Jul 25 06:24:23 PM PDT 24
Peak memory 198180 kb
Host smart-f022d495-184a-439c-a1f8-fcac741490fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471565423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.471565423
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3424026898
Short name T35
Test name
Test status
Simulation time 35268591 ps
CPU time 0.64 seconds
Started Jul 25 06:24:29 PM PDT 24
Finished Jul 25 06:24:30 PM PDT 24
Peak memory 198048 kb
Host smart-ffc95546-940e-4079-8788-747393fb4568
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424026898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3424026898
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1818523851
Short name T224
Test name
Test status
Simulation time 38322568 ps
CPU time 0.61 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 198160 kb
Host smart-601179ae-f4bd-40f5-9ca0-077755a4752d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818523851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1818523851
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2513612067
Short name T482
Test name
Test status
Simulation time 153640349 ps
CPU time 0.69 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:31 PM PDT 24
Peak memory 201460 kb
Host smart-3e6bf9d6-18f6-45e7-8bee-c24352ff3e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513612067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2513612067
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.751324659
Short name T159
Test name
Test status
Simulation time 70011938 ps
CPU time 0.76 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:20 PM PDT 24
Peak memory 198632 kb
Host smart-2aa4d227-e491-4673-8e23-5230c711d464
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751324659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wa
keup_race.751324659
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1402200763
Short name T246
Test name
Test status
Simulation time 137467832 ps
CPU time 0.78 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 198504 kb
Host smart-e4bdaeb9-60c0-4176-9aa5-762d66cc876a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402200763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1402200763
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.3907940057
Short name T375
Test name
Test status
Simulation time 286679715 ps
CPU time 0.78 seconds
Started Jul 25 06:24:32 PM PDT 24
Finished Jul 25 06:24:33 PM PDT 24
Peak memory 209516 kb
Host smart-25b1080a-5994-4011-9943-853cd1eac254
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907940057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3907940057
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1887707589
Short name T57
Test name
Test status
Simulation time 43504364 ps
CPU time 0.64 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:21 PM PDT 24
Peak memory 198352 kb
Host smart-77e0b5f6-f4d4-4f5d-a3cf-586def54ecea
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887707589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.1887707589
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2334767435
Short name T403
Test name
Test status
Simulation time 60305212 ps
CPU time 0.82 seconds
Started Jul 25 06:24:21 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 198132 kb
Host smart-663e9f24-e652-4715-8a03-d8df3c450e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334767435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2334767435
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1115735293
Short name T503
Test name
Test status
Simulation time 33101116 ps
CPU time 0.71 seconds
Started Jul 25 06:24:20 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 199420 kb
Host smart-7ae61d83-16ee-48e5-b306-429da43e8d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115735293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1115735293
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.3212806020
Short name T59
Test name
Test status
Simulation time 93622287 ps
CPU time 0.8 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 200024 kb
Host smart-59854df4-99cf-46c4-8a82-183906e52fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212806020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.3212806020
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2469077392
Short name T108
Test name
Test status
Simulation time 47102496 ps
CPU time 0.78 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 199196 kb
Host smart-0e5934d7-318c-45b5-8610-c3fa498547ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469077392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.2469077392
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2409807633
Short name T423
Test name
Test status
Simulation time 32526630 ps
CPU time 0.63 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 198060 kb
Host smart-ccb02b22-0ade-4a05-8d95-e86c944a452a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409807633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.2409807633
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.534074845
Short name T11
Test name
Test status
Simulation time 305303167 ps
CPU time 0.96 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 198464 kb
Host smart-b21a498d-caa6-43f8-ac56-a30bbc876098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534074845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.534074845
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.1960050153
Short name T422
Test name
Test status
Simulation time 54902043 ps
CPU time 0.69 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198088 kb
Host smart-29fccfed-357d-44c8-9fbc-355cfe3de0bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960050153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.1960050153
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.385894150
Short name T546
Test name
Test status
Simulation time 52116905 ps
CPU time 0.59 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 198164 kb
Host smart-3ee95d01-fcf2-4404-808d-226a5c33feb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385894150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.385894150
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2214985349
Short name T464
Test name
Test status
Simulation time 42896833 ps
CPU time 0.71 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 201440 kb
Host smart-5b093de8-7864-4a82-8963-98fab9a3bf16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214985349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2214985349
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.413479812
Short name T385
Test name
Test status
Simulation time 77937762 ps
CPU time 0.7 seconds
Started Jul 25 06:21:32 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 198720 kb
Host smart-f06a6312-3ace-4b5b-a571-f0c2a8dd48fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413479812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.413479812
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1773510887
Short name T601
Test name
Test status
Simulation time 151604006 ps
CPU time 0.85 seconds
Started Jul 25 06:21:29 PM PDT 24
Finished Jul 25 06:21:30 PM PDT 24
Peak memory 209572 kb
Host smart-8e04526f-17ba-412f-ae90-7394cf7ac5b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773510887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1773510887
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.101262413
Short name T429
Test name
Test status
Simulation time 65049933 ps
CPU time 0.77 seconds
Started Jul 25 06:21:28 PM PDT 24
Finished Jul 25 06:21:29 PM PDT 24
Peak memory 198176 kb
Host smart-d6fa723b-9ccb-40f3-8aec-827a246dee98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101262413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.101262413
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2571741842
Short name T597
Test name
Test status
Simulation time 39488545 ps
CPU time 0.7 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 199420 kb
Host smart-46ad1300-0a2f-478f-9b56-8f1313bafc8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571741842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2571741842
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.308612684
Short name T526
Test name
Test status
Simulation time 232650622 ps
CPU time 0.72 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198732 kb
Host smart-52411005-c465-49c0-b062-d7ec3b55a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308612684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.308612684
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.4026791783
Short name T261
Test name
Test status
Simulation time 40788137 ps
CPU time 0.57 seconds
Started Jul 25 06:24:32 PM PDT 24
Finished Jul 25 06:24:33 PM PDT 24
Peak memory 197384 kb
Host smart-2c6168b1-234c-447f-9dc3-00e210710418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026791783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.4026791783
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3786870908
Short name T366
Test name
Test status
Simulation time 161320425 ps
CPU time 0.95 seconds
Started Jul 25 06:24:32 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198444 kb
Host smart-f9f345e7-7fb3-4237-a5f1-b230a03486ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786870908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3786870908
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.3287831403
Short name T481
Test name
Test status
Simulation time 62448612 ps
CPU time 0.73 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 198148 kb
Host smart-0250459c-b273-496b-8d5e-012b283e94d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287831403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3287831403
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.1663183890
Short name T327
Test name
Test status
Simulation time 110420950 ps
CPU time 0.62 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 198156 kb
Host smart-5cd679c4-ce32-4293-8363-d5f91f282c9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663183890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1663183890
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1009167139
Short name T218
Test name
Test status
Simulation time 55205762 ps
CPU time 0.69 seconds
Started Jul 25 06:24:30 PM PDT 24
Finished Jul 25 06:24:30 PM PDT 24
Peak memory 201412 kb
Host smart-fbda09c0-5298-4c4c-a045-234428b0d4be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009167139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1009167139
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.2469272905
Short name T320
Test name
Test status
Simulation time 29716640 ps
CPU time 0.74 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198704 kb
Host smart-1e6d7193-9805-4f25-922e-76df31f31070
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469272905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.2469272905
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3209839681
Short name T511
Test name
Test status
Simulation time 173571325 ps
CPU time 0.78 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 209540 kb
Host smart-105ce291-dbdd-4a3b-a24c-2798a7f9acca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209839681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3209839681
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1135172646
Short name T396
Test name
Test status
Simulation time 53971882 ps
CPU time 0.85 seconds
Started Jul 25 06:24:28 PM PDT 24
Finished Jul 25 06:24:29 PM PDT 24
Peak memory 199368 kb
Host smart-f0134411-8dff-4e4c-ba16-46e2b14d7b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135172646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1135172646
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2192464128
Short name T325
Test name
Test status
Simulation time 99165450 ps
CPU time 0.64 seconds
Started Jul 25 06:24:29 PM PDT 24
Finished Jul 25 06:24:30 PM PDT 24
Peak memory 198624 kb
Host smart-427ea184-9036-4ef5-b544-d3d783a81961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192464128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2192464128
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.3628139217
Short name T105
Test name
Test status
Simulation time 67372241 ps
CPU time 0.72 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 198496 kb
Host smart-8357c213-77cd-40b7-9cb0-219b4dd263ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628139217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3628139217
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.303271814
Short name T518
Test name
Test status
Simulation time 60478660 ps
CPU time 0.79 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 199136 kb
Host smart-73274348-db77-4ec9-bb52-846a74200450
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303271814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.303271814
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2847174451
Short name T373
Test name
Test status
Simulation time 37450180 ps
CPU time 0.59 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 197172 kb
Host smart-1362be87-2d15-4e27-ba5f-3a0dba94395f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847174451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2847174451
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.3658543161
Short name T360
Test name
Test status
Simulation time 308589172 ps
CPU time 0.94 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 198232 kb
Host smart-0c19a7f9-0d0d-4755-9a6c-e37cf0cf580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658543161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.3658543161
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3821073090
Short name T5
Test name
Test status
Simulation time 31461682 ps
CPU time 0.65 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 197960 kb
Host smart-d82b2f33-dcf7-439e-ba9c-52a8d98ef504
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821073090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3821073090
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.796046475
Short name T6
Test name
Test status
Simulation time 76071764 ps
CPU time 0.63 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198380 kb
Host smart-016f9312-671e-44c5-9b8d-06a03c005aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796046475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.796046475
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2511131875
Short name T209
Test name
Test status
Simulation time 80739983 ps
CPU time 0.68 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 201448 kb
Host smart-18e582d7-518f-4745-a0b3-841f4b6baade
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511131875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2511131875
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2188731442
Short name T372
Test name
Test status
Simulation time 96114209 ps
CPU time 0.72 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198416 kb
Host smart-91ed5fb5-e6cd-4b96-901d-be00542150f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188731442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2188731442
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.3837744138
Short name T442
Test name
Test status
Simulation time 156675860 ps
CPU time 0.79 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 209496 kb
Host smart-c02ef7ed-e96a-4964-b239-597ecb982508
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837744138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.3837744138
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.101621708
Short name T542
Test name
Test status
Simulation time 92929188 ps
CPU time 0.81 seconds
Started Jul 25 06:24:32 PM PDT 24
Finished Jul 25 06:24:33 PM PDT 24
Peak memory 199260 kb
Host smart-70521d22-0088-49a6-b738-8bef96ada357
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101621708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_
mubi.101621708
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3972410113
Short name T314
Test name
Test status
Simulation time 30971019 ps
CPU time 0.67 seconds
Started Jul 25 06:24:29 PM PDT 24
Finished Jul 25 06:24:30 PM PDT 24
Peak memory 198560 kb
Host smart-5c31cdae-c2ad-4c2c-8ae8-6fdf4fb74c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972410113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3972410113
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.349487544
Short name T215
Test name
Test status
Simulation time 110539038 ps
CPU time 0.83 seconds
Started Jul 25 06:24:38 PM PDT 24
Finished Jul 25 06:24:39 PM PDT 24
Peak memory 200020 kb
Host smart-5ea579e7-7626-4406-b2ae-17a7be1d971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349487544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.349487544
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1465594592
Short name T153
Test name
Test status
Simulation time 70552478 ps
CPU time 0.69 seconds
Started Jul 25 06:24:37 PM PDT 24
Finished Jul 25 06:24:38 PM PDT 24
Peak memory 198260 kb
Host smart-6c041ec1-c1b2-475a-a288-07df92da9ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465594592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.1465594592
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2705567676
Short name T365
Test name
Test status
Simulation time 31380060 ps
CPU time 0.61 seconds
Started Jul 25 06:24:36 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 197388 kb
Host smart-47668130-84fd-43be-99d0-6e61240408c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705567676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2705567676
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3536981120
Short name T506
Test name
Test status
Simulation time 158530711 ps
CPU time 1.01 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198184 kb
Host smart-fcfb8111-19f9-4409-9389-9097d605f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536981120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3536981120
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.461564053
Short name T474
Test name
Test status
Simulation time 48072426 ps
CPU time 0.6 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198084 kb
Host smart-c771fe58-c666-4589-9c6f-c20f3d1ff917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461564053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.461564053
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.3494378504
Short name T231
Test name
Test status
Simulation time 65870904 ps
CPU time 0.62 seconds
Started Jul 25 06:24:36 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 198116 kb
Host smart-7a7a80d5-7161-4698-b9cf-cd9ab1a1ca60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494378504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3494378504
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2119301554
Short name T469
Test name
Test status
Simulation time 74554091 ps
CPU time 0.69 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198480 kb
Host smart-053d8f66-4b60-47ed-b347-fa00a1dc8383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119301554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2119301554
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1033339336
Short name T286
Test name
Test status
Simulation time 109164212 ps
CPU time 0.97 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 209544 kb
Host smart-3e5e5a44-8755-425e-ba36-156edd7a28b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033339336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1033339336
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.237596388
Short name T99
Test name
Test status
Simulation time 50585741 ps
CPU time 0.9 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 199444 kb
Host smart-c1374165-a209-481d-9d22-2918111118ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237596388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.237596388
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.978701905
Short name T13
Test name
Test status
Simulation time 39951070 ps
CPU time 0.65 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198508 kb
Host smart-c95110b4-709a-48bb-8529-9c25c37b80ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978701905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.978701905
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3880538472
Short name T537
Test name
Test status
Simulation time 45482212 ps
CPU time 1.11 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 200484 kb
Host smart-c9f5ba92-3bbc-4730-9d23-52316bc8a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880538472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3880538472
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.487882220
Short name T150
Test name
Test status
Simulation time 57982768 ps
CPU time 0.84 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 198756 kb
Host smart-43e27465-2ebf-4afe-bdab-2375236b7d33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487882220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.487882220
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.462554586
Short name T484
Test name
Test status
Simulation time 37845990 ps
CPU time 0.56 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198040 kb
Host smart-2227d490-887a-4e38-8c65-a2589967ffee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462554586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.462554586
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3730517707
Short name T398
Test name
Test status
Simulation time 608741649 ps
CPU time 0.95 seconds
Started Jul 25 06:24:37 PM PDT 24
Finished Jul 25 06:24:38 PM PDT 24
Peak memory 198132 kb
Host smart-2759a0bf-7c95-434b-a139-ff6651cf548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730517707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3730517707
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.3114460740
Short name T543
Test name
Test status
Simulation time 49980239 ps
CPU time 0.68 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198132 kb
Host smart-a754feaa-5b55-4be6-8aa7-dc738e798ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114460740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3114460740
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.382413776
Short name T487
Test name
Test status
Simulation time 106169675 ps
CPU time 0.63 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198440 kb
Host smart-d9e25ed8-a568-47d8-a4cd-d60934870883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382413776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.382413776
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.1248393815
Short name T212
Test name
Test status
Simulation time 46050618 ps
CPU time 0.77 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 201484 kb
Host smart-6681b347-5ad5-45f7-aabc-0229e93ef907
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248393815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.1248393815
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.3642101707
Short name T298
Test name
Test status
Simulation time 32885966 ps
CPU time 0.67 seconds
Started Jul 25 06:24:38 PM PDT 24
Finished Jul 25 06:24:39 PM PDT 24
Peak memory 199208 kb
Host smart-5ee879b7-4984-486b-9437-e51666ee9191
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642101707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3642101707
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3404479370
Short name T260
Test name
Test status
Simulation time 119369688 ps
CPU time 0.85 seconds
Started Jul 25 06:24:31 PM PDT 24
Finished Jul 25 06:24:32 PM PDT 24
Peak memory 209656 kb
Host smart-de617bb8-3540-4d72-9e68-b2b9329044fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404479370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3404479370
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1040233218
Short name T336
Test name
Test status
Simulation time 113843343 ps
CPU time 0.79 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198272 kb
Host smart-708306e9-e974-496e-a8b7-9da3ca4dbf7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040233218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1040233218
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.3504695606
Short name T523
Test name
Test status
Simulation time 30340005 ps
CPU time 0.69 seconds
Started Jul 25 06:24:36 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 198580 kb
Host smart-1b799498-212d-4ce0-ba5a-b7311877b46a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504695606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3504695606
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2282010466
Short name T551
Test name
Test status
Simulation time 78619086 ps
CPU time 0.91 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 200780 kb
Host smart-d5dddfd2-898d-4c8d-8794-b68c28d8140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282010466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2282010466
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2092676218
Short name T416
Test name
Test status
Simulation time 110935822 ps
CPU time 0.68 seconds
Started Jul 25 06:24:41 PM PDT 24
Finished Jul 25 06:24:42 PM PDT 24
Peak memory 198320 kb
Host smart-1aa88f8c-edcf-4677-acfb-5e946fc8d76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092676218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2092676218
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3239944463
Short name T529
Test name
Test status
Simulation time 38372840 ps
CPU time 0.61 seconds
Started Jul 25 06:24:34 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 197364 kb
Host smart-af706903-1ffb-49b5-a665-798cf8f5a056
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239944463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.3239944463
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3674838766
Short name T457
Test name
Test status
Simulation time 625178568 ps
CPU time 1.02 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198468 kb
Host smart-6baff309-24c3-4d71-a57f-4f5dca4583e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674838766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3674838766
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.623040869
Short name T458
Test name
Test status
Simulation time 31236597 ps
CPU time 0.62 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 198164 kb
Host smart-02cb7e74-c448-415f-98a9-809c70216b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623040869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.623040869
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1329460211
Short name T605
Test name
Test status
Simulation time 21654752 ps
CPU time 0.61 seconds
Started Jul 25 06:24:35 PM PDT 24
Finished Jul 25 06:24:36 PM PDT 24
Peak memory 198148 kb
Host smart-48edffb8-94d9-4845-839a-817675f8be24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329460211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1329460211
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.523680641
Short name T466
Test name
Test status
Simulation time 60864725 ps
CPU time 0.7 seconds
Started Jul 25 06:24:42 PM PDT 24
Finished Jul 25 06:24:43 PM PDT 24
Peak memory 201456 kb
Host smart-f0d83e16-3525-47a4-a860-7bf6e3ba0734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523680641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali
d.523680641
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1245691573
Short name T110
Test name
Test status
Simulation time 41147581 ps
CPU time 0.74 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 199208 kb
Host smart-6cc3c740-c0f2-42fa-81d6-e82eba9dc775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245691573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1245691573
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3774514280
Short name T525
Test name
Test status
Simulation time 120534042 ps
CPU time 0.81 seconds
Started Jul 25 06:24:42 PM PDT 24
Finished Jul 25 06:24:43 PM PDT 24
Peak memory 209580 kb
Host smart-3a2b9cc6-f68f-4496-a65d-fdffc1d3ada3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774514280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3774514280
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.329980552
Short name T290
Test name
Test status
Simulation time 122315641 ps
CPU time 0.82 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:34 PM PDT 24
Peak memory 198992 kb
Host smart-af119ff9-dad1-4423-9e43-7c92bb597dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329980552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.329980552
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1732853907
Short name T397
Test name
Test status
Simulation time 103861940 ps
CPU time 0.67 seconds
Started Jul 25 06:24:33 PM PDT 24
Finished Jul 25 06:24:35 PM PDT 24
Peak memory 198448 kb
Host smart-c4e3ad28-8b81-4d25-b10e-b657d6cb8ccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732853907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1732853907
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.14817196
Short name T302
Test name
Test status
Simulation time 33961297 ps
CPU time 0.68 seconds
Started Jul 25 06:24:41 PM PDT 24
Finished Jul 25 06:24:42 PM PDT 24
Peak memory 198552 kb
Host smart-1a25d6d5-ba93-4623-95c6-839e356ecfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14817196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.14817196
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4188694934
Short name T571
Test name
Test status
Simulation time 60107268 ps
CPU time 0.78 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 199148 kb
Host smart-e70f55db-5415-4fd8-80d4-fe457605ce24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188694934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.4188694934
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2797949034
Short name T337
Test name
Test status
Simulation time 32950380 ps
CPU time 0.61 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 197416 kb
Host smart-3df646b0-46b6-43b5-88f0-1ed92c8002c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797949034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2797949034
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3282924129
Short name T567
Test name
Test status
Simulation time 2131083794 ps
CPU time 0.99 seconds
Started Jul 25 06:24:41 PM PDT 24
Finished Jul 25 06:24:42 PM PDT 24
Peak memory 198440 kb
Host smart-d0ecddf4-b0be-423b-a447-79279d025dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282924129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3282924129
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.520069922
Short name T459
Test name
Test status
Simulation time 45635713 ps
CPU time 0.67 seconds
Started Jul 25 06:24:39 PM PDT 24
Finished Jul 25 06:24:40 PM PDT 24
Peak memory 198180 kb
Host smart-01dc7edd-b160-47bd-b652-888e9229baf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520069922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.520069922
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1436511331
Short name T48
Test name
Test status
Simulation time 79309697 ps
CPU time 0.63 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 198152 kb
Host smart-5d4e6e42-ab41-4b2b-ab32-c83f28f81604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436511331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1436511331
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.4134401678
Short name T285
Test name
Test status
Simulation time 65385174 ps
CPU time 0.75 seconds
Started Jul 25 06:24:41 PM PDT 24
Finished Jul 25 06:24:42 PM PDT 24
Peak memory 199228 kb
Host smart-ccc02d13-39f1-4115-9487-bca94f6faa0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134401678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.4134401678
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3123203425
Short name T591
Test name
Test status
Simulation time 116037945 ps
CPU time 1.01 seconds
Started Jul 25 06:24:39 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 209536 kb
Host smart-c914734e-8005-48e1-9bf2-70dfa02a63d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123203425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3123203425
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1587984131
Short name T498
Test name
Test status
Simulation time 57875628 ps
CPU time 0.85 seconds
Started Jul 25 06:24:40 PM PDT 24
Finished Jul 25 06:24:41 PM PDT 24
Peak memory 197976 kb
Host smart-413e07ca-31be-43cf-824a-c23abcd9db2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587984131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1587984131
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1222338152
Short name T381
Test name
Test status
Simulation time 52771762 ps
CPU time 0.63 seconds
Started Jul 25 06:24:39 PM PDT 24
Finished Jul 25 06:24:40 PM PDT 24
Peak memory 198628 kb
Host smart-2ae0dcbe-5395-4c45-9fb5-5322affe6000
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222338152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1222338152
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.3023782229
Short name T40
Test name
Test status
Simulation time 65923752 ps
CPU time 0.63 seconds
Started Jul 25 06:24:50 PM PDT 24
Finished Jul 25 06:24:51 PM PDT 24
Peak memory 198664 kb
Host smart-6f46d659-1602-40e9-9bb5-d4f82ebe506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023782229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3023782229
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1826141692
Short name T624
Test name
Test status
Simulation time 29707153 ps
CPU time 0.64 seconds
Started Jul 25 06:24:47 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 198076 kb
Host smart-7833bc3a-2a73-4488-a653-63b3963251ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826141692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1826141692
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3805901115
Short name T519
Test name
Test status
Simulation time 1491071337 ps
CPU time 0.95 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:46 PM PDT 24
Peak memory 198156 kb
Host smart-16ab5217-8c65-4597-8d3e-9e668621b9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805901115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3805901115
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.322951963
Short name T235
Test name
Test status
Simulation time 241243404 ps
CPU time 0.63 seconds
Started Jul 25 06:24:46 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 198192 kb
Host smart-942c6007-3ada-4535-a919-46c433f6c9ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322951963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.322951963
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.3374853548
Short name T376
Test name
Test status
Simulation time 28889297 ps
CPU time 0.61 seconds
Started Jul 25 06:24:48 PM PDT 24
Finished Jul 25 06:24:49 PM PDT 24
Peak memory 198136 kb
Host smart-26c38ba2-72f2-44ff-8609-a23aca7f7053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374853548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3374853548
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1695271097
Short name T194
Test name
Test status
Simulation time 60679980 ps
CPU time 0.7 seconds
Started Jul 25 06:24:56 PM PDT 24
Finished Jul 25 06:24:57 PM PDT 24
Peak memory 201464 kb
Host smart-8024a625-0f52-462e-8502-6db8ba3e8aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695271097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1695271097
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3736073858
Short name T278
Test name
Test status
Simulation time 100284351 ps
CPU time 0.83 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:46 PM PDT 24
Peak memory 198496 kb
Host smart-ce90e269-9772-45dd-91b0-00dcd1db221d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736073858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3736073858
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1741458000
Short name T46
Test name
Test status
Simulation time 165834577 ps
CPU time 0.79 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:46 PM PDT 24
Peak memory 209620 kb
Host smart-28eac0d3-c8cb-4c0c-b048-be4e0a2023e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741458000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1741458000
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3457924267
Short name T281
Test name
Test status
Simulation time 69013964 ps
CPU time 0.9 seconds
Started Jul 25 06:24:48 PM PDT 24
Finished Jul 25 06:24:49 PM PDT 24
Peak memory 199272 kb
Host smart-13d0ac23-1e3c-4ae4-8f98-011fefcb4d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457924267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3457924267
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.1210954251
Short name T295
Test name
Test status
Simulation time 29801248 ps
CPU time 0.64 seconds
Started Jul 25 06:24:48 PM PDT 24
Finished Jul 25 06:24:49 PM PDT 24
Peak memory 198564 kb
Host smart-a0fe5566-9654-4940-9edf-f30022558705
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210954251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.1210954251
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.720893486
Short name T115
Test name
Test status
Simulation time 20574118 ps
CPU time 0.73 seconds
Started Jul 25 06:24:50 PM PDT 24
Finished Jul 25 06:24:51 PM PDT 24
Peak memory 199272 kb
Host smart-d9bfbf4a-0a9b-4e08-a888-b4dc5b83b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720893486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.720893486
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1083792631
Short name T496
Test name
Test status
Simulation time 60649724 ps
CPU time 0.75 seconds
Started Jul 25 06:24:56 PM PDT 24
Finished Jul 25 06:24:57 PM PDT 24
Peak memory 199228 kb
Host smart-cb7ffc23-9306-4870-bdc2-5863d437f226
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083792631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1083792631
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.734358768
Short name T242
Test name
Test status
Simulation time 41769245 ps
CPU time 0.6 seconds
Started Jul 25 06:24:44 PM PDT 24
Finished Jul 25 06:24:45 PM PDT 24
Peak memory 198080 kb
Host smart-39552fbf-b15b-4739-96d5-735b3aa2774f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734358768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.734358768
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2576518353
Short name T236
Test name
Test status
Simulation time 310496462 ps
CPU time 0.97 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:46 PM PDT 24
Peak memory 198196 kb
Host smart-355e1346-2a8b-45f5-bd54-c46ac175aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576518353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2576518353
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1092158365
Short name T517
Test name
Test status
Simulation time 48281057 ps
CPU time 0.67 seconds
Started Jul 25 06:24:56 PM PDT 24
Finished Jul 25 06:24:57 PM PDT 24
Peak memory 198104 kb
Host smart-9f21d648-fa2f-4afa-a2dc-82746159ecb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092158365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1092158365
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.29735437
Short name T428
Test name
Test status
Simulation time 38038757 ps
CPU time 0.69 seconds
Started Jul 25 06:24:50 PM PDT 24
Finished Jul 25 06:24:51 PM PDT 24
Peak memory 198196 kb
Host smart-6caf5195-ad2d-452f-bfa4-d409343bf906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29735437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.29735437
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.3488956345
Short name T106
Test name
Test status
Simulation time 136263277 ps
CPU time 0.7 seconds
Started Jul 25 06:24:44 PM PDT 24
Finished Jul 25 06:24:45 PM PDT 24
Peak memory 201416 kb
Host smart-ff335d05-751b-4daa-9da3-a82b68f78751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488956345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.3488956345
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.220671024
Short name T434
Test name
Test status
Simulation time 114737941 ps
CPU time 0.79 seconds
Started Jul 25 06:24:46 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 199164 kb
Host smart-d57abab1-c24a-48b8-80e3-b992d089dfce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220671024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.220671024
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1244894394
Short name T520
Test name
Test status
Simulation time 150922401 ps
CPU time 0.85 seconds
Started Jul 25 06:24:56 PM PDT 24
Finished Jul 25 06:24:57 PM PDT 24
Peak memory 209512 kb
Host smart-f685eaca-b1bf-4e3e-892a-9071975ea2bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244894394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1244894394
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1842845075
Short name T339
Test name
Test status
Simulation time 65542914 ps
CPU time 0.75 seconds
Started Jul 25 06:24:46 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 198224 kb
Host smart-1f6574f5-db84-4005-a9f7-0dc3c4ee5874
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842845075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1842845075
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.150014679
Short name T273
Test name
Test status
Simulation time 40290829 ps
CPU time 0.7 seconds
Started Jul 25 06:24:49 PM PDT 24
Finished Jul 25 06:24:49 PM PDT 24
Peak memory 198604 kb
Host smart-310ee634-1250-44a0-a762-937269e8e5cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150014679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.150014679
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1034804129
Short name T114
Test name
Test status
Simulation time 58464898 ps
CPU time 0.81 seconds
Started Jul 25 06:24:44 PM PDT 24
Finished Jul 25 06:24:45 PM PDT 24
Peak memory 200064 kb
Host smart-8190ffda-fd9f-40bc-a8ac-ddc72c48755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034804129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1034804129
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.3210469794
Short name T161
Test name
Test status
Simulation time 69614167 ps
CPU time 0.76 seconds
Started Jul 25 06:24:48 PM PDT 24
Finished Jul 25 06:24:49 PM PDT 24
Peak memory 198384 kb
Host smart-93df30c8-93be-45c1-84a8-9c1c831058ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210469794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.3210469794
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3271645950
Short name T307
Test name
Test status
Simulation time 30966329 ps
CPU time 0.62 seconds
Started Jul 25 06:24:44 PM PDT 24
Finished Jul 25 06:24:45 PM PDT 24
Peak memory 198136 kb
Host smart-a6687022-9125-42a5-bc9e-4630a55937ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271645950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.3271645950
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1348285858
Short name T232
Test name
Test status
Simulation time 628116800 ps
CPU time 0.98 seconds
Started Jul 25 06:24:52 PM PDT 24
Finished Jul 25 06:24:53 PM PDT 24
Peak memory 198464 kb
Host smart-39665e74-6a3d-47cf-9da8-bff35f42b590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348285858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1348285858
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1847056930
Short name T353
Test name
Test status
Simulation time 64031465 ps
CPU time 0.69 seconds
Started Jul 25 06:24:47 PM PDT 24
Finished Jul 25 06:24:48 PM PDT 24
Peak memory 198084 kb
Host smart-b30cab8a-d7f6-4fce-80c3-6bea0eab30b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847056930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1847056930
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3249030924
Short name T47
Test name
Test status
Simulation time 109641151 ps
CPU time 0.58 seconds
Started Jul 25 06:24:45 PM PDT 24
Finished Jul 25 06:24:45 PM PDT 24
Peak memory 198164 kb
Host smart-41c85bde-bc9c-4bb8-9759-19eeb79f476c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249030924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3249030924
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.4222291075
Short name T197
Test name
Test status
Simulation time 40651892 ps
CPU time 0.72 seconds
Started Jul 25 06:24:54 PM PDT 24
Finished Jul 25 06:24:55 PM PDT 24
Peak memory 201460 kb
Host smart-6b5c91c7-eee9-4ffb-bdfe-88919950097a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222291075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.4222291075
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3593440481
Short name T606
Test name
Test status
Simulation time 76195263 ps
CPU time 0.8 seconds
Started Jul 25 06:24:46 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 199220 kb
Host smart-3d79d0b1-17e1-4b3c-b5c7-30c0ed50976f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593440481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3593440481
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.456858256
Short name T559
Test name
Test status
Simulation time 106325503 ps
CPU time 0.91 seconds
Started Jul 25 06:24:54 PM PDT 24
Finished Jul 25 06:24:55 PM PDT 24
Peak memory 209504 kb
Host smart-7c1c3bfd-4782-4e40-a774-5a733e13a966
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456858256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.456858256
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.2714031581
Short name T53
Test name
Test status
Simulation time 41109055 ps
CPU time 0.73 seconds
Started Jul 25 06:24:52 PM PDT 24
Finished Jul 25 06:24:53 PM PDT 24
Peak memory 198672 kb
Host smart-5ec7ef25-6f11-4bde-bf0a-b4c600dc611a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714031581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.2714031581
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3229565116
Short name T433
Test name
Test status
Simulation time 61985996 ps
CPU time 0.77 seconds
Started Jul 25 06:24:53 PM PDT 24
Finished Jul 25 06:24:54 PM PDT 24
Peak memory 198268 kb
Host smart-b6b2de21-8d73-4b63-80a1-73e731feb1a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229565116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3229565116
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1438363463
Short name T405
Test name
Test status
Simulation time 73976545 ps
CPU time 0.72 seconds
Started Jul 25 06:25:05 PM PDT 24
Finished Jul 25 06:25:05 PM PDT 24
Peak memory 199028 kb
Host smart-99447306-4f71-4657-adcc-1075c81b274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438363463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1438363463
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3935563801
Short name T180
Test name
Test status
Simulation time 68667091 ps
CPU time 0.64 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 198360 kb
Host smart-62828dba-45b2-4131-bd9b-a4f2b4d401e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935563801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3935563801
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1720118079
Short name T557
Test name
Test status
Simulation time 38945867 ps
CPU time 0.65 seconds
Started Jul 25 06:24:57 PM PDT 24
Finished Jul 25 06:24:58 PM PDT 24
Peak memory 197412 kb
Host smart-3d484fd8-5487-4d7e-8d65-ba7df9ef9329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720118079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1720118079
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.844980320
Short name T463
Test name
Test status
Simulation time 37529509 ps
CPU time 0.63 seconds
Started Jul 25 06:25:12 PM PDT 24
Finished Jul 25 06:25:13 PM PDT 24
Peak memory 198116 kb
Host smart-b2fcfa89-7bd1-46f1-996b-85dc5df818b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844980320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.844980320
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3820177282
Short name T247
Test name
Test status
Simulation time 40828380 ps
CPU time 0.61 seconds
Started Jul 25 06:25:05 PM PDT 24
Finished Jul 25 06:25:06 PM PDT 24
Peak memory 198172 kb
Host smart-2a687d77-ea41-473e-8ba6-7028db91ce63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820177282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3820177282
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2931282368
Short name T412
Test name
Test status
Simulation time 44138099 ps
CPU time 0.76 seconds
Started Jul 25 06:24:55 PM PDT 24
Finished Jul 25 06:24:55 PM PDT 24
Peak memory 199172 kb
Host smart-86d98797-7af1-4020-882c-6c847e4786cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931282368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2931282368
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2139641676
Short name T598
Test name
Test status
Simulation time 206164110 ps
CPU time 0.83 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 209596 kb
Host smart-9d1f7dfd-a283-4faa-b4ac-310bf2aff321
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139641676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2139641676
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3129142576
Short name T70
Test name
Test status
Simulation time 58387781 ps
CPU time 0.86 seconds
Started Jul 25 06:24:58 PM PDT 24
Finished Jul 25 06:24:59 PM PDT 24
Peak memory 198084 kb
Host smart-a6c34264-29ab-41c4-bf45-04d7c9064c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129142576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3129142576
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2496675608
Short name T558
Test name
Test status
Simulation time 46508321 ps
CPU time 0.67 seconds
Started Jul 25 06:25:06 PM PDT 24
Finished Jul 25 06:25:06 PM PDT 24
Peak memory 198592 kb
Host smart-5028bb6e-c590-4e4f-a348-29e5f8e167b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496675608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2496675608
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3650739031
Short name T251
Test name
Test status
Simulation time 38898014 ps
CPU time 0.71 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198700 kb
Host smart-73c37aac-a38a-4b3f-90d0-59dc2ea7ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650739031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3650739031
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3983661782
Short name T561
Test name
Test status
Simulation time 52802029 ps
CPU time 0.82 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 199236 kb
Host smart-b9c0f3e1-b3c0-40ad-b5a6-076683fe34c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983661782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.3983661782
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1125974156
Short name T364
Test name
Test status
Simulation time 28915064 ps
CPU time 0.68 seconds
Started Jul 25 06:21:34 PM PDT 24
Finished Jul 25 06:21:35 PM PDT 24
Peak memory 197404 kb
Host smart-4008c02e-d0a6-401f-aa4e-74c68ed05c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125974156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1125974156
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2516174259
Short name T41
Test name
Test status
Simulation time 554790206 ps
CPU time 0.97 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198156 kb
Host smart-95a3172c-24ed-40d8-9d95-81a272f591bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516174259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2516174259
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.1410710944
Short name T548
Test name
Test status
Simulation time 42542787 ps
CPU time 0.68 seconds
Started Jul 25 06:21:33 PM PDT 24
Finished Jul 25 06:21:34 PM PDT 24
Peak memory 198188 kb
Host smart-26af6575-1a83-4635-a88e-0498277b825f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410710944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1410710944
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.4219015716
Short name T409
Test name
Test status
Simulation time 75254240 ps
CPU time 0.61 seconds
Started Jul 25 06:21:31 PM PDT 24
Finished Jul 25 06:21:32 PM PDT 24
Peak memory 198208 kb
Host smart-9f735d39-3476-4c71-8a7d-8ffcdec9c34c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219015716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.4219015716
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.4084900617
Short name T186
Test name
Test status
Simulation time 165887047 ps
CPU time 0.68 seconds
Started Jul 25 06:21:41 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 201428 kb
Host smart-6ea778eb-c2c9-429c-b0d6-f5f579708f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084900617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.4084900617
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2126046995
Short name T238
Test name
Test status
Simulation time 57189882 ps
CPU time 0.68 seconds
Started Jul 25 06:21:32 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 199224 kb
Host smart-38e3898f-c093-4bb2-9add-3be2f2d96b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126046995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2126046995
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1116531627
Short name T579
Test name
Test status
Simulation time 106252918 ps
CPU time 0.93 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:41 PM PDT 24
Peak memory 209544 kb
Host smart-0ebe6deb-935e-4c42-a8c3-4887ca733e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116531627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1116531627
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2164058779
Short name T530
Test name
Test status
Simulation time 65472930 ps
CPU time 0.93 seconds
Started Jul 25 06:21:32 PM PDT 24
Finished Jul 25 06:21:33 PM PDT 24
Peak memory 199132 kb
Host smart-cda46273-4599-419e-a30c-e88e96d9d33d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164058779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2164058779
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.231468628
Short name T332
Test name
Test status
Simulation time 30832999 ps
CPU time 0.7 seconds
Started Jul 25 06:21:30 PM PDT 24
Finished Jul 25 06:21:31 PM PDT 24
Peak memory 199392 kb
Host smart-8842a3b2-4e52-4a53-9cce-6ffda3b06b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231468628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.231468628
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3513187884
Short name T61
Test name
Test status
Simulation time 28993833 ps
CPU time 0.64 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:40 PM PDT 24
Peak memory 198640 kb
Host smart-d246857f-ad5d-40ef-9b43-b435381d98c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513187884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3513187884
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1103911830
Short name T536
Test name
Test status
Simulation time 62988849 ps
CPU time 0.81 seconds
Started Jul 25 06:21:44 PM PDT 24
Finished Jul 25 06:21:45 PM PDT 24
Peak memory 198588 kb
Host smart-6875a570-b9a4-45b2-a55c-159f4e199528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103911830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1103911830
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2675131927
Short name T555
Test name
Test status
Simulation time 40189629 ps
CPU time 0.57 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:41 PM PDT 24
Peak memory 198080 kb
Host smart-32682a0e-445f-4b61-9239-c97d9f48a1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675131927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2675131927
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.1789941030
Short name T616
Test name
Test status
Simulation time 754732426 ps
CPU time 1 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 198188 kb
Host smart-4de3242c-013f-46b0-be8b-f861f24e3c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789941030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1789941030
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.4099294926
Short name T335
Test name
Test status
Simulation time 39299901 ps
CPU time 0.65 seconds
Started Jul 25 06:21:41 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 197488 kb
Host smart-d17d4336-e491-4a39-a872-d768eb02116c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099294926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.4099294926
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1407271864
Short name T98
Test name
Test status
Simulation time 34600753 ps
CPU time 0.64 seconds
Started Jul 25 06:21:42 PM PDT 24
Finished Jul 25 06:21:43 PM PDT 24
Peak memory 198520 kb
Host smart-ac5675ca-c9fe-4860-a7ab-7c09c8f58f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407271864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1407271864
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1386055726
Short name T185
Test name
Test status
Simulation time 46343517 ps
CPU time 0.71 seconds
Started Jul 25 06:21:42 PM PDT 24
Finished Jul 25 06:21:43 PM PDT 24
Peak memory 201408 kb
Host smart-194908ea-7629-41fe-a4c3-4ff1612da012
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386055726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1386055726
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1608592810
Short name T300
Test name
Test status
Simulation time 54406518 ps
CPU time 0.85 seconds
Started Jul 25 06:21:47 PM PDT 24
Finished Jul 25 06:21:48 PM PDT 24
Peak memory 199144 kb
Host smart-8ddb6dde-d8aa-45e6-8693-5fd63bc1bc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608592810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1608592810
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.4050302046
Short name T622
Test name
Test status
Simulation time 109464061 ps
CPU time 1.13 seconds
Started Jul 25 06:21:39 PM PDT 24
Finished Jul 25 06:21:40 PM PDT 24
Peak memory 209532 kb
Host smart-2c6e3141-e8a8-40d1-a99d-9ed66681ad88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050302046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.4050302046
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1805204032
Short name T223
Test name
Test status
Simulation time 80584683 ps
CPU time 0.78 seconds
Started Jul 25 06:21:39 PM PDT 24
Finished Jul 25 06:21:40 PM PDT 24
Peak memory 199268 kb
Host smart-31a7d644-727b-4598-b617-cd91f0886698
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805204032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1805204032
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1328164324
Short name T58
Test name
Test status
Simulation time 32650619 ps
CPU time 0.68 seconds
Started Jul 25 06:21:41 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 199452 kb
Host smart-36491127-cf50-406d-a9ea-cb40c930c2fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328164324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1328164324
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1869619965
Short name T165
Test name
Test status
Simulation time 52630484 ps
CPU time 0.77 seconds
Started Jul 25 06:21:47 PM PDT 24
Finished Jul 25 06:21:48 PM PDT 24
Peak memory 199212 kb
Host smart-1a8945c5-3020-42f6-b565-5f669daf0839
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869619965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1869619965
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1800573876
Short name T293
Test name
Test status
Simulation time 29894056 ps
CPU time 0.64 seconds
Started Jul 25 06:21:42 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 198052 kb
Host smart-40e99085-7d05-41fc-b98d-a33ac24d5e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800573876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.1800573876
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.166629794
Short name T143
Test name
Test status
Simulation time 633348808 ps
CPU time 0.98 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:41 PM PDT 24
Peak memory 198176 kb
Host smart-d5d7a0ed-7668-4a10-b8eb-484ef302bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166629794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.166629794
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.215691432
Short name T578
Test name
Test status
Simulation time 63901366 ps
CPU time 0.63 seconds
Started Jul 25 06:21:52 PM PDT 24
Finished Jul 25 06:21:53 PM PDT 24
Peak memory 198208 kb
Host smart-45d469de-b9e3-4c35-88da-2a9ac5124360
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215691432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.215691432
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.3290689490
Short name T414
Test name
Test status
Simulation time 120717889 ps
CPU time 0.59 seconds
Started Jul 25 06:21:41 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 198204 kb
Host smart-2ef61d3e-7f81-4cf3-a72a-e301cf78b6ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290689490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3290689490
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3817578138
Short name T585
Test name
Test status
Simulation time 78882922 ps
CPU time 0.66 seconds
Started Jul 25 06:21:50 PM PDT 24
Finished Jul 25 06:21:51 PM PDT 24
Peak memory 201456 kb
Host smart-b091bc02-e864-4a13-a277-d402aaab3375
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817578138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3817578138
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.4069322247
Short name T574
Test name
Test status
Simulation time 69634437 ps
CPU time 0.75 seconds
Started Jul 25 06:21:43 PM PDT 24
Finished Jul 25 06:21:44 PM PDT 24
Peak memory 199192 kb
Host smart-b5ed4fe5-a2c8-4865-8190-de3ffd03c63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069322247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.4069322247
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2621009040
Short name T486
Test name
Test status
Simulation time 159992998 ps
CPU time 0.83 seconds
Started Jul 25 06:21:46 PM PDT 24
Finished Jul 25 06:21:47 PM PDT 24
Peak memory 209564 kb
Host smart-e3846ec2-5aad-4719-ac6f-42cdb6ff0c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621009040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2621009040
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.791015849
Short name T89
Test name
Test status
Simulation time 120327738 ps
CPU time 0.78 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:41 PM PDT 24
Peak memory 199416 kb
Host smart-67cbe1af-9d2a-4c96-8388-912952f4a018
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791015849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.791015849
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1711197202
Short name T344
Test name
Test status
Simulation time 28821206 ps
CPU time 0.65 seconds
Started Jul 25 06:21:40 PM PDT 24
Finished Jul 25 06:21:41 PM PDT 24
Peak memory 198560 kb
Host smart-e0b7752b-cf70-41f2-a406-88b649f2318d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711197202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1711197202
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1480727861
Short name T445
Test name
Test status
Simulation time 109035350 ps
CPU time 0.66 seconds
Started Jul 25 06:21:51 PM PDT 24
Finished Jul 25 06:21:52 PM PDT 24
Peak memory 198692 kb
Host smart-36f382f7-a652-45d1-8318-4806c10e0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480727861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1480727861
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1462500562
Short name T470
Test name
Test status
Simulation time 56365734 ps
CPU time 0.76 seconds
Started Jul 25 06:21:54 PM PDT 24
Finished Jul 25 06:21:55 PM PDT 24
Peak memory 199224 kb
Host smart-6d6f865f-03e2-488a-9883-508f4cf1aa21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462500562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1462500562
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.288269067
Short name T329
Test name
Test status
Simulation time 40208677 ps
CPU time 0.58 seconds
Started Jul 25 06:21:50 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 198096 kb
Host smart-30031499-33a0-436a-a249-6f111a0760ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288269067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m
alfunc.288269067
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3530162312
Short name T289
Test name
Test status
Simulation time 605102850 ps
CPU time 0.94 seconds
Started Jul 25 06:21:47 PM PDT 24
Finished Jul 25 06:21:48 PM PDT 24
Peak memory 198156 kb
Host smart-e74c7083-0f43-45a0-939a-0c5d490631fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530162312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3530162312
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3146940553
Short name T539
Test name
Test status
Simulation time 42575403 ps
CPU time 0.67 seconds
Started Jul 25 06:21:54 PM PDT 24
Finished Jul 25 06:21:55 PM PDT 24
Peak memory 197348 kb
Host smart-26d27da5-e521-4e3d-8f50-3cf7944de875
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146940553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3146940553
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.987877645
Short name T346
Test name
Test status
Simulation time 37101981 ps
CPU time 0.62 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 198164 kb
Host smart-ba1d6cc9-07e2-4b5f-9954-84d1d19ef34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987877645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.987877645
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1590169044
Short name T358
Test name
Test status
Simulation time 73184929 ps
CPU time 0.66 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 198128 kb
Host smart-3d201d28-3f91-4444-8084-b65f844c2ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590169044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1590169044
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.1811107471
Short name T609
Test name
Test status
Simulation time 102732859 ps
CPU time 0.94 seconds
Started Jul 25 06:21:52 PM PDT 24
Finished Jul 25 06:21:53 PM PDT 24
Peak memory 209592 kb
Host smart-b716991b-c0cf-463d-bc88-580e006e9017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811107471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.1811107471
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3137875596
Short name T378
Test name
Test status
Simulation time 186713687 ps
CPU time 0.72 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 198352 kb
Host smart-06b3b9c2-08a8-4251-8963-0bbd989e3bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137875596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3137875596
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.4091784993
Short name T93
Test name
Test status
Simulation time 42234307 ps
CPU time 0.65 seconds
Started Jul 25 06:21:54 PM PDT 24
Finished Jul 25 06:21:55 PM PDT 24
Peak memory 199416 kb
Host smart-c1119e95-31c8-4e93-aba2-553f522c9e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091784993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.4091784993
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.2808457392
Short name T334
Test name
Test status
Simulation time 70912969 ps
CPU time 0.63 seconds
Started Jul 25 06:21:54 PM PDT 24
Finished Jul 25 06:21:55 PM PDT 24
Peak memory 198600 kb
Host smart-d43aeb12-6b4c-4a1e-a9f0-ea7506b956f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808457392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.2808457392
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.937697998
Short name T118
Test name
Test status
Simulation time 34447448 ps
CPU time 0.79 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 199012 kb
Host smart-4c96c665-bb6f-43e3-a09b-d32b55ee0025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937697998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.937697998
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2745176542
Short name T388
Test name
Test status
Simulation time 54273113 ps
CPU time 0.69 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 198380 kb
Host smart-8bbdf269-b241-451e-a6ed-af1460670105
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745176542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2745176542
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3084643736
Short name T502
Test name
Test status
Simulation time 29084632 ps
CPU time 0.65 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 198076 kb
Host smart-f46a8de8-462d-462b-9610-2752eebcec9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084643736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3084643736
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.558864723
Short name T299
Test name
Test status
Simulation time 499035240 ps
CPU time 0.98 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 198432 kb
Host smart-285208cb-6877-48da-888e-3ce6752a9f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558864723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.558864723
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2700630380
Short name T254
Test name
Test status
Simulation time 57991034 ps
CPU time 0.63 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 198136 kb
Host smart-0fb36d4a-07e7-4390-81e8-ce98423f4711
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700630380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2700630380
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.4085012300
Short name T407
Test name
Test status
Simulation time 42188368 ps
CPU time 0.64 seconds
Started Jul 25 06:21:50 PM PDT 24
Finished Jul 25 06:21:51 PM PDT 24
Peak memory 198184 kb
Host smart-8acdf4c2-2be7-48f1-a446-05f9b4ea264a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085012300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.4085012300
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.500103180
Short name T183
Test name
Test status
Simulation time 66534375 ps
CPU time 0.69 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 201484 kb
Host smart-6563ae4e-5423-41d2-86f6-2c9b4c03fd3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500103180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid
.500103180
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2102312394
Short name T323
Test name
Test status
Simulation time 21922510 ps
CPU time 0.62 seconds
Started Jul 25 06:21:54 PM PDT 24
Finished Jul 25 06:21:55 PM PDT 24
Peak memory 198164 kb
Host smart-1fe2e050-e139-43e5-9313-8915e98e8664
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102312394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2102312394
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3304316757
Short name T351
Test name
Test status
Simulation time 187856120 ps
CPU time 0.77 seconds
Started Jul 25 06:21:50 PM PDT 24
Finished Jul 25 06:21:51 PM PDT 24
Peak memory 209560 kb
Host smart-ce231392-24a7-4d2e-929e-116400f64b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304316757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3304316757
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1073309601
Short name T4
Test name
Test status
Simulation time 214881243 ps
CPU time 0.69 seconds
Started Jul 25 06:21:49 PM PDT 24
Finished Jul 25 06:21:50 PM PDT 24
Peak memory 198172 kb
Host smart-8390124c-45a7-4f02-b79d-c1bdefee2fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073309601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1073309601
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2891592125
Short name T92
Test name
Test status
Simulation time 32265877 ps
CPU time 0.67 seconds
Started Jul 25 06:21:48 PM PDT 24
Finished Jul 25 06:21:48 PM PDT 24
Peak memory 199428 kb
Host smart-d3ff0881-2417-41e2-8715-2ffafd2a1ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891592125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2891592125
Directory /workspace/9.pwrmgr_smoke/latest
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