Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 562 1 T2 2 T5 2 T8 2
auto[1] 494 1 T5 4 T6 6 T10 4


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 584 1 T2 1 T5 1 T6 2
auto[1] 472 1 T2 1 T5 5 T6 4


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 479 1 T2 2 T5 4 T6 5
auto[1] 577 1 T5 2 T6 1 T8 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 875 1 T2 2 T5 4 T6 4
auto[1] 181 1 T5 2 T6 2 T8 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 480 1 T2 2 T5 5 T6 2
auto[1] 576 1 T5 1 T6 4 T8 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 555 1 T5 3 T6 1 T8 2
auto[1] 501 1 T2 2 T5 3 T6 5


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 24 1 T59 1 T91 2 T171 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 3 1 T172 1 T173 1 T174 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 37 1 T14 1 T17 1 T59 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 4 1 T175 1 T146 1 T176 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 15 1 T48 1 T30 1 T71 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T71 1 - - - -
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 72 1 T8 1 T15 1 T24 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 54 1 T8 1 T15 1 T24 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 18 1 T2 1 T91 1 T93 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 3 1 T177 1 T178 1 T179 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 31 1 T50 1 T17 1 T91 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T180 1 T58 2 T181 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 34 1 T14 1 T30 1 T93 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 3 1 T58 1 T148 1 T182 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 28 1 T10 1 T14 2 T17 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 3 1 T10 1 T183 1 T184 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 27 1 T14 1 T17 2 T30 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T176 1 - - - -
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 17 1 T10 1 T14 1 T54 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 3 1 T54 1 T172 1 T185 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 27 1 T50 1 T17 1 T29 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 6 1 T29 1 T186 1 T187 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 27 1 T14 1 T30 2 T59 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 4 1 T68 1 T188 1 T189 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 28 1 T2 1 T5 1 T50 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 6 1 T5 1 T92 1 T57 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 15 1 T59 1 T190 1 T191 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 4 1 T191 1 T58 1 T182 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 27 1 T14 1 T37 1 T93 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 6 1 T192 1 T193 1 T194 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 24 1 T10 1 T30 1 T91 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 5 1 T10 1 T55 1 T193 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 25 1 T88 1 T91 1 T93 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 4 1 T195 1 T196 1 T197 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 27 1 T10 1 T17 1 T29 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 5 1 T10 1 T29 1 T148 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 27 1 T5 1 T6 1 T48 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 5 1 T92 1 T58 1 T181 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 24 1 T59 1 T68 1 T71 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 5 1 T68 1 T178 1 T64 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 22 1 T93 1 T120 1 T147 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 3 1 T198 1 T187 1 T197 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 31 1 T14 2 T59 1 T91 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T54 1 T55 1 T145 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 26 1 T37 1 T71 1 T120 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 2 1 T199 1 T200 1 - -
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 32 1 T6 1 T30 1 T59 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 6 1 T201 1 T186 1 T56 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 30 1 T50 1 T119 1 T91 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 5 1 T50 2 T183 1 T191 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 23 1 T5 1 T10 1 T17 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 2 1 T5 1 T192 1 - -
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 25 1 T14 1 T30 1 T68 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 4 1 T195 1 T202 2 T179 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 20 1 T48 1 T17 1 T59 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 2 1 T48 1 T185 1 - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 33 1 T5 1 T6 1 T37 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 7 1 T6 1 T196 1 T177 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 26 1 T88 1 T59 2 T37 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 6 1 T88 1 T71 1 T198 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 27 1 T6 1 T10 1 T48 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 5 1 T6 1 T48 1 T199 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 26 1 T14 1 T88 1 T17 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 4 1 T180 1 T56 1 T203 1

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