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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 98.23 96.15 99.44 96.00 96.18 100.00 95.91


Total test records in report: 737
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T556 /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2735506467 Jul 27 06:13:30 PM PDT 24 Jul 27 06:13:31 PM PDT 24 66369227 ps
T557 /workspace/coverage/default/20.pwrmgr_aborted_low_power.2028565446 Jul 27 06:15:52 PM PDT 24 Jul 27 06:15:53 PM PDT 24 28269890 ps
T558 /workspace/coverage/default/34.pwrmgr_escalation_timeout.714280503 Jul 27 06:17:28 PM PDT 24 Jul 27 06:17:29 PM PDT 24 604009756 ps
T559 /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.510201482 Jul 27 06:16:21 PM PDT 24 Jul 27 06:16:22 PM PDT 24 28222032 ps
T560 /workspace/coverage/default/2.pwrmgr_global_esc.2141363475 Jul 27 06:12:44 PM PDT 24 Jul 27 06:12:45 PM PDT 24 48372278 ps
T561 /workspace/coverage/default/46.pwrmgr_escalation_timeout.4180945658 Jul 27 06:18:44 PM PDT 24 Jul 27 06:18:45 PM PDT 24 853373955 ps
T562 /workspace/coverage/default/38.pwrmgr_reset.516879393 Jul 27 06:17:49 PM PDT 24 Jul 27 06:17:50 PM PDT 24 269792988 ps
T563 /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1060760339 Jul 27 06:14:56 PM PDT 24 Jul 27 06:14:56 PM PDT 24 48850910 ps
T564 /workspace/coverage/default/9.pwrmgr_glitch.3910295398 Jul 27 06:14:13 PM PDT 24 Jul 27 06:14:14 PM PDT 24 41175130 ps
T565 /workspace/coverage/default/18.pwrmgr_reset.4084025352 Jul 27 06:15:33 PM PDT 24 Jul 27 06:15:34 PM PDT 24 75321882 ps
T184 /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3050250643 Jul 27 06:17:04 PM PDT 24 Jul 27 06:17:04 PM PDT 24 66385961 ps
T566 /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.801925366 Jul 27 06:18:47 PM PDT 24 Jul 27 06:18:48 PM PDT 24 32819658 ps
T567 /workspace/coverage/default/48.pwrmgr_reset_invalid.886312564 Jul 27 06:18:47 PM PDT 24 Jul 27 06:18:49 PM PDT 24 150221534 ps
T568 /workspace/coverage/default/33.pwrmgr_glitch.3919721637 Jul 27 06:17:28 PM PDT 24 Jul 27 06:17:29 PM PDT 24 48475478 ps
T569 /workspace/coverage/default/8.pwrmgr_glitch.3638397313 Jul 27 06:14:01 PM PDT 24 Jul 27 06:14:02 PM PDT 24 47668025 ps
T570 /workspace/coverage/default/47.pwrmgr_glitch.3514907822 Jul 27 06:18:46 PM PDT 24 Jul 27 06:18:47 PM PDT 24 65427380 ps
T571 /workspace/coverage/default/27.pwrmgr_smoke.1048774464 Jul 27 06:16:48 PM PDT 24 Jul 27 06:16:49 PM PDT 24 30826125 ps
T572 /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.150312795 Jul 27 06:17:29 PM PDT 24 Jul 27 06:17:30 PM PDT 24 149771716 ps
T573 /workspace/coverage/default/31.pwrmgr_reset.2030952094 Jul 27 06:17:02 PM PDT 24 Jul 27 06:17:03 PM PDT 24 48119832 ps
T574 /workspace/coverage/default/39.pwrmgr_global_esc.1536505574 Jul 27 06:18:06 PM PDT 24 Jul 27 06:18:07 PM PDT 24 42344481 ps
T575 /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3426354178 Jul 27 06:18:47 PM PDT 24 Jul 27 06:18:48 PM PDT 24 102780317 ps
T576 /workspace/coverage/default/44.pwrmgr_reset.3737567314 Jul 27 06:18:26 PM PDT 24 Jul 27 06:18:27 PM PDT 24 131361567 ps
T577 /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2834219127 Jul 27 06:12:09 PM PDT 24 Jul 27 06:12:10 PM PDT 24 64399862 ps
T578 /workspace/coverage/default/32.pwrmgr_lowpower_invalid.525434683 Jul 27 06:17:23 PM PDT 24 Jul 27 06:17:24 PM PDT 24 46496723 ps
T173 /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2489493902 Jul 27 06:18:07 PM PDT 24 Jul 27 06:18:08 PM PDT 24 80842657 ps
T579 /workspace/coverage/default/38.pwrmgr_aborted_low_power.523916662 Jul 27 06:17:54 PM PDT 24 Jul 27 06:17:55 PM PDT 24 45292641 ps
T580 /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.457538395 Jul 27 06:19:00 PM PDT 24 Jul 27 06:19:01 PM PDT 24 70702345 ps
T581 /workspace/coverage/default/39.pwrmgr_reset.1869647199 Jul 27 06:18:02 PM PDT 24 Jul 27 06:18:03 PM PDT 24 86070033 ps
T582 /workspace/coverage/default/5.pwrmgr_reset.2167631105 Jul 27 06:13:23 PM PDT 24 Jul 27 06:13:24 PM PDT 24 27206282 ps
T583 /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3816739334 Jul 27 06:18:17 PM PDT 24 Jul 27 06:18:18 PM PDT 24 48728352 ps
T584 /workspace/coverage/default/47.pwrmgr_reset_invalid.427567408 Jul 27 06:18:49 PM PDT 24 Jul 27 06:18:50 PM PDT 24 150253908 ps
T585 /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3468508986 Jul 27 06:16:31 PM PDT 24 Jul 27 06:16:32 PM PDT 24 39934535 ps
T586 /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2970027870 Jul 27 06:12:49 PM PDT 24 Jul 27 06:12:50 PM PDT 24 81313830 ps
T587 /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.921989429 Jul 27 06:17:51 PM PDT 24 Jul 27 06:17:52 PM PDT 24 273414296 ps
T588 /workspace/coverage/default/32.pwrmgr_smoke.1895021106 Jul 27 06:17:14 PM PDT 24 Jul 27 06:17:15 PM PDT 24 55667654 ps
T589 /workspace/coverage/default/29.pwrmgr_smoke.1346357087 Jul 27 06:16:51 PM PDT 24 Jul 27 06:16:52 PM PDT 24 47587496 ps
T590 /workspace/coverage/default/23.pwrmgr_reset.805609252 Jul 27 06:16:11 PM PDT 24 Jul 27 06:16:12 PM PDT 24 97095435 ps
T591 /workspace/coverage/default/14.pwrmgr_reset_invalid.2310982333 Jul 27 06:15:03 PM PDT 24 Jul 27 06:15:04 PM PDT 24 231758504 ps
T35 /workspace/coverage/default/1.pwrmgr_sec_cm.358946738 Jul 27 06:12:38 PM PDT 24 Jul 27 06:12:40 PM PDT 24 658545736 ps
T592 /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2125474269 Jul 27 06:13:05 PM PDT 24 Jul 27 06:13:06 PM PDT 24 29481839 ps
T593 /workspace/coverage/default/3.pwrmgr_global_esc.3902356623 Jul 27 06:13:03 PM PDT 24 Jul 27 06:13:03 PM PDT 24 51391984 ps
T594 /workspace/coverage/default/15.pwrmgr_reset_invalid.1279642763 Jul 27 06:15:13 PM PDT 24 Jul 27 06:15:14 PM PDT 24 167757294 ps
T595 /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.51136511 Jul 27 06:13:32 PM PDT 24 Jul 27 06:13:33 PM PDT 24 39640901 ps
T596 /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2752553236 Jul 27 06:14:02 PM PDT 24 Jul 27 06:14:03 PM PDT 24 73050530 ps
T597 /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1192755779 Jul 27 06:18:48 PM PDT 24 Jul 27 06:18:49 PM PDT 24 45330883 ps
T598 /workspace/coverage/default/19.pwrmgr_smoke.1551991868 Jul 27 06:15:31 PM PDT 24 Jul 27 06:15:32 PM PDT 24 28279432 ps
T599 /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4067065766 Jul 27 06:12:51 PM PDT 24 Jul 27 06:12:51 PM PDT 24 59990561 ps
T600 /workspace/coverage/default/41.pwrmgr_glitch.3486619305 Jul 27 06:18:10 PM PDT 24 Jul 27 06:18:11 PM PDT 24 33366448 ps
T601 /workspace/coverage/default/3.pwrmgr_reset_invalid.3011544277 Jul 27 06:13:08 PM PDT 24 Jul 27 06:13:09 PM PDT 24 165717506 ps
T602 /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.605227453 Jul 27 06:15:51 PM PDT 24 Jul 27 06:15:52 PM PDT 24 64245087 ps
T603 /workspace/coverage/default/34.pwrmgr_reset_invalid.682409293 Jul 27 06:17:29 PM PDT 24 Jul 27 06:17:30 PM PDT 24 111298204 ps
T604 /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.884104934 Jul 27 06:15:59 PM PDT 24 Jul 27 06:16:01 PM PDT 24 53635929 ps
T605 /workspace/coverage/default/30.pwrmgr_global_esc.2624724229 Jul 27 06:17:07 PM PDT 24 Jul 27 06:17:07 PM PDT 24 185797182 ps
T606 /workspace/coverage/default/31.pwrmgr_escalation_timeout.918665556 Jul 27 06:17:26 PM PDT 24 Jul 27 06:17:27 PM PDT 24 320111257 ps
T607 /workspace/coverage/default/45.pwrmgr_reset_invalid.1857575629 Jul 27 06:18:37 PM PDT 24 Jul 27 06:18:38 PM PDT 24 92468366 ps
T608 /workspace/coverage/default/15.pwrmgr_reset.2793728537 Jul 27 06:15:07 PM PDT 24 Jul 27 06:15:07 PM PDT 24 19725880 ps
T609 /workspace/coverage/default/37.pwrmgr_glitch.3399781640 Jul 27 06:17:50 PM PDT 24 Jul 27 06:17:50 PM PDT 24 97451534 ps
T610 /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.494485931 Jul 27 06:12:09 PM PDT 24 Jul 27 06:12:10 PM PDT 24 36885140 ps
T611 /workspace/coverage/default/6.pwrmgr_smoke.2877628148 Jul 27 06:13:30 PM PDT 24 Jul 27 06:13:30 PM PDT 24 39324239 ps
T612 /workspace/coverage/default/6.pwrmgr_reset.497188336 Jul 27 06:13:37 PM PDT 24 Jul 27 06:13:38 PM PDT 24 62476401 ps
T613 /workspace/coverage/default/17.pwrmgr_smoke.886996120 Jul 27 06:15:19 PM PDT 24 Jul 27 06:15:20 PM PDT 24 49559702 ps
T614 /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1608606512 Jul 27 06:16:20 PM PDT 24 Jul 27 06:16:21 PM PDT 24 104817948 ps
T615 /workspace/coverage/default/2.pwrmgr_aborted_low_power.771027305 Jul 27 06:12:43 PM PDT 24 Jul 27 06:12:44 PM PDT 24 32491389 ps
T174 /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3530246949 Jul 27 06:17:49 PM PDT 24 Jul 27 06:17:50 PM PDT 24 44764465 ps
T616 /workspace/coverage/default/19.pwrmgr_escalation_timeout.3676847303 Jul 27 06:15:41 PM PDT 24 Jul 27 06:15:42 PM PDT 24 314907663 ps
T617 /workspace/coverage/default/40.pwrmgr_glitch.2142800898 Jul 27 06:18:09 PM PDT 24 Jul 27 06:18:10 PM PDT 24 33182374 ps
T618 /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.185620574 Jul 27 06:18:08 PM PDT 24 Jul 27 06:18:09 PM PDT 24 35351770 ps
T619 /workspace/coverage/default/41.pwrmgr_aborted_low_power.845704875 Jul 27 06:18:06 PM PDT 24 Jul 27 06:18:07 PM PDT 24 34771886 ps
T620 /workspace/coverage/default/44.pwrmgr_reset_invalid.3493174433 Jul 27 06:18:29 PM PDT 24 Jul 27 06:18:30 PM PDT 24 197294871 ps
T621 /workspace/coverage/default/22.pwrmgr_reset.1705019825 Jul 27 06:16:01 PM PDT 24 Jul 27 06:16:02 PM PDT 24 62744191 ps
T622 /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2112276996 Jul 27 06:12:39 PM PDT 24 Jul 27 06:12:39 PM PDT 24 52204924 ps
T623 /workspace/coverage/default/13.pwrmgr_smoke.2981929969 Jul 27 06:14:46 PM PDT 24 Jul 27 06:14:47 PM PDT 24 38258666 ps
T65 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.992373464 Jul 27 06:19:58 PM PDT 24 Jul 27 06:19:59 PM PDT 24 21493250 ps
T25 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3108470020 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:54 PM PDT 24 289228065 ps
T75 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.346396214 Jul 27 06:20:25 PM PDT 24 Jul 27 06:20:26 PM PDT 24 52680980 ps
T66 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1868328601 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:59 PM PDT 24 74575347 ps
T26 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3542341499 Jul 27 06:20:10 PM PDT 24 Jul 27 06:20:11 PM PDT 24 125625455 ps
T27 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2505654041 Jul 27 06:20:10 PM PDT 24 Jul 27 06:20:11 PM PDT 24 97710280 ps
T76 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1711626166 Jul 27 06:19:47 PM PDT 24 Jul 27 06:19:48 PM PDT 24 52948621 ps
T110 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2912646691 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:18 PM PDT 24 27734448 ps
T77 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3079711935 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:17 PM PDT 24 60725105 ps
T160 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1421292882 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 52094085 ps
T161 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.373821628 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:57 PM PDT 24 52443236 ps
T111 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3486994555 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 83778984 ps
T125 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1247196226 Jul 27 06:19:46 PM PDT 24 Jul 27 06:19:47 PM PDT 24 51152737 ps
T162 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.28549727 Jul 27 06:20:26 PM PDT 24 Jul 27 06:20:27 PM PDT 24 37683030 ps
T624 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1639863890 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 22579758 ps
T60 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3403152692 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 47162933 ps
T112 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.971690383 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 27888577 ps
T625 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2120679510 Jul 27 06:20:26 PM PDT 24 Jul 27 06:20:27 PM PDT 24 18002081 ps
T80 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3584507785 Jul 27 06:20:02 PM PDT 24 Jul 27 06:20:03 PM PDT 24 42973773 ps
T102 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3605941671 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 21732402 ps
T61 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2432671599 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:19 PM PDT 24 204589037 ps
T113 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2393116163 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:48 PM PDT 24 45876549 ps
T626 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1202547768 Jul 27 06:19:57 PM PDT 24 Jul 27 06:20:00 PM PDT 24 812207136 ps
T627 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1247837428 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:50 PM PDT 24 40667720 ps
T114 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.264774388 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:49 PM PDT 24 93098189 ps
T63 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2917287434 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:09 PM PDT 24 31345977 ps
T81 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1628712879 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 59159821 ps
T74 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.432724033 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 273474281 ps
T82 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.310240343 Jul 27 06:20:00 PM PDT 24 Jul 27 06:20:01 PM PDT 24 54411530 ps
T628 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.541205270 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 43673366 ps
T84 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1016801076 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:10 PM PDT 24 161750560 ps
T629 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2826477488 Jul 27 06:20:26 PM PDT 24 Jul 27 06:20:26 PM PDT 24 16820336 ps
T73 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1128092245 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:52 PM PDT 24 96262482 ps
T630 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2464767462 Jul 27 06:20:20 PM PDT 24 Jul 27 06:20:20 PM PDT 24 29566139 ps
T83 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3112449857 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:12 PM PDT 24 110325564 ps
T631 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.205391530 Jul 27 06:20:19 PM PDT 24 Jul 27 06:20:20 PM PDT 24 33471752 ps
T87 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3156261327 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:54 PM PDT 24 148776470 ps
T632 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2877512275 Jul 27 06:20:19 PM PDT 24 Jul 27 06:20:19 PM PDT 24 18915802 ps
T633 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.331704620 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:09 PM PDT 24 351442189 ps
T115 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.519191612 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:08 PM PDT 24 19581705 ps
T634 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1387209464 Jul 27 06:20:05 PM PDT 24 Jul 27 06:20:06 PM PDT 24 65367584 ps
T635 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.906312852 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:51 PM PDT 24 37220817 ps
T126 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1481072560 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:54 PM PDT 24 152347169 ps
T103 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2032399204 Jul 27 06:19:58 PM PDT 24 Jul 27 06:19:59 PM PDT 24 27397524 ps
T636 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.3691988271 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 67123580 ps
T116 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.162005651 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 16328146 ps
T62 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3549580553 Jul 27 06:19:58 PM PDT 24 Jul 27 06:20:00 PM PDT 24 206308880 ps
T637 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.108849047 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:12 PM PDT 24 55925533 ps
T117 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1932751181 Jul 27 06:20:05 PM PDT 24 Jul 27 06:20:06 PM PDT 24 44813079 ps
T118 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2394314185 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:49 PM PDT 24 19814066 ps
T638 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2015044372 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:51 PM PDT 24 131041387 ps
T639 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2357925947 Jul 27 06:20:00 PM PDT 24 Jul 27 06:20:01 PM PDT 24 76617207 ps
T640 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3118486897 Jul 27 06:20:20 PM PDT 24 Jul 27 06:20:21 PM PDT 24 59726628 ps
T641 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.497760454 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 59580457 ps
T642 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.310234230 Jul 27 06:19:53 PM PDT 24 Jul 27 06:19:55 PM PDT 24 188534456 ps
T643 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3828896723 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 144269203 ps
T644 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1354241244 Jul 27 06:20:29 PM PDT 24 Jul 27 06:20:30 PM PDT 24 20004258 ps
T645 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2402606621 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 111063207 ps
T151 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2350634199 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:12 PM PDT 24 259848910 ps
T646 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.4279402194 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:53 PM PDT 24 861022101 ps
T647 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.404847160 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:49 PM PDT 24 32630022 ps
T127 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3258039920 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 121303106 ps
T648 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.937779701 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 19269548 ps
T649 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.624777163 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 45331529 ps
T650 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2508217343 Jul 27 06:20:27 PM PDT 24 Jul 27 06:20:28 PM PDT 24 37140639 ps
T128 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2241851482 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:13 PM PDT 24 44265232 ps
T104 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3440397015 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:49 PM PDT 24 40281106 ps
T651 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.73909457 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:53 PM PDT 24 71912117 ps
T652 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2673289079 Jul 27 06:20:29 PM PDT 24 Jul 27 06:20:30 PM PDT 24 42796029 ps
T653 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3822584211 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:52 PM PDT 24 1187150885 ps
T654 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3559178780 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:14 PM PDT 24 129759782 ps
T85 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2349834060 Jul 27 06:20:01 PM PDT 24 Jul 27 06:20:03 PM PDT 24 194182537 ps
T655 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.672918891 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:17 PM PDT 24 28338949 ps
T656 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1703813622 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:07 PM PDT 24 193771307 ps
T657 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3759201724 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 275380776 ps
T658 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4045441529 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:18 PM PDT 24 16270967 ps
T659 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.259769239 Jul 27 06:19:57 PM PDT 24 Jul 27 06:19:59 PM PDT 24 117304026 ps
T660 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2773024599 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:50 PM PDT 24 19168074 ps
T661 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1156179901 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:08 PM PDT 24 51091167 ps
T662 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1274653520 Jul 27 06:19:50 PM PDT 24 Jul 27 06:19:51 PM PDT 24 71651463 ps
T663 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1820896711 Jul 27 06:19:57 PM PDT 24 Jul 27 06:19:58 PM PDT 24 29053071 ps
T664 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4041280428 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:52 PM PDT 24 180038324 ps
T665 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1891400309 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 47257701 ps
T666 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2862672715 Jul 27 06:20:19 PM PDT 24 Jul 27 06:20:20 PM PDT 24 60915370 ps
T667 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.212602159 Jul 27 06:20:20 PM PDT 24 Jul 27 06:20:21 PM PDT 24 27737894 ps
T668 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2437221497 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 288850847 ps
T669 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.933793171 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 144013346 ps
T670 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1475448156 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:10 PM PDT 24 303407705 ps
T671 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.555101462 Jul 27 06:20:18 PM PDT 24 Jul 27 06:20:19 PM PDT 24 55028133 ps
T672 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1988172239 Jul 27 06:20:15 PM PDT 24 Jul 27 06:20:16 PM PDT 24 15707915 ps
T673 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.174146445 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:20 PM PDT 24 642818895 ps
T674 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.16804209 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:13 PM PDT 24 49165365 ps
T149 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1134636509 Jul 27 06:19:51 PM PDT 24 Jul 27 06:19:52 PM PDT 24 178772569 ps
T675 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3106971669 Jul 27 06:20:19 PM PDT 24 Jul 27 06:20:20 PM PDT 24 47064776 ps
T86 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3295474402 Jul 27 06:20:10 PM PDT 24 Jul 27 06:20:12 PM PDT 24 183059306 ps
T676 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3187329141 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:12 PM PDT 24 20193637 ps
T677 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2963144225 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:15 PM PDT 24 429164814 ps
T678 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1156781575 Jul 27 06:19:59 PM PDT 24 Jul 27 06:20:00 PM PDT 24 35115846 ps
T679 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2862186201 Jul 27 06:20:30 PM PDT 24 Jul 27 06:20:30 PM PDT 24 107697072 ps
T680 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3231565704 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 19008915 ps
T681 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.4128957577 Jul 27 06:20:02 PM PDT 24 Jul 27 06:20:03 PM PDT 24 26392409 ps
T682 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3530368598 Jul 27 06:19:47 PM PDT 24 Jul 27 06:19:49 PM PDT 24 186229290 ps
T683 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1950299940 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:57 PM PDT 24 248467294 ps
T684 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1784880060 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 71062118 ps
T685 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3994371970 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:07 PM PDT 24 74011822 ps
T78 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1888885664 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:18 PM PDT 24 189298090 ps
T686 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1580059063 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:13 PM PDT 24 48411453 ps
T79 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.468417583 Jul 27 06:20:00 PM PDT 24 Jul 27 06:20:02 PM PDT 24 424602717 ps
T687 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3754263891 Jul 27 06:19:57 PM PDT 24 Jul 27 06:19:58 PM PDT 24 57831246 ps
T105 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.68514997 Jul 27 06:19:47 PM PDT 24 Jul 27 06:19:48 PM PDT 24 36262994 ps
T688 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.214503416 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:53 PM PDT 24 46720070 ps
T689 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.350990408 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 18264539 ps
T690 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3297441877 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 56409933 ps
T691 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2194442482 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:17 PM PDT 24 36061791 ps
T692 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.845787268 Jul 27 06:20:29 PM PDT 24 Jul 27 06:20:29 PM PDT 24 35109371 ps
T693 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3511670413 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 31690598 ps
T694 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3961287200 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:11 PM PDT 24 24821594 ps
T695 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1358136594 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:49 PM PDT 24 21667721 ps
T696 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4091093319 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 122630365 ps
T697 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2309956155 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 404513192 ps
T698 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2487416894 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:07 PM PDT 24 82273185 ps
T699 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3256934454 Jul 27 06:20:11 PM PDT 24 Jul 27 06:20:13 PM PDT 24 73998946 ps
T700 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3766371320 Jul 27 06:20:12 PM PDT 24 Jul 27 06:20:13 PM PDT 24 43032408 ps
T701 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1926967664 Jul 27 06:20:20 PM PDT 24 Jul 27 06:20:21 PM PDT 24 49693517 ps
T702 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3721904997 Jul 27 06:19:57 PM PDT 24 Jul 27 06:19:58 PM PDT 24 18769328 ps
T703 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2393377357 Jul 27 06:20:06 PM PDT 24 Jul 27 06:20:09 PM PDT 24 111048527 ps
T704 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.474276288 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:17 PM PDT 24 47013690 ps
T705 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2308831645 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 200482328 ps
T706 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1404532739 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:49 PM PDT 24 37989408 ps
T707 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4241058911 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 62447143 ps
T708 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1710364416 Jul 27 06:20:27 PM PDT 24 Jul 27 06:20:28 PM PDT 24 29216062 ps
T709 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1709643765 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 120891472 ps
T710 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1968026363 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 48866750 ps
T106 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1195926649 Jul 27 06:19:55 PM PDT 24 Jul 27 06:19:56 PM PDT 24 75684244 ps
T711 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1356549240 Jul 27 06:19:52 PM PDT 24 Jul 27 06:19:53 PM PDT 24 67780465 ps
T712 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3088722525 Jul 27 06:20:15 PM PDT 24 Jul 27 06:20:16 PM PDT 24 16983640 ps
T713 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.263276714 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:18 PM PDT 24 71119298 ps
T714 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1184894675 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:56 PM PDT 24 16238192 ps
T715 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2917259130 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:57 PM PDT 24 35251015 ps
T716 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2268389741 Jul 27 06:20:28 PM PDT 24 Jul 27 06:20:29 PM PDT 24 18073874 ps
T717 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3882858845 Jul 27 06:20:27 PM PDT 24 Jul 27 06:20:28 PM PDT 24 51951838 ps
T718 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1922856198 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:17 PM PDT 24 20873583 ps
T719 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3473144234 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:09 PM PDT 24 44081080 ps
T720 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.213719159 Jul 27 06:20:03 PM PDT 24 Jul 27 06:20:05 PM PDT 24 78089152 ps
T721 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3113327653 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:17 PM PDT 24 23266092 ps
T107 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2527126734 Jul 27 06:20:18 PM PDT 24 Jul 27 06:20:19 PM PDT 24 23932302 ps
T722 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2867260909 Jul 27 06:19:59 PM PDT 24 Jul 27 06:20:00 PM PDT 24 31705084 ps
T150 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.758894298 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:11 PM PDT 24 182595752 ps
T723 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3608740 Jul 27 06:20:28 PM PDT 24 Jul 27 06:20:28 PM PDT 24 48462583 ps
T724 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2577901615 Jul 27 06:20:01 PM PDT 24 Jul 27 06:20:01 PM PDT 24 54271504 ps
T725 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1915816231 Jul 27 06:19:59 PM PDT 24 Jul 27 06:20:00 PM PDT 24 41880644 ps
T726 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1818067491 Jul 27 06:19:56 PM PDT 24 Jul 27 06:19:57 PM PDT 24 20227298 ps
T727 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2078168883 Jul 27 06:20:20 PM PDT 24 Jul 27 06:20:21 PM PDT 24 21984977 ps
T728 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1573395521 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:18 PM PDT 24 32669663 ps
T729 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3630530092 Jul 27 06:19:59 PM PDT 24 Jul 27 06:20:01 PM PDT 24 109258196 ps
T730 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2209813828 Jul 27 06:20:10 PM PDT 24 Jul 27 06:20:12 PM PDT 24 177199094 ps
T731 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3141829231 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 245246304 ps
T732 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3251639499 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:08 PM PDT 24 41654310 ps
T108 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1776984563 Jul 27 06:19:57 PM PDT 24 Jul 27 06:19:58 PM PDT 24 125391873 ps
T733 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.772136790 Jul 27 06:20:08 PM PDT 24 Jul 27 06:20:09 PM PDT 24 54964209 ps
T734 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2075417084 Jul 27 06:20:17 PM PDT 24 Jul 27 06:20:18 PM PDT 24 57028722 ps
T735 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1266369735 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 72376193 ps
T736 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.829287569 Jul 27 06:20:07 PM PDT 24 Jul 27 06:20:09 PM PDT 24 139838748 ps
T109 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2771866638 Jul 27 06:20:16 PM PDT 24 Jul 27 06:20:17 PM PDT 24 21564088 ps
T737 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1006505581 Jul 27 06:20:09 PM PDT 24 Jul 27 06:20:10 PM PDT 24 143902358 ps

Test location /workspace/coverage/default/48.pwrmgr_smoke.3129236993
Short name T8
Test name
Test status
Simulation time 55005526 ps
CPU time 0.64 seconds
Started Jul 27 06:18:48 PM PDT 24
Finished Jul 27 06:18:49 PM PDT 24
Peak memory 198536 kb
Host smart-a97beee4-9f74-43a3-a623-0ce84b305654
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129236993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3129236993
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.805265947
Short name T44
Test name
Test status
Simulation time 92963560 ps
CPU time 0.97 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 209568 kb
Host smart-02c8c1ae-1172-47a7-8153-7941e1198207
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805265947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.805265947
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1435439300
Short name T14
Test name
Test status
Simulation time 28850413 ps
CPU time 0.95 seconds
Started Jul 27 06:12:26 PM PDT 24
Finished Jul 27 06:12:27 PM PDT 24
Peak memory 200784 kb
Host smart-d880a48c-4a4d-4f77-83b6-7e940718ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435439300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1435439300
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1178082442
Short name T31
Test name
Test status
Simulation time 56543013 ps
CPU time 0.65 seconds
Started Jul 27 06:14:20 PM PDT 24
Finished Jul 27 06:14:21 PM PDT 24
Peak memory 198300 kb
Host smart-8643455d-42ad-4f6a-a8fc-0eef082e7ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178082442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1178082442
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1575675162
Short name T22
Test name
Test status
Simulation time 1426534145 ps
CPU time 1.42 seconds
Started Jul 27 06:12:51 PM PDT 24
Finished Jul 27 06:12:52 PM PDT 24
Peak memory 217964 kb
Host smart-69060665-2c7e-43d3-b434-3a208c18ef93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575675162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1575675162
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2505654041
Short name T27
Test name
Test status
Simulation time 97710280 ps
CPU time 0.79 seconds
Started Jul 27 06:20:10 PM PDT 24
Finished Jul 27 06:20:11 PM PDT 24
Peak memory 195820 kb
Host smart-70c0f474-5bf4-4955-8a51-90cdb9c13827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505654041 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2505654041
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2956051873
Short name T5
Test name
Test status
Simulation time 42543946 ps
CPU time 0.7 seconds
Started Jul 27 06:14:11 PM PDT 24
Finished Jul 27 06:14:12 PM PDT 24
Peak memory 201404 kb
Host smart-c0829277-7e3e-46e9-ab63-209d422f500f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956051873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2956051873
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2270038241
Short name T10
Test name
Test status
Simulation time 58585761 ps
CPU time 0.73 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 199200 kb
Host smart-bb0d7fa6-c57e-4d7e-9f78-db3caffb92a6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270038241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.2270038241
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2432671599
Short name T61
Test name
Test status
Simulation time 204589037 ps
CPU time 1.66 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:19 PM PDT 24
Peak memory 201068 kb
Host smart-6b491df6-11f4-4d00-accf-8db11aba912f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432671599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2432671599
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.2877396029
Short name T205
Test name
Test status
Simulation time 114681384 ps
CPU time 1.02 seconds
Started Jul 27 06:12:17 PM PDT 24
Finished Jul 27 06:12:18 PM PDT 24
Peak memory 209484 kb
Host smart-81b5d5b0-376d-4ea9-b285-3648422ffc43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877396029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.2877396029
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1883694858
Short name T12
Test name
Test status
Simulation time 28600021 ps
CPU time 0.66 seconds
Started Jul 27 06:16:51 PM PDT 24
Finished Jul 27 06:16:52 PM PDT 24
Peak memory 198080 kb
Host smart-d36849ec-06fa-444a-af84-4bd877f93a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883694858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1883694858
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.4277665307
Short name T59
Test name
Test status
Simulation time 221237235 ps
CPU time 0.82 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 200144 kb
Host smart-2aebafcc-b98b-44e3-92f9-b1b5ba7f6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277665307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.4277665307
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.637562378
Short name T29
Test name
Test status
Simulation time 39423363 ps
CPU time 0.72 seconds
Started Jul 27 06:15:10 PM PDT 24
Finished Jul 27 06:15:11 PM PDT 24
Peak memory 198544 kb
Host smart-22f9bffc-6db2-4c73-b0b1-8717884035cf
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637562378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_c
m_ctrl_config_regwen.637562378
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1639863890
Short name T624
Test name
Test status
Simulation time 22579758 ps
CPU time 0.63 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 195544 kb
Host smart-395b4689-5026-4d9b-8925-8edc66da6233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639863890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1639863890
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1128092245
Short name T73
Test name
Test status
Simulation time 96262482 ps
CPU time 2.18 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:52 PM PDT 24
Peak memory 197908 kb
Host smart-00e95578-c4d5-4f3f-ae5c-d24955a75a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128092245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1128092245
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.1533433857
Short name T55
Test name
Test status
Simulation time 53768058 ps
CPU time 0.75 seconds
Started Jul 27 06:17:02 PM PDT 24
Finished Jul 27 06:17:03 PM PDT 24
Peak memory 198816 kb
Host smart-c20a6f57-42a9-41e6-911c-0f3627111c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533433857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1533433857
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.3657302870
Short name T58
Test name
Test status
Simulation time 97781632 ps
CPU time 0.8 seconds
Started Jul 27 06:15:21 PM PDT 24
Finished Jul 27 06:15:21 PM PDT 24
Peak memory 198500 kb
Host smart-a896b0ca-2cd3-4f1c-b488-40b9edfb331a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657302870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.3657302870
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1195926649
Short name T106
Test name
Test status
Simulation time 75684244 ps
CPU time 0.98 seconds
Started Jul 27 06:19:55 PM PDT 24
Finished Jul 27 06:19:56 PM PDT 24
Peak memory 199320 kb
Host smart-a2fb5f72-b2b9-4f66-ad85-14c03cb337e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195926649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
195926649
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2129673332
Short name T33
Test name
Test status
Simulation time 83458014 ps
CPU time 0.68 seconds
Started Jul 27 06:17:54 PM PDT 24
Finished Jul 27 06:17:55 PM PDT 24
Peak memory 198100 kb
Host smart-f60bc5a5-89f9-4e82-b12f-5cac1ba59f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129673332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2129673332
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1174397834
Short name T152
Test name
Test status
Simulation time 46824611 ps
CPU time 0.69 seconds
Started Jul 27 06:16:46 PM PDT 24
Finished Jul 27 06:16:47 PM PDT 24
Peak memory 199420 kb
Host smart-98f2aba3-19e8-4cee-a055-59fe99db0e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174397834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.1174397834
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1337821042
Short name T171
Test name
Test status
Simulation time 80462808 ps
CPU time 0.8 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 200264 kb
Host smart-6789bd48-d737-4c18-a40a-853814c031c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337821042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1337821042
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2571242516
Short name T198
Test name
Test status
Simulation time 43751798 ps
CPU time 0.71 seconds
Started Jul 27 06:16:46 PM PDT 24
Finished Jul 27 06:16:47 PM PDT 24
Peak memory 201396 kb
Host smart-fbeeb247-b744-4a94-99e2-84c90d5dc6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571242516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2571242516
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.1218203194
Short name T56
Test name
Test status
Simulation time 49716144 ps
CPU time 0.66 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198316 kb
Host smart-b7d92465-9283-43b1-aa8a-43b968500655
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218203194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1218203194
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1056561279
Short name T67
Test name
Test status
Simulation time 50960968 ps
CPU time 0.64 seconds
Started Jul 27 06:14:33 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 199436 kb
Host smart-5c342260-24a6-4e64-89b2-57eb9fb4e0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056561279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1056561279
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1828209287
Short name T177
Test name
Test status
Simulation time 80528625 ps
CPU time 0.7 seconds
Started Jul 27 06:18:08 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 201264 kb
Host smart-3447796e-7390-4912-808e-a6b5b17a72b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828209287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1828209287
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1346869049
Short name T158
Test name
Test status
Simulation time 57523551 ps
CPU time 0.71 seconds
Started Jul 27 06:18:48 PM PDT 24
Finished Jul 27 06:18:49 PM PDT 24
Peak memory 198568 kb
Host smart-a519869d-8a6d-46ce-ac75-1a3a03fe5f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346869049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1346869049
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2170724927
Short name T189
Test name
Test status
Simulation time 47045589 ps
CPU time 0.63 seconds
Started Jul 27 06:12:25 PM PDT 24
Finished Jul 27 06:12:25 PM PDT 24
Peak memory 198336 kb
Host smart-78326ba3-a2c1-4fa4-974b-52d76a59a2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170724927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2170724927
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.2963072970
Short name T54
Test name
Test status
Simulation time 50195726 ps
CPU time 0.67 seconds
Started Jul 27 06:16:19 PM PDT 24
Finished Jul 27 06:16:20 PM PDT 24
Peak memory 198404 kb
Host smart-5cab85b4-d862-421d-849c-8a4afbf37c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963072970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.2963072970
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.4146806704
Short name T16
Test name
Test status
Simulation time 92971302 ps
CPU time 1 seconds
Started Jul 27 06:18:18 PM PDT 24
Finished Jul 27 06:18:19 PM PDT 24
Peak memory 209544 kb
Host smart-d1913688-3f27-43d7-8891-46ca675826d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146806704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.4146806704
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1547891982
Short name T199
Test name
Test status
Simulation time 49503363 ps
CPU time 0.68 seconds
Started Jul 27 06:14:32 PM PDT 24
Finished Jul 27 06:14:33 PM PDT 24
Peak memory 201408 kb
Host smart-5b4fabdb-db88-40e2-a785-98ff41701eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547891982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1547891982
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.2385183061
Short name T176
Test name
Test status
Simulation time 43756984 ps
CPU time 0.75 seconds
Started Jul 27 06:14:32 PM PDT 24
Finished Jul 27 06:14:33 PM PDT 24
Peak memory 201472 kb
Host smart-3d10f304-2728-4664-b27c-a731cff4fad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385183061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.2385183061
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.662972428
Short name T141
Test name
Test status
Simulation time 54198918 ps
CPU time 0.8 seconds
Started Jul 27 06:15:42 PM PDT 24
Finished Jul 27 06:15:43 PM PDT 24
Peak memory 198604 kb
Host smart-176c2127-4c6b-4c23-9a89-9c8a448811d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662972428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disa
ble_rom_integrity_check.662972428
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1784097639
Short name T195
Test name
Test status
Simulation time 41673489 ps
CPU time 0.72 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:52 PM PDT 24
Peak memory 201468 kb
Host smart-17c14c36-5f45-4f69-beed-1e13d3b0ce7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784097639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1784097639
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1888885664
Short name T78
Test name
Test status
Simulation time 189298090 ps
CPU time 1.63 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 195892 kb
Host smart-8c0c4dc9-b833-42d8-a0d5-011c6e5ad682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888885664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.1888885664
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2394314185
Short name T118
Test name
Test status
Simulation time 19814066 ps
CPU time 0.69 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 197736 kb
Host smart-361063bb-849d-43fb-8c56-6e94ce3bcca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394314185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2394314185
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.541205270
Short name T628
Test name
Test status
Simulation time 43673366 ps
CPU time 0.62 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195552 kb
Host smart-0fc87bf3-c645-4a1c-ac5e-f14948278b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541205270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.541205270
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2112276996
Short name T622
Test name
Test status
Simulation time 52204924 ps
CPU time 0.68 seconds
Started Jul 27 06:12:39 PM PDT 24
Finished Jul 27 06:12:39 PM PDT 24
Peak memory 201412 kb
Host smart-3d6e4c6a-2d9c-4bec-910a-e00cb9ca93f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112276996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2112276996
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3081616738
Short name T68
Test name
Test status
Simulation time 49455825 ps
CPU time 0.71 seconds
Started Jul 27 06:14:57 PM PDT 24
Finished Jul 27 06:14:58 PM PDT 24
Peak memory 201416 kb
Host smart-381c15a1-2dec-439d-8832-af9096239979
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081616738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3081616738
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.3277686341
Short name T154
Test name
Test status
Simulation time 78408655 ps
CPU time 0.69 seconds
Started Jul 27 06:15:12 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 199244 kb
Host smart-ef1924ac-648f-46f8-8f1f-b62c3109b401
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277686341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.3277686341
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3478792402
Short name T207
Test name
Test status
Simulation time 147567131 ps
CPU time 0.76 seconds
Started Jul 27 06:15:14 PM PDT 24
Finished Jul 27 06:15:15 PM PDT 24
Peak memory 198084 kb
Host smart-7eaf6b3e-6d2d-4927-96ad-4af4b8945bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478792402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3478792402
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.602064926
Short name T153
Test name
Test status
Simulation time 55321741 ps
CPU time 0.69 seconds
Started Jul 27 06:15:17 PM PDT 24
Finished Jul 27 06:15:18 PM PDT 24
Peak memory 199232 kb
Host smart-f587e9e9-c140-4e28-af0b-b283e79651bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602064926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.602064926
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1148152052
Short name T183
Test name
Test status
Simulation time 57787248 ps
CPU time 0.71 seconds
Started Jul 27 06:16:13 PM PDT 24
Finished Jul 27 06:16:13 PM PDT 24
Peak memory 201476 kb
Host smart-4493c7a0-ac0b-4d58-85b2-50fcc62cf14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148152052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1148152052
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.541264381
Short name T172
Test name
Test status
Simulation time 37360061 ps
CPU time 0.72 seconds
Started Jul 27 06:16:22 PM PDT 24
Finished Jul 27 06:16:23 PM PDT 24
Peak memory 201456 kb
Host smart-de04a6c9-94e1-4e47-877c-b91c0bba248c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541264381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invali
d.541264381
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.4242352974
Short name T203
Test name
Test status
Simulation time 43841035 ps
CPU time 0.73 seconds
Started Jul 27 06:16:14 PM PDT 24
Finished Jul 27 06:16:15 PM PDT 24
Peak memory 199188 kb
Host smart-724e3606-3d61-4f15-a2d8-8271c8bf26de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242352974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.4242352974
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.3769049618
Short name T185
Test name
Test status
Simulation time 43379938 ps
CPU time 0.71 seconds
Started Jul 27 06:13:24 PM PDT 24
Finished Jul 27 06:13:25 PM PDT 24
Peak memory 201396 kb
Host smart-9037143c-e0ea-4dd9-a0e1-50ecf8f333ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769049618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.3769049618
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.2765782162
Short name T147
Test name
Test status
Simulation time 182391920 ps
CPU time 1.57 seconds
Started Jul 27 06:13:22 PM PDT 24
Finished Jul 27 06:13:24 PM PDT 24
Peak memory 201208 kb
Host smart-4cecd403-caf4-4320-9099-f644abdad6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765782162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.2765782162
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.327079361
Short name T71
Test name
Test status
Simulation time 74117065 ps
CPU time 0.65 seconds
Started Jul 27 06:13:29 PM PDT 24
Finished Jul 27 06:13:30 PM PDT 24
Peak memory 201408 kb
Host smart-922f41e7-88ab-4d49-809b-8edd92463ad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327079361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.327079361
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.310234230
Short name T642
Test name
Test status
Simulation time 188534456 ps
CPU time 1.6 seconds
Started Jul 27 06:19:53 PM PDT 24
Finished Jul 27 06:19:55 PM PDT 24
Peak memory 200996 kb
Host smart-d2ba9ca3-8392-4a94-9918-1bbe2995c8df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310234230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
310234230
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.2090034288
Short name T18
Test name
Test status
Simulation time 62484707 ps
CPU time 0.69 seconds
Started Jul 27 06:12:09 PM PDT 24
Finished Jul 27 06:12:10 PM PDT 24
Peak memory 198108 kb
Host smart-13a3fd7e-1d92-4f17-a92a-d78ef2222603
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090034288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.2090034288
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1274653520
Short name T662
Test name
Test status
Simulation time 71651463 ps
CPU time 1.01 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:51 PM PDT 24
Peak memory 195540 kb
Host smart-32838489-cbc1-456a-9555-dbb1f9541efe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274653520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1
274653520
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1868328601
Short name T66
Test name
Test status
Simulation time 74575347 ps
CPU time 2.88 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:59 PM PDT 24
Peak memory 199516 kb
Host smart-068f80f7-cc61-45b9-a9d4-1e0face21445
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868328601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1
868328601
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.68514997
Short name T105
Test name
Test status
Simulation time 36262994 ps
CPU time 0.7 seconds
Started Jul 27 06:19:47 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 198212 kb
Host smart-e653f3c6-f3db-48e3-a287-4df23a77f3c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68514997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.68514997
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.404847160
Short name T647
Test name
Test status
Simulation time 32630022 ps
CPU time 0.78 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 195768 kb
Host smart-7578c78b-3095-4244-9800-3a683a9290e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404847160 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.404847160
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.214503416
Short name T688
Test name
Test status
Simulation time 46720070 ps
CPU time 0.62 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:53 PM PDT 24
Peak memory 195560 kb
Host smart-16b89aa4-8bcd-4401-97ef-626abf37cf6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214503416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.214503416
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1266369735
Short name T735
Test name
Test status
Simulation time 72376193 ps
CPU time 0.81 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195680 kb
Host smart-b7d37020-6e9d-4b93-9cd7-e4b44dad71c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266369735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1266369735
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3530368598
Short name T682
Test name
Test status
Simulation time 186229290 ps
CPU time 1.93 seconds
Started Jul 27 06:19:47 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 196828 kb
Host smart-63ad5153-a7a3-42e2-aa35-a94593ef83a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530368598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3530368598
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.4279402194
Short name T646
Test name
Test status
Simulation time 861022101 ps
CPU time 3.25 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:53 PM PDT 24
Peak memory 200828 kb
Host smart-3624044a-1848-4ecd-9bf9-c1928696b284
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279402194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.4
279402194
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3440397015
Short name T104
Test name
Test status
Simulation time 40281106 ps
CPU time 0.62 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 195616 kb
Host smart-2c88b828-da92-4195-970b-b52515727612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440397015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
440397015
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1356549240
Short name T711
Test name
Test status
Simulation time 67780465 ps
CPU time 0.74 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:53 PM PDT 24
Peak memory 195796 kb
Host smart-dc15fb1b-1d3c-4f93-b24e-56c372114f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356549240 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1356549240
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1784880060
Short name T684
Test name
Test status
Simulation time 71062118 ps
CPU time 0.66 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195656 kb
Host smart-0cf5457a-c853-4709-8914-e1002b7fe5e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784880060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1784880060
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1818067491
Short name T726
Test name
Test status
Simulation time 20227298 ps
CPU time 0.64 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:57 PM PDT 24
Peak memory 195504 kb
Host smart-009ea26c-9cfc-43f0-b927-9a6ad287c453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818067491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1818067491
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.264774388
Short name T114
Test name
Test status
Simulation time 93098189 ps
CPU time 0.76 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 195636 kb
Host smart-7c085db2-eeaf-4a72-a5f1-9c99243c55a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264774388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.264774388
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2015044372
Short name T638
Test name
Test status
Simulation time 131041387 ps
CPU time 1.76 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:51 PM PDT 24
Peak memory 201244 kb
Host smart-1656de4f-61a7-457a-a0a4-762d102a11e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015044372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2015044372
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3108470020
Short name T25
Test name
Test status
Simulation time 289228065 ps
CPU time 1.56 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:54 PM PDT 24
Peak memory 195900 kb
Host smart-3ffda2c2-f879-4e95-89b8-be6e371ea8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108470020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3108470020
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3258039920
Short name T127
Test name
Test status
Simulation time 121303106 ps
CPU time 0.93 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 196692 kb
Host smart-bffebc48-f946-4d1b-9084-ee1002c83823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258039920 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.3258039920
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2487416894
Short name T698
Test name
Test status
Simulation time 82273185 ps
CPU time 0.62 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195664 kb
Host smart-996ff037-fd96-4e6a-956b-c40da1c7e141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487416894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2487416894
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3251639499
Short name T732
Test name
Test status
Simulation time 41654310 ps
CPU time 0.63 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195576 kb
Host smart-4a2eee82-49a6-40c5-8b5e-e04a9f56a831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251639499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3251639499
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3511670413
Short name T693
Test name
Test status
Simulation time 31690598 ps
CPU time 0.66 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 195700 kb
Host smart-36b6e70e-4b97-4949-a099-a3ae4e92fd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511670413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3511670413
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2393377357
Short name T703
Test name
Test status
Simulation time 111048527 ps
CPU time 2.38 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 197888 kb
Host smart-9c1d5dd3-8c8f-434d-b39a-b0b290e3b8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393377357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2393377357
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1006505581
Short name T737
Test name
Test status
Simulation time 143902358 ps
CPU time 1.08 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 200948 kb
Host smart-0ad5dfa9-f70b-4681-9b80-9c12c4d3c47b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006505581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1006505581
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1387209464
Short name T634
Test name
Test status
Simulation time 65367584 ps
CPU time 1.32 seconds
Started Jul 27 06:20:05 PM PDT 24
Finished Jul 27 06:20:06 PM PDT 24
Peak memory 199832 kb
Host smart-901b08cf-b8c3-4f30-8b1f-ea8922134d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387209464 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1387209464
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3994371970
Short name T685
Test name
Test status
Simulation time 74011822 ps
CPU time 0.66 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195668 kb
Host smart-d20fb196-09b4-41dd-9b32-5bec048ad3bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994371970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3994371970
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.350990408
Short name T689
Test name
Test status
Simulation time 18264539 ps
CPU time 0.6 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 195480 kb
Host smart-8a4e3cc7-6854-4f78-9a23-ba9faefed1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350990408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.350990408
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3766371320
Short name T700
Test name
Test status
Simulation time 43032408 ps
CPU time 0.94 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:13 PM PDT 24
Peak memory 199800 kb
Host smart-e863b0b5-32cc-43a2-90bb-9b2d36547746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766371320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3766371320
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.331704620
Short name T633
Test name
Test status
Simulation time 351442189 ps
CPU time 2.17 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 197916 kb
Host smart-5a7ead87-8bcb-4f3f-bc87-1a14732dd463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331704620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.331704620
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1475448156
Short name T670
Test name
Test status
Simulation time 303407705 ps
CPU time 1.46 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 201156 kb
Host smart-0b9bcc90-bd8c-47bb-b236-6f3df13b190c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475448156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1475448156
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1156179901
Short name T661
Test name
Test status
Simulation time 51091167 ps
CPU time 0.75 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195788 kb
Host smart-7c68e36d-aba4-4625-b341-2d0e6c22e7b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156179901 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1156179901
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3231565704
Short name T680
Test name
Test status
Simulation time 19008915 ps
CPU time 0.66 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 198780 kb
Host smart-096051c1-cbb7-4ab9-9507-33df8ab72ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231565704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3231565704
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.772136790
Short name T733
Test name
Test status
Simulation time 54964209 ps
CPU time 0.65 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 195544 kb
Host smart-1e424a2c-55f8-4c28-bc60-fb00da12bf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772136790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.772136790
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.933793171
Short name T669
Test name
Test status
Simulation time 144013346 ps
CPU time 0.94 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 200336 kb
Host smart-6bc0b76b-640c-43c6-bb82-c22d0b0d03e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933793171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sa
me_csr_outstanding.933793171
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3112449857
Short name T83
Test name
Test status
Simulation time 110325564 ps
CPU time 1.58 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 196900 kb
Host smart-2fa43c8d-0b34-4ca3-b008-1e459d5e385a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112449857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3112449857
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2437221497
Short name T668
Test name
Test status
Simulation time 288850847 ps
CPU time 1.63 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 201144 kb
Host smart-2172040b-8143-44db-8fa0-46adb2364cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437221497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.2437221497
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.624777163
Short name T649
Test name
Test status
Simulation time 45331529 ps
CPU time 0.91 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195788 kb
Host smart-115f2426-e4b0-4ec2-b692-7b2fede20258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624777163 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.624777163
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3961287200
Short name T694
Test name
Test status
Simulation time 24821594 ps
CPU time 0.64 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:11 PM PDT 24
Peak memory 197708 kb
Host smart-878ec613-9f29-4bb3-802b-1f51181b4948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961287200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3961287200
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4091093319
Short name T696
Test name
Test status
Simulation time 122630365 ps
CPU time 0.86 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 198944 kb
Host smart-ebe7a83a-5441-4f1a-a6e9-827e374ac702
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091093319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.4091093319
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.829287569
Short name T736
Test name
Test status
Simulation time 139838748 ps
CPU time 2.12 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 196980 kb
Host smart-b310882b-b78d-486f-af97-a516203fe029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829287569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.829287569
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3141829231
Short name T731
Test name
Test status
Simulation time 245246304 ps
CPU time 1.06 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 200748 kb
Host smart-22b94ce1-e5ee-40ef-9f51-e86a3daa6380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141829231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3141829231
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1628712879
Short name T81
Test name
Test status
Simulation time 59159821 ps
CPU time 1.03 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195772 kb
Host smart-e6b7cc14-575f-439d-944d-ebeaa61f4fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628712879 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1628712879
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1703813622
Short name T656
Test name
Test status
Simulation time 193771307 ps
CPU time 0.62 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195648 kb
Host smart-295cf314-c1a1-44fc-8e91-75c090ef10ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703813622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1703813622
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3486994555
Short name T111
Test name
Test status
Simulation time 83778984 ps
CPU time 0.79 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 197884 kb
Host smart-d5778886-212d-42d2-af7e-99328084ca5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486994555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3486994555
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3559178780
Short name T654
Test name
Test status
Simulation time 129759782 ps
CPU time 2.33 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:14 PM PDT 24
Peak memory 196464 kb
Host smart-0f12fafd-03d6-4120-85ba-3bd31656e5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559178780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3559178780
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3295474402
Short name T86
Test name
Test status
Simulation time 183059306 ps
CPU time 1.62 seconds
Started Jul 27 06:20:10 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 201120 kb
Host smart-13df1c6b-096b-4245-afa0-5473cc36e8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295474402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3295474402
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.162005651
Short name T116
Test name
Test status
Simulation time 16328146 ps
CPU time 0.63 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195652 kb
Host smart-93b5fdf7-c23a-4f36-afd4-a7be4613d1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162005651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.162005651
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1580059063
Short name T686
Test name
Test status
Simulation time 48411453 ps
CPU time 0.61 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:13 PM PDT 24
Peak memory 195568 kb
Host smart-01ca30bd-3b76-4d9a-bbf8-ae338dd532e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580059063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1580059063
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.497760454
Short name T641
Test name
Test status
Simulation time 59580457 ps
CPU time 0.82 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195652 kb
Host smart-dbf3c70f-3972-4c56-9ae0-f5d9a5687171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497760454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.497760454
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3759201724
Short name T657
Test name
Test status
Simulation time 275380776 ps
CPU time 1.22 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 196096 kb
Host smart-e6cd4483-797d-4546-949d-7d2f0287d643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759201724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3759201724
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2402606621
Short name T645
Test name
Test status
Simulation time 111063207 ps
CPU time 1.2 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 200328 kb
Host smart-35b7c027-f564-4d85-a96f-e40903e2cf07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402606621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2402606621
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4241058911
Short name T707
Test name
Test status
Simulation time 62447143 ps
CPU time 0.71 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 200416 kb
Host smart-ec35f6ec-6ec6-411d-8078-0eee6a654878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241058911 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.4241058911
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.519191612
Short name T115
Test name
Test status
Simulation time 19581705 ps
CPU time 0.65 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195648 kb
Host smart-7bb122b0-61d1-4d70-b64c-52e056a99ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519191612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.519191612
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1891400309
Short name T665
Test name
Test status
Simulation time 47257701 ps
CPU time 0.63 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 195620 kb
Host smart-a803f908-f816-4580-a7b1-33495bc9a65d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891400309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1891400309
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3828896723
Short name T643
Test name
Test status
Simulation time 144269203 ps
CPU time 0.85 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195712 kb
Host smart-cc769993-70f5-439b-abcf-1d4565b30529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828896723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3828896723
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3256934454
Short name T699
Test name
Test status
Simulation time 73998946 ps
CPU time 1.55 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:13 PM PDT 24
Peak memory 201252 kb
Host smart-fe30552e-f9b7-46b0-a411-ecbb0265b00b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256934454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3256934454
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2350634199
Short name T151
Test name
Test status
Simulation time 259848910 ps
CPU time 1.04 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 201160 kb
Host smart-c73706c7-d2ed-42a4-8c62-13869880ba27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350634199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2350634199
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.432724033
Short name T74
Test name
Test status
Simulation time 273474281 ps
CPU time 0.97 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 195812 kb
Host smart-e6e9ad0d-3441-4c36-84e8-3f16a121b3d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432724033 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.432724033
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3473144234
Short name T719
Test name
Test status
Simulation time 44081080 ps
CPU time 0.64 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 197804 kb
Host smart-5adc8eaa-07fa-45cc-aa39-2bd6d74a6107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473144234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3473144234
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.16804209
Short name T674
Test name
Test status
Simulation time 49165365 ps
CPU time 0.63 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:13 PM PDT 24
Peak memory 195552 kb
Host smart-f2a4275e-7661-44c8-8d3a-1c7e514afc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16804209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.16804209
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1709643765
Short name T709
Test name
Test status
Simulation time 120891472 ps
CPU time 0.71 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 195708 kb
Host smart-e896a244-e296-48c6-b901-3d378cfd0c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709643765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.1709643765
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3542341499
Short name T26
Test name
Test status
Simulation time 125625455 ps
CPU time 1.29 seconds
Started Jul 27 06:20:10 PM PDT 24
Finished Jul 27 06:20:11 PM PDT 24
Peak memory 197940 kb
Host smart-e614060d-66f4-4c09-b87c-24688acba5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542341499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3542341499
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2209813828
Short name T730
Test name
Test status
Simulation time 177199094 ps
CPU time 1.56 seconds
Started Jul 27 06:20:10 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 201172 kb
Host smart-daa17449-e53c-4271-ba5b-4c629a98712c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209813828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.2209813828
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.263276714
Short name T713
Test name
Test status
Simulation time 71119298 ps
CPU time 0.95 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 201052 kb
Host smart-e5a3bbb8-c0f7-49e3-80b6-663970872afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263276714 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.263276714
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2527126734
Short name T107
Test name
Test status
Simulation time 23932302 ps
CPU time 0.69 seconds
Started Jul 27 06:20:18 PM PDT 24
Finished Jul 27 06:20:19 PM PDT 24
Peak memory 195668 kb
Host smart-12cdef6d-5d1c-435a-a349-ffeadfb656dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527126734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2527126734
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2464767462
Short name T630
Test name
Test status
Simulation time 29566139 ps
CPU time 0.61 seconds
Started Jul 27 06:20:20 PM PDT 24
Finished Jul 27 06:20:20 PM PDT 24
Peak memory 195540 kb
Host smart-ee69c418-f66e-4ba0-846d-6612cd7767da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464767462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2464767462
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2912646691
Short name T110
Test name
Test status
Simulation time 27734448 ps
CPU time 0.72 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 197892 kb
Host smart-8e07bfa9-a2e1-4e77-b4d4-9c214c899967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912646691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2912646691
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2917287434
Short name T63
Test name
Test status
Simulation time 31345977 ps
CPU time 1.31 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 201236 kb
Host smart-e4ecec44-bc4d-413a-8e66-c124034f1d41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917287434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.2917287434
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2075417084
Short name T734
Test name
Test status
Simulation time 57028722 ps
CPU time 0.74 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 195976 kb
Host smart-f47d5340-3854-40a9-8233-da87c780d3c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075417084 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2075417084
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2771866638
Short name T109
Test name
Test status
Simulation time 21564088 ps
CPU time 0.67 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195684 kb
Host smart-702181a5-9517-419c-b52d-86db9527bc96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771866638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2771866638
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.212602159
Short name T667
Test name
Test status
Simulation time 27737894 ps
CPU time 0.61 seconds
Started Jul 27 06:20:20 PM PDT 24
Finished Jul 27 06:20:21 PM PDT 24
Peak memory 195564 kb
Host smart-aa0459f0-012d-46b2-b8ce-0524bfb9fea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212602159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.212602159
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1573395521
Short name T728
Test name
Test status
Simulation time 32669663 ps
CPU time 0.72 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 197868 kb
Host smart-3ebb8da9-9008-43e9-a786-5a7bed2c5e86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573395521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1573395521
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.174146445
Short name T673
Test name
Test status
Simulation time 642818895 ps
CPU time 2.79 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:20 PM PDT 24
Peak memory 197020 kb
Host smart-7a7f5012-e5da-4577-ac36-fcc74518d2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174146445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.174146445
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1404532739
Short name T706
Test name
Test status
Simulation time 37989408 ps
CPU time 1 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 200628 kb
Host smart-9ae76ec6-186a-4f02-9da0-43aeb0c07138
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404532739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1
404532739
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4041280428
Short name T664
Test name
Test status
Simulation time 180038324 ps
CPU time 2.69 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:52 PM PDT 24
Peak memory 195728 kb
Host smart-10ee18b7-51f3-4ef8-99dc-54693ea99617
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041280428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.4
041280428
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.906312852
Short name T635
Test name
Test status
Simulation time 37220817 ps
CPU time 0.71 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:51 PM PDT 24
Peak memory 197812 kb
Host smart-87833ae2-46cb-4063-be43-3c8424a9e21c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906312852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.906312852
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3297441877
Short name T690
Test name
Test status
Simulation time 56409933 ps
CPU time 0.87 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195976 kb
Host smart-914d9b75-2d8c-4c4f-a1e7-728a1320399c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297441877 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.3297441877
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2393116163
Short name T113
Test name
Test status
Simulation time 45876549 ps
CPU time 0.67 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 197772 kb
Host smart-5d0ab3a1-feac-4f3b-bd0c-c9bcbbfd6fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393116163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2393116163
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1711626166
Short name T76
Test name
Test status
Simulation time 52948621 ps
CPU time 0.61 seconds
Started Jul 27 06:19:47 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 195552 kb
Host smart-980b6f43-a849-402d-bf4c-f1d46e261b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711626166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1711626166
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.971690383
Short name T112
Test name
Test status
Simulation time 27888577 ps
CPU time 0.73 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195600 kb
Host smart-71343da1-1b92-4465-b639-1e50e6fef28e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971690383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sam
e_csr_outstanding.971690383
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1950299940
Short name T683
Test name
Test status
Simulation time 248467294 ps
CPU time 1.1 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:57 PM PDT 24
Peak memory 195848 kb
Host smart-83b787d0-9c56-425b-b2b7-aaa82dec86f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950299940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1950299940
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2877512275
Short name T632
Test name
Test status
Simulation time 18915802 ps
CPU time 0.63 seconds
Started Jul 27 06:20:19 PM PDT 24
Finished Jul 27 06:20:19 PM PDT 24
Peak memory 195552 kb
Host smart-c00a1799-d0ed-4ff4-99e7-3b7f37b2ab30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877512275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2877512275
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1922856198
Short name T718
Test name
Test status
Simulation time 20873583 ps
CPU time 0.6 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195532 kb
Host smart-1fd603b6-fb2a-4bad-82cc-886c660eec17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922856198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.1922856198
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3113327653
Short name T721
Test name
Test status
Simulation time 23266092 ps
CPU time 0.6 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195604 kb
Host smart-4e3073d9-75b2-4378-96d6-ed59461b771c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113327653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3113327653
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1988172239
Short name T672
Test name
Test status
Simulation time 15707915 ps
CPU time 0.62 seconds
Started Jul 27 06:20:15 PM PDT 24
Finished Jul 27 06:20:16 PM PDT 24
Peak memory 195560 kb
Host smart-a5597932-4b45-4040-a5a7-de15c120550a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988172239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1988172239
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3106971669
Short name T675
Test name
Test status
Simulation time 47064776 ps
CPU time 0.62 seconds
Started Jul 27 06:20:19 PM PDT 24
Finished Jul 27 06:20:20 PM PDT 24
Peak memory 195568 kb
Host smart-29621976-2227-447d-87a4-b42af921dca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106971669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3106971669
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2194442482
Short name T691
Test name
Test status
Simulation time 36061791 ps
CPU time 0.65 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195568 kb
Host smart-8040c818-08b3-47f0-90fe-b5bd7c7a7c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194442482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2194442482
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3118486897
Short name T640
Test name
Test status
Simulation time 59726628 ps
CPU time 0.62 seconds
Started Jul 27 06:20:20 PM PDT 24
Finished Jul 27 06:20:21 PM PDT 24
Peak memory 195564 kb
Host smart-aa344470-af0b-489d-a1b5-d3c00f9efcb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118486897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3118486897
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.555101462
Short name T671
Test name
Test status
Simulation time 55028133 ps
CPU time 0.63 seconds
Started Jul 27 06:20:18 PM PDT 24
Finished Jul 27 06:20:19 PM PDT 24
Peak memory 195568 kb
Host smart-141bde16-c519-48cd-a174-8b01b3f20ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555101462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.555101462
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.474276288
Short name T704
Test name
Test status
Simulation time 47013690 ps
CPU time 0.6 seconds
Started Jul 27 06:20:16 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195564 kb
Host smart-b84fe4e1-4ec6-40de-9bc8-1add0ed93038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474276288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.474276288
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1926967664
Short name T701
Test name
Test status
Simulation time 49693517 ps
CPU time 0.63 seconds
Started Jul 27 06:20:20 PM PDT 24
Finished Jul 27 06:20:21 PM PDT 24
Peak memory 195564 kb
Host smart-c7eb92fb-bdd5-4924-8dca-3ffab91924d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926967664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1926967664
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1247196226
Short name T125
Test name
Test status
Simulation time 51152737 ps
CPU time 0.85 seconds
Started Jul 27 06:19:46 PM PDT 24
Finished Jul 27 06:19:47 PM PDT 24
Peak memory 197780 kb
Host smart-66b520e1-529e-421c-86be-3bb0f62b4cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247196226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1
247196226
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3822584211
Short name T653
Test name
Test status
Simulation time 1187150885 ps
CPU time 1.98 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:52 PM PDT 24
Peak memory 195812 kb
Host smart-054cbf60-c772-4487-8d4e-6e28b0a8388d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822584211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.3
822584211
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2917259130
Short name T715
Test name
Test status
Simulation time 35251015 ps
CPU time 0.66 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:57 PM PDT 24
Peak memory 195624 kb
Host smart-ac5d4f64-6eed-48bb-8ff2-c2c5fc357aeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917259130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
917259130
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.73909457
Short name T651
Test name
Test status
Simulation time 71912117 ps
CPU time 0.98 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:53 PM PDT 24
Peak memory 195796 kb
Host smart-91aaf624-9dfb-4217-94c0-15e7ff829182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73909457 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.73909457
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1358136594
Short name T695
Test name
Test status
Simulation time 21667721 ps
CPU time 0.7 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:49 PM PDT 24
Peak memory 197784 kb
Host smart-c03d78b1-3a48-487e-a769-cd6ec2c31b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358136594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1358136594
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1247837428
Short name T627
Test name
Test status
Simulation time 40667720 ps
CPU time 0.63 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195584 kb
Host smart-dc188c5d-072c-4d9d-97e7-4c2d7adbad26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247837428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1247837428
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.937779701
Short name T648
Test name
Test status
Simulation time 19269548 ps
CPU time 0.69 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 197884 kb
Host smart-ebf39da5-ae4c-4209-9881-5f9c3fce7cc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937779701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.937779701
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1481072560
Short name T126
Test name
Test status
Simulation time 152347169 ps
CPU time 2.83 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:54 PM PDT 24
Peak memory 198072 kb
Host smart-d1992dbd-9949-4d9f-aa2c-6f048f108fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481072560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1481072560
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1134636509
Short name T149
Test name
Test status
Simulation time 178772569 ps
CPU time 1.61 seconds
Started Jul 27 06:19:51 PM PDT 24
Finished Jul 27 06:19:52 PM PDT 24
Peak memory 195912 kb
Host smart-78de0747-4c3f-4e92-b5b0-801d1ce15f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134636509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1134636509
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3079711935
Short name T77
Test name
Test status
Simulation time 60725105 ps
CPU time 0.63 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195560 kb
Host smart-4c26b320-f6d7-4625-8ef2-55e58bfd5a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079711935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3079711935
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2862672715
Short name T666
Test name
Test status
Simulation time 60915370 ps
CPU time 0.6 seconds
Started Jul 27 06:20:19 PM PDT 24
Finished Jul 27 06:20:20 PM PDT 24
Peak memory 195560 kb
Host smart-c178d325-86e9-4f8c-b9c0-57120d3315b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862672715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2862672715
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3088722525
Short name T712
Test name
Test status
Simulation time 16983640 ps
CPU time 0.64 seconds
Started Jul 27 06:20:15 PM PDT 24
Finished Jul 27 06:20:16 PM PDT 24
Peak memory 195532 kb
Host smart-f4cf7bf0-3e3b-4cec-b4f9-e5956642e5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088722525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3088722525
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4045441529
Short name T658
Test name
Test status
Simulation time 16270967 ps
CPU time 0.62 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:18 PM PDT 24
Peak memory 195540 kb
Host smart-20f4e7fb-bfef-4368-8a66-f407c5b46599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045441529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4045441529
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2078168883
Short name T727
Test name
Test status
Simulation time 21984977 ps
CPU time 0.6 seconds
Started Jul 27 06:20:20 PM PDT 24
Finished Jul 27 06:20:21 PM PDT 24
Peak memory 195540 kb
Host smart-b60bdf61-588e-4434-8cf5-c8ba26e83fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078168883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2078168883
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.672918891
Short name T655
Test name
Test status
Simulation time 28338949 ps
CPU time 0.6 seconds
Started Jul 27 06:20:17 PM PDT 24
Finished Jul 27 06:20:17 PM PDT 24
Peak memory 195560 kb
Host smart-1d33e2f1-1659-42df-9b83-a5f4078402dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672918891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.672918891
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.205391530
Short name T631
Test name
Test status
Simulation time 33471752 ps
CPU time 0.62 seconds
Started Jul 27 06:20:19 PM PDT 24
Finished Jul 27 06:20:20 PM PDT 24
Peak memory 195556 kb
Host smart-6a9459a4-4637-42cc-aadd-7fa82ef6c3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205391530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.205391530
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3608740
Short name T723
Test name
Test status
Simulation time 48462583 ps
CPU time 0.64 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 195564 kb
Host smart-95d49081-c1e7-47a2-9a28-b6b4570a164c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3608740
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.346396214
Short name T75
Test name
Test status
Simulation time 52680980 ps
CPU time 0.61 seconds
Started Jul 27 06:20:25 PM PDT 24
Finished Jul 27 06:20:26 PM PDT 24
Peak memory 195580 kb
Host smart-28634683-fdc8-495f-90bc-aebf6537785e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346396214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.346396214
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2862186201
Short name T679
Test name
Test status
Simulation time 107697072 ps
CPU time 0.61 seconds
Started Jul 27 06:20:30 PM PDT 24
Finished Jul 27 06:20:30 PM PDT 24
Peak memory 195580 kb
Host smart-7e56eaea-2a53-4f54-9c67-20027ebe7401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862186201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2862186201
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2032399204
Short name T103
Test name
Test status
Simulation time 27397524 ps
CPU time 0.95 seconds
Started Jul 27 06:19:58 PM PDT 24
Finished Jul 27 06:19:59 PM PDT 24
Peak memory 199012 kb
Host smart-f469a588-b584-48f2-be76-61cf533900c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032399204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2
032399204
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1202547768
Short name T626
Test name
Test status
Simulation time 812207136 ps
CPU time 2.7 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:20:00 PM PDT 24
Peak memory 195692 kb
Host smart-2feb586e-7c94-4095-b6c2-7b30a79ab17e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202547768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
202547768
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1156781575
Short name T678
Test name
Test status
Simulation time 35115846 ps
CPU time 0.7 seconds
Started Jul 27 06:19:59 PM PDT 24
Finished Jul 27 06:20:00 PM PDT 24
Peak memory 195608 kb
Host smart-c22b0401-6161-467e-b7f7-440c50faeee9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156781575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
156781575
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3584507785
Short name T80
Test name
Test status
Simulation time 42973773 ps
CPU time 0.8 seconds
Started Jul 27 06:20:02 PM PDT 24
Finished Jul 27 06:20:03 PM PDT 24
Peak memory 195772 kb
Host smart-0090acd6-ed57-4540-bda2-e0d102249073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584507785 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3584507785
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2867260909
Short name T722
Test name
Test status
Simulation time 31705084 ps
CPU time 0.68 seconds
Started Jul 27 06:19:59 PM PDT 24
Finished Jul 27 06:20:00 PM PDT 24
Peak memory 195608 kb
Host smart-eebe15e2-e297-437f-8cfa-51bb909992ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867260909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2867260909
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2773024599
Short name T660
Test name
Test status
Simulation time 19168074 ps
CPU time 0.61 seconds
Started Jul 27 06:19:50 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195532 kb
Host smart-fea3ff46-5882-49a2-958d-e15282ad661b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773024599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2773024599
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3630530092
Short name T729
Test name
Test status
Simulation time 109258196 ps
CPU time 0.85 seconds
Started Jul 27 06:19:59 PM PDT 24
Finished Jul 27 06:20:01 PM PDT 24
Peak memory 200300 kb
Host smart-61c60a15-eebb-4af0-95b3-cf15e2b311e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630530092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3630530092
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3156261327
Short name T87
Test name
Test status
Simulation time 148776470 ps
CPU time 1.44 seconds
Started Jul 27 06:19:52 PM PDT 24
Finished Jul 27 06:19:54 PM PDT 24
Peak memory 196892 kb
Host smart-b39990ee-de55-461a-9b58-c99da59e84f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156261327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3156261327
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2309956155
Short name T697
Test name
Test status
Simulation time 404513192 ps
CPU time 1.09 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195724 kb
Host smart-f9e4be38-fa9a-44cb-ad70-7c4cd04a71b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309956155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2309956155
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2268389741
Short name T716
Test name
Test status
Simulation time 18073874 ps
CPU time 0.61 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:20:29 PM PDT 24
Peak memory 195540 kb
Host smart-c2a0587e-7591-4b2b-b74b-99271c1f4165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268389741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2268389741
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2120679510
Short name T625
Test name
Test status
Simulation time 18002081 ps
CPU time 0.62 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:27 PM PDT 24
Peak memory 195568 kb
Host smart-d7473f3c-6756-4329-ab5a-60f303d7ebe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120679510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.2120679510
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2508217343
Short name T650
Test name
Test status
Simulation time 37140639 ps
CPU time 0.63 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 195552 kb
Host smart-e6d4ea8f-0009-4776-8845-c7681b05ddd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508217343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.2508217343
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2826477488
Short name T629
Test name
Test status
Simulation time 16820336 ps
CPU time 0.62 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:26 PM PDT 24
Peak memory 195536 kb
Host smart-a9cf4f60-02ac-4f72-9104-0d098e02b7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826477488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2826477488
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.845787268
Short name T692
Test name
Test status
Simulation time 35109371 ps
CPU time 0.59 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:29 PM PDT 24
Peak memory 195764 kb
Host smart-fa5ed770-4bd0-4518-af37-c5e1ef597f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845787268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.845787268
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.28549727
Short name T162
Test name
Test status
Simulation time 37683030 ps
CPU time 0.6 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:27 PM PDT 24
Peak memory 195496 kb
Host smart-6b93b2c0-1879-4600-96f6-c53ce8e9285a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28549727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.28549727
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3882858845
Short name T717
Test name
Test status
Simulation time 51951838 ps
CPU time 0.65 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 195532 kb
Host smart-8445c45d-352e-4308-84f0-9f6835058d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882858845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3882858845
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1710364416
Short name T708
Test name
Test status
Simulation time 29216062 ps
CPU time 0.63 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 195520 kb
Host smart-9bf691eb-076c-4fe6-aab5-ea39d9ae023f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710364416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1710364416
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2673289079
Short name T652
Test name
Test status
Simulation time 42796029 ps
CPU time 0.64 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:30 PM PDT 24
Peak memory 195484 kb
Host smart-042ca357-f8c8-4ce8-a47c-dbfb56feb08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673289079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2673289079
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1354241244
Short name T644
Test name
Test status
Simulation time 20004258 ps
CPU time 0.61 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:30 PM PDT 24
Peak memory 195564 kb
Host smart-f0153df7-d1a6-4436-8d47-9e89205bbee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354241244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1354241244
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3754263891
Short name T687
Test name
Test status
Simulation time 57831246 ps
CPU time 0.96 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:19:58 PM PDT 24
Peak memory 195776 kb
Host smart-a443b94d-9f4a-4861-acc9-070cab68f4e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754263891 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3754263891
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1820896711
Short name T663
Test name
Test status
Simulation time 29053071 ps
CPU time 0.64 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:19:58 PM PDT 24
Peak memory 195620 kb
Host smart-58f2f33e-cf2f-46ba-a309-e7b7b677952e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820896711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1820896711
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3721904997
Short name T702
Test name
Test status
Simulation time 18769328 ps
CPU time 0.64 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:19:58 PM PDT 24
Peak memory 195464 kb
Host smart-34336948-c25c-4ecf-967a-9b748a6497a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721904997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3721904997
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2357925947
Short name T639
Test name
Test status
Simulation time 76617207 ps
CPU time 0.72 seconds
Started Jul 27 06:20:00 PM PDT 24
Finished Jul 27 06:20:01 PM PDT 24
Peak memory 197868 kb
Host smart-62a0b25d-a187-45e9-a3ae-dd9c933c8afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357925947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2357925947
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.4128957577
Short name T681
Test name
Test status
Simulation time 26392409 ps
CPU time 1.07 seconds
Started Jul 27 06:20:02 PM PDT 24
Finished Jul 27 06:20:03 PM PDT 24
Peak memory 196696 kb
Host smart-36ce508b-70fb-4583-bd2c-a9306e734380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128957577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.4128957577
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2349834060
Short name T85
Test name
Test status
Simulation time 194182537 ps
CPU time 1.81 seconds
Started Jul 27 06:20:01 PM PDT 24
Finished Jul 27 06:20:03 PM PDT 24
Peak memory 195908 kb
Host smart-4dd1af0f-801b-46ba-8ad4-4b99d0c8a9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349834060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2349834060
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.310240343
Short name T82
Test name
Test status
Simulation time 54411530 ps
CPU time 0.94 seconds
Started Jul 27 06:20:00 PM PDT 24
Finished Jul 27 06:20:01 PM PDT 24
Peak memory 195792 kb
Host smart-c4134271-7067-4866-9211-bc608601416a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310240343 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.310240343
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1184894675
Short name T714
Test name
Test status
Simulation time 16238192 ps
CPU time 0.62 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:56 PM PDT 24
Peak memory 195748 kb
Host smart-9d52bcba-e2fc-43a7-a9bd-fe9bc76fa5f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184894675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1184894675
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.373821628
Short name T161
Test name
Test status
Simulation time 52443236 ps
CPU time 0.62 seconds
Started Jul 27 06:19:56 PM PDT 24
Finished Jul 27 06:19:57 PM PDT 24
Peak memory 195548 kb
Host smart-c3ca622e-6716-43a7-9593-2df58081aba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373821628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.373821628
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.992373464
Short name T65
Test name
Test status
Simulation time 21493250 ps
CPU time 0.73 seconds
Started Jul 27 06:19:58 PM PDT 24
Finished Jul 27 06:19:59 PM PDT 24
Peak memory 197900 kb
Host smart-3e6e4734-2f26-4bd0-9994-c6e41488fe9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992373464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.992373464
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.259769239
Short name T659
Test name
Test status
Simulation time 117304026 ps
CPU time 1.39 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:19:59 PM PDT 24
Peak memory 197916 kb
Host smart-5d79a827-5d31-49aa-aab9-2e45f2030719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259769239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.259769239
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3549580553
Short name T62
Test name
Test status
Simulation time 206308880 ps
CPU time 1.73 seconds
Started Jul 27 06:19:58 PM PDT 24
Finished Jul 27 06:20:00 PM PDT 24
Peak memory 201008 kb
Host smart-a6c589fd-6e85-4807-8d04-c943304c374c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549580553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3549580553
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1016801076
Short name T84
Test name
Test status
Simulation time 161750560 ps
CPU time 1.26 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 198156 kb
Host smart-067cc2aa-ad6f-4a92-9bf3-e2bebb8bb43e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016801076 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1016801076
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1776984563
Short name T108
Test name
Test status
Simulation time 125391873 ps
CPU time 0.61 seconds
Started Jul 27 06:19:57 PM PDT 24
Finished Jul 27 06:19:58 PM PDT 24
Peak memory 197972 kb
Host smart-de179c9e-6971-49b7-9749-912bb374c290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776984563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1776984563
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2577901615
Short name T724
Test name
Test status
Simulation time 54271504 ps
CPU time 0.66 seconds
Started Jul 27 06:20:01 PM PDT 24
Finished Jul 27 06:20:01 PM PDT 24
Peak memory 195568 kb
Host smart-b560be46-226b-45d4-be87-977d60e9b1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577901615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2577901615
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1915816231
Short name T725
Test name
Test status
Simulation time 41880644 ps
CPU time 0.72 seconds
Started Jul 27 06:19:59 PM PDT 24
Finished Jul 27 06:20:00 PM PDT 24
Peak memory 195648 kb
Host smart-7c583f7f-0a3b-4cf3-8172-4ae6a42f8b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915816231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1915816231
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.213719159
Short name T720
Test name
Test status
Simulation time 78089152 ps
CPU time 1.86 seconds
Started Jul 27 06:20:03 PM PDT 24
Finished Jul 27 06:20:05 PM PDT 24
Peak memory 198156 kb
Host smart-67c43269-af74-442e-a9fd-d13d501585d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213719159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.213719159
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.468417583
Short name T79
Test name
Test status
Simulation time 424602717 ps
CPU time 1.53 seconds
Started Jul 27 06:20:00 PM PDT 24
Finished Jul 27 06:20:02 PM PDT 24
Peak memory 201028 kb
Host smart-996edfe6-70e9-4fc7-a731-70384771dea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468417583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.
468417583
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.108849047
Short name T637
Test name
Test status
Simulation time 55925533 ps
CPU time 1.48 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 198680 kb
Host smart-00bf5138-bc6e-452c-9e3a-c3b1f68e97e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108849047 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.108849047
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3605941671
Short name T102
Test name
Test status
Simulation time 21732402 ps
CPU time 0.71 seconds
Started Jul 27 06:20:06 PM PDT 24
Finished Jul 27 06:20:07 PM PDT 24
Peak memory 195580 kb
Host smart-f065f3f7-d145-47ee-a430-95d10553086b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605941671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3605941671
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1421292882
Short name T160
Test name
Test status
Simulation time 52094085 ps
CPU time 0.62 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 195564 kb
Host smart-4e1638e9-a073-4ac1-91f6-b8618f1b17b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421292882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1421292882
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1932751181
Short name T117
Test name
Test status
Simulation time 44813079 ps
CPU time 0.89 seconds
Started Jul 27 06:20:05 PM PDT 24
Finished Jul 27 06:20:06 PM PDT 24
Peak memory 195692 kb
Host smart-128eceb4-7153-43c8-8be4-ccb78525d333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932751181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.1932751181
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2963144225
Short name T677
Test name
Test status
Simulation time 429164814 ps
CPU time 2.59 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:15 PM PDT 24
Peak memory 198132 kb
Host smart-c56dbc82-e007-4f27-b269-b5b6a557ec06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963144225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2963144225
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2308831645
Short name T705
Test name
Test status
Simulation time 200482328 ps
CPU time 1 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 200908 kb
Host smart-289715f0-318e-49e0-ae61-06fbe4bbd371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308831645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2308831645
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2241851482
Short name T128
Test name
Test status
Simulation time 44265232 ps
CPU time 0.76 seconds
Started Jul 27 06:20:12 PM PDT 24
Finished Jul 27 06:20:13 PM PDT 24
Peak memory 195712 kb
Host smart-51dca7e4-b65b-43ff-9dcd-c887107dfeea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241851482 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2241851482
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.3691988271
Short name T636
Test name
Test status
Simulation time 67123580 ps
CPU time 0.64 seconds
Started Jul 27 06:20:07 PM PDT 24
Finished Jul 27 06:20:08 PM PDT 24
Peak memory 197784 kb
Host smart-ac133200-3b20-477c-9a76-cbd298499886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691988271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.3691988271
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3187329141
Short name T676
Test name
Test status
Simulation time 20193637 ps
CPU time 0.61 seconds
Started Jul 27 06:20:11 PM PDT 24
Finished Jul 27 06:20:12 PM PDT 24
Peak memory 195556 kb
Host smart-1117e8dd-8a5d-4533-b095-5344f3741592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187329141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3187329141
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1968026363
Short name T710
Test name
Test status
Simulation time 48866750 ps
CPU time 0.68 seconds
Started Jul 27 06:20:08 PM PDT 24
Finished Jul 27 06:20:09 PM PDT 24
Peak memory 197848 kb
Host smart-158a7a57-f95c-4676-a5ac-b9e2c2df34d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968026363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.1968026363
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3403152692
Short name T60
Test name
Test status
Simulation time 47162933 ps
CPU time 1.18 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:10 PM PDT 24
Peak memory 196940 kb
Host smart-603b391e-ff09-4c02-a8b6-f827da646b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403152692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3403152692
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.758894298
Short name T150
Test name
Test status
Simulation time 182595752 ps
CPU time 1.64 seconds
Started Jul 27 06:20:09 PM PDT 24
Finished Jul 27 06:20:11 PM PDT 24
Peak memory 200932 kb
Host smart-cc594a1e-d3be-4692-a516-d58dbb556d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758894298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
758894298
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.2513506368
Short name T93
Test name
Test status
Simulation time 37457239 ps
CPU time 0.85 seconds
Started Jul 27 06:12:05 PM PDT 24
Finished Jul 27 06:12:06 PM PDT 24
Peak memory 200260 kb
Host smart-fce6c2c1-ee83-4647-82d9-64596807f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513506368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2513506368
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2834219127
Short name T577
Test name
Test status
Simulation time 64399862 ps
CPU time 0.69 seconds
Started Jul 27 06:12:09 PM PDT 24
Finished Jul 27 06:12:10 PM PDT 24
Peak memory 198496 kb
Host smart-0dade08b-579d-40a4-90b8-cca36ddf1f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834219127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2834219127
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.494485931
Short name T610
Test name
Test status
Simulation time 36885140 ps
CPU time 0.57 seconds
Started Jul 27 06:12:09 PM PDT 24
Finished Jul 27 06:12:10 PM PDT 24
Peak memory 198104 kb
Host smart-45829521-1d24-4da5-be16-1543bb7a3a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494485931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_m
alfunc.494485931
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3643060986
Short name T484
Test name
Test status
Simulation time 285912797 ps
CPU time 1.02 seconds
Started Jul 27 06:12:10 PM PDT 24
Finished Jul 27 06:12:11 PM PDT 24
Peak memory 198184 kb
Host smart-291cb62e-3600-4e2d-aa56-649a4acfca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643060986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3643060986
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.2592480746
Short name T356
Test name
Test status
Simulation time 28912817 ps
CPU time 0.61 seconds
Started Jul 27 06:12:09 PM PDT 24
Finished Jul 27 06:12:10 PM PDT 24
Peak memory 198488 kb
Host smart-38d0192d-53ab-427a-a966-b282274f1c6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592480746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2592480746
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.795476840
Short name T179
Test name
Test status
Simulation time 38100401 ps
CPU time 0.73 seconds
Started Jul 27 06:12:15 PM PDT 24
Finished Jul 27 06:12:16 PM PDT 24
Peak memory 201448 kb
Host smart-4937e11c-5215-4b2e-add5-0a76feda60ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795476840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.795476840
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.494722025
Short name T220
Test name
Test status
Simulation time 127426608 ps
CPU time 0.75 seconds
Started Jul 27 06:11:56 PM PDT 24
Finished Jul 27 06:11:57 PM PDT 24
Peak memory 199144 kb
Host smart-b174045e-8c12-4481-bd4c-7c84242add81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494722025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.494722025
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.232980796
Short name T23
Test name
Test status
Simulation time 462358450 ps
CPU time 1.15 seconds
Started Jul 27 06:12:16 PM PDT 24
Finished Jul 27 06:12:17 PM PDT 24
Peak memory 216956 kb
Host smart-0b1ca6ae-dc26-4ab6-9b64-0196916979db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232980796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.232980796
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2281799298
Short name T328
Test name
Test status
Simulation time 114517221 ps
CPU time 0.8 seconds
Started Jul 27 06:12:04 PM PDT 24
Finished Jul 27 06:12:05 PM PDT 24
Peak memory 199248 kb
Host smart-4521617c-8cf8-4d4c-ac59-21cf0083cf49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281799298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2281799298
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2430130578
Short name T387
Test name
Test status
Simulation time 36234552 ps
CPU time 0.66 seconds
Started Jul 27 06:11:49 PM PDT 24
Finished Jul 27 06:11:50 PM PDT 24
Peak memory 199416 kb
Host smart-358e1c18-95b9-4c8b-bad7-4d8a7eb64dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430130578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2430130578
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1284187243
Short name T165
Test name
Test status
Simulation time 114092771 ps
CPU time 0.66 seconds
Started Jul 27 06:12:30 PM PDT 24
Finished Jul 27 06:12:31 PM PDT 24
Peak memory 199560 kb
Host smart-b5ab0fd8-18c9-43f1-8669-fe5758ff7fee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284187243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1284187243
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2710872610
Short name T13
Test name
Test status
Simulation time 38350308 ps
CPU time 0.62 seconds
Started Jul 27 06:12:34 PM PDT 24
Finished Jul 27 06:12:34 PM PDT 24
Peak memory 198072 kb
Host smart-829134e8-ab91-444a-bdfb-4619d520ae61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710872610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.2710872610
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.367137344
Short name T11
Test name
Test status
Simulation time 1898022900 ps
CPU time 0.91 seconds
Started Jul 27 06:12:30 PM PDT 24
Finished Jul 27 06:12:31 PM PDT 24
Peak memory 198092 kb
Host smart-feea5dd4-ab52-4592-b0c0-ef719edf8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367137344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.367137344
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3919176070
Short name T314
Test name
Test status
Simulation time 37444950 ps
CPU time 0.65 seconds
Started Jul 27 06:12:33 PM PDT 24
Finished Jul 27 06:12:34 PM PDT 24
Peak memory 198088 kb
Host smart-41d9a5fb-a97e-4af6-b24c-3f8529e0231b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919176070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3919176070
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.218537233
Short name T383
Test name
Test status
Simulation time 148995930 ps
CPU time 0.58 seconds
Started Jul 27 06:12:30 PM PDT 24
Finished Jul 27 06:12:31 PM PDT 24
Peak memory 198136 kb
Host smart-97388f60-8652-4162-bfa1-4c2804d4e859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218537233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.218537233
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1193108985
Short name T450
Test name
Test status
Simulation time 47677991 ps
CPU time 0.74 seconds
Started Jul 27 06:12:27 PM PDT 24
Finished Jul 27 06:12:28 PM PDT 24
Peak memory 199236 kb
Host smart-74a0a0f8-5db8-41ff-916f-fb03df287c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193108985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1193108985
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.751745020
Short name T43
Test name
Test status
Simulation time 108714758 ps
CPU time 0.95 seconds
Started Jul 27 06:12:32 PM PDT 24
Finished Jul 27 06:12:33 PM PDT 24
Peak memory 209500 kb
Host smart-ddb37019-6b32-4155-a7ad-a4fb97c8c255
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751745020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.751745020
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.358946738
Short name T35
Test name
Test status
Simulation time 658545736 ps
CPU time 2.12 seconds
Started Jul 27 06:12:38 PM PDT 24
Finished Jul 27 06:12:40 PM PDT 24
Peak memory 216964 kb
Host smart-1f1f3893-511b-44e7-9ea8-528b9bcb7c19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358946738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.358946738
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2174742885
Short name T386
Test name
Test status
Simulation time 59126884 ps
CPU time 0.81 seconds
Started Jul 27 06:12:30 PM PDT 24
Finished Jul 27 06:12:31 PM PDT 24
Peak memory 198256 kb
Host smart-27247e34-b90f-47c0-b944-1357cc101813
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174742885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2174742885
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2571426552
Short name T457
Test name
Test status
Simulation time 27342264 ps
CPU time 0.65 seconds
Started Jul 27 06:12:17 PM PDT 24
Finished Jul 27 06:12:18 PM PDT 24
Peak memory 199336 kb
Host smart-8e7266c7-0694-41a5-9995-b40e22adbb18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571426552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2571426552
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2796623587
Short name T119
Test name
Test status
Simulation time 24722802 ps
CPU time 0.63 seconds
Started Jul 27 06:14:23 PM PDT 24
Finished Jul 27 06:14:23 PM PDT 24
Peak memory 199252 kb
Host smart-ec7b2a12-d6a3-4a26-8e6f-8ec1c4ce14b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796623587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2796623587
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.570934452
Short name T443
Test name
Test status
Simulation time 30114030 ps
CPU time 0.64 seconds
Started Jul 27 06:14:22 PM PDT 24
Finished Jul 27 06:14:23 PM PDT 24
Peak memory 198088 kb
Host smart-ce79b392-c135-47ab-910c-0c49debd964b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570934452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_
malfunc.570934452
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.2465086509
Short name T552
Test name
Test status
Simulation time 582856231 ps
CPU time 0.94 seconds
Started Jul 27 06:14:22 PM PDT 24
Finished Jul 27 06:14:23 PM PDT 24
Peak memory 198136 kb
Host smart-02589774-7097-46bb-b940-7291825fa25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465086509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2465086509
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2603801794
Short name T321
Test name
Test status
Simulation time 47651427 ps
CPU time 0.62 seconds
Started Jul 27 06:14:20 PM PDT 24
Finished Jul 27 06:14:21 PM PDT 24
Peak memory 198072 kb
Host smart-d308c125-e94d-4c5a-a423-de65ea585f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603801794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2603801794
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.1939232436
Short name T405
Test name
Test status
Simulation time 184072530 ps
CPU time 0.61 seconds
Started Jul 27 06:14:22 PM PDT 24
Finished Jul 27 06:14:23 PM PDT 24
Peak memory 198432 kb
Host smart-0bee6a36-9a4e-4b5e-92cb-f6f5a41ccf1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939232436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1939232436
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2610609799
Short name T472
Test name
Test status
Simulation time 69706948 ps
CPU time 0.86 seconds
Started Jul 27 06:14:21 PM PDT 24
Finished Jul 27 06:14:22 PM PDT 24
Peak memory 198368 kb
Host smart-20d327a6-f4c5-4554-be60-d353d895d56b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610609799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2610609799
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.4122297110
Short name T431
Test name
Test status
Simulation time 97766776 ps
CPU time 0.92 seconds
Started Jul 27 06:14:22 PM PDT 24
Finished Jul 27 06:14:23 PM PDT 24
Peak memory 209500 kb
Host smart-7303b867-102f-4ffd-9fc3-c18e311a94b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122297110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.4122297110
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3342043196
Short name T230
Test name
Test status
Simulation time 60202627 ps
CPU time 0.83 seconds
Started Jul 27 06:14:23 PM PDT 24
Finished Jul 27 06:14:24 PM PDT 24
Peak memory 198008 kb
Host smart-fb0a35cc-4241-495d-be4e-94ad5087b147
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342043196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3342043196
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2249439646
Short name T301
Test name
Test status
Simulation time 62204751 ps
CPU time 0.64 seconds
Started Jul 27 06:14:23 PM PDT 24
Finished Jul 27 06:14:24 PM PDT 24
Peak memory 198568 kb
Host smart-9714bf74-f9a5-41ed-81e7-c77bb369c526
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249439646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2249439646
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.1111533295
Short name T421
Test name
Test status
Simulation time 155719244 ps
CPU time 0.67 seconds
Started Jul 27 06:14:33 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 198680 kb
Host smart-93698424-89b5-4787-9748-4648a05492d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111533295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1111533295
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3248392365
Short name T166
Test name
Test status
Simulation time 63566827 ps
CPU time 0.75 seconds
Started Jul 27 06:14:32 PM PDT 24
Finished Jul 27 06:14:33 PM PDT 24
Peak memory 199168 kb
Host smart-a866cfc8-1f58-4c87-9574-8ceea14db1b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248392365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.3248392365
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1589715281
Short name T284
Test name
Test status
Simulation time 40722142 ps
CPU time 0.6 seconds
Started Jul 27 06:14:33 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 197304 kb
Host smart-47684c98-792c-468d-8831-9679d53cb79b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589715281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1589715281
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1368622325
Short name T424
Test name
Test status
Simulation time 1353849556 ps
CPU time 0.98 seconds
Started Jul 27 06:14:33 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 198172 kb
Host smart-990c93d3-a1ff-4e7b-bfd1-1b4ac92ba9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368622325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1368622325
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.405116012
Short name T28
Test name
Test status
Simulation time 47836177 ps
CPU time 0.61 seconds
Started Jul 27 06:14:34 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 198060 kb
Host smart-560335b8-cb03-487f-bb24-90586f8ab77c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405116012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.405116012
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.611862700
Short name T250
Test name
Test status
Simulation time 121935987 ps
CPU time 0.61 seconds
Started Jul 27 06:14:34 PM PDT 24
Finished Jul 27 06:14:35 PM PDT 24
Peak memory 198152 kb
Host smart-6ec2b58a-5fa2-4898-ae40-690eee551454
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611862700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.611862700
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.972371650
Short name T432
Test name
Test status
Simulation time 56421732 ps
CPU time 0.85 seconds
Started Jul 27 06:14:36 PM PDT 24
Finished Jul 27 06:14:37 PM PDT 24
Peak memory 199220 kb
Host smart-220b5b82-b358-4bff-8f2f-4c316c12f09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972371650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.972371650
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1542673585
Short name T224
Test name
Test status
Simulation time 100839126 ps
CPU time 1.02 seconds
Started Jul 27 06:14:33 PM PDT 24
Finished Jul 27 06:14:34 PM PDT 24
Peak memory 209552 kb
Host smart-483dab74-0f78-4f4d-9253-ea2c6841f4c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542673585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1542673585
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.315404370
Short name T233
Test name
Test status
Simulation time 59636996 ps
CPU time 0.84 seconds
Started Jul 27 06:14:32 PM PDT 24
Finished Jul 27 06:14:33 PM PDT 24
Peak memory 199268 kb
Host smart-bab630f6-34f8-40df-9b00-b789b83f57a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315404370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.315404370
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.661502655
Short name T408
Test name
Test status
Simulation time 65743719 ps
CPU time 0.89 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 200240 kb
Host smart-6f4e9ae1-effb-43fa-ab6e-392bf9b1b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661502655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.661502655
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2936547111
Short name T167
Test name
Test status
Simulation time 79246422 ps
CPU time 0.67 seconds
Started Jul 27 06:14:44 PM PDT 24
Finished Jul 27 06:14:45 PM PDT 24
Peak memory 198564 kb
Host smart-ec24caf9-269b-4891-aeaa-2a0513a4a834
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936547111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2936547111
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1283423056
Short name T289
Test name
Test status
Simulation time 36514781 ps
CPU time 0.58 seconds
Started Jul 27 06:14:44 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 198052 kb
Host smart-719197ab-378b-490c-b43f-9b5cb1f622f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283423056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1283423056
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.618794727
Short name T380
Test name
Test status
Simulation time 162720917 ps
CPU time 0.99 seconds
Started Jul 27 06:14:44 PM PDT 24
Finished Jul 27 06:14:45 PM PDT 24
Peak memory 198120 kb
Host smart-3b728797-3e3b-4b6b-9a65-6b10873014a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618794727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.618794727
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.3748677486
Short name T336
Test name
Test status
Simulation time 59460646 ps
CPU time 0.68 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 198156 kb
Host smart-719ee508-8239-4fdb-8693-86dfa3b50968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748677486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3748677486
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.4066724467
Short name T53
Test name
Test status
Simulation time 37952616 ps
CPU time 0.64 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 198172 kb
Host smart-2ba28769-d866-4c36-a7c1-544c4201bb6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066724467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.4066724467
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.4002236078
Short name T175
Test name
Test status
Simulation time 38554867 ps
CPU time 0.71 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 201404 kb
Host smart-a6553f0d-77af-4839-8d6f-43fb658ba4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002236078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.4002236078
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.1556376728
Short name T234
Test name
Test status
Simulation time 65503752 ps
CPU time 0.7 seconds
Started Jul 27 06:14:45 PM PDT 24
Finished Jul 27 06:14:46 PM PDT 24
Peak memory 199076 kb
Host smart-f1543c3d-55f1-48df-83f7-eb458976a9b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556376728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1556376728
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2902413504
Short name T430
Test name
Test status
Simulation time 54604295 ps
CPU time 0.81 seconds
Started Jul 27 06:14:43 PM PDT 24
Finished Jul 27 06:14:44 PM PDT 24
Peak memory 198260 kb
Host smart-961bb13c-4da6-4a80-8f42-ae83cac71efc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902413504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2902413504
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.574315502
Short name T391
Test name
Test status
Simulation time 31470918 ps
CPU time 0.69 seconds
Started Jul 27 06:14:45 PM PDT 24
Finished Jul 27 06:14:46 PM PDT 24
Peak memory 198484 kb
Host smart-5411295b-415a-46e5-8470-a3d672f2db09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574315502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.574315502
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1154742945
Short name T91
Test name
Test status
Simulation time 49685770 ps
CPU time 0.95 seconds
Started Jul 27 06:14:55 PM PDT 24
Finished Jul 27 06:14:56 PM PDT 24
Peak memory 200336 kb
Host smart-2d61a73c-74fe-431f-bef4-7105a0ae501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154742945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1154742945
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1222995861
Short name T164
Test name
Test status
Simulation time 132226805 ps
CPU time 0.65 seconds
Started Jul 27 06:14:55 PM PDT 24
Finished Jul 27 06:14:56 PM PDT 24
Peak memory 198440 kb
Host smart-4e7491b8-21de-42fc-8515-3f687b70e719
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222995861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1222995861
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1060760339
Short name T563
Test name
Test status
Simulation time 48850910 ps
CPU time 0.59 seconds
Started Jul 27 06:14:56 PM PDT 24
Finished Jul 27 06:14:56 PM PDT 24
Peak memory 198072 kb
Host smart-5d7a61e9-c44a-42a2-a32f-6cdd3cba85a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060760339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.1060760339
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.473047376
Short name T385
Test name
Test status
Simulation time 450377457 ps
CPU time 0.97 seconds
Started Jul 27 06:14:56 PM PDT 24
Finished Jul 27 06:14:57 PM PDT 24
Peak memory 198140 kb
Host smart-3cee8bc5-0f22-4d87-89ae-f6a2bb42a6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473047376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.473047376
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2916579410
Short name T338
Test name
Test status
Simulation time 61916982 ps
CPU time 0.66 seconds
Started Jul 27 06:14:55 PM PDT 24
Finished Jul 27 06:14:56 PM PDT 24
Peak memory 197428 kb
Host smart-8169a1a0-1a69-4209-aff9-8f55cc47f978
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916579410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2916579410
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2418046253
Short name T275
Test name
Test status
Simulation time 31257164 ps
CPU time 0.63 seconds
Started Jul 27 06:14:54 PM PDT 24
Finished Jul 27 06:14:55 PM PDT 24
Peak memory 198412 kb
Host smart-347c3e34-d6c1-4db4-81c9-ba23b38977f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418046253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2418046253
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.292443416
Short name T46
Test name
Test status
Simulation time 103572561 ps
CPU time 0.85 seconds
Started Jul 27 06:14:44 PM PDT 24
Finished Jul 27 06:14:45 PM PDT 24
Peak memory 198604 kb
Host smart-f7c6533a-d1b6-434c-8a1a-2dfa384449f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292443416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.292443416
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.4217446333
Short name T228
Test name
Test status
Simulation time 119234643 ps
CPU time 0.89 seconds
Started Jul 27 06:14:54 PM PDT 24
Finished Jul 27 06:14:55 PM PDT 24
Peak memory 201384 kb
Host smart-e45979b3-4704-414c-b488-8867ecab6214
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217446333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.4217446333
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1546347167
Short name T346
Test name
Test status
Simulation time 52531420 ps
CPU time 0.86 seconds
Started Jul 27 06:14:54 PM PDT 24
Finished Jul 27 06:14:55 PM PDT 24
Peak memory 198196 kb
Host smart-7e58e6b5-6514-4337-9fad-fec953ad7781
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546347167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1546347167
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2981929969
Short name T623
Test name
Test status
Simulation time 38258666 ps
CPU time 0.66 seconds
Started Jul 27 06:14:46 PM PDT 24
Finished Jul 27 06:14:47 PM PDT 24
Peak memory 199340 kb
Host smart-3109054c-9011-44df-b86c-31bc4578f34b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981929969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2981929969
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.3262152961
Short name T101
Test name
Test status
Simulation time 186569015 ps
CPU time 0.76 seconds
Started Jul 27 06:15:05 PM PDT 24
Finished Jul 27 06:15:06 PM PDT 24
Peak memory 200056 kb
Host smart-03b50ab0-3326-433c-92b0-31d371046348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262152961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3262152961
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3508292892
Short name T341
Test name
Test status
Simulation time 71852908 ps
CPU time 0.67 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:04 PM PDT 24
Peak memory 198304 kb
Host smart-a9dc49d3-69ea-40ad-802c-a32d933fd90b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508292892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3508292892
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.73153689
Short name T451
Test name
Test status
Simulation time 48175465 ps
CPU time 0.6 seconds
Started Jul 27 06:15:02 PM PDT 24
Finished Jul 27 06:15:03 PM PDT 24
Peak memory 198060 kb
Host smart-266db96b-be19-4d07-a512-cd3cf43561a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73153689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_m
alfunc.73153689
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.464544005
Short name T349
Test name
Test status
Simulation time 317483148 ps
CPU time 0.99 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:05 PM PDT 24
Peak memory 198140 kb
Host smart-7529ad9a-07d6-415a-8484-7b54056ea4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464544005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.464544005
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2739276984
Short name T300
Test name
Test status
Simulation time 60146144 ps
CPU time 0.69 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:04 PM PDT 24
Peak memory 198084 kb
Host smart-7e4c0413-3aa8-4cad-81a0-a84f632af295
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739276984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2739276984
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1769471178
Short name T251
Test name
Test status
Simulation time 28434088 ps
CPU time 0.64 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:05 PM PDT 24
Peak memory 198180 kb
Host smart-6a55238d-3871-4348-b01c-03d78e2294e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769471178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1769471178
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.3241183692
Short name T474
Test name
Test status
Simulation time 109666449 ps
CPU time 0.68 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:05 PM PDT 24
Peak memory 201424 kb
Host smart-d03f1987-f036-481b-9124-86038f42aaef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241183692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.3241183692
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1927449991
Short name T306
Test name
Test status
Simulation time 67865950 ps
CPU time 0.92 seconds
Started Jul 27 06:14:54 PM PDT 24
Finished Jul 27 06:14:55 PM PDT 24
Peak memory 199192 kb
Host smart-3f575c82-ac53-4ac5-abb7-6a50054816a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927449991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1927449991
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2310982333
Short name T591
Test name
Test status
Simulation time 231758504 ps
CPU time 0.77 seconds
Started Jul 27 06:15:03 PM PDT 24
Finished Jul 27 06:15:04 PM PDT 24
Peak memory 209512 kb
Host smart-d09620b6-ee84-495a-8a2d-5672f368bee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310982333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2310982333
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1962261114
Short name T445
Test name
Test status
Simulation time 54414722 ps
CPU time 0.9 seconds
Started Jul 27 06:15:07 PM PDT 24
Finished Jul 27 06:15:08 PM PDT 24
Peak memory 199680 kb
Host smart-84791b69-c22a-42bb-9aa8-d9974a8c604f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962261114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1962261114
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.660824909
Short name T553
Test name
Test status
Simulation time 205874259 ps
CPU time 0.62 seconds
Started Jul 27 06:14:54 PM PDT 24
Finished Jul 27 06:14:55 PM PDT 24
Peak memory 198604 kb
Host smart-a96554af-29a4-42f4-b4f6-20fbc8fde9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660824909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.660824909
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3163309018
Short name T288
Test name
Test status
Simulation time 141590640 ps
CPU time 0.77 seconds
Started Jul 27 06:15:05 PM PDT 24
Finished Jul 27 06:15:06 PM PDT 24
Peak memory 198816 kb
Host smart-f8e47352-cf89-4759-935a-abf4b0aacfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163309018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3163309018
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.132550359
Short name T132
Test name
Test status
Simulation time 32122325 ps
CPU time 0.63 seconds
Started Jul 27 06:15:14 PM PDT 24
Finished Jul 27 06:15:15 PM PDT 24
Peak memory 198056 kb
Host smart-8fb69375-1e2d-4c5e-941e-82cc80bf3d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132550359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_
malfunc.132550359
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.3830496618
Short name T130
Test name
Test status
Simulation time 167175040 ps
CPU time 0.98 seconds
Started Jul 27 06:15:11 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 198488 kb
Host smart-fbd5dfb8-6cd2-4981-bbca-b9b5628bdf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830496618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3830496618
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.988967014
Short name T293
Test name
Test status
Simulation time 33109184 ps
CPU time 0.66 seconds
Started Jul 27 06:15:11 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 197448 kb
Host smart-1397ed9d-97f4-4002-8a79-cea80bbaaa60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988967014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.988967014
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3862978478
Short name T453
Test name
Test status
Simulation time 36073249 ps
CPU time 0.65 seconds
Started Jul 27 06:15:13 PM PDT 24
Finished Jul 27 06:15:14 PM PDT 24
Peak memory 198136 kb
Host smart-9520b0e8-ccfe-4d72-a4ce-f8477f0d84c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862978478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3862978478
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3730562706
Short name T475
Test name
Test status
Simulation time 67892554 ps
CPU time 0.66 seconds
Started Jul 27 06:15:11 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 201376 kb
Host smart-34549970-5924-4089-bcde-4c566a6aa0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730562706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3730562706
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1584093896
Short name T554
Test name
Test status
Simulation time 23996221 ps
CPU time 0.65 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:04 PM PDT 24
Peak memory 198276 kb
Host smart-348da28c-d0b9-4f0a-84bb-6a2c2fcdbe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584093896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1584093896
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2793728537
Short name T608
Test name
Test status
Simulation time 19725880 ps
CPU time 0.62 seconds
Started Jul 27 06:15:07 PM PDT 24
Finished Jul 27 06:15:07 PM PDT 24
Peak memory 198108 kb
Host smart-7ff94d30-7b3e-414d-a2ef-3e0a54e2685d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793728537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2793728537
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1279642763
Short name T594
Test name
Test status
Simulation time 167757294 ps
CPU time 0.78 seconds
Started Jul 27 06:15:13 PM PDT 24
Finished Jul 27 06:15:14 PM PDT 24
Peak memory 209524 kb
Host smart-e7fdb337-7f0e-415b-8324-53725cabe436
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279642763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1279642763
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.46405290
Short name T144
Test name
Test status
Simulation time 225862678 ps
CPU time 0.65 seconds
Started Jul 27 06:15:04 PM PDT 24
Finished Jul 27 06:15:05 PM PDT 24
Peak memory 198536 kb
Host smart-f83ed03e-8145-4b18-ae08-8b5b6195547e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46405290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.46405290
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.695930322
Short name T99
Test name
Test status
Simulation time 28485334 ps
CPU time 0.62 seconds
Started Jul 27 06:15:12 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 199240 kb
Host smart-ffd633f7-cda4-47ed-ac6c-4dc42cbcdd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695930322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.695930322
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.985242922
Short name T362
Test name
Test status
Simulation time 66916416 ps
CPU time 0.6 seconds
Started Jul 27 06:15:12 PM PDT 24
Finished Jul 27 06:15:13 PM PDT 24
Peak memory 198076 kb
Host smart-5eaca630-0bec-4b82-93d8-16c82724d03f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985242922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.985242922
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3893883456
Short name T319
Test name
Test status
Simulation time 167010067 ps
CPU time 0.99 seconds
Started Jul 27 06:15:20 PM PDT 24
Finished Jul 27 06:15:21 PM PDT 24
Peak memory 198188 kb
Host smart-285e7678-07ca-4925-9119-82a56ca04b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893883456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3893883456
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.1162743452
Short name T210
Test name
Test status
Simulation time 35530958 ps
CPU time 0.62 seconds
Started Jul 27 06:15:19 PM PDT 24
Finished Jul 27 06:15:20 PM PDT 24
Peak memory 198096 kb
Host smart-76f2395c-123b-4591-a8b8-ef83961ebb02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162743452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1162743452
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2537822851
Short name T313
Test name
Test status
Simulation time 54490865 ps
CPU time 0.64 seconds
Started Jul 27 06:15:19 PM PDT 24
Finished Jul 27 06:15:19 PM PDT 24
Peak memory 198156 kb
Host smart-f51bf8e0-ec6b-4d2d-8959-23e221c71163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537822851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2537822851
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.973413561
Short name T193
Test name
Test status
Simulation time 46729772 ps
CPU time 0.75 seconds
Started Jul 27 06:15:17 PM PDT 24
Finished Jul 27 06:15:18 PM PDT 24
Peak memory 201448 kb
Host smart-7a7a6cd5-0166-4b9b-a1ff-f5ff2c1fd489
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973413561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invali
d.973413561
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1087753367
Short name T416
Test name
Test status
Simulation time 42980064 ps
CPU time 0.76 seconds
Started Jul 27 06:15:13 PM PDT 24
Finished Jul 27 06:15:13 PM PDT 24
Peak memory 199180 kb
Host smart-08484d03-27fa-45fc-9fbb-9d26ed51e9a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087753367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1087753367
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.4292885814
Short name T529
Test name
Test status
Simulation time 103838393 ps
CPU time 1.02 seconds
Started Jul 27 06:15:17 PM PDT 24
Finished Jul 27 06:15:18 PM PDT 24
Peak memory 209408 kb
Host smart-d2bab237-0c45-4844-96eb-5cae4aff0e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292885814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.4292885814
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.3377259595
Short name T481
Test name
Test status
Simulation time 53263021 ps
CPU time 0.77 seconds
Started Jul 27 06:15:12 PM PDT 24
Finished Jul 27 06:15:13 PM PDT 24
Peak memory 198280 kb
Host smart-bd2059ef-13fd-4d6c-837c-70f39bd32939
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377259595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3377259595
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2503632844
Short name T325
Test name
Test status
Simulation time 39439708 ps
CPU time 0.64 seconds
Started Jul 27 06:15:11 PM PDT 24
Finished Jul 27 06:15:12 PM PDT 24
Peak memory 198560 kb
Host smart-014c8c1e-5b17-49e7-a30e-e3a9d248a940
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503632844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2503632844
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.696569855
Short name T122
Test name
Test status
Simulation time 28279065 ps
CPU time 0.63 seconds
Started Jul 27 06:15:17 PM PDT 24
Finished Jul 27 06:15:18 PM PDT 24
Peak memory 198608 kb
Host smart-b37c3236-b379-4cff-a8c5-7fa50103734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696569855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.696569855
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3514039948
Short name T392
Test name
Test status
Simulation time 75821483 ps
CPU time 0.66 seconds
Started Jul 27 06:15:27 PM PDT 24
Finished Jul 27 06:15:28 PM PDT 24
Peak memory 199096 kb
Host smart-8502daa5-9add-4691-85f4-d809b0045e1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514039948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3514039948
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1258490321
Short name T136
Test name
Test status
Simulation time 79293593 ps
CPU time 0.57 seconds
Started Jul 27 06:15:26 PM PDT 24
Finished Jul 27 06:15:27 PM PDT 24
Peak memory 198108 kb
Host smart-8bf80484-55c6-4374-96f8-1affb8afff74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258490321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.1258490321
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3415122560
Short name T317
Test name
Test status
Simulation time 165289584 ps
CPU time 1.02 seconds
Started Jul 27 06:15:28 PM PDT 24
Finished Jul 27 06:15:29 PM PDT 24
Peak memory 198088 kb
Host smart-26c402f8-23ab-4896-bdcc-e2366ac46aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415122560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3415122560
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.1391733715
Short name T371
Test name
Test status
Simulation time 49967521 ps
CPU time 0.66 seconds
Started Jul 27 06:15:24 PM PDT 24
Finished Jul 27 06:15:25 PM PDT 24
Peak memory 198192 kb
Host smart-5fded16f-d21f-4d52-9524-6f668b4df707
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391733715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1391733715
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2408044597
Short name T537
Test name
Test status
Simulation time 32539980 ps
CPU time 0.6 seconds
Started Jul 27 06:15:23 PM PDT 24
Finished Jul 27 06:15:24 PM PDT 24
Peak memory 198444 kb
Host smart-058dd18a-1afe-439f-8906-673f6a6742d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408044597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2408044597
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.554971033
Short name T466
Test name
Test status
Simulation time 53172639 ps
CPU time 0.66 seconds
Started Jul 27 06:15:27 PM PDT 24
Finished Jul 27 06:15:28 PM PDT 24
Peak memory 201404 kb
Host smart-1b17cc18-6b56-4a75-94f9-4570723fde9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554971033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invali
d.554971033
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3030389115
Short name T413
Test name
Test status
Simulation time 25094212 ps
CPU time 0.67 seconds
Started Jul 27 06:15:18 PM PDT 24
Finished Jul 27 06:15:18 PM PDT 24
Peak memory 198200 kb
Host smart-fcde2828-744b-416f-a30f-cd27d7bdfd22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030389115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3030389115
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1031075783
Short name T455
Test name
Test status
Simulation time 109922195 ps
CPU time 0.86 seconds
Started Jul 27 06:15:24 PM PDT 24
Finished Jul 27 06:15:24 PM PDT 24
Peak memory 209576 kb
Host smart-50425920-5fd0-4e9b-ac06-c7dd25c77f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031075783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1031075783
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.643629666
Short name T504
Test name
Test status
Simulation time 87535014 ps
CPU time 0.81 seconds
Started Jul 27 06:15:31 PM PDT 24
Finished Jul 27 06:15:32 PM PDT 24
Peak memory 199052 kb
Host smart-9d4aacce-df3f-431f-8d5e-115d674996e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643629666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_
mubi.643629666
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.886996120
Short name T613
Test name
Test status
Simulation time 49559702 ps
CPU time 0.65 seconds
Started Jul 27 06:15:19 PM PDT 24
Finished Jul 27 06:15:20 PM PDT 24
Peak memory 198512 kb
Host smart-0132b11e-8656-4b9d-86b8-dd73f69501bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886996120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.886996120
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3021171485
Short name T507
Test name
Test status
Simulation time 37550866 ps
CPU time 0.66 seconds
Started Jul 27 06:15:34 PM PDT 24
Finished Jul 27 06:15:35 PM PDT 24
Peak memory 199196 kb
Host smart-c97784e2-dc37-4885-87de-cb08927aada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021171485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3021171485
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2592417754
Short name T420
Test name
Test status
Simulation time 71665256 ps
CPU time 0.68 seconds
Started Jul 27 06:15:31 PM PDT 24
Finished Jul 27 06:15:32 PM PDT 24
Peak memory 198464 kb
Host smart-b9ac77f3-acd3-4a03-be14-c7303961bb59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592417754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2592417754
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4101520606
Short name T409
Test name
Test status
Simulation time 30002886 ps
CPU time 0.63 seconds
Started Jul 27 06:15:33 PM PDT 24
Finished Jul 27 06:15:34 PM PDT 24
Peak memory 198056 kb
Host smart-25ce7ef4-0e54-44ac-8518-36dd6e9c3ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101520606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.4101520606
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2101559998
Short name T487
Test name
Test status
Simulation time 800181537 ps
CPU time 1.03 seconds
Started Jul 27 06:15:32 PM PDT 24
Finished Jul 27 06:15:33 PM PDT 24
Peak memory 198168 kb
Host smart-898b13c9-7450-483d-b583-e1f0d11efd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101559998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2101559998
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.1264338355
Short name T545
Test name
Test status
Simulation time 50219905 ps
CPU time 0.61 seconds
Started Jul 27 06:15:32 PM PDT 24
Finished Jul 27 06:15:32 PM PDT 24
Peak memory 197444 kb
Host smart-fcc30ad9-dfe1-4c3f-955f-8ff7b415ab4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264338355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.1264338355
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3741551108
Short name T548
Test name
Test status
Simulation time 42187785 ps
CPU time 0.63 seconds
Started Jul 27 06:15:33 PM PDT 24
Finished Jul 27 06:15:34 PM PDT 24
Peak memory 198104 kb
Host smart-f01b8cd1-4703-4596-9c12-ef32592f94f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741551108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3741551108
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.4246363716
Short name T180
Test name
Test status
Simulation time 85851224 ps
CPU time 0.64 seconds
Started Jul 27 06:15:32 PM PDT 24
Finished Jul 27 06:15:33 PM PDT 24
Peak memory 201428 kb
Host smart-4d476e40-3636-4496-97f6-95f2ac98a30b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246363716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.4246363716
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.4084025352
Short name T565
Test name
Test status
Simulation time 75321882 ps
CPU time 0.85 seconds
Started Jul 27 06:15:33 PM PDT 24
Finished Jul 27 06:15:34 PM PDT 24
Peak memory 198380 kb
Host smart-d4c2a31f-c77c-417c-9f54-0eb1ee787305
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084025352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.4084025352
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1779280255
Short name T4
Test name
Test status
Simulation time 116938045 ps
CPU time 0.98 seconds
Started Jul 27 06:15:31 PM PDT 24
Finished Jul 27 06:15:33 PM PDT 24
Peak memory 209492 kb
Host smart-d0415ead-ef2e-44b9-ab2e-ed9bf4141be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779280255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1779280255
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3118395207
Short name T9
Test name
Test status
Simulation time 66210428 ps
CPU time 0.8 seconds
Started Jul 27 06:15:32 PM PDT 24
Finished Jul 27 06:15:33 PM PDT 24
Peak memory 198128 kb
Host smart-9ef9ab72-5469-48d1-b42d-c8e3bcc1c137
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118395207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3118395207
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3799410388
Short name T364
Test name
Test status
Simulation time 60168568 ps
CPU time 0.63 seconds
Started Jul 27 06:15:32 PM PDT 24
Finished Jul 27 06:15:33 PM PDT 24
Peak memory 198492 kb
Host smart-ee4491c7-3865-48c8-ac22-1008e3aba9d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799410388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3799410388
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.906139828
Short name T388
Test name
Test status
Simulation time 22597771 ps
CPU time 0.69 seconds
Started Jul 27 06:15:42 PM PDT 24
Finished Jul 27 06:15:43 PM PDT 24
Peak memory 198768 kb
Host smart-7b6b7ae0-2595-4844-a993-1b06b3b19a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906139828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.906139828
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2545060064
Short name T372
Test name
Test status
Simulation time 30890707 ps
CPU time 0.61 seconds
Started Jul 27 06:15:42 PM PDT 24
Finished Jul 27 06:15:43 PM PDT 24
Peak memory 197356 kb
Host smart-681908d5-5b99-41ba-bbc3-f11a916d7ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545060064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2545060064
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.3676847303
Short name T616
Test name
Test status
Simulation time 314907663 ps
CPU time 0.99 seconds
Started Jul 27 06:15:41 PM PDT 24
Finished Jul 27 06:15:42 PM PDT 24
Peak memory 198168 kb
Host smart-2a7a466f-4327-4103-a9a5-358eb05f99da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676847303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3676847303
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1060053721
Short name T215
Test name
Test status
Simulation time 37245222 ps
CPU time 0.61 seconds
Started Jul 27 06:15:41 PM PDT 24
Finished Jul 27 06:15:42 PM PDT 24
Peak memory 198076 kb
Host smart-098f437c-ce8f-4a6e-b0a5-b7482116bbf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060053721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1060053721
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.2386404479
Short name T254
Test name
Test status
Simulation time 45186386 ps
CPU time 0.63 seconds
Started Jul 27 06:15:42 PM PDT 24
Finished Jul 27 06:15:42 PM PDT 24
Peak memory 198448 kb
Host smart-b2bce363-76ff-4be2-81df-36325ec1750a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386404479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2386404479
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.568247428
Short name T181
Test name
Test status
Simulation time 73850876 ps
CPU time 0.65 seconds
Started Jul 27 06:15:40 PM PDT 24
Finished Jul 27 06:15:41 PM PDT 24
Peak memory 201396 kb
Host smart-2e3a1eb1-0397-4628-a572-2f445b6d5f91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568247428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invali
d.568247428
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2306066567
Short name T525
Test name
Test status
Simulation time 114447016 ps
CPU time 0.65 seconds
Started Jul 27 06:15:34 PM PDT 24
Finished Jul 27 06:15:35 PM PDT 24
Peak memory 199156 kb
Host smart-699d75b5-6117-41c4-b697-2342b0b7a436
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306066567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2306066567
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3032688690
Short name T38
Test name
Test status
Simulation time 112232257 ps
CPU time 1.15 seconds
Started Jul 27 06:15:39 PM PDT 24
Finished Jul 27 06:15:40 PM PDT 24
Peak memory 209524 kb
Host smart-f995e105-9873-4170-8e4e-488ded7827b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032688690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3032688690
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3276219561
Short name T143
Test name
Test status
Simulation time 79496834 ps
CPU time 0.82 seconds
Started Jul 27 06:15:39 PM PDT 24
Finished Jul 27 06:15:40 PM PDT 24
Peak memory 199292 kb
Host smart-0aa94b62-5420-4eea-a2e7-2636f81a789d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276219561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3276219561
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1551991868
Short name T598
Test name
Test status
Simulation time 28279432 ps
CPU time 0.66 seconds
Started Jul 27 06:15:31 PM PDT 24
Finished Jul 27 06:15:32 PM PDT 24
Peak memory 199400 kb
Host smart-0d126b66-a93f-4477-b8a9-284796934992
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551991868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1551991868
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.771027305
Short name T615
Test name
Test status
Simulation time 32491389 ps
CPU time 1.11 seconds
Started Jul 27 06:12:43 PM PDT 24
Finished Jul 27 06:12:44 PM PDT 24
Peak memory 200964 kb
Host smart-75d8fdd5-de5e-4146-ac4b-efab3c15c1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771027305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.771027305
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4067065766
Short name T599
Test name
Test status
Simulation time 59990561 ps
CPU time 0.78 seconds
Started Jul 27 06:12:51 PM PDT 24
Finished Jul 27 06:12:51 PM PDT 24
Peak memory 199136 kb
Host smart-0d872708-1cd2-4988-9ac4-b1763cce55b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067065766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.4067065766
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3313576075
Short name T382
Test name
Test status
Simulation time 48851526 ps
CPU time 0.62 seconds
Started Jul 27 06:12:45 PM PDT 24
Finished Jul 27 06:12:45 PM PDT 24
Peak memory 198068 kb
Host smart-2819beda-7067-4698-8d60-7e3a782d07e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313576075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3313576075
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2214533646
Short name T363
Test name
Test status
Simulation time 625928644 ps
CPU time 1 seconds
Started Jul 27 06:12:49 PM PDT 24
Finished Jul 27 06:12:50 PM PDT 24
Peak memory 198192 kb
Host smart-dba90890-e3bd-4ab3-88fa-e8239272cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214533646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2214533646
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1523533051
Short name T378
Test name
Test status
Simulation time 56493888 ps
CPU time 0.62 seconds
Started Jul 27 06:12:51 PM PDT 24
Finished Jul 27 06:12:51 PM PDT 24
Peak memory 198048 kb
Host smart-2e4a3a59-62be-43ff-80ee-5eda3fc116dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523533051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1523533051
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2141363475
Short name T560
Test name
Test status
Simulation time 48372278 ps
CPU time 0.65 seconds
Started Jul 27 06:12:44 PM PDT 24
Finished Jul 27 06:12:45 PM PDT 24
Peak memory 198132 kb
Host smart-1ad5502d-02d1-4e05-bcd1-7d6b9334e8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141363475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2141363475
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2970027870
Short name T586
Test name
Test status
Simulation time 81313830 ps
CPU time 0.69 seconds
Started Jul 27 06:12:49 PM PDT 24
Finished Jul 27 06:12:50 PM PDT 24
Peak memory 201456 kb
Host smart-98a3b70e-4889-4386-8f70-e569e488c24d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970027870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2970027870
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.1199193411
Short name T145
Test name
Test status
Simulation time 54467585 ps
CPU time 0.61 seconds
Started Jul 27 06:12:42 PM PDT 24
Finished Jul 27 06:12:43 PM PDT 24
Peak memory 199224 kb
Host smart-4afbd005-8bc9-4785-b537-2f104ace2e57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199193411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.1199193411
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.777708544
Short name T428
Test name
Test status
Simulation time 98467723 ps
CPU time 0.86 seconds
Started Jul 27 06:12:38 PM PDT 24
Finished Jul 27 06:12:39 PM PDT 24
Peak memory 199148 kb
Host smart-c8e4cc08-8c31-4146-88a0-e1701e4b9bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777708544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.777708544
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.790249769
Short name T264
Test name
Test status
Simulation time 105054856 ps
CPU time 1.09 seconds
Started Jul 27 06:12:51 PM PDT 24
Finished Jul 27 06:12:52 PM PDT 24
Peak memory 209480 kb
Host smart-e2e972c6-d600-4909-955c-cd086a311294
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790249769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.790249769
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1750756766
Short name T401
Test name
Test status
Simulation time 61475467 ps
CPU time 0.72 seconds
Started Jul 27 06:12:45 PM PDT 24
Finished Jul 27 06:12:46 PM PDT 24
Peak memory 198072 kb
Host smart-ad8edc68-7587-4d60-8b23-e50fba43956a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750756766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1750756766
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.4103098224
Short name T520
Test name
Test status
Simulation time 30059597 ps
CPU time 0.7 seconds
Started Jul 27 06:12:38 PM PDT 24
Finished Jul 27 06:12:38 PM PDT 24
Peak memory 199432 kb
Host smart-7f7ec373-de0d-4b2e-93b7-f01dc8aa0cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103098224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.4103098224
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2028565446
Short name T557
Test name
Test status
Simulation time 28269890 ps
CPU time 0.88 seconds
Started Jul 27 06:15:52 PM PDT 24
Finished Jul 27 06:15:53 PM PDT 24
Peak memory 200004 kb
Host smart-e40457c7-6e37-476c-b1c3-fd5a7e85222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028565446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2028565446
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.605227453
Short name T602
Test name
Test status
Simulation time 64245087 ps
CPU time 0.69 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:52 PM PDT 24
Peak memory 198432 kb
Host smart-55e699de-e84c-4f5d-81e4-29a0ad9e18ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605227453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.605227453
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2924123481
Short name T235
Test name
Test status
Simulation time 63373238 ps
CPU time 0.58 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:51 PM PDT 24
Peak memory 197300 kb
Host smart-9293a77b-4570-4900-9108-90c3e3341123
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924123481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2924123481
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.1067386387
Short name T460
Test name
Test status
Simulation time 161450956 ps
CPU time 0.96 seconds
Started Jul 27 06:15:49 PM PDT 24
Finished Jul 27 06:15:51 PM PDT 24
Peak memory 198156 kb
Host smart-15730aeb-8dcc-4302-b72e-38c83ee8bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067386387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1067386387
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.3152975476
Short name T303
Test name
Test status
Simulation time 71189271 ps
CPU time 0.61 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:52 PM PDT 24
Peak memory 198188 kb
Host smart-e6f244de-43da-4d07-a142-562803526405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152975476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3152975476
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2247829830
Short name T226
Test name
Test status
Simulation time 104093203 ps
CPU time 0.64 seconds
Started Jul 27 06:15:49 PM PDT 24
Finished Jul 27 06:15:50 PM PDT 24
Peak memory 198144 kb
Host smart-f6af6e45-34c0-47be-8d98-f9fe10407f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247829830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2247829830
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.2145504183
Short name T269
Test name
Test status
Simulation time 130367034 ps
CPU time 0.77 seconds
Started Jul 27 06:15:50 PM PDT 24
Finished Jul 27 06:15:51 PM PDT 24
Peak memory 198524 kb
Host smart-31e9d19d-70c9-416b-b20e-a815cdb048f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145504183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2145504183
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3431910509
Short name T505
Test name
Test status
Simulation time 119934962 ps
CPU time 0.94 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:53 PM PDT 24
Peak memory 209480 kb
Host smart-625f7d60-55cd-45e6-91cd-dd31ac448be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431910509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3431910509
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3236568055
Short name T7
Test name
Test status
Simulation time 52519012 ps
CPU time 0.91 seconds
Started Jul 27 06:15:52 PM PDT 24
Finished Jul 27 06:15:53 PM PDT 24
Peak memory 199416 kb
Host smart-a9062eeb-fa3b-440d-9b38-e1ce08c20fe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236568055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3236568055
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.486934016
Short name T329
Test name
Test status
Simulation time 49651007 ps
CPU time 0.65 seconds
Started Jul 27 06:15:51 PM PDT 24
Finished Jul 27 06:15:52 PM PDT 24
Peak memory 198548 kb
Host smart-7a82bca6-bc9f-42e9-8473-f088a13afdc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486934016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.486934016
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.262562925
Short name T96
Test name
Test status
Simulation time 51236878 ps
CPU time 0.77 seconds
Started Jul 27 06:15:49 PM PDT 24
Finished Jul 27 06:15:50 PM PDT 24
Peak memory 198884 kb
Host smart-0d64bb62-df1f-4dbd-abb0-55e1054ff877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262562925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.262562925
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.897043993
Short name T311
Test name
Test status
Simulation time 69357608 ps
CPU time 0.64 seconds
Started Jul 27 06:16:00 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 199168 kb
Host smart-c09bb178-88c8-4304-8484-b7b703f56547
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897043993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.897043993
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3014986500
Short name T260
Test name
Test status
Simulation time 29142084 ps
CPU time 0.64 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 198036 kb
Host smart-f0aba60b-6d1b-4d11-a648-2006e1472831
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014986500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.3014986500
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.709729939
Short name T476
Test name
Test status
Simulation time 307657126 ps
CPU time 1.04 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:02 PM PDT 24
Peak memory 198188 kb
Host smart-375615a5-8caf-44a6-afbf-adb1e1df2703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709729939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.709729939
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.4043645145
Short name T551
Test name
Test status
Simulation time 63801574 ps
CPU time 0.66 seconds
Started Jul 27 06:16:02 PM PDT 24
Finished Jul 27 06:16:03 PM PDT 24
Peak memory 198140 kb
Host smart-f1f2dc6b-19d6-4c91-b4aa-b752893599a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043645145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.4043645145
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3375899401
Short name T217
Test name
Test status
Simulation time 98337455 ps
CPU time 0.59 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 198192 kb
Host smart-83c8b940-6225-4aee-acdd-77ed029c4c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375899401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3375899401
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.477903986
Short name T92
Test name
Test status
Simulation time 74978501 ps
CPU time 0.67 seconds
Started Jul 27 06:16:00 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 201448 kb
Host smart-474a703c-b5c7-404f-bb28-35ae8e39a993
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477903986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.477903986
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2862414474
Short name T482
Test name
Test status
Simulation time 32027225 ps
CPU time 0.67 seconds
Started Jul 27 06:15:54 PM PDT 24
Finished Jul 27 06:15:55 PM PDT 24
Peak memory 198244 kb
Host smart-058a137c-fbf6-4832-929d-c541b6f3cd9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862414474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2862414474
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1922180631
Short name T379
Test name
Test status
Simulation time 104730505 ps
CPU time 1.01 seconds
Started Jul 27 06:16:00 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 209592 kb
Host smart-cceb3844-cfca-4c41-940a-224542cd7807
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922180631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1922180631
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3684115598
Short name T449
Test name
Test status
Simulation time 56689585 ps
CPU time 0.8 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:02 PM PDT 24
Peak memory 198220 kb
Host smart-1f5fe020-5ba6-4100-a8f4-e8b08a880964
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684115598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3684115598
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2977358490
Short name T398
Test name
Test status
Simulation time 30000277 ps
CPU time 0.67 seconds
Started Jul 27 06:15:49 PM PDT 24
Finished Jul 27 06:15:50 PM PDT 24
Peak memory 199360 kb
Host smart-ed31f212-5f95-4efb-9365-ab60c5bb34c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977358490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2977358490
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.882858190
Short name T190
Test name
Test status
Simulation time 90324061 ps
CPU time 0.81 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:02 PM PDT 24
Peak memory 200108 kb
Host smart-7267cc82-3855-43f6-9302-af9756bb58a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882858190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.882858190
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2324177550
Short name T470
Test name
Test status
Simulation time 68602958 ps
CPU time 0.66 seconds
Started Jul 27 06:16:11 PM PDT 24
Finished Jul 27 06:16:12 PM PDT 24
Peak memory 199112 kb
Host smart-4e1dbb8a-b6e7-42f5-8e72-d93cb4048505
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324177550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2324177550
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3715357949
Short name T331
Test name
Test status
Simulation time 94323093 ps
CPU time 0.6 seconds
Started Jul 27 06:16:00 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 198092 kb
Host smart-6b087d49-b778-42ca-8447-2e850ac9a14e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715357949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3715357949
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.3245069738
Short name T495
Test name
Test status
Simulation time 168270214 ps
CPU time 0.99 seconds
Started Jul 27 06:16:13 PM PDT 24
Finished Jul 27 06:16:14 PM PDT 24
Peak memory 198152 kb
Host smart-31699316-95f7-499a-9eaf-5114e81b01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245069738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3245069738
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.1041301378
Short name T216
Test name
Test status
Simulation time 35743340 ps
CPU time 0.61 seconds
Started Jul 27 06:16:10 PM PDT 24
Finished Jul 27 06:16:10 PM PDT 24
Peak memory 198044 kb
Host smart-e72a904d-3659-4816-8351-a1255f7b51c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041301378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.1041301378
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3468766179
Short name T253
Test name
Test status
Simulation time 98723384 ps
CPU time 0.63 seconds
Started Jul 27 06:16:02 PM PDT 24
Finished Jul 27 06:16:03 PM PDT 24
Peak memory 198492 kb
Host smart-e3960ec5-00ce-4d2a-a7c8-05d3c33db45e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468766179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3468766179
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1705019825
Short name T621
Test name
Test status
Simulation time 62744191 ps
CPU time 0.66 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:02 PM PDT 24
Peak memory 198220 kb
Host smart-21f60ca3-15d9-46a8-bb57-f44092aceed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705019825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1705019825
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.444489178
Short name T345
Test name
Test status
Simulation time 161122041 ps
CPU time 0.79 seconds
Started Jul 27 06:16:15 PM PDT 24
Finished Jul 27 06:16:16 PM PDT 24
Peak memory 209524 kb
Host smart-97395bf0-7917-444c-a9fc-4d4ba6b94022
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444489178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.444489178
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.884104934
Short name T604
Test name
Test status
Simulation time 53635929 ps
CPU time 0.78 seconds
Started Jul 27 06:15:59 PM PDT 24
Finished Jul 27 06:16:01 PM PDT 24
Peak memory 198168 kb
Host smart-26992652-8804-4181-bdd6-75224c6433bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884104934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.884104934
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3250296483
Short name T467
Test name
Test status
Simulation time 61117357 ps
CPU time 0.66 seconds
Started Jul 27 06:16:01 PM PDT 24
Finished Jul 27 06:16:02 PM PDT 24
Peak memory 198548 kb
Host smart-26e1e4eb-2baa-492f-8229-990fadb8d248
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250296483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3250296483
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2217816081
Short name T438
Test name
Test status
Simulation time 84188411 ps
CPU time 0.77 seconds
Started Jul 27 06:16:12 PM PDT 24
Finished Jul 27 06:16:13 PM PDT 24
Peak memory 200068 kb
Host smart-31d2c5af-d6fd-4a01-89a4-57c95bbf6700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217816081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2217816081
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.1509793122
Short name T367
Test name
Test status
Simulation time 61102996 ps
CPU time 0.83 seconds
Started Jul 27 06:16:12 PM PDT 24
Finished Jul 27 06:16:13 PM PDT 24
Peak memory 199120 kb
Host smart-8e3490a7-1749-480e-9d88-b95e2446ae49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509793122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.1509793122
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3823505251
Short name T134
Test name
Test status
Simulation time 39107935 ps
CPU time 0.6 seconds
Started Jul 27 06:16:13 PM PDT 24
Finished Jul 27 06:16:13 PM PDT 24
Peak memory 198084 kb
Host smart-b7c11b38-6887-449c-bd3b-6409de5a2d27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823505251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.3823505251
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3161883038
Short name T295
Test name
Test status
Simulation time 1012342730 ps
CPU time 0.96 seconds
Started Jul 27 06:16:14 PM PDT 24
Finished Jul 27 06:16:15 PM PDT 24
Peak memory 198392 kb
Host smart-409b0a79-a445-40c9-a7a9-1ac979659c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161883038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3161883038
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1141356882
Short name T249
Test name
Test status
Simulation time 42114771 ps
CPU time 0.59 seconds
Started Jul 27 06:16:12 PM PDT 24
Finished Jul 27 06:16:12 PM PDT 24
Peak memory 198128 kb
Host smart-ce684386-d23c-4ca6-bb7c-8449a841160e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141356882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1141356882
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3396084612
Short name T452
Test name
Test status
Simulation time 36838206 ps
CPU time 0.63 seconds
Started Jul 27 06:16:14 PM PDT 24
Finished Jul 27 06:16:15 PM PDT 24
Peak memory 198068 kb
Host smart-3b045ab9-0891-4d2a-b5e9-687ef8bc2f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396084612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3396084612
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2800907641
Short name T194
Test name
Test status
Simulation time 39649245 ps
CPU time 0.69 seconds
Started Jul 27 06:16:10 PM PDT 24
Finished Jul 27 06:16:11 PM PDT 24
Peak memory 201400 kb
Host smart-0fcf8367-cb99-406c-8148-273850152ec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800907641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2800907641
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.805609252
Short name T590
Test name
Test status
Simulation time 97095435 ps
CPU time 0.72 seconds
Started Jul 27 06:16:11 PM PDT 24
Finished Jul 27 06:16:12 PM PDT 24
Peak memory 198372 kb
Host smart-cb1d17d9-be2a-4d67-99e6-e1aff8a67006
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805609252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.805609252
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3209841335
Short name T238
Test name
Test status
Simulation time 120531558 ps
CPU time 0.86 seconds
Started Jul 27 06:16:17 PM PDT 24
Finished Jul 27 06:16:18 PM PDT 24
Peak memory 209520 kb
Host smart-86ae50df-0ebe-46f2-b3a7-a4804ffa3b91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209841335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3209841335
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1293172687
Short name T121
Test name
Test status
Simulation time 237026505 ps
CPU time 0.79 seconds
Started Jul 27 06:16:14 PM PDT 24
Finished Jul 27 06:16:15 PM PDT 24
Peak memory 198268 kb
Host smart-5c1f1e25-614c-4b44-8691-817d5e864294
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293172687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1293172687
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.3227093862
Short name T473
Test name
Test status
Simulation time 35149321 ps
CPU time 0.66 seconds
Started Jul 27 06:16:12 PM PDT 24
Finished Jul 27 06:16:13 PM PDT 24
Peak memory 198524 kb
Host smart-7b039f29-91e2-4c8c-bd38-5708800ce998
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227093862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3227093862
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.3296646013
Short name T2
Test name
Test status
Simulation time 69884426 ps
CPU time 0.62 seconds
Started Jul 27 06:16:11 PM PDT 24
Finished Jul 27 06:16:12 PM PDT 24
Peak memory 198640 kb
Host smart-bf26d646-da83-40ef-97bf-befba79a5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296646013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3296646013
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1419941604
Short name T156
Test name
Test status
Simulation time 66453222 ps
CPU time 0.68 seconds
Started Jul 27 06:16:19 PM PDT 24
Finished Jul 27 06:16:20 PM PDT 24
Peak memory 199168 kb
Host smart-664545a3-4a02-4756-88e5-b5aac7d87445
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419941604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1419941604
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.510201482
Short name T559
Test name
Test status
Simulation time 28222032 ps
CPU time 0.63 seconds
Started Jul 27 06:16:21 PM PDT 24
Finished Jul 27 06:16:22 PM PDT 24
Peak memory 198056 kb
Host smart-a1fc6611-e189-46ac-9eb4-43714e149e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510201482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_
malfunc.510201482
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3057280973
Short name T129
Test name
Test status
Simulation time 160398829 ps
CPU time 0.99 seconds
Started Jul 27 06:16:19 PM PDT 24
Finished Jul 27 06:16:20 PM PDT 24
Peak memory 198136 kb
Host smart-364162f3-bab1-43f6-97b5-a5af7809e4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057280973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3057280973
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.1707002246
Short name T335
Test name
Test status
Simulation time 34085939 ps
CPU time 0.65 seconds
Started Jul 27 06:16:25 PM PDT 24
Finished Jul 27 06:16:25 PM PDT 24
Peak memory 197400 kb
Host smart-c0dfbb3b-b2b7-4eb6-b36d-868bebe75ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707002246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.1707002246
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.1705791732
Short name T411
Test name
Test status
Simulation time 36159222 ps
CPU time 0.64 seconds
Started Jul 27 06:16:18 PM PDT 24
Finished Jul 27 06:16:19 PM PDT 24
Peak memory 198180 kb
Host smart-df0f6c29-045e-4e34-973b-f693fec155ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705791732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1705791732
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.3113684666
Short name T463
Test name
Test status
Simulation time 46539464 ps
CPU time 0.67 seconds
Started Jul 27 06:16:14 PM PDT 24
Finished Jul 27 06:16:14 PM PDT 24
Peak memory 198228 kb
Host smart-f1c38711-b18e-417f-844f-6a613f04e826
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113684666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3113684666
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2895645287
Short name T404
Test name
Test status
Simulation time 126365827 ps
CPU time 0.85 seconds
Started Jul 27 06:16:24 PM PDT 24
Finished Jul 27 06:16:25 PM PDT 24
Peak memory 209496 kb
Host smart-d1808cff-4a7d-4d1e-b907-58720142d800
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895645287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2895645287
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1412603198
Short name T64
Test name
Test status
Simulation time 115252235 ps
CPU time 0.68 seconds
Started Jul 27 06:16:20 PM PDT 24
Finished Jul 27 06:16:21 PM PDT 24
Peak memory 198604 kb
Host smart-97bb9476-57d1-458b-ba63-0bdf722d6d8b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412603198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1412603198
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1608606512
Short name T614
Test name
Test status
Simulation time 104817948 ps
CPU time 0.75 seconds
Started Jul 27 06:16:20 PM PDT 24
Finished Jul 27 06:16:21 PM PDT 24
Peak memory 198168 kb
Host smart-0fa5fece-5b9d-4ac9-a832-7b9e8a3b123c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608606512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1608606512
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.417514433
Short name T69
Test name
Test status
Simulation time 63120607 ps
CPU time 0.65 seconds
Started Jul 27 06:16:13 PM PDT 24
Finished Jul 27 06:16:14 PM PDT 24
Peak memory 198556 kb
Host smart-bfa30913-77b3-441d-b9f7-33dae35f1d27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417514433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.417514433
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.4001116845
Short name T357
Test name
Test status
Simulation time 118234128 ps
CPU time 0.81 seconds
Started Jul 27 06:16:19 PM PDT 24
Finished Jul 27 06:16:20 PM PDT 24
Peak memory 200048 kb
Host smart-68f257b4-b65f-41c0-af7e-5f6e8caad564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001116845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.4001116845
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2257257345
Short name T139
Test name
Test status
Simulation time 75204274 ps
CPU time 0.66 seconds
Started Jul 27 06:16:27 PM PDT 24
Finished Jul 27 06:16:28 PM PDT 24
Peak memory 198532 kb
Host smart-dfdf91c4-442e-4d49-9fd9-a5fd14b20f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257257345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2257257345
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1463957505
Short name T521
Test name
Test status
Simulation time 39123638 ps
CPU time 0.59 seconds
Started Jul 27 06:16:17 PM PDT 24
Finished Jul 27 06:16:18 PM PDT 24
Peak memory 197376 kb
Host smart-a9f5c2d0-c542-42f8-8d3c-074d5c44169c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463957505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1463957505
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2108786405
Short name T402
Test name
Test status
Simulation time 163717200 ps
CPU time 1 seconds
Started Jul 27 06:16:27 PM PDT 24
Finished Jul 27 06:16:28 PM PDT 24
Peak memory 198128 kb
Host smart-a009266d-e831-495b-8435-e27d01391cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108786405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2108786405
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2782308999
Short name T229
Test name
Test status
Simulation time 48003455 ps
CPU time 0.6 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:29 PM PDT 24
Peak memory 198124 kb
Host smart-80fb8b9f-bb52-406d-847b-29c04cde3ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782308999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2782308999
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1227592417
Short name T304
Test name
Test status
Simulation time 32883469 ps
CPU time 0.65 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:28 PM PDT 24
Peak memory 198160 kb
Host smart-2d60621a-1104-4def-808d-a2e1c31dda0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227592417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1227592417
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.167884304
Short name T191
Test name
Test status
Simulation time 50146788 ps
CPU time 0.68 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:29 PM PDT 24
Peak memory 201464 kb
Host smart-56d34cc7-62d8-4863-8e1d-d424462ddfa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167884304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.167884304
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.3779902490
Short name T277
Test name
Test status
Simulation time 50542720 ps
CPU time 0.6 seconds
Started Jul 27 06:16:19 PM PDT 24
Finished Jul 27 06:16:20 PM PDT 24
Peak memory 198140 kb
Host smart-c55881b0-b39c-4396-b1ee-2013645beba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779902490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.3779902490
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1191246215
Short name T486
Test name
Test status
Simulation time 97488768 ps
CPU time 0.96 seconds
Started Jul 27 06:16:27 PM PDT 24
Finished Jul 27 06:16:28 PM PDT 24
Peak memory 209572 kb
Host smart-b88d72ce-829c-40ab-a874-3e73f286d755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191246215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1191246215
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1281224338
Short name T446
Test name
Test status
Simulation time 62794213 ps
CPU time 0.81 seconds
Started Jul 27 06:16:21 PM PDT 24
Finished Jul 27 06:16:22 PM PDT 24
Peak memory 199224 kb
Host smart-29263190-fdac-48d0-924b-ee30cef16449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281224338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1281224338
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.471575077
Short name T15
Test name
Test status
Simulation time 48409210 ps
CPU time 0.63 seconds
Started Jul 27 06:16:20 PM PDT 24
Finished Jul 27 06:16:21 PM PDT 24
Peak memory 199384 kb
Host smart-c291e2a1-4b39-42e4-b5fd-d4d4b80d9d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471575077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.471575077
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.4041792796
Short name T37
Test name
Test status
Simulation time 129918096 ps
CPU time 0.79 seconds
Started Jul 27 06:16:26 PM PDT 24
Finished Jul 27 06:16:27 PM PDT 24
Peak memory 200008 kb
Host smart-7b981b29-1b9c-4af0-ba71-4c504aaff97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041792796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.4041792796
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3468508986
Short name T585
Test name
Test status
Simulation time 39934535 ps
CPU time 0.61 seconds
Started Jul 27 06:16:31 PM PDT 24
Finished Jul 27 06:16:32 PM PDT 24
Peak memory 198084 kb
Host smart-198959a3-ff29-4c17-98ec-bff9a00eb833
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468508986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3468508986
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1011536593
Short name T513
Test name
Test status
Simulation time 320577226 ps
CPU time 1 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:29 PM PDT 24
Peak memory 198176 kb
Host smart-a0587263-57c2-4534-aaa3-fbfa05f2b466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011536593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1011536593
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.3769341141
Short name T351
Test name
Test status
Simulation time 33582660 ps
CPU time 0.6 seconds
Started Jul 27 06:16:37 PM PDT 24
Finished Jul 27 06:16:38 PM PDT 24
Peak memory 198148 kb
Host smart-2441a286-1fa1-4273-a4f6-18c906289762
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769341141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3769341141
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.265755779
Short name T458
Test name
Test status
Simulation time 46806649 ps
CPU time 0.63 seconds
Started Jul 27 06:16:27 PM PDT 24
Finished Jul 27 06:16:28 PM PDT 24
Peak memory 198152 kb
Host smart-ecc8b63d-9260-4647-a61b-60fcd424da32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265755779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.265755779
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.4134736189
Short name T200
Test name
Test status
Simulation time 70446834 ps
CPU time 0.68 seconds
Started Jul 27 06:16:46 PM PDT 24
Finished Jul 27 06:16:47 PM PDT 24
Peak memory 201436 kb
Host smart-3f6ea5a2-c7be-4a16-a106-bfbecd573ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134736189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.4134736189
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3101155003
Short name T549
Test name
Test status
Simulation time 41508969 ps
CPU time 0.65 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:29 PM PDT 24
Peak memory 198328 kb
Host smart-bb34e0a3-79ae-4759-a601-fe026113368f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101155003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3101155003
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3741530383
Short name T433
Test name
Test status
Simulation time 135286322 ps
CPU time 0.87 seconds
Started Jul 27 06:16:47 PM PDT 24
Finished Jul 27 06:16:48 PM PDT 24
Peak memory 209516 kb
Host smart-e82657e3-be31-46b1-96b7-c75b9f80e3ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741530383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3741530383
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1952216005
Short name T359
Test name
Test status
Simulation time 80986195 ps
CPU time 0.71 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:29 PM PDT 24
Peak memory 198108 kb
Host smart-2673dce3-8ab0-4f13-a07a-9f88dd0102b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952216005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1952216005
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1710088101
Short name T282
Test name
Test status
Simulation time 45725449 ps
CPU time 0.66 seconds
Started Jul 27 06:16:28 PM PDT 24
Finished Jul 27 06:16:30 PM PDT 24
Peak memory 199424 kb
Host smart-be7d099f-4219-4e9c-aaf2-af8a8199811e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710088101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1710088101
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2529157279
Short name T95
Test name
Test status
Simulation time 51478049 ps
CPU time 0.78 seconds
Started Jul 27 06:16:47 PM PDT 24
Finished Jul 27 06:16:48 PM PDT 24
Peak memory 199940 kb
Host smart-434e5f27-2a8f-4847-a8fa-92cc7ce18cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529157279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2529157279
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1350769006
Short name T308
Test name
Test status
Simulation time 63984613 ps
CPU time 0.65 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 198368 kb
Host smart-69c2e319-1c0a-4794-b7a7-cd38bc24d732
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350769006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1350769006
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.89142946
Short name T454
Test name
Test status
Simulation time 28782467 ps
CPU time 0.62 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 197368 kb
Host smart-6a0f8899-7d53-4b5b-98e4-73998d3b31ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89142946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_m
alfunc.89142946
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.379519430
Short name T536
Test name
Test status
Simulation time 316807320 ps
CPU time 0.96 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 198164 kb
Host smart-b96f2d7d-ea47-4a87-a791-8580b07e6554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379519430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.379519430
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1381006810
Short name T493
Test name
Test status
Simulation time 94340568 ps
CPU time 0.6 seconds
Started Jul 27 06:16:49 PM PDT 24
Finished Jul 27 06:16:50 PM PDT 24
Peak memory 198120 kb
Host smart-44278a74-3d49-4a76-a63b-9727293aac82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381006810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1381006810
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3340800885
Short name T315
Test name
Test status
Simulation time 79418009 ps
CPU time 0.6 seconds
Started Jul 27 06:16:47 PM PDT 24
Finished Jul 27 06:16:48 PM PDT 24
Peak memory 198124 kb
Host smart-c0668e28-cebb-44b9-980d-a78da2bb0d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340800885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3340800885
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.468875170
Short name T42
Test name
Test status
Simulation time 41629465 ps
CPU time 0.7 seconds
Started Jul 27 06:16:47 PM PDT 24
Finished Jul 27 06:16:48 PM PDT 24
Peak memory 199144 kb
Host smart-e56cffa3-b2bf-4348-b14f-7fca5fddce2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468875170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.468875170
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3970175040
Short name T271
Test name
Test status
Simulation time 150992053 ps
CPU time 0.86 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 209500 kb
Host smart-33bb4cc8-5e0e-469c-9b20-011d1a112783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970175040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3970175040
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2303245045
Short name T305
Test name
Test status
Simulation time 108322542 ps
CPU time 0.77 seconds
Started Jul 27 06:16:46 PM PDT 24
Finished Jul 27 06:16:47 PM PDT 24
Peak memory 198176 kb
Host smart-0473ded8-7868-458a-8a86-e6d0602b0be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303245045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2303245045
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.1048774464
Short name T571
Test name
Test status
Simulation time 30826125 ps
CPU time 0.72 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 199408 kb
Host smart-3b3d4d70-8a11-48ca-8227-ca8402cc7629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048774464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1048774464
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.316200904
Short name T17
Test name
Test status
Simulation time 49336234 ps
CPU time 0.75 seconds
Started Jul 27 06:16:51 PM PDT 24
Finished Jul 27 06:16:52 PM PDT 24
Peak memory 199944 kb
Host smart-adb80b15-c1c6-4582-be70-8e2accf367c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316200904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.316200904
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.4252471659
Short name T546
Test name
Test status
Simulation time 64319085 ps
CPU time 0.73 seconds
Started Jul 27 06:16:50 PM PDT 24
Finished Jul 27 06:16:51 PM PDT 24
Peak memory 199196 kb
Host smart-5b66b5e1-8326-4be9-bfef-7784664a4d23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252471659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.4252471659
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3944434504
Short name T550
Test name
Test status
Simulation time 161695678 ps
CPU time 0.97 seconds
Started Jul 27 06:16:49 PM PDT 24
Finished Jul 27 06:16:50 PM PDT 24
Peak memory 198456 kb
Host smart-bcbdc531-755b-4372-ba2a-6c0821a65754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944434504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3944434504
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2029367354
Short name T279
Test name
Test status
Simulation time 48176906 ps
CPU time 0.68 seconds
Started Jul 27 06:16:50 PM PDT 24
Finished Jul 27 06:16:51 PM PDT 24
Peak memory 197436 kb
Host smart-bc16852d-0229-4680-bb88-727292e38498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029367354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2029367354
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.2620368352
Short name T532
Test name
Test status
Simulation time 51607728 ps
CPU time 0.6 seconds
Started Jul 27 06:16:50 PM PDT 24
Finished Jul 27 06:16:50 PM PDT 24
Peak memory 198444 kb
Host smart-e1ce07f9-2015-46f5-8500-4b812efc5968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620368352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2620368352
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3036308921
Short name T197
Test name
Test status
Simulation time 49812436 ps
CPU time 0.72 seconds
Started Jul 27 06:16:50 PM PDT 24
Finished Jul 27 06:16:51 PM PDT 24
Peak memory 201220 kb
Host smart-fc37fafa-067e-4b35-8f1d-59be7efa0a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036308921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3036308921
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3254096753
Short name T479
Test name
Test status
Simulation time 75040376 ps
CPU time 0.93 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 198556 kb
Host smart-f5c7cec4-2ac7-4ab4-aa02-a13f210a8596
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254096753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3254096753
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3234847200
Short name T290
Test name
Test status
Simulation time 198117007 ps
CPU time 0.87 seconds
Started Jul 27 06:16:51 PM PDT 24
Finished Jul 27 06:16:52 PM PDT 24
Peak memory 209552 kb
Host smart-91bef018-6645-499e-94da-f26b3b0de584
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234847200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3234847200
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.89451157
Short name T124
Test name
Test status
Simulation time 108923428 ps
CPU time 0.9 seconds
Started Jul 27 06:16:48 PM PDT 24
Finished Jul 27 06:16:49 PM PDT 24
Peak memory 199408 kb
Host smart-a25197fc-af47-46c9-8eb6-63a6141cf5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89451157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.89451157
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3658073188
Short name T361
Test name
Test status
Simulation time 41311880 ps
CPU time 0.64 seconds
Started Jul 27 06:16:45 PM PDT 24
Finished Jul 27 06:16:46 PM PDT 24
Peak memory 198688 kb
Host smart-9626952f-c915-40db-8d61-c3ab980856ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658073188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3658073188
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3882142622
Short name T358
Test name
Test status
Simulation time 39015304 ps
CPU time 0.67 seconds
Started Jul 27 06:17:00 PM PDT 24
Finished Jul 27 06:17:01 PM PDT 24
Peak memory 198716 kb
Host smart-ec63e221-004f-4b44-abbd-caf69af5f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882142622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3882142622
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2897046200
Short name T503
Test name
Test status
Simulation time 60606716 ps
CPU time 0.92 seconds
Started Jul 27 06:17:01 PM PDT 24
Finished Jul 27 06:17:02 PM PDT 24
Peak memory 199176 kb
Host smart-291372c9-0dbf-4bc0-8f53-f87ba026581a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897046200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2897046200
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.622691413
Short name T326
Test name
Test status
Simulation time 38834785 ps
CPU time 0.61 seconds
Started Jul 27 06:17:02 PM PDT 24
Finished Jul 27 06:17:03 PM PDT 24
Peak memory 198084 kb
Host smart-e917c872-3773-48d9-816c-dc34167a7ef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622691413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.622691413
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1698263114
Short name T477
Test name
Test status
Simulation time 166065867 ps
CPU time 1 seconds
Started Jul 27 06:17:04 PM PDT 24
Finished Jul 27 06:17:06 PM PDT 24
Peak memory 198472 kb
Host smart-fe0721f3-0a90-453a-84f8-0634201a7840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698263114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1698263114
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1512072533
Short name T318
Test name
Test status
Simulation time 33052634 ps
CPU time 0.61 seconds
Started Jul 27 06:16:59 PM PDT 24
Finished Jul 27 06:17:00 PM PDT 24
Peak memory 197468 kb
Host smart-143bc70d-88c1-4449-970e-6137b347299e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512072533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1512072533
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1712071249
Short name T247
Test name
Test status
Simulation time 106213956 ps
CPU time 0.63 seconds
Started Jul 27 06:17:03 PM PDT 24
Finished Jul 27 06:17:04 PM PDT 24
Peak memory 198136 kb
Host smart-862ba6df-ffe4-4603-abd4-2f5ef8f77c34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712071249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1712071249
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.2003073593
Short name T178
Test name
Test status
Simulation time 43149323 ps
CPU time 0.71 seconds
Started Jul 27 06:17:05 PM PDT 24
Finished Jul 27 06:17:06 PM PDT 24
Peak memory 201416 kb
Host smart-5d527a8e-8377-4a64-84a2-0959ca4d3bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003073593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.2003073593
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.492670581
Short name T45
Test name
Test status
Simulation time 41266933 ps
CPU time 0.72 seconds
Started Jul 27 06:16:50 PM PDT 24
Finished Jul 27 06:16:51 PM PDT 24
Peak memory 199168 kb
Host smart-b5e460a0-3b13-4a91-89b4-6b5906281a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492670581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.492670581
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1627453795
Short name T497
Test name
Test status
Simulation time 102243600 ps
CPU time 1.08 seconds
Started Jul 27 06:17:04 PM PDT 24
Finished Jul 27 06:17:05 PM PDT 24
Peak memory 209544 kb
Host smart-83ea90ba-4aa0-449e-8f84-cabdc68d1f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627453795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1627453795
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3293449979
Short name T47
Test name
Test status
Simulation time 54286774 ps
CPU time 0.81 seconds
Started Jul 27 06:16:59 PM PDT 24
Finished Jul 27 06:17:00 PM PDT 24
Peak memory 198208 kb
Host smart-ebbc28a6-22af-42c2-b039-a669e5e6f1df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293449979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3293449979
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1346357087
Short name T589
Test name
Test status
Simulation time 47587496 ps
CPU time 0.71 seconds
Started Jul 27 06:16:51 PM PDT 24
Finished Jul 27 06:16:52 PM PDT 24
Peak memory 199488 kb
Host smart-8ab291f3-7b4a-437c-97d7-1ac466357855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346357087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1346357087
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3783026656
Short name T547
Test name
Test status
Simulation time 51193490 ps
CPU time 1 seconds
Started Jul 27 06:13:03 PM PDT 24
Finished Jul 27 06:13:04 PM PDT 24
Peak memory 200808 kb
Host smart-f22b655b-5668-4136-b8be-3f9f449e31c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783026656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3783026656
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.4241829245
Short name T519
Test name
Test status
Simulation time 55585223 ps
CPU time 0.81 seconds
Started Jul 27 06:13:09 PM PDT 24
Finished Jul 27 06:13:10 PM PDT 24
Peak memory 198560 kb
Host smart-68f9eb07-0947-4af8-84c8-73a87b2176b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241829245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.4241829245
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2125474269
Short name T592
Test name
Test status
Simulation time 29481839 ps
CPU time 0.63 seconds
Started Jul 27 06:13:05 PM PDT 24
Finished Jul 27 06:13:06 PM PDT 24
Peak memory 198080 kb
Host smart-6f4aa25a-71ad-4ddc-a748-9efbee0df997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125474269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2125474269
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3277363486
Short name T340
Test name
Test status
Simulation time 304723999 ps
CPU time 0.97 seconds
Started Jul 27 06:13:04 PM PDT 24
Finished Jul 27 06:13:05 PM PDT 24
Peak memory 198148 kb
Host smart-8c86312c-6900-4777-9394-2d41578ffa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277363486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3277363486
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.3621649566
Short name T422
Test name
Test status
Simulation time 49571262 ps
CPU time 0.68 seconds
Started Jul 27 06:13:04 PM PDT 24
Finished Jul 27 06:13:05 PM PDT 24
Peak memory 197384 kb
Host smart-58b185ee-16d7-43e0-b6d8-52561965ac49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621649566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3621649566
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3902356623
Short name T593
Test name
Test status
Simulation time 51391984 ps
CPU time 0.69 seconds
Started Jul 27 06:13:03 PM PDT 24
Finished Jul 27 06:13:03 PM PDT 24
Peak memory 198136 kb
Host smart-04ea2c6d-456c-44a9-b3f3-bdc3bbd03692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902356623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3902356623
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.3379754672
Short name T202
Test name
Test status
Simulation time 42860546 ps
CPU time 0.74 seconds
Started Jul 27 06:13:08 PM PDT 24
Finished Jul 27 06:13:09 PM PDT 24
Peak memory 201500 kb
Host smart-33ff6237-c834-4f5d-8e45-9445173de2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379754672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.3379754672
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.681474225
Short name T148
Test name
Test status
Simulation time 51924060 ps
CPU time 0.78 seconds
Started Jul 27 06:12:54 PM PDT 24
Finished Jul 27 06:12:55 PM PDT 24
Peak memory 198456 kb
Host smart-44196a82-d945-4760-9384-83f9408aba0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681474225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wak
eup_race.681474225
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1817702584
Short name T369
Test name
Test status
Simulation time 64986945 ps
CPU time 0.65 seconds
Started Jul 27 06:12:51 PM PDT 24
Finished Jul 27 06:12:52 PM PDT 24
Peak memory 198284 kb
Host smart-2a9985e1-f019-499e-b625-eee332b6f6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817702584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1817702584
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3011544277
Short name T601
Test name
Test status
Simulation time 165717506 ps
CPU time 0.8 seconds
Started Jul 27 06:13:08 PM PDT 24
Finished Jul 27 06:13:09 PM PDT 24
Peak memory 209568 kb
Host smart-fe9fb19b-6513-49ad-b620-02760803eaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011544277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3011544277
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.1514926635
Short name T34
Test name
Test status
Simulation time 765473552 ps
CPU time 1.59 seconds
Started Jul 27 06:13:09 PM PDT 24
Finished Jul 27 06:13:10 PM PDT 24
Peak memory 218056 kb
Host smart-a700d710-cd86-4185-8629-493e164a98d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514926635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1514926635
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3319060233
Short name T302
Test name
Test status
Simulation time 62536358 ps
CPU time 0.86 seconds
Started Jul 27 06:13:02 PM PDT 24
Finished Jul 27 06:13:03 PM PDT 24
Peak memory 199168 kb
Host smart-e07f182e-47a5-4b45-8acb-eaf0712565fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319060233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3319060233
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.1775844815
Short name T518
Test name
Test status
Simulation time 53980115 ps
CPU time 0.67 seconds
Started Jul 27 06:12:50 PM PDT 24
Finished Jul 27 06:12:51 PM PDT 24
Peak memory 198580 kb
Host smart-b671a61f-92a4-4ecf-b283-7d693f3b2d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775844815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1775844815
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2846536091
Short name T501
Test name
Test status
Simulation time 92878199 ps
CPU time 0.82 seconds
Started Jul 27 06:17:02 PM PDT 24
Finished Jul 27 06:17:03 PM PDT 24
Peak memory 200160 kb
Host smart-20f7cf4c-ec8e-40d6-90ff-0ca118232ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846536091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2846536091
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.123617592
Short name T155
Test name
Test status
Simulation time 57574686 ps
CPU time 0.8 seconds
Started Jul 27 06:16:59 PM PDT 24
Finished Jul 27 06:17:00 PM PDT 24
Peak memory 199128 kb
Host smart-d5c70679-974d-434f-a243-b20068d503d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123617592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.123617592
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1189607391
Short name T465
Test name
Test status
Simulation time 46268501 ps
CPU time 0.59 seconds
Started Jul 27 06:16:59 PM PDT 24
Finished Jul 27 06:17:00 PM PDT 24
Peak memory 198076 kb
Host smart-ed029d20-9bec-4c3e-95e5-038c13c32494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189607391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1189607391
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3972280641
Short name T377
Test name
Test status
Simulation time 935442461 ps
CPU time 0.91 seconds
Started Jul 27 06:16:59 PM PDT 24
Finished Jul 27 06:17:00 PM PDT 24
Peak memory 198164 kb
Host smart-47319d12-9172-4156-a039-88eaba85d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972280641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3972280641
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.3619427286
Short name T237
Test name
Test status
Simulation time 75111699 ps
CPU time 0.65 seconds
Started Jul 27 06:17:05 PM PDT 24
Finished Jul 27 06:17:05 PM PDT 24
Peak memory 198096 kb
Host smart-92f431c6-84b1-4c95-b24b-fb05f183876b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619427286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3619427286
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2624724229
Short name T605
Test name
Test status
Simulation time 185797182 ps
CPU time 0.63 seconds
Started Jul 27 06:17:07 PM PDT 24
Finished Jul 27 06:17:07 PM PDT 24
Peak memory 198048 kb
Host smart-792328d6-0522-4614-907c-a7cffbf5615e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624724229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2624724229
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3050250643
Short name T184
Test name
Test status
Simulation time 66385961 ps
CPU time 0.69 seconds
Started Jul 27 06:17:04 PM PDT 24
Finished Jul 27 06:17:04 PM PDT 24
Peak memory 201412 kb
Host smart-b98a3943-d7e1-4e9f-b6bf-abcff0fbabb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050250643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.3050250643
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2705405826
Short name T544
Test name
Test status
Simulation time 72972942 ps
CPU time 0.95 seconds
Started Jul 27 06:17:03 PM PDT 24
Finished Jul 27 06:17:04 PM PDT 24
Peak memory 199228 kb
Host smart-1cb25232-cf96-4dc5-a2de-c45f2be27b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705405826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2705405826
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2927571220
Short name T219
Test name
Test status
Simulation time 155795118 ps
CPU time 0.84 seconds
Started Jul 27 06:17:01 PM PDT 24
Finished Jul 27 06:17:02 PM PDT 24
Peak memory 209520 kb
Host smart-5cbe3c03-4e8d-48f3-bef6-b00e401956c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927571220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2927571220
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2476571269
Short name T94
Test name
Test status
Simulation time 123422384 ps
CPU time 0.77 seconds
Started Jul 27 06:17:01 PM PDT 24
Finished Jul 27 06:17:02 PM PDT 24
Peak memory 199288 kb
Host smart-7fee7ba2-ef26-4f60-8232-42dbc596d78a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476571269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2476571269
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.1438917286
Short name T407
Test name
Test status
Simulation time 49980458 ps
CPU time 0.63 seconds
Started Jul 27 06:17:01 PM PDT 24
Finished Jul 27 06:17:01 PM PDT 24
Peak memory 199424 kb
Host smart-e9b8bade-3614-47fa-a217-beb90b44711b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438917286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1438917286
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.524353316
Short name T97
Test name
Test status
Simulation time 35598301 ps
CPU time 0.62 seconds
Started Jul 27 06:17:04 PM PDT 24
Finished Jul 27 06:17:05 PM PDT 24
Peak memory 198676 kb
Host smart-ea7dd172-5dde-48c7-872d-8226a379aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524353316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.524353316
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1074685600
Short name T170
Test name
Test status
Simulation time 71116976 ps
CPU time 0.67 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 198456 kb
Host smart-ee5f7a06-7fa5-4b6e-ad39-990d5d9289a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074685600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1074685600
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.355622155
Short name T512
Test name
Test status
Simulation time 86404163 ps
CPU time 0.59 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 198048 kb
Host smart-b707acc2-33cb-4710-af5b-4397c32f0f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355622155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_
malfunc.355622155
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.918665556
Short name T606
Test name
Test status
Simulation time 320111257 ps
CPU time 0.98 seconds
Started Jul 27 06:17:26 PM PDT 24
Finished Jul 27 06:17:27 PM PDT 24
Peak memory 198176 kb
Host smart-858d16a5-b6df-4fb9-bdb7-49ad94a85e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918665556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.918665556
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1652367690
Short name T374
Test name
Test status
Simulation time 56217296 ps
CPU time 0.61 seconds
Started Jul 27 06:17:11 PM PDT 24
Finished Jul 27 06:17:12 PM PDT 24
Peak memory 197452 kb
Host smart-2913ca49-2685-4544-a421-b8a4891219de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652367690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1652367690
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.3563991688
Short name T332
Test name
Test status
Simulation time 48956355 ps
CPU time 0.59 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 198148 kb
Host smart-f3db819a-66fe-4959-bdc6-7339ce532d86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563991688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3563991688
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.4263045044
Short name T50
Test name
Test status
Simulation time 55453467 ps
CPU time 0.68 seconds
Started Jul 27 06:17:21 PM PDT 24
Finished Jul 27 06:17:22 PM PDT 24
Peak memory 201424 kb
Host smart-04695d3d-e405-407f-a7db-ae06acc62a12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263045044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.4263045044
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.2030952094
Short name T573
Test name
Test status
Simulation time 48119832 ps
CPU time 0.77 seconds
Started Jul 27 06:17:02 PM PDT 24
Finished Jul 27 06:17:03 PM PDT 24
Peak memory 198392 kb
Host smart-04ebadf4-8eaa-4e07-a5be-80dd33c4ac18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030952094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2030952094
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.2045560400
Short name T248
Test name
Test status
Simulation time 163028043 ps
CPU time 0.79 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 209612 kb
Host smart-9c58ec14-015c-42c6-b625-841288cfcfbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045560400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.2045560400
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3785456394
Short name T502
Test name
Test status
Simulation time 53912112 ps
CPU time 0.89 seconds
Started Jul 27 06:17:10 PM PDT 24
Finished Jul 27 06:17:11 PM PDT 24
Peak memory 198228 kb
Host smart-193638e3-e6ba-4cd7-a6b4-6944b20ca940
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785456394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3785456394
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.479570377
Short name T381
Test name
Test status
Simulation time 37900374 ps
CPU time 0.65 seconds
Started Jul 27 06:17:00 PM PDT 24
Finished Jul 27 06:17:01 PM PDT 24
Peak memory 198516 kb
Host smart-b81abb10-442b-4ca8-9cde-282797d50d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479570377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.479570377
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2791958351
Short name T390
Test name
Test status
Simulation time 111631067 ps
CPU time 0.8 seconds
Started Jul 27 06:17:11 PM PDT 24
Finished Jul 27 06:17:11 PM PDT 24
Peak memory 200160 kb
Host smart-368e3bfa-65df-4baf-b035-873caa46ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791958351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2791958351
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1364423363
Short name T471
Test name
Test status
Simulation time 71277056 ps
CPU time 0.68 seconds
Started Jul 27 06:17:13 PM PDT 24
Finished Jul 27 06:17:14 PM PDT 24
Peak memory 199128 kb
Host smart-5b87c21a-6d6c-46e5-9cce-bc1bb4b6ef0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364423363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1364423363
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2982909526
Short name T49
Test name
Test status
Simulation time 32418770 ps
CPU time 0.61 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 197320 kb
Host smart-8dc334f0-5bc9-4ac4-88ac-78c0eb8e409b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982909526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2982909526
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.3039477220
Short name T352
Test name
Test status
Simulation time 364911942 ps
CPU time 0.98 seconds
Started Jul 27 06:17:15 PM PDT 24
Finished Jul 27 06:17:16 PM PDT 24
Peak memory 198496 kb
Host smart-6d8bbff4-f5ab-4cc1-9cf5-99f410139e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039477220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3039477220
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3052924235
Short name T280
Test name
Test status
Simulation time 32306047 ps
CPU time 0.63 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 197364 kb
Host smart-f48e93d7-e386-4c3b-a8a1-aac728814c48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052924235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3052924235
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.327831400
Short name T366
Test name
Test status
Simulation time 34899560 ps
CPU time 0.62 seconds
Started Jul 27 06:17:12 PM PDT 24
Finished Jul 27 06:17:13 PM PDT 24
Peak memory 198124 kb
Host smart-82f92e03-bc6c-434b-adbb-e75f8c473b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327831400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.327831400
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.525434683
Short name T578
Test name
Test status
Simulation time 46496723 ps
CPU time 0.71 seconds
Started Jul 27 06:17:23 PM PDT 24
Finished Jul 27 06:17:24 PM PDT 24
Peak memory 201432 kb
Host smart-a8442cb9-8fc2-4ae3-8e9d-1b376ef939da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525434683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.525434683
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2552282729
Short name T213
Test name
Test status
Simulation time 74108556 ps
CPU time 0.66 seconds
Started Jul 27 06:17:11 PM PDT 24
Finished Jul 27 06:17:12 PM PDT 24
Peak memory 198252 kb
Host smart-a63f2021-cbb7-4109-9ad7-37f077e29087
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552282729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2552282729
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.488374391
Short name T297
Test name
Test status
Simulation time 169383358 ps
CPU time 0.8 seconds
Started Jul 27 06:17:11 PM PDT 24
Finished Jul 27 06:17:11 PM PDT 24
Peak memory 209580 kb
Host smart-c6816603-68ef-43c7-84c5-30560c7b2fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488374391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.488374391
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797327481
Short name T222
Test name
Test status
Simulation time 52157122 ps
CPU time 0.78 seconds
Started Jul 27 06:17:13 PM PDT 24
Finished Jul 27 06:17:14 PM PDT 24
Peak memory 198136 kb
Host smart-b475b99e-5021-4cc6-b302-65fe2ef2f0cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797327481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3797327481
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1895021106
Short name T588
Test name
Test status
Simulation time 55667654 ps
CPU time 0.65 seconds
Started Jul 27 06:17:14 PM PDT 24
Finished Jul 27 06:17:15 PM PDT 24
Peak memory 198612 kb
Host smart-2f9456bf-86ee-4aeb-b4b7-36810e1d8bad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895021106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1895021106
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.336385841
Short name T188
Test name
Test status
Simulation time 28565722 ps
CPU time 0.65 seconds
Started Jul 27 06:17:26 PM PDT 24
Finished Jul 27 06:17:26 PM PDT 24
Peak memory 198360 kb
Host smart-58476a41-372e-4143-814a-1847500dae87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336385841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.336385841
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.695870592
Short name T320
Test name
Test status
Simulation time 46208015 ps
CPU time 0.6 seconds
Started Jul 27 06:17:19 PM PDT 24
Finished Jul 27 06:17:20 PM PDT 24
Peak memory 198524 kb
Host smart-ba49f73c-61cb-40d5-bea0-a3c29eb03765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695870592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.695870592
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1358186924
Short name T459
Test name
Test status
Simulation time 58375019 ps
CPU time 0.75 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 198552 kb
Host smart-ec4528d1-f83e-4129-b991-1c7804641dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358186924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1358186924
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.4072192159
Short name T259
Test name
Test status
Simulation time 29595074 ps
CPU time 0.63 seconds
Started Jul 27 06:17:27 PM PDT 24
Finished Jul 27 06:17:28 PM PDT 24
Peak memory 198064 kb
Host smart-86f50c15-9dc3-4fb3-8e8a-cb927bacd0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072192159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.4072192159
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.693742468
Short name T244
Test name
Test status
Simulation time 272414572 ps
CPU time 1.02 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 198188 kb
Host smart-73789b6c-b656-429e-b694-f3e781b09853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693742468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.693742468
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3919721637
Short name T568
Test name
Test status
Simulation time 48475478 ps
CPU time 0.69 seconds
Started Jul 27 06:17:28 PM PDT 24
Finished Jul 27 06:17:29 PM PDT 24
Peak memory 198088 kb
Host smart-48bb3e6f-dc47-4471-959c-33651a30135f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919721637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3919721637
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.4152644454
Short name T296
Test name
Test status
Simulation time 144492758 ps
CPU time 0.61 seconds
Started Jul 27 06:17:28 PM PDT 24
Finished Jul 27 06:17:28 PM PDT 24
Peak memory 198116 kb
Host smart-a554480b-e9cb-4184-abb2-ba826fe9e027
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152644454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.4152644454
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1208263668
Short name T192
Test name
Test status
Simulation time 79841707 ps
CPU time 0.67 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 201420 kb
Host smart-3f1e0d75-5844-417a-a357-535e2c7b8c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208263668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1208263668
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2673661815
Short name T500
Test name
Test status
Simulation time 126459691 ps
CPU time 0.73 seconds
Started Jul 27 06:17:21 PM PDT 24
Finished Jul 27 06:17:22 PM PDT 24
Peak memory 199224 kb
Host smart-a911e477-355f-4591-ba24-74a4e4ec566c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673661815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2673661815
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.3462360311
Short name T262
Test name
Test status
Simulation time 145411770 ps
CPU time 0.84 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 209500 kb
Host smart-83b4dc22-c6c2-4fb2-bd94-c932824c3d2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462360311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3462360311
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.150312795
Short name T572
Test name
Test status
Simulation time 149771716 ps
CPU time 0.74 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 198220 kb
Host smart-52a2e9eb-ff6b-4db0-98e3-fb045f48b217
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150312795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_
mubi.150312795
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.1905657343
Short name T272
Test name
Test status
Simulation time 64509027 ps
CPU time 0.65 seconds
Started Jul 27 06:17:20 PM PDT 24
Finished Jul 27 06:17:21 PM PDT 24
Peak memory 198552 kb
Host smart-848ca669-d374-4f61-b85f-2a375668f760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905657343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1905657343
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.3678188833
Short name T265
Test name
Test status
Simulation time 33860782 ps
CPU time 0.87 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 200220 kb
Host smart-2675c392-026c-4cb0-be88-36d17ddfe954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678188833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.3678188833
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2715699170
Short name T538
Test name
Test status
Simulation time 52321031 ps
CPU time 0.83 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 198716 kb
Host smart-92539a4a-e65a-4f48-bd3d-706a64a7aa2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715699170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2715699170
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.339329090
Short name T307
Test name
Test status
Simulation time 28594664 ps
CPU time 0.62 seconds
Started Jul 27 06:17:27 PM PDT 24
Finished Jul 27 06:17:28 PM PDT 24
Peak memory 197360 kb
Host smart-1479553f-e51b-4695-ac41-ea2bcdf60538
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339329090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_
malfunc.339329090
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.714280503
Short name T558
Test name
Test status
Simulation time 604009756 ps
CPU time 0.96 seconds
Started Jul 27 06:17:28 PM PDT 24
Finished Jul 27 06:17:29 PM PDT 24
Peak memory 198436 kb
Host smart-e819b02c-d17d-4af7-9e0d-de9c8b57b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714280503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.714280503
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.1675021862
Short name T256
Test name
Test status
Simulation time 85294067 ps
CPU time 0.57 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:29 PM PDT 24
Peak memory 198076 kb
Host smart-11bf69c3-1950-456a-96d7-f41397583361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675021862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1675021862
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3531633179
Short name T232
Test name
Test status
Simulation time 47011866 ps
CPU time 0.67 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 198152 kb
Host smart-7b909273-82ff-4f8c-a087-9579449a3487
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531633179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3531633179
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.3747646619
Short name T492
Test name
Test status
Simulation time 63437390 ps
CPU time 0.66 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 201488 kb
Host smart-0445db53-081a-41b5-9765-db6dbd10b1e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747646619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.3747646619
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1258315822
Short name T350
Test name
Test status
Simulation time 102750379 ps
CPU time 0.73 seconds
Started Jul 27 06:17:28 PM PDT 24
Finished Jul 27 06:17:29 PM PDT 24
Peak memory 198404 kb
Host smart-5bb1f968-b094-4739-9832-7ed86144c449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258315822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1258315822
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.682409293
Short name T603
Test name
Test status
Simulation time 111298204 ps
CPU time 0.91 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 201316 kb
Host smart-f8ec158f-253e-4395-9963-30c2946ed9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682409293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.682409293
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1823556928
Short name T535
Test name
Test status
Simulation time 129515827 ps
CPU time 0.7 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 198088 kb
Host smart-2b9090ec-fcc5-4082-b2d9-4055f71698d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823556928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1823556928
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1982510680
Short name T267
Test name
Test status
Simulation time 29233442 ps
CPU time 0.7 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 199448 kb
Host smart-098c6ba3-5702-49f0-b3ca-da82c31fb9b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982510680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1982510680
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3222132561
Short name T100
Test name
Test status
Simulation time 36033900 ps
CPU time 0.78 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 198828 kb
Host smart-79a23019-0bd9-4e14-8a49-2a61bf655a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222132561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3222132561
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2782480238
Short name T140
Test name
Test status
Simulation time 71658773 ps
CPU time 0.69 seconds
Started Jul 27 06:17:38 PM PDT 24
Finished Jul 27 06:17:38 PM PDT 24
Peak memory 198316 kb
Host smart-24351980-8249-4458-92dd-0a214883c4a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782480238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2782480238
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.520586891
Short name T540
Test name
Test status
Simulation time 43439025 ps
CPU time 0.61 seconds
Started Jul 27 06:17:29 PM PDT 24
Finished Jul 27 06:17:30 PM PDT 24
Peak memory 197364 kb
Host smart-f4a04db2-de9e-4042-86e1-600d35495235
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520586891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.520586891
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2179027552
Short name T36
Test name
Test status
Simulation time 662301348 ps
CPU time 0.99 seconds
Started Jul 27 06:17:39 PM PDT 24
Finished Jul 27 06:17:40 PM PDT 24
Peak memory 198180 kb
Host smart-149cd1ea-8a1d-41f3-a482-6bed87903070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179027552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2179027552
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1110854896
Short name T291
Test name
Test status
Simulation time 45679229 ps
CPU time 0.66 seconds
Started Jul 27 06:17:38 PM PDT 24
Finished Jul 27 06:17:39 PM PDT 24
Peak memory 198172 kb
Host smart-3fb482e7-0834-44f6-a77a-a880fe42146d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110854896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1110854896
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.4147492226
Short name T231
Test name
Test status
Simulation time 59918699 ps
CPU time 0.6 seconds
Started Jul 27 06:17:38 PM PDT 24
Finished Jul 27 06:17:39 PM PDT 24
Peak memory 198132 kb
Host smart-f4c2593d-3a76-4d5d-a76b-7cd59ed516cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147492226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.4147492226
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.682094401
Short name T186
Test name
Test status
Simulation time 50291545 ps
CPU time 0.7 seconds
Started Jul 27 06:17:38 PM PDT 24
Finished Jul 27 06:17:39 PM PDT 24
Peak memory 201468 kb
Host smart-eb06dbf3-0d04-4cf6-8930-2fabaa0a213e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682094401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.682094401
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1745272041
Short name T245
Test name
Test status
Simulation time 122786120 ps
CPU time 0.74 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 198456 kb
Host smart-b217d944-15ca-45c9-acf7-127eadaf8e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745272041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1745272041
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.2586009435
Short name T365
Test name
Test status
Simulation time 100180137 ps
CPU time 0.94 seconds
Started Jul 27 06:17:39 PM PDT 24
Finished Jul 27 06:17:40 PM PDT 24
Peak memory 209500 kb
Host smart-f4365dbc-fee7-41df-adb9-8fe1c17372d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586009435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2586009435
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.4055760813
Short name T396
Test name
Test status
Simulation time 53722240 ps
CPU time 0.79 seconds
Started Jul 27 06:17:30 PM PDT 24
Finished Jul 27 06:17:31 PM PDT 24
Peak memory 198256 kb
Host smart-6b0a5331-6ed3-49a2-a946-0f3b7785523c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055760813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4055760813
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1636073257
Short name T333
Test name
Test status
Simulation time 60530901 ps
CPU time 0.64 seconds
Started Jul 27 06:17:27 PM PDT 24
Finished Jul 27 06:17:28 PM PDT 24
Peak memory 198584 kb
Host smart-5c37cab8-0270-45a9-b45b-c8b99e3d0cad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636073257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1636073257
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.965072154
Short name T394
Test name
Test status
Simulation time 82949395 ps
CPU time 0.9 seconds
Started Jul 27 06:17:38 PM PDT 24
Finished Jul 27 06:17:39 PM PDT 24
Peak memory 200284 kb
Host smart-823df70a-4f3b-4af7-8152-30f82ac9be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965072154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.965072154
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1759482227
Short name T159
Test name
Test status
Simulation time 88800293 ps
CPU time 0.67 seconds
Started Jul 27 06:17:50 PM PDT 24
Finished Jul 27 06:17:51 PM PDT 24
Peak memory 198564 kb
Host smart-43ded139-21e9-4229-9c48-2b909fdc29eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759482227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1759482227
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3707075407
Short name T337
Test name
Test status
Simulation time 31062797 ps
CPU time 0.65 seconds
Started Jul 27 06:17:40 PM PDT 24
Finished Jul 27 06:17:41 PM PDT 24
Peak memory 198080 kb
Host smart-a53092e8-b08d-4792-9b40-a3d34dee5271
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707075407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3707075407
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.43930350
Short name T270
Test name
Test status
Simulation time 1263409295 ps
CPU time 0.95 seconds
Started Jul 27 06:17:40 PM PDT 24
Finished Jul 27 06:17:41 PM PDT 24
Peak memory 198136 kb
Host smart-ceeea10f-11b1-465d-af64-01f410bcf313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43930350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.43930350
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3400654042
Short name T434
Test name
Test status
Simulation time 95591697 ps
CPU time 0.63 seconds
Started Jul 27 06:17:49 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 197424 kb
Host smart-e3e39e6d-30ad-43dd-bebf-8d48d39e1a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400654042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3400654042
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3651780814
Short name T39
Test name
Test status
Simulation time 47932584 ps
CPU time 0.61 seconds
Started Jul 27 06:17:40 PM PDT 24
Finished Jul 27 06:17:41 PM PDT 24
Peak memory 198496 kb
Host smart-79905ecf-d6f5-4e94-9bbd-e8e7c2a3ebe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651780814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3651780814
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3530246949
Short name T174
Test name
Test status
Simulation time 44764465 ps
CPU time 0.75 seconds
Started Jul 27 06:17:49 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 201468 kb
Host smart-83708d92-9181-4f70-8afb-47442198d3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530246949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3530246949
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1408418927
Short name T347
Test name
Test status
Simulation time 96623963 ps
CPU time 0.8 seconds
Started Jul 27 06:17:39 PM PDT 24
Finished Jul 27 06:17:40 PM PDT 24
Peak memory 199128 kb
Host smart-0975a4d7-b17c-494b-8253-28ac2f306e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408418927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1408418927
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3716758415
Short name T323
Test name
Test status
Simulation time 90960046 ps
CPU time 0.93 seconds
Started Jul 27 06:17:55 PM PDT 24
Finished Jul 27 06:17:56 PM PDT 24
Peak memory 209520 kb
Host smart-dcee9814-a53a-4426-b8e4-a167ffc9cf4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716758415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3716758415
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1013627380
Short name T516
Test name
Test status
Simulation time 54000084 ps
CPU time 0.9 seconds
Started Jul 27 06:17:39 PM PDT 24
Finished Jul 27 06:17:40 PM PDT 24
Peak memory 199264 kb
Host smart-78077584-aba8-4b9a-969f-3e3110111803
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013627380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1013627380
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.1621487897
Short name T316
Test name
Test status
Simulation time 28568658 ps
CPU time 0.66 seconds
Started Jul 27 06:17:40 PM PDT 24
Finished Jul 27 06:17:41 PM PDT 24
Peak memory 199380 kb
Host smart-f37bdb28-1147-4ced-81c9-511bc0d10e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621487897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.1621487897
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.2109250886
Short name T461
Test name
Test status
Simulation time 32830539 ps
CPU time 1.05 seconds
Started Jul 27 06:17:51 PM PDT 24
Finished Jul 27 06:17:52 PM PDT 24
Peak memory 200904 kb
Host smart-56142bd6-a332-49a0-84bc-2dcbde78c4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109250886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2109250886
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3547481542
Short name T488
Test name
Test status
Simulation time 55840250 ps
CPU time 0.57 seconds
Started Jul 27 06:17:52 PM PDT 24
Finished Jul 27 06:17:52 PM PDT 24
Peak memory 198040 kb
Host smart-6848f9c2-8b57-460a-999b-a977019fe696
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547481542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.3547481542
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.3265380644
Short name T255
Test name
Test status
Simulation time 160624947 ps
CPU time 0.98 seconds
Started Jul 27 06:17:52 PM PDT 24
Finished Jul 27 06:17:53 PM PDT 24
Peak memory 198140 kb
Host smart-34f31a5f-8be4-4944-ae44-ca9e5caa0da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265380644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3265380644
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3399781640
Short name T609
Test name
Test status
Simulation time 97451534 ps
CPU time 0.62 seconds
Started Jul 27 06:17:50 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 198088 kb
Host smart-e8cb36f4-a4e1-49e6-a7ab-efa4a7a3b3f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399781640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3399781640
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.682995843
Short name T287
Test name
Test status
Simulation time 47595479 ps
CPU time 0.66 seconds
Started Jul 27 06:17:49 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 198152 kb
Host smart-1392fcc8-db53-45a9-943d-ff1bb70aa075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682995843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.682995843
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3367713695
Short name T201
Test name
Test status
Simulation time 80293366 ps
CPU time 0.66 seconds
Started Jul 27 06:17:52 PM PDT 24
Finished Jul 27 06:17:53 PM PDT 24
Peak memory 201432 kb
Host smart-a21b8c93-27f7-4a50-8414-697979dc4f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367713695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3367713695
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1800218942
Short name T285
Test name
Test status
Simulation time 31651956 ps
CPU time 0.63 seconds
Started Jul 27 06:17:50 PM PDT 24
Finished Jul 27 06:17:51 PM PDT 24
Peak memory 198252 kb
Host smart-d057efcc-830d-4738-9cb8-eabad9b6a011
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800218942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1800218942
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1512544832
Short name T339
Test name
Test status
Simulation time 165495104 ps
CPU time 0.79 seconds
Started Jul 27 06:17:51 PM PDT 24
Finished Jul 27 06:17:52 PM PDT 24
Peak memory 209492 kb
Host smart-5dcb896d-536a-4e84-b412-762d085c47aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512544832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1512544832
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.499407042
Short name T478
Test name
Test status
Simulation time 89213617 ps
CPU time 0.81 seconds
Started Jul 27 06:17:50 PM PDT 24
Finished Jul 27 06:17:51 PM PDT 24
Peak memory 199284 kb
Host smart-3ec67f7d-1fce-4347-8895-34d3f48592ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499407042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.499407042
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1287791014
Short name T373
Test name
Test status
Simulation time 31958387 ps
CPU time 0.7 seconds
Started Jul 27 06:17:50 PM PDT 24
Finished Jul 27 06:17:51 PM PDT 24
Peak memory 199388 kb
Host smart-b9256c22-6e14-4222-acf0-c041d4a19279
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287791014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1287791014
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.523916662
Short name T579
Test name
Test status
Simulation time 45292641 ps
CPU time 0.89 seconds
Started Jul 27 06:17:54 PM PDT 24
Finished Jul 27 06:17:55 PM PDT 24
Peak memory 200748 kb
Host smart-0fab562d-ca1b-4767-91ca-a19cc6d07f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523916662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.523916662
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3743037331
Short name T72
Test name
Test status
Simulation time 67332054 ps
CPU time 0.73 seconds
Started Jul 27 06:18:04 PM PDT 24
Finished Jul 27 06:18:05 PM PDT 24
Peak memory 199144 kb
Host smart-ffbcf571-7bf8-45b7-b224-049070226fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743037331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3743037331
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.373807545
Short name T312
Test name
Test status
Simulation time 30481564 ps
CPU time 0.6 seconds
Started Jul 27 06:17:49 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 197988 kb
Host smart-37ac0c12-fe5e-4a59-9f55-7ca427f545f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373807545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_
malfunc.373807545
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3317169982
Short name T133
Test name
Test status
Simulation time 307415490 ps
CPU time 0.94 seconds
Started Jul 27 06:17:57 PM PDT 24
Finished Jul 27 06:17:58 PM PDT 24
Peak memory 198548 kb
Host smart-8150e690-4b09-4173-9efb-f6ce19ab080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317169982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3317169982
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.629844313
Short name T399
Test name
Test status
Simulation time 45467219 ps
CPU time 0.62 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:06 PM PDT 24
Peak memory 198160 kb
Host smart-e683a10e-c0ee-4442-97cc-d3bf998b11a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629844313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.629844313
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3312250380
Short name T517
Test name
Test status
Simulation time 83543671 ps
CPU time 0.63 seconds
Started Jul 27 06:18:01 PM PDT 24
Finished Jul 27 06:18:02 PM PDT 24
Peak memory 198536 kb
Host smart-2a5ec4bb-3007-4911-bedf-5151ac6aa3aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312250380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3312250380
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.1705820439
Short name T400
Test name
Test status
Simulation time 49660939 ps
CPU time 0.7 seconds
Started Jul 27 06:17:58 PM PDT 24
Finished Jul 27 06:17:59 PM PDT 24
Peak memory 201384 kb
Host smart-bfb129b2-6e12-41da-b268-bfddfed59a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705820439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.1705820439
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.516879393
Short name T562
Test name
Test status
Simulation time 269792988 ps
CPU time 0.78 seconds
Started Jul 27 06:17:49 PM PDT 24
Finished Jul 27 06:17:50 PM PDT 24
Peak memory 198564 kb
Host smart-4d247bab-842c-46da-a423-9e70ecbbf38b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516879393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.516879393
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.4216368035
Short name T506
Test name
Test status
Simulation time 112063650 ps
CPU time 0.97 seconds
Started Jul 27 06:18:01 PM PDT 24
Finished Jul 27 06:18:02 PM PDT 24
Peak memory 209500 kb
Host smart-6bdeedb8-1750-4421-b872-6f322a4a9c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216368035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.4216368035
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.921989429
Short name T587
Test name
Test status
Simulation time 273414296 ps
CPU time 0.68 seconds
Started Jul 27 06:17:51 PM PDT 24
Finished Jul 27 06:17:52 PM PDT 24
Peak memory 198296 kb
Host smart-32e7981b-5dad-404f-98fa-5abe526549f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921989429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.921989429
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3205047807
Short name T89
Test name
Test status
Simulation time 76406077 ps
CPU time 0.65 seconds
Started Jul 27 06:17:54 PM PDT 24
Finished Jul 27 06:17:55 PM PDT 24
Peak memory 198512 kb
Host smart-d6f7046c-7d16-412a-a380-adaa555f7780
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205047807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3205047807
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3832524002
Short name T511
Test name
Test status
Simulation time 44376059 ps
CPU time 0.91 seconds
Started Jul 27 06:18:04 PM PDT 24
Finished Jul 27 06:18:05 PM PDT 24
Peak memory 200784 kb
Host smart-45bb4c61-37e7-43a2-98a0-f18b30fad499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832524002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3832524002
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1992167464
Short name T343
Test name
Test status
Simulation time 59872504 ps
CPU time 0.72 seconds
Started Jul 27 06:17:58 PM PDT 24
Finished Jul 27 06:17:58 PM PDT 24
Peak memory 199172 kb
Host smart-b8a906ad-c336-4d1b-8347-64b43ffc7d43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992167464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.1992167464
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.1288876068
Short name T376
Test name
Test status
Simulation time 35101249 ps
CPU time 0.64 seconds
Started Jul 27 06:18:01 PM PDT 24
Finished Jul 27 06:18:02 PM PDT 24
Peak memory 198064 kb
Host smart-cbed68e9-4f15-4056-8493-43e395522506
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288876068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.1288876068
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2344236346
Short name T261
Test name
Test status
Simulation time 163479725 ps
CPU time 1.07 seconds
Started Jul 27 06:18:02 PM PDT 24
Finished Jul 27 06:18:04 PM PDT 24
Peak memory 198472 kb
Host smart-563d4ff1-9b3c-447e-a007-502cca521bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344236346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2344236346
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3237730264
Short name T555
Test name
Test status
Simulation time 50830037 ps
CPU time 0.63 seconds
Started Jul 27 06:17:57 PM PDT 24
Finished Jul 27 06:17:57 PM PDT 24
Peak memory 198084 kb
Host smart-eedef9d7-dfdf-4e3e-a93a-dd99bca55738
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237730264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3237730264
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1536505574
Short name T574
Test name
Test status
Simulation time 42344481 ps
CPU time 0.67 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 198152 kb
Host smart-f4deb298-550f-4932-83e7-08b4d00530c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536505574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1536505574
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3192968425
Short name T88
Test name
Test status
Simulation time 55296038 ps
CPU time 0.69 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 201424 kb
Host smart-f6c3e33e-f353-492a-9f2d-b4a625d70645
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192968425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3192968425
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1869647199
Short name T581
Test name
Test status
Simulation time 86070033 ps
CPU time 0.88 seconds
Started Jul 27 06:18:02 PM PDT 24
Finished Jul 27 06:18:03 PM PDT 24
Peak memory 198488 kb
Host smart-6c6d8dcc-7a93-4c02-a579-3a5d094beb58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869647199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1869647199
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2217446784
Short name T283
Test name
Test status
Simulation time 162202634 ps
CPU time 0.79 seconds
Started Jul 27 06:17:58 PM PDT 24
Finished Jul 27 06:17:59 PM PDT 24
Peak memory 209508 kb
Host smart-fefeeac3-6280-4ff4-a054-4e756d4b2bf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217446784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2217446784
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3031255931
Short name T146
Test name
Test status
Simulation time 50353901 ps
CPU time 0.81 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 199212 kb
Host smart-1ccd6b16-a85d-4f52-810d-1cf8fdfa9f15
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031255931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.3031255931
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.701218060
Short name T360
Test name
Test status
Simulation time 56237691 ps
CPU time 0.81 seconds
Started Jul 27 06:17:57 PM PDT 24
Finished Jul 27 06:17:58 PM PDT 24
Peak memory 198164 kb
Host smart-b7fc26bc-7e26-41fb-8089-d149b362e764
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701218060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.701218060
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.823665085
Short name T24
Test name
Test status
Simulation time 61742537 ps
CPU time 0.68 seconds
Started Jul 27 06:18:01 PM PDT 24
Finished Jul 27 06:18:02 PM PDT 24
Peak memory 199428 kb
Host smart-71193bdc-2029-4091-b442-6731312ecf35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823665085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.823665085
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.948772891
Short name T539
Test name
Test status
Simulation time 33892232 ps
CPU time 1.04 seconds
Started Jul 27 06:13:07 PM PDT 24
Finished Jul 27 06:13:09 PM PDT 24
Peak memory 200980 kb
Host smart-3c7b00c1-fca0-4ad9-a233-07b0be77a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948772891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.948772891
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1006982760
Short name T168
Test name
Test status
Simulation time 62640824 ps
CPU time 0.69 seconds
Started Jul 27 06:13:15 PM PDT 24
Finished Jul 27 06:13:16 PM PDT 24
Peak memory 198368 kb
Host smart-d2b2eed1-1ee6-4fcf-ad75-2f2b08c26521
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006982760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1006982760
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3427969029
Short name T368
Test name
Test status
Simulation time 39020113 ps
CPU time 0.59 seconds
Started Jul 27 06:13:17 PM PDT 24
Finished Jul 27 06:13:18 PM PDT 24
Peak memory 198056 kb
Host smart-59e5192e-1114-4132-829a-feeda23a516f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427969029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3427969029
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.3016860499
Short name T273
Test name
Test status
Simulation time 368307281 ps
CPU time 1.01 seconds
Started Jul 27 06:13:16 PM PDT 24
Finished Jul 27 06:13:18 PM PDT 24
Peak memory 198180 kb
Host smart-7c36a0eb-9f2e-4733-8567-f5a4d0b74f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016860499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3016860499
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3315280796
Short name T389
Test name
Test status
Simulation time 45478922 ps
CPU time 0.68 seconds
Started Jul 27 06:13:15 PM PDT 24
Finished Jul 27 06:13:15 PM PDT 24
Peak memory 198164 kb
Host smart-ab732509-0862-4be4-990c-cca9fb797c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315280796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3315280796
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2829522883
Short name T292
Test name
Test status
Simulation time 35611639 ps
CPU time 0.64 seconds
Started Jul 27 06:13:18 PM PDT 24
Finished Jul 27 06:13:19 PM PDT 24
Peak memory 198460 kb
Host smart-2b0c07aa-a082-4d82-8db2-d1738f74ae8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829522883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2829522883
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.2370970667
Short name T70
Test name
Test status
Simulation time 44296631 ps
CPU time 0.76 seconds
Started Jul 27 06:13:08 PM PDT 24
Finished Jul 27 06:13:09 PM PDT 24
Peak memory 198444 kb
Host smart-9180cb4c-45d4-4b26-8bc4-7b8e3069a5f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370970667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.2370970667
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2747625863
Short name T342
Test name
Test status
Simulation time 95086132 ps
CPU time 1.12 seconds
Started Jul 27 06:13:22 PM PDT 24
Finished Jul 27 06:13:24 PM PDT 24
Peak memory 209604 kb
Host smart-5c938ccb-a2f1-42f1-a1c8-1ac88b094ea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747625863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2747625863
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.4134826863
Short name T21
Test name
Test status
Simulation time 326828911 ps
CPU time 1.38 seconds
Started Jul 27 06:13:23 PM PDT 24
Finished Jul 27 06:13:25 PM PDT 24
Peak memory 217692 kb
Host smart-c2f05c79-3709-4b99-b2e3-4f6ac569d7c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134826863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.4134826863
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1132539646
Short name T410
Test name
Test status
Simulation time 203868282 ps
CPU time 0.73 seconds
Started Jul 27 06:13:15 PM PDT 24
Finished Jul 27 06:13:16 PM PDT 24
Peak memory 199516 kb
Host smart-b527750e-c124-4818-a03b-4f97a2a47ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132539646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1132539646
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.271827936
Short name T354
Test name
Test status
Simulation time 32448788 ps
CPU time 0.65 seconds
Started Jul 27 06:13:08 PM PDT 24
Finished Jul 27 06:13:09 PM PDT 24
Peak memory 198648 kb
Host smart-42a60516-e470-4373-9176-8c191d02e8dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271827936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.271827936
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.590205195
Short name T531
Test name
Test status
Simulation time 28996228 ps
CPU time 0.9 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:11 PM PDT 24
Peak memory 200080 kb
Host smart-e4e65e36-4535-46e0-90e6-c17000a95b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590205195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.590205195
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3564951040
Short name T137
Test name
Test status
Simulation time 52053874 ps
CPU time 0.81 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:11 PM PDT 24
Peak memory 198652 kb
Host smart-786be558-a201-4d19-b35c-c7a9a7229482
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564951040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3564951040
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.4172710075
Short name T490
Test name
Test status
Simulation time 31136415 ps
CPU time 0.62 seconds
Started Jul 27 06:18:08 PM PDT 24
Finished Jul 27 06:18:09 PM PDT 24
Peak memory 197364 kb
Host smart-0ab3d43f-ea26-418c-8c9c-24309fca9970
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172710075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.4172710075
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.1212932470
Short name T242
Test name
Test status
Simulation time 163908478 ps
CPU time 0.94 seconds
Started Jul 27 06:18:08 PM PDT 24
Finished Jul 27 06:18:09 PM PDT 24
Peak memory 198152 kb
Host smart-9971dc0a-07b1-43cc-8b33-8e3d656bca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212932470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1212932470
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2142800898
Short name T617
Test name
Test status
Simulation time 33182374 ps
CPU time 0.62 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 198172 kb
Host smart-d42c47d3-6a06-4da7-ac74-486368c34bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142800898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2142800898
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.176709754
Short name T243
Test name
Test status
Simulation time 87341181 ps
CPU time 0.58 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 198128 kb
Host smart-afa2dd9f-8e50-42e4-8bf0-5daebcf5d697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176709754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.176709754
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.466930313
Short name T227
Test name
Test status
Simulation time 59412581 ps
CPU time 0.77 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 198388 kb
Host smart-2a607790-862e-4a64-bc27-8cc3f524709b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466930313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.466930313
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1005749062
Short name T221
Test name
Test status
Simulation time 96312315 ps
CPU time 0.91 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 209584 kb
Host smart-af6992a2-4c9b-4a92-8f09-54dea97d195e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005749062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1005749062
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1222818689
Short name T508
Test name
Test status
Simulation time 174279332 ps
CPU time 0.75 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 199576 kb
Host smart-cfe0d4be-312a-48dc-9017-9c505219abee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222818689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1222818689
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.380396103
Short name T496
Test name
Test status
Simulation time 31006102 ps
CPU time 0.66 seconds
Started Jul 27 06:17:57 PM PDT 24
Finished Jul 27 06:17:58 PM PDT 24
Peak memory 199612 kb
Host smart-fc2220c5-1f6f-4fa5-aaff-b92610a94310
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380396103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.380396103
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.845704875
Short name T619
Test name
Test status
Simulation time 34771886 ps
CPU time 1.11 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 200976 kb
Host smart-8eddd9e5-63f9-4917-99fa-a7caa6872c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845704875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.845704875
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2438543410
Short name T469
Test name
Test status
Simulation time 66062998 ps
CPU time 0.77 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:11 PM PDT 24
Peak memory 198580 kb
Host smart-9f3bf7bc-f3bc-4ef2-aa84-82edaf86b761
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438543410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2438543410
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.185620574
Short name T618
Test name
Test status
Simulation time 35351770 ps
CPU time 0.6 seconds
Started Jul 27 06:18:08 PM PDT 24
Finished Jul 27 06:18:09 PM PDT 24
Peak memory 198080 kb
Host smart-ecefd19a-e270-44a8-b5cc-c2295ad52d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185620574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_
malfunc.185620574
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1351032308
Short name T131
Test name
Test status
Simulation time 625722329 ps
CPU time 0.99 seconds
Started Jul 27 06:18:11 PM PDT 24
Finished Jul 27 06:18:12 PM PDT 24
Peak memory 198168 kb
Host smart-bb19793c-9b13-4ac7-9b74-f47f671dbe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351032308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1351032308
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3486619305
Short name T600
Test name
Test status
Simulation time 33366448 ps
CPU time 0.68 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:11 PM PDT 24
Peak memory 198128 kb
Host smart-ec8249b8-c9c2-45e2-b09f-30bacec8b0d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486619305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3486619305
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.3571130314
Short name T240
Test name
Test status
Simulation time 42720908 ps
CPU time 0.65 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:11 PM PDT 24
Peak memory 198148 kb
Host smart-2ebc8d1b-4327-4e4d-92d9-b2161d97bd7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571130314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3571130314
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2489493902
Short name T173
Test name
Test status
Simulation time 80842657 ps
CPU time 0.65 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 201428 kb
Host smart-7c0d9dda-b124-4a2b-a42e-abe15c7140ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489493902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2489493902
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2790865960
Short name T322
Test name
Test status
Simulation time 95323202 ps
CPU time 0.66 seconds
Started Jul 27 06:18:08 PM PDT 24
Finished Jul 27 06:18:09 PM PDT 24
Peak memory 198436 kb
Host smart-c42725e9-467f-4b60-a4a7-2278c0b192b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790865960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2790865960
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1225533971
Short name T412
Test name
Test status
Simulation time 101928394 ps
CPU time 1.03 seconds
Started Jul 27 06:18:06 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 209444 kb
Host smart-60f4b032-4ccc-4d67-bac6-b5fcd33c641b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225533971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1225533971
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2555195282
Short name T415
Test name
Test status
Simulation time 73331019 ps
CPU time 0.93 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 199436 kb
Host smart-5ff80ea3-a1d1-4bc6-95bd-6bdb5eac41df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555195282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2555195282
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.2426702100
Short name T330
Test name
Test status
Simulation time 56375552 ps
CPU time 0.64 seconds
Started Jul 27 06:18:16 PM PDT 24
Finished Jul 27 06:18:17 PM PDT 24
Peak memory 198580 kb
Host smart-dd4e160d-7fdf-40a3-a1a4-22b775986434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426702100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2426702100
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.4212684550
Short name T543
Test name
Test status
Simulation time 54557875 ps
CPU time 0.72 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 198668 kb
Host smart-266065aa-9227-4e78-bfe6-11ad53c05767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212684550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.4212684550
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2660737363
Short name T483
Test name
Test status
Simulation time 92544008 ps
CPU time 0.66 seconds
Started Jul 27 06:18:17 PM PDT 24
Finished Jul 27 06:18:18 PM PDT 24
Peak memory 198540 kb
Host smart-91f2dabd-7f00-4fff-8ffd-f596a00db22c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660737363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2660737363
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3053054642
Short name T384
Test name
Test status
Simulation time 40378929 ps
CPU time 0.61 seconds
Started Jul 27 06:18:16 PM PDT 24
Finished Jul 27 06:18:16 PM PDT 24
Peak memory 198080 kb
Host smart-7c49b81d-ee9b-4990-8ad6-a7bfc0bee427
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053054642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3053054642
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1529205808
Short name T299
Test name
Test status
Simulation time 305775536 ps
CPU time 0.93 seconds
Started Jul 27 06:18:18 PM PDT 24
Finished Jul 27 06:18:19 PM PDT 24
Peak memory 198160 kb
Host smart-7ec6acad-433c-4ffd-b976-015bd5e87973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529205808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1529205808
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.3421082158
Short name T40
Test name
Test status
Simulation time 39014877 ps
CPU time 0.63 seconds
Started Jul 27 06:18:16 PM PDT 24
Finished Jul 27 06:18:17 PM PDT 24
Peak memory 198056 kb
Host smart-287f753f-2ee8-4192-ac9e-28b99f75974e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421082158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3421082158
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.3643556618
Short name T395
Test name
Test status
Simulation time 81095517 ps
CPU time 0.61 seconds
Started Jul 27 06:18:07 PM PDT 24
Finished Jul 27 06:18:08 PM PDT 24
Peak memory 198456 kb
Host smart-46139b73-55ed-437d-ab51-c351c153030f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643556618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3643556618
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3816739334
Short name T583
Test name
Test status
Simulation time 48728352 ps
CPU time 0.72 seconds
Started Jul 27 06:18:17 PM PDT 24
Finished Jul 27 06:18:18 PM PDT 24
Peak memory 201448 kb
Host smart-5e84f977-7d2a-40c9-8fd5-71e4a210eba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816739334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3816739334
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.1235295980
Short name T489
Test name
Test status
Simulation time 92892026 ps
CPU time 0.73 seconds
Started Jul 27 06:18:10 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 199124 kb
Host smart-43b17617-3a5e-4c07-8258-6f72695c044e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235295980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1235295980
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2843388541
Short name T1
Test name
Test status
Simulation time 162549727 ps
CPU time 0.71 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 198236 kb
Host smart-4b8fe30a-c4f0-4dde-a67d-f33c6b4a2325
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843388541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2843388541
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.165836245
Short name T515
Test name
Test status
Simulation time 66865908 ps
CPU time 0.66 seconds
Started Jul 27 06:18:09 PM PDT 24
Finished Jul 27 06:18:10 PM PDT 24
Peak memory 198584 kb
Host smart-44911fca-d5dd-4bfa-8732-e00144f7438a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165836245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.165836245
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3068798189
Short name T30
Test name
Test status
Simulation time 62654383 ps
CPU time 0.73 seconds
Started Jul 27 06:18:19 PM PDT 24
Finished Jul 27 06:18:20 PM PDT 24
Peak memory 199224 kb
Host smart-742411ff-a90e-4570-b12b-ec59501d8518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068798189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3068798189
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.4264509993
Short name T32
Test name
Test status
Simulation time 65592534 ps
CPU time 0.72 seconds
Started Jul 27 06:18:19 PM PDT 24
Finished Jul 27 06:18:19 PM PDT 24
Peak memory 199184 kb
Host smart-5b50ef30-22ce-4747-a515-6ad7b9dc1329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264509993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.4264509993
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3635271460
Short name T268
Test name
Test status
Simulation time 39246478 ps
CPU time 0.59 seconds
Started Jul 27 06:18:19 PM PDT 24
Finished Jul 27 06:18:20 PM PDT 24
Peak memory 198132 kb
Host smart-0f6a415a-fa4b-402c-8367-d25e34776049
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635271460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3635271460
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.2647785685
Short name T393
Test name
Test status
Simulation time 408917650 ps
CPU time 0.94 seconds
Started Jul 27 06:18:19 PM PDT 24
Finished Jul 27 06:18:20 PM PDT 24
Peak memory 198456 kb
Host smart-cda00bbb-4f5a-4a83-aaf8-164e38f218f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647785685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2647785685
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2978992927
Short name T20
Test name
Test status
Simulation time 37410850 ps
CPU time 0.62 seconds
Started Jul 27 06:18:15 PM PDT 24
Finished Jul 27 06:18:16 PM PDT 24
Peak memory 198120 kb
Host smart-3020dc82-4ff1-4bfe-9781-a4a50b8cc689
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978992927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2978992927
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.1626109585
Short name T294
Test name
Test status
Simulation time 27544815 ps
CPU time 0.61 seconds
Started Jul 27 06:18:19 PM PDT 24
Finished Jul 27 06:18:20 PM PDT 24
Peak memory 198116 kb
Host smart-2855a349-c08f-493f-9cef-7ca8f0ca017d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626109585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1626109585
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.4127446159
Short name T533
Test name
Test status
Simulation time 60863915 ps
CPU time 0.69 seconds
Started Jul 27 06:18:27 PM PDT 24
Finished Jul 27 06:18:28 PM PDT 24
Peak memory 201428 kb
Host smart-8938f451-9465-4319-875f-acfd6296118c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127446159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.4127446159
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.3876122055
Short name T464
Test name
Test status
Simulation time 36584499 ps
CPU time 0.67 seconds
Started Jul 27 06:18:18 PM PDT 24
Finished Jul 27 06:18:19 PM PDT 24
Peak memory 199128 kb
Host smart-20cfdf01-78e2-4ae2-bfef-879bc409ed8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876122055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3876122055
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2349224396
Short name T441
Test name
Test status
Simulation time 95885196 ps
CPU time 1.03 seconds
Started Jul 27 06:18:18 PM PDT 24
Finished Jul 27 06:18:19 PM PDT 24
Peak memory 209580 kb
Host smart-b6fad49b-c0b1-4e0c-87b6-6db00af6ddde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349224396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2349224396
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.746625691
Short name T123
Test name
Test status
Simulation time 240286173 ps
CPU time 0.82 seconds
Started Jul 27 06:18:16 PM PDT 24
Finished Jul 27 06:18:17 PM PDT 24
Peak memory 198312 kb
Host smart-066b8fed-c55d-408d-9108-880a511b0e01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746625691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_
mubi.746625691
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1838598490
Short name T444
Test name
Test status
Simulation time 29801091 ps
CPU time 0.66 seconds
Started Jul 27 06:18:17 PM PDT 24
Finished Jul 27 06:18:18 PM PDT 24
Peak memory 198568 kb
Host smart-80cec8fc-927c-4cd6-93fe-9afefa888047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838598490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1838598490
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.4146394024
Short name T406
Test name
Test status
Simulation time 35398969 ps
CPU time 1.12 seconds
Started Jul 27 06:18:26 PM PDT 24
Finished Jul 27 06:18:27 PM PDT 24
Peak memory 200992 kb
Host smart-a52a63ba-909b-4ffb-a30a-df044d6b4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146394024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4146394024
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3696898914
Short name T157
Test name
Test status
Simulation time 58538649 ps
CPU time 0.76 seconds
Started Jul 27 06:18:27 PM PDT 24
Finished Jul 27 06:18:28 PM PDT 24
Peak memory 199248 kb
Host smart-08b73dfa-cbdd-4cd6-a03c-89ccec8368eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696898914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3696898914
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3380952656
Short name T278
Test name
Test status
Simulation time 32517068 ps
CPU time 0.61 seconds
Started Jul 27 06:18:25 PM PDT 24
Finished Jul 27 06:18:26 PM PDT 24
Peak memory 198064 kb
Host smart-2e3ac79e-60be-4f4d-b748-185b69630ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380952656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.3380952656
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.980241318
Short name T276
Test name
Test status
Simulation time 158916194 ps
CPU time 0.99 seconds
Started Jul 27 06:18:26 PM PDT 24
Finished Jul 27 06:18:27 PM PDT 24
Peak memory 198164 kb
Host smart-31617dc4-8994-48fc-896e-09e1baaeec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980241318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.980241318
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1313089634
Short name T442
Test name
Test status
Simulation time 33575157 ps
CPU time 0.61 seconds
Started Jul 27 06:18:26 PM PDT 24
Finished Jul 27 06:18:26 PM PDT 24
Peak memory 198096 kb
Host smart-36ffde94-a14b-4ddd-a7eb-3034d9393e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313089634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1313089634
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2700574111
Short name T246
Test name
Test status
Simulation time 64891876 ps
CPU time 0.62 seconds
Started Jul 27 06:18:27 PM PDT 24
Finished Jul 27 06:18:27 PM PDT 24
Peak memory 198464 kb
Host smart-18448c7f-e3ef-4fc7-9991-f7d4a0d036c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700574111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2700574111
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.4153643326
Short name T48
Test name
Test status
Simulation time 69474497 ps
CPU time 0.69 seconds
Started Jul 27 06:18:37 PM PDT 24
Finished Jul 27 06:18:38 PM PDT 24
Peak memory 201416 kb
Host smart-3fa331ad-1ba4-42b6-8bf6-05354c32d6e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153643326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.4153643326
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3737567314
Short name T576
Test name
Test status
Simulation time 131361567 ps
CPU time 0.79 seconds
Started Jul 27 06:18:26 PM PDT 24
Finished Jul 27 06:18:27 PM PDT 24
Peak memory 198536 kb
Host smart-f3e7202f-9816-4e78-a31e-ac3ad900c1c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737567314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3737567314
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3493174433
Short name T620
Test name
Test status
Simulation time 197294871 ps
CPU time 0.81 seconds
Started Jul 27 06:18:29 PM PDT 24
Finished Jul 27 06:18:30 PM PDT 24
Peak memory 209492 kb
Host smart-976b1761-6a16-43fa-b669-5e97f324c22c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493174433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3493174433
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3392079295
Short name T522
Test name
Test status
Simulation time 64561697 ps
CPU time 0.84 seconds
Started Jul 27 06:18:25 PM PDT 24
Finished Jul 27 06:18:26 PM PDT 24
Peak memory 198204 kb
Host smart-bd28755f-14e3-4c1a-8860-ca49cf01193d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392079295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3392079295
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1092953283
Short name T90
Test name
Test status
Simulation time 28729996 ps
CPU time 0.73 seconds
Started Jul 27 06:18:26 PM PDT 24
Finished Jul 27 06:18:27 PM PDT 24
Peak memory 199480 kb
Host smart-c6c2f4bc-1222-4c91-a596-819efc84ba95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092953283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1092953283
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.1242958494
Short name T528
Test name
Test status
Simulation time 119764116 ps
CPU time 0.76 seconds
Started Jul 27 06:18:35 PM PDT 24
Finished Jul 27 06:18:35 PM PDT 24
Peak memory 198892 kb
Host smart-43b3583f-50af-405b-a592-2aeea226bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242958494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.1242958494
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3621604850
Short name T534
Test name
Test status
Simulation time 59846085 ps
CPU time 0.74 seconds
Started Jul 27 06:18:36 PM PDT 24
Finished Jul 27 06:18:37 PM PDT 24
Peak memory 199176 kb
Host smart-4be1162c-d1a7-412b-9b80-e07b9442e050
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621604850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3621604850
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2799352077
Short name T274
Test name
Test status
Simulation time 126298956 ps
CPU time 0.59 seconds
Started Jul 27 06:18:36 PM PDT 24
Finished Jul 27 06:18:37 PM PDT 24
Peak memory 197368 kb
Host smart-42fa0d55-71a3-4ed2-bb28-15166577f123
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799352077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2799352077
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1988822907
Short name T509
Test name
Test status
Simulation time 632838299 ps
CPU time 0.92 seconds
Started Jul 27 06:18:37 PM PDT 24
Finished Jul 27 06:18:38 PM PDT 24
Peak memory 198132 kb
Host smart-b8b054af-9075-4dc1-98c9-c324b57388a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988822907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1988822907
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.1715672165
Short name T218
Test name
Test status
Simulation time 73538426 ps
CPU time 0.59 seconds
Started Jul 27 06:18:36 PM PDT 24
Finished Jul 27 06:18:37 PM PDT 24
Peak memory 197516 kb
Host smart-f8d289e1-4058-4a3d-bba2-18c6a32b3e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715672165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1715672165
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2627676147
Short name T456
Test name
Test status
Simulation time 105911762 ps
CPU time 0.65 seconds
Started Jul 27 06:18:35 PM PDT 24
Finished Jul 27 06:18:36 PM PDT 24
Peak memory 198128 kb
Host smart-c4e556ea-45a7-4a54-9573-77de7efd4e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627676147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2627676147
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2832418784
Short name T266
Test name
Test status
Simulation time 46258411 ps
CPU time 0.73 seconds
Started Jul 27 06:18:37 PM PDT 24
Finished Jul 27 06:18:38 PM PDT 24
Peak memory 201344 kb
Host smart-d6ecc59e-d73b-4a5f-b831-5c7ca0e80ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832418784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2832418784
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.4281538052
Short name T214
Test name
Test status
Simulation time 52101561 ps
CPU time 0.64 seconds
Started Jul 27 06:18:36 PM PDT 24
Finished Jul 27 06:18:36 PM PDT 24
Peak memory 198372 kb
Host smart-15b0f5bb-eb8e-44a0-a902-7d371cb28523
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281538052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.4281538052
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.1857575629
Short name T607
Test name
Test status
Simulation time 92468366 ps
CPU time 1.02 seconds
Started Jul 27 06:18:37 PM PDT 24
Finished Jul 27 06:18:38 PM PDT 24
Peak memory 209560 kb
Host smart-84e429c8-9d82-4c61-8f61-85c81be7b71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857575629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1857575629
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3422702418
Short name T397
Test name
Test status
Simulation time 76249646 ps
CPU time 0.72 seconds
Started Jul 27 06:18:35 PM PDT 24
Finished Jul 27 06:18:36 PM PDT 24
Peak memory 197968 kb
Host smart-faf679d2-a4b9-4827-a52f-51de3803e399
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422702418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3422702418
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.894746445
Short name T414
Test name
Test status
Simulation time 31474098 ps
CPU time 0.68 seconds
Started Jul 27 06:18:35 PM PDT 24
Finished Jul 27 06:18:36 PM PDT 24
Peak memory 199432 kb
Host smart-3497d175-3cd9-40be-ac96-9d31c2995c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894746445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.894746445
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.1859919826
Short name T541
Test name
Test status
Simulation time 73719387 ps
CPU time 0.99 seconds
Started Jul 27 06:18:35 PM PDT 24
Finished Jul 27 06:18:36 PM PDT 24
Peak memory 200812 kb
Host smart-cf5c79b4-22b9-42d6-95b0-a0665c776877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859919826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1859919826
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.737222233
Short name T142
Test name
Test status
Simulation time 68248641 ps
CPU time 0.74 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198636 kb
Host smart-da9a2cb3-83c6-43ff-903a-f49884e3e463
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737222233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.737222233
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.532726097
Short name T327
Test name
Test status
Simulation time 32345258 ps
CPU time 0.64 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198084 kb
Host smart-50c4ef0f-b18b-40e9-add5-72ec3190ad9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532726097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.532726097
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.4180945658
Short name T561
Test name
Test status
Simulation time 853373955 ps
CPU time 0.93 seconds
Started Jul 27 06:18:44 PM PDT 24
Finished Jul 27 06:18:45 PM PDT 24
Peak memory 198104 kb
Host smart-ab568e10-287e-4c19-8686-a469c7231d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180945658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.4180945658
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.3287555368
Short name T211
Test name
Test status
Simulation time 61139666 ps
CPU time 0.6 seconds
Started Jul 27 06:18:44 PM PDT 24
Finished Jul 27 06:18:45 PM PDT 24
Peak memory 197444 kb
Host smart-3ffb2ba0-e491-43c4-9e24-ee4c1f73d597
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287555368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3287555368
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1767513482
Short name T212
Test name
Test status
Simulation time 73434849 ps
CPU time 0.61 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198120 kb
Host smart-abbf7626-271f-496b-94b9-3b2b87898e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767513482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1767513482
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.2030251541
Short name T6
Test name
Test status
Simulation time 338096304 ps
CPU time 0.69 seconds
Started Jul 27 06:18:45 PM PDT 24
Finished Jul 27 06:18:46 PM PDT 24
Peak memory 201464 kb
Host smart-b4e41604-4d38-4225-841b-19392c740318
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030251541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.2030251541
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.329166144
Short name T309
Test name
Test status
Simulation time 135607795 ps
CPU time 0.7 seconds
Started Jul 27 06:18:34 PM PDT 24
Finished Jul 27 06:18:35 PM PDT 24
Peak memory 199072 kb
Host smart-f5ffd2ec-5983-4717-84a9-71cfc8b85d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329166144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.329166144
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1521203485
Short name T225
Test name
Test status
Simulation time 154337026 ps
CPU time 0.83 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 209552 kb
Host smart-3db9342c-0ae4-4751-9a38-0ddd68fd3b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521203485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1521203485
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3426354178
Short name T575
Test name
Test status
Simulation time 102780317 ps
CPU time 0.89 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 199248 kb
Host smart-79eb54b4-0cb9-4b06-af78-ca863244d16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426354178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3426354178
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2354061787
Short name T523
Test name
Test status
Simulation time 28681898 ps
CPU time 0.63 seconds
Started Jul 27 06:18:36 PM PDT 24
Finished Jul 27 06:18:37 PM PDT 24
Peak memory 199488 kb
Host smart-de068f2f-70ef-487c-9074-b9a122adf6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354061787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2354061787
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.4081826264
Short name T57
Test name
Test status
Simulation time 32713280 ps
CPU time 0.76 seconds
Started Jul 27 06:18:37 PM PDT 24
Finished Jul 27 06:18:38 PM PDT 24
Peak memory 198256 kb
Host smart-d139bea4-ddab-43c7-84c4-f9123c7d6ddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081826264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.4081826264
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3759627437
Short name T417
Test name
Test status
Simulation time 36607617 ps
CPU time 0.83 seconds
Started Jul 27 06:18:45 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198840 kb
Host smart-f5d8ca08-d9ab-4dbb-b923-3878ac2340ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759627437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3759627437
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3710423406
Short name T418
Test name
Test status
Simulation time 65776257 ps
CPU time 0.84 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 199140 kb
Host smart-f1b7bb53-e455-4f4d-a255-1296300bac5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710423406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3710423406
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2894735483
Short name T135
Test name
Test status
Simulation time 73990412 ps
CPU time 0.6 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198100 kb
Host smart-fb833e63-bb16-442e-a082-2e2403c873ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894735483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.2894735483
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.3758431820
Short name T429
Test name
Test status
Simulation time 555585031 ps
CPU time 0.95 seconds
Started Jul 27 06:18:45 PM PDT 24
Finished Jul 27 06:18:46 PM PDT 24
Peak memory 198184 kb
Host smart-c77ac8b9-ee0e-4f3e-8090-1af8c0c99f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758431820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.3758431820
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.3514907822
Short name T570
Test name
Test status
Simulation time 65427380 ps
CPU time 0.61 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198168 kb
Host smart-83167d2f-a1bc-482d-9270-67cae73e08d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514907822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3514907822
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2154586122
Short name T480
Test name
Test status
Simulation time 81134924 ps
CPU time 0.63 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198428 kb
Host smart-22731c23-089e-4967-b3b2-5c8b676c729a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154586122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2154586122
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1192755779
Short name T597
Test name
Test status
Simulation time 45330883 ps
CPU time 0.75 seconds
Started Jul 27 06:18:48 PM PDT 24
Finished Jul 27 06:18:49 PM PDT 24
Peak memory 201440 kb
Host smart-0d5caa5f-edd0-41d6-b30b-c52eeba27a72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192755779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1192755779
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.3854822726
Short name T223
Test name
Test status
Simulation time 58215531 ps
CPU time 0.81 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 199132 kb
Host smart-4e2312cf-00d5-474f-a536-78f8aab1c529
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854822726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.3854822726
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.427567408
Short name T584
Test name
Test status
Simulation time 150253908 ps
CPU time 0.78 seconds
Started Jul 27 06:18:49 PM PDT 24
Finished Jul 27 06:18:50 PM PDT 24
Peak memory 209504 kb
Host smart-896b3426-3d8d-4742-aafe-9e0fb551ae62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427567408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.427567408
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3622394611
Short name T530
Test name
Test status
Simulation time 51303707 ps
CPU time 0.89 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 199144 kb
Host smart-9e995099-2ad6-4d54-ad5b-196ad528203f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622394611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3622394611
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.852070470
Short name T462
Test name
Test status
Simulation time 50438050 ps
CPU time 0.62 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198580 kb
Host smart-3bde70b4-0083-411d-84f2-7e3d28e601ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852070470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.852070470
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1182106574
Short name T239
Test name
Test status
Simulation time 23592087 ps
CPU time 0.73 seconds
Started Jul 27 06:18:50 PM PDT 24
Finished Jul 27 06:18:51 PM PDT 24
Peak memory 198700 kb
Host smart-8886b9a8-2380-487a-8213-a7276f080e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182106574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1182106574
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.801925366
Short name T566
Test name
Test status
Simulation time 32819658 ps
CPU time 0.61 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 197392 kb
Host smart-50c9f1e6-ed2d-4aca-a10a-5a30b0a63e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801925366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.801925366
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.716249052
Short name T355
Test name
Test status
Simulation time 172022593 ps
CPU time 0.97 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198132 kb
Host smart-da33c1eb-ca6a-4be8-a016-9f49b9e6f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716249052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.716249052
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1638046582
Short name T208
Test name
Test status
Simulation time 35231627 ps
CPU time 0.64 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198140 kb
Host smart-e1a4d015-8cf9-4e7b-95e2-59b71902e101
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638046582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1638046582
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.2883447705
Short name T209
Test name
Test status
Simulation time 37087407 ps
CPU time 0.61 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198180 kb
Host smart-abe9d2e2-027f-4c45-b2a6-249acd945ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883447705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2883447705
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3270328596
Short name T196
Test name
Test status
Simulation time 76882680 ps
CPU time 0.69 seconds
Started Jul 27 06:18:57 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 201232 kb
Host smart-fcc8a030-c0c7-4f1f-9903-b58c0e55343c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270328596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3270328596
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1379184208
Short name T435
Test name
Test status
Simulation time 76791772 ps
CPU time 0.7 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:48 PM PDT 24
Peak memory 198520 kb
Host smart-7a25c9f3-eaba-48be-9aac-5e9aaa543b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379184208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1379184208
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.886312564
Short name T567
Test name
Test status
Simulation time 150221534 ps
CPU time 0.85 seconds
Started Jul 27 06:18:47 PM PDT 24
Finished Jul 27 06:18:49 PM PDT 24
Peak memory 209516 kb
Host smart-3ce137ad-4b9b-4a3f-98e9-cb232a3f851e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886312564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.886312564
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2268552907
Short name T206
Test name
Test status
Simulation time 89306395 ps
CPU time 0.73 seconds
Started Jul 27 06:18:46 PM PDT 24
Finished Jul 27 06:18:47 PM PDT 24
Peak memory 198332 kb
Host smart-632420eb-43ca-48c8-a7ca-5a2745227239
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268552907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2268552907
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1806341888
Short name T163
Test name
Test status
Simulation time 70063603 ps
CPU time 0.65 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:03 PM PDT 24
Peak memory 199164 kb
Host smart-976a1ff3-c9a4-449f-a36a-3ad948a94699
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806341888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1806341888
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.457538395
Short name T580
Test name
Test status
Simulation time 70702345 ps
CPU time 0.6 seconds
Started Jul 27 06:19:00 PM PDT 24
Finished Jul 27 06:19:01 PM PDT 24
Peak memory 197344 kb
Host smart-15e68703-8686-4d31-a886-9064a86ce5d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457538395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.457538395
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1208016440
Short name T437
Test name
Test status
Simulation time 162323520 ps
CPU time 1.04 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:03 PM PDT 24
Peak memory 198468 kb
Host smart-e331cb48-945d-4bfd-8208-f9fe17e4bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208016440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1208016440
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.3026472271
Short name T448
Test name
Test status
Simulation time 54115053 ps
CPU time 0.58 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:03 PM PDT 24
Peak memory 197388 kb
Host smart-96d3b223-1281-41bd-b068-920745f12387
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026472271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3026472271
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.2386809148
Short name T542
Test name
Test status
Simulation time 50650128 ps
CPU time 0.63 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 198104 kb
Host smart-773b8e6e-ca11-4f1c-b188-98e726c312a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386809148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2386809148
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2280144146
Short name T514
Test name
Test status
Simulation time 43896651 ps
CPU time 0.71 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 201404 kb
Host smart-c3de6984-9eae-47b1-8d16-afbbd2b0673b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280144146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2280144146
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.787272398
Short name T281
Test name
Test status
Simulation time 106841730 ps
CPU time 0.73 seconds
Started Jul 27 06:19:05 PM PDT 24
Finished Jul 27 06:19:06 PM PDT 24
Peak memory 199156 kb
Host smart-4d6d3b44-c58b-47bc-818b-28849681df65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787272398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.787272398
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.158133787
Short name T257
Test name
Test status
Simulation time 107697234 ps
CPU time 0.93 seconds
Started Jul 27 06:19:05 PM PDT 24
Finished Jul 27 06:19:06 PM PDT 24
Peak memory 209492 kb
Host smart-5e7637bc-e927-4c02-bad5-2cba626a3fd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158133787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.158133787
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1986651502
Short name T41
Test name
Test status
Simulation time 74146012 ps
CPU time 0.95 seconds
Started Jul 27 06:19:05 PM PDT 24
Finished Jul 27 06:19:06 PM PDT 24
Peak memory 199660 kb
Host smart-7eb7576d-06ad-4752-a479-2f7b57596500
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986651502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1986651502
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3284477772
Short name T436
Test name
Test status
Simulation time 73538102 ps
CPU time 0.69 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:03 PM PDT 24
Peak memory 198560 kb
Host smart-912ae16e-0b8d-4c2c-b5f6-401d22a75f78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284477772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3284477772
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2297415984
Short name T120
Test name
Test status
Simulation time 133853161 ps
CPU time 0.8 seconds
Started Jul 27 06:13:23 PM PDT 24
Finished Jul 27 06:13:24 PM PDT 24
Peak memory 200016 kb
Host smart-08301131-e14b-4855-85d4-4bcd61712f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297415984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2297415984
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2735506467
Short name T556
Test name
Test status
Simulation time 66369227 ps
CPU time 0.82 seconds
Started Jul 27 06:13:30 PM PDT 24
Finished Jul 27 06:13:31 PM PDT 24
Peak memory 199136 kb
Host smart-6a69c1ea-4e8d-47ce-81b3-6a0d5206a81a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735506467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2735506467
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.51136511
Short name T595
Test name
Test status
Simulation time 39640901 ps
CPU time 0.61 seconds
Started Jul 27 06:13:32 PM PDT 24
Finished Jul 27 06:13:33 PM PDT 24
Peak memory 198100 kb
Host smart-065075bf-c8e0-4e75-a910-ee11af987197
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51136511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_ma
lfunc.51136511
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.312784662
Short name T426
Test name
Test status
Simulation time 162151398 ps
CPU time 0.95 seconds
Started Jul 27 06:13:30 PM PDT 24
Finished Jul 27 06:13:31 PM PDT 24
Peak memory 198136 kb
Host smart-78d9316c-b952-484a-930e-f6c21fd27970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312784662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.312784662
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2811474269
Short name T353
Test name
Test status
Simulation time 32055602 ps
CPU time 0.63 seconds
Started Jul 27 06:13:30 PM PDT 24
Finished Jul 27 06:13:31 PM PDT 24
Peak memory 198168 kb
Host smart-2f326a92-6bdf-4164-a7a5-78df660c0993
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811474269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2811474269
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.2479790497
Short name T491
Test name
Test status
Simulation time 218104023 ps
CPU time 0.6 seconds
Started Jul 27 06:13:30 PM PDT 24
Finished Jul 27 06:13:31 PM PDT 24
Peak memory 198156 kb
Host smart-6d26fb47-edc0-4a8d-b662-a132df606e83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479790497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2479790497
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2167631105
Short name T582
Test name
Test status
Simulation time 27206282 ps
CPU time 0.61 seconds
Started Jul 27 06:13:23 PM PDT 24
Finished Jul 27 06:13:24 PM PDT 24
Peak memory 198156 kb
Host smart-f3b0e517-64b3-442e-944e-931fa2720b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167631105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2167631105
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1633476039
Short name T370
Test name
Test status
Simulation time 130924484 ps
CPU time 0.86 seconds
Started Jul 27 06:13:32 PM PDT 24
Finished Jul 27 06:13:33 PM PDT 24
Peak memory 209528 kb
Host smart-afef02a8-10c3-41a0-894c-c6f9d737d66b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633476039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1633476039
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.249094583
Short name T298
Test name
Test status
Simulation time 68243946 ps
CPU time 0.89 seconds
Started Jul 27 06:13:31 PM PDT 24
Finished Jul 27 06:13:32 PM PDT 24
Peak memory 199268 kb
Host smart-561698ab-e992-4f26-800a-5699fd95dc38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249094583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.249094583
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2040425553
Short name T524
Test name
Test status
Simulation time 64167802 ps
CPU time 0.65 seconds
Started Jul 27 06:13:24 PM PDT 24
Finished Jul 27 06:13:25 PM PDT 24
Peak memory 199424 kb
Host smart-99d22a7d-da0f-4e97-a9eb-cdd650afee93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040425553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2040425553
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.4033721509
Short name T526
Test name
Test status
Simulation time 38125624 ps
CPU time 0.68 seconds
Started Jul 27 06:13:36 PM PDT 24
Finished Jul 27 06:13:37 PM PDT 24
Peak memory 198648 kb
Host smart-73eeb106-b0d5-4176-8465-31d259069d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033721509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.4033721509
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2609960668
Short name T138
Test name
Test status
Simulation time 131439410 ps
CPU time 0.67 seconds
Started Jul 27 06:13:44 PM PDT 24
Finished Jul 27 06:13:45 PM PDT 24
Peak memory 198504 kb
Host smart-14a1bf8c-4d95-434d-a82d-7132b885ad34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609960668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2609960668
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2251514946
Short name T447
Test name
Test status
Simulation time 36821574 ps
CPU time 0.58 seconds
Started Jul 27 06:13:45 PM PDT 24
Finished Jul 27 06:13:45 PM PDT 24
Peak memory 198072 kb
Host smart-8e386f23-7d6c-4974-9883-7355c32fa795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251514946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2251514946
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.175069918
Short name T485
Test name
Test status
Simulation time 790868718 ps
CPU time 0.98 seconds
Started Jul 27 06:13:45 PM PDT 24
Finished Jul 27 06:13:46 PM PDT 24
Peak memory 198180 kb
Host smart-6ff721ba-b422-4a99-8ed2-d80ec69a76b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175069918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.175069918
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3087192346
Short name T19
Test name
Test status
Simulation time 82834889 ps
CPU time 0.65 seconds
Started Jul 27 06:13:45 PM PDT 24
Finished Jul 27 06:13:46 PM PDT 24
Peak memory 197464 kb
Host smart-9069b997-7f15-455a-b39a-052b8787315e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087192346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3087192346
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2747612943
Short name T334
Test name
Test status
Simulation time 219297524 ps
CPU time 0.63 seconds
Started Jul 27 06:13:47 PM PDT 24
Finished Jul 27 06:13:47 PM PDT 24
Peak memory 198148 kb
Host smart-c5a4a0b4-0b52-4ac0-98e5-20de33e8be5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747612943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2747612943
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.3507229351
Short name T419
Test name
Test status
Simulation time 44177037 ps
CPU time 0.75 seconds
Started Jul 27 06:13:49 PM PDT 24
Finished Jul 27 06:13:50 PM PDT 24
Peak memory 201476 kb
Host smart-c4893135-bcb3-4938-b9cb-b7ec819e7c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507229351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.3507229351
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.497188336
Short name T612
Test name
Test status
Simulation time 62476401 ps
CPU time 0.87 seconds
Started Jul 27 06:13:37 PM PDT 24
Finished Jul 27 06:13:38 PM PDT 24
Peak memory 199136 kb
Host smart-b5231a6c-1449-4583-9026-01b1ef1c0ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497188336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.497188336
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.2230436728
Short name T494
Test name
Test status
Simulation time 90427842 ps
CPU time 0.9 seconds
Started Jul 27 06:13:46 PM PDT 24
Finished Jul 27 06:13:47 PM PDT 24
Peak memory 209540 kb
Host smart-b2fe7193-adca-49ee-b8ca-2a8b49172574
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230436728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.2230436728
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1913284398
Short name T423
Test name
Test status
Simulation time 52620051 ps
CPU time 0.85 seconds
Started Jul 27 06:13:48 PM PDT 24
Finished Jul 27 06:13:49 PM PDT 24
Peak memory 199280 kb
Host smart-0370e4a7-ff5f-4aca-ba0f-d7a6e422bcbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913284398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1913284398
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.2877628148
Short name T611
Test name
Test status
Simulation time 39324239 ps
CPU time 0.64 seconds
Started Jul 27 06:13:30 PM PDT 24
Finished Jul 27 06:13:30 PM PDT 24
Peak memory 198564 kb
Host smart-3ff854d4-e8d2-4af5-93b1-1833177c6216
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877628148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2877628148
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2202659823
Short name T527
Test name
Test status
Simulation time 108194577 ps
CPU time 0.77 seconds
Started Jul 27 06:13:46 PM PDT 24
Finished Jul 27 06:13:47 PM PDT 24
Peak memory 199856 kb
Host smart-c9da3db9-7d56-4de1-b87e-c8840e629434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202659823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2202659823
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1317547309
Short name T169
Test name
Test status
Simulation time 48824027 ps
CPU time 0.77 seconds
Started Jul 27 06:13:55 PM PDT 24
Finished Jul 27 06:13:56 PM PDT 24
Peak memory 199212 kb
Host smart-0e845d5c-1a74-4481-8e3e-e80b899e42f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317547309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1317547309
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2373577789
Short name T252
Test name
Test status
Simulation time 32433972 ps
CPU time 0.62 seconds
Started Jul 27 06:13:48 PM PDT 24
Finished Jul 27 06:13:49 PM PDT 24
Peak memory 198084 kb
Host smart-03a55763-7ed8-449a-9002-260fd05a5bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373577789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2373577789
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2325569151
Short name T348
Test name
Test status
Simulation time 294950384 ps
CPU time 0.98 seconds
Started Jul 27 06:13:54 PM PDT 24
Finished Jul 27 06:13:55 PM PDT 24
Peak memory 198180 kb
Host smart-2c5f39da-3dc7-4c02-b732-0c80f42d8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325569151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2325569151
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1381641506
Short name T236
Test name
Test status
Simulation time 39493355 ps
CPU time 0.61 seconds
Started Jul 27 06:13:57 PM PDT 24
Finished Jul 27 06:13:58 PM PDT 24
Peak memory 198108 kb
Host smart-6594251a-18e6-4cdc-aeff-eda08c692e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381641506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1381641506
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.357927417
Short name T52
Test name
Test status
Simulation time 47806721 ps
CPU time 0.68 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 198152 kb
Host smart-49c5b6af-d23a-4984-bd18-f1169c14687b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357927417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.357927417
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2550177408
Short name T182
Test name
Test status
Simulation time 43434180 ps
CPU time 0.71 seconds
Started Jul 27 06:14:00 PM PDT 24
Finished Jul 27 06:14:01 PM PDT 24
Peak memory 201428 kb
Host smart-ad5dd7e3-3564-4a6e-b6cd-45f0abfea481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550177408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2550177408
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.4008270152
Short name T375
Test name
Test status
Simulation time 260652597 ps
CPU time 0.72 seconds
Started Jul 27 06:13:46 PM PDT 24
Finished Jul 27 06:13:47 PM PDT 24
Peak memory 198456 kb
Host smart-8f04e620-a1b0-4c76-9df7-3937bdab5303
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008270152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.4008270152
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1845539209
Short name T286
Test name
Test status
Simulation time 120446377 ps
CPU time 0.94 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 209616 kb
Host smart-fc0a052e-6c64-42aa-bf9a-8715731db1a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845539209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1845539209
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2475064722
Short name T241
Test name
Test status
Simulation time 135008426 ps
CPU time 0.78 seconds
Started Jul 27 06:13:44 PM PDT 24
Finished Jul 27 06:13:45 PM PDT 24
Peak memory 199628 kb
Host smart-a3d4fa0e-cc0a-4279-b75c-e9f5ed1cf478
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475064722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2475064722
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3824807910
Short name T439
Test name
Test status
Simulation time 39126419 ps
CPU time 0.64 seconds
Started Jul 27 06:13:44 PM PDT 24
Finished Jul 27 06:13:45 PM PDT 24
Peak memory 198488 kb
Host smart-da324da0-5509-457f-ad87-24d93a5e8bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824807910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3824807910
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.2784611127
Short name T263
Test name
Test status
Simulation time 220034814 ps
CPU time 0.73 seconds
Started Jul 27 06:14:03 PM PDT 24
Finished Jul 27 06:14:04 PM PDT 24
Peak memory 198716 kb
Host smart-0fd40d2c-fcbf-4b88-b3d0-2615ad412b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784611127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2784611127
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.486360208
Short name T440
Test name
Test status
Simulation time 52636419 ps
CPU time 0.79 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 198592 kb
Host smart-da5cbdd1-bff9-426b-8c4d-75815fe9acf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486360208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.486360208
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2419115016
Short name T498
Test name
Test status
Simulation time 31066854 ps
CPU time 0.65 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 197412 kb
Host smart-109bfe24-25c7-46f7-97fa-677832e39093
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419115016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2419115016
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.4034852791
Short name T310
Test name
Test status
Simulation time 317026415 ps
CPU time 0.96 seconds
Started Jul 27 06:14:05 PM PDT 24
Finished Jul 27 06:14:06 PM PDT 24
Peak memory 198168 kb
Host smart-e65e66ff-0964-45d2-becf-e45e08ffec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034852791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.4034852791
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3638397313
Short name T569
Test name
Test status
Simulation time 47668025 ps
CPU time 0.65 seconds
Started Jul 27 06:14:01 PM PDT 24
Finished Jul 27 06:14:02 PM PDT 24
Peak memory 198152 kb
Host smart-fb12f571-6c62-4950-baaa-1a5aeefa4f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638397313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3638397313
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.2105920371
Short name T427
Test name
Test status
Simulation time 34903596 ps
CPU time 0.59 seconds
Started Jul 27 06:14:03 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 198464 kb
Host smart-66e2ba98-6f98-490c-b064-1a84d1bd4ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105920371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2105920371
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2450952035
Short name T3
Test name
Test status
Simulation time 127596851 ps
CPU time 0.66 seconds
Started Jul 27 06:13:56 PM PDT 24
Finished Jul 27 06:13:57 PM PDT 24
Peak memory 198376 kb
Host smart-d3bcd97c-61de-4f67-84ec-4963eedf111e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450952035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2450952035
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.1428052152
Short name T425
Test name
Test status
Simulation time 121190042 ps
CPU time 1.04 seconds
Started Jul 27 06:14:01 PM PDT 24
Finished Jul 27 06:14:02 PM PDT 24
Peak memory 209484 kb
Host smart-88869dd8-0faf-4ad7-b65d-43fbaa8954be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428052152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.1428052152
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2752553236
Short name T596
Test name
Test status
Simulation time 73050530 ps
CPU time 0.78 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 198176 kb
Host smart-fdf6e2d5-17e1-40d5-831e-d05d04bad73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752553236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2752553236
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2955328754
Short name T499
Test name
Test status
Simulation time 63195640 ps
CPU time 0.63 seconds
Started Jul 27 06:14:02 PM PDT 24
Finished Jul 27 06:14:03 PM PDT 24
Peak memory 198532 kb
Host smart-5860d103-7de4-4f9a-99b1-fe980e45de77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955328754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2955328754
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2726383273
Short name T98
Test name
Test status
Simulation time 98911443 ps
CPU time 0.85 seconds
Started Jul 27 06:14:13 PM PDT 24
Finished Jul 27 06:14:14 PM PDT 24
Peak memory 200180 kb
Host smart-c86d70bc-28f0-4367-850c-8f236ca02a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726383273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2726383273
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.872847607
Short name T403
Test name
Test status
Simulation time 62359809 ps
CPU time 0.73 seconds
Started Jul 27 06:14:14 PM PDT 24
Finished Jul 27 06:14:15 PM PDT 24
Peak memory 199140 kb
Host smart-45bc66e6-47dc-4d62-ac5d-2b2b457c9fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872847607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.872847607
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2891000620
Short name T258
Test name
Test status
Simulation time 53373791 ps
CPU time 0.61 seconds
Started Jul 27 06:14:13 PM PDT 24
Finished Jul 27 06:14:14 PM PDT 24
Peak memory 198092 kb
Host smart-8e630d8b-2eb4-4c44-ad0f-b0504752850c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891000620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2891000620
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1682883243
Short name T324
Test name
Test status
Simulation time 163201781 ps
CPU time 0.99 seconds
Started Jul 27 06:14:11 PM PDT 24
Finished Jul 27 06:14:12 PM PDT 24
Peak memory 198468 kb
Host smart-670749c8-9dd4-40f3-914c-9a84c28a91a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682883243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1682883243
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.3910295398
Short name T564
Test name
Test status
Simulation time 41175130 ps
CPU time 0.6 seconds
Started Jul 27 06:14:13 PM PDT 24
Finished Jul 27 06:14:14 PM PDT 24
Peak memory 198156 kb
Host smart-00b1c6f1-a265-4a10-9a10-1dde93d62da7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910295398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3910295398
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.1143324535
Short name T51
Test name
Test status
Simulation time 28154287 ps
CPU time 0.63 seconds
Started Jul 27 06:14:11 PM PDT 24
Finished Jul 27 06:14:12 PM PDT 24
Peak memory 198136 kb
Host smart-9a6969c1-19e3-49be-8213-f89c866484c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143324535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1143324535
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.647528940
Short name T187
Test name
Test status
Simulation time 56431953 ps
CPU time 0.69 seconds
Started Jul 27 06:14:11 PM PDT 24
Finished Jul 27 06:14:12 PM PDT 24
Peak memory 201216 kb
Host smart-be109419-f060-4bb9-9b60-2af85576de90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647528940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid
.647528940
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2935521675
Short name T204
Test name
Test status
Simulation time 36686421 ps
CPU time 0.65 seconds
Started Jul 27 06:14:12 PM PDT 24
Finished Jul 27 06:14:13 PM PDT 24
Peak memory 198440 kb
Host smart-ff13ccfc-080d-4279-940c-d41647c36c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935521675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2935521675
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.1744727190
Short name T510
Test name
Test status
Simulation time 155547992 ps
CPU time 0.79 seconds
Started Jul 27 06:14:13 PM PDT 24
Finished Jul 27 06:14:14 PM PDT 24
Peak memory 209572 kb
Host smart-bc037659-4590-4fba-a4d6-0405a9d7305f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744727190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1744727190
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1712636159
Short name T344
Test name
Test status
Simulation time 65177700 ps
CPU time 0.77 seconds
Started Jul 27 06:14:12 PM PDT 24
Finished Jul 27 06:14:13 PM PDT 24
Peak memory 198344 kb
Host smart-941e2784-7e08-4776-95ee-44507c02328a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712636159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1712636159
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3532196984
Short name T468
Test name
Test status
Simulation time 184220550 ps
CPU time 0.63 seconds
Started Jul 27 06:14:11 PM PDT 24
Finished Jul 27 06:14:12 PM PDT 24
Peak memory 198536 kb
Host smart-08fd635b-32ec-42ac-8e98-fa255685db8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532196984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3532196984
Directory /workspace/9.pwrmgr_smoke/latest
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