Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T5

2

T6

10

T7

2

auto[1]

475

1

T5

1

T6

7

T14

3

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591

1

T5

2

T6

9

T7

2

auto[1]

483

1

T5

1

T6

8

T14

3

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

496

1

T5

1

T6

8

T14

3

auto[1]

578

1

T5

2

T6

9

T7

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

889

1

T5

3

T6

17

T7

1

auto[1]

185

1

T7

1

T29

2

T30

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

490

1

T6

6

T14

4

T29

6

auto[1]

584

1

T5

3

T6

11

T7

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

593

1

T5

1

T6

9

T7

2

auto[1]

481

1

T5

2

T6

8

T14

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

24

1

T6

1

T14

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T167

1

T168

1

T169

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T47

1

T127

1

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T27

1

T170

1

T147

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

28

1

T6

1

T127

1

T171

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T172

1

T173

1

T174

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T6

1

T7

1

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

60

1

T7

1

T53

1

T54

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T14

1

T48

1

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T48

1

T25

1

T95

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T14

1

T95

1

T97

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T175

1

T52

1

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T6

1

T47

1

T55

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T176

1

T177

1

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T5

1

T14

2

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T63

1

T178

1

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

26

1

T179

1

T180

5

T181

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T50

1

T182

1

T183

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T6

1

T30

1

T55

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T167

1

T184

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T6

1

T14

1

T47

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T186

1

T170

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T5

1

T47

1

T129

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T187

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

23

1

T55

1

T127

2

T188

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T188

1

T189

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T6

2

T29

1

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T88

1

T173

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T6

1

T97

1

T179

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T179

1

T177

1

T190

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T6

1

T48

1

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T48

1

T191

1

T174

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28

1

T29

1

T55

1

T26

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T29

1

T26

1

T192

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T6

1

T14

1

T30

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T30

1

T50

1

T193

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

24

1

T48

1

T127

2

T90

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T90

1

T194

1

T169

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T6

2

T88

1

T90

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T195

1

T196

1

T64

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T6

1

T55

2

T188

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T188

1

T176

1

T193

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T30

1

T47

1

T88

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T191

1

T197

1

T187

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T5

1

T6

1

T88

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T88

1

T27

1

T198

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T47

2

T90

1

T168

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T51

1

T198

1

T189

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

24

1

T29

1

T47

1

T167

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T29

1

T186

1

T63

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32

1

T47

4

T89

1

T127

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T49

1

T199

1

T200

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T30

1

T89

1

T96

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T30

1

T89

1

T96

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T6

1

T89

1

T179

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T89

1

T179

1

T51

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T55

1

T127

1

T98

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T172

1

T192

1

T201

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T29

1

T127

1

T96

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T96

1

T148

1

T202

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T6

1

T47

1

T55

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T90

1

T168

1

T202

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T14

2

T25

1

T95

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T25

1

T95

1

T203

1