Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.23 96.15 99.44 96.00 96.18 100.00 95.74


Total test records in report: 739
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T558 /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1876861568 Jul 28 05:07:28 PM PDT 24 Jul 28 05:07:29 PM PDT 24 57937282 ps
T559 /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.622936876 Jul 28 05:08:56 PM PDT 24 Jul 28 05:08:57 PM PDT 24 78156787 ps
T560 /workspace/coverage/default/25.pwrmgr_reset.1863914877 Jul 28 05:08:02 PM PDT 24 Jul 28 05:08:02 PM PDT 24 64856358 ps
T561 /workspace/coverage/default/11.pwrmgr_reset.1369989363 Jul 28 05:07:28 PM PDT 24 Jul 28 05:07:29 PM PDT 24 87884382 ps
T178 /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1369678832 Jul 28 05:07:49 PM PDT 24 Jul 28 05:07:50 PM PDT 24 46274900 ps
T562 /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1219413475 Jul 28 05:08:49 PM PDT 24 Jul 28 05:08:50 PM PDT 24 149303539 ps
T563 /workspace/coverage/default/3.pwrmgr_global_esc.2162586189 Jul 28 05:07:08 PM PDT 24 Jul 28 05:07:08 PM PDT 24 75099083 ps
T564 /workspace/coverage/default/23.pwrmgr_aborted_low_power.464845184 Jul 28 05:07:48 PM PDT 24 Jul 28 05:07:49 PM PDT 24 79008703 ps
T565 /workspace/coverage/default/38.pwrmgr_glitch.396961942 Jul 28 05:08:39 PM PDT 24 Jul 28 05:08:40 PM PDT 24 39197367 ps
T566 /workspace/coverage/default/9.pwrmgr_reset_invalid.813153271 Jul 28 05:07:22 PM PDT 24 Jul 28 05:07:23 PM PDT 24 233321810 ps
T567 /workspace/coverage/default/20.pwrmgr_glitch.2968463454 Jul 28 05:07:48 PM PDT 24 Jul 28 05:07:49 PM PDT 24 48047331 ps
T568 /workspace/coverage/default/7.pwrmgr_global_esc.3376545241 Jul 28 05:07:15 PM PDT 24 Jul 28 05:07:16 PM PDT 24 43932241 ps
T569 /workspace/coverage/default/45.pwrmgr_reset_invalid.2961881956 Jul 28 05:08:57 PM PDT 24 Jul 28 05:08:58 PM PDT 24 177323232 ps
T570 /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.348096807 Jul 28 05:07:16 PM PDT 24 Jul 28 05:07:17 PM PDT 24 30805431 ps
T571 /workspace/coverage/default/15.pwrmgr_glitch.2095383159 Jul 28 05:07:58 PM PDT 24 Jul 28 05:07:59 PM PDT 24 23459690 ps
T572 /workspace/coverage/default/24.pwrmgr_escalation_timeout.1966426625 Jul 28 05:08:13 PM PDT 24 Jul 28 05:08:14 PM PDT 24 304791311 ps
T573 /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.19336716 Jul 28 05:08:11 PM PDT 24 Jul 28 05:08:12 PM PDT 24 78262570 ps
T574 /workspace/coverage/default/48.pwrmgr_global_esc.4122297937 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:32 PM PDT 24 31622533 ps
T575 /workspace/coverage/default/16.pwrmgr_reset_invalid.764898241 Jul 28 05:07:57 PM PDT 24 Jul 28 05:07:58 PM PDT 24 243727688 ps
T576 /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1419717803 Jul 28 05:08:37 PM PDT 24 Jul 28 05:08:38 PM PDT 24 72107067 ps
T206 /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1564427901 Jul 28 05:07:49 PM PDT 24 Jul 28 05:07:50 PM PDT 24 55429423 ps
T577 /workspace/coverage/default/36.pwrmgr_escalation_timeout.4010457800 Jul 28 05:08:52 PM PDT 24 Jul 28 05:08:53 PM PDT 24 991262943 ps
T578 /workspace/coverage/default/37.pwrmgr_glitch.53108849 Jul 28 05:08:37 PM PDT 24 Jul 28 05:08:38 PM PDT 24 232535297 ps
T579 /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.4133794016 Jul 28 05:07:47 PM PDT 24 Jul 28 05:07:48 PM PDT 24 55204090 ps
T580 /workspace/coverage/default/19.pwrmgr_smoke.1686723261 Jul 28 05:07:56 PM PDT 24 Jul 28 05:07:57 PM PDT 24 35970813 ps
T581 /workspace/coverage/default/39.pwrmgr_glitch.1314066448 Jul 28 05:08:44 PM PDT 24 Jul 28 05:08:50 PM PDT 24 46473308 ps
T582 /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.4010783032 Jul 28 05:08:43 PM PDT 24 Jul 28 05:08:44 PM PDT 24 86038045 ps
T583 /workspace/coverage/default/10.pwrmgr_global_esc.2843026449 Jul 28 05:07:14 PM PDT 24 Jul 28 05:07:15 PM PDT 24 34948520 ps
T584 /workspace/coverage/default/5.pwrmgr_glitch.195673796 Jul 28 05:07:10 PM PDT 24 Jul 28 05:07:11 PM PDT 24 42274280 ps
T585 /workspace/coverage/default/8.pwrmgr_glitch.4108651249 Jul 28 05:07:30 PM PDT 24 Jul 28 05:07:31 PM PDT 24 76195008 ps
T586 /workspace/coverage/default/19.pwrmgr_reset.962692636 Jul 28 05:07:50 PM PDT 24 Jul 28 05:07:51 PM PDT 24 74136803 ps
T587 /workspace/coverage/default/10.pwrmgr_glitch.252116986 Jul 28 05:07:27 PM PDT 24 Jul 28 05:07:28 PM PDT 24 30108279 ps
T588 /workspace/coverage/default/28.pwrmgr_reset.1006566495 Jul 28 05:08:04 PM PDT 24 Jul 28 05:08:05 PM PDT 24 37173525 ps
T589 /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.448720438 Jul 28 05:07:31 PM PDT 24 Jul 28 05:07:32 PM PDT 24 53264592 ps
T590 /workspace/coverage/default/6.pwrmgr_glitch.814040210 Jul 28 05:07:21 PM PDT 24 Jul 28 05:07:22 PM PDT 24 70314491 ps
T591 /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.4151290269 Jul 28 05:08:53 PM PDT 24 Jul 28 05:08:54 PM PDT 24 59810907 ps
T592 /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.432949773 Jul 28 05:07:22 PM PDT 24 Jul 28 05:07:22 PM PDT 24 29156016 ps
T593 /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3341422492 Jul 28 05:08:10 PM PDT 24 Jul 28 05:08:11 PM PDT 24 179855316 ps
T594 /workspace/coverage/default/39.pwrmgr_global_esc.2620255828 Jul 28 05:08:51 PM PDT 24 Jul 28 05:08:51 PM PDT 24 24927061 ps
T595 /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3042946285 Jul 28 05:08:49 PM PDT 24 Jul 28 05:08:50 PM PDT 24 30213537 ps
T596 /workspace/coverage/default/46.pwrmgr_aborted_low_power.231597535 Jul 28 05:08:58 PM PDT 24 Jul 28 05:08:59 PM PDT 24 47797807 ps
T597 /workspace/coverage/default/9.pwrmgr_glitch.2393448647 Jul 28 05:07:25 PM PDT 24 Jul 28 05:07:26 PM PDT 24 38962999 ps
T598 /workspace/coverage/default/17.pwrmgr_reset.617129763 Jul 28 05:07:47 PM PDT 24 Jul 28 05:07:47 PM PDT 24 43505498 ps
T599 /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.462678748 Jul 28 05:07:55 PM PDT 24 Jul 28 05:07:56 PM PDT 24 60948717 ps
T600 /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2234743605 Jul 28 05:07:02 PM PDT 24 Jul 28 05:07:02 PM PDT 24 90381944 ps
T601 /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2235439726 Jul 28 05:07:05 PM PDT 24 Jul 28 05:07:06 PM PDT 24 281487608 ps
T602 /workspace/coverage/default/12.pwrmgr_glitch.4207927834 Jul 28 05:07:35 PM PDT 24 Jul 28 05:07:36 PM PDT 24 40908613 ps
T603 /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2051650706 Jul 28 05:08:41 PM PDT 24 Jul 28 05:08:47 PM PDT 24 49075730 ps
T604 /workspace/coverage/default/32.pwrmgr_smoke.1885332745 Jul 28 05:08:25 PM PDT 24 Jul 28 05:08:26 PM PDT 24 38324473 ps
T605 /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3307382927 Jul 28 05:07:21 PM PDT 24 Jul 28 05:07:22 PM PDT 24 99253182 ps
T606 /workspace/coverage/default/10.pwrmgr_smoke.772804196 Jul 28 05:07:26 PM PDT 24 Jul 28 05:07:27 PM PDT 24 27940345 ps
T607 /workspace/coverage/default/22.pwrmgr_smoke.135623933 Jul 28 05:07:53 PM PDT 24 Jul 28 05:07:54 PM PDT 24 60953683 ps
T608 /workspace/coverage/default/39.pwrmgr_reset.859986955 Jul 28 05:08:43 PM PDT 24 Jul 28 05:08:44 PM PDT 24 81855227 ps
T609 /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1503697028 Jul 28 05:07:48 PM PDT 24 Jul 28 05:07:49 PM PDT 24 227789663 ps
T610 /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.887672708 Jul 28 05:07:20 PM PDT 24 Jul 28 05:07:21 PM PDT 24 51624761 ps
T611 /workspace/coverage/default/40.pwrmgr_glitch.1679814846 Jul 28 05:08:55 PM PDT 24 Jul 28 05:08:56 PM PDT 24 58636929 ps
T149 /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.1772830372 Jul 28 05:07:02 PM PDT 24 Jul 28 05:07:03 PM PDT 24 98015159 ps
T612 /workspace/coverage/default/39.pwrmgr_aborted_low_power.2760701631 Jul 28 05:08:37 PM PDT 24 Jul 28 05:08:38 PM PDT 24 137387585 ps
T613 /workspace/coverage/default/1.pwrmgr_global_esc.1393107567 Jul 28 05:06:59 PM PDT 24 Jul 28 05:07:00 PM PDT 24 72451385 ps
T614 /workspace/coverage/default/11.pwrmgr_glitch.1112613951 Jul 28 05:07:25 PM PDT 24 Jul 28 05:07:26 PM PDT 24 54991757 ps
T615 /workspace/coverage/default/49.pwrmgr_aborted_low_power.2951930768 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:15 PM PDT 24 41730455 ps
T616 /workspace/coverage/default/7.pwrmgr_aborted_low_power.843603959 Jul 28 05:07:16 PM PDT 24 Jul 28 05:07:18 PM PDT 24 36887889 ps
T617 /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2068563939 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:09 PM PDT 24 77939626 ps
T618 /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2085714285 Jul 28 05:08:46 PM PDT 24 Jul 28 05:08:47 PM PDT 24 53136887 ps
T619 /workspace/coverage/default/49.pwrmgr_glitch.546578232 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:18 PM PDT 24 40624300 ps
T620 /workspace/coverage/default/46.pwrmgr_escalation_timeout.4095201436 Jul 28 05:09:06 PM PDT 24 Jul 28 05:09:07 PM PDT 24 158977267 ps
T621 /workspace/coverage/default/13.pwrmgr_global_esc.2536897923 Jul 28 05:07:43 PM PDT 24 Jul 28 05:07:43 PM PDT 24 76160841 ps
T622 /workspace/coverage/default/28.pwrmgr_smoke.2190670682 Jul 28 05:08:02 PM PDT 24 Jul 28 05:08:03 PM PDT 24 49304884 ps
T623 /workspace/coverage/default/18.pwrmgr_glitch.2011192213 Jul 28 05:07:59 PM PDT 24 Jul 28 05:08:00 PM PDT 24 49040198 ps
T169 /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1944682470 Jul 28 05:09:12 PM PDT 24 Jul 28 05:09:12 PM PDT 24 44305031 ps
T624 /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2805459735 Jul 28 05:07:09 PM PDT 24 Jul 28 05:07:10 PM PDT 24 38966103 ps
T625 /workspace/coverage/default/24.pwrmgr_smoke.4059860425 Jul 28 05:08:18 PM PDT 24 Jul 28 05:08:19 PM PDT 24 58135724 ps
T626 /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3195629432 Jul 28 05:08:32 PM PDT 24 Jul 28 05:08:33 PM PDT 24 60747750 ps
T627 /workspace/coverage/default/29.pwrmgr_reset.1303236558 Jul 28 05:08:18 PM PDT 24 Jul 28 05:08:19 PM PDT 24 49127968 ps
T21 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1387025989 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 145769108 ps
T73 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2600351908 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 19546031 ps
T76 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3961453886 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 21645677 ps
T74 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1602734259 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 48291061 ps
T75 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4185142 Jul 28 05:01:42 PM PDT 24 Jul 28 05:01:43 PM PDT 24 36789244 ps
T153 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1283342504 Jul 28 05:01:53 PM PDT 24 Jul 28 05:01:53 PM PDT 24 50598695 ps
T22 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.396756655 Jul 28 05:01:42 PM PDT 24 Jul 28 05:01:43 PM PDT 24 103299210 ps
T79 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1529448661 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:35 PM PDT 24 53123313 ps
T119 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2742154622 Jul 28 05:01:30 PM PDT 24 Jul 28 05:01:31 PM PDT 24 30632074 ps
T120 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1057885911 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:47 PM PDT 24 74655431 ps
T157 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3439749818 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:45 PM PDT 24 25077309 ps
T23 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3828712574 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:35 PM PDT 24 84967586 ps
T154 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3296562076 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 45213963 ps
T628 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4142355949 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 18185280 ps
T61 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.729039015 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:33 PM PDT 24 165158487 ps
T121 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3396156888 Jul 28 05:01:35 PM PDT 24 Jul 28 05:01:35 PM PDT 24 26434979 ps
T57 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3233773793 Jul 28 05:01:22 PM PDT 24 Jul 28 05:01:23 PM PDT 24 52767971 ps
T629 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.765930766 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 54467004 ps
T59 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3612227213 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:36 PM PDT 24 449583098 ps
T122 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.3672739159 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:39 PM PDT 24 23324852 ps
T155 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1364808347 Jul 28 05:01:33 PM PDT 24 Jul 28 05:01:34 PM PDT 24 16967567 ps
T70 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4183499084 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:58 PM PDT 24 199923996 ps
T58 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.889358672 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:45 PM PDT 24 88951112 ps
T107 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.850133831 Jul 28 05:01:27 PM PDT 24 Jul 28 05:01:28 PM PDT 24 16670931 ps
T630 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1441592637 Jul 28 05:01:50 PM PDT 24 Jul 28 05:01:51 PM PDT 24 20444970 ps
T71 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.822768646 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 90637971 ps
T631 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.77741702 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 144376480 ps
T123 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2687060313 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:43 PM PDT 24 29564454 ps
T156 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2680936599 Jul 28 05:02:05 PM PDT 24 Jul 28 05:02:05 PM PDT 24 18684443 ps
T124 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2717007102 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:39 PM PDT 24 64782527 ps
T125 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1064675476 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:35 PM PDT 24 18005346 ps
T62 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1597477873 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:57 PM PDT 24 458236564 ps
T108 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3210757106 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 56373956 ps
T126 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.712972531 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 22566754 ps
T99 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.803972369 Jul 28 05:02:01 PM PDT 24 Jul 28 05:02:07 PM PDT 24 269405298 ps
T72 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.218897695 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 86433858 ps
T83 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3127302601 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:43 PM PDT 24 204802069 ps
T632 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3297416829 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:44 PM PDT 24 18801813 ps
T633 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2462403032 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 67166090 ps
T634 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2246792868 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 21844337 ps
T635 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3628586569 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:45 PM PDT 24 36239201 ps
T130 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2703605420 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 29013707 ps
T636 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1010917972 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 29086846 ps
T637 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3036993823 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:31 PM PDT 24 29403777 ps
T638 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3074896976 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:52 PM PDT 24 41721168 ps
T109 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1337561889 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 105838702 ps
T81 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3748610163 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 99511815 ps
T100 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2956351446 Jul 28 05:01:53 PM PDT 24 Jul 28 05:01:54 PM PDT 24 44933399 ps
T639 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.834192316 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:13 PM PDT 24 20407137 ps
T640 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2472036093 Jul 28 05:01:43 PM PDT 24 Jul 28 05:01:44 PM PDT 24 17768142 ps
T641 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.27808902 Jul 28 05:01:36 PM PDT 24 Jul 28 05:01:37 PM PDT 24 19379373 ps
T642 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1197924170 Jul 28 05:01:58 PM PDT 24 Jul 28 05:01:58 PM PDT 24 18172187 ps
T643 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.1520952505 Jul 28 05:02:11 PM PDT 24 Jul 28 05:02:12 PM PDT 24 166011539 ps
T77 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1389283131 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:49 PM PDT 24 556210489 ps
T644 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2203856496 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 89742741 ps
T80 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4216357618 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:32 PM PDT 24 97281779 ps
T645 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.918314177 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:43 PM PDT 24 35133290 ps
T78 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2691434018 Jul 28 05:01:27 PM PDT 24 Jul 28 05:01:29 PM PDT 24 487507674 ps
T82 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2570233199 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:00 PM PDT 24 198034964 ps
T646 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3368924164 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 51254443 ps
T647 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.183790302 Jul 28 05:01:49 PM PDT 24 Jul 28 05:01:49 PM PDT 24 40220863 ps
T648 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3850980484 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:48 PM PDT 24 34045657 ps
T649 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.574851819 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:53 PM PDT 24 26505888 ps
T110 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1453553679 Jul 28 05:01:25 PM PDT 24 Jul 28 05:01:26 PM PDT 24 88158192 ps
T650 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3289950268 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 44730516 ps
T651 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4268327580 Jul 28 05:01:36 PM PDT 24 Jul 28 05:01:37 PM PDT 24 19629652 ps
T652 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1423119040 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:44 PM PDT 24 70122272 ps
T653 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2494749221 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:52 PM PDT 24 16302516 ps
T654 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.4058268300 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:47 PM PDT 24 53370791 ps
T655 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.608198364 Jul 28 05:01:26 PM PDT 24 Jul 28 05:01:27 PM PDT 24 34670129 ps
T111 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1004432110 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:35 PM PDT 24 25828894 ps
T656 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3847777394 Jul 28 05:01:32 PM PDT 24 Jul 28 05:01:33 PM PDT 24 49279024 ps
T657 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.777861323 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 76456513 ps
T658 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3984957841 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:39 PM PDT 24 21272933 ps
T659 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1237641853 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 31192023 ps
T660 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3203407903 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 18622234 ps
T84 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3916994953 Jul 28 05:01:43 PM PDT 24 Jul 28 05:01:50 PM PDT 24 225452364 ps
T661 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1167152336 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 191366846 ps
T662 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1399417905 Jul 28 05:01:42 PM PDT 24 Jul 28 05:01:43 PM PDT 24 25243191 ps
T663 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3527517727 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:37 PM PDT 24 38231391 ps
T664 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2809922556 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 43767790 ps
T665 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3779134459 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:48 PM PDT 24 21005753 ps
T666 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2577961681 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:56 PM PDT 24 18016125 ps
T667 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2521101325 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:53 PM PDT 24 118800635 ps
T668 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3380692374 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 47968391 ps
T669 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.494193220 Jul 28 05:01:30 PM PDT 24 Jul 28 05:01:31 PM PDT 24 222386991 ps
T670 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.606563317 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:40 PM PDT 24 115816822 ps
T671 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.741729408 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:40 PM PDT 24 240873446 ps
T672 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1307652850 Jul 28 05:01:50 PM PDT 24 Jul 28 05:01:51 PM PDT 24 32030149 ps
T673 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.580158265 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:45 PM PDT 24 131949227 ps
T674 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3687559768 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 502251560 ps
T112 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1062681631 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 44892531 ps
T675 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2890317690 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:39 PM PDT 24 153607750 ps
T676 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1233069593 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:53 PM PDT 24 15356092 ps
T677 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1229483796 Jul 28 05:01:59 PM PDT 24 Jul 28 05:01:59 PM PDT 24 19260328 ps
T678 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.753681063 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 17844964 ps
T679 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.7620679 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:42 PM PDT 24 53178392 ps
T85 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2795923638 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 344335569 ps
T680 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4144318599 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 63083018 ps
T681 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.38499074 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:38 PM PDT 24 1229242148 ps
T682 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3415774921 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 68898857 ps
T683 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.65027250 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:53 PM PDT 24 20280605 ps
T684 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1888206521 Jul 28 05:01:34 PM PDT 24 Jul 28 05:01:35 PM PDT 24 58069725 ps
T685 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.372345423 Jul 28 05:01:25 PM PDT 24 Jul 28 05:01:26 PM PDT 24 123395000 ps
T686 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1224887200 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:47 PM PDT 24 271612380 ps
T687 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3324980557 Jul 28 05:01:36 PM PDT 24 Jul 28 05:01:36 PM PDT 24 34440059 ps
T688 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2477898537 Jul 28 05:01:30 PM PDT 24 Jul 28 05:01:32 PM PDT 24 315704865 ps
T689 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1577161465 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 17344017 ps
T690 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2823197796 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:55 PM PDT 24 17668561 ps
T691 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2975397496 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 18448509 ps
T692 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3781818658 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 79056960 ps
T693 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.19295357 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 55713504 ps
T694 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.307517867 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 31113465 ps
T695 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1972094540 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:43 PM PDT 24 239663940 ps
T696 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3790523411 Jul 28 05:01:33 PM PDT 24 Jul 28 05:01:35 PM PDT 24 137818132 ps
T697 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1305114077 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:49 PM PDT 24 66192425 ps
T698 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.776723741 Jul 28 05:01:35 PM PDT 24 Jul 28 05:01:37 PM PDT 24 585531503 ps
T699 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3296996468 Jul 28 05:02:01 PM PDT 24 Jul 28 05:02:01 PM PDT 24 19257581 ps
T700 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1635004739 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:56 PM PDT 24 57763323 ps
T701 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2238180154 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:54 PM PDT 24 19933457 ps
T702 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3448798875 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 19568200 ps
T703 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.535417462 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:45 PM PDT 24 18454861 ps
T704 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1043852489 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:47 PM PDT 24 51170317 ps
T705 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2494873593 Jul 28 05:01:35 PM PDT 24 Jul 28 05:01:36 PM PDT 24 55005986 ps
T706 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2226386247 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 39668783 ps
T707 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.474737510 Jul 28 05:01:57 PM PDT 24 Jul 28 05:01:58 PM PDT 24 20022441 ps
T708 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.919337400 Jul 28 05:01:36 PM PDT 24 Jul 28 05:01:38 PM PDT 24 1954968517 ps
T709 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1604543572 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 111428002 ps
T710 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2898250561 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:48 PM PDT 24 21365597 ps
T711 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3802073690 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:31 PM PDT 24 51236671 ps
T712 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1912005622 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:47 PM PDT 24 40024923 ps
T713 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.908449776 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 21820389 ps
T113 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.21799120 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:39 PM PDT 24 87387142 ps
T714 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2387409397 Jul 28 05:01:37 PM PDT 24 Jul 28 05:01:38 PM PDT 24 240059926 ps
T715 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3771835174 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:32 PM PDT 24 68276330 ps
T716 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2477419074 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 22129943 ps
T114 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3772778678 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 172412223 ps
T717 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.840338066 Jul 28 05:01:43 PM PDT 24 Jul 28 05:01:45 PM PDT 24 443123410 ps
T718 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2244042629 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:52 PM PDT 24 66005360 ps
T719 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.858256476 Jul 28 05:01:42 PM PDT 24 Jul 28 05:01:44 PM PDT 24 185134228 ps
T720 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1268074189 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:54 PM PDT 24 213428350 ps
T115 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.30661164 Jul 28 05:01:36 PM PDT 24 Jul 28 05:01:37 PM PDT 24 798690320 ps
T721 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2720830684 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:40 PM PDT 24 305839456 ps
T722 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2459035724 Jul 28 05:01:50 PM PDT 24 Jul 28 05:01:50 PM PDT 24 51063005 ps
T723 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2601489246 Jul 28 05:01:23 PM PDT 24 Jul 28 05:01:26 PM PDT 24 126933501 ps
T724 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2202171150 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 94815106 ps
T725 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1045387450 Jul 28 05:01:42 PM PDT 24 Jul 28 05:01:43 PM PDT 24 97971629 ps
T726 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2933433604 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:42 PM PDT 24 84788773 ps
T727 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3037088809 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:55 PM PDT 24 20469143 ps
T116 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.357375311 Jul 28 05:01:31 PM PDT 24 Jul 28 05:01:32 PM PDT 24 16933678 ps
T728 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.4026102117 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:46 PM PDT 24 35936079 ps
T729 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1316947567 Jul 28 05:01:38 PM PDT 24 Jul 28 05:01:40 PM PDT 24 103632196 ps
T117 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3094992334 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 17793847 ps
T730 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.815133865 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:04 PM PDT 24 44992595 ps
T731 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.860094123 Jul 28 05:01:39 PM PDT 24 Jul 28 05:01:40 PM PDT 24 19637952 ps
T732 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2258795868 Jul 28 05:01:54 PM PDT 24 Jul 28 05:02:00 PM PDT 24 19837302 ps
T733 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.4241277807 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:47 PM PDT 24 1729597683 ps
T118 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3204162190 Jul 28 05:01:32 PM PDT 24 Jul 28 05:01:33 PM PDT 24 32562497 ps
T734 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2050702971 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:45 PM PDT 24 44050657 ps
T735 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4016403736 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 36072904 ps
T736 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3607073929 Jul 28 05:01:35 PM PDT 24 Jul 28 05:01:36 PM PDT 24 22909024 ps
T737 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.573085555 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:41 PM PDT 24 972930914 ps
T738 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3536129549 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 40373453 ps
T151 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3387382912 Jul 28 05:01:41 PM PDT 24 Jul 28 05:01:43 PM PDT 24 497234091 ps
T739 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.940652869 Jul 28 05:01:40 PM PDT 24 Jul 28 05:01:43 PM PDT 24 77199035 ps

Test location /workspace/coverage/default/48.pwrmgr_smoke.1642531457
Short name T7
Test name
Test status
Simulation time 38619850 ps
CPU time 0.63 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 198564 kb
Host smart-2bab4f6f-8709-4104-a72e-62f2d92e4ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642531457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1642531457
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.2476036190
Short name T8
Test name
Test status
Simulation time 144606735 ps
CPU time 0.86 seconds
Started Jul 28 05:07:53 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 209540 kb
Host smart-ba7d5a79-da01-49df-b773-bc822ec1c7b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476036190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2476036190
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.2588584400
Short name T6
Test name
Test status
Simulation time 49276502 ps
CPU time 0.96 seconds
Started Jul 28 05:07:54 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 200748 kb
Host smart-9eedcb79-a6e5-4a44-a734-fa2e0a104626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588584400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2588584400
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3828712574
Short name T23
Test name
Test status
Simulation time 84967586 ps
CPU time 1.05 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 197756 kb
Host smart-cbd670dc-93d4-4955-8d8f-263d31af07e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828712574 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3828712574
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3131929016
Short name T17
Test name
Test status
Simulation time 400332719 ps
CPU time 1.25 seconds
Started Jul 28 05:07:18 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 216940 kb
Host smart-6726c57a-da10-4239-a77e-cfba4c96308f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131929016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3131929016
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.4174793408
Short name T30
Test name
Test status
Simulation time 46942562 ps
CPU time 0.71 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 201500 kb
Host smart-7cda3c04-0ed3-4493-acc3-0f8c5fde280d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174793408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.4174793408
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2405741542
Short name T20
Test name
Test status
Simulation time 114587037 ps
CPU time 0.63 seconds
Started Jul 28 05:07:57 PM PDT 24
Finished Jul 28 05:07:58 PM PDT 24
Peak memory 198576 kb
Host smart-0554082d-d436-4764-96d0-2c7343cb1f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405741542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2405741542
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.2598772444
Short name T25
Test name
Test status
Simulation time 62974239 ps
CPU time 0.68 seconds
Started Jul 28 05:07:54 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 199148 kb
Host smart-238b229c-8cf0-49ff-97ff-b31abb9eaa3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598772444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.2598772444
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.729039015
Short name T61
Test name
Test status
Simulation time 165158487 ps
CPU time 1.1 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:33 PM PDT 24
Peak memory 195876 kb
Host smart-10e284ed-b248-410e-965d-14b7b95c20a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729039015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
729039015
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3559636632
Short name T65
Test name
Test status
Simulation time 70612255 ps
CPU time 0.99 seconds
Started Jul 28 05:07:13 PM PDT 24
Finished Jul 28 05:07:14 PM PDT 24
Peak memory 199556 kb
Host smart-1adc31f1-1ba6-401a-91ea-6861e2cbfe93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559636632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3559636632
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.1046354442
Short name T180
Test name
Test status
Simulation time 306108395 ps
CPU time 2.45 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 200916 kb
Host smart-1b5c0e01-3206-4a43-8a98-b4ffebaccd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046354442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.1046354442
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.534250955
Short name T147
Test name
Test status
Simulation time 297234343 ps
CPU time 0.71 seconds
Started Jul 28 05:07:41 PM PDT 24
Finished Jul 28 05:07:41 PM PDT 24
Peak memory 198456 kb
Host smart-fb495b29-8f8d-4176-8fe3-9dbbb9c2fe4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534250955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.534250955
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4185142
Short name T75
Test name
Test status
Simulation time 36789244 ps
CPU time 0.61 seconds
Started Jul 28 05:01:42 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195456 kb
Host smart-ec704441-7fbb-48f1-8dd7-0e5ca0461ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.4185142
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3577992417
Short name T13
Test name
Test status
Simulation time 484156103 ps
CPU time 0.98 seconds
Started Jul 28 05:07:22 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 198124 kb
Host smart-63577ad0-492b-4398-948a-fec1ea68e26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577992417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3577992417
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.377348994
Short name T141
Test name
Test status
Simulation time 79591259 ps
CPU time 0.67 seconds
Started Jul 28 05:07:45 PM PDT 24
Finished Jul 28 05:07:46 PM PDT 24
Peak memory 199168 kb
Host smart-605f70b1-684c-4c7b-b035-0b9596e19738
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377348994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.377348994
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1004432110
Short name T111
Test name
Test status
Simulation time 25828894 ps
CPU time 0.91 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 195564 kb
Host smart-534f1c95-683e-4538-a402-c739d772c15f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004432110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1
004432110
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.2351060038
Short name T50
Test name
Test status
Simulation time 75996066 ps
CPU time 0.66 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 198484 kb
Host smart-5115414c-21f1-44d9-98ed-76b57c0fe581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351060038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.2351060038
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2243351770
Short name T96
Test name
Test status
Simulation time 135627763 ps
CPU time 0.65 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 201316 kb
Host smart-6778f15a-fabd-4f57-9c75-442e27cc48a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243351770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2243351770
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2026650647
Short name T64
Test name
Test status
Simulation time 54947951 ps
CPU time 0.76 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 198724 kb
Host smart-de8cddd6-8428-4db2-a8ff-fa334fd4ca11
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026650647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2026650647
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3933397988
Short name T90
Test name
Test status
Simulation time 119129075 ps
CPU time 0.66 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 201368 kb
Host smart-bd2d78b2-11fe-4c06-94fa-27bd54a4f93c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933397988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3933397988
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3127302601
Short name T83
Test name
Test status
Simulation time 204802069 ps
CPU time 1.73 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 201124 kb
Host smart-c243e30f-2545-4a50-886c-d2023f98416e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127302601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.3127302601
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2040333531
Short name T9
Test name
Test status
Simulation time 62484413 ps
CPU time 0.77 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 199064 kb
Host smart-4aeb1f05-adb1-4a63-854f-c10eb7a582e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040333531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2040333531
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.462678748
Short name T599
Test name
Test status
Simulation time 60948717 ps
CPU time 0.83 seconds
Started Jul 28 05:07:55 PM PDT 24
Finished Jul 28 05:07:56 PM PDT 24
Peak memory 199112 kb
Host smart-4544ffa7-e7c6-498d-ab31-25ec2b4ed918
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462678748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disa
ble_rom_integrity_check.462678748
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.3648693089
Short name T177
Test name
Test status
Simulation time 50536837 ps
CPU time 0.68 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 198204 kb
Host smart-1478c534-c81d-458a-849e-80053ce17541
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648693089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.3648693089
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1839385492
Short name T63
Test name
Test status
Simulation time 103432532 ps
CPU time 0.64 seconds
Started Jul 28 05:08:16 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 198628 kb
Host smart-f85463c0-f38b-4d45-a953-ce7bead20f9b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839385492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.1839385492
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1997133960
Short name T88
Test name
Test status
Simulation time 55352633 ps
CPU time 0.67 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 201428 kb
Host smart-40555fd9-3d7a-4f22-a176-26b94ec66c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997133960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.1997133960
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.1903177057
Short name T93
Test name
Test status
Simulation time 44253475 ps
CPU time 0.66 seconds
Started Jul 28 05:06:55 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 198640 kb
Host smart-bcfd565e-d749-4bea-bd78-087a71076c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903177057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1903177057
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.394158498
Short name T192
Test name
Test status
Simulation time 43564749 ps
CPU time 0.73 seconds
Started Jul 28 05:07:26 PM PDT 24
Finished Jul 28 05:07:27 PM PDT 24
Peak memory 201352 kb
Host smart-cbe35c4a-69da-4d14-898a-d433792371cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394158498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.394158498
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.447962790
Short name T52
Test name
Test status
Simulation time 29501314 ps
CPU time 0.68 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 198552 kb
Host smart-18c6d9c2-6d84-41cb-8355-4a5592e7a380
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447962790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.447962790
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.494193220
Short name T669
Test name
Test status
Simulation time 222386991 ps
CPU time 1.16 seconds
Started Jul 28 05:01:30 PM PDT 24
Finished Jul 28 05:01:31 PM PDT 24
Peak memory 195860 kb
Host smart-ff46563f-49d6-407e-abe6-07a2aa5c50d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494193220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.494193220
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.4132438810
Short name T174
Test name
Test status
Simulation time 47911284 ps
CPU time 0.77 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 201508 kb
Host smart-6c5fc925-83dc-4df2-823e-9cf13c7e18f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132438810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.4132438810
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3699018077
Short name T56
Test name
Test status
Simulation time 66120096 ps
CPU time 0.72 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198512 kb
Host smart-7038dbdc-1c8b-4314-93a9-a19292dc51c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699018077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3699018077
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1622756700
Short name T167
Test name
Test status
Simulation time 42527777 ps
CPU time 0.72 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 201428 kb
Host smart-d5bb5377-4696-4ebb-9cc5-106ea9480f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622756700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1622756700
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.4105122615
Short name T208
Test name
Test status
Simulation time 49143328 ps
CPU time 0.78 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 199156 kb
Host smart-9d4b2f9c-c23f-4536-97cc-15837320af65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105122615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.4105122615
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.3213405576
Short name T51
Test name
Test status
Simulation time 68362273 ps
CPU time 0.66 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 198616 kb
Host smart-ff3a4453-bef3-4653-b1b2-0b87dd287949
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213405576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.3213405576
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3547877180
Short name T187
Test name
Test status
Simulation time 46354755 ps
CPU time 0.7 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 201320 kb
Host smart-870b0f77-45b8-4dac-8e3b-e45a747bb137
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547877180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3547877180
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3319636582
Short name T188
Test name
Test status
Simulation time 52556091 ps
CPU time 0.69 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 201404 kb
Host smart-3817d165-ba9f-4f71-989b-32ab1d79fc65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319636582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3319636582
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2742154622
Short name T119
Test name
Test status
Simulation time 30632074 ps
CPU time 0.63 seconds
Started Jul 28 05:01:30 PM PDT 24
Finished Jul 28 05:01:31 PM PDT 24
Peak memory 198800 kb
Host smart-f3a9e964-af1c-4ba3-b228-7280c7ccaaf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742154622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2742154622
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3036993823
Short name T637
Test name
Test status
Simulation time 29403777 ps
CPU time 0.59 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:31 PM PDT 24
Peak memory 195524 kb
Host smart-b0d566b1-3bb1-44bc-aec9-f49b6a7c54cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036993823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3036993823
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.677578048
Short name T503
Test name
Test status
Simulation time 71485976 ps
CPU time 0.88 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:06:58 PM PDT 24
Peak memory 198580 kb
Host smart-0e3e9632-976e-4985-a36f-b123d12a8eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677578048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.677578048
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.4245295762
Short name T214
Test name
Test status
Simulation time 71677802 ps
CPU time 0.73 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 198304 kb
Host smart-d6331d0b-cf4f-4015-aa64-dfd643b4c898
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245295762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.4245295762
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2140192848
Short name T200
Test name
Test status
Simulation time 41467391 ps
CPU time 0.74 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 201380 kb
Host smart-e55b948e-bf77-4468-a060-f0a518b2b761
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140192848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2140192848
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1604543572
Short name T709
Test name
Test status
Simulation time 111428002 ps
CPU time 1.12 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 201052 kb
Host smart-20432544-7bdd-4da4-86c3-5d54ce36863c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604543572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1604543572
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2795923638
Short name T85
Test name
Test status
Simulation time 344335569 ps
CPU time 1.5 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 200940 kb
Host smart-77c3aaf0-801f-4ebd-9aa3-0cffa6dfd020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795923638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2795923638
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.3547502001
Short name T16
Test name
Test status
Simulation time 63317999 ps
CPU time 0.7 seconds
Started Jul 28 05:07:41 PM PDT 24
Finished Jul 28 05:07:41 PM PDT 24
Peak memory 198128 kb
Host smart-53077bc8-85bc-4aa5-a695-0f294c4d495f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547502001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3547502001
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.919337400
Short name T708
Test name
Test status
Simulation time 1954968517 ps
CPU time 2.08 seconds
Started Jul 28 05:01:36 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 195756 kb
Host smart-4392c014-d1c6-4188-bf99-2e9262b15fc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919337400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.919337400
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3204162190
Short name T118
Test name
Test status
Simulation time 32562497 ps
CPU time 0.68 seconds
Started Jul 28 05:01:32 PM PDT 24
Finished Jul 28 05:01:33 PM PDT 24
Peak memory 195520 kb
Host smart-eb8b3fde-0c21-4ca2-9b25-af4daca0da62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204162190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
204162190
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4216357618
Short name T80
Test name
Test status
Simulation time 97281779 ps
CPU time 1.18 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:32 PM PDT 24
Peak memory 199024 kb
Host smart-3bbbb178-75b6-408f-ac1d-3c1e61b5f68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216357618 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.4216357618
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2717007102
Short name T124
Test name
Test status
Simulation time 64782527 ps
CPU time 0.87 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:39 PM PDT 24
Peak memory 195816 kb
Host smart-c408b519-0b32-4866-9f04-991ee51dbfd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717007102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2717007102
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1453553679
Short name T110
Test name
Test status
Simulation time 88158192 ps
CPU time 0.79 seconds
Started Jul 28 05:01:25 PM PDT 24
Finished Jul 28 05:01:26 PM PDT 24
Peak memory 195492 kb
Host smart-c412df6e-f45b-4f5d-b1ec-999aeee89560
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453553679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
453553679
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.38499074
Short name T681
Test name
Test status
Simulation time 1229242148 ps
CPU time 3.4 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 195692 kb
Host smart-b5ea5c2d-2d7c-4340-809f-6c0401232350
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.38499074
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2703605420
Short name T130
Test name
Test status
Simulation time 29013707 ps
CPU time 0.63 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 195516 kb
Host smart-0e81a63c-b087-4026-b451-9f23ca045979
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703605420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
703605420
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3233773793
Short name T57
Test name
Test status
Simulation time 52767971 ps
CPU time 0.86 seconds
Started Jul 28 05:01:22 PM PDT 24
Finished Jul 28 05:01:23 PM PDT 24
Peak memory 195620 kb
Host smart-f7e42db3-4efd-4830-8f14-e501c4275b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233773793 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3233773793
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.357375311
Short name T116
Test name
Test status
Simulation time 16933678 ps
CPU time 0.66 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:32 PM PDT 24
Peak memory 195568 kb
Host smart-736086dd-f4c8-44ad-b9eb-37943dc9ebca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357375311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.357375311
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3324980557
Short name T687
Test name
Test status
Simulation time 34440059 ps
CPU time 0.62 seconds
Started Jul 28 05:01:36 PM PDT 24
Finished Jul 28 05:01:36 PM PDT 24
Peak memory 195504 kb
Host smart-f13ca13d-2ef0-424f-bdf8-bdede5be84a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324980557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3324980557
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.27808902
Short name T641
Test name
Test status
Simulation time 19379373 ps
CPU time 0.7 seconds
Started Jul 28 05:01:36 PM PDT 24
Finished Jul 28 05:01:37 PM PDT 24
Peak memory 197828 kb
Host smart-4fb27d20-bf7f-4d1a-bf9f-a37c492816eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same
_csr_outstanding.27808902
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2601489246
Short name T723
Test name
Test status
Simulation time 126933501 ps
CPU time 2.62 seconds
Started Jul 28 05:01:23 PM PDT 24
Finished Jul 28 05:01:26 PM PDT 24
Peak memory 197952 kb
Host smart-820b0528-3512-4e7b-88a0-d9b90f5ed981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601489246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2601489246
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.372345423
Short name T685
Test name
Test status
Simulation time 123395000 ps
CPU time 1.05 seconds
Started Jul 28 05:01:25 PM PDT 24
Finished Jul 28 05:01:26 PM PDT 24
Peak memory 200840 kb
Host smart-964919e7-89cd-40e6-b5b8-19956c6e52a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372345423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.
372345423
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.889358672
Short name T58
Test name
Test status
Simulation time 88951112 ps
CPU time 1.1 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 201196 kb
Host smart-17c59b94-1434-4a33-8ad2-620153512a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889358672 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.889358672
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1010917972
Short name T636
Test name
Test status
Simulation time 29086846 ps
CPU time 0.61 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 195652 kb
Host smart-4caf5ccd-bbb7-4d49-bd26-575eb2e5ee15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010917972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1010917972
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.765930766
Short name T629
Test name
Test status
Simulation time 54467004 ps
CPU time 0.62 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195564 kb
Host smart-39e20ee6-da9b-4c9c-86f2-4a2496ba8b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765930766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.765930766
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1064675476
Short name T125
Test name
Test status
Simulation time 18005346 ps
CPU time 0.65 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 195544 kb
Host smart-8ee0bc89-f131-4f11-9fb6-8489d4bfdb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064675476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1064675476
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2720830684
Short name T721
Test name
Test status
Simulation time 305839456 ps
CPU time 1.59 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 196868 kb
Host smart-569dc1fa-c5e1-4452-91ea-d30bfdc1c222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720830684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2720830684
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.218897695
Short name T72
Test name
Test status
Simulation time 86433858 ps
CPU time 0.93 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 196732 kb
Host smart-d6292ed2-7242-4257-bbe0-f7bdafae25ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218897695 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.218897695
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3074896976
Short name T638
Test name
Test status
Simulation time 41721168 ps
CPU time 0.66 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 197704 kb
Host smart-3d904a9a-fcb3-4d13-a0a8-f15862941397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074896976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3074896976
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3296562076
Short name T154
Test name
Test status
Simulation time 45213963 ps
CPU time 0.58 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 195504 kb
Host smart-7e8fa718-5899-4c61-ad9e-98ab3236fe13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296562076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3296562076
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3396156888
Short name T121
Test name
Test status
Simulation time 26434979 ps
CPU time 0.7 seconds
Started Jul 28 05:01:35 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 195608 kb
Host smart-e4fb4b0b-66d8-4072-b11a-41a00d873839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396156888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3396156888
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3916994953
Short name T84
Test name
Test status
Simulation time 225452364 ps
CPU time 2.37 seconds
Started Jul 28 05:01:43 PM PDT 24
Finished Jul 28 05:01:50 PM PDT 24
Peak memory 198324 kb
Host smart-93485cfb-9c35-4000-9d5b-b3cb17a39de0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916994953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3916994953
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1389283131
Short name T77
Test name
Test status
Simulation time 556210489 ps
CPU time 1.56 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 200968 kb
Host smart-8dd35143-06eb-48f0-a7c7-d6a6d62a2fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389283131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1389283131
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3781818658
Short name T692
Test name
Test status
Simulation time 79056960 ps
CPU time 0.96 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195724 kb
Host smart-5b75ce74-11b1-4175-a131-3e17a2742f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781818658 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3781818658
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1062681631
Short name T112
Test name
Test status
Simulation time 44892531 ps
CPU time 0.64 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 195652 kb
Host smart-9f6698f6-aa82-4d4e-8680-23b7c42d1c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062681631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1062681631
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3439749818
Short name T157
Test name
Test status
Simulation time 25077309 ps
CPU time 0.62 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 195484 kb
Host smart-0991a9bf-dd15-4366-8d21-c4b1370bd463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439749818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3439749818
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2244042629
Short name T718
Test name
Test status
Simulation time 66005360 ps
CPU time 0.78 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 198896 kb
Host smart-f67abc97-7d97-4817-98e5-7a37353b597a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244042629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2244042629
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.4241277807
Short name T733
Test name
Test status
Simulation time 1729597683 ps
CPU time 2.09 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 196868 kb
Host smart-93a4b69a-9523-4da8-9549-9bd5450ca2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241277807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.4241277807
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1387025989
Short name T21
Test name
Test status
Simulation time 145769108 ps
CPU time 1.07 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 201100 kb
Host smart-99ab6e0d-317a-4ae8-a1f4-767b6c710b84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387025989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1387025989
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.183790302
Short name T647
Test name
Test status
Simulation time 40220863 ps
CPU time 0.75 seconds
Started Jul 28 05:01:49 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 195732 kb
Host smart-4e7a0053-de44-45ac-8721-8d51d94a0c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183790302 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.183790302
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3297416829
Short name T632
Test name
Test status
Simulation time 18801813 ps
CPU time 0.61 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:44 PM PDT 24
Peak memory 197796 kb
Host smart-8664135a-ef70-4dbb-bf56-81a8c33c92f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297416829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3297416829
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2494749221
Short name T653
Test name
Test status
Simulation time 16302516 ps
CPU time 0.62 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 195476 kb
Host smart-b9347874-ac3c-4de3-a24d-1cc68443b44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494749221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2494749221
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3289950268
Short name T650
Test name
Test status
Simulation time 44730516 ps
CPU time 0.74 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 195732 kb
Host smart-710fca5e-28aa-4d1c-86c1-c39c1dc05c5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289950268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3289950268
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3748610163
Short name T81
Test name
Test status
Simulation time 99511815 ps
CPU time 1.74 seconds
Started Jul 28 05:01:48 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 197964 kb
Host smart-e9b9cb8c-85cd-401c-97a3-36fe7f365366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748610163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3748610163
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1167152336
Short name T661
Test name
Test status
Simulation time 191366846 ps
CPU time 0.99 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195912 kb
Host smart-516e5c0b-0c64-4fe6-9616-014081ecbf5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167152336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1167152336
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.777861323
Short name T657
Test name
Test status
Simulation time 76456513 ps
CPU time 1 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 196692 kb
Host smart-4c7a195d-592b-40e9-a5c7-aa0f72d23386
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777861323 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.777861323
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3527517727
Short name T663
Test name
Test status
Simulation time 38231391 ps
CPU time 0.63 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:37 PM PDT 24
Peak memory 197692 kb
Host smart-daff8816-c0f2-4679-9eb2-b4bb486cfabd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527517727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3527517727
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1441592637
Short name T630
Test name
Test status
Simulation time 20444970 ps
CPU time 0.59 seconds
Started Jul 28 05:01:50 PM PDT 24
Finished Jul 28 05:01:51 PM PDT 24
Peak memory 195488 kb
Host smart-826ca3a5-ed41-4267-8c09-5e960b917640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441592637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1441592637
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1399417905
Short name T662
Test name
Test status
Simulation time 25243191 ps
CPU time 0.74 seconds
Started Jul 28 05:01:42 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195504 kb
Host smart-157166ac-4f7f-45de-a8f1-a9ffb254fdbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399417905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1399417905
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3850980484
Short name T648
Test name
Test status
Simulation time 34045657 ps
CPU time 1.58 seconds
Started Jul 28 05:01:46 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 196868 kb
Host smart-bb187abf-b423-41a8-b028-139553bd83ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850980484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3850980484
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.573085555
Short name T737
Test name
Test status
Simulation time 972930914 ps
CPU time 1.09 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195880 kb
Host smart-3d294e70-8863-4277-a15b-793b417f9ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573085555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.573085555
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3368924164
Short name T646
Test name
Test status
Simulation time 51254443 ps
CPU time 0.93 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195832 kb
Host smart-604c4f64-1c1a-4812-b778-5e9689b0d056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368924164 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3368924164
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.574851819
Short name T649
Test name
Test status
Simulation time 26505888 ps
CPU time 0.69 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:53 PM PDT 24
Peak memory 199028 kb
Host smart-df1d9a34-5313-4edc-bd3b-47cb8f292eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574851819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.574851819
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2823197796
Short name T690
Test name
Test status
Simulation time 17668561 ps
CPU time 0.61 seconds
Started Jul 28 05:01:55 PM PDT 24
Finished Jul 28 05:01:55 PM PDT 24
Peak memory 195484 kb
Host smart-6fb0f23f-06d3-437f-9434-7ccddafbd809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823197796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2823197796
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2521101325
Short name T667
Test name
Test status
Simulation time 118800635 ps
CPU time 0.82 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:53 PM PDT 24
Peak memory 198884 kb
Host smart-0f314ba2-148b-43ab-a15e-27c462185e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521101325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.2521101325
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.4026102117
Short name T728
Test name
Test status
Simulation time 35936079 ps
CPU time 1.58 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 196844 kb
Host smart-882207db-4cb3-4edf-ad27-b322a1dd2b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026102117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.4026102117
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1045387450
Short name T725
Test name
Test status
Simulation time 97971629 ps
CPU time 1.12 seconds
Started Jul 28 05:01:42 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195796 kb
Host smart-7db09672-4e68-46a5-ad28-255de926c989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045387450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1045387450
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2933433604
Short name T726
Test name
Test status
Simulation time 84788773 ps
CPU time 0.79 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 195788 kb
Host smart-25edaf83-c422-4f6e-8190-3ebe20c982d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933433604 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.2933433604
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3094992334
Short name T117
Test name
Test status
Simulation time 17793847 ps
CPU time 0.65 seconds
Started Jul 28 05:01:48 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 196736 kb
Host smart-37f5b8a5-92ec-4411-abb0-7fcdf9010626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094992334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3094992334
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.474737510
Short name T707
Test name
Test status
Simulation time 20022441 ps
CPU time 0.61 seconds
Started Jul 28 05:01:57 PM PDT 24
Finished Jul 28 05:01:58 PM PDT 24
Peak memory 195532 kb
Host smart-60f7edf8-59b1-440d-b581-8353f3d8e8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474737510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.474737510
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3415774921
Short name T682
Test name
Test status
Simulation time 68898857 ps
CPU time 0.85 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 195552 kb
Host smart-6d08e92e-f9b4-4879-9e19-521842425925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415774921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3415774921
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1597477873
Short name T62
Test name
Test status
Simulation time 458236564 ps
CPU time 2.25 seconds
Started Jul 28 05:01:55 PM PDT 24
Finished Jul 28 05:01:57 PM PDT 24
Peak memory 196980 kb
Host smart-0d9a781e-f184-44e1-8aae-8671d0184f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597477873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1597477873
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.803972369
Short name T99
Test name
Test status
Simulation time 269405298 ps
CPU time 1.55 seconds
Started Jul 28 05:02:01 PM PDT 24
Finished Jul 28 05:02:07 PM PDT 24
Peak memory 195904 kb
Host smart-c194bb00-0efc-49ad-a095-d9e600458e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803972369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.803972369
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1912005622
Short name T712
Test name
Test status
Simulation time 40024923 ps
CPU time 1.01 seconds
Started Jul 28 05:01:46 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 195748 kb
Host smart-4130e25f-5d9d-4d9f-884e-4f3d95761b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912005622 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1912005622
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1043852489
Short name T704
Test name
Test status
Simulation time 51170317 ps
CPU time 0.65 seconds
Started Jul 28 05:01:46 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 195660 kb
Host smart-2eadb3ac-1b27-45fc-9992-86ba8df570c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043852489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1043852489
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.19295357
Short name T693
Test name
Test status
Simulation time 55713504 ps
CPU time 0.6 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195540 kb
Host smart-082ede8b-758a-4d9f-816c-0f07ed3c66a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.19295357
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.918314177
Short name T645
Test name
Test status
Simulation time 35133290 ps
CPU time 0.87 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 198880 kb
Host smart-66d096f8-1334-4c96-80e3-10513ff55704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918314177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.918314177
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1224887200
Short name T686
Test name
Test status
Simulation time 271612380 ps
CPU time 2.52 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 195980 kb
Host smart-2d40e2b2-1663-41e6-94f0-521f155d7e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224887200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1224887200
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4183499084
Short name T70
Test name
Test status
Simulation time 199923996 ps
CPU time 1.72 seconds
Started Jul 28 05:01:56 PM PDT 24
Finished Jul 28 05:01:58 PM PDT 24
Peak memory 201088 kb
Host smart-abba8142-68de-4c74-ad02-21b19063e2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183499084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.4183499084
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.580158265
Short name T673
Test name
Test status
Simulation time 131949227 ps
CPU time 1.14 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 198160 kb
Host smart-d9b667e5-93a0-47ae-9f1f-25f244a5565a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580158265 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.580158265
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3448798875
Short name T702
Test name
Test status
Simulation time 19568200 ps
CPU time 0.66 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 197704 kb
Host smart-cf15fa21-2a0b-4a4e-9f53-ecc6e157e8c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448798875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3448798875
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4268327580
Short name T651
Test name
Test status
Simulation time 19629652 ps
CPU time 0.67 seconds
Started Jul 28 05:01:36 PM PDT 24
Finished Jul 28 05:01:37 PM PDT 24
Peak memory 195476 kb
Host smart-977630d6-71aa-4863-b364-e2d8616eb669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268327580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.4268327580
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1635004739
Short name T700
Test name
Test status
Simulation time 57763323 ps
CPU time 0.69 seconds
Started Jul 28 05:01:56 PM PDT 24
Finished Jul 28 05:01:56 PM PDT 24
Peak memory 197808 kb
Host smart-b7013369-806b-496b-89c5-f702da339804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635004739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.1635004739
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4016403736
Short name T735
Test name
Test status
Simulation time 36072904 ps
CPU time 1.57 seconds
Started Jul 28 05:01:48 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 197876 kb
Host smart-23c18489-82f5-4ca8-bb67-d383c5d3d06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016403736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.4016403736
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.396756655
Short name T22
Test name
Test status
Simulation time 103299210 ps
CPU time 1.34 seconds
Started Jul 28 05:01:42 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 200596 kb
Host smart-5222661f-cc20-4ea9-b58a-5e49259e84f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396756655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.396756655
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2956351446
Short name T100
Test name
Test status
Simulation time 44933399 ps
CPU time 0.91 seconds
Started Jul 28 05:01:53 PM PDT 24
Finished Jul 28 05:01:54 PM PDT 24
Peak memory 195732 kb
Host smart-6206b52c-0879-4c80-a004-968cf2987a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956351446 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2956351446
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.65027250
Short name T683
Test name
Test status
Simulation time 20280605 ps
CPU time 0.69 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:53 PM PDT 24
Peak memory 197964 kb
Host smart-3d159518-c8fb-4297-9ec2-d5b4a38bff71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65027250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.65027250
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2050702971
Short name T734
Test name
Test status
Simulation time 44050657 ps
CPU time 0.59 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 195564 kb
Host smart-73a7220e-57b0-46b8-8fb7-54ce675d5cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050702971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.2050702971
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2687060313
Short name T123
Test name
Test status
Simulation time 29564454 ps
CPU time 0.77 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195568 kb
Host smart-bd4c5b22-03a0-4e5a-80e2-ff92a40b4d07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687060313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.2687060313
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2570233199
Short name T82
Test name
Test status
Simulation time 198034964 ps
CPU time 2.58 seconds
Started Jul 28 05:01:57 PM PDT 24
Finished Jul 28 05:02:00 PM PDT 24
Peak memory 197072 kb
Host smart-22755377-a332-4187-a060-f8ea6e79002c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570233199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2570233199
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.858256476
Short name T719
Test name
Test status
Simulation time 185134228 ps
CPU time 1.62 seconds
Started Jul 28 05:01:42 PM PDT 24
Finished Jul 28 05:01:44 PM PDT 24
Peak memory 195940 kb
Host smart-e7d7a548-b4d5-4a08-8d43-a2597a9ad802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858256476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err
.858256476
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.30661164
Short name T115
Test name
Test status
Simulation time 798690320 ps
CPU time 0.98 seconds
Started Jul 28 05:01:36 PM PDT 24
Finished Jul 28 05:01:37 PM PDT 24
Peak memory 198948 kb
Host smart-6e6f690d-bb5b-4938-ba47-b368ce2e3470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30661164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.30661164
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.940652869
Short name T739
Test name
Test status
Simulation time 77199035 ps
CPU time 2.92 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 201060 kb
Host smart-7b585a14-7d6b-494a-8d0b-3e5c9e02bd1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940652869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.940652869
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1529448661
Short name T79
Test name
Test status
Simulation time 53123313 ps
CPU time 0.66 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 198844 kb
Host smart-cb744a28-94a5-49b8-a7c4-917f2aab7571
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529448661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
529448661
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3802073690
Short name T711
Test name
Test status
Simulation time 51236671 ps
CPU time 0.71 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:31 PM PDT 24
Peak memory 195732 kb
Host smart-13af846e-607b-4843-8bd4-b775d10efd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802073690 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.3802073690
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.21799120
Short name T113
Test name
Test status
Simulation time 87387142 ps
CPU time 0.66 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:39 PM PDT 24
Peak memory 195580 kb
Host smart-d767b2e3-b830-4f10-9188-56f05bf41ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.21799120
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1364808347
Short name T155
Test name
Test status
Simulation time 16967567 ps
CPU time 0.59 seconds
Started Jul 28 05:01:33 PM PDT 24
Finished Jul 28 05:01:34 PM PDT 24
Peak memory 195544 kb
Host smart-70eb2c69-d479-4d44-9a4d-10b9792d78e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364808347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1364808347
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3771835174
Short name T715
Test name
Test status
Simulation time 68276330 ps
CPU time 0.88 seconds
Started Jul 28 05:01:31 PM PDT 24
Finished Jul 28 05:01:32 PM PDT 24
Peak memory 195612 kb
Host smart-c307bb19-8e87-47a8-a1c6-d4c4ad3370be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771835174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3771835174
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3790523411
Short name T696
Test name
Test status
Simulation time 137818132 ps
CPU time 2.66 seconds
Started Jul 28 05:01:33 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 196900 kb
Host smart-36bee0c5-5655-4cf9-a43f-1210cf975bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790523411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3790523411
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.840338066
Short name T717
Test name
Test status
Simulation time 443123410 ps
CPU time 1.51 seconds
Started Jul 28 05:01:43 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 201172 kb
Host smart-4d974f25-9133-48bf-975a-e2c8ae3a87ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840338066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
840338066
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.535417462
Short name T703
Test name
Test status
Simulation time 18454861 ps
CPU time 0.59 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 195540 kb
Host smart-3992318d-af4d-4584-aa80-110c339cc985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535417462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.535417462
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4142355949
Short name T628
Test name
Test status
Simulation time 18185280 ps
CPU time 0.61 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195600 kb
Host smart-51ffe201-da98-4172-99d9-15323bdce429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142355949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.4142355949
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2600351908
Short name T73
Test name
Test status
Simulation time 19546031 ps
CPU time 0.59 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 195472 kb
Host smart-09a14ba3-d2e4-469b-8d58-1a703b630132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600351908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2600351908
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3536129549
Short name T738
Test name
Test status
Simulation time 40373453 ps
CPU time 0.59 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195584 kb
Host smart-e476dd4a-045e-4050-9dc7-789e5ae927f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536129549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3536129549
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1307652850
Short name T672
Test name
Test status
Simulation time 32030149 ps
CPU time 0.63 seconds
Started Jul 28 05:01:50 PM PDT 24
Finished Jul 28 05:01:51 PM PDT 24
Peak memory 195484 kb
Host smart-9867df52-94ae-4274-a358-84d48671e57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307652850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1307652850
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1197924170
Short name T642
Test name
Test status
Simulation time 18172187 ps
CPU time 0.61 seconds
Started Jul 28 05:01:58 PM PDT 24
Finished Jul 28 05:01:58 PM PDT 24
Peak memory 195484 kb
Host smart-ecaf8331-87d5-4dd2-930e-7219b5392b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197924170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1197924170
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1233069593
Short name T676
Test name
Test status
Simulation time 15356092 ps
CPU time 0.61 seconds
Started Jul 28 05:01:52 PM PDT 24
Finished Jul 28 05:01:53 PM PDT 24
Peak memory 195520 kb
Host smart-6fc0f486-7036-4a55-9478-2094809f60f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233069593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1233069593
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2809922556
Short name T664
Test name
Test status
Simulation time 43767790 ps
CPU time 0.6 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 195564 kb
Host smart-72a1f0a5-5a2a-4e78-9878-3f7c5f07f648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809922556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2809922556
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2258795868
Short name T732
Test name
Test status
Simulation time 19837302 ps
CPU time 0.62 seconds
Started Jul 28 05:01:54 PM PDT 24
Finished Jul 28 05:02:00 PM PDT 24
Peak memory 195476 kb
Host smart-359a6a4a-6785-44c2-8bf6-bc36ae7e883e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258795868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2258795868
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2459035724
Short name T722
Test name
Test status
Simulation time 51063005 ps
CPU time 0.59 seconds
Started Jul 28 05:01:50 PM PDT 24
Finished Jul 28 05:01:50 PM PDT 24
Peak memory 195496 kb
Host smart-741f02fb-4779-4bb7-8ad7-71cad6f5c908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459035724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2459035724
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1337561889
Short name T109
Test name
Test status
Simulation time 105838702 ps
CPU time 0.77 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 197852 kb
Host smart-2fc8ffb8-05e5-42e3-8453-b9ff59a530dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337561889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1
337561889
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1972094540
Short name T695
Test name
Test status
Simulation time 239663940 ps
CPU time 2.06 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195700 kb
Host smart-d732f7ce-301e-4000-9975-8f64301482c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972094540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
972094540
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.608198364
Short name T655
Test name
Test status
Simulation time 34670129 ps
CPU time 0.69 seconds
Started Jul 28 05:01:26 PM PDT 24
Finished Jul 28 05:01:27 PM PDT 24
Peak memory 198004 kb
Host smart-e861105f-671e-43eb-a267-61f3cddba8e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608198364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.608198364
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.822768646
Short name T71
Test name
Test status
Simulation time 90637971 ps
CPU time 0.81 seconds
Started Jul 28 05:01:48 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 195704 kb
Host smart-922e9472-24a8-48be-80de-1de6ee314759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822768646 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.822768646
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.850133831
Short name T107
Test name
Test status
Simulation time 16670931 ps
CPU time 0.66 seconds
Started Jul 28 05:01:27 PM PDT 24
Finished Jul 28 05:01:28 PM PDT 24
Peak memory 198776 kb
Host smart-a476b3bf-c06e-45fd-9bda-ce6bc6037e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850133831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.850133831
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3607073929
Short name T736
Test name
Test status
Simulation time 22909024 ps
CPU time 0.61 seconds
Started Jul 28 05:01:35 PM PDT 24
Finished Jul 28 05:01:36 PM PDT 24
Peak memory 195496 kb
Host smart-3d373ce8-0dee-43b2-9651-6834ed57382c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607073929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3607073929
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3380692374
Short name T668
Test name
Test status
Simulation time 47968391 ps
CPU time 0.7 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 197552 kb
Host smart-bbde52a5-761b-44aa-b525-9b5cd34f525c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380692374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3380692374
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.606563317
Short name T670
Test name
Test status
Simulation time 115816822 ps
CPU time 1.4 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 195940 kb
Host smart-6bf41d07-87e9-44d8-ad61-c0cbab078b98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606563317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.606563317
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3387382912
Short name T151
Test name
Test status
Simulation time 497234091 ps
CPU time 1.44 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:43 PM PDT 24
Peak memory 195832 kb
Host smart-ede69801-94f8-47d8-afbf-ea8a8482ff2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387382912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3387382912
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2898250561
Short name T710
Test name
Test status
Simulation time 21365597 ps
CPU time 0.6 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195452 kb
Host smart-b9031cd1-8c6b-4074-9ae6-719837fb4336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898250561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.2898250561
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2462403032
Short name T633
Test name
Test status
Simulation time 67166090 ps
CPU time 0.59 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195544 kb
Host smart-e2f49e7d-c0fa-4599-bbd3-b54b568ec1c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462403032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2462403032
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.307517867
Short name T694
Test name
Test status
Simulation time 31113465 ps
CPU time 0.62 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 195584 kb
Host smart-4caaffc1-5e6c-4e8f-aa0f-65d32398fe6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307517867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.307517867
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.1520952505
Short name T643
Test name
Test status
Simulation time 166011539 ps
CPU time 0.6 seconds
Started Jul 28 05:02:11 PM PDT 24
Finished Jul 28 05:02:12 PM PDT 24
Peak memory 195524 kb
Host smart-a52cc291-d772-451c-8e1b-3560aff95774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520952505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.1520952505
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2472036093
Short name T640
Test name
Test status
Simulation time 17768142 ps
CPU time 0.61 seconds
Started Jul 28 05:01:43 PM PDT 24
Finished Jul 28 05:01:44 PM PDT 24
Peak memory 195540 kb
Host smart-c7ad1ba6-5558-41b0-8200-2b090fe7f7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472036093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2472036093
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.834192316
Short name T639
Test name
Test status
Simulation time 20407137 ps
CPU time 0.59 seconds
Started Jul 28 05:02:12 PM PDT 24
Finished Jul 28 05:02:13 PM PDT 24
Peak memory 195516 kb
Host smart-ca060e64-eb5e-40f3-91bb-d1be39bb1e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834192316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.834192316
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3296996468
Short name T699
Test name
Test status
Simulation time 19257581 ps
CPU time 0.62 seconds
Started Jul 28 05:02:01 PM PDT 24
Finished Jul 28 05:02:01 PM PDT 24
Peak memory 195456 kb
Host smart-1b4c8d69-e871-4017-ae3c-bdff7d325ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296996468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3296996468
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1602734259
Short name T74
Test name
Test status
Simulation time 48291061 ps
CPU time 0.62 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195496 kb
Host smart-4d91a19a-ad88-4fd1-b0cc-d5314f582455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602734259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1602734259
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2975397496
Short name T691
Test name
Test status
Simulation time 18448509 ps
CPU time 0.61 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195516 kb
Host smart-e706e33a-df06-478c-96b9-5bc7381c0ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975397496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2975397496
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3772778678
Short name T114
Test name
Test status
Simulation time 172412223 ps
CPU time 0.97 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195592 kb
Host smart-6e905109-60a1-4a6d-9254-d40b7f794296
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772778678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3
772778678
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1268074189
Short name T720
Test name
Test status
Simulation time 213428350 ps
CPU time 3.16 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:54 PM PDT 24
Peak memory 195928 kb
Host smart-f7803072-e61e-40b7-8106-5a639de848aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268074189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
268074189
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1237641853
Short name T659
Test name
Test status
Simulation time 31192023 ps
CPU time 0.63 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 198804 kb
Host smart-b735c519-c0e5-4031-887f-27ccbaf03bef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237641853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
237641853
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3961453886
Short name T76
Test name
Test status
Simulation time 21645677 ps
CPU time 0.59 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195556 kb
Host smart-6a318249-7c1a-4462-8c9a-58fc4a991278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961453886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3961453886
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2890317690
Short name T675
Test name
Test status
Simulation time 153607750 ps
CPU time 0.58 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:39 PM PDT 24
Peak memory 195476 kb
Host smart-3f055f07-9596-428c-b080-a8e9745b99bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890317690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2890317690
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.908449776
Short name T713
Test name
Test status
Simulation time 21820389 ps
CPU time 0.73 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 195608 kb
Host smart-372c476d-69b4-4596-bcdb-f153ad3e733d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908449776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sam
e_csr_outstanding.908449776
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2477898537
Short name T688
Test name
Test status
Simulation time 315704865 ps
CPU time 1.61 seconds
Started Jul 28 05:01:30 PM PDT 24
Finished Jul 28 05:01:32 PM PDT 24
Peak memory 197832 kb
Host smart-83da5d9f-9d3a-4636-a74b-c97fbfbdcf88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477898537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2477898537
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2202171150
Short name T724
Test name
Test status
Simulation time 94815106 ps
CPU time 1.09 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 200612 kb
Host smart-fb9974b1-c8ff-40f9-b627-292e905492a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202171150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2202171150
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2477419074
Short name T716
Test name
Test status
Simulation time 22129943 ps
CPU time 0.61 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 195492 kb
Host smart-5c773269-8c3b-4d3e-a612-1da0c83a79c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477419074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2477419074
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1283342504
Short name T153
Test name
Test status
Simulation time 50598695 ps
CPU time 0.6 seconds
Started Jul 28 05:01:53 PM PDT 24
Finished Jul 28 05:01:53 PM PDT 24
Peak memory 195484 kb
Host smart-8184c238-8125-4ae2-a50d-2b7590006e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283342504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1283342504
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3779134459
Short name T665
Test name
Test status
Simulation time 21005753 ps
CPU time 0.59 seconds
Started Jul 28 05:01:48 PM PDT 24
Finished Jul 28 05:01:48 PM PDT 24
Peak memory 195544 kb
Host smart-ef27f0ec-b0ab-4a3e-8330-262479645c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779134459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3779134459
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2577961681
Short name T666
Test name
Test status
Simulation time 18016125 ps
CPU time 0.6 seconds
Started Jul 28 05:01:55 PM PDT 24
Finished Jul 28 05:01:56 PM PDT 24
Peak memory 195544 kb
Host smart-82a5267b-4c46-429b-a059-961814054ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577961681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2577961681
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1229483796
Short name T677
Test name
Test status
Simulation time 19260328 ps
CPU time 0.61 seconds
Started Jul 28 05:01:59 PM PDT 24
Finished Jul 28 05:01:59 PM PDT 24
Peak memory 195580 kb
Host smart-b61a757f-1e83-43e9-a053-f6be8526d319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229483796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1229483796
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3203407903
Short name T660
Test name
Test status
Simulation time 18622234 ps
CPU time 0.62 seconds
Started Jul 28 05:01:45 PM PDT 24
Finished Jul 28 05:01:46 PM PDT 24
Peak memory 195480 kb
Host smart-9a7e60cc-7069-4713-acae-5d15852dfb00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203407903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3203407903
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2238180154
Short name T701
Test name
Test status
Simulation time 19933457 ps
CPU time 0.59 seconds
Started Jul 28 05:01:54 PM PDT 24
Finished Jul 28 05:01:54 PM PDT 24
Peak memory 195524 kb
Host smart-40371e35-d73f-48cf-9f8d-d2f28dc44a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238180154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.2238180154
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1577161465
Short name T689
Test name
Test status
Simulation time 17344017 ps
CPU time 0.59 seconds
Started Jul 28 05:01:51 PM PDT 24
Finished Jul 28 05:01:52 PM PDT 24
Peak memory 195496 kb
Host smart-c0b0eef8-418f-4460-b4ac-5e92ec7919e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577161465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1577161465
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2680936599
Short name T156
Test name
Test status
Simulation time 18684443 ps
CPU time 0.62 seconds
Started Jul 28 05:02:05 PM PDT 24
Finished Jul 28 05:02:05 PM PDT 24
Peak memory 195464 kb
Host smart-a8e45f28-e101-4cb8-88ab-e9c402903459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680936599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2680936599
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3037088809
Short name T727
Test name
Test status
Simulation time 20469143 ps
CPU time 0.61 seconds
Started Jul 28 05:01:54 PM PDT 24
Finished Jul 28 05:01:55 PM PDT 24
Peak memory 195496 kb
Host smart-204c3681-e65a-435d-bd61-9e983cb63755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037088809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3037088809
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3847777394
Short name T656
Test name
Test status
Simulation time 49279024 ps
CPU time 0.77 seconds
Started Jul 28 05:01:32 PM PDT 24
Finished Jul 28 05:01:33 PM PDT 24
Peak memory 195776 kb
Host smart-d756f137-1d5c-44cd-af90-3d7446d56a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847777394 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3847777394
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.753681063
Short name T678
Test name
Test status
Simulation time 17844964 ps
CPU time 0.72 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 197976 kb
Host smart-8fb9fe3b-4f4a-484c-b8ad-379f81f64a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753681063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.753681063
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.77741702
Short name T631
Test name
Test status
Simulation time 144376480 ps
CPU time 0.61 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195540 kb
Host smart-1d65630a-9547-4dcb-b766-79825584a48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77741702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.77741702
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.3672739159
Short name T122
Test name
Test status
Simulation time 23324852 ps
CPU time 0.72 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:39 PM PDT 24
Peak memory 197900 kb
Host smart-425b78c4-d04d-4643-8ac4-2cc93963d1a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672739159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.3672739159
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1305114077
Short name T697
Test name
Test status
Simulation time 66192425 ps
CPU time 1.42 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:49 PM PDT 24
Peak memory 196024 kb
Host smart-812eebe2-ae64-40f4-a908-7f644f6cb01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305114077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1305114077
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.4058268300
Short name T654
Test name
Test status
Simulation time 53370791 ps
CPU time 0.85 seconds
Started Jul 28 05:01:46 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 195784 kb
Host smart-c699a8d6-4b9c-4794-a859-44594651acb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058268300 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.4058268300
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.712972531
Short name T126
Test name
Test status
Simulation time 22566754 ps
CPU time 0.66 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 197728 kb
Host smart-9011d9f7-9ebb-41b7-9ea8-d02cecaf23b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712972531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.712972531
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1888206521
Short name T684
Test name
Test status
Simulation time 58069725 ps
CPU time 0.6 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:35 PM PDT 24
Peak memory 195476 kb
Host smart-aa3e7c48-4234-442a-a8f0-ea3e9db91ba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888206521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1888206521
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2494873593
Short name T705
Test name
Test status
Simulation time 55005986 ps
CPU time 0.68 seconds
Started Jul 28 05:01:35 PM PDT 24
Finished Jul 28 05:01:36 PM PDT 24
Peak memory 198808 kb
Host smart-65e1b427-ee69-4800-890f-26f32714cec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494873593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2494873593
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.776723741
Short name T698
Test name
Test status
Simulation time 585531503 ps
CPU time 1.54 seconds
Started Jul 28 05:01:35 PM PDT 24
Finished Jul 28 05:01:37 PM PDT 24
Peak memory 197892 kb
Host smart-08bb072f-9c3b-4797-9a76-e6a90353d872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776723741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.776723741
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3612227213
Short name T59
Test name
Test status
Simulation time 449583098 ps
CPU time 1.52 seconds
Started Jul 28 05:01:34 PM PDT 24
Finished Jul 28 05:01:36 PM PDT 24
Peak memory 195800 kb
Host smart-2275ffcc-56e4-4cb2-9b32-9bfc702e05ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612227213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3612227213
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.7620679
Short name T679
Test name
Test status
Simulation time 53178392 ps
CPU time 1.39 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 198544 kb
Host smart-24209c3d-e1d1-41e8-88d6-968f8dffc6c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7620679 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.7620679
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3210757106
Short name T108
Test name
Test status
Simulation time 56373956 ps
CPU time 0.66 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 197984 kb
Host smart-114fb1b4-9f23-4ef8-b454-bc027155544a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210757106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3210757106
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2246792868
Short name T634
Test name
Test status
Simulation time 21844337 ps
CPU time 0.63 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195492 kb
Host smart-a45af08d-dbe0-4ae5-a750-446398ce2964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246792868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2246792868
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2203856496
Short name T644
Test name
Test status
Simulation time 89742741 ps
CPU time 0.87 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 198920 kb
Host smart-ac5b0d16-c0b0-4258-b38e-1b3e995deb15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203856496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2203856496
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.741729408
Short name T671
Test name
Test status
Simulation time 240873446 ps
CPU time 1.29 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 196912 kb
Host smart-01b46b80-6e2b-4b16-8cbe-f9ce2a50003c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741729408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.741729408
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2691434018
Short name T78
Test name
Test status
Simulation time 487507674 ps
CPU time 1.43 seconds
Started Jul 28 05:01:27 PM PDT 24
Finished Jul 28 05:01:29 PM PDT 24
Peak memory 195928 kb
Host smart-95382d81-9672-4329-9f3c-765491995f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691434018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2691434018
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2226386247
Short name T706
Test name
Test status
Simulation time 39668783 ps
CPU time 0.72 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:42 PM PDT 24
Peak memory 195384 kb
Host smart-1100de4a-4f19-4595-9544-d420b5f8d105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226386247 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2226386247
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3984957841
Short name T658
Test name
Test status
Simulation time 21272933 ps
CPU time 0.61 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:39 PM PDT 24
Peak memory 197636 kb
Host smart-e2db66ca-fbbb-47fe-8c6a-04a71bae8d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984957841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3984957841
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3628586569
Short name T635
Test name
Test status
Simulation time 36239201 ps
CPU time 0.58 seconds
Started Jul 28 05:01:44 PM PDT 24
Finished Jul 28 05:01:45 PM PDT 24
Peak memory 195572 kb
Host smart-dd3cf376-a9ea-4bc8-888c-04c8343b557f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628586569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3628586569
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4144318599
Short name T680
Test name
Test status
Simulation time 63083018 ps
CPU time 0.85 seconds
Started Jul 28 05:01:40 PM PDT 24
Finished Jul 28 05:01:41 PM PDT 24
Peak memory 195620 kb
Host smart-5234dc21-8d31-4853-9ef2-824b871bda9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144318599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.4144318599
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1316947567
Short name T729
Test name
Test status
Simulation time 103632196 ps
CPU time 2.03 seconds
Started Jul 28 05:01:38 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 196960 kb
Host smart-1eaf9943-611f-4256-86d9-b03b095cdf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316947567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1316947567
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3687559768
Short name T674
Test name
Test status
Simulation time 502251560 ps
CPU time 0.99 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 200948 kb
Host smart-8bc566ee-0538-47db-85c0-1fcb46c6154c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687559768 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3687559768
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.860094123
Short name T731
Test name
Test status
Simulation time 19637952 ps
CPU time 0.65 seconds
Started Jul 28 05:01:39 PM PDT 24
Finished Jul 28 05:01:40 PM PDT 24
Peak memory 197768 kb
Host smart-af487cd7-13ee-43a2-b23f-91c2acc108e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860094123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.860094123
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.815133865
Short name T730
Test name
Test status
Simulation time 44992595 ps
CPU time 0.58 seconds
Started Jul 28 05:02:03 PM PDT 24
Finished Jul 28 05:02:04 PM PDT 24
Peak memory 195484 kb
Host smart-519d6d74-3572-4bd7-b596-e367427543d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815133865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.815133865
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1057885911
Short name T120
Test name
Test status
Simulation time 74655431 ps
CPU time 0.74 seconds
Started Jul 28 05:01:47 PM PDT 24
Finished Jul 28 05:01:47 PM PDT 24
Peak memory 197848 kb
Host smart-b2a787ed-fe97-480e-b890-067c822d9543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057885911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.1057885911
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1423119040
Short name T652
Test name
Test status
Simulation time 70122272 ps
CPU time 1.99 seconds
Started Jul 28 05:01:41 PM PDT 24
Finished Jul 28 05:01:44 PM PDT 24
Peak memory 196852 kb
Host smart-2a51df3a-db7e-45d7-a9f7-1219bc2a4c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423119040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1423119040
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2387409397
Short name T714
Test name
Test status
Simulation time 240059926 ps
CPU time 1.08 seconds
Started Jul 28 05:01:37 PM PDT 24
Finished Jul 28 05:01:38 PM PDT 24
Peak memory 201204 kb
Host smart-17daa7cb-e487-43d5-83a7-070d4754f49e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387409397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2387409397
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.256132983
Short name T383
Test name
Test status
Simulation time 35066046 ps
CPU time 0.85 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 200204 kb
Host smart-6edadeca-0af9-4127-a337-515a1439ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256132983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.256132983
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1546692920
Short name T375
Test name
Test status
Simulation time 31032995 ps
CPU time 0.63 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 197316 kb
Host smart-5c5f95d3-06bd-4c91-ab31-25a9a4ab1ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546692920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1546692920
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.4043947558
Short name T327
Test name
Test status
Simulation time 317451350 ps
CPU time 0.98 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 198476 kb
Host smart-ff79e875-c9bc-4c5b-baae-082534e69acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043947558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.4043947558
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3845327798
Short name T319
Test name
Test status
Simulation time 48140116 ps
CPU time 0.61 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:06:58 PM PDT 24
Peak memory 198020 kb
Host smart-8eda8593-6ba4-4311-b14f-5cf53689a748
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845327798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3845327798
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3359853195
Short name T234
Test name
Test status
Simulation time 48839608 ps
CPU time 0.66 seconds
Started Jul 28 05:07:11 PM PDT 24
Finished Jul 28 05:07:12 PM PDT 24
Peak memory 198044 kb
Host smart-3a632e10-e37f-4595-9d76-3636d3eb566c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359853195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3359853195
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.1428341641
Short name T197
Test name
Test status
Simulation time 43015902 ps
CPU time 0.73 seconds
Started Jul 28 05:07:10 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 201444 kb
Host smart-19ee0861-866b-44e0-b93e-9a8ef55f1aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428341641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.1428341641
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.442878494
Short name T237
Test name
Test status
Simulation time 45025221 ps
CPU time 0.73 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:06:51 PM PDT 24
Peak memory 199148 kb
Host smart-9163368e-dadf-428b-a4db-6a043ecd5873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442878494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.442878494
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3013883838
Short name T526
Test name
Test status
Simulation time 160057691 ps
CPU time 0.84 seconds
Started Jul 28 05:07:05 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 209568 kb
Host smart-a2ab6181-16ef-4cb5-838c-69315d85cc2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013883838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3013883838
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.400522556
Short name T18
Test name
Test status
Simulation time 529480492 ps
CPU time 1.06 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 216920 kb
Host smart-f1ccff6c-83cd-444b-96be-12dcb194a33b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400522556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.400522556
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2970011657
Short name T308
Test name
Test status
Simulation time 119062911 ps
CPU time 0.8 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:54 PM PDT 24
Peak memory 199396 kb
Host smart-612a8e99-810d-4729-9582-e7a8b3817a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970011657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2970011657
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1041237195
Short name T507
Test name
Test status
Simulation time 134667197 ps
CPU time 0.81 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:14 PM PDT 24
Peak memory 200056 kb
Host smart-09593a39-79e6-4a63-bf66-9a66f8d561f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041237195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1041237195
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2750102561
Short name T494
Test name
Test status
Simulation time 45336051 ps
CPU time 0.65 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 196780 kb
Host smart-8fa6e90d-9a6b-4f04-af8e-346047e3dc53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750102561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.2750102561
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1258416283
Short name T445
Test name
Test status
Simulation time 163404042 ps
CPU time 0.97 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 198152 kb
Host smart-c9fbab21-938f-4d23-8465-bf940289e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258416283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1258416283
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1470252019
Short name T501
Test name
Test status
Simulation time 55683512 ps
CPU time 0.61 seconds
Started Jul 28 05:07:18 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 198012 kb
Host smart-94747454-8903-45da-b0c8-d58f1a8cd6f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470252019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1470252019
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1393107567
Short name T613
Test name
Test status
Simulation time 72451385 ps
CPU time 0.6 seconds
Started Jul 28 05:06:59 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 198088 kb
Host smart-46af8c8e-1d0d-4290-b72d-240cc92f0669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393107567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1393107567
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2194414608
Short name T201
Test name
Test status
Simulation time 44852029 ps
CPU time 0.73 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 201440 kb
Host smart-8c4cd28c-ff35-4a25-bc35-8af65d1d3fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194414608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2194414608
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1205766518
Short name T10
Test name
Test status
Simulation time 38861538 ps
CPU time 0.7 seconds
Started Jul 28 05:06:59 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 198228 kb
Host smart-930eda16-3a0b-4d4c-98b4-f265fa557a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205766518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1205766518
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2986014139
Short name T213
Test name
Test status
Simulation time 148237516 ps
CPU time 0.83 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 209432 kb
Host smart-f8214f09-e6df-455e-9ced-8cfa976cff0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986014139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2986014139
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2311592153
Short name T347
Test name
Test status
Simulation time 54075997 ps
CPU time 0.77 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 197964 kb
Host smart-3a709f7c-4ea3-4a93-a996-263483b8f6b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311592153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2311592153
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2842938237
Short name T290
Test name
Test status
Simulation time 90379557 ps
CPU time 0.68 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 198508 kb
Host smart-b0882a75-7af6-4a60-ba9c-eb9356f83545
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842938237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2842938237
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2537107260
Short name T105
Test name
Test status
Simulation time 74376378 ps
CPU time 0.92 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 200728 kb
Host smart-502d2d18-21f6-485f-bfb6-eb5b54f19a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537107260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2537107260
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3365685773
Short name T146
Test name
Test status
Simulation time 54911484 ps
CPU time 0.81 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 199124 kb
Host smart-53fa2118-977b-4a1a-a4cb-d9d60e0159e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365685773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.3365685773
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2776476956
Short name T280
Test name
Test status
Simulation time 33013025 ps
CPU time 0.59 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 197352 kb
Host smart-b2b11db4-5c42-4ce2-acdd-e75da52138a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776476956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2776476956
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3880801559
Short name T462
Test name
Test status
Simulation time 1347735019 ps
CPU time 0.97 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 198444 kb
Host smart-d47ef62f-e01d-4ae6-aebc-385bee37a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880801559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3880801559
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.252116986
Short name T587
Test name
Test status
Simulation time 30108279 ps
CPU time 0.64 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 198112 kb
Host smart-ef47f067-d833-4344-be7d-e0265d68e1fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252116986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.252116986
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2843026449
Short name T583
Test name
Test status
Simulation time 34948520 ps
CPU time 0.6 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 198144 kb
Host smart-1328dd0e-9c39-4a9e-bbff-81ea71d1fb52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843026449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2843026449
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.4171797906
Short name T29
Test name
Test status
Simulation time 50404716 ps
CPU time 0.65 seconds
Started Jul 28 05:07:38 PM PDT 24
Finished Jul 28 05:07:39 PM PDT 24
Peak memory 201380 kb
Host smart-6566a2b4-9fe6-4987-88e4-907e36ea9598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171797906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.4171797906
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.619811086
Short name T479
Test name
Test status
Simulation time 149363370 ps
CPU time 0.86 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 209492 kb
Host smart-83f2f1f9-58f7-44fe-a34a-ab756159ba36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619811086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.619811086
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3263028412
Short name T69
Test name
Test status
Simulation time 131864441 ps
CPU time 0.65 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:27 PM PDT 24
Peak memory 198248 kb
Host smart-e40c82de-eef4-4e76-bcae-01cac279bb63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263028412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3263028412
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.772804196
Short name T606
Test name
Test status
Simulation time 27940345 ps
CPU time 0.68 seconds
Started Jul 28 05:07:26 PM PDT 24
Finished Jul 28 05:07:27 PM PDT 24
Peak memory 199356 kb
Host smart-ac5e49f1-e19d-4be9-9db3-ac4f4268d2b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772804196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.772804196
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.1939406623
Short name T511
Test name
Test status
Simulation time 32778605 ps
CPU time 1.02 seconds
Started Jul 28 05:07:52 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 201016 kb
Host smart-1ad04ba7-9477-4533-8d39-10e67a7bcd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939406623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1939406623
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.2072971358
Short name T166
Test name
Test status
Simulation time 46649572 ps
CPU time 0.76 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 199200 kb
Host smart-06c55ee2-1c91-4340-8386-89b54e10ef85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072971358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.2072971358
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3955072929
Short name T491
Test name
Test status
Simulation time 29723553 ps
CPU time 0.63 seconds
Started Jul 28 05:07:44 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 198032 kb
Host smart-9441a756-2872-4d1c-a9a9-aa1a68485c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955072929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3955072929
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1112613951
Short name T614
Test name
Test status
Simulation time 54991757 ps
CPU time 0.65 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 198180 kb
Host smart-79744bdd-69a4-44b2-b9de-8b8076c12d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112613951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1112613951
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1178294994
Short name T277
Test name
Test status
Simulation time 107922539 ps
CPU time 0.62 seconds
Started Jul 28 05:07:46 PM PDT 24
Finished Jul 28 05:07:46 PM PDT 24
Peak memory 198380 kb
Host smart-10b1d164-9d14-4f31-8c85-1ef641de0d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178294994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1178294994
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.1369989363
Short name T561
Test name
Test status
Simulation time 87884382 ps
CPU time 0.8 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 198476 kb
Host smart-ef7cdae8-49f2-415c-9077-7a783110d645
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369989363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1369989363
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1661158199
Short name T545
Test name
Test status
Simulation time 120931616 ps
CPU time 0.84 seconds
Started Jul 28 05:07:34 PM PDT 24
Finished Jul 28 05:07:35 PM PDT 24
Peak memory 209188 kb
Host smart-63cabc66-2208-4d5c-9919-f8b01d8efbcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661158199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1661158199
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.420965520
Short name T264
Test name
Test status
Simulation time 79138187 ps
CPU time 0.71 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 198040 kb
Host smart-6d47810f-c110-400c-806b-27812067f8d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420965520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.420965520
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.3613551407
Short name T53
Test name
Test status
Simulation time 153799991 ps
CPU time 0.68 seconds
Started Jul 28 05:07:45 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 198548 kb
Host smart-67b78d26-1df5-4205-8fc7-cb99b3ce9d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613551407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3613551407
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.3521712106
Short name T542
Test name
Test status
Simulation time 25977609 ps
CPU time 0.7 seconds
Started Jul 28 05:07:26 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 199236 kb
Host smart-3598dcd5-5202-47f3-bb5c-bcc6c68539e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521712106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3521712106
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.448720438
Short name T589
Test name
Test status
Simulation time 53264592 ps
CPU time 0.82 seconds
Started Jul 28 05:07:31 PM PDT 24
Finished Jul 28 05:07:32 PM PDT 24
Peak memory 199228 kb
Host smart-b227635e-6e3e-4061-8221-f2c5928c8f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448720438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.448720438
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2375727397
Short name T11
Test name
Test status
Simulation time 39013611 ps
CPU time 0.59 seconds
Started Jul 28 05:07:50 PM PDT 24
Finished Jul 28 05:07:51 PM PDT 24
Peak memory 198096 kb
Host smart-81dbdc0e-5bf8-48a0-b82a-d58a60676bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375727397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.2375727397
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.836526208
Short name T338
Test name
Test status
Simulation time 749059922 ps
CPU time 0.92 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 198188 kb
Host smart-925506b1-afe0-43c7-acb1-f309ea75aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836526208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.836526208
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.4207927834
Short name T602
Test name
Test status
Simulation time 40908613 ps
CPU time 0.57 seconds
Started Jul 28 05:07:35 PM PDT 24
Finished Jul 28 05:07:36 PM PDT 24
Peak memory 198072 kb
Host smart-d6eb4718-847e-4938-9b55-2538d45c0c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207927834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.4207927834
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.564691638
Short name T382
Test name
Test status
Simulation time 41849010 ps
CPU time 0.66 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 198068 kb
Host smart-0865fc43-ac17-42ac-a8fc-3ea79ff95360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564691638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.564691638
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2706479109
Short name T48
Test name
Test status
Simulation time 77129485 ps
CPU time 0.68 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:35 PM PDT 24
Peak memory 201464 kb
Host smart-353f8003-5473-4d23-a5de-788ee55654ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706479109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2706479109
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.923038161
Short name T256
Test name
Test status
Simulation time 113530358 ps
CPU time 0.74 seconds
Started Jul 28 05:07:37 PM PDT 24
Finished Jul 28 05:07:38 PM PDT 24
Peak memory 199208 kb
Host smart-84b81dae-c425-45d4-adeb-c24113af7dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923038161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.923038161
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.1839726241
Short name T301
Test name
Test status
Simulation time 149198856 ps
CPU time 0.81 seconds
Started Jul 28 05:07:55 PM PDT 24
Finished Jul 28 05:07:56 PM PDT 24
Peak memory 209508 kb
Host smart-086026ee-e2af-4761-ac07-5a6d3bb43f6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839726241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1839726241
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1876861568
Short name T558
Test name
Test status
Simulation time 57937282 ps
CPU time 0.78 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 198160 kb
Host smart-de27ccd6-3b45-4197-bb9e-4c5269614b1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876861568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1876861568
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.2402980661
Short name T247
Test name
Test status
Simulation time 62401470 ps
CPU time 0.63 seconds
Started Jul 28 05:07:36 PM PDT 24
Finished Jul 28 05:07:37 PM PDT 24
Peak memory 199376 kb
Host smart-d1e16154-deb8-4070-aba6-502103c074c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402980661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2402980661
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2898234684
Short name T385
Test name
Test status
Simulation time 25743531 ps
CPU time 0.69 seconds
Started Jul 28 05:07:35 PM PDT 24
Finished Jul 28 05:07:36 PM PDT 24
Peak memory 198628 kb
Host smart-f1de0ec6-2d11-4627-9a99-25978a9f71df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898234684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2898234684
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3101956033
Short name T132
Test name
Test status
Simulation time 29724537 ps
CPU time 0.66 seconds
Started Jul 28 05:07:36 PM PDT 24
Finished Jul 28 05:07:37 PM PDT 24
Peak memory 198108 kb
Host smart-2b110ccb-6464-4fc6-857a-080a386a2218
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101956033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3101956033
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.631638658
Short name T326
Test name
Test status
Simulation time 662215743 ps
CPU time 0.95 seconds
Started Jul 28 05:07:54 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 198172 kb
Host smart-7006b503-c120-40c0-bbca-ec34856944b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631638658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.631638658
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.1294951199
Short name T519
Test name
Test status
Simulation time 55080644 ps
CPU time 0.67 seconds
Started Jul 28 05:07:32 PM PDT 24
Finished Jul 28 05:07:33 PM PDT 24
Peak memory 198016 kb
Host smart-3d64a9ff-2a64-4f8c-b977-0d53ab1de3ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294951199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.1294951199
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2536897923
Short name T621
Test name
Test status
Simulation time 76160841 ps
CPU time 0.61 seconds
Started Jul 28 05:07:43 PM PDT 24
Finished Jul 28 05:07:43 PM PDT 24
Peak memory 198120 kb
Host smart-6f8beb74-230c-4759-8691-45d41db0eae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536897923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2536897923
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1943948024
Short name T447
Test name
Test status
Simulation time 47464183 ps
CPU time 0.73 seconds
Started Jul 28 05:07:41 PM PDT 24
Finished Jul 28 05:07:42 PM PDT 24
Peak memory 201292 kb
Host smart-4cad6b7e-f4ee-4569-b3ac-85746c7fc0d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943948024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1943948024
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.1596127311
Short name T27
Test name
Test status
Simulation time 46045743 ps
CPU time 0.7 seconds
Started Jul 28 05:07:32 PM PDT 24
Finished Jul 28 05:07:32 PM PDT 24
Peak memory 199176 kb
Host smart-c88341bf-9c3e-4f8e-a15a-eb38f11d834a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596127311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.1596127311
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3767436459
Short name T428
Test name
Test status
Simulation time 79000744 ps
CPU time 0.69 seconds
Started Jul 28 05:07:40 PM PDT 24
Finished Jul 28 05:07:40 PM PDT 24
Peak memory 199104 kb
Host smart-38c1ec58-e64e-4f05-a511-bf5a9f641280
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767436459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3767436459
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2107092748
Short name T448
Test name
Test status
Simulation time 106111266 ps
CPU time 0.91 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 209520 kb
Host smart-79aa3f70-e332-47cb-adad-ead8a499ef9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107092748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2107092748
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2763512365
Short name T450
Test name
Test status
Simulation time 77882882 ps
CPU time 0.74 seconds
Started Jul 28 05:07:26 PM PDT 24
Finished Jul 28 05:07:27 PM PDT 24
Peak memory 198164 kb
Host smart-a3861252-585b-498b-9ed9-2174a53a1484
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763512365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2763512365
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.3498827653
Short name T442
Test name
Test status
Simulation time 38452788 ps
CPU time 0.69 seconds
Started Jul 28 05:07:27 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 199348 kb
Host smart-f3ddbc69-f76e-4d48-8a9e-1c581a0748fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498827653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.3498827653
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1321127051
Short name T102
Test name
Test status
Simulation time 19955884 ps
CPU time 0.64 seconds
Started Jul 28 05:07:44 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 199244 kb
Host smart-63f47928-ffa6-479b-a8ee-95714151acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321127051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1321127051
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1493434414
Short name T159
Test name
Test status
Simulation time 57150391 ps
CPU time 0.72 seconds
Started Jul 28 05:07:35 PM PDT 24
Finished Jul 28 05:07:36 PM PDT 24
Peak memory 199540 kb
Host smart-ff0de507-214a-424e-964a-5ca57bfc0ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493434414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1493434414
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1192149550
Short name T287
Test name
Test status
Simulation time 47862649 ps
CPU time 0.58 seconds
Started Jul 28 05:07:44 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 198004 kb
Host smart-5a1082d6-71cd-4aed-8143-8fc42876af4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192149550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1192149550
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.274065251
Short name T354
Test name
Test status
Simulation time 800642655 ps
CPU time 0.95 seconds
Started Jul 28 05:07:29 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 198108 kb
Host smart-ee903c5d-b67d-4c56-9ec0-908dc75092a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274065251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.274065251
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.716304057
Short name T219
Test name
Test status
Simulation time 39133094 ps
CPU time 0.57 seconds
Started Jul 28 05:07:29 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 198092 kb
Host smart-1aa44d54-d34d-4ac7-bdf4-9a67ab35bc67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716304057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.716304057
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1090717041
Short name T186
Test name
Test status
Simulation time 38278568 ps
CPU time 0.68 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 201372 kb
Host smart-414e8d85-5d1d-48e5-a701-664127128b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090717041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1090717041
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2110641731
Short name T312
Test name
Test status
Simulation time 87730276 ps
CPU time 0.93 seconds
Started Jul 28 05:07:28 PM PDT 24
Finished Jul 28 05:07:29 PM PDT 24
Peak memory 199064 kb
Host smart-ddf1bb7d-9b7b-4526-a41f-eb75a85209b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110641731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2110641731
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3268735605
Short name T304
Test name
Test status
Simulation time 105390129 ps
CPU time 0.91 seconds
Started Jul 28 05:07:36 PM PDT 24
Finished Jul 28 05:07:37 PM PDT 24
Peak memory 209536 kb
Host smart-9c7e7646-33b9-4c13-b817-1111d967185c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268735605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3268735605
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1714579688
Short name T275
Test name
Test status
Simulation time 71016155 ps
CPU time 0.74 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 198004 kb
Host smart-55e58074-6c12-4f2b-b560-1a50b5709384
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714579688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1714579688
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.3844354479
Short name T263
Test name
Test status
Simulation time 28368433 ps
CPU time 0.72 seconds
Started Jul 28 05:07:43 PM PDT 24
Finished Jul 28 05:07:44 PM PDT 24
Peak memory 199404 kb
Host smart-32a1908b-af08-4f2f-8ad8-c5d66d6b5f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844354479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3844354479
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3943734869
Short name T438
Test name
Test status
Simulation time 57616141 ps
CPU time 0.71 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 199400 kb
Host smart-23428e1c-270e-4858-bb2b-08386566bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943734869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3943734869
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3008763609
Short name T309
Test name
Test status
Simulation time 38621979 ps
CPU time 0.59 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 197336 kb
Host smart-e294bbb6-41ce-4255-b21a-29d1c66d46eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008763609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.3008763609
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.1728199779
Short name T404
Test name
Test status
Simulation time 157617831 ps
CPU time 0.96 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 198128 kb
Host smart-7115f1ca-a2b5-4600-8572-d71e2c33ce7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728199779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1728199779
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2095383159
Short name T571
Test name
Test status
Simulation time 23459690 ps
CPU time 0.62 seconds
Started Jul 28 05:07:58 PM PDT 24
Finished Jul 28 05:07:59 PM PDT 24
Peak memory 198236 kb
Host smart-745373a2-fcb1-4941-85b1-03f5c3b736f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095383159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2095383159
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3822075092
Short name T358
Test name
Test status
Simulation time 50098860 ps
CPU time 0.63 seconds
Started Jul 28 05:07:58 PM PDT 24
Finished Jul 28 05:07:58 PM PDT 24
Peak memory 198640 kb
Host smart-9087940f-0a5b-4ecf-998c-12ba88532af0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822075092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3822075092
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.1026668386
Short name T217
Test name
Test status
Simulation time 44507657 ps
CPU time 0.66 seconds
Started Jul 28 05:07:50 PM PDT 24
Finished Jul 28 05:07:51 PM PDT 24
Peak memory 198232 kb
Host smart-46f757fa-1bd5-4308-a6f3-099ebf8ab0f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026668386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.1026668386
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1350226712
Short name T427
Test name
Test status
Simulation time 406961942 ps
CPU time 0.79 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 209728 kb
Host smart-f70c8ae8-2fb5-40e7-8126-02ba3b2be5a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350226712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1350226712
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2451949746
Short name T454
Test name
Test status
Simulation time 51426076 ps
CPU time 0.74 seconds
Started Jul 28 05:07:52 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 198188 kb
Host smart-bbafa254-5977-458e-9e6e-f6e5f53c1620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451949746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2451949746
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.845681712
Short name T293
Test name
Test status
Simulation time 50434454 ps
CPU time 0.63 seconds
Started Jul 28 05:07:43 PM PDT 24
Finished Jul 28 05:07:44 PM PDT 24
Peak memory 198544 kb
Host smart-51b84a5a-5dcf-40b7-a3c4-106ae1f27df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845681712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.845681712
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.3008296631
Short name T549
Test name
Test status
Simulation time 69816574 ps
CPU time 0.85 seconds
Started Jul 28 05:07:43 PM PDT 24
Finished Jul 28 05:07:44 PM PDT 24
Peak memory 200260 kb
Host smart-c7510245-a2a5-4b45-822f-b08026a807d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008296631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3008296631
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.529410963
Short name T131
Test name
Test status
Simulation time 74934597 ps
CPU time 0.58 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 197272 kb
Host smart-28650806-048a-4c10-b81c-f2f99002a3b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529410963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.529410963
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3876096713
Short name T342
Test name
Test status
Simulation time 157441565 ps
CPU time 1.02 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198096 kb
Host smart-5041cf3e-1fac-401a-b63d-099e0c4bb3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876096713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3876096713
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.2975248153
Short name T373
Test name
Test status
Simulation time 75163652 ps
CPU time 0.59 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 198184 kb
Host smart-ec6b0299-e0de-4c8b-bcfe-a5b401dec16e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975248153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2975248153
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.779228673
Short name T527
Test name
Test status
Simulation time 47535590 ps
CPU time 0.7 seconds
Started Jul 28 05:07:52 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 198080 kb
Host smart-19e8e9d4-acb7-458f-a628-fb4f16399a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779228673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.779228673
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1334828855
Short name T190
Test name
Test status
Simulation time 44668597 ps
CPU time 0.71 seconds
Started Jul 28 05:07:36 PM PDT 24
Finished Jul 28 05:07:37 PM PDT 24
Peak memory 201136 kb
Host smart-82655c9f-e996-4b59-a79b-47e288bee7f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334828855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1334828855
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1493840811
Short name T446
Test name
Test status
Simulation time 117920887 ps
CPU time 0.77 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 198476 kb
Host smart-574d342c-0edd-4e38-80b2-d8b099a7e271
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493840811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1493840811
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.764898241
Short name T575
Test name
Test status
Simulation time 243727688 ps
CPU time 0.78 seconds
Started Jul 28 05:07:57 PM PDT 24
Finished Jul 28 05:07:58 PM PDT 24
Peak memory 209528 kb
Host smart-386d83f3-8a21-4fba-9bcf-d3a8f087561c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764898241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.764898241
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1948094021
Short name T152
Test name
Test status
Simulation time 152392139 ps
CPU time 0.8 seconds
Started Jul 28 05:07:45 PM PDT 24
Finished Jul 28 05:07:46 PM PDT 24
Peak memory 199308 kb
Host smart-64707181-0603-4f7e-b9eb-67ecb2db60b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948094021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1948094021
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.1730155622
Short name T54
Test name
Test status
Simulation time 64113479 ps
CPU time 0.6 seconds
Started Jul 28 05:07:46 PM PDT 24
Finished Jul 28 05:07:46 PM PDT 24
Peak memory 198528 kb
Host smart-70a2a0c8-b6d2-45b8-a984-4e3fd7c3dcf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730155622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1730155622
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.3522461352
Short name T512
Test name
Test status
Simulation time 44903969 ps
CPU time 0.89 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 200300 kb
Host smart-2a2f2ead-c8ce-4cf7-8548-73396d7a8ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522461352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3522461352
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.4133794016
Short name T579
Test name
Test status
Simulation time 55204090 ps
CPU time 0.77 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 199080 kb
Host smart-96f8b8ff-027f-44c1-aa69-b8c0b0e87f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133794016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.4133794016
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1489205006
Short name T238
Test name
Test status
Simulation time 39118663 ps
CPU time 0.56 seconds
Started Jul 28 05:07:51 PM PDT 24
Finished Jul 28 05:07:52 PM PDT 24
Peak memory 198080 kb
Host smart-c3a615d3-8095-4b28-b599-08a580f1080d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489205006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.1489205006
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3222660024
Short name T544
Test name
Test status
Simulation time 607488119 ps
CPU time 0.98 seconds
Started Jul 28 05:08:00 PM PDT 24
Finished Jul 28 05:08:01 PM PDT 24
Peak memory 198160 kb
Host smart-e9a65072-b8b8-4045-9d58-8c4da9c77107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222660024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3222660024
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.230246155
Short name T509
Test name
Test status
Simulation time 36747539 ps
CPU time 0.61 seconds
Started Jul 28 05:07:45 PM PDT 24
Finished Jul 28 05:07:46 PM PDT 24
Peak memory 198092 kb
Host smart-3e254bd0-0a0c-4b19-a97b-934e1d0b52dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230246155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.230246155
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.611137727
Short name T499
Test name
Test status
Simulation time 45810746 ps
CPU time 0.62 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 198060 kb
Host smart-4bbc1a0e-b062-4450-9706-8c8c8d814084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611137727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.611137727
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.617129763
Short name T598
Test name
Test status
Simulation time 43505498 ps
CPU time 0.6 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:47 PM PDT 24
Peak memory 198140 kb
Host smart-48ee76d7-1b6f-4791-82ae-0b8a8e9767ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617129763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.617129763
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.3886990268
Short name T33
Test name
Test status
Simulation time 158407184 ps
CPU time 0.77 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 209520 kb
Host smart-bca64adc-83a3-482c-82af-21bcdaaa78a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886990268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3886990268
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1010149195
Short name T265
Test name
Test status
Simulation time 114052900 ps
CPU time 0.73 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 198076 kb
Host smart-a335808d-372c-4ba9-a6f5-1a5553f99544
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010149195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1010149195
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2796682973
Short name T289
Test name
Test status
Simulation time 46324530 ps
CPU time 0.67 seconds
Started Jul 28 05:07:58 PM PDT 24
Finished Jul 28 05:07:59 PM PDT 24
Peak memory 198728 kb
Host smart-f21a2209-90ce-405b-afdc-2958008221c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796682973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2796682973
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.921944332
Short name T518
Test name
Test status
Simulation time 56604530 ps
CPU time 0.78 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 200104 kb
Host smart-1335f4cb-5458-4e9e-afb8-4126a96d853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921944332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.921944332
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1564427901
Short name T206
Test name
Test status
Simulation time 55429423 ps
CPU time 0.72 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 198316 kb
Host smart-a3d597f2-e4df-40a2-93f7-2c6e549d2d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564427901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1564427901
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3391131297
Short name T476
Test name
Test status
Simulation time 29098318 ps
CPU time 0.63 seconds
Started Jul 28 05:07:54 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 197360 kb
Host smart-5209ca03-4177-41a8-84c1-1f2b09e44125
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391131297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.3391131297
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2981429750
Short name T269
Test name
Test status
Simulation time 197759515 ps
CPU time 0.95 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 198148 kb
Host smart-14ed0d71-33bd-40ec-963d-1adaf42e877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981429750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2981429750
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2011192213
Short name T623
Test name
Test status
Simulation time 49040198 ps
CPU time 0.65 seconds
Started Jul 28 05:07:59 PM PDT 24
Finished Jul 28 05:08:00 PM PDT 24
Peak memory 198008 kb
Host smart-bc450f19-33ac-4435-aebf-826d5e880a05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011192213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2011192213
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3213021369
Short name T252
Test name
Test status
Simulation time 46259865 ps
CPU time 0.66 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 198400 kb
Host smart-89c580bc-78c1-4b39-be74-55a51fcc2be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213021369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3213021369
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1369678832
Short name T178
Test name
Test status
Simulation time 46274900 ps
CPU time 0.71 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 201316 kb
Host smart-8fae117f-b40d-4725-baee-eb641ae27e52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369678832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1369678832
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.1580074709
Short name T241
Test name
Test status
Simulation time 33574957 ps
CPU time 0.7 seconds
Started Jul 28 05:07:50 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 199036 kb
Host smart-083e7097-f6e5-4fb8-8529-c5ef4f4b7a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580074709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1580074709
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2297318084
Short name T403
Test name
Test status
Simulation time 102337661 ps
CPU time 1 seconds
Started Jul 28 05:07:51 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 209532 kb
Host smart-417b1bc0-e565-44d5-a897-f12f23528f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297318084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2297318084
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1503697028
Short name T609
Test name
Test status
Simulation time 227789663 ps
CPU time 0.91 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 199016 kb
Host smart-3482573f-bd41-4691-b515-5f728d601a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503697028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1503697028
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.1387458257
Short name T443
Test name
Test status
Simulation time 35016755 ps
CPU time 0.68 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 199340 kb
Host smart-265cf221-faec-458e-90c4-ee2ba2a60157
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387458257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1387458257
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1076905430
Short name T434
Test name
Test status
Simulation time 34050180 ps
CPU time 0.65 seconds
Started Jul 28 05:08:06 PM PDT 24
Finished Jul 28 05:08:07 PM PDT 24
Peak memory 198548 kb
Host smart-03b81ee9-bc47-4737-bdeb-9fe4122c3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076905430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1076905430
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2122985593
Short name T414
Test name
Test status
Simulation time 32196815 ps
CPU time 0.61 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 198068 kb
Host smart-cd92f780-9a63-4cd5-a304-ba6fa47606a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122985593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2122985593
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2527442195
Short name T268
Test name
Test status
Simulation time 1382776092 ps
CPU time 0.95 seconds
Started Jul 28 05:07:51 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 198448 kb
Host smart-71f787e0-668e-4809-9324-2a12975bb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527442195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2527442195
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.202925425
Short name T279
Test name
Test status
Simulation time 38509515 ps
CPU time 0.65 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 198016 kb
Host smart-f734a59a-0a57-40df-8536-0f5800e92139
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202925425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.202925425
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.481973929
Short name T310
Test name
Test status
Simulation time 25151465 ps
CPU time 0.61 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198140 kb
Host smart-3f0999b7-4f23-42eb-a49b-02dc411bf32a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481973929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.481973929
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.962692636
Short name T586
Test name
Test status
Simulation time 74136803 ps
CPU time 0.72 seconds
Started Jul 28 05:07:50 PM PDT 24
Finished Jul 28 05:07:51 PM PDT 24
Peak memory 199140 kb
Host smart-68b4de2e-8a15-424e-841a-f83ac14f7dc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962692636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.962692636
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.4199209411
Short name T422
Test name
Test status
Simulation time 183038192 ps
CPU time 0.8 seconds
Started Jul 28 05:07:45 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 209484 kb
Host smart-0442ab7e-935e-4dd8-acfc-d74a8ff52a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199209411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.4199209411
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1561922604
Short name T227
Test name
Test status
Simulation time 85196402 ps
CPU time 0.68 seconds
Started Jul 28 05:08:03 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 198204 kb
Host smart-97b60f22-6b51-456e-b890-67bdba71a80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561922604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1561922604
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1686723261
Short name T580
Test name
Test status
Simulation time 35970813 ps
CPU time 0.64 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 199384 kb
Host smart-87cab086-141d-4463-9be6-783ccb64da7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686723261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1686723261
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.3982510182
Short name T106
Test name
Test status
Simulation time 54979767 ps
CPU time 0.82 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 200156 kb
Host smart-cf5cb0c0-8935-4754-9626-80caefbf3882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982510182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.3982510182
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1368289609
Short name T140
Test name
Test status
Simulation time 66580805 ps
CPU time 0.79 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 199056 kb
Host smart-c20ec020-3dd3-4c96-8b7a-4aebf20bca9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368289609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1368289609
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.4271359520
Short name T139
Test name
Test status
Simulation time 32918857 ps
CPU time 0.6 seconds
Started Jul 28 05:07:04 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 198024 kb
Host smart-494f4e17-abb7-49cf-87f0-4c858d73c1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271359520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.4271359520
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3777690983
Short name T135
Test name
Test status
Simulation time 827489534 ps
CPU time 0.93 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:06:58 PM PDT 24
Peak memory 198056 kb
Host smart-79584df6-97f2-40b5-b23d-5eab367e6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777690983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3777690983
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1564665218
Short name T246
Test name
Test status
Simulation time 48194747 ps
CPU time 0.72 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 197344 kb
Host smart-6f57b8b5-f258-4736-a457-642d8d15a88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564665218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1564665218
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.881415888
Short name T363
Test name
Test status
Simulation time 85422869 ps
CPU time 0.63 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 198152 kb
Host smart-c4d68fe6-15f3-4f98-96fb-ddf08245dcc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881415888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.881415888
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.30767629
Short name T179
Test name
Test status
Simulation time 54205787 ps
CPU time 0.69 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 201404 kb
Host smart-883479f3-8e5d-4482-96bd-d2f16c4bd7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.30767629
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1821927626
Short name T294
Test name
Test status
Simulation time 293375874 ps
CPU time 0.72 seconds
Started Jul 28 05:06:59 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 198432 kb
Host smart-c00910b9-4f6a-40b0-b978-a28bd481612a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821927626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1821927626
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3556720515
Short name T333
Test name
Test status
Simulation time 171914477 ps
CPU time 0.78 seconds
Started Jul 28 05:07:10 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 201368 kb
Host smart-31459bee-f6f1-4661-bc99-94cd282cb24b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556720515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3556720515
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1221059623
Short name T31
Test name
Test status
Simulation time 770915153 ps
CPU time 1.74 seconds
Started Jul 28 05:07:01 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 217768 kb
Host smart-2309061b-6710-436a-be4d-0aa225e382f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221059623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1221059623
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2234743605
Short name T600
Test name
Test status
Simulation time 90381944 ps
CPU time 0.81 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 199212 kb
Host smart-b681a6b3-e28d-4c6e-9e0e-b4f08a02d743
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234743605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2234743605
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.4128681073
Short name T439
Test name
Test status
Simulation time 59235489 ps
CPU time 0.65 seconds
Started Jul 28 05:07:07 PM PDT 24
Finished Jul 28 05:07:08 PM PDT 24
Peak memory 198504 kb
Host smart-80669520-84e7-46f9-b088-762a13d04fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128681073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.4128681073
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.473410067
Short name T104
Test name
Test status
Simulation time 36818018 ps
CPU time 0.59 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 198520 kb
Host smart-bee7bd96-1f7d-4e8b-b5fa-50eaba964c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473410067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.473410067
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.2976984351
Short name T207
Test name
Test status
Simulation time 56967783 ps
CPU time 0.78 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 199056 kb
Host smart-f69f6c33-129d-4881-9d9a-c436774f8626
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976984351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.2976984351
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1360372748
Short name T387
Test name
Test status
Simulation time 30103243 ps
CPU time 0.62 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198012 kb
Host smart-8eb976b6-e43e-4fd9-9bbd-8a500b350331
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360372748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1360372748
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.3089975517
Short name T502
Test name
Test status
Simulation time 161875042 ps
CPU time 0.94 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198080 kb
Host smart-b7faf1ea-804a-4013-a749-961c8ad0284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089975517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.3089975517
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2968463454
Short name T567
Test name
Test status
Simulation time 48047331 ps
CPU time 0.67 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 198104 kb
Host smart-f5ae1b3e-aba5-4422-8ca6-1591659d9e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968463454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2968463454
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.499411407
Short name T536
Test name
Test status
Simulation time 82575730 ps
CPU time 0.62 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 198400 kb
Host smart-d251147c-e317-4844-896f-854b9b72aaea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499411407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.499411407
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2051172187
Short name T211
Test name
Test status
Simulation time 152069954 ps
CPU time 0.66 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 201340 kb
Host smart-55abde7f-6bae-49dd-abdd-14d826257b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051172187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2051172187
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1448964310
Short name T362
Test name
Test status
Simulation time 89047158 ps
CPU time 0.61 seconds
Started Jul 28 05:07:51 PM PDT 24
Finished Jul 28 05:07:52 PM PDT 24
Peak memory 198216 kb
Host smart-e2db536c-1218-4350-8399-cbb5e9071ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448964310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1448964310
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3869232140
Short name T260
Test name
Test status
Simulation time 163414911 ps
CPU time 0.79 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 209472 kb
Host smart-bd2ac931-9add-436d-b634-967a365d20e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869232140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3869232140
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2466965044
Short name T474
Test name
Test status
Simulation time 104016827 ps
CPU time 0.74 seconds
Started Jul 28 05:07:54 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 198108 kb
Host smart-ba9ca27c-cbbf-4d6e-b5b8-0e1007459dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466965044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2466965044
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1887706976
Short name T318
Test name
Test status
Simulation time 31399832 ps
CPU time 0.67 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:05 PM PDT 24
Peak memory 199344 kb
Host smart-ba913823-cd31-400d-9708-60a17b28cad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887706976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1887706976
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.2048033406
Short name T493
Test name
Test status
Simulation time 377830254 ps
CPU time 1.29 seconds
Started Jul 28 05:07:53 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 201136 kb
Host smart-bb949cec-b378-48ed-9f68-4177401faa4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048033406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2048033406
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3385131240
Short name T128
Test name
Test status
Simulation time 55428750 ps
CPU time 0.73 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 198928 kb
Host smart-a29b58f3-ec6d-4876-a07f-bc4fe9d8f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385131240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3385131240
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4058819101
Short name T144
Test name
Test status
Simulation time 67830000 ps
CPU time 0.83 seconds
Started Jul 28 05:07:53 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 198564 kb
Host smart-c3827814-2a1e-4668-82ab-629ee4a63e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058819101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.4058819101
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2579212608
Short name T278
Test name
Test status
Simulation time 30913899 ps
CPU time 0.65 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 197304 kb
Host smart-b29381e1-6a87-49a9-8452-8de96f9a9d90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579212608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2579212608
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.2113539787
Short name T483
Test name
Test status
Simulation time 837766511 ps
CPU time 0.94 seconds
Started Jul 28 05:07:55 PM PDT 24
Finished Jul 28 05:07:56 PM PDT 24
Peak memory 198520 kb
Host smart-fe3402c4-6767-48eb-a192-658840b82c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113539787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2113539787
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2488468861
Short name T240
Test name
Test status
Simulation time 53734454 ps
CPU time 0.59 seconds
Started Jul 28 05:07:50 PM PDT 24
Finished Jul 28 05:07:51 PM PDT 24
Peak memory 197416 kb
Host smart-703ead28-5ed5-43b8-a4ec-d86cb61ae9d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488468861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2488468861
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.383862090
Short name T492
Test name
Test status
Simulation time 173092664 ps
CPU time 0.59 seconds
Started Jul 28 05:08:23 PM PDT 24
Finished Jul 28 05:08:24 PM PDT 24
Peak memory 198096 kb
Host smart-1a20d902-1998-436d-a733-f5fa7d4077d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383862090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.383862090
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2267463506
Short name T467
Test name
Test status
Simulation time 56334690 ps
CPU time 0.69 seconds
Started Jul 28 05:07:52 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 198260 kb
Host smart-66f771a2-4110-4765-a375-cdf509d0c8dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267463506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2267463506
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3758593192
Short name T553
Test name
Test status
Simulation time 101801069 ps
CPU time 0.95 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 209564 kb
Host smart-f1cc62dd-4dae-4816-af46-c7d568a84f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758593192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3758593192
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2921449087
Short name T329
Test name
Test status
Simulation time 110573041 ps
CPU time 0.75 seconds
Started Jul 28 05:07:47 PM PDT 24
Finished Jul 28 05:07:48 PM PDT 24
Peak memory 198156 kb
Host smart-efcd7ad2-1c95-411a-a63c-9c6181a11896
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921449087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2921449087
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1784375238
Short name T295
Test name
Test status
Simulation time 178630210 ps
CPU time 0.62 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 198556 kb
Host smart-dc1bf4c4-f4c5-497d-b9df-cb87c85eabe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784375238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1784375238
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2675305819
Short name T40
Test name
Test status
Simulation time 37446536 ps
CPU time 0.59 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 197324 kb
Host smart-67082f4c-03a7-4df2-962e-7d1a571b2606
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675305819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2675305819
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.3680839916
Short name T36
Test name
Test status
Simulation time 168649117 ps
CPU time 0.96 seconds
Started Jul 28 05:08:12 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 198432 kb
Host smart-e20d3bea-dd35-4010-90cb-4871c88bbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680839916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3680839916
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2230871067
Short name T444
Test name
Test status
Simulation time 105912103 ps
CPU time 0.6 seconds
Started Jul 28 05:07:52 PM PDT 24
Finished Jul 28 05:07:53 PM PDT 24
Peak memory 198084 kb
Host smart-20e44979-9fbe-4763-ba63-ebf09823c739
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230871067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2230871067
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.74274672
Short name T243
Test name
Test status
Simulation time 40655357 ps
CPU time 0.59 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 198096 kb
Host smart-6548f94e-8d12-4c6c-825c-fd7f0b01dd8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74274672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.74274672
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3039742528
Short name T170
Test name
Test status
Simulation time 69916257 ps
CPU time 0.66 seconds
Started Jul 28 05:07:51 PM PDT 24
Finished Jul 28 05:07:52 PM PDT 24
Peak memory 201436 kb
Host smart-a8a4aba0-27c7-4471-8d89-6afb84b2ab2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039742528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3039742528
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.847185011
Short name T335
Test name
Test status
Simulation time 32566294 ps
CPU time 0.64 seconds
Started Jul 28 05:07:53 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 199164 kb
Host smart-9da69c84-5c29-453b-8c96-a2fcea257d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847185011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.847185011
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.619551629
Short name T436
Test name
Test status
Simulation time 110971653 ps
CPU time 1.09 seconds
Started Jul 28 05:07:59 PM PDT 24
Finished Jul 28 05:08:00 PM PDT 24
Peak memory 209424 kb
Host smart-6f362901-3301-4fbd-938c-b7df5c181adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619551629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.619551629
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.2718974464
Short name T150
Test name
Test status
Simulation time 48616743 ps
CPU time 0.64 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198624 kb
Host smart-022250ba-152c-4190-8010-1582e6327517
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718974464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.2718974464
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3341422492
Short name T593
Test name
Test status
Simulation time 179855316 ps
CPU time 0.87 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199244 kb
Host smart-bf4ea635-2af8-449e-8d28-a588e4694db7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341422492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3341422492
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.135623933
Short name T607
Test name
Test status
Simulation time 60953683 ps
CPU time 0.63 seconds
Started Jul 28 05:07:53 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 198484 kb
Host smart-150c0375-d914-4147-a982-0f2ba3b998c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135623933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.135623933
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.464845184
Short name T564
Test name
Test status
Simulation time 79008703 ps
CPU time 0.91 seconds
Started Jul 28 05:07:48 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 200068 kb
Host smart-0718278b-72f2-4518-a0c3-14b4198eef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464845184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.464845184
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.1830475326
Short name T161
Test name
Test status
Simulation time 48775911 ps
CPU time 0.75 seconds
Started Jul 28 05:08:12 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 198564 kb
Host smart-dcee2ab5-827e-4e80-bfe5-902c6d1ea83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830475326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.1830475326
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3344852665
Short name T510
Test name
Test status
Simulation time 41195782 ps
CPU time 0.58 seconds
Started Jul 28 05:07:55 PM PDT 24
Finished Jul 28 05:07:56 PM PDT 24
Peak memory 198096 kb
Host smart-d700a43d-7664-4389-a8d1-840809151940
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344852665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.3344852665
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.982276720
Short name T296
Test name
Test status
Simulation time 598972131 ps
CPU time 0.95 seconds
Started Jul 28 05:08:16 PM PDT 24
Finished Jul 28 05:08:17 PM PDT 24
Peak memory 198624 kb
Host smart-44389c1e-a9c7-45b6-be23-ab0ecc8773ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982276720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.982276720
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.3839430785
Short name T232
Test name
Test status
Simulation time 74562139 ps
CPU time 0.59 seconds
Started Jul 28 05:08:19 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 198112 kb
Host smart-060f8096-c4f2-4236-81a1-6773f15817f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839430785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.3839430785
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.344333601
Short name T413
Test name
Test status
Simulation time 27295820 ps
CPU time 0.59 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 198096 kb
Host smart-2a67f773-d9c0-4dc4-bd6b-90b370cf468a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344333601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.344333601
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2292374509
Short name T175
Test name
Test status
Simulation time 82013249 ps
CPU time 0.66 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 201420 kb
Host smart-f3dc5c3f-c233-42f1-a260-58ee612aa1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292374509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2292374509
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.2450120930
Short name T242
Test name
Test status
Simulation time 71183177 ps
CPU time 0.86 seconds
Started Jul 28 05:07:49 PM PDT 24
Finished Jul 28 05:07:50 PM PDT 24
Peak memory 198440 kb
Host smart-6ab02057-48f7-421a-b8fb-e50fb4b3729f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450120930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2450120930
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.2770609384
Short name T303
Test name
Test status
Simulation time 156303406 ps
CPU time 0.8 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 209508 kb
Host smart-f76169d9-a73c-4d1a-9f84-cbda433ed3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770609384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2770609384
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.690749048
Short name T286
Test name
Test status
Simulation time 73803788 ps
CPU time 0.89 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 199312 kb
Host smart-f1d0f99e-f0bb-45b3-8494-faabfe8eaadf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690749048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.690749048
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.3577684738
Short name T530
Test name
Test status
Simulation time 63307835 ps
CPU time 0.63 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 198520 kb
Host smart-bd6d82dc-306d-4b6f-b372-6a1c966fb0df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577684738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3577684738
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.703310025
Short name T101
Test name
Test status
Simulation time 23828437 ps
CPU time 0.65 seconds
Started Jul 28 05:08:20 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 198716 kb
Host smart-f228433e-533f-4e87-be5f-793e3cc83445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703310025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.703310025
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.229069878
Short name T158
Test name
Test status
Simulation time 50888651 ps
CPU time 0.75 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198280 kb
Host smart-6705e450-4d70-4b52-a509-8b86bcf03333
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229069878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disa
ble_rom_integrity_check.229069878
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3601827005
Short name T343
Test name
Test status
Simulation time 42097254 ps
CPU time 0.6 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 198024 kb
Host smart-f8801b44-988c-4f5f-b44f-b51703528975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601827005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3601827005
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.1966426625
Short name T572
Test name
Test status
Simulation time 304791311 ps
CPU time 0.91 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 198184 kb
Host smart-583d70b8-5839-4899-9cda-6f536b36e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966426625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1966426625
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.626397965
Short name T4
Test name
Test status
Simulation time 22760459 ps
CPU time 0.65 seconds
Started Jul 28 05:07:59 PM PDT 24
Finished Jul 28 05:07:59 PM PDT 24
Peak memory 198084 kb
Host smart-d77ee726-28b3-4f48-af64-d8d2f72a75e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626397965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.626397965
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.4260916905
Short name T218
Test name
Test status
Simulation time 35689819 ps
CPU time 0.61 seconds
Started Jul 28 05:08:06 PM PDT 24
Finished Jul 28 05:08:07 PM PDT 24
Peak memory 198116 kb
Host smart-775ca38c-0ba8-4b55-963e-d65880aad93d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260916905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.4260916905
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.2096779901
Short name T538
Test name
Test status
Simulation time 104117619 ps
CPU time 0.67 seconds
Started Jul 28 05:08:19 PM PDT 24
Finished Jul 28 05:08:20 PM PDT 24
Peak memory 201444 kb
Host smart-4277195a-5704-4a7e-a24d-14b2440f27de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096779901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.2096779901
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2316011661
Short name T371
Test name
Test status
Simulation time 68430164 ps
CPU time 0.74 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199416 kb
Host smart-c5dff70d-1641-495b-affd-6c29cced2b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316011661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2316011661
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.4119411766
Short name T466
Test name
Test status
Simulation time 147573176 ps
CPU time 0.81 seconds
Started Jul 28 05:08:24 PM PDT 24
Finished Jul 28 05:08:25 PM PDT 24
Peak memory 209504 kb
Host smart-737f1593-e1a7-4dab-8e91-9ec09284fdba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119411766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.4119411766
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.872971748
Short name T220
Test name
Test status
Simulation time 82831952 ps
CPU time 0.79 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199240 kb
Host smart-a85c6159-524a-45bd-974b-b50db38f479e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872971748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_
mubi.872971748
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.4059860425
Short name T625
Test name
Test status
Simulation time 58135724 ps
CPU time 0.61 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 198544 kb
Host smart-adb4e01f-5f51-41a0-9903-91d39c3ffce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059860425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.4059860425
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3323581768
Short name T506
Test name
Test status
Simulation time 59326589 ps
CPU time 0.81 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 199996 kb
Host smart-e1353364-459f-4747-a3a5-04ab332848b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323581768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3323581768
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.4033403279
Short name T204
Test name
Test status
Simulation time 51007667 ps
CPU time 0.77 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 199204 kb
Host smart-99ce3cdf-c01a-4a4c-9ab0-8823ec5e0f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033403279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.4033403279
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.773414548
Short name T485
Test name
Test status
Simulation time 32694597 ps
CPU time 0.59 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198028 kb
Host smart-4ac76c01-44bc-4318-8cfb-b4289c06264a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773414548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.773414548
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2622490587
Short name T12
Test name
Test status
Simulation time 540466620 ps
CPU time 0.95 seconds
Started Jul 28 05:08:16 PM PDT 24
Finished Jul 28 05:08:22 PM PDT 24
Peak memory 198368 kb
Host smart-2f02751a-8370-4ed3-805d-d0408f127ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622490587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2622490587
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.1570362941
Short name T225
Test name
Test status
Simulation time 55585066 ps
CPU time 0.66 seconds
Started Jul 28 05:08:07 PM PDT 24
Finished Jul 28 05:08:07 PM PDT 24
Peak memory 198072 kb
Host smart-7b6dfbd2-9a8d-4800-a3d6-7d29708f9733
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570362941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1570362941
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.232485996
Short name T346
Test name
Test status
Simulation time 35659522 ps
CPU time 0.57 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 198444 kb
Host smart-8131f1b6-2393-41ae-976b-a3af20373576
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232485996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.232485996
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.318111958
Short name T535
Test name
Test status
Simulation time 43395768 ps
CPU time 0.72 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 201376 kb
Host smart-cb791346-8953-4af2-bfb4-0a72cff8a4b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318111958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.318111958
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.2833762667
Short name T49
Test name
Test status
Simulation time 42053779 ps
CPU time 0.7 seconds
Started Jul 28 05:08:08 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 198276 kb
Host smart-85a2eb24-ad54-4cc6-8e18-70adf1f34601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833762667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.2833762667
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1863914877
Short name T560
Test name
Test status
Simulation time 64856358 ps
CPU time 0.71 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 198292 kb
Host smart-e44e193e-f6f3-4127-8c59-063b3e666853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863914877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1863914877
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.163992902
Short name T314
Test name
Test status
Simulation time 107905485 ps
CPU time 1.06 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 209452 kb
Host smart-ea944a54-9236-4186-b628-7ac56b417c16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163992902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.163992902
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1986384937
Short name T228
Test name
Test status
Simulation time 79455913 ps
CPU time 0.77 seconds
Started Jul 28 05:08:00 PM PDT 24
Finished Jul 28 05:08:01 PM PDT 24
Peak memory 197896 kb
Host smart-cdb57d6c-44f7-4f0e-a957-92b0389ab157
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986384937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1986384937
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.3058829878
Short name T67
Test name
Test status
Simulation time 85340022 ps
CPU time 0.64 seconds
Started Jul 28 05:07:59 PM PDT 24
Finished Jul 28 05:08:00 PM PDT 24
Peak memory 198592 kb
Host smart-25d00eb1-240c-403f-b072-95efe1839ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058829878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.3058829878
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.956701470
Short name T97
Test name
Test status
Simulation time 25315968 ps
CPU time 0.9 seconds
Started Jul 28 05:08:12 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 200756 kb
Host smart-12c789fa-bf3f-4785-b9cf-1c9ac18c1401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956701470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.956701470
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3823907323
Short name T431
Test name
Test status
Simulation time 95223437 ps
CPU time 0.71 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:06 PM PDT 24
Peak memory 198376 kb
Host smart-507d160d-58cd-45b4-885f-531e3c7264d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823907323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3823907323
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1031379803
Short name T322
Test name
Test status
Simulation time 39048608 ps
CPU time 0.59 seconds
Started Jul 28 05:08:30 PM PDT 24
Finished Jul 28 05:08:31 PM PDT 24
Peak memory 197308 kb
Host smart-3c025901-5157-4f7b-82f3-108a165de4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031379803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1031379803
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2225364608
Short name T381
Test name
Test status
Simulation time 158867010 ps
CPU time 1.04 seconds
Started Jul 28 05:08:29 PM PDT 24
Finished Jul 28 05:08:30 PM PDT 24
Peak memory 198080 kb
Host smart-d5dd1555-edc8-48a8-8825-3440aba3956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225364608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2225364608
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.1411951258
Short name T368
Test name
Test status
Simulation time 64263254 ps
CPU time 0.67 seconds
Started Jul 28 05:08:12 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 198028 kb
Host smart-cf318c79-b973-426e-8bcd-25d09f337eba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411951258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1411951258
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.61015529
Short name T216
Test name
Test status
Simulation time 33532992 ps
CPU time 0.61 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198088 kb
Host smart-c18dfd77-4a7e-4e18-a63b-aad9f409cfa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61015529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.61015529
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.963178846
Short name T168
Test name
Test status
Simulation time 94206948 ps
CPU time 0.64 seconds
Started Jul 28 05:08:05 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 201348 kb
Host smart-c5b6bbe5-1bc3-4ea0-bf82-94e75e776d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963178846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invali
d.963178846
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.846797601
Short name T306
Test name
Test status
Simulation time 94794207 ps
CPU time 0.79 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 199144 kb
Host smart-21998088-b85c-432d-9d64-8ae2eacfbe98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846797601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.846797601
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2684979278
Short name T236
Test name
Test status
Simulation time 149642493 ps
CPU time 0.81 seconds
Started Jul 28 05:08:08 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 199244 kb
Host smart-341215cf-105e-4fa3-8687-e1c67e2f82eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684979278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2684979278
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1893725404
Short name T337
Test name
Test status
Simulation time 39741194 ps
CPU time 0.63 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 199332 kb
Host smart-38edb37f-44f1-424c-b0e3-a0806ffd2050
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893725404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1893725404
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.82633350
Short name T171
Test name
Test status
Simulation time 56208294 ps
CPU time 0.77 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199036 kb
Host smart-ceb0789b-7a92-4756-a365-2f53f9fdb74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82633350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.82633350
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1987914243
Short name T541
Test name
Test status
Simulation time 54905445 ps
CPU time 0.82 seconds
Started Jul 28 05:08:21 PM PDT 24
Finished Jul 28 05:08:22 PM PDT 24
Peak memory 199176 kb
Host smart-1824d6aa-1b04-41a7-8ab6-245a924db581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987914243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1987914243
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1790976014
Short name T554
Test name
Test status
Simulation time 31913666 ps
CPU time 0.6 seconds
Started Jul 28 05:07:56 PM PDT 24
Finished Jul 28 05:07:57 PM PDT 24
Peak memory 197988 kb
Host smart-d46e1659-9937-4a47-8ca3-a05097523a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790976014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1790976014
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3264423688
Short name T270
Test name
Test status
Simulation time 635597388 ps
CPU time 1.04 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198056 kb
Host smart-ef06663d-76db-481e-8a85-a9ee065da5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264423688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3264423688
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3988135952
Short name T360
Test name
Test status
Simulation time 58279497 ps
CPU time 0.64 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 198048 kb
Host smart-d453d7d8-7077-4fe6-938d-d879623442ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988135952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3988135952
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3953577427
Short name T379
Test name
Test status
Simulation time 43908770 ps
CPU time 0.58 seconds
Started Jul 28 05:08:37 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 198068 kb
Host smart-6d6c3fa4-1bef-45b6-9c76-7f7375c11501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953577427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3953577427
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2048609313
Short name T89
Test name
Test status
Simulation time 56753751 ps
CPU time 0.64 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 201408 kb
Host smart-2e8cbbee-b6fa-4f15-a7d5-ce0e45a0a2f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048609313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2048609313
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.535929736
Short name T359
Test name
Test status
Simulation time 69716293 ps
CPU time 0.88 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 198536 kb
Host smart-42fb8005-9bf8-4fb8-85ab-358c5877ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535929736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.535929736
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.228560268
Short name T336
Test name
Test status
Simulation time 150575508 ps
CPU time 0.83 seconds
Started Jul 28 05:08:34 PM PDT 24
Finished Jul 28 05:08:34 PM PDT 24
Peak memory 209492 kb
Host smart-4a2223ee-7a0a-4593-a51f-5671add64ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228560268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.228560268
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.19336716
Short name T573
Test name
Test status
Simulation time 78262570 ps
CPU time 0.81 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 198964 kb
Host smart-61154e32-e978-4cf4-90db-8ae79ef75ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.19336716
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.4002896358
Short name T435
Test name
Test status
Simulation time 32311807 ps
CPU time 0.7 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 199480 kb
Host smart-6d52a14c-9192-42f8-b127-86b699f90f00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002896358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.4002896358
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.1442579511
Short name T14
Test name
Test status
Simulation time 33526244 ps
CPU time 0.84 seconds
Started Jul 28 05:08:08 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 198968 kb
Host smart-a8504137-07dc-442d-b786-ad80a2819f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442579511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1442579511
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3506629296
Short name T514
Test name
Test status
Simulation time 55919478 ps
CPU time 0.74 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199264 kb
Host smart-180a188a-3a7d-4798-97c9-e43e13ca4c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506629296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3506629296
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1830699401
Short name T429
Test name
Test status
Simulation time 51244935 ps
CPU time 0.61 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 198012 kb
Host smart-785541e5-86e8-4b01-b2c3-e12cc82f36d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830699401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1830699401
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.823469236
Short name T384
Test name
Test status
Simulation time 223716457 ps
CPU time 0.92 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 198472 kb
Host smart-cdf632da-931a-4f45-80b3-c2858a28b11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823469236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.823469236
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.239015205
Short name T288
Test name
Test status
Simulation time 33428136 ps
CPU time 0.63 seconds
Started Jul 28 05:08:08 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 198120 kb
Host smart-686c3a74-22be-4f86-b8e9-15302986cbf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239015205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.239015205
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3119306272
Short name T68
Test name
Test status
Simulation time 45729402 ps
CPU time 0.64 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 198384 kb
Host smart-62e3d1be-a832-470d-85f4-b7eb51d1bc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119306272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3119306272
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3859955514
Short name T183
Test name
Test status
Simulation time 67807097 ps
CPU time 0.67 seconds
Started Jul 28 05:08:01 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 201416 kb
Host smart-e0e8b678-2eb3-45db-8b3a-9ca58e0a4b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859955514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3859955514
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1006566495
Short name T588
Test name
Test status
Simulation time 37173525 ps
CPU time 0.66 seconds
Started Jul 28 05:08:04 PM PDT 24
Finished Jul 28 05:08:05 PM PDT 24
Peak memory 198152 kb
Host smart-2e20052c-b217-483c-9240-6debfdff4163
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006566495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1006566495
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.4002994552
Short name T235
Test name
Test status
Simulation time 114560280 ps
CPU time 0.87 seconds
Started Jul 28 05:08:17 PM PDT 24
Finished Jul 28 05:08:18 PM PDT 24
Peak memory 209392 kb
Host smart-61bf702e-6277-49e9-bdcf-eadc036dfb74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002994552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.4002994552
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3800640999
Short name T487
Test name
Test status
Simulation time 69279233 ps
CPU time 0.98 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 199284 kb
Host smart-2fc6b0a0-fe6b-43df-946e-8ed66d0fe5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800640999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3800640999
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2190670682
Short name T622
Test name
Test status
Simulation time 49304884 ps
CPU time 0.64 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 199304 kb
Host smart-3112770d-ae47-4af1-ac6a-67289431c03c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190670682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2190670682
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2961763603
Short name T461
Test name
Test status
Simulation time 106350751 ps
CPU time 0.83 seconds
Started Jul 28 05:08:10 PM PDT 24
Finished Jul 28 05:08:11 PM PDT 24
Peak memory 198984 kb
Host smart-abb82a61-335c-48c0-a85a-a48b13db86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961763603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2961763603
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1738678907
Short name T391
Test name
Test status
Simulation time 99761839 ps
CPU time 0.64 seconds
Started Jul 28 05:08:19 PM PDT 24
Finished Jul 28 05:08:20 PM PDT 24
Peak memory 199152 kb
Host smart-b61a667d-ab24-457e-b0bd-e02e5ab0374e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738678907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.1738678907
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.1640396668
Short name T425
Test name
Test status
Simulation time 33707438 ps
CPU time 0.6 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 198076 kb
Host smart-9620757d-cd62-4b18-a021-c3c332153280
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640396668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.1640396668
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1843398284
Short name T402
Test name
Test status
Simulation time 166407211 ps
CPU time 0.98 seconds
Started Jul 28 05:08:36 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 198360 kb
Host smart-22c41529-3ec5-4ca1-b7d0-f470c69dcda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843398284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1843398284
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.916530725
Short name T356
Test name
Test status
Simulation time 35927419 ps
CPU time 0.61 seconds
Started Jul 28 05:08:09 PM PDT 24
Finished Jul 28 05:08:10 PM PDT 24
Peak memory 198100 kb
Host smart-122db468-133f-49dd-a3d0-aa07d70d33c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916530725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.916530725
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3318793606
Short name T380
Test name
Test status
Simulation time 58877538 ps
CPU time 0.6 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 197952 kb
Host smart-b01d8414-a1c6-4b3d-9f17-70980abae7a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318793606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3318793606
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.871834457
Short name T196
Test name
Test status
Simulation time 49792707 ps
CPU time 0.65 seconds
Started Jul 28 05:08:23 PM PDT 24
Finished Jul 28 05:08:24 PM PDT 24
Peak memory 201436 kb
Host smart-c62f7611-b53e-4edf-84b5-eefdc25cb48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871834457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.871834457
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1303236558
Short name T627
Test name
Test status
Simulation time 49127968 ps
CPU time 0.78 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 199192 kb
Host smart-61e22e2e-dd61-46b7-bdb2-7cd375a683d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303236558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1303236558
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1750088085
Short name T229
Test name
Test status
Simulation time 117588594 ps
CPU time 0.87 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 201308 kb
Host smart-7349b4ec-2686-45ac-8dd9-07dea465b6e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750088085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1750088085
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2820754512
Short name T498
Test name
Test status
Simulation time 121851421 ps
CPU time 0.71 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198080 kb
Host smart-0a0b6b35-ca76-48be-9574-c27aab3758d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820754512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2820754512
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.212144811
Short name T407
Test name
Test status
Simulation time 52217091 ps
CPU time 0.68 seconds
Started Jul 28 05:08:08 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 199440 kb
Host smart-bfc7c916-d28b-4119-9470-fb2d8393751f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212144811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.212144811
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.655438217
Short name T55
Test name
Test status
Simulation time 196931674 ps
CPU time 0.86 seconds
Started Jul 28 05:07:12 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 200164 kb
Host smart-13c1dbec-776d-4c31-8482-69e8c4927b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655438217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.655438217
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.491369712
Short name T330
Test name
Test status
Simulation time 51585330 ps
CPU time 0.77 seconds
Started Jul 28 05:07:05 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 199140 kb
Host smart-04351374-3e5d-40f7-bef8-8fb4a29b3d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491369712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.491369712
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2805459735
Short name T624
Test name
Test status
Simulation time 38966103 ps
CPU time 0.58 seconds
Started Jul 28 05:07:09 PM PDT 24
Finished Jul 28 05:07:10 PM PDT 24
Peak memory 198044 kb
Host smart-2b970cb4-4a3b-4f9c-9261-1edc9b58b4c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805459735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2805459735
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.599144680
Short name T271
Test name
Test status
Simulation time 540974147 ps
CPU time 0.96 seconds
Started Jul 28 05:07:07 PM PDT 24
Finished Jul 28 05:07:08 PM PDT 24
Peak memory 198108 kb
Host smart-39f52087-2f28-41fe-b244-ec69c2792503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599144680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.599144680
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1087340054
Short name T441
Test name
Test status
Simulation time 168791686 ps
CPU time 0.61 seconds
Started Jul 28 05:07:05 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 198092 kb
Host smart-5d9f6ef6-0ec2-4f6e-888f-ffc7ec3a4da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087340054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1087340054
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.2162586189
Short name T563
Test name
Test status
Simulation time 75099083 ps
CPU time 0.61 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:07:08 PM PDT 24
Peak memory 198128 kb
Host smart-5028082b-d563-45d0-b7d9-84159e1b8d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162586189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2162586189
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1036943021
Short name T182
Test name
Test status
Simulation time 51137546 ps
CPU time 0.68 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 201388 kb
Host smart-f90566a6-063f-466b-b072-f42ad5b70f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036943021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1036943021
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.2439105377
Short name T44
Test name
Test status
Simulation time 68862756 ps
CPU time 0.79 seconds
Started Jul 28 05:07:09 PM PDT 24
Finished Jul 28 05:07:10 PM PDT 24
Peak memory 199348 kb
Host smart-5bc8be72-c356-4cea-a082-b154267aa188
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439105377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2439105377
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1946297797
Short name T426
Test name
Test status
Simulation time 223127741 ps
CPU time 0.84 seconds
Started Jul 28 05:07:07 PM PDT 24
Finished Jul 28 05:07:08 PM PDT 24
Peak memory 209528 kb
Host smart-ccaa8196-c595-4af0-a8e3-1cd95680947b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946297797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1946297797
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.4237723421
Short name T32
Test name
Test status
Simulation time 621283350 ps
CPU time 2.02 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 218744 kb
Host smart-60759877-9cce-4ad5-bcb8-f3e8e36109f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237723421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4237723421
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2235439726
Short name T601
Test name
Test status
Simulation time 281487608 ps
CPU time 0.68 seconds
Started Jul 28 05:07:05 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 198184 kb
Host smart-68314e4a-0223-4f41-be83-49773fef135c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235439726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2235439726
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2558336683
Short name T255
Test name
Test status
Simulation time 29268612 ps
CPU time 0.76 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 199412 kb
Host smart-cc4de233-1465-4b21-9141-8f2c4ecae108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558336683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2558336683
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2106784837
Short name T5
Test name
Test status
Simulation time 71287199 ps
CPU time 0.61 seconds
Started Jul 28 05:08:31 PM PDT 24
Finished Jul 28 05:08:32 PM PDT 24
Peak memory 198844 kb
Host smart-74c88e4f-d61b-455e-966f-fad6d833fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106784837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2106784837
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.355134520
Short name T28
Test name
Test status
Simulation time 52959046 ps
CPU time 0.69 seconds
Started Jul 28 05:08:27 PM PDT 24
Finished Jul 28 05:08:27 PM PDT 24
Peak memory 199104 kb
Host smart-01fbd356-61da-49db-b0d3-4a1505e4d04e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355134520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.355134520
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.4010783032
Short name T582
Test name
Test status
Simulation time 86038045 ps
CPU time 0.58 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 197308 kb
Host smart-71425fac-b024-47b7-961d-bb68570bcadd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010783032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.4010783032
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.991958637
Short name T504
Test name
Test status
Simulation time 607833923 ps
CPU time 0.93 seconds
Started Jul 28 05:08:24 PM PDT 24
Finished Jul 28 05:08:25 PM PDT 24
Peak memory 198164 kb
Host smart-579d1ce5-e3b4-4ebe-b978-7bafbb5b02a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991958637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.991958637
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2244516115
Short name T547
Test name
Test status
Simulation time 61822312 ps
CPU time 0.6 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 197332 kb
Host smart-f316c7d2-c7ab-40ed-a077-d686177ccdfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244516115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2244516115
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3707478531
Short name T370
Test name
Test status
Simulation time 22140513 ps
CPU time 0.59 seconds
Started Jul 28 05:08:19 PM PDT 24
Finished Jul 28 05:08:20 PM PDT 24
Peak memory 198080 kb
Host smart-775a231d-74cf-4731-99a2-66a26f389452
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707478531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3707478531
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3448574644
Short name T185
Test name
Test status
Simulation time 44804213 ps
CPU time 0.71 seconds
Started Jul 28 05:08:20 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 201360 kb
Host smart-b809258b-a177-44fe-a075-e6ff86195643
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448574644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.3448574644
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.3812761540
Short name T376
Test name
Test status
Simulation time 74638195 ps
CPU time 0.91 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 199068 kb
Host smart-483504ab-5b97-4870-a460-7bfc5715402a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812761540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3812761540
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3346705594
Short name T409
Test name
Test status
Simulation time 146118734 ps
CPU time 0.82 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 209528 kb
Host smart-8f1860c9-65fd-4099-8039-7e742ee0f19d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346705594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3346705594
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3982204846
Short name T87
Test name
Test status
Simulation time 107763586 ps
CPU time 0.71 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 198132 kb
Host smart-99e326a2-e5e1-498d-b619-1b3f0d342d6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982204846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3982204846
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.583621316
Short name T297
Test name
Test status
Simulation time 33898052 ps
CPU time 0.64 seconds
Started Jul 28 05:08:02 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 198480 kb
Host smart-1858f5cc-6e60-4f85-b8ff-da29a34fbf92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583621316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.583621316
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.234490115
Short name T272
Test name
Test status
Simulation time 33725323 ps
CPU time 0.65 seconds
Started Jul 28 05:08:39 PM PDT 24
Finished Jul 28 05:08:40 PM PDT 24
Peak memory 198640 kb
Host smart-ee26d369-2ab1-4bd7-9ddc-2efb05edcc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234490115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.234490115
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.2222019952
Short name T416
Test name
Test status
Simulation time 95392465 ps
CPU time 0.67 seconds
Started Jul 28 05:08:20 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 198460 kb
Host smart-ad49de33-8527-4a46-8fe1-1a379873cb39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222019952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.2222019952
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2389248341
Short name T418
Test name
Test status
Simulation time 28536057 ps
CPU time 0.61 seconds
Started Jul 28 05:08:20 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 197376 kb
Host smart-d5523625-134e-4b5e-8e6c-7f9ed73c0a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389248341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2389248341
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1819560114
Short name T486
Test name
Test status
Simulation time 159269973 ps
CPU time 0.93 seconds
Started Jul 28 05:08:40 PM PDT 24
Finished Jul 28 05:08:41 PM PDT 24
Peak memory 198140 kb
Host smart-9722fd53-10e0-4292-a1b1-28a5368ec6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819560114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1819560114
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3660678943
Short name T463
Test name
Test status
Simulation time 29695206 ps
CPU time 0.61 seconds
Started Jul 28 05:08:27 PM PDT 24
Finished Jul 28 05:08:28 PM PDT 24
Peak memory 198052 kb
Host smart-aa8c63c4-128c-4397-a56b-91b42cabd49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660678943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3660678943
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.31868437
Short name T455
Test name
Test status
Simulation time 67037079 ps
CPU time 0.62 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 198100 kb
Host smart-4829853d-c79a-43bd-ab5c-167e284a2c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.31868437
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1419717803
Short name T576
Test name
Test status
Simulation time 72107067 ps
CPU time 0.72 seconds
Started Jul 28 05:08:37 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 201420 kb
Host smart-ae702e7c-c78d-4ffa-89c9-7ba9252afc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419717803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.1419717803
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3399292822
Short name T369
Test name
Test status
Simulation time 111821410 ps
CPU time 0.73 seconds
Started Jul 28 05:08:38 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 199100 kb
Host smart-b93b5c5a-d82e-4c8d-8d38-721638fa7611
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399292822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3399292822
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1633952333
Short name T267
Test name
Test status
Simulation time 115571283 ps
CPU time 0.97 seconds
Started Jul 28 05:08:30 PM PDT 24
Finished Jul 28 05:08:31 PM PDT 24
Peak memory 209528 kb
Host smart-1f470b9d-e8e8-481e-90bb-c75f15e28587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633952333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1633952333
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3344631169
Short name T284
Test name
Test status
Simulation time 52429438 ps
CPU time 0.84 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 199272 kb
Host smart-dd8c29d2-a3ee-44e2-b4ce-634ad5ced9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344631169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3344631169
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3481889041
Short name T548
Test name
Test status
Simulation time 51931905 ps
CPU time 0.62 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 198500 kb
Host smart-124c307f-335a-4ad4-82b6-a6dcb8bc76db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481889041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3481889041
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.1216345422
Short name T181
Test name
Test status
Simulation time 42899702 ps
CPU time 0.74 seconds
Started Jul 28 05:08:14 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 199932 kb
Host smart-92deb247-701a-46fd-bb7d-1977185a29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216345422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1216345422
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1824851013
Short name T142
Test name
Test status
Simulation time 68603859 ps
CPU time 0.82 seconds
Started Jul 28 05:08:25 PM PDT 24
Finished Jul 28 05:08:26 PM PDT 24
Peak memory 198520 kb
Host smart-a290a5f7-63b9-4e7f-9ef9-8dbe1a63e969
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824851013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1824851013
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.365915957
Short name T138
Test name
Test status
Simulation time 32292083 ps
CPU time 0.61 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 198056 kb
Host smart-aec45c52-17e4-4b0b-9215-c0f0e7fde8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365915957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.365915957
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.607674183
Short name T292
Test name
Test status
Simulation time 316972275 ps
CPU time 0.97 seconds
Started Jul 28 05:08:17 PM PDT 24
Finished Jul 28 05:08:18 PM PDT 24
Peak memory 198076 kb
Host smart-4a536f97-3fb6-44e6-8543-f317419e60ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607674183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.607674183
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3508323495
Short name T394
Test name
Test status
Simulation time 57907703 ps
CPU time 0.6 seconds
Started Jul 28 05:08:22 PM PDT 24
Finished Jul 28 05:08:23 PM PDT 24
Peak memory 197960 kb
Host smart-dc9b39a3-759f-4a74-9d65-ab3375f5837e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508323495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3508323495
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3656883859
Short name T307
Test name
Test status
Simulation time 76809124 ps
CPU time 0.61 seconds
Started Jul 28 05:08:42 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 198040 kb
Host smart-6e198146-01bb-4ed7-8b98-50e96c2a07ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656883859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3656883859
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.869177139
Short name T534
Test name
Test status
Simulation time 41876950 ps
CPU time 0.72 seconds
Started Jul 28 05:08:17 PM PDT 24
Finished Jul 28 05:08:18 PM PDT 24
Peak memory 201392 kb
Host smart-368bf64e-2714-41a3-a203-35351ecdfe08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869177139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.869177139
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.3582468066
Short name T399
Test name
Test status
Simulation time 36422717 ps
CPU time 0.59 seconds
Started Jul 28 05:08:22 PM PDT 24
Finished Jul 28 05:08:23 PM PDT 24
Peak memory 198112 kb
Host smart-04c406df-5266-45bb-a41c-b05142747124
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582468066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3582468066
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1394807879
Short name T464
Test name
Test status
Simulation time 151037783 ps
CPU time 0.79 seconds
Started Jul 28 05:08:17 PM PDT 24
Finished Jul 28 05:08:18 PM PDT 24
Peak memory 209476 kb
Host smart-f5a3b1f9-1fcc-4638-92bc-866c5671ab49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394807879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1394807879
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.1072953996
Short name T86
Test name
Test status
Simulation time 82546348 ps
CPU time 0.69 seconds
Started Jul 28 05:08:40 PM PDT 24
Finished Jul 28 05:08:41 PM PDT 24
Peak memory 198344 kb
Host smart-ab9d52cc-a20a-4343-8343-9aed0a67e47c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072953996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1072953996
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1885332745
Short name T604
Test name
Test status
Simulation time 38324473 ps
CPU time 0.65 seconds
Started Jul 28 05:08:25 PM PDT 24
Finished Jul 28 05:08:26 PM PDT 24
Peak memory 199428 kb
Host smart-2a7180cf-83e5-4b22-93b0-ab65dae38a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885332745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1885332745
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.2683468957
Short name T524
Test name
Test status
Simulation time 23437272 ps
CPU time 0.65 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:46 PM PDT 24
Peak memory 198688 kb
Host smart-bce1b1bd-6583-4b3a-a02c-f8a587e234e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683468957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2683468957
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2753463157
Short name T164
Test name
Test status
Simulation time 72729971 ps
CPU time 0.65 seconds
Started Jul 28 05:08:21 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 198476 kb
Host smart-0d8eab51-fa0b-4ec1-8749-95df2534fa47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753463157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2753463157
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3119338879
Short name T136
Test name
Test status
Simulation time 30413937 ps
CPU time 0.59 seconds
Started Jul 28 05:08:38 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 198060 kb
Host smart-ea884942-01bc-493b-8d76-d0e07e57e95f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119338879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3119338879
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2605856780
Short name T411
Test name
Test status
Simulation time 932692874 ps
CPU time 0.95 seconds
Started Jul 28 05:08:31 PM PDT 24
Finished Jul 28 05:08:32 PM PDT 24
Peak memory 198448 kb
Host smart-1640dea8-a7cc-421a-ba6a-0f62fd980463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605856780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2605856780
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2456074117
Short name T533
Test name
Test status
Simulation time 43196477 ps
CPU time 0.67 seconds
Started Jul 28 05:08:44 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 197388 kb
Host smart-3ac2490a-beb1-4173-9196-15ab26a03c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456074117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2456074117
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3608707310
Short name T281
Test name
Test status
Simulation time 36977944 ps
CPU time 0.63 seconds
Started Jul 28 05:08:12 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 198156 kb
Host smart-1066eb69-00af-4354-a4b6-3bf1008cd26e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608707310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3608707310
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3859413460
Short name T176
Test name
Test status
Simulation time 50796374 ps
CPU time 0.7 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 201212 kb
Host smart-384925c8-fd2c-4622-aee4-c996a5426354
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859413460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3859413460
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.693942841
Short name T3
Test name
Test status
Simulation time 65580832 ps
CPU time 0.86 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 199100 kb
Host smart-47ab5757-e27b-48c2-92d5-79d6d0f223b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693942841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.693942841
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.760299229
Short name T516
Test name
Test status
Simulation time 115105303 ps
CPU time 0.91 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 209708 kb
Host smart-713ed172-e8e8-4b1c-87be-a7d8cbaff5b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760299229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.760299229
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2985065092
Short name T344
Test name
Test status
Simulation time 84975234 ps
CPU time 0.69 seconds
Started Jul 28 05:08:33 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 198080 kb
Host smart-52078d22-e235-484d-a65c-748580a91cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985065092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2985065092
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3775365496
Short name T551
Test name
Test status
Simulation time 32892538 ps
CPU time 0.66 seconds
Started Jul 28 05:08:11 PM PDT 24
Finished Jul 28 05:08:12 PM PDT 24
Peak memory 199396 kb
Host smart-4631dde4-13c0-4188-af83-2be6669d1f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775365496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3775365496
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.586066491
Short name T417
Test name
Test status
Simulation time 33612843 ps
CPU time 0.94 seconds
Started Jul 28 05:08:15 PM PDT 24
Finished Jul 28 05:08:16 PM PDT 24
Peak memory 200728 kb
Host smart-f5b7bd8e-cd74-49e6-b9d1-3b611e936a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586066491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.586066491
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3195629432
Short name T626
Test name
Test status
Simulation time 60747750 ps
CPU time 0.8 seconds
Started Jul 28 05:08:32 PM PDT 24
Finished Jul 28 05:08:33 PM PDT 24
Peak memory 199184 kb
Host smart-bb5fe4f5-c6af-4c99-aad2-91d0eda9d317
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195629432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3195629432
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.433856
Short name T311
Test name
Test status
Simulation time 39770520 ps
CPU time 0.58 seconds
Started Jul 28 05:08:45 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 198056 kb
Host smart-7ea28705-3334-4c84-a7fb-8a2e89146a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfu
nc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_mal
func.433856
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.440023274
Short name T517
Test name
Test status
Simulation time 306970558 ps
CPU time 0.96 seconds
Started Jul 28 05:08:31 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 198108 kb
Host smart-9ba1a7b3-dae2-4e92-9877-90a1ee395d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440023274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.440023274
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.3183566173
Short name T15
Test name
Test status
Simulation time 38690463 ps
CPU time 0.65 seconds
Started Jul 28 05:08:40 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 198104 kb
Host smart-7334fd4d-4b2a-4204-a2c2-29f622f71c98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183566173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3183566173
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.4068355125
Short name T317
Test name
Test status
Simulation time 79150147 ps
CPU time 0.61 seconds
Started Jul 28 05:08:24 PM PDT 24
Finished Jul 28 05:08:25 PM PDT 24
Peak memory 198088 kb
Host smart-96543966-fcb3-49db-b04a-60634d05d3b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068355125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.4068355125
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.212731743
Short name T191
Test name
Test status
Simulation time 46668859 ps
CPU time 0.74 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 201400 kb
Host smart-2e20978b-2765-48ad-a5f4-2a4c843f6827
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212731743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invali
d.212731743
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.1067773656
Short name T184
Test name
Test status
Simulation time 29405142 ps
CPU time 0.64 seconds
Started Jul 28 05:08:53 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 199240 kb
Host smart-3915fcfa-0dbd-44a4-8fb9-02b497416c93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067773656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.1067773656
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.4045872292
Short name T34
Test name
Test status
Simulation time 44956521 ps
CPU time 0.61 seconds
Started Jul 28 05:08:39 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 198276 kb
Host smart-b681cf5b-6861-442c-b6ae-6494552f75a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045872292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.4045872292
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.3493355970
Short name T341
Test name
Test status
Simulation time 102186434 ps
CPU time 0.94 seconds
Started Jul 28 05:08:13 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 209456 kb
Host smart-4cd585ae-b414-4e88-b1d0-38c6eeb46c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493355970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3493355970
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1380774987
Short name T433
Test name
Test status
Simulation time 57272834 ps
CPU time 0.78 seconds
Started Jul 28 05:08:18 PM PDT 24
Finished Jul 28 05:08:19 PM PDT 24
Peak memory 198184 kb
Host smart-bdbb13a9-3e34-4d8b-87fe-8d2b41ee7370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380774987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1380774987
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.754148556
Short name T515
Test name
Test status
Simulation time 26778440 ps
CPU time 0.75 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 199396 kb
Host smart-0105c450-23d0-41d1-857b-159cfbf1f3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754148556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.754148556
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.143661387
Short name T129
Test name
Test status
Simulation time 29250292 ps
CPU time 1 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 200996 kb
Host smart-dc32238e-e2cb-4f02-9220-52d15dfd6482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143661387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.143661387
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.638084159
Short name T353
Test name
Test status
Simulation time 64081094 ps
CPU time 0.69 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198456 kb
Host smart-0a8b658b-c67b-4e1a-a882-807327ae3e34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638084159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.638084159
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3814948847
Short name T251
Test name
Test status
Simulation time 30483528 ps
CPU time 0.66 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 198132 kb
Host smart-4ccf56ed-3cc1-481a-a5cb-ebe113807962
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814948847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3814948847
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.233201925
Short name T520
Test name
Test status
Simulation time 1497702572 ps
CPU time 0.98 seconds
Started Jul 28 05:08:28 PM PDT 24
Finished Jul 28 05:08:29 PM PDT 24
Peak memory 198104 kb
Host smart-49ff1dac-54ad-474a-a04b-e9bf3c5af9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233201925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.233201925
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1960573584
Short name T405
Test name
Test status
Simulation time 22113529 ps
CPU time 0.61 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 198160 kb
Host smart-e5cc4d84-f1a6-495b-aa42-965a11b9630d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960573584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1960573584
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.2442047309
Short name T531
Test name
Test status
Simulation time 27993957 ps
CPU time 0.61 seconds
Started Jul 28 05:08:42 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 198392 kb
Host smart-7fe3c429-efb6-48a6-bb99-f9c909a21d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442047309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2442047309
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1053513281
Short name T194
Test name
Test status
Simulation time 43232888 ps
CPU time 0.77 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:57 PM PDT 24
Peak memory 201464 kb
Host smart-914f27ce-86da-4eb8-b110-dda6351aa358
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053513281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.1053513281
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.4222059859
Short name T377
Test name
Test status
Simulation time 57110727 ps
CPU time 0.66 seconds
Started Jul 28 05:08:31 PM PDT 24
Finished Jul 28 05:08:32 PM PDT 24
Peak memory 198244 kb
Host smart-f3de2553-4dfe-48bd-825d-a03475955c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222059859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.4222059859
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.584023640
Short name T325
Test name
Test status
Simulation time 100717952 ps
CPU time 1.04 seconds
Started Jul 28 05:08:47 PM PDT 24
Finished Jul 28 05:08:48 PM PDT 24
Peak memory 209540 kb
Host smart-9d69f181-f5f5-4f0f-a11c-cc12bfd57b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584023640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.584023640
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3792223964
Short name T365
Test name
Test status
Simulation time 72351939 ps
CPU time 0.76 seconds
Started Jul 28 05:08:34 PM PDT 24
Finished Jul 28 05:08:35 PM PDT 24
Peak memory 197984 kb
Host smart-f2675826-2458-46b8-8477-79a6949d4f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792223964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3792223964
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.512623985
Short name T345
Test name
Test status
Simulation time 30842564 ps
CPU time 0.68 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 199416 kb
Host smart-d5dbdd4a-539c-4bee-b608-e6e9dd147b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512623985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.512623985
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.1783013022
Short name T500
Test name
Test status
Simulation time 231610017 ps
CPU time 0.87 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 200232 kb
Host smart-7200f80d-5993-4a18-a8ee-122ccca20d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783013022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.1783013022
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2085714285
Short name T618
Test name
Test status
Simulation time 53136887 ps
CPU time 0.77 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 198544 kb
Host smart-96871a51-a5b2-40e2-8bb8-cf31797e17ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085714285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2085714285
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2361560356
Short name T495
Test name
Test status
Simulation time 39184935 ps
CPU time 0.6 seconds
Started Jul 28 05:08:25 PM PDT 24
Finished Jul 28 05:08:25 PM PDT 24
Peak memory 198124 kb
Host smart-d1b6870e-05f2-4675-b90d-65874f3b9ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361560356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2361560356
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.4010457800
Short name T577
Test name
Test status
Simulation time 991262943 ps
CPU time 0.97 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:53 PM PDT 24
Peak memory 198152 kb
Host smart-e1257184-d828-47f0-b531-cc4a3dab6a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010457800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.4010457800
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.707617626
Short name T459
Test name
Test status
Simulation time 55477630 ps
CPU time 0.57 seconds
Started Jul 28 05:08:36 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 198136 kb
Host smart-dbb654ee-a974-4516-a3de-2787b8782594
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707617626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.707617626
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2441950890
Short name T273
Test name
Test status
Simulation time 53842859 ps
CPU time 0.62 seconds
Started Jul 28 05:08:24 PM PDT 24
Finished Jul 28 05:08:25 PM PDT 24
Peak memory 198144 kb
Host smart-1f369a35-4ce2-4e98-871f-ee424c077054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441950890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2441950890
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2051650706
Short name T603
Test name
Test status
Simulation time 49075730 ps
CPU time 0.72 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 201384 kb
Host smart-1e20ee8b-65fd-4dd9-80cd-16a9a1549fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051650706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.2051650706
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1377497208
Short name T357
Test name
Test status
Simulation time 39587047 ps
CPU time 0.71 seconds
Started Jul 28 05:08:39 PM PDT 24
Finished Jul 28 05:08:40 PM PDT 24
Peak memory 199104 kb
Host smart-faccd7af-6b5c-45f7-b8e4-928b8b27f02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377497208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1377497208
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.565175938
Short name T484
Test name
Test status
Simulation time 158010618 ps
CPU time 0.81 seconds
Started Jul 28 05:08:32 PM PDT 24
Finished Jul 28 05:08:33 PM PDT 24
Peak memory 209452 kb
Host smart-c91f162f-e2d7-4a1a-9622-9229b5ae8224
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565175938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.565175938
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.4151290269
Short name T591
Test name
Test status
Simulation time 59810907 ps
CPU time 0.8 seconds
Started Jul 28 05:08:53 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 198152 kb
Host smart-fce5fbd8-9075-4523-9eef-38bed9a7d4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151290269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4151290269
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3997440156
Short name T482
Test name
Test status
Simulation time 30872711 ps
CPU time 0.64 seconds
Started Jul 28 05:08:45 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 199356 kb
Host smart-a7c98cc8-7a1a-4b60-868e-96b7404f5133
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997440156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3997440156
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.129700374
Short name T47
Test name
Test status
Simulation time 213123231 ps
CPU time 0.83 seconds
Started Jul 28 05:08:40 PM PDT 24
Finished Jul 28 05:08:41 PM PDT 24
Peak memory 200088 kb
Host smart-6a8eb3b5-ca25-409d-9f64-323839398f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129700374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.129700374
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.507282986
Short name T205
Test name
Test status
Simulation time 60658036 ps
CPU time 0.75 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 199156 kb
Host smart-8b2a2d67-f363-40fd-96e1-4bb1ed924105
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507282986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.507282986
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1525102451
Short name T523
Test name
Test status
Simulation time 30263545 ps
CPU time 0.66 seconds
Started Jul 28 05:08:44 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 197312 kb
Host smart-82d576b5-b0a3-417c-ad80-7a2775f2a0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525102451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1525102451
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.3805764262
Short name T133
Test name
Test status
Simulation time 160882354 ps
CPU time 0.91 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 198128 kb
Host smart-610b53cb-0d9a-4efc-a561-09a0457e0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805764262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3805764262
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.53108849
Short name T578
Test name
Test status
Simulation time 232535297 ps
CPU time 0.64 seconds
Started Jul 28 05:08:37 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 198188 kb
Host smart-85805494-830f-4421-95a2-1a3bee7c144b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53108849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.53108849
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1511388610
Short name T355
Test name
Test status
Simulation time 22679471 ps
CPU time 0.59 seconds
Started Jul 28 05:08:38 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 198412 kb
Host smart-6ff4635a-5640-47e2-8dd9-686324666e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511388610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1511388610
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3428191259
Short name T432
Test name
Test status
Simulation time 74015064 ps
CPU time 0.69 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:53 PM PDT 24
Peak memory 201372 kb
Host smart-dd1de698-7c30-40cb-aeba-9a1f51236c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428191259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3428191259
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.3146272166
Short name T233
Test name
Test status
Simulation time 32583583 ps
CPU time 0.66 seconds
Started Jul 28 05:08:47 PM PDT 24
Finished Jul 28 05:08:48 PM PDT 24
Peak memory 199136 kb
Host smart-2aa2f741-45bc-4690-859b-371ad0a81ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146272166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3146272166
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.662309720
Short name T421
Test name
Test status
Simulation time 122967574 ps
CPU time 0.92 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:53 PM PDT 24
Peak memory 209444 kb
Host smart-dc2aad83-1639-4dde-ba06-6e3fbc614863
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662309720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.662309720
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3107644720
Short name T470
Test name
Test status
Simulation time 63606164 ps
CPU time 0.71 seconds
Started Jul 28 05:08:53 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 198124 kb
Host smart-14bbe4d3-152a-46f5-b7b5-5d521a7859cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107644720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3107644720
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1083272187
Short name T299
Test name
Test status
Simulation time 84289208 ps
CPU time 0.62 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 199404 kb
Host smart-9fd70297-747d-437a-bbcc-be7e0ed61f37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083272187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1083272187
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2886987246
Short name T473
Test name
Test status
Simulation time 70542651 ps
CPU time 0.66 seconds
Started Jul 28 05:08:54 PM PDT 24
Finished Jul 28 05:08:55 PM PDT 24
Peak memory 198752 kb
Host smart-75f6c7f8-e2d4-487e-9ba1-f03f9bcbd878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886987246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2886987246
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3529210618
Short name T162
Test name
Test status
Simulation time 56615953 ps
CPU time 0.71 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 198640 kb
Host smart-51b9bebc-59a3-4265-a618-ff5a71ea5487
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529210618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3529210618
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3042946285
Short name T595
Test name
Test status
Simulation time 30213537 ps
CPU time 0.64 seconds
Started Jul 28 05:08:49 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 197320 kb
Host smart-e53aff7f-e8b0-448e-90bc-b48f209f62da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042946285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3042946285
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.44904634
Short name T244
Test name
Test status
Simulation time 309015778 ps
CPU time 0.93 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198176 kb
Host smart-2b1cc4bb-8526-4f2c-8475-88752364c3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44904634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.44904634
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.396961942
Short name T565
Test name
Test status
Simulation time 39197367 ps
CPU time 0.59 seconds
Started Jul 28 05:08:39 PM PDT 24
Finished Jul 28 05:08:40 PM PDT 24
Peak memory 198004 kb
Host smart-cb26fbfa-bf53-43fc-9e46-dccc8bd0bff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396961942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.396961942
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3089231331
Short name T222
Test name
Test status
Simulation time 38571239 ps
CPU time 0.64 seconds
Started Jul 28 05:08:35 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 198424 kb
Host smart-07e1f695-c77a-423f-98b0-465a030870e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089231331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3089231331
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.759468578
Short name T198
Test name
Test status
Simulation time 133036412 ps
CPU time 0.65 seconds
Started Jul 28 05:08:47 PM PDT 24
Finished Jul 28 05:08:48 PM PDT 24
Peak memory 201376 kb
Host smart-0b195a20-c2eb-4e24-aca6-5ff46c0614a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759468578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.759468578
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3958976631
Short name T250
Test name
Test status
Simulation time 47736153 ps
CPU time 0.75 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 199144 kb
Host smart-9ce1d654-c976-4991-ba20-8b7830ad3eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958976631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3958976631
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1528561316
Short name T262
Test name
Test status
Simulation time 178811022 ps
CPU time 0.85 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 209464 kb
Host smart-40a2a803-989f-43d6-8747-8e5f6142e876
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528561316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1528561316
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1219413475
Short name T562
Test name
Test status
Simulation time 149303539 ps
CPU time 0.64 seconds
Started Jul 28 05:08:49 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 198104 kb
Host smart-49b9bfe0-a13d-4b6e-a5cb-22ab077d9753
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219413475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1219413475
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.2537004483
Short name T452
Test name
Test status
Simulation time 36779462 ps
CPU time 0.63 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198512 kb
Host smart-19abebfd-c051-4193-8950-c45f4eada8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537004483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2537004483
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.2760701631
Short name T612
Test name
Test status
Simulation time 137387585 ps
CPU time 0.76 seconds
Started Jul 28 05:08:37 PM PDT 24
Finished Jul 28 05:08:38 PM PDT 24
Peak memory 198916 kb
Host smart-c9a98862-d169-4611-964f-9e35804df6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760701631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2760701631
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.665413126
Short name T352
Test name
Test status
Simulation time 65981959 ps
CPU time 0.7 seconds
Started Jul 28 05:08:54 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 199092 kb
Host smart-85bd80fe-bade-44c7-a664-541c305b9a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665413126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disa
ble_rom_integrity_check.665413126
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.259637743
Short name T245
Test name
Test status
Simulation time 33026191 ps
CPU time 0.62 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 198036 kb
Host smart-70c89114-4b5f-414f-920f-b4972e02c105
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259637743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.259637743
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3382784166
Short name T532
Test name
Test status
Simulation time 158946964 ps
CPU time 0.97 seconds
Started Jul 28 05:09:01 PM PDT 24
Finished Jul 28 05:09:02 PM PDT 24
Peak memory 198112 kb
Host smart-74ea825f-305e-47c8-b221-8d9bbedde67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382784166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3382784166
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1314066448
Short name T581
Test name
Test status
Simulation time 46473308 ps
CPU time 0.68 seconds
Started Jul 28 05:08:44 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 198036 kb
Host smart-bdc58860-0a67-4b9e-9c70-4d6d855b29af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314066448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1314066448
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2620255828
Short name T594
Test name
Test status
Simulation time 24927061 ps
CPU time 0.6 seconds
Started Jul 28 05:08:51 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198076 kb
Host smart-5689a78e-6c16-4886-8386-da245c5ecd34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620255828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2620255828
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.736598594
Short name T195
Test name
Test status
Simulation time 123653931 ps
CPU time 0.66 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 201356 kb
Host smart-cfed5ed2-ec82-4441-b2f9-cc2d1d4724fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736598594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invali
d.736598594
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3931652586
Short name T60
Test name
Test status
Simulation time 117667113 ps
CPU time 0.61 seconds
Started Jul 28 05:08:53 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 198096 kb
Host smart-ed89bd8b-b753-42a9-bc9e-1a9daabc0413
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931652586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3931652586
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.859986955
Short name T608
Test name
Test status
Simulation time 81855227 ps
CPU time 0.76 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 199064 kb
Host smart-77e1ee7b-4cd7-484d-b687-d75401cc2536
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859986955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.859986955
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2371214878
Short name T406
Test name
Test status
Simulation time 114967656 ps
CPU time 0.89 seconds
Started Jul 28 05:08:42 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 209560 kb
Host smart-08bb756d-182e-4ca4-878c-00cd3e30e40b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371214878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2371214878
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.226652559
Short name T249
Test name
Test status
Simulation time 49339854 ps
CPU time 0.8 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 199252 kb
Host smart-41bd3fb1-275f-4257-a6c3-74746978e1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226652559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.226652559
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2255015003
Short name T248
Test name
Test status
Simulation time 84793349 ps
CPU time 0.6 seconds
Started Jul 28 05:08:44 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 198536 kb
Host smart-0f1b1443-fc3e-4605-a1de-b0c22dd57f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255015003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2255015003
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2606472867
Short name T127
Test name
Test status
Simulation time 119068970 ps
CPU time 0.76 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 200016 kb
Host smart-e6e42ac9-e643-4b67-bd11-e85b77b2ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606472867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2606472867
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1254186026
Short name T160
Test name
Test status
Simulation time 47231393 ps
CPU time 0.79 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 199228 kb
Host smart-d6d27fb0-bda4-4a81-bc69-1b24f35e0ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254186026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1254186026
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.118687198
Short name T419
Test name
Test status
Simulation time 32519628 ps
CPU time 0.59 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 198012 kb
Host smart-7b13bf14-8279-49af-8814-3cccecb739de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118687198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_m
alfunc.118687198
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.53337068
Short name T41
Test name
Test status
Simulation time 319382598 ps
CPU time 0.99 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 198184 kb
Host smart-090bb335-1c8f-483b-85cc-40cdce7350ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53337068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.53337068
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3988868607
Short name T540
Test name
Test status
Simulation time 48601897 ps
CPU time 0.61 seconds
Started Jul 28 05:07:24 PM PDT 24
Finished Jul 28 05:07:25 PM PDT 24
Peak memory 197336 kb
Host smart-3902ac34-95b8-4aba-82d3-985a3968947d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988868607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3988868607
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2260677523
Short name T46
Test name
Test status
Simulation time 50228514 ps
CPU time 0.59 seconds
Started Jul 28 05:07:11 PM PDT 24
Finished Jul 28 05:07:12 PM PDT 24
Peak memory 198076 kb
Host smart-2ae37026-4644-4e25-aa39-179f4c829dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260677523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2260677523
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1358952241
Short name T172
Test name
Test status
Simulation time 45638387 ps
CPU time 0.74 seconds
Started Jul 28 05:07:03 PM PDT 24
Finished Jul 28 05:07:04 PM PDT 24
Peak memory 201384 kb
Host smart-75e77f63-2cb9-40d9-baea-c886b01b5247
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358952241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1358952241
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.1772830372
Short name T149
Test name
Test status
Simulation time 98015159 ps
CPU time 0.69 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 199152 kb
Host smart-f95993b5-cce6-4931-964b-5d1c48aee059
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772830372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.1772830372
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.367239192
Short name T253
Test name
Test status
Simulation time 100814711 ps
CPU time 0.76 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 198448 kb
Host smart-164a4250-88be-4a7f-b933-724a47a87d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367239192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.367239192
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1544877652
Short name T478
Test name
Test status
Simulation time 158786978 ps
CPU time 0.86 seconds
Started Jul 28 05:07:09 PM PDT 24
Finished Jul 28 05:07:10 PM PDT 24
Peak memory 209484 kb
Host smart-882631b9-490b-40a0-8094-45ced74cb102
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544877652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1544877652
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.4096508280
Short name T19
Test name
Test status
Simulation time 515270771 ps
CPU time 1.07 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 216880 kb
Host smart-708538a7-1857-41f0-9068-c01c0387113d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096508280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.4096508280
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.808409834
Short name T393
Test name
Test status
Simulation time 51526752 ps
CPU time 0.84 seconds
Started Jul 28 05:07:04 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 198120 kb
Host smart-535149fb-1080-4bf8-982c-5c8f0e136f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808409834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.808409834
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.449105303
Short name T469
Test name
Test status
Simulation time 31744394 ps
CPU time 0.7 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 199436 kb
Host smart-a946670f-59bf-4d20-9f6d-293b2f315a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449105303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.449105303
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1541633330
Short name T98
Test name
Test status
Simulation time 32969809 ps
CPU time 0.75 seconds
Started Jul 28 05:08:54 PM PDT 24
Finished Jul 28 05:08:55 PM PDT 24
Peak memory 198856 kb
Host smart-6971b108-194b-402f-8212-d953e74e44c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541633330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1541633330
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3109635839
Short name T35
Test name
Test status
Simulation time 119596855 ps
CPU time 0.66 seconds
Started Jul 28 05:08:44 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 198548 kb
Host smart-6dca7206-5366-46c8-a5b5-059e51b237f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109635839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3109635839
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.297662943
Short name T472
Test name
Test status
Simulation time 29890735 ps
CPU time 0.63 seconds
Started Jul 28 05:09:10 PM PDT 24
Finished Jul 28 05:09:11 PM PDT 24
Peak memory 198008 kb
Host smart-1c0029ed-acdb-4079-8f0b-31b9b0b71d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297662943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.297662943
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3673163051
Short name T300
Test name
Test status
Simulation time 165659040 ps
CPU time 0.98 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 197932 kb
Host smart-2c22c5f3-31da-4a8e-9896-eb3d0e5eeb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673163051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3673163051
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1679814846
Short name T611
Test name
Test status
Simulation time 58636929 ps
CPU time 0.81 seconds
Started Jul 28 05:08:55 PM PDT 24
Finished Jul 28 05:08:56 PM PDT 24
Peak memory 198192 kb
Host smart-05b47494-452e-42ef-b60a-cb0164bb839a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679814846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1679814846
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.956633138
Short name T2
Test name
Test status
Simulation time 195392920 ps
CPU time 0.59 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 198120 kb
Host smart-489c73b7-1524-473e-bc57-197cfdc305f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956633138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.956633138
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2129582345
Short name T202
Test name
Test status
Simulation time 52299022 ps
CPU time 0.69 seconds
Started Jul 28 05:08:42 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 201324 kb
Host smart-291baf33-8532-4e8b-b7e2-4f974016dc14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129582345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2129582345
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.4091928845
Short name T42
Test name
Test status
Simulation time 93347098 ps
CPU time 0.71 seconds
Started Jul 28 05:08:39 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 198344 kb
Host smart-bb7f5839-9acd-4612-bd0d-509f88f6f2b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091928845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.4091928845
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.24170612
Short name T392
Test name
Test status
Simulation time 111283323 ps
CPU time 1.05 seconds
Started Jul 28 05:08:53 PM PDT 24
Finished Jul 28 05:08:54 PM PDT 24
Peak memory 209492 kb
Host smart-324088b5-4e56-47ad-ad83-34280d7aed83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24170612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.24170612
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1432118505
Short name T350
Test name
Test status
Simulation time 57654728 ps
CPU time 0.82 seconds
Started Jul 28 05:08:38 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 198220 kb
Host smart-56b22fbe-6440-44e4-9115-d979e010f6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432118505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1432118505
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1886172521
Short name T388
Test name
Test status
Simulation time 32698039 ps
CPU time 0.69 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 198504 kb
Host smart-423deb57-eda3-4f0a-9964-7319b0393d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886172521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1886172521
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.492284479
Short name T396
Test name
Test status
Simulation time 63489534 ps
CPU time 0.73 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:57 PM PDT 24
Peak memory 198864 kb
Host smart-b8ffa849-f74e-453d-a76d-492c7bd6a9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492284479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.492284479
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.3939529400
Short name T456
Test name
Test status
Simulation time 66262622 ps
CPU time 0.83 seconds
Started Jul 28 05:08:49 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 199160 kb
Host smart-45fabad0-3f2c-4c29-98d1-c90f33585b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939529400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.3939529400
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1649052614
Short name T460
Test name
Test status
Simulation time 31035950 ps
CPU time 0.62 seconds
Started Jul 28 05:08:49 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 197344 kb
Host smart-e5d7bdeb-9237-4750-b295-1325f0eaeaf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649052614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1649052614
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2846738625
Short name T497
Test name
Test status
Simulation time 633505511 ps
CPU time 0.95 seconds
Started Jul 28 05:08:54 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 198076 kb
Host smart-df15d127-d13a-4c12-bfef-e8c74c05ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846738625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2846738625
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3553750193
Short name T453
Test name
Test status
Simulation time 75581726 ps
CPU time 0.64 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 198172 kb
Host smart-e4ac45e8-ad73-4b67-b462-dafdad22ce63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553750193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3553750193
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.261558579
Short name T331
Test name
Test status
Simulation time 45896093 ps
CPU time 0.62 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 197912 kb
Host smart-d4c1436f-f160-40df-891d-573a2e97e79c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261558579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.261558579
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2177927796
Short name T193
Test name
Test status
Simulation time 57541551 ps
CPU time 0.68 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 201352 kb
Host smart-85974a76-9126-4ea8-9613-1b5c1c096389
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177927796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2177927796
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.1297506627
Short name T471
Test name
Test status
Simulation time 141967567 ps
CPU time 0.8 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198392 kb
Host smart-f148ab7a-b49d-4d6b-b236-5c99905124e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297506627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1297506627
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.931213516
Short name T496
Test name
Test status
Simulation time 114789436 ps
CPU time 0.89 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 209404 kb
Host smart-cc531a58-9a0a-42e6-a06c-15950b8e7e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931213516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.931213516
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1351712337
Short name T324
Test name
Test status
Simulation time 86177764 ps
CPU time 0.73 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 198228 kb
Host smart-80bf8600-bf57-4216-af8f-0e9469282457
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351712337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1351712337
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.43564720
Short name T328
Test name
Test status
Simulation time 52143668 ps
CPU time 0.61 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 198508 kb
Host smart-44d8a5be-a52d-4f43-ba91-1f3323edc7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43564720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.43564720
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.2279124889
Short name T332
Test name
Test status
Simulation time 25207949 ps
CPU time 0.69 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 196584 kb
Host smart-bed27d51-6c0c-4fd6-8064-4eda97a2f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279124889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2279124889
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.948788128
Short name T315
Test name
Test status
Simulation time 99016379 ps
CPU time 0.63 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 198112 kb
Host smart-4e036fc2-7764-4164-aee7-075e45326bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948788128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.948788128
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3047342327
Short name T543
Test name
Test status
Simulation time 29596985 ps
CPU time 0.68 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 196696 kb
Host smart-67077cee-f26b-448c-bf3c-4cb7dda30c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047342327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3047342327
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.934028179
Short name T282
Test name
Test status
Simulation time 159713096 ps
CPU time 0.99 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 198080 kb
Host smart-d5b4c234-df85-45d9-aaff-c86831ec0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934028179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.934028179
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.659187142
Short name T24
Test name
Test status
Simulation time 43287912 ps
CPU time 0.58 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 197880 kb
Host smart-86d8296c-58ac-4492-b46e-2917691271a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659187142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.659187142
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.3461768929
Short name T316
Test name
Test status
Simulation time 45460618 ps
CPU time 0.6 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 198056 kb
Host smart-0009a663-95c6-439f-b16d-de9b89a6a127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461768929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3461768929
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3179305875
Short name T199
Test name
Test status
Simulation time 50956325 ps
CPU time 0.68 seconds
Started Jul 28 05:08:43 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 201392 kb
Host smart-47b2a191-1525-4f07-931f-08c56abf5853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179305875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3179305875
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3895269429
Short name T340
Test name
Test status
Simulation time 335517378 ps
CPU time 0.69 seconds
Started Jul 28 05:08:45 PM PDT 24
Finished Jul 28 05:08:46 PM PDT 24
Peak memory 198296 kb
Host smart-fae138eb-8f82-4779-9b16-0f5be8f09316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895269429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3895269429
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.648720270
Short name T43
Test name
Test status
Simulation time 152221806 ps
CPU time 0.76 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:05 PM PDT 24
Peak memory 209260 kb
Host smart-9cea157f-b476-46d4-b131-76fbb38cf3b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648720270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.648720270
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1036816163
Short name T210
Test name
Test status
Simulation time 42215027 ps
CPU time 0.61 seconds
Started Jul 28 05:08:41 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 198284 kb
Host smart-bc4786e2-9397-4cf5-b048-e161a647aa90
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036816163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1036816163
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1960047015
Short name T212
Test name
Test status
Simulation time 75665743 ps
CPU time 0.76 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:01 PM PDT 24
Peak memory 198100 kb
Host smart-08bf3ccf-3ff2-40b4-8450-5e5e6951b455
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960047015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1960047015
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.3203117104
Short name T397
Test name
Test status
Simulation time 35354249 ps
CPU time 0.67 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 199376 kb
Host smart-6c643db4-6d96-4108-9f85-b0af578eb2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203117104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.3203117104
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.4022378187
Short name T557
Test name
Test status
Simulation time 34615221 ps
CPU time 0.67 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:57 PM PDT 24
Peak memory 198788 kb
Host smart-8a0ba2fc-9719-4b33-9d0d-f9fc82004ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022378187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.4022378187
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2191541511
Short name T39
Test name
Test status
Simulation time 57130072 ps
CPU time 0.8 seconds
Started Jul 28 05:09:02 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 199148 kb
Host smart-caa47309-b5ce-4c1f-b226-362e4996c246
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191541511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2191541511
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3847140382
Short name T430
Test name
Test status
Simulation time 36382351 ps
CPU time 0.58 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:23 PM PDT 24
Peak memory 197992 kb
Host smart-0ce65679-c0d2-4844-86c1-4fc948db5909
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847140382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3847140382
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.100692306
Short name T400
Test name
Test status
Simulation time 296644021 ps
CPU time 0.94 seconds
Started Jul 28 05:08:54 PM PDT 24
Finished Jul 28 05:08:55 PM PDT 24
Peak memory 198372 kb
Host smart-948e7b95-3f0a-401a-882e-8397887dfee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100692306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.100692306
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2786011533
Short name T313
Test name
Test status
Simulation time 46677379 ps
CPU time 0.67 seconds
Started Jul 28 05:08:55 PM PDT 24
Finished Jul 28 05:08:56 PM PDT 24
Peak memory 197364 kb
Host smart-7d7c155f-305c-4e0e-8f18-f1e9fa186ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786011533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2786011533
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.456354814
Short name T259
Test name
Test status
Simulation time 41764913 ps
CPU time 0.62 seconds
Started Jul 28 05:09:02 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 198200 kb
Host smart-0418fcfb-9cb3-4ead-bf25-42da7b452582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456354814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.456354814
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1081943387
Short name T529
Test name
Test status
Simulation time 45155156 ps
CPU time 0.67 seconds
Started Jul 28 05:08:38 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 199148 kb
Host smart-22ca43cd-ec48-473c-9a6b-2067bf66827a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081943387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1081943387
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1154681794
Short name T323
Test name
Test status
Simulation time 109675695 ps
CPU time 0.93 seconds
Started Jul 28 05:09:23 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 209504 kb
Host smart-5e792e9a-bb33-4f7b-afbb-864ef61c1f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154681794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1154681794
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2170641039
Short name T148
Test name
Test status
Simulation time 23591899 ps
CPU time 0.63 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:53 PM PDT 24
Peak memory 198632 kb
Host smart-8a943a46-3ea6-4a1d-83f5-9fa035cb9ec9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170641039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.2170641039
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1928535562
Short name T480
Test name
Test status
Simulation time 89131733 ps
CPU time 0.79 seconds
Started Jul 28 05:09:16 PM PDT 24
Finished Jul 28 05:09:17 PM PDT 24
Peak memory 199400 kb
Host smart-52596eaa-9321-42ef-9e51-8644e84f9152
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928535562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1928535562
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1957280128
Short name T412
Test name
Test status
Simulation time 28566967 ps
CPU time 0.7 seconds
Started Jul 28 05:08:51 PM PDT 24
Finished Jul 28 05:08:52 PM PDT 24
Peak memory 199380 kb
Host smart-a1cc957c-bb46-4742-aa4a-cc08843c1b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957280128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1957280128
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1011218344
Short name T103
Test name
Test status
Simulation time 42494710 ps
CPU time 0.65 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 198580 kb
Host smart-7e59d1ac-782f-4c64-9c34-faaeda3482ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011218344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1011218344
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2987037239
Short name T274
Test name
Test status
Simulation time 70394388 ps
CPU time 0.66 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 198624 kb
Host smart-2bffc0e2-6874-45f7-8a04-373dbdaa4590
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987037239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2987037239
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1046670582
Short name T539
Test name
Test status
Simulation time 32073127 ps
CPU time 0.6 seconds
Started Jul 28 05:08:50 PM PDT 24
Finished Jul 28 05:08:50 PM PDT 24
Peak memory 198020 kb
Host smart-64816011-9e44-4e63-bd87-77f1549150a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046670582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1046670582
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3700485598
Short name T556
Test name
Test status
Simulation time 693516974 ps
CPU time 0.96 seconds
Started Jul 28 05:08:59 PM PDT 24
Finished Jul 28 05:09:01 PM PDT 24
Peak memory 198132 kb
Host smart-d0c3f4fd-1a59-451f-b51f-178d26893930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700485598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3700485598
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1981321857
Short name T221
Test name
Test status
Simulation time 39145589 ps
CPU time 0.6 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:56 PM PDT 24
Peak memory 198196 kb
Host smart-787cd096-08a1-4b01-a3dd-b72ecfe9e5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981321857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1981321857
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.4197869280
Short name T489
Test name
Test status
Simulation time 21455240 ps
CPU time 0.58 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:53 PM PDT 24
Peak memory 198392 kb
Host smart-6481f978-3594-46e1-8643-577dbcbac95c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197869280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.4197869280
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.3500049973
Short name T420
Test name
Test status
Simulation time 43162076 ps
CPU time 0.71 seconds
Started Jul 28 05:08:45 PM PDT 24
Finished Jul 28 05:08:45 PM PDT 24
Peak memory 201216 kb
Host smart-29e43df6-6479-44d6-9e96-ca2bf6768f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500049973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.3500049973
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.770290682
Short name T361
Test name
Test status
Simulation time 83512095 ps
CPU time 0.79 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 198500 kb
Host smart-f4f2ea1a-63d5-460a-93e0-e0b6fe420848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770290682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.770290682
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1339907204
Short name T410
Test name
Test status
Simulation time 105791560 ps
CPU time 1.06 seconds
Started Jul 28 05:08:57 PM PDT 24
Finished Jul 28 05:08:58 PM PDT 24
Peak memory 209436 kb
Host smart-b053aa52-59ae-4fba-aeb3-57cedf810648
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339907204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1339907204
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1016689862
Short name T475
Test name
Test status
Simulation time 71805473 ps
CPU time 0.7 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 198276 kb
Host smart-2287560a-0983-4e46-b470-95758325bca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016689862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1016689862
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1053404105
Short name T92
Test name
Test status
Simulation time 33070847 ps
CPU time 0.68 seconds
Started Jul 28 05:08:52 PM PDT 24
Finished Jul 28 05:08:52 PM PDT 24
Peak memory 198804 kb
Host smart-cdce43e0-bc1e-4bcd-be5d-6b97619d6cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053404105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1053404105
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2764332866
Short name T378
Test name
Test status
Simulation time 114946931 ps
CPU time 0.83 seconds
Started Jul 28 05:08:48 PM PDT 24
Finished Jul 28 05:08:49 PM PDT 24
Peak memory 200160 kb
Host smart-faf2e234-cbba-49e0-9641-34c6e6db4997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764332866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2764332866
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.1519053023
Short name T143
Test name
Test status
Simulation time 55172383 ps
CPU time 0.74 seconds
Started Jul 28 05:08:51 PM PDT 24
Finished Jul 28 05:08:52 PM PDT 24
Peak memory 199160 kb
Host smart-07ac76c4-4a2c-403d-baa4-931653b666d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519053023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.1519053023
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.64520304
Short name T348
Test name
Test status
Simulation time 40413447 ps
CPU time 0.6 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 197376 kb
Host smart-dc09ef49-0ba6-42bb-8152-670c3f05a6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64520304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_m
alfunc.64520304
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1961693317
Short name T291
Test name
Test status
Simulation time 602086799 ps
CPU time 0.97 seconds
Started Jul 28 05:08:57 PM PDT 24
Finished Jul 28 05:08:58 PM PDT 24
Peak memory 198172 kb
Host smart-2cea798f-e6fc-477e-bbd1-f4ea52267268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961693317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1961693317
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.971351725
Short name T298
Test name
Test status
Simulation time 65993486 ps
CPU time 0.57 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 198040 kb
Host smart-e3c524f1-9a28-4b8b-a575-b5e93cec3e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971351725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.971351725
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.108005810
Short name T349
Test name
Test status
Simulation time 38130721 ps
CPU time 0.62 seconds
Started Jul 28 05:08:59 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 198452 kb
Host smart-a25e6179-0231-4ec4-af0a-3efe638ddc62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108005810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.108005810
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2554476181
Short name T226
Test name
Test status
Simulation time 21344065 ps
CPU time 0.65 seconds
Started Jul 28 05:08:46 PM PDT 24
Finished Jul 28 05:08:47 PM PDT 24
Peak memory 198176 kb
Host smart-a69b9295-752a-4da7-9199-6648443ab00f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554476181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2554476181
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2961881956
Short name T569
Test name
Test status
Simulation time 177323232 ps
CPU time 0.85 seconds
Started Jul 28 05:08:57 PM PDT 24
Finished Jul 28 05:08:58 PM PDT 24
Peak memory 209424 kb
Host smart-fe005faa-6c9d-4915-a2ef-51f0da2c71a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961881956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2961881956
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.622936876
Short name T559
Test name
Test status
Simulation time 78156787 ps
CPU time 0.72 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:57 PM PDT 24
Peak memory 198100 kb
Host smart-1ec8d9c1-149e-483a-a4be-47dacada60a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622936876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_
mubi.622936876
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.263657124
Short name T283
Test name
Test status
Simulation time 28976687 ps
CPU time 0.68 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 198560 kb
Host smart-0cdcc280-3271-44cb-bd96-3db9441fc5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263657124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.263657124
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.231597535
Short name T596
Test name
Test status
Simulation time 47797807 ps
CPU time 0.61 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 198644 kb
Host smart-7e0ac24e-e7ce-4df4-bf8c-2e4efbbb0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231597535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.231597535
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.3931321448
Short name T334
Test name
Test status
Simulation time 51050782 ps
CPU time 0.79 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 199184 kb
Host smart-e65b3edc-faf1-41cf-b236-89edb9df8698
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931321448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.3931321448
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1926327118
Short name T395
Test name
Test status
Simulation time 40918109 ps
CPU time 0.57 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 197432 kb
Host smart-1f3e6ef1-9cc6-49b2-8b44-b5a571c01881
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926327118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1926327118
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.4095201436
Short name T620
Test name
Test status
Simulation time 158977267 ps
CPU time 0.98 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 198096 kb
Host smart-d6a8b509-75ef-46c1-baa1-8d42251413ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095201436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.4095201436
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2189958695
Short name T230
Test name
Test status
Simulation time 24117192 ps
CPU time 0.61 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 197376 kb
Host smart-76ad5adc-e8c4-4670-b1b9-0be0f62994b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189958695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2189958695
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2066035343
Short name T231
Test name
Test status
Simulation time 119452302 ps
CPU time 0.62 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 198488 kb
Host smart-61a718c2-bf21-4ca5-a241-8af632da70d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066035343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2066035343
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3334760690
Short name T95
Test name
Test status
Simulation time 111331894 ps
CPU time 0.64 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 201316 kb
Host smart-0dea6cae-540b-4c85-9f4e-dbb7b814f365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334760690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3334760690
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2509677233
Short name T223
Test name
Test status
Simulation time 100845776 ps
CPU time 0.73 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 198428 kb
Host smart-6b70a61b-9af1-422e-a6d1-d4642a36a4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509677233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2509677233
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.4226711059
Short name T45
Test name
Test status
Simulation time 188185072 ps
CPU time 0.78 seconds
Started Jul 28 05:09:02 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 209496 kb
Host smart-ee9d05d4-667f-4fb9-a765-e5ba953142d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226711059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.4226711059
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2989760280
Short name T261
Test name
Test status
Simulation time 87647235 ps
CPU time 0.69 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:56 PM PDT 24
Peak memory 198072 kb
Host smart-a7f04bb1-cfd0-4115-baab-07b4a9fd9565
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989760280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2989760280
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.822707353
Short name T91
Test name
Test status
Simulation time 56435610 ps
CPU time 0.61 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 198488 kb
Host smart-9d62cfbc-d68c-4bc9-9d2d-ccc71b396153
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822707353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.822707353
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2288330477
Short name T401
Test name
Test status
Simulation time 34484591 ps
CPU time 0.98 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201008 kb
Host smart-425f47fd-b2b5-446e-8111-1b43f72005d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288330477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2288330477
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1005829497
Short name T145
Test name
Test status
Simulation time 46472677 ps
CPU time 0.74 seconds
Started Jul 28 05:08:51 PM PDT 24
Finished Jul 28 05:08:52 PM PDT 24
Peak memory 198380 kb
Host smart-1b0695b7-9aef-4ec4-a018-c0e76b9b588c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005829497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1005829497
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3570572336
Short name T505
Test name
Test status
Simulation time 40228184 ps
CPU time 0.6 seconds
Started Jul 28 05:08:59 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 197404 kb
Host smart-ceb34595-468e-4cce-a768-db3acdf43975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570572336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3570572336
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.1667520509
Short name T134
Test name
Test status
Simulation time 163771266 ps
CPU time 0.98 seconds
Started Jul 28 05:09:02 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 198092 kb
Host smart-d730aeae-a3aa-48a9-8419-03f36d1599df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667520509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1667520509
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1234352857
Short name T366
Test name
Test status
Simulation time 56672038 ps
CPU time 0.6 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 197976 kb
Host smart-3af2addf-9966-4c4d-a146-1568df6b30f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234352857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1234352857
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.3994476032
Short name T477
Test name
Test status
Simulation time 44554785 ps
CPU time 0.6 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 198404 kb
Host smart-8488a9e4-e5eb-42e8-9db8-c70061eec6a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994476032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3994476032
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2886012538
Short name T481
Test name
Test status
Simulation time 73813756 ps
CPU time 0.72 seconds
Started Jul 28 05:08:57 PM PDT 24
Finished Jul 28 05:08:58 PM PDT 24
Peak memory 201452 kb
Host smart-745b95d3-70cc-4d80-a360-043e4ab8e934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886012538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2886012538
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2093081960
Short name T451
Test name
Test status
Simulation time 45879232 ps
CPU time 0.61 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 198552 kb
Host smart-b62a2b0f-8a1b-4b95-897f-2c2d4cde1d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093081960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2093081960
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1121550545
Short name T215
Test name
Test status
Simulation time 102694302 ps
CPU time 0.87 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 209412 kb
Host smart-69f9fe3e-f181-424f-84c0-faf3cd88eff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121550545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1121550545
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3023930636
Short name T254
Test name
Test status
Simulation time 60703835 ps
CPU time 0.81 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:01 PM PDT 24
Peak memory 198016 kb
Host smart-f6377985-daf2-4d42-8c8d-3a953e89b984
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023930636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3023930636
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1013802709
Short name T321
Test name
Test status
Simulation time 37200392 ps
CPU time 0.64 seconds
Started Jul 28 05:08:56 PM PDT 24
Finished Jul 28 05:08:57 PM PDT 24
Peak memory 198744 kb
Host smart-005e4af7-ccf1-4c80-8a6b-88fa6879358b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013802709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1013802709
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1070048732
Short name T555
Test name
Test status
Simulation time 30109933 ps
CPU time 0.74 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 199036 kb
Host smart-b0a47f69-bf2c-44bd-b843-d7209e34acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070048732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1070048732
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.43897525
Short name T163
Test name
Test status
Simulation time 61206989 ps
CPU time 0.83 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:01 PM PDT 24
Peak memory 199188 kb
Host smart-0f7164b3-d941-40bb-adc1-23b3de1e8a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43897525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disab
le_rom_integrity_check.43897525
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1899314382
Short name T390
Test name
Test status
Simulation time 51776988 ps
CPU time 0.59 seconds
Started Jul 28 05:09:02 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 197312 kb
Host smart-0f221534-c0c2-4680-9745-c44ecba4e696
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899314382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.1899314382
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.56915267
Short name T415
Test name
Test status
Simulation time 167000352 ps
CPU time 0.94 seconds
Started Jul 28 05:09:10 PM PDT 24
Finished Jul 28 05:09:11 PM PDT 24
Peak memory 198440 kb
Host smart-03954fe1-ae6c-4113-a470-5554aef8019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56915267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.56915267
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3324822552
Short name T38
Test name
Test status
Simulation time 53776092 ps
CPU time 0.64 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:17 PM PDT 24
Peak memory 198020 kb
Host smart-cc4a37be-6dc0-4eb2-940f-97e8bc3e448f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324822552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3324822552
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.4122297937
Short name T574
Test name
Test status
Simulation time 31622533 ps
CPU time 0.62 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 198048 kb
Host smart-56270583-7a47-4398-8fb0-2337281f0fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122297937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.4122297937
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3296534409
Short name T339
Test name
Test status
Simulation time 121999593 ps
CPU time 0.74 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 199152 kb
Host smart-064fc5ee-06f7-47d3-9b89-8fc073aaeca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296534409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3296534409
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2719497399
Short name T546
Test name
Test status
Simulation time 105090070 ps
CPU time 0.97 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 209524 kb
Host smart-63aababa-5567-4109-a5c4-38c698ed6c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719497399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2719497399
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2178114991
Short name T408
Test name
Test status
Simulation time 158662833 ps
CPU time 0.84 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 199620 kb
Host smart-92a710ea-7506-41a3-8c5f-947edfa9ce8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178114991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2178114991
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.3920123433
Short name T26
Test name
Test status
Simulation time 30193430 ps
CPU time 0.69 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 198084 kb
Host smart-8af50da5-229a-48a1-a9b6-0e690b848561
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920123433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.3920123433
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2951930768
Short name T615
Test name
Test status
Simulation time 41730455 ps
CPU time 0.65 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 199224 kb
Host smart-80d9fc62-d387-49dc-8483-ea2d5096c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951930768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2951930768
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2068563939
Short name T617
Test name
Test status
Simulation time 77939626 ps
CPU time 0.67 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 198472 kb
Host smart-e6227a90-e703-4ecf-8f21-60752a9d3c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068563939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2068563939
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.8444545
Short name T508
Test name
Test status
Simulation time 38564716 ps
CPU time 0.58 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 198120 kb
Host smart-8c5146a2-5443-42f7-9d3c-310cf51d7fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8444545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malf
unc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_ma
lfunc.8444545
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1590513862
Short name T458
Test name
Test status
Simulation time 310384611 ps
CPU time 0.95 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 198464 kb
Host smart-3e605558-bcc3-44ce-9bd8-b15e86e0e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590513862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1590513862
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.546578232
Short name T619
Test name
Test status
Simulation time 40624300 ps
CPU time 0.67 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 198024 kb
Host smart-36aa7e50-fde1-4565-bb5e-50389c1716fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546578232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.546578232
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.1053833175
Short name T285
Test name
Test status
Simulation time 31316511 ps
CPU time 0.6 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 198084 kb
Host smart-ac5d374f-a914-4d97-ab55-dd598a428dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053833175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.1053833175
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1944682470
Short name T169
Test name
Test status
Simulation time 44305031 ps
CPU time 0.7 seconds
Started Jul 28 05:09:12 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 201356 kb
Host smart-fcadc671-c1d9-4932-bb33-8c495cb4aa2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944682470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1944682470
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.1797394949
Short name T488
Test name
Test status
Simulation time 99604189 ps
CPU time 0.73 seconds
Started Jul 28 05:09:13 PM PDT 24
Finished Jul 28 05:09:14 PM PDT 24
Peak memory 199092 kb
Host smart-d71f076d-b257-4455-ba3c-27cacb8b1075
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797394949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1797394949
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2047160607
Short name T305
Test name
Test status
Simulation time 111201538 ps
CPU time 1.12 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 209420 kb
Host smart-f03532ee-5462-4a35-9f5f-bd473bc39d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047160607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2047160607
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1709547456
Short name T372
Test name
Test status
Simulation time 62492435 ps
CPU time 0.9 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 198196 kb
Host smart-cd588dfa-056f-42d4-b63f-0ddfddadbae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709547456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1709547456
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3271276081
Short name T94
Test name
Test status
Simulation time 30559618 ps
CPU time 0.69 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 199444 kb
Host smart-001b3b85-8846-447e-9ddc-7e358d8cba36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271276081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3271276081
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.567211625
Short name T525
Test name
Test status
Simulation time 28105531 ps
CPU time 0.69 seconds
Started Jul 28 05:07:05 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 198772 kb
Host smart-e92887c7-d04b-4dbc-8bc4-eb8e43d3cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567211625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.567211625
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.394459832
Short name T302
Test name
Test status
Simulation time 71110328 ps
CPU time 0.64 seconds
Started Jul 28 05:07:04 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 199176 kb
Host smart-31d20e5a-a946-4fe9-bf89-ed74745cf961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394459832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disab
le_rom_integrity_check.394459832
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.432949773
Short name T592
Test name
Test status
Simulation time 29156016 ps
CPU time 0.63 seconds
Started Jul 28 05:07:22 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 198044 kb
Host smart-f3da4a86-f49f-49c2-bcfc-8674ff83391b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432949773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.432949773
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2329147006
Short name T137
Test name
Test status
Simulation time 158463529 ps
CPU time 0.93 seconds
Started Jul 28 05:07:11 PM PDT 24
Finished Jul 28 05:07:12 PM PDT 24
Peak memory 198156 kb
Host smart-8600f164-19af-46bf-91ca-561887d15e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329147006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2329147006
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.195673796
Short name T584
Test name
Test status
Simulation time 42274280 ps
CPU time 0.64 seconds
Started Jul 28 05:07:10 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 198360 kb
Host smart-053225c5-7060-484b-9464-68a705974ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195673796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.195673796
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.2285365602
Short name T257
Test name
Test status
Simulation time 24173644 ps
CPU time 0.62 seconds
Started Jul 28 05:07:06 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 198140 kb
Host smart-9f8f4cec-f5d1-4fda-888c-49073dea29de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285365602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2285365602
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.4172986602
Short name T173
Test name
Test status
Simulation time 49464390 ps
CPU time 0.67 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 201324 kb
Host smart-cb20fdce-8170-4aba-8d19-fe07a03f150c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172986602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.4172986602
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.4067395586
Short name T465
Test name
Test status
Simulation time 38327886 ps
CPU time 0.61 seconds
Started Jul 28 05:07:06 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 198328 kb
Host smart-2c50d096-c0b1-473d-a188-771b37e44c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067395586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.4067395586
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2527713818
Short name T449
Test name
Test status
Simulation time 118119339 ps
CPU time 0.91 seconds
Started Jul 28 05:07:02 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 209492 kb
Host smart-53ec3f21-ce2e-41ab-a7a8-a479d50e55f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527713818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2527713818
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1546176282
Short name T424
Test name
Test status
Simulation time 32706627 ps
CPU time 0.68 seconds
Started Jul 28 05:07:06 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 199432 kb
Host smart-df81b91f-e750-4303-bf2c-bdb074fcc558
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546176282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1546176282
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1041185058
Short name T552
Test name
Test status
Simulation time 46353541 ps
CPU time 0.61 seconds
Started Jul 28 05:07:13 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 198536 kb
Host smart-30b0ba0e-0819-463d-9c9a-17199ab4addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041185058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1041185058
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3307382927
Short name T605
Test name
Test status
Simulation time 99253182 ps
CPU time 0.63 seconds
Started Jul 28 05:07:21 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 198340 kb
Host smart-43ff9313-be0c-410c-a947-50e66792679b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307382927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.3307382927
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3229607587
Short name T258
Test name
Test status
Simulation time 36583745 ps
CPU time 0.59 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 198124 kb
Host smart-f78b6e3d-48d6-4938-aa77-bc2c514fbc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229607587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.3229607587
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3097154188
Short name T522
Test name
Test status
Simulation time 165184726 ps
CPU time 1.01 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 198076 kb
Host smart-2f64b2a4-4521-420b-94a4-a25ffb0691d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097154188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3097154188
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.814040210
Short name T590
Test name
Test status
Simulation time 70314491 ps
CPU time 0.58 seconds
Started Jul 28 05:07:21 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 197356 kb
Host smart-804852da-f5df-48ce-9669-8ce9a4610891
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814040210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.814040210
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.3891379683
Short name T468
Test name
Test status
Simulation time 23085149 ps
CPU time 0.64 seconds
Started Jul 28 05:07:18 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 198040 kb
Host smart-c1572d5a-12bb-4963-b963-738bf768cc6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891379683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3891379683
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2644769455
Short name T189
Test name
Test status
Simulation time 75714254 ps
CPU time 0.65 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 201376 kb
Host smart-1c748cc7-3644-45f8-ade3-f34de82e8936
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644769455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2644769455
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.314624209
Short name T389
Test name
Test status
Simulation time 38755685 ps
CPU time 0.71 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 198316 kb
Host smart-6292beb7-d9ce-4467-b2c4-6297307a7e6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314624209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.314624209
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1296628111
Short name T440
Test name
Test status
Simulation time 495672763 ps
CPU time 0.75 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 209504 kb
Host smart-1c7101ae-cc2b-472c-a64d-58094842dbf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296628111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1296628111
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.887672708
Short name T610
Test name
Test status
Simulation time 51624761 ps
CPU time 0.83 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 198368 kb
Host smart-9335dab4-7f8a-4b1b-890b-7d681dece877
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887672708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.887672708
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1285146900
Short name T386
Test name
Test status
Simulation time 82879518 ps
CPU time 0.61 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 199408 kb
Host smart-336e1478-d2b2-4379-8f31-c305f05aa4a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285146900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1285146900
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.843603959
Short name T616
Test name
Test status
Simulation time 36887889 ps
CPU time 1.1 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 200884 kb
Host smart-1753a84f-7d21-430d-ba66-b93e3595e88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843603959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.843603959
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1383101001
Short name T457
Test name
Test status
Simulation time 73546192 ps
CPU time 0.68 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 197648 kb
Host smart-a7e822b8-23e4-416b-957a-787e137760eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383101001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1383101001
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.348096807
Short name T570
Test name
Test status
Simulation time 30805431 ps
CPU time 0.63 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 198044 kb
Host smart-7b5d47b7-7ff2-4100-9967-b35f2b447580
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348096807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_m
alfunc.348096807
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.638406194
Short name T364
Test name
Test status
Simulation time 164632034 ps
CPU time 0.98 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 198428 kb
Host smart-6d6c7ba7-25b0-45f3-b93a-199404ecb7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638406194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.638406194
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1119452403
Short name T1
Test name
Test status
Simulation time 47528855 ps
CPU time 0.71 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 197532 kb
Host smart-156b0e94-89aa-4794-9314-a024be6f7d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119452403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1119452403
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.3376545241
Short name T568
Test name
Test status
Simulation time 43932241 ps
CPU time 0.66 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 198636 kb
Host smart-dcf2de53-ceff-4d03-8f04-36a6c90ff3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376545241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3376545241
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.942389580
Short name T423
Test name
Test status
Simulation time 39149552 ps
CPU time 0.71 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 199204 kb
Host smart-e5765d9d-9bbf-4c30-a5fa-cebbd62fdde2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942389580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.942389580
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3195750519
Short name T367
Test name
Test status
Simulation time 158284960 ps
CPU time 0.83 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 209536 kb
Host smart-6128b9e0-8a53-4573-b0d7-b547325b276e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195750519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3195750519
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2870917907
Short name T276
Test name
Test status
Simulation time 107166789 ps
CPU time 0.71 seconds
Started Jul 28 05:07:23 PM PDT 24
Finished Jul 28 05:07:24 PM PDT 24
Peak memory 198244 kb
Host smart-0326e3c5-a5bd-492c-b0a7-259d34b53e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870917907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2870917907
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2297272780
Short name T351
Test name
Test status
Simulation time 30368714 ps
CPU time 0.69 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 199348 kb
Host smart-344015e1-0757-414a-af54-979ed0e48671
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297272780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2297272780
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.4292147255
Short name T550
Test name
Test status
Simulation time 96315733 ps
CPU time 0.73 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 198904 kb
Host smart-217b395b-f372-454b-9e7d-86a3b2fbd449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292147255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.4292147255
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3986996718
Short name T165
Test name
Test status
Simulation time 57416903 ps
CPU time 0.77 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 198908 kb
Host smart-2c22f519-90f3-4d7b-8133-655bd6a946e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986996718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3986996718
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1854851018
Short name T239
Test name
Test status
Simulation time 29208439 ps
CPU time 0.63 seconds
Started Jul 28 05:07:18 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 197956 kb
Host smart-2f4243af-9254-4439-9ef7-62c6481619a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854851018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1854851018
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2684676370
Short name T490
Test name
Test status
Simulation time 159721185 ps
CPU time 1.01 seconds
Started Jul 28 05:07:16 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 197544 kb
Host smart-6eadd8fd-557c-4ece-92c6-26128d344f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684676370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2684676370
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.4108651249
Short name T585
Test name
Test status
Simulation time 76195008 ps
CPU time 0.62 seconds
Started Jul 28 05:07:30 PM PDT 24
Finished Jul 28 05:07:31 PM PDT 24
Peak memory 197420 kb
Host smart-5b419f67-416b-4fcf-9494-052342d29c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108651249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.4108651249
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.3033240037
Short name T398
Test name
Test status
Simulation time 29744964 ps
CPU time 0.6 seconds
Started Jul 28 05:07:21 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 198184 kb
Host smart-97cab49b-c894-40c5-b8fa-dc7fc2aa27c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033240037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.3033240037
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.520761560
Short name T203
Test name
Test status
Simulation time 36051807 ps
CPU time 0.73 seconds
Started Jul 28 05:07:21 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 201424 kb
Host smart-e56d0db5-03c7-4848-9797-d22f5f453690
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520761560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.520761560
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2972992313
Short name T66
Test name
Test status
Simulation time 48775562 ps
CPU time 0.67 seconds
Started Jul 28 05:07:13 PM PDT 24
Finished Jul 28 05:07:14 PM PDT 24
Peak memory 199072 kb
Host smart-07bf5b37-0a78-467f-b810-a238a0bead0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972992313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2972992313
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.4113835956
Short name T528
Test name
Test status
Simulation time 181713296 ps
CPU time 0.79 seconds
Started Jul 28 05:07:10 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 209496 kb
Host smart-5f0cba88-40cd-4634-b0b9-67d3545191bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113835956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.4113835956
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.202551722
Short name T537
Test name
Test status
Simulation time 82868675 ps
CPU time 0.8 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 199312 kb
Host smart-fc43bf43-10c2-4fa9-8bfb-b1e7f5306a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202551722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.202551722
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2571846844
Short name T374
Test name
Test status
Simulation time 44680519 ps
CPU time 0.62 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 199340 kb
Host smart-bb6ed79f-d55a-4843-a01b-bae3baf26b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571846844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2571846844
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3296774921
Short name T320
Test name
Test status
Simulation time 253748926 ps
CPU time 0.75 seconds
Started Jul 28 05:07:30 PM PDT 24
Finished Jul 28 05:07:31 PM PDT 24
Peak memory 199924 kb
Host smart-3816b3ca-cdbf-48dc-824f-b303b8be5c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296774921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3296774921
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.443479299
Short name T209
Test name
Test status
Simulation time 53572765 ps
CPU time 0.82 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 198584 kb
Host smart-0da49c94-32c1-4296-adb3-531982f3d466
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443479299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.443479299
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.104634588
Short name T37
Test name
Test status
Simulation time 53361295 ps
CPU time 0.63 seconds
Started Jul 28 05:07:20 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 197440 kb
Host smart-cfeec3f1-769e-4e0a-8e50-30232b8cba28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104634588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_m
alfunc.104634588
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.34412457
Short name T513
Test name
Test status
Simulation time 1850012678 ps
CPU time 0.97 seconds
Started Jul 28 05:07:19 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 198360 kb
Host smart-b6f3ec4f-6a77-4732-a64e-b4366cb4f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34412457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.34412457
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2393448647
Short name T597
Test name
Test status
Simulation time 38962999 ps
CPU time 0.7 seconds
Started Jul 28 05:07:25 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 197352 kb
Host smart-83b34687-b58b-4470-a4ee-c9090c4089a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393448647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2393448647
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.3845590463
Short name T224
Test name
Test status
Simulation time 80793486 ps
CPU time 0.59 seconds
Started Jul 28 05:07:15 PM PDT 24
Finished Jul 28 05:07:16 PM PDT 24
Peak memory 198072 kb
Host smart-e3bede85-27df-4062-8f66-c6e72a327374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845590463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3845590463
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3529586731
Short name T521
Test name
Test status
Simulation time 50361902 ps
CPU time 0.73 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 198468 kb
Host smart-22e9260c-e173-4184-9698-0733bccd9935
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529586731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3529586731
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.813153271
Short name T566
Test name
Test status
Simulation time 233321810 ps
CPU time 0.77 seconds
Started Jul 28 05:07:22 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 209480 kb
Host smart-261b3550-4408-4a86-b4e8-6699f2a9d462
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813153271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.813153271
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2329345905
Short name T437
Test name
Test status
Simulation time 99644170 ps
CPU time 0.75 seconds
Started Jul 28 05:07:21 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 197876 kb
Host smart-3a4da867-b70b-4f33-ab06-796c334dde5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329345905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2329345905
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2769730907
Short name T266
Test name
Test status
Simulation time 39831259 ps
CPU time 0.6 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:15 PM PDT 24
Peak memory 198536 kb
Host smart-b6cc9caa-96f1-4ef1-86b2-2a6cfd7dee6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769730907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2769730907
Directory /workspace/9.pwrmgr_smoke/latest
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