Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570

1

T5

10

T14

5

T11

2

auto[1]

430

1

T5

3

T14

1

T29

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608

1

T5

4

T14

4

T11

2

auto[1]

392

1

T5

9

T14

2

T29

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

440

1

T5

6

T14

6

T29

2

auto[1]

560

1

T5

7

T11

2

T29

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

796

1

T5

13

T14

4

T11

1

auto[1]

204

1

T14

2

T11

1

T29

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

433

1

T5

5

T14

5

T32

1

auto[1]

567

1

T5

8

T14

1

T11

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567

1

T5

9

T14

4

T11

2

auto[1]

433

1

T5

4

T14

2

T29

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

29

1

T5

1

T14

1

T181

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T14

1

T181

1

T182

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

26

1

T5

1

T30

1

T13

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T24

1

T181

1

T61

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T5

1

T27

1

T84

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T183

1

T184

1

T66

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

75

1

T5

1

T11

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

58

1

T11

1

T52

1

T53

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T14

1

T12

1

T27

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T185

1

T186

1

-

-

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T13

1

T57

2

T187

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T188

1

T189

1

T190

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T54

1

T181

1

T56

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T191

1

T192

1

T154

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T27

1

T193

1

T91

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T193

1

T194

1

T195

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

28

1

T14

1

T27

1

T56

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T14

1

T196

1

T188

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

13

1

T56

1

T97

1

T197

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T48

1

T153

1

-

-

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20

1

T5

2

T54

1

T189

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T198

1

T199

1

T200

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T5

1

T201

1

T47

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T47

1

T202

1

T203

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T54

2

T56

1

T196

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T196

1

T155

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T5

1

T83

1

T84

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T83

1

T204

1

T193

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T5

1

T12

1

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T50

1

T189

1

T205

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

30

1

T5

1

T29

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T29

1

T32

1

T31

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28

1

T30

1

T24

1

T54

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T24

1

T91

1

T206

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T31

1

T194

1

T57

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T194

1

T187

1

T195

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T29

1

T30

1

T27

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T29

1

T30

1

T25

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T29

1

T83

1

T54

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T207

1

T203

1

T208

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T204

1

T193

1

T56

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T51

1

T209

2

T191

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T32

1

T30

1

T54

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T30

1

T206

1

T210

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T14

1

T32

1

T54

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T32

1

T211

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T29

1

T55

1

T57

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T47

1

T210

1

T212

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

20

1

T5

1

T84

1

T204

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T84

1

T183

1

T205

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

20

1

T5

1

T13

1

T31

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T31

1

T213

1

T152

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

21

1

T27

1

T84

1

T54

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T84

1

T64

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T27

1

T201

1

T91

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T201

1

T91

1

T213

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

18

1

T27

1

T83

1

T201

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T201

1

T214

2

T215

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

12

1

T12

1

T54

2

T204

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T204

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

14

1

T32

1

T27

1

T194

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T216

1

T217

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T5

1

T13

1

T54

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T190

1

-

-

-

-