Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.23 96.15 99.44 96.00 96.18 100.00 95.74


Total test records in report: 745
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T557 /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.937526601 Jul 29 07:07:58 PM PDT 24 Jul 29 07:07:59 PM PDT 24 30437095 ps
T215 /workspace/coverage/default/16.pwrmgr_wakeup.2923227131 Jul 29 07:07:37 PM PDT 24 Jul 29 07:07:38 PM PDT 24 108980936 ps
T558 /workspace/coverage/default/35.pwrmgr_reset.167612783 Jul 29 07:08:36 PM PDT 24 Jul 29 07:08:37 PM PDT 24 45267127 ps
T559 /workspace/coverage/default/25.pwrmgr_global_esc.212188910 Jul 29 07:08:03 PM PDT 24 Jul 29 07:08:04 PM PDT 24 43469229 ps
T560 /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2421038742 Jul 29 07:08:34 PM PDT 24 Jul 29 07:08:35 PM PDT 24 83543478 ps
T561 /workspace/coverage/default/40.pwrmgr_reset.759928426 Jul 29 07:08:52 PM PDT 24 Jul 29 07:08:53 PM PDT 24 24670642 ps
T562 /workspace/coverage/default/20.pwrmgr_escalation_timeout.3150839587 Jul 29 07:07:58 PM PDT 24 Jul 29 07:07:59 PM PDT 24 161906984 ps
T563 /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.331681476 Jul 29 07:07:19 PM PDT 24 Jul 29 07:07:20 PM PDT 24 81945723 ps
T564 /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3252340401 Jul 29 07:07:18 PM PDT 24 Jul 29 07:07:19 PM PDT 24 67923214 ps
T565 /workspace/coverage/default/17.pwrmgr_global_esc.3620558225 Jul 29 07:07:46 PM PDT 24 Jul 29 07:07:46 PM PDT 24 68079216 ps
T566 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1903501167 Jul 29 07:08:57 PM PDT 24 Jul 29 07:08:57 PM PDT 24 46048142 ps
T567 /workspace/coverage/default/36.pwrmgr_glitch.3511519222 Jul 29 07:08:39 PM PDT 24 Jul 29 07:08:40 PM PDT 24 39340097 ps
T568 /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101209608 Jul 29 07:06:59 PM PDT 24 Jul 29 07:07:00 PM PDT 24 54130476 ps
T569 /workspace/coverage/default/28.pwrmgr_aborted_low_power.3501983275 Jul 29 07:08:16 PM PDT 24 Jul 29 07:08:17 PM PDT 24 58957551 ps
T570 /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2097450798 Jul 29 07:09:14 PM PDT 24 Jul 29 07:09:15 PM PDT 24 56596022 ps
T571 /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2976085292 Jul 29 07:08:04 PM PDT 24 Jul 29 07:08:05 PM PDT 24 63567665 ps
T572 /workspace/coverage/default/0.pwrmgr_smoke.1258628574 Jul 29 07:06:33 PM PDT 24 Jul 29 07:06:34 PM PDT 24 36207586 ps
T66 /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.402586197 Jul 29 07:08:06 PM PDT 24 Jul 29 07:08:08 PM PDT 24 135351959 ps
T573 /workspace/coverage/default/28.pwrmgr_global_esc.3793591990 Jul 29 07:08:17 PM PDT 24 Jul 29 07:08:18 PM PDT 24 26420764 ps
T574 /workspace/coverage/default/44.pwrmgr_aborted_low_power.4131125020 Jul 29 07:09:02 PM PDT 24 Jul 29 07:09:03 PM PDT 24 41851901 ps
T575 /workspace/coverage/default/24.pwrmgr_reset_invalid.2082256054 Jul 29 07:08:03 PM PDT 24 Jul 29 07:08:04 PM PDT 24 187095879 ps
T576 /workspace/coverage/default/27.pwrmgr_global_esc.3224253189 Jul 29 07:08:08 PM PDT 24 Jul 29 07:08:08 PM PDT 24 36418295 ps
T577 /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2652288592 Jul 29 07:07:08 PM PDT 24 Jul 29 07:07:09 PM PDT 24 56377151 ps
T578 /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3835835085 Jul 29 07:06:39 PM PDT 24 Jul 29 07:06:40 PM PDT 24 36533853 ps
T579 /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1213101097 Jul 29 07:06:48 PM PDT 24 Jul 29 07:06:49 PM PDT 24 71593977 ps
T580 /workspace/coverage/default/4.pwrmgr_escalation_timeout.2653025310 Jul 29 07:06:50 PM PDT 24 Jul 29 07:06:51 PM PDT 24 319128835 ps
T581 /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2045228018 Jul 29 07:09:01 PM PDT 24 Jul 29 07:09:02 PM PDT 24 56026626 ps
T582 /workspace/coverage/default/46.pwrmgr_smoke.2480976402 Jul 29 07:09:23 PM PDT 24 Jul 29 07:09:24 PM PDT 24 47173103 ps
T583 /workspace/coverage/default/26.pwrmgr_smoke.2110126852 Jul 29 07:08:04 PM PDT 24 Jul 29 07:08:05 PM PDT 24 52651451 ps
T584 /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1577694941 Jul 29 07:08:57 PM PDT 24 Jul 29 07:08:58 PM PDT 24 86209265 ps
T585 /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.544248819 Jul 29 07:08:09 PM PDT 24 Jul 29 07:08:10 PM PDT 24 67682233 ps
T586 /workspace/coverage/default/37.pwrmgr_glitch.2927145081 Jul 29 07:08:43 PM PDT 24 Jul 29 07:08:44 PM PDT 24 51158049 ps
T587 /workspace/coverage/default/41.pwrmgr_aborted_low_power.2271753526 Jul 29 07:08:52 PM PDT 24 Jul 29 07:08:53 PM PDT 24 46390391 ps
T588 /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1867751408 Jul 29 07:09:07 PM PDT 24 Jul 29 07:09:08 PM PDT 24 29816993 ps
T589 /workspace/coverage/default/15.pwrmgr_reset.3561365678 Jul 29 07:07:24 PM PDT 24 Jul 29 07:07:25 PM PDT 24 62743992 ps
T590 /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.645172879 Jul 29 07:07:04 PM PDT 24 Jul 29 07:07:05 PM PDT 24 59469242 ps
T591 /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3954313238 Jul 29 07:09:18 PM PDT 24 Jul 29 07:09:19 PM PDT 24 71841922 ps
T592 /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3439186450 Jul 29 07:08:45 PM PDT 24 Jul 29 07:08:45 PM PDT 24 61846051 ps
T593 /workspace/coverage/default/26.pwrmgr_reset_invalid.3788819009 Jul 29 07:08:02 PM PDT 24 Jul 29 07:08:03 PM PDT 24 94865233 ps
T594 /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3491094303 Jul 29 07:08:45 PM PDT 24 Jul 29 07:08:46 PM PDT 24 63885168 ps
T595 /workspace/coverage/default/21.pwrmgr_global_esc.1534796195 Jul 29 07:07:56 PM PDT 24 Jul 29 07:07:57 PM PDT 24 30392586 ps
T596 /workspace/coverage/default/9.pwrmgr_glitch.2662336574 Jul 29 07:07:04 PM PDT 24 Jul 29 07:07:04 PM PDT 24 50048834 ps
T597 /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1831691010 Jul 29 07:09:13 PM PDT 24 Jul 29 07:09:14 PM PDT 24 43646022 ps
T598 /workspace/coverage/default/23.pwrmgr_aborted_low_power.98281497 Jul 29 07:07:57 PM PDT 24 Jul 29 07:07:58 PM PDT 24 41246287 ps
T599 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2016424764 Jul 29 07:08:04 PM PDT 24 Jul 29 07:08:05 PM PDT 24 75646837 ps
T600 /workspace/coverage/default/25.pwrmgr_escalation_timeout.3831779613 Jul 29 07:08:02 PM PDT 24 Jul 29 07:08:03 PM PDT 24 681332387 ps
T601 /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1954989947 Jul 29 07:08:37 PM PDT 24 Jul 29 07:08:38 PM PDT 24 54930369 ps
T186 /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3749168317 Jul 29 07:08:36 PM PDT 24 Jul 29 07:08:37 PM PDT 24 42480032 ps
T602 /workspace/coverage/default/41.pwrmgr_escalation_timeout.1709199089 Jul 29 07:08:52 PM PDT 24 Jul 29 07:08:54 PM PDT 24 240809663 ps
T603 /workspace/coverage/default/9.pwrmgr_smoke.1392261577 Jul 29 07:07:08 PM PDT 24 Jul 29 07:07:09 PM PDT 24 43377384 ps
T604 /workspace/coverage/default/48.pwrmgr_reset.1582378892 Jul 29 07:09:17 PM PDT 24 Jul 29 07:09:18 PM PDT 24 156979913 ps
T605 /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3012388743 Jul 29 07:08:14 PM PDT 24 Jul 29 07:08:15 PM PDT 24 104529518 ps
T606 /workspace/coverage/default/42.pwrmgr_reset.4055481381 Jul 29 07:09:01 PM PDT 24 Jul 29 07:09:02 PM PDT 24 128237561 ps
T607 /workspace/coverage/default/27.pwrmgr_smoke.242544686 Jul 29 07:08:07 PM PDT 24 Jul 29 07:08:08 PM PDT 24 59804849 ps
T608 /workspace/coverage/default/48.pwrmgr_smoke.3304930899 Jul 29 07:09:12 PM PDT 24 Jul 29 07:09:13 PM PDT 24 187359790 ps
T609 /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1201512330 Jul 29 07:07:36 PM PDT 24 Jul 29 07:07:37 PM PDT 24 59883614 ps
T610 /workspace/coverage/default/12.pwrmgr_aborted_low_power.1477447449 Jul 29 07:07:16 PM PDT 24 Jul 29 07:07:17 PM PDT 24 171664262 ps
T611 /workspace/coverage/default/33.pwrmgr_aborted_low_power.1684116227 Jul 29 07:08:33 PM PDT 24 Jul 29 07:08:34 PM PDT 24 27649068 ps
T612 /workspace/coverage/default/40.pwrmgr_reset_invalid.2247956088 Jul 29 07:08:51 PM PDT 24 Jul 29 07:08:52 PM PDT 24 123665107 ps
T613 /workspace/coverage/default/34.pwrmgr_escalation_timeout.3248535090 Jul 29 07:08:37 PM PDT 24 Jul 29 07:08:39 PM PDT 24 166885080 ps
T614 /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1265076047 Jul 29 07:07:56 PM PDT 24 Jul 29 07:07:57 PM PDT 24 39804386 ps
T615 /workspace/coverage/default/28.pwrmgr_reset.3044685140 Jul 29 07:08:08 PM PDT 24 Jul 29 07:08:08 PM PDT 24 66796338 ps
T616 /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.3243080435 Jul 29 07:07:57 PM PDT 24 Jul 29 07:07:58 PM PDT 24 69878893 ps
T617 /workspace/coverage/default/13.pwrmgr_escalation_timeout.2702695647 Jul 29 07:07:16 PM PDT 24 Jul 29 07:07:17 PM PDT 24 165942532 ps
T618 /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.591053337 Jul 29 07:08:24 PM PDT 24 Jul 29 07:08:25 PM PDT 24 38780022 ps
T619 /workspace/coverage/default/33.pwrmgr_global_esc.485970291 Jul 29 07:08:34 PM PDT 24 Jul 29 07:08:35 PM PDT 24 33047781 ps
T620 /workspace/coverage/default/20.pwrmgr_aborted_low_power.1802106901 Jul 29 07:07:54 PM PDT 24 Jul 29 07:07:55 PM PDT 24 32249929 ps
T621 /workspace/coverage/default/48.pwrmgr_global_esc.750230173 Jul 29 07:09:12 PM PDT 24 Jul 29 07:09:13 PM PDT 24 47334870 ps
T622 /workspace/coverage/default/45.pwrmgr_reset.3781057272 Jul 29 07:09:09 PM PDT 24 Jul 29 07:09:10 PM PDT 24 62369056 ps
T623 /workspace/coverage/default/0.pwrmgr_global_esc.3422868481 Jul 29 07:06:31 PM PDT 24 Jul 29 07:06:32 PM PDT 24 34193789 ps
T624 /workspace/coverage/default/16.pwrmgr_smoke.205573986 Jul 29 07:07:37 PM PDT 24 Jul 29 07:07:38 PM PDT 24 29567107 ps
T625 /workspace/coverage/default/31.pwrmgr_global_esc.1080153022 Jul 29 07:08:29 PM PDT 24 Jul 29 07:08:30 PM PDT 24 129774033 ps
T626 /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.271701063 Jul 29 07:08:08 PM PDT 24 Jul 29 07:08:09 PM PDT 24 72797668 ps
T34 /workspace/coverage/default/0.pwrmgr_sec_cm.265677936 Jul 29 07:06:41 PM PDT 24 Jul 29 07:06:44 PM PDT 24 585336792 ps
T627 /workspace/coverage/default/5.pwrmgr_smoke.1821275943 Jul 29 07:06:46 PM PDT 24 Jul 29 07:06:47 PM PDT 24 28195801 ps
T628 /workspace/coverage/default/18.pwrmgr_glitch.3524127810 Jul 29 07:07:45 PM PDT 24 Jul 29 07:07:46 PM PDT 24 51742743 ps
T629 /workspace/coverage/default/2.pwrmgr_reset_invalid.1785244698 Jul 29 07:06:46 PM PDT 24 Jul 29 07:06:47 PM PDT 24 90937142 ps
T630 /workspace/coverage/default/4.pwrmgr_aborted_low_power.562654350 Jul 29 07:06:47 PM PDT 24 Jul 29 07:06:48 PM PDT 24 31013786 ps
T631 /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2240476077 Jul 29 07:07:40 PM PDT 24 Jul 29 07:07:41 PM PDT 24 78489567 ps
T632 /workspace/coverage/default/34.pwrmgr_glitch.246586444 Jul 29 07:08:36 PM PDT 24 Jul 29 07:08:37 PM PDT 24 70075895 ps
T20 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1553015145 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:50 PM PDT 24 246841429 ps
T72 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.485595429 Jul 29 07:02:05 PM PDT 24 Jul 29 07:02:06 PM PDT 24 16973815 ps
T73 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.976616338 Jul 29 07:01:10 PM PDT 24 Jul 29 07:01:11 PM PDT 24 25077490 ps
T21 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2500803343 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:49 PM PDT 24 140226394 ps
T22 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4062588312 Jul 29 07:01:54 PM PDT 24 Jul 29 07:01:56 PM PDT 24 52495055 ps
T67 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.144555197 Jul 29 07:01:03 PM PDT 24 Jul 29 07:01:06 PM PDT 24 77076488 ps
T74 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2254009947 Jul 29 07:02:06 PM PDT 24 Jul 29 07:02:07 PM PDT 24 30212635 ps
T59 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1227622423 Jul 29 07:01:36 PM PDT 24 Jul 29 07:01:38 PM PDT 24 253353084 ps
T58 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3823895831 Jul 29 07:01:52 PM PDT 24 Jul 29 07:01:53 PM PDT 24 38166525 ps
T92 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3866292592 Jul 29 07:01:06 PM PDT 24 Jul 29 07:01:07 PM PDT 24 39492984 ps
T114 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2300404493 Jul 29 07:01:52 PM PDT 24 Jul 29 07:01:53 PM PDT 24 87999937 ps
T168 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.45164372 Jul 29 07:02:06 PM PDT 24 Jul 29 07:02:07 PM PDT 24 31273556 ps
T63 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2302303809 Jul 29 07:01:33 PM PDT 24 Jul 29 07:01:34 PM PDT 24 45055336 ps
T69 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.106417309 Jul 29 07:01:34 PM PDT 24 Jul 29 07:01:35 PM PDT 24 35637954 ps
T115 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1379579686 Jul 29 07:01:26 PM PDT 24 Jul 29 07:01:27 PM PDT 24 25324381 ps
T60 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4105635949 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:53 PM PDT 24 178618198 ps
T116 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1586465882 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:50 PM PDT 24 96756880 ps
T117 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.4261942649 Jul 29 07:00:52 PM PDT 24 Jul 29 07:00:52 PM PDT 24 21287516 ps
T169 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1174796662 Jul 29 07:02:03 PM PDT 24 Jul 29 07:02:04 PM PDT 24 18465534 ps
T118 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.3315720681 Jul 29 07:01:21 PM PDT 24 Jul 29 07:01:22 PM PDT 24 43785012 ps
T70 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3967169598 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:53 PM PDT 24 492452345 ps
T170 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.74400185 Jul 29 07:00:51 PM PDT 24 Jul 29 07:00:52 PM PDT 24 43126025 ps
T103 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1966571397 Jul 29 07:01:47 PM PDT 24 Jul 29 07:01:48 PM PDT 24 36337947 ps
T119 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1343605532 Jul 29 07:00:56 PM PDT 24 Jul 29 07:00:57 PM PDT 24 33402193 ps
T75 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3937446663 Jul 29 07:01:09 PM PDT 24 Jul 29 07:01:11 PM PDT 24 199529161 ps
T135 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3307428401 Jul 29 07:01:10 PM PDT 24 Jul 29 07:01:12 PM PDT 24 474845158 ps
T633 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.164869876 Jul 29 07:02:00 PM PDT 24 Jul 29 07:02:01 PM PDT 24 53251533 ps
T104 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3596026228 Jul 29 07:01:26 PM PDT 24 Jul 29 07:01:26 PM PDT 24 20409279 ps
T171 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.419199069 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:13 PM PDT 24 17825086 ps
T172 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.764140655 Jul 29 07:01:38 PM PDT 24 Jul 29 07:01:38 PM PDT 24 18866419 ps
T71 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3557556430 Jul 29 07:01:55 PM PDT 24 Jul 29 07:01:57 PM PDT 24 78055268 ps
T105 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1777816601 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:13 PM PDT 24 3069539405 ps
T120 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3628968867 Jul 29 07:01:32 PM PDT 24 Jul 29 07:01:33 PM PDT 24 33936770 ps
T78 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2407708554 Jul 29 07:01:22 PM PDT 24 Jul 29 07:01:24 PM PDT 24 245450468 ps
T634 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3104074908 Jul 29 07:00:56 PM PDT 24 Jul 29 07:00:57 PM PDT 24 90752338 ps
T62 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.322609705 Jul 29 07:01:53 PM PDT 24 Jul 29 07:01:54 PM PDT 24 105176781 ps
T635 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.166493256 Jul 29 07:01:59 PM PDT 24 Jul 29 07:02:00 PM PDT 24 29898571 ps
T106 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3111164275 Jul 29 07:01:17 PM PDT 24 Jul 29 07:01:17 PM PDT 24 43219563 ps
T121 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3150189813 Jul 29 07:01:52 PM PDT 24 Jul 29 07:01:53 PM PDT 24 40720866 ps
T636 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1677499120 Jul 29 07:01:43 PM PDT 24 Jul 29 07:01:45 PM PDT 24 203851855 ps
T637 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3044551370 Jul 29 07:01:59 PM PDT 24 Jul 29 07:02:00 PM PDT 24 59582193 ps
T136 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.704635183 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:52 PM PDT 24 103766501 ps
T79 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.451915382 Jul 29 07:01:12 PM PDT 24 Jul 29 07:01:14 PM PDT 24 203248580 ps
T638 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.4279496863 Jul 29 07:01:37 PM PDT 24 Jul 29 07:01:37 PM PDT 24 28284197 ps
T639 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1831388742 Jul 29 07:01:17 PM PDT 24 Jul 29 07:01:18 PM PDT 24 93712682 ps
T640 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1734720 Jul 29 07:01:51 PM PDT 24 Jul 29 07:01:52 PM PDT 24 36678932 ps
T641 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2204816601 Jul 29 07:00:51 PM PDT 24 Jul 29 07:00:52 PM PDT 24 50718636 ps
T137 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1544730666 Jul 29 07:01:34 PM PDT 24 Jul 29 07:01:36 PM PDT 24 199528359 ps
T138 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2208227146 Jul 29 07:01:29 PM PDT 24 Jul 29 07:01:31 PM PDT 24 294210686 ps
T642 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1716017603 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:51 PM PDT 24 98520042 ps
T643 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3891829886 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 48578096 ps
T644 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3791329514 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:49 PM PDT 24 22495898 ps
T76 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.122807137 Jul 29 07:01:51 PM PDT 24 Jul 29 07:01:53 PM PDT 24 189262015 ps
T645 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3596639228 Jul 29 07:01:10 PM PDT 24 Jul 29 07:01:11 PM PDT 24 20091292 ps
T646 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3085970663 Jul 29 07:02:06 PM PDT 24 Jul 29 07:02:07 PM PDT 24 46405883 ps
T647 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3190459381 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:49 PM PDT 24 22727865 ps
T648 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1971683573 Jul 29 07:01:59 PM PDT 24 Jul 29 07:02:00 PM PDT 24 21758482 ps
T649 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1715088282 Jul 29 07:01:12 PM PDT 24 Jul 29 07:01:13 PM PDT 24 44423186 ps
T113 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3290246423 Jul 29 07:00:52 PM PDT 24 Jul 29 07:00:56 PM PDT 24 325316639 ps
T173 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3111855096 Jul 29 07:02:06 PM PDT 24 Jul 29 07:02:06 PM PDT 24 25635043 ps
T650 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1955753567 Jul 29 07:01:18 PM PDT 24 Jul 29 07:01:19 PM PDT 24 44777300 ps
T651 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2285655592 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 44172156 ps
T652 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2777139916 Jul 29 07:01:46 PM PDT 24 Jul 29 07:01:46 PM PDT 24 53955836 ps
T653 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2438555769 Jul 29 07:01:19 PM PDT 24 Jul 29 07:01:22 PM PDT 24 416942182 ps
T654 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.4026481194 Jul 29 07:01:32 PM PDT 24 Jul 29 07:01:34 PM PDT 24 55843201 ps
T655 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1279310076 Jul 29 07:02:08 PM PDT 24 Jul 29 07:02:09 PM PDT 24 41238448 ps
T656 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.830813096 Jul 29 07:01:52 PM PDT 24 Jul 29 07:01:53 PM PDT 24 143849912 ps
T156 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1749151079 Jul 29 07:01:22 PM PDT 24 Jul 29 07:01:24 PM PDT 24 224045810 ps
T657 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.456536190 Jul 29 07:01:33 PM PDT 24 Jul 29 07:01:34 PM PDT 24 28675425 ps
T658 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2005078006 Jul 29 07:01:09 PM PDT 24 Jul 29 07:01:10 PM PDT 24 135756592 ps
T659 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1259330580 Jul 29 07:00:56 PM PDT 24 Jul 29 07:00:57 PM PDT 24 17911496 ps
T660 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2466570422 Jul 29 07:01:28 PM PDT 24 Jul 29 07:01:30 PM PDT 24 294625089 ps
T661 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.169115854 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:50 PM PDT 24 29714746 ps
T662 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3047254096 Jul 29 07:01:23 PM PDT 24 Jul 29 07:01:25 PM PDT 24 169741167 ps
T663 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3701178822 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 22334346 ps
T664 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1435980911 Jul 29 07:01:19 PM PDT 24 Jul 29 07:01:20 PM PDT 24 39976848 ps
T665 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4030805944 Jul 29 07:01:54 PM PDT 24 Jul 29 07:01:54 PM PDT 24 26296273 ps
T666 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1894873630 Jul 29 07:01:27 PM PDT 24 Jul 29 07:01:28 PM PDT 24 19483724 ps
T667 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2430177457 Jul 29 07:01:38 PM PDT 24 Jul 29 07:01:39 PM PDT 24 87674111 ps
T668 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2046669711 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 20196643 ps
T669 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2495457971 Jul 29 07:01:29 PM PDT 24 Jul 29 07:01:30 PM PDT 24 20578924 ps
T670 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3306057729 Jul 29 07:01:32 PM PDT 24 Jul 29 07:01:33 PM PDT 24 31266597 ps
T671 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1959693759 Jul 29 07:01:34 PM PDT 24 Jul 29 07:01:36 PM PDT 24 182667083 ps
T672 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.425582004 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:48 PM PDT 24 38198327 ps
T673 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2036569275 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 46578808 ps
T674 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2956660945 Jul 29 07:01:17 PM PDT 24 Jul 29 07:01:19 PM PDT 24 51419684 ps
T675 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3462029731 Jul 29 07:01:27 PM PDT 24 Jul 29 07:01:29 PM PDT 24 182610238 ps
T676 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1966106733 Jul 29 07:02:11 PM PDT 24 Jul 29 07:02:11 PM PDT 24 22689818 ps
T677 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3243797193 Jul 29 07:01:31 PM PDT 24 Jul 29 07:01:32 PM PDT 24 212595308 ps
T678 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1904583135 Jul 29 07:01:17 PM PDT 24 Jul 29 07:01:18 PM PDT 24 52908390 ps
T679 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.313913282 Jul 29 07:01:58 PM PDT 24 Jul 29 07:01:59 PM PDT 24 83864081 ps
T680 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1687540868 Jul 29 07:01:15 PM PDT 24 Jul 29 07:01:17 PM PDT 24 252618019 ps
T681 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2922332088 Jul 29 07:01:27 PM PDT 24 Jul 29 07:01:28 PM PDT 24 50720336 ps
T682 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3290725143 Jul 29 07:01:27 PM PDT 24 Jul 29 07:01:28 PM PDT 24 19898626 ps
T683 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2319563264 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:49 PM PDT 24 27097741 ps
T684 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.4243219614 Jul 29 07:01:37 PM PDT 24 Jul 29 07:01:40 PM PDT 24 189999343 ps
T685 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1034882525 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:50 PM PDT 24 154244484 ps
T686 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1850392908 Jul 29 07:01:38 PM PDT 24 Jul 29 07:01:38 PM PDT 24 19783836 ps
T687 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.305931915 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:14 PM PDT 24 147524592 ps
T688 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3899632217 Jul 29 07:02:00 PM PDT 24 Jul 29 07:02:00 PM PDT 24 31106523 ps
T689 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1688652415 Jul 29 07:01:39 PM PDT 24 Jul 29 07:01:39 PM PDT 24 44217241 ps
T690 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2857522483 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:51 PM PDT 24 46841376 ps
T691 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.523636910 Jul 29 07:01:28 PM PDT 24 Jul 29 07:01:29 PM PDT 24 40717346 ps
T692 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3920973281 Jul 29 07:02:00 PM PDT 24 Jul 29 07:02:01 PM PDT 24 34884821 ps
T693 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2152107313 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 16955865 ps
T694 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1144395900 Jul 29 07:01:12 PM PDT 24 Jul 29 07:01:13 PM PDT 24 22653969 ps
T695 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1018509544 Jul 29 07:01:44 PM PDT 24 Jul 29 07:01:45 PM PDT 24 21933213 ps
T696 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1772640206 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 23630848 ps
T697 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1681681676 Jul 29 07:01:29 PM PDT 24 Jul 29 07:01:29 PM PDT 24 26479544 ps
T698 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2212406787 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:51 PM PDT 24 42527150 ps
T107 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.537590993 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 31741584 ps
T77 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1492036325 Jul 29 07:00:52 PM PDT 24 Jul 29 07:00:53 PM PDT 24 125471372 ps
T699 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3876695378 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:51 PM PDT 24 24296630 ps
T700 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3170710776 Jul 29 07:01:33 PM PDT 24 Jul 29 07:01:34 PM PDT 24 66917319 ps
T701 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.875005967 Jul 29 07:01:53 PM PDT 24 Jul 29 07:01:54 PM PDT 24 19441377 ps
T702 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.198477582 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:14 PM PDT 24 120024253 ps
T703 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1375838731 Jul 29 07:02:03 PM PDT 24 Jul 29 07:02:04 PM PDT 24 43492087 ps
T704 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.408901196 Jul 29 07:01:50 PM PDT 24 Jul 29 07:01:51 PM PDT 24 171058772 ps
T705 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1986599567 Jul 29 07:01:34 PM PDT 24 Jul 29 07:01:35 PM PDT 24 55338322 ps
T706 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4053721805 Jul 29 07:01:58 PM PDT 24 Jul 29 07:01:59 PM PDT 24 19172383 ps
T707 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.116715985 Jul 29 07:02:10 PM PDT 24 Jul 29 07:02:11 PM PDT 24 15709313 ps
T708 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1457719589 Jul 29 07:01:54 PM PDT 24 Jul 29 07:01:57 PM PDT 24 113407532 ps
T709 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2023620274 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 124189045 ps
T710 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.734607909 Jul 29 07:01:13 PM PDT 24 Jul 29 07:01:14 PM PDT 24 101531753 ps
T711 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2719062439 Jul 29 07:01:47 PM PDT 24 Jul 29 07:01:48 PM PDT 24 2188938884 ps
T80 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.791718902 Jul 29 07:01:29 PM PDT 24 Jul 29 07:01:30 PM PDT 24 107578732 ps
T108 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.4242301349 Jul 29 07:00:51 PM PDT 24 Jul 29 07:00:52 PM PDT 24 23860431 ps
T712 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1650338958 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 47328891 ps
T713 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2224698168 Jul 29 07:02:05 PM PDT 24 Jul 29 07:02:06 PM PDT 24 48521541 ps
T714 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.606988597 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 21125123 ps
T715 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2784043423 Jul 29 07:01:44 PM PDT 24 Jul 29 07:01:45 PM PDT 24 164572507 ps
T716 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4208167962 Jul 29 07:01:16 PM PDT 24 Jul 29 07:01:17 PM PDT 24 25573466 ps
T717 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3971236763 Jul 29 07:02:04 PM PDT 24 Jul 29 07:02:05 PM PDT 24 18376129 ps
T109 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.656036702 Jul 29 07:01:53 PM PDT 24 Jul 29 07:01:53 PM PDT 24 36445665 ps
T718 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.829490824 Jul 29 07:01:23 PM PDT 24 Jul 29 07:01:24 PM PDT 24 16839486 ps
T719 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3969724248 Jul 29 07:02:06 PM PDT 24 Jul 29 07:02:07 PM PDT 24 57660405 ps
T720 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3267472297 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:12 PM PDT 24 25820332 ps
T721 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3533427700 Jul 29 07:02:08 PM PDT 24 Jul 29 07:02:09 PM PDT 24 47771640 ps
T722 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1648436886 Jul 29 07:01:51 PM PDT 24 Jul 29 07:01:52 PM PDT 24 20612935 ps
T723 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3944322724 Jul 29 07:02:07 PM PDT 24 Jul 29 07:02:08 PM PDT 24 51667555 ps
T724 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3529016425 Jul 29 07:00:51 PM PDT 24 Jul 29 07:00:54 PM PDT 24 49743026 ps
T725 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3753270022 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:51 PM PDT 24 164778954 ps
T110 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2259285217 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:13 PM PDT 24 34623411 ps
T726 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1933169742 Jul 29 07:01:44 PM PDT 24 Jul 29 07:01:47 PM PDT 24 180400944 ps
T727 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.3701364853 Jul 29 07:01:31 PM PDT 24 Jul 29 07:01:32 PM PDT 24 22292686 ps
T728 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.277907180 Jul 29 07:01:48 PM PDT 24 Jul 29 07:01:49 PM PDT 24 43039340 ps
T729 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2365527320 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:50 PM PDT 24 22191735 ps
T730 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.361171201 Jul 29 07:01:12 PM PDT 24 Jul 29 07:01:13 PM PDT 24 53657601 ps
T731 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.4094459922 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:50 PM PDT 24 814961977 ps
T732 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1659374726 Jul 29 07:01:32 PM PDT 24 Jul 29 07:01:34 PM PDT 24 156685252 ps
T733 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2432638841 Jul 29 07:01:23 PM PDT 24 Jul 29 07:01:23 PM PDT 24 21422178 ps
T734 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3026397503 Jul 29 07:01:49 PM PDT 24 Jul 29 07:01:49 PM PDT 24 18997777 ps
T735 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.515206604 Jul 29 07:01:26 PM PDT 24 Jul 29 07:01:27 PM PDT 24 33305098 ps
T736 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1980762863 Jul 29 07:01:36 PM PDT 24 Jul 29 07:01:37 PM PDT 24 32416441 ps
T737 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3909751316 Jul 29 07:00:57 PM PDT 24 Jul 29 07:00:58 PM PDT 24 52968478 ps
T738 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2553338065 Jul 29 07:01:40 PM PDT 24 Jul 29 07:01:41 PM PDT 24 297980985 ps
T739 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1028945872 Jul 29 07:00:56 PM PDT 24 Jul 29 07:00:57 PM PDT 24 102542255 ps
T111 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.481945614 Jul 29 07:01:44 PM PDT 24 Jul 29 07:01:44 PM PDT 24 21238309 ps
T740 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1635855999 Jul 29 07:01:36 PM PDT 24 Jul 29 07:01:37 PM PDT 24 361731754 ps
T741 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2986391494 Jul 29 07:01:27 PM PDT 24 Jul 29 07:01:28 PM PDT 24 69235902 ps
T742 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1368096227 Jul 29 07:01:33 PM PDT 24 Jul 29 07:01:34 PM PDT 24 40018721 ps
T743 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1042627720 Jul 29 07:02:03 PM PDT 24 Jul 29 07:02:04 PM PDT 24 48508846 ps
T744 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.12637229 Jul 29 07:01:12 PM PDT 24 Jul 29 07:01:13 PM PDT 24 79053130 ps
T745 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1615790531 Jul 29 07:01:32 PM PDT 24 Jul 29 07:01:32 PM PDT 24 83626731 ps
T112 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.371197046 Jul 29 07:01:11 PM PDT 24 Jul 29 07:01:13 PM PDT 24 25752326 ps

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2050738386
Short name T5
Test name
Test status
Simulation time 38989264 ps
CPU time 0.83 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:18 PM PDT 24
Peak memory 200160 kb
Host smart-8976c66c-06d2-4ada-81d0-ec4e0666c1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050738386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2050738386
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1998969611
Short name T40
Test name
Test status
Simulation time 110761360 ps
CPU time 1.03 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 209096 kb
Host smart-ad75dc40-8d01-4996-b08d-28bfa5ebfbec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998969611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1998969611
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.746640137
Short name T11
Test name
Test status
Simulation time 209648809 ps
CPU time 0.66 seconds
Started Jul 29 07:08:02 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 198480 kb
Host smart-33650e00-ff43-4bb0-85e3-90cfdc79bdd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746640137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.746640137
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3354717791
Short name T7
Test name
Test status
Simulation time 50196479 ps
CPU time 0.84 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 199332 kb
Host smart-8cd6c115-9478-471a-9e02-24e065496c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354717791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3354717791
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4062588312
Short name T22
Test name
Test status
Simulation time 52495055 ps
CPU time 1.4 seconds
Started Jul 29 07:01:54 PM PDT 24
Finished Jul 29 07:01:56 PM PDT 24
Peak memory 196384 kb
Host smart-4822a7bb-4d99-4366-92ff-a59f5ae50c0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062588312 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.4062588312
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2714567187
Short name T17
Test name
Test status
Simulation time 325354747 ps
CPU time 1.5 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:50 PM PDT 24
Peak memory 216868 kb
Host smart-893431e0-24bd-41ea-a299-b084c3e7629a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714567187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2714567187
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3737922319
Short name T14
Test name
Test status
Simulation time 44778291 ps
CPU time 0.72 seconds
Started Jul 29 07:08:23 PM PDT 24
Finished Jul 29 07:08:24 PM PDT 24
Peak memory 201200 kb
Host smart-f1e63e8a-f1d8-418a-acb1-f81dd729c394
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737922319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3737922319
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.3073563099
Short name T24
Test name
Test status
Simulation time 296360316 ps
CPU time 0.76 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 199384 kb
Host smart-c2d349ab-0aa5-49bc-a8d0-6a46cce02c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073563099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.3073563099
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1227622423
Short name T59
Test name
Test status
Simulation time 253353084 ps
CPU time 1.57 seconds
Started Jul 29 07:01:36 PM PDT 24
Finished Jul 29 07:01:38 PM PDT 24
Peak memory 200668 kb
Host smart-6059af93-99a6-4e55-8ffa-e1ed5faa79e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227622423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1227622423
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1956739478
Short name T126
Test name
Test status
Simulation time 97033275 ps
CPU time 0.92 seconds
Started Jul 29 07:09:16 PM PDT 24
Finished Jul 29 07:09:17 PM PDT 24
Peak memory 199668 kb
Host smart-a0d478df-88bc-44f0-99c4-2733f57527bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956739478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1956739478
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.402586197
Short name T66
Test name
Test status
Simulation time 135351959 ps
CPU time 1.09 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:08 PM PDT 24
Peak memory 199740 kb
Host smart-48f5a1b7-498b-4144-af04-bf7fc13c13ec
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402586197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_c
m_ctrl_config_regwen.402586197
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1777816601
Short name T105
Test name
Test status
Simulation time 3069539405 ps
CPU time 2.16 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 195380 kb
Host smart-72d117d5-8b26-4e14-9948-5ce7b90a170b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777816601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
777816601
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1504444811
Short name T224
Test name
Test status
Simulation time 90397274 ps
CPU time 0.84 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 199420 kb
Host smart-6d69456a-1e41-47ec-901c-657f64c27c33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504444811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1504444811
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.166493256
Short name T635
Test name
Test status
Simulation time 29898571 ps
CPU time 0.63 seconds
Started Jul 29 07:01:59 PM PDT 24
Finished Jul 29 07:02:00 PM PDT 24
Peak memory 195072 kb
Host smart-2e0912ee-d468-4e18-b157-b4bc80f1496e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166493256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.166493256
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3517478170
Short name T46
Test name
Test status
Simulation time 31851022 ps
CPU time 0.62 seconds
Started Jul 29 07:08:53 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 198264 kb
Host smart-7cee4fff-a339-464e-bcda-ab0b09b4d872
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517478170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3517478170
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2444387018
Short name T201
Test name
Test status
Simulation time 43820129 ps
CPU time 0.73 seconds
Started Jul 29 07:09:06 PM PDT 24
Finished Jul 29 07:09:07 PM PDT 24
Peak memory 201616 kb
Host smart-45026c1b-99b8-4215-8eb8-3d91d88072e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444387018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2444387018
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.3705103144
Short name T51
Test name
Test status
Simulation time 58883442 ps
CPU time 0.6 seconds
Started Jul 29 07:06:33 PM PDT 24
Finished Jul 29 07:06:34 PM PDT 24
Peak memory 198232 kb
Host smart-a67cbea3-aa3c-4c7c-8f2c-58828db045cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705103144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3705103144
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1841419695
Short name T57
Test name
Test status
Simulation time 38887739 ps
CPU time 1.09 seconds
Started Jul 29 07:08:46 PM PDT 24
Finished Jul 29 07:08:47 PM PDT 24
Peak memory 200976 kb
Host smart-1b189de5-7a0c-41f0-b9c4-0f16b2688751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841419695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1841419695
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.213294670
Short name T158
Test name
Test status
Simulation time 89538197 ps
CPU time 0.71 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 199180 kb
Host smart-84e3cb7e-e845-4966-b244-2a9e7267381b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213294670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.213294670
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.35408201
Short name T133
Test name
Test status
Simulation time 115342763 ps
CPU time 0.86 seconds
Started Jul 29 07:07:06 PM PDT 24
Finished Jul 29 07:07:06 PM PDT 24
Peak memory 201384 kb
Host smart-500909bf-dde5-441e-8bd4-4a0afcbdb7c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.35408201
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.1648531165
Short name T159
Test name
Test status
Simulation time 67045579 ps
CPU time 0.66 seconds
Started Jul 29 07:07:21 PM PDT 24
Finished Jul 29 07:07:22 PM PDT 24
Peak memory 198360 kb
Host smart-29ed620b-f0d7-457c-af77-002c4e8d3d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648531165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.1648531165
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.2316147605
Short name T48
Test name
Test status
Simulation time 60351015 ps
CPU time 0.8 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 198392 kb
Host smart-5ae7c089-c4b8-4bda-b7ba-6eed7d1096ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316147605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2316147605
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4125173486
Short name T142
Test name
Test status
Simulation time 64145908 ps
CPU time 0.64 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:13 PM PDT 24
Peak memory 198208 kb
Host smart-e537b1a3-60b4-45c9-9a9d-1623ae48b2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125173486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.4125173486
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.3572290532
Short name T155
Test name
Test status
Simulation time 89987324 ps
CPU time 0.67 seconds
Started Jul 29 07:08:01 PM PDT 24
Finished Jul 29 07:08:02 PM PDT 24
Peak memory 198344 kb
Host smart-eb73137a-c3bd-4464-afce-73fe0685fbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572290532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.3572290532
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.743686254
Short name T27
Test name
Test status
Simulation time 66205901 ps
CPU time 0.75 seconds
Started Jul 29 07:07:36 PM PDT 24
Finished Jul 29 07:07:37 PM PDT 24
Peak memory 198972 kb
Host smart-2a7bc786-6fa5-44a3-9eca-4f5efa607958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743686254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.743686254
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.2110174713
Short name T54
Test name
Test status
Simulation time 52826760 ps
CPU time 0.99 seconds
Started Jul 29 07:07:50 PM PDT 24
Finished Jul 29 07:07:51 PM PDT 24
Peak memory 200256 kb
Host smart-0d7bf799-ac56-4619-90bd-28bc58b26a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110174713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.2110174713
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.671272022
Short name T90
Test name
Test status
Simulation time 57214659 ps
CPU time 0.63 seconds
Started Jul 29 07:06:39 PM PDT 24
Finished Jul 29 07:06:40 PM PDT 24
Peak memory 198460 kb
Host smart-74f51c36-837e-4cd5-9b56-f4304ecd31b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671272022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.671272022
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.3047220932
Short name T211
Test name
Test status
Simulation time 44784223 ps
CPU time 0.76 seconds
Started Jul 29 07:07:19 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 201396 kb
Host smart-2a7807f9-8088-479a-a746-42c799be5105
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047220932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.3047220932
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3376412167
Short name T192
Test name
Test status
Simulation time 54537157 ps
CPU time 0.67 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 201208 kb
Host smart-a936ea88-dbdf-4dd6-acf0-c0369bec303f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376412167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3376412167
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.4107971561
Short name T200
Test name
Test status
Simulation time 76666023 ps
CPU time 0.65 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 198152 kb
Host smart-69679c34-49db-48c6-8872-c086f206d1c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107971561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.4107971561
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3942810466
Short name T164
Test name
Test status
Simulation time 61292244 ps
CPU time 0.8 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 198444 kb
Host smart-14f8c715-1284-4ebb-96da-b579487f2228
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942810466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.3942810466
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.3944339852
Short name T84
Test name
Test status
Simulation time 168477624 ps
CPU time 0.66 seconds
Started Jul 29 07:09:00 PM PDT 24
Finished Jul 29 07:09:01 PM PDT 24
Peak memory 201372 kb
Host smart-14152799-8674-4745-851a-5e4ce42196a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944339852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.3944339852
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.4261942649
Short name T117
Test name
Test status
Simulation time 21287516 ps
CPU time 0.62 seconds
Started Jul 29 07:00:52 PM PDT 24
Finished Jul 29 07:00:52 PM PDT 24
Peak memory 197324 kb
Host smart-0d040d10-92b9-4bb7-bd83-184c314221f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261942649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.4261942649
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.265677936
Short name T34
Test name
Test status
Simulation time 585336792 ps
CPU time 2.12 seconds
Started Jul 29 07:06:41 PM PDT 24
Finished Jul 29 07:06:44 PM PDT 24
Peak memory 217936 kb
Host smart-dd4f79c5-f8be-4a1e-bd74-96ea1efa84d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265677936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.265677936
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3306057729
Short name T670
Test name
Test status
Simulation time 31266597 ps
CPU time 0.61 seconds
Started Jul 29 07:01:32 PM PDT 24
Finished Jul 29 07:01:33 PM PDT 24
Peak memory 195104 kb
Host smart-39bda5b2-b458-443c-9c5b-a02272164074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306057729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3306057729
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.1706952995
Short name T190
Test name
Test status
Simulation time 111378429 ps
CPU time 0.65 seconds
Started Jul 29 07:06:36 PM PDT 24
Finished Jul 29 07:06:37 PM PDT 24
Peak memory 201396 kb
Host smart-592fb86c-1c21-49b0-a66a-6874e310d916
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706952995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.1706952995
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2091734009
Short name T187
Test name
Test status
Simulation time 120802706 ps
CPU time 0.67 seconds
Started Jul 29 07:07:24 PM PDT 24
Finished Jul 29 07:07:25 PM PDT 24
Peak memory 201412 kb
Host smart-a9b1952e-147b-4244-bce3-108a35e6254b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091734009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.2091734009
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.2923227131
Short name T215
Test name
Test status
Simulation time 108980936 ps
CPU time 0.66 seconds
Started Jul 29 07:07:37 PM PDT 24
Finished Jul 29 07:07:38 PM PDT 24
Peak memory 198528 kb
Host smart-bfe7cd89-7a80-4f7c-bbd3-04ac1bdd8383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923227131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2923227131
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.1439439796
Short name T152
Test name
Test status
Simulation time 54467505 ps
CPU time 0.65 seconds
Started Jul 29 07:07:54 PM PDT 24
Finished Jul 29 07:07:55 PM PDT 24
Peak memory 198248 kb
Host smart-011a45a0-25f3-4304-8bc0-c50d07954e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439439796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.1439439796
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.4141735945
Short name T25
Test name
Test status
Simulation time 72381939 ps
CPU time 0.63 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:08:00 PM PDT 24
Peak memory 198232 kb
Host smart-9c25ca3c-bd00-45f5-bf87-e54b1c888e60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141735945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.4141735945
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2136212942
Short name T167
Test name
Test status
Simulation time 53743476 ps
CPU time 0.81 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 199216 kb
Host smart-98dd62ad-33df-4928-baf3-15929c20d634
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136212942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2136212942
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3749168317
Short name T186
Test name
Test status
Simulation time 42480032 ps
CPU time 0.72 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 201316 kb
Host smart-ea959bc7-de58-4ff7-8f91-4931fdb31108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749168317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3749168317
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.166324372
Short name T204
Test name
Test status
Simulation time 51568556 ps
CPU time 0.7 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 201356 kb
Host smart-2cf9622f-554a-43f7-bab2-54e16da50022
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166324372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.166324372
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2089384188
Short name T216
Test name
Test status
Simulation time 45996941 ps
CPU time 0.64 seconds
Started Jul 29 07:08:58 PM PDT 24
Finished Jul 29 07:08:59 PM PDT 24
Peak memory 198504 kb
Host smart-21aae64f-37b3-4f6f-b21b-7cd6ec9999bb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089384188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2089384188
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3704967323
Short name T163
Test name
Test status
Simulation time 59713346 ps
CPU time 0.69 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:46 PM PDT 24
Peak memory 199132 kb
Host smart-62a0e399-e7b6-4be0-990a-b264d1b1ba3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704967323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3704967323
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1492036325
Short name T77
Test name
Test status
Simulation time 125471372 ps
CPU time 1.1 seconds
Started Jul 29 07:00:52 PM PDT 24
Finished Jul 29 07:00:53 PM PDT 24
Peak memory 200644 kb
Host smart-7cf71c7e-6d5b-4cc4-add8-5a9d29b621e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492036325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.1492036325
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3104074908
Short name T634
Test name
Test status
Simulation time 90752338 ps
CPU time 1.46 seconds
Started Jul 29 07:00:56 PM PDT 24
Finished Jul 29 07:00:57 PM PDT 24
Peak memory 196432 kb
Host smart-53405474-2701-43bb-b7d9-e7ae7f14c5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104074908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3104074908
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.322609705
Short name T62
Test name
Test status
Simulation time 105176781 ps
CPU time 1.07 seconds
Started Jul 29 07:01:53 PM PDT 24
Finished Jul 29 07:01:54 PM PDT 24
Peak memory 195408 kb
Host smart-bb1c4b17-587f-4668-bf56-b92a4e93eb3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322609705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err
.322609705
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.188309024
Short name T16
Test name
Test status
Simulation time 52086352 ps
CPU time 0.6 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 198120 kb
Host smart-e7564c05-9369-4f63-b007-bceaee4bc4c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188309024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.188309024
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2204816601
Short name T641
Test name
Test status
Simulation time 50718636 ps
CPU time 0.88 seconds
Started Jul 29 07:00:51 PM PDT 24
Finished Jul 29 07:00:52 PM PDT 24
Peak memory 195056 kb
Host smart-c201961a-6009-46f2-9acc-45dc6968e806
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204816601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
204816601
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3290246423
Short name T113
Test name
Test status
Simulation time 325316639 ps
CPU time 3.32 seconds
Started Jul 29 07:00:52 PM PDT 24
Finished Jul 29 07:00:56 PM PDT 24
Peak memory 199104 kb
Host smart-fab128db-d979-4afb-964f-9af017e9096d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290246423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
290246423
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.4242301349
Short name T108
Test name
Test status
Simulation time 23860431 ps
CPU time 0.64 seconds
Started Jul 29 07:00:51 PM PDT 24
Finished Jul 29 07:00:52 PM PDT 24
Peak memory 197660 kb
Host smart-578e5da9-1f54-4218-be82-4d35719ff4a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242301349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.4
242301349
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3909751316
Short name T737
Test name
Test status
Simulation time 52968478 ps
CPU time 0.75 seconds
Started Jul 29 07:00:57 PM PDT 24
Finished Jul 29 07:00:58 PM PDT 24
Peak memory 195316 kb
Host smart-6d88f677-c443-41d5-a088-e41f922c55df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909751316 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3909751316
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.74400185
Short name T170
Test name
Test status
Simulation time 43126025 ps
CPU time 0.63 seconds
Started Jul 29 07:00:51 PM PDT 24
Finished Jul 29 07:00:52 PM PDT 24
Peak memory 195052 kb
Host smart-55c985e4-198c-432c-9985-09e59fed9e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74400185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.74400185
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1343605532
Short name T119
Test name
Test status
Simulation time 33402193 ps
CPU time 0.82 seconds
Started Jul 29 07:00:56 PM PDT 24
Finished Jul 29 07:00:57 PM PDT 24
Peak memory 195060 kb
Host smart-176403ab-e9ca-4b51-a498-b5aa840e0355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343605532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1343605532
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3529016425
Short name T724
Test name
Test status
Simulation time 49743026 ps
CPU time 2.3 seconds
Started Jul 29 07:00:51 PM PDT 24
Finished Jul 29 07:00:54 PM PDT 24
Peak memory 196408 kb
Host smart-1759dddb-1b6c-47e8-99a6-d6033edf671e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529016425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3529016425
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.537590993
Short name T107
Test name
Test status
Simulation time 31741584 ps
CPU time 0.83 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 197532 kb
Host smart-e09604f3-89bf-42b4-b52b-774c63145c90
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537590993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.537590993
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.144555197
Short name T67
Test name
Test status
Simulation time 77076488 ps
CPU time 2.8 seconds
Started Jul 29 07:01:03 PM PDT 24
Finished Jul 29 07:01:06 PM PDT 24
Peak memory 195268 kb
Host smart-0de95eea-0348-441f-8896-a366b37fb263
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144555197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.144555197
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1715088282
Short name T649
Test name
Test status
Simulation time 44423186 ps
CPU time 0.7 seconds
Started Jul 29 07:01:12 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 197732 kb
Host smart-1c92f112-ca6c-4931-a1e9-3233aa7d7806
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715088282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1
715088282
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.361171201
Short name T730
Test name
Test status
Simulation time 53657601 ps
CPU time 0.91 seconds
Started Jul 29 07:01:12 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 195184 kb
Host smart-810af1d9-7777-493d-90a7-85592b0cdc4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361171201 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.361171201
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3891829886
Short name T643
Test name
Test status
Simulation time 48578096 ps
CPU time 0.64 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 195120 kb
Host smart-4c9489ce-916d-4fa4-ac7d-1c24019ab16d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891829886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3891829886
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1259330580
Short name T659
Test name
Test status
Simulation time 17911496 ps
CPU time 0.65 seconds
Started Jul 29 07:00:56 PM PDT 24
Finished Jul 29 07:00:57 PM PDT 24
Peak memory 194988 kb
Host smart-a35c57ff-d50a-4418-8e04-461e60b14c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259330580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1259330580
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2023620274
Short name T709
Test name
Test status
Simulation time 124189045 ps
CPU time 0.89 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 195136 kb
Host smart-3ab4249c-37b3-47a9-b56e-208df6fb8790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023620274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.2023620274
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1028945872
Short name T739
Test name
Test status
Simulation time 102542255 ps
CPU time 1.11 seconds
Started Jul 29 07:00:56 PM PDT 24
Finished Jul 29 07:00:57 PM PDT 24
Peak memory 195428 kb
Host smart-0f3f4ea8-8aed-4d61-8dee-762088494f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028945872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1028945872
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2302303809
Short name T63
Test name
Test status
Simulation time 45055336 ps
CPU time 1.24 seconds
Started Jul 29 07:01:33 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 197824 kb
Host smart-cfafc13e-d5f7-4d2d-aff2-43bebea4b60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302303809 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2302303809
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1980762863
Short name T736
Test name
Test status
Simulation time 32416441 ps
CPU time 0.64 seconds
Started Jul 29 07:01:36 PM PDT 24
Finished Jul 29 07:01:37 PM PDT 24
Peak memory 197308 kb
Host smart-09704578-84db-4a1d-a964-22595aae904b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980762863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1980762863
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1635855999
Short name T740
Test name
Test status
Simulation time 361731754 ps
CPU time 0.89 seconds
Started Jul 29 07:01:36 PM PDT 24
Finished Jul 29 07:01:37 PM PDT 24
Peak memory 195124 kb
Host smart-cb32e6d6-495a-444c-bb49-a49c7f67affe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635855999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1635855999
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.4026481194
Short name T654
Test name
Test status
Simulation time 55843201 ps
CPU time 1.33 seconds
Started Jul 29 07:01:32 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 196396 kb
Host smart-4399ebb2-99ef-4d3c-909a-dcc827353b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026481194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.4026481194
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1544730666
Short name T137
Test name
Test status
Simulation time 199528359 ps
CPU time 1.75 seconds
Started Jul 29 07:01:34 PM PDT 24
Finished Jul 29 07:01:36 PM PDT 24
Peak memory 200508 kb
Host smart-14b02143-9e79-472c-925f-aebf442bcb05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544730666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1544730666
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.106417309
Short name T69
Test name
Test status
Simulation time 35637954 ps
CPU time 0.84 seconds
Started Jul 29 07:01:34 PM PDT 24
Finished Jul 29 07:01:35 PM PDT 24
Peak memory 195244 kb
Host smart-4f3b199f-5f52-4771-b685-399b8ada6801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106417309 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.106417309
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.456536190
Short name T657
Test name
Test status
Simulation time 28675425 ps
CPU time 0.64 seconds
Started Jul 29 07:01:33 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 197324 kb
Host smart-b93ae33d-ca40-4b42-83e8-8d5adb30d31e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456536190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.456536190
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1368096227
Short name T742
Test name
Test status
Simulation time 40018721 ps
CPU time 0.62 seconds
Started Jul 29 07:01:33 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 195084 kb
Host smart-ae5896ed-3e8e-436c-ae39-2add181cf8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368096227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1368096227
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3628968867
Short name T120
Test name
Test status
Simulation time 33936770 ps
CPU time 0.73 seconds
Started Jul 29 07:01:32 PM PDT 24
Finished Jul 29 07:01:33 PM PDT 24
Peak memory 195084 kb
Host smart-85042a3b-26ca-41ab-9be6-03d91e69cacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628968867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3628968867
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1659374726
Short name T732
Test name
Test status
Simulation time 156685252 ps
CPU time 1.53 seconds
Started Jul 29 07:01:32 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 196400 kb
Host smart-8770bc07-26be-496f-aaad-f160d13d6fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659374726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1659374726
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1959693759
Short name T671
Test name
Test status
Simulation time 182667083 ps
CPU time 1.63 seconds
Started Jul 29 07:01:34 PM PDT 24
Finished Jul 29 07:01:36 PM PDT 24
Peak memory 200620 kb
Host smart-4dc64e12-de54-4578-8cf6-9a4dc42721e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959693759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1959693759
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2777139916
Short name T652
Test name
Test status
Simulation time 53955836 ps
CPU time 0.67 seconds
Started Jul 29 07:01:46 PM PDT 24
Finished Jul 29 07:01:46 PM PDT 24
Peak memory 195316 kb
Host smart-aa2ce497-53cb-4c22-8e75-9d2b83f6cccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777139916 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2777139916
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.481945614
Short name T111
Test name
Test status
Simulation time 21238309 ps
CPU time 0.73 seconds
Started Jul 29 07:01:44 PM PDT 24
Finished Jul 29 07:01:44 PM PDT 24
Peak memory 198228 kb
Host smart-aed0b7cd-08fd-42e4-81f6-028dfa87a254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481945614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.481945614
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1018509544
Short name T695
Test name
Test status
Simulation time 21933213 ps
CPU time 0.6 seconds
Started Jul 29 07:01:44 PM PDT 24
Finished Jul 29 07:01:45 PM PDT 24
Peak memory 195040 kb
Host smart-d580c709-a371-4243-a7ae-01d4fa691938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018509544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1018509544
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2784043423
Short name T715
Test name
Test status
Simulation time 164572507 ps
CPU time 0.87 seconds
Started Jul 29 07:01:44 PM PDT 24
Finished Jul 29 07:01:45 PM PDT 24
Peak memory 198572 kb
Host smart-df29d1e4-e9bc-4a56-ad15-97a8881c9ffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784043423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2784043423
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2430177457
Short name T667
Test name
Test status
Simulation time 87674111 ps
CPU time 1.31 seconds
Started Jul 29 07:01:38 PM PDT 24
Finished Jul 29 07:01:39 PM PDT 24
Peak memory 196368 kb
Host smart-7c38c8d4-9d12-4f79-93f9-b450b385464a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430177457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2430177457
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2553338065
Short name T738
Test name
Test status
Simulation time 297980985 ps
CPU time 1.1 seconds
Started Jul 29 07:01:40 PM PDT 24
Finished Jul 29 07:01:41 PM PDT 24
Peak memory 200624 kb
Host smart-d2f390ab-f95e-4a43-bc57-ae9ca97558d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553338065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.2553338065
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.425582004
Short name T672
Test name
Test status
Simulation time 38198327 ps
CPU time 0.75 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:48 PM PDT 24
Peak memory 195312 kb
Host smart-3739d039-5266-48a3-9330-6f588ac9b297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425582004 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.425582004
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3791329514
Short name T644
Test name
Test status
Simulation time 22495898 ps
CPU time 0.63 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195164 kb
Host smart-bb30a372-be88-457c-b925-6781ce05d83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791329514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3791329514
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2319563264
Short name T683
Test name
Test status
Simulation time 27097741 ps
CPU time 0.6 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195064 kb
Host smart-750c347d-6f6f-4c47-ba0d-5943ca332bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319563264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2319563264
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1716017603
Short name T642
Test name
Test status
Simulation time 98520042 ps
CPU time 0.74 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 195116 kb
Host smart-703be84a-e9cb-425f-b58c-83e680afaaa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716017603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1716017603
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1933169742
Short name T726
Test name
Test status
Simulation time 180400944 ps
CPU time 2.2 seconds
Started Jul 29 07:01:44 PM PDT 24
Finished Jul 29 07:01:47 PM PDT 24
Peak memory 197628 kb
Host smart-05665098-fe34-4763-928d-26a357c46ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933169742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1933169742
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1677499120
Short name T636
Test name
Test status
Simulation time 203851855 ps
CPU time 1.18 seconds
Started Jul 29 07:01:43 PM PDT 24
Finished Jul 29 07:01:45 PM PDT 24
Peak memory 195400 kb
Host smart-afc4de07-751a-4721-87d9-bbe5f4e7d05a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677499120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1677499120
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2857522483
Short name T690
Test name
Test status
Simulation time 46841376 ps
CPU time 1.05 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 195252 kb
Host smart-79508b5d-4202-46c5-b738-6898cb9ad4b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857522483 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.2857522483
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1966571397
Short name T103
Test name
Test status
Simulation time 36337947 ps
CPU time 0.65 seconds
Started Jul 29 07:01:47 PM PDT 24
Finished Jul 29 07:01:48 PM PDT 24
Peak memory 197320 kb
Host smart-2b91e453-c878-43fd-84fb-ab9c2eb12230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966571397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1966571397
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.277907180
Short name T728
Test name
Test status
Simulation time 43039340 ps
CPU time 0.63 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195056 kb
Host smart-70e49cee-936a-4741-bb50-c2b1eab3c507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277907180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.277907180
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2212406787
Short name T698
Test name
Test status
Simulation time 42527150 ps
CPU time 0.82 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 198624 kb
Host smart-80a84e96-ab1b-426c-b048-3636489ef7cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212406787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2212406787
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3753270022
Short name T725
Test name
Test status
Simulation time 164778954 ps
CPU time 2.03 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 196440 kb
Host smart-cd07e285-de2d-4813-ab69-328ccb9ad18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753270022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3753270022
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1553015145
Short name T20
Test name
Test status
Simulation time 246841429 ps
CPU time 1.52 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 200472 kb
Host smart-9a299260-98aa-4b77-a96b-f58642b93062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553015145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1553015145
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2500803343
Short name T21
Test name
Test status
Simulation time 140226394 ps
CPU time 0.84 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195300 kb
Host smart-4cab6379-89e8-41f0-b607-adf84187367d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500803343 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2500803343
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2365527320
Short name T729
Test name
Test status
Simulation time 22191735 ps
CPU time 0.66 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 195132 kb
Host smart-fe7f36c6-f3b6-4643-ba2a-ce51c3958e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365527320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2365527320
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1648436886
Short name T722
Test name
Test status
Simulation time 20612935 ps
CPU time 0.66 seconds
Started Jul 29 07:01:51 PM PDT 24
Finished Jul 29 07:01:52 PM PDT 24
Peak memory 195088 kb
Host smart-a2053218-5cdd-433f-9278-c3c613c27727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648436886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1648436886
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1586465882
Short name T116
Test name
Test status
Simulation time 96756880 ps
CPU time 0.86 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 198480 kb
Host smart-127cdfc7-0bcb-403c-a26a-c766ff6b3c20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586465882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1586465882
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.704635183
Short name T136
Test name
Test status
Simulation time 103766501 ps
CPU time 1.95 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:52 PM PDT 24
Peak memory 197428 kb
Host smart-3fcb6e58-2746-48d3-9d97-6878e5d0a91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704635183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.704635183
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2719062439
Short name T711
Test name
Test status
Simulation time 2188938884 ps
CPU time 1.24 seconds
Started Jul 29 07:01:47 PM PDT 24
Finished Jul 29 07:01:48 PM PDT 24
Peak memory 200612 kb
Host smart-d9469fd9-47bf-4fdc-b04d-1b2ebdd895f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719062439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2719062439
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1734720
Short name T640
Test name
Test status
Simulation time 36678932 ps
CPU time 0.87 seconds
Started Jul 29 07:01:51 PM PDT 24
Finished Jul 29 07:01:52 PM PDT 24
Peak memory 195284 kb
Host smart-84f76b13-5acd-4a75-b03e-8b24857d4b01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734720 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.1734720
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.169115854
Short name T661
Test name
Test status
Simulation time 29714746 ps
CPU time 0.66 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 197276 kb
Host smart-c0f08c74-9ed9-4337-97ed-cd8a47d41c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169115854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.169115854
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3190459381
Short name T647
Test name
Test status
Simulation time 22727865 ps
CPU time 0.63 seconds
Started Jul 29 07:01:48 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195016 kb
Host smart-3b911c3d-1ae1-4117-9f42-2b3bf487762c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190459381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3190459381
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3876695378
Short name T699
Test name
Test status
Simulation time 24296630 ps
CPU time 0.87 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 195164 kb
Host smart-586991e2-0593-4385-b534-2cc66fcf7f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876695378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3876695378
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3967169598
Short name T70
Test name
Test status
Simulation time 492452345 ps
CPU time 2.97 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 197656 kb
Host smart-7e84a4a8-fd6f-4419-8bff-6d66bb17442a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967169598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3967169598
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.4094459922
Short name T731
Test name
Test status
Simulation time 814961977 ps
CPU time 1.1 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 200352 kb
Host smart-2ff8ecd4-9afd-4025-8c57-9b290b3e5516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094459922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.4094459922
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1034882525
Short name T685
Test name
Test status
Simulation time 154244484 ps
CPU time 0.67 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:50 PM PDT 24
Peak memory 195132 kb
Host smart-cb479494-ec17-434e-b399-d366c8298bae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034882525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1034882525
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3026397503
Short name T734
Test name
Test status
Simulation time 18997777 ps
CPU time 0.64 seconds
Started Jul 29 07:01:49 PM PDT 24
Finished Jul 29 07:01:49 PM PDT 24
Peak memory 195092 kb
Host smart-698861c5-ef61-4e7d-beff-12c371897695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026397503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3026397503
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.408901196
Short name T704
Test name
Test status
Simulation time 171058772 ps
CPU time 0.76 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:51 PM PDT 24
Peak memory 197392 kb
Host smart-4a8b854f-27a0-4821-9685-4d3bf41dc459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408901196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.408901196
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4105635949
Short name T60
Test name
Test status
Simulation time 178618198 ps
CPU time 2.83 seconds
Started Jul 29 07:01:50 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 200720 kb
Host smart-779edc0e-5866-4562-b859-ddf4e732d144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105635949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4105635949
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.122807137
Short name T76
Test name
Test status
Simulation time 189262015 ps
CPU time 1.69 seconds
Started Jul 29 07:01:51 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 200460 kb
Host smart-13eb6909-9253-40b1-bfcf-ecb185be9c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122807137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err
.122807137
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3823895831
Short name T58
Test name
Test status
Simulation time 38166525 ps
CPU time 0.9 seconds
Started Jul 29 07:01:52 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 195264 kb
Host smart-ebcb7734-2673-439c-874f-a85cd47a991a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823895831 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3823895831
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.656036702
Short name T109
Test name
Test status
Simulation time 36445665 ps
CPU time 0.68 seconds
Started Jul 29 07:01:53 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 196408 kb
Host smart-cbd490e9-f01d-40aa-8697-1cb792a87723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656036702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.656036702
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.875005967
Short name T701
Test name
Test status
Simulation time 19441377 ps
CPU time 0.64 seconds
Started Jul 29 07:01:53 PM PDT 24
Finished Jul 29 07:01:54 PM PDT 24
Peak memory 195056 kb
Host smart-778be54f-7a7a-4603-a0ee-e42b5df3bc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875005967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.875005967
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2300404493
Short name T114
Test name
Test status
Simulation time 87999937 ps
CPU time 0.76 seconds
Started Jul 29 07:01:52 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 198900 kb
Host smart-15169f15-9c61-4a18-b14d-b992802c37b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300404493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2300404493
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1457719589
Short name T708
Test name
Test status
Simulation time 113407532 ps
CPU time 2.46 seconds
Started Jul 29 07:01:54 PM PDT 24
Finished Jul 29 07:01:57 PM PDT 24
Peak memory 197756 kb
Host smart-1ab809ab-b5bd-4ad7-8b2d-24f5eb2d18c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457719589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1457719589
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.830813096
Short name T656
Test name
Test status
Simulation time 143849912 ps
CPU time 1.04 seconds
Started Jul 29 07:01:52 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 200152 kb
Host smart-415841ea-8243-41d4-9e3e-db259890695e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830813096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.830813096
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3044551370
Short name T637
Test name
Test status
Simulation time 59582193 ps
CPU time 1.12 seconds
Started Jul 29 07:01:59 PM PDT 24
Finished Jul 29 07:02:00 PM PDT 24
Peak memory 200756 kb
Host smart-a13a80c3-d6b2-42d1-abf7-2d3ad5a16b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044551370 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3044551370
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3150189813
Short name T121
Test name
Test status
Simulation time 40720866 ps
CPU time 0.67 seconds
Started Jul 29 07:01:52 PM PDT 24
Finished Jul 29 07:01:53 PM PDT 24
Peak memory 195160 kb
Host smart-81f9e02c-d51c-4115-8936-7638547be2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150189813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3150189813
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4030805944
Short name T665
Test name
Test status
Simulation time 26296273 ps
CPU time 0.6 seconds
Started Jul 29 07:01:54 PM PDT 24
Finished Jul 29 07:01:54 PM PDT 24
Peak memory 195100 kb
Host smart-24583689-fcbd-4f3b-98ef-950698d72a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030805944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4030805944
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.313913282
Short name T679
Test name
Test status
Simulation time 83864081 ps
CPU time 0.85 seconds
Started Jul 29 07:01:58 PM PDT 24
Finished Jul 29 07:01:59 PM PDT 24
Peak memory 198348 kb
Host smart-cf33d50c-8e5b-4d9f-af9e-19f70dc1abb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313913282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sa
me_csr_outstanding.313913282
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3557556430
Short name T71
Test name
Test status
Simulation time 78055268 ps
CPU time 1.71 seconds
Started Jul 29 07:01:55 PM PDT 24
Finished Jul 29 07:01:57 PM PDT 24
Peak memory 196828 kb
Host smart-403e18d3-bdfe-4e6d-bc54-5e9fb1de9335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557556430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3557556430
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2259285217
Short name T110
Test name
Test status
Simulation time 34623411 ps
CPU time 0.81 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 195048 kb
Host smart-9c948068-60c6-4799-b4c2-f66df4cf78c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259285217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
259285217
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3307428401
Short name T135
Test name
Test status
Simulation time 474845158 ps
CPU time 2.04 seconds
Started Jul 29 07:01:10 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 195232 kb
Host smart-55c11ae2-486c-4a72-b675-7b855d15259a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307428401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
307428401
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3267472297
Short name T720
Test name
Test status
Simulation time 25820332 ps
CPU time 0.67 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 198288 kb
Host smart-45de6b30-2bb7-4da6-b49f-1c0c799b0dc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267472297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
267472297
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3866292592
Short name T92
Test name
Test status
Simulation time 39492984 ps
CPU time 0.73 seconds
Started Jul 29 07:01:06 PM PDT 24
Finished Jul 29 07:01:07 PM PDT 24
Peak memory 195296 kb
Host smart-a1ca1f9f-b359-4662-ab03-ec1f54d46252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866292592 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.3866292592
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2046669711
Short name T668
Test name
Test status
Simulation time 20196643 ps
CPU time 0.62 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 195172 kb
Host smart-37972740-4017-48dc-83a0-bdf3b85fc268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046669711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2046669711
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.976616338
Short name T73
Test name
Test status
Simulation time 25077490 ps
CPU time 0.61 seconds
Started Jul 29 07:01:10 PM PDT 24
Finished Jul 29 07:01:11 PM PDT 24
Peak memory 194972 kb
Host smart-20f22549-f4b7-4b78-a658-ad5c0ff8ff9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976616338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.976616338
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3596639228
Short name T645
Test name
Test status
Simulation time 20091292 ps
CPU time 0.76 seconds
Started Jul 29 07:01:10 PM PDT 24
Finished Jul 29 07:01:11 PM PDT 24
Peak memory 197380 kb
Host smart-802c1307-d515-414c-8822-26159f8d255c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596639228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3596639228
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3937446663
Short name T75
Test name
Test status
Simulation time 199529161 ps
CPU time 1.41 seconds
Started Jul 29 07:01:09 PM PDT 24
Finished Jul 29 07:01:11 PM PDT 24
Peak memory 196424 kb
Host smart-e4a90f70-9584-4d55-889b-4a6a5d01edac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937446663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3937446663
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2005078006
Short name T658
Test name
Test status
Simulation time 135756592 ps
CPU time 1.1 seconds
Started Jul 29 07:01:09 PM PDT 24
Finished Jul 29 07:01:10 PM PDT 24
Peak memory 200268 kb
Host smart-5eb4b2cd-7d31-478d-88bf-7fac106249cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005078006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.2005078006
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1042627720
Short name T743
Test name
Test status
Simulation time 48508846 ps
CPU time 0.67 seconds
Started Jul 29 07:02:03 PM PDT 24
Finished Jul 29 07:02:04 PM PDT 24
Peak memory 195068 kb
Host smart-71ea5edb-c3cf-4d9a-b904-d18626cd9fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042627720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1042627720
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3920973281
Short name T692
Test name
Test status
Simulation time 34884821 ps
CPU time 0.57 seconds
Started Jul 29 07:02:00 PM PDT 24
Finished Jul 29 07:02:01 PM PDT 24
Peak memory 195012 kb
Host smart-09f8b8e7-b559-486b-bd97-b1d5a399cf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920973281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3920973281
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4053721805
Short name T706
Test name
Test status
Simulation time 19172383 ps
CPU time 0.61 seconds
Started Jul 29 07:01:58 PM PDT 24
Finished Jul 29 07:01:59 PM PDT 24
Peak memory 195092 kb
Host smart-8fcd465a-dc8f-47bb-946e-e6784c5c523a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053721805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.4053721805
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1174796662
Short name T169
Test name
Test status
Simulation time 18465534 ps
CPU time 0.64 seconds
Started Jul 29 07:02:03 PM PDT 24
Finished Jul 29 07:02:04 PM PDT 24
Peak memory 195064 kb
Host smart-5064f9e1-058a-46b2-82da-33a09738bb91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174796662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1174796662
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1375838731
Short name T703
Test name
Test status
Simulation time 43492087 ps
CPU time 0.64 seconds
Started Jul 29 07:02:03 PM PDT 24
Finished Jul 29 07:02:04 PM PDT 24
Peak memory 195064 kb
Host smart-63233af1-76d4-409d-b0eb-7fbf58a9b25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375838731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1375838731
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1971683573
Short name T648
Test name
Test status
Simulation time 21758482 ps
CPU time 0.63 seconds
Started Jul 29 07:01:59 PM PDT 24
Finished Jul 29 07:02:00 PM PDT 24
Peak memory 195104 kb
Host smart-d70d87b3-d984-4697-bece-c7e49335521d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971683573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1971683573
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3899632217
Short name T688
Test name
Test status
Simulation time 31106523 ps
CPU time 0.61 seconds
Started Jul 29 07:02:00 PM PDT 24
Finished Jul 29 07:02:00 PM PDT 24
Peak memory 195092 kb
Host smart-b98e95b5-fcaa-466c-af31-a612baecb23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899632217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3899632217
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.164869876
Short name T633
Test name
Test status
Simulation time 53251533 ps
CPU time 0.63 seconds
Started Jul 29 07:02:00 PM PDT 24
Finished Jul 29 07:02:01 PM PDT 24
Peak memory 195092 kb
Host smart-aa6ecbd9-5686-4a16-a40e-233fff8a43a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164869876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.164869876
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3701178822
Short name T663
Test name
Test status
Simulation time 22334346 ps
CPU time 0.64 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 195060 kb
Host smart-4afd1e23-67a9-476e-ac3e-3d0dbebb4938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701178822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3701178822
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.371197046
Short name T112
Test name
Test status
Simulation time 25752326 ps
CPU time 0.91 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 195104 kb
Host smart-fc525c05-fbe8-43c0-84fd-929b0c757ff0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371197046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.371197046
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.734607909
Short name T710
Test name
Test status
Simulation time 101531753 ps
CPU time 0.68 seconds
Started Jul 29 07:01:13 PM PDT 24
Finished Jul 29 07:01:14 PM PDT 24
Peak memory 197688 kb
Host smart-b62e2388-3fe1-4b4c-9345-f5ea36150e9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734607909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.734607909
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2956660945
Short name T674
Test name
Test status
Simulation time 51419684 ps
CPU time 1.41 seconds
Started Jul 29 07:01:17 PM PDT 24
Finished Jul 29 07:01:19 PM PDT 24
Peak memory 197400 kb
Host smart-422d6688-f6e6-4748-a76f-7d5e4a55eac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956660945 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2956660945
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1650338958
Short name T712
Test name
Test status
Simulation time 47328891 ps
CPU time 0.6 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:12 PM PDT 24
Peak memory 195156 kb
Host smart-47279925-8e45-4944-9762-545232219ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650338958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1650338958
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1144395900
Short name T694
Test name
Test status
Simulation time 22653969 ps
CPU time 0.6 seconds
Started Jul 29 07:01:12 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 195204 kb
Host smart-82eba8c0-e760-4eae-b02b-d4f22511a744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144395900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1144395900
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.12637229
Short name T744
Test name
Test status
Simulation time 79053130 ps
CPU time 0.73 seconds
Started Jul 29 07:01:12 PM PDT 24
Finished Jul 29 07:01:13 PM PDT 24
Peak memory 197400 kb
Host smart-35eb1fb1-0005-45c8-9505-560f8d071ddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12637229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same
_csr_outstanding.12637229
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.198477582
Short name T702
Test name
Test status
Simulation time 120024253 ps
CPU time 2.42 seconds
Started Jul 29 07:01:11 PM PDT 24
Finished Jul 29 07:01:14 PM PDT 24
Peak memory 196452 kb
Host smart-5cf4e4f5-331b-4dc6-8d93-8b898be1cbbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198477582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.198477582
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.451915382
Short name T79
Test name
Test status
Simulation time 203248580 ps
CPU time 1.68 seconds
Started Jul 29 07:01:12 PM PDT 24
Finished Jul 29 07:01:14 PM PDT 24
Peak memory 195416 kb
Host smart-5a10f275-f4f8-4d47-884d-0e7442c2b219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451915382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.
451915382
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2036569275
Short name T673
Test name
Test status
Simulation time 46578808 ps
CPU time 0.62 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 195092 kb
Host smart-e38eb383-4e12-41b9-8648-fe3e37d69010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036569275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.2036569275
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2285655592
Short name T651
Test name
Test status
Simulation time 44172156 ps
CPU time 0.59 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 195104 kb
Host smart-ac94e70f-5694-4417-a03b-503b4af47326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285655592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2285655592
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2152107313
Short name T693
Test name
Test status
Simulation time 16955865 ps
CPU time 0.6 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 195104 kb
Host smart-63e229d0-a5b1-4958-a8c6-4b2ca8115e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152107313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2152107313
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.606988597
Short name T714
Test name
Test status
Simulation time 21125123 ps
CPU time 0.62 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 195076 kb
Host smart-eb30fe40-e207-4202-a136-755226c417e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606988597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.606988597
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2254009947
Short name T74
Test name
Test status
Simulation time 30212635 ps
CPU time 0.63 seconds
Started Jul 29 07:02:06 PM PDT 24
Finished Jul 29 07:02:07 PM PDT 24
Peak memory 195020 kb
Host smart-ab4b3a06-f82d-4f49-9663-873863a8bd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254009947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2254009947
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.45164372
Short name T168
Test name
Test status
Simulation time 31273556 ps
CPU time 0.6 seconds
Started Jul 29 07:02:06 PM PDT 24
Finished Jul 29 07:02:07 PM PDT 24
Peak memory 195056 kb
Host smart-1e1e3e48-a9eb-4baf-b44c-33160da5af61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45164372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.45164372
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3085970663
Short name T646
Test name
Test status
Simulation time 46405883 ps
CPU time 0.63 seconds
Started Jul 29 07:02:06 PM PDT 24
Finished Jul 29 07:02:07 PM PDT 24
Peak memory 194976 kb
Host smart-f743a4a8-3b54-4d75-a36d-5ba5a390fe65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085970663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3085970663
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2224698168
Short name T713
Test name
Test status
Simulation time 48521541 ps
CPU time 0.62 seconds
Started Jul 29 07:02:05 PM PDT 24
Finished Jul 29 07:02:06 PM PDT 24
Peak memory 195084 kb
Host smart-810d6eaa-baba-4fc5-9cc3-14f0f71d56a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224698168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2224698168
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1279310076
Short name T655
Test name
Test status
Simulation time 41238448 ps
CPU time 0.6 seconds
Started Jul 29 07:02:08 PM PDT 24
Finished Jul 29 07:02:09 PM PDT 24
Peak memory 195104 kb
Host smart-6f36b48d-f20a-459d-82b4-f6c068a69611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279310076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1279310076
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1772640206
Short name T696
Test name
Test status
Simulation time 23630848 ps
CPU time 0.63 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 194988 kb
Host smart-f8061b9f-d97a-45e9-9722-8d2ba6f9b8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772640206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1772640206
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1435980911
Short name T664
Test name
Test status
Simulation time 39976848 ps
CPU time 0.97 seconds
Started Jul 29 07:01:19 PM PDT 24
Finished Jul 29 07:01:20 PM PDT 24
Peak memory 195076 kb
Host smart-6536c07a-0245-4437-91ac-f4b6f54d6df8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435980911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
435980911
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2438555769
Short name T653
Test name
Test status
Simulation time 416942182 ps
CPU time 3.3 seconds
Started Jul 29 07:01:19 PM PDT 24
Finished Jul 29 07:01:22 PM PDT 24
Peak memory 195280 kb
Host smart-5eba0272-54c7-4202-8d49-8e49c16834da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438555769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2
438555769
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3111164275
Short name T106
Test name
Test status
Simulation time 43219563 ps
CPU time 0.66 seconds
Started Jul 29 07:01:17 PM PDT 24
Finished Jul 29 07:01:17 PM PDT 24
Peak memory 195160 kb
Host smart-14dd154c-c5c3-40c6-802e-6df2ac0ac8b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111164275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
111164275
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1955753567
Short name T650
Test name
Test status
Simulation time 44777300 ps
CPU time 0.93 seconds
Started Jul 29 07:01:18 PM PDT 24
Finished Jul 29 07:01:19 PM PDT 24
Peak memory 195464 kb
Host smart-fd14232a-1c4a-45ba-8871-f118c6441d65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955753567 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1955753567
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1904583135
Short name T678
Test name
Test status
Simulation time 52908390 ps
CPU time 0.59 seconds
Started Jul 29 07:01:17 PM PDT 24
Finished Jul 29 07:01:18 PM PDT 24
Peak memory 197304 kb
Host smart-4c5a3591-e0dd-407f-8169-90d45d7e1934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904583135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1904583135
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4208167962
Short name T716
Test name
Test status
Simulation time 25573466 ps
CPU time 0.6 seconds
Started Jul 29 07:01:16 PM PDT 24
Finished Jul 29 07:01:17 PM PDT 24
Peak memory 195092 kb
Host smart-ba94e92d-3a55-441c-b427-40789c328829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208167962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.4208167962
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2432638841
Short name T733
Test name
Test status
Simulation time 21422178 ps
CPU time 0.8 seconds
Started Jul 29 07:01:23 PM PDT 24
Finished Jul 29 07:01:23 PM PDT 24
Peak memory 195132 kb
Host smart-c7f04048-52dc-4088-b9e7-95e3bd056dd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432638841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.2432638841
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3047254096
Short name T662
Test name
Test status
Simulation time 169741167 ps
CPU time 2.21 seconds
Started Jul 29 07:01:23 PM PDT 24
Finished Jul 29 07:01:25 PM PDT 24
Peak memory 196484 kb
Host smart-942d8301-62e3-4ac0-bbea-d818e8d449bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047254096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3047254096
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1831388742
Short name T639
Test name
Test status
Simulation time 93712682 ps
CPU time 1.12 seconds
Started Jul 29 07:01:17 PM PDT 24
Finished Jul 29 07:01:18 PM PDT 24
Peak memory 200500 kb
Host smart-0d62dc05-43e3-482c-a6c1-a0ffba040594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831388742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1831388742
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3944322724
Short name T723
Test name
Test status
Simulation time 51667555 ps
CPU time 0.61 seconds
Started Jul 29 07:02:07 PM PDT 24
Finished Jul 29 07:02:08 PM PDT 24
Peak memory 194972 kb
Host smart-78588f03-e827-474c-a243-668935e39710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944322724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3944322724
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3111855096
Short name T173
Test name
Test status
Simulation time 25635043 ps
CPU time 0.61 seconds
Started Jul 29 07:02:06 PM PDT 24
Finished Jul 29 07:02:06 PM PDT 24
Peak memory 195076 kb
Host smart-0caffe86-4dba-4b7f-b5e8-1ec96fcd7fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111855096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3111855096
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.485595429
Short name T72
Test name
Test status
Simulation time 16973815 ps
CPU time 0.61 seconds
Started Jul 29 07:02:05 PM PDT 24
Finished Jul 29 07:02:06 PM PDT 24
Peak memory 195036 kb
Host smart-627d1def-dc65-41cf-96ef-d79039e0b265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485595429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.485595429
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3969724248
Short name T719
Test name
Test status
Simulation time 57660405 ps
CPU time 0.63 seconds
Started Jul 29 07:02:06 PM PDT 24
Finished Jul 29 07:02:07 PM PDT 24
Peak memory 195240 kb
Host smart-81092ea0-7fa5-4a81-8aa8-45ae40dd9929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969724248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.3969724248
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3971236763
Short name T717
Test name
Test status
Simulation time 18376129 ps
CPU time 0.6 seconds
Started Jul 29 07:02:04 PM PDT 24
Finished Jul 29 07:02:05 PM PDT 24
Peak memory 195040 kb
Host smart-60b751a9-d593-4577-808e-f0028fe9be0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971236763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3971236763
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3533427700
Short name T721
Test name
Test status
Simulation time 47771640 ps
CPU time 0.59 seconds
Started Jul 29 07:02:08 PM PDT 24
Finished Jul 29 07:02:09 PM PDT 24
Peak memory 195000 kb
Host smart-b6159927-3137-4c8d-93d4-ab3e5b548f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533427700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3533427700
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.116715985
Short name T707
Test name
Test status
Simulation time 15709313 ps
CPU time 0.61 seconds
Started Jul 29 07:02:10 PM PDT 24
Finished Jul 29 07:02:11 PM PDT 24
Peak memory 195016 kb
Host smart-54ef8fee-fa49-452a-aaf9-00c5a4c3f94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116715985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.116715985
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.419199069
Short name T171
Test name
Test status
Simulation time 17825086 ps
CPU time 0.58 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:13 PM PDT 24
Peak memory 195068 kb
Host smart-16f23f27-8887-47bf-8306-533fd9060eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419199069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.419199069
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.305931915
Short name T687
Test name
Test status
Simulation time 147524592 ps
CPU time 0.58 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:14 PM PDT 24
Peak memory 195092 kb
Host smart-a6b53371-5754-40c1-98f9-c03d76d38742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305931915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.305931915
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1966106733
Short name T676
Test name
Test status
Simulation time 22689818 ps
CPU time 0.59 seconds
Started Jul 29 07:02:11 PM PDT 24
Finished Jul 29 07:02:11 PM PDT 24
Peak memory 195104 kb
Host smart-7278aad1-7c97-46a6-9e93-2f733dc1107c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966106733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1966106733
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1986599567
Short name T705
Test name
Test status
Simulation time 55338322 ps
CPU time 0.81 seconds
Started Jul 29 07:01:34 PM PDT 24
Finished Jul 29 07:01:35 PM PDT 24
Peak memory 195272 kb
Host smart-2def3164-bcf5-4eb1-9de6-9815a96b9cc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986599567 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1986599567
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3596026228
Short name T104
Test name
Test status
Simulation time 20409279 ps
CPU time 0.66 seconds
Started Jul 29 07:01:26 PM PDT 24
Finished Jul 29 07:01:26 PM PDT 24
Peak memory 197316 kb
Host smart-4a3a9f78-30bc-4dad-bf1d-7967e300d2a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596026228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3596026228
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.829490824
Short name T718
Test name
Test status
Simulation time 16839486 ps
CPU time 0.59 seconds
Started Jul 29 07:01:23 PM PDT 24
Finished Jul 29 07:01:24 PM PDT 24
Peak memory 195072 kb
Host smart-0397b706-fc74-4682-8d86-5116c9859e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829490824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.829490824
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.3315720681
Short name T118
Test name
Test status
Simulation time 43785012 ps
CPU time 0.9 seconds
Started Jul 29 07:01:21 PM PDT 24
Finished Jul 29 07:01:22 PM PDT 24
Peak memory 198820 kb
Host smart-c21140cb-10a4-432b-8549-29382cbf0936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315720681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.3315720681
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1687540868
Short name T680
Test name
Test status
Simulation time 252618019 ps
CPU time 1.86 seconds
Started Jul 29 07:01:15 PM PDT 24
Finished Jul 29 07:01:17 PM PDT 24
Peak memory 196388 kb
Host smart-2cd088ea-f80f-41a5-ab7e-ef1b11b6afce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687540868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1687540868
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3243797193
Short name T677
Test name
Test status
Simulation time 212595308 ps
CPU time 1.09 seconds
Started Jul 29 07:01:31 PM PDT 24
Finished Jul 29 07:01:32 PM PDT 24
Peak memory 200492 kb
Host smart-15923cf8-5efe-45d1-ab06-204f9d8fb02a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243797193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3243797193
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1688652415
Short name T689
Test name
Test status
Simulation time 44217241 ps
CPU time 0.71 seconds
Started Jul 29 07:01:39 PM PDT 24
Finished Jul 29 07:01:39 PM PDT 24
Peak memory 195328 kb
Host smart-d1951caf-582a-4ad1-ac8f-664aa0f7c5c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688652415 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1688652415
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3290725143
Short name T682
Test name
Test status
Simulation time 19898626 ps
CPU time 0.65 seconds
Started Jul 29 07:01:27 PM PDT 24
Finished Jul 29 07:01:28 PM PDT 24
Peak memory 195072 kb
Host smart-527e4128-898f-47d4-9bde-9c32f1e37d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290725143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3290725143
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.4279496863
Short name T638
Test name
Test status
Simulation time 28284197 ps
CPU time 0.59 seconds
Started Jul 29 07:01:37 PM PDT 24
Finished Jul 29 07:01:37 PM PDT 24
Peak memory 195060 kb
Host smart-1a7f3811-6d13-4fc5-847c-cf5f34c5f340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279496863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.4279496863
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1379579686
Short name T115
Test name
Test status
Simulation time 25324381 ps
CPU time 0.75 seconds
Started Jul 29 07:01:26 PM PDT 24
Finished Jul 29 07:01:27 PM PDT 24
Peak memory 195124 kb
Host smart-c81a4c13-72d3-4590-b263-b75c5bb8c04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379579686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1379579686
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2407708554
Short name T78
Test name
Test status
Simulation time 245450468 ps
CPU time 2.19 seconds
Started Jul 29 07:01:22 PM PDT 24
Finished Jul 29 07:01:24 PM PDT 24
Peak memory 197452 kb
Host smart-b4a956b0-dd70-41b1-adb1-3854c414ebe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407708554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2407708554
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1749151079
Short name T156
Test name
Test status
Simulation time 224045810 ps
CPU time 1.53 seconds
Started Jul 29 07:01:22 PM PDT 24
Finished Jul 29 07:01:24 PM PDT 24
Peak memory 200508 kb
Host smart-0b02360b-6c92-4d9f-b012-992460e0c9c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749151079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1749151079
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2922332088
Short name T681
Test name
Test status
Simulation time 50720336 ps
CPU time 0.88 seconds
Started Jul 29 07:01:27 PM PDT 24
Finished Jul 29 07:01:28 PM PDT 24
Peak memory 195300 kb
Host smart-3d2a0196-0c07-4c8f-a169-85864fd15acf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922332088 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2922332088
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1681681676
Short name T697
Test name
Test status
Simulation time 26479544 ps
CPU time 0.62 seconds
Started Jul 29 07:01:29 PM PDT 24
Finished Jul 29 07:01:29 PM PDT 24
Peak memory 195060 kb
Host smart-606137a5-0936-4ecb-a1b9-f3a748837bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681681676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1681681676
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.764140655
Short name T172
Test name
Test status
Simulation time 18866419 ps
CPU time 0.63 seconds
Started Jul 29 07:01:38 PM PDT 24
Finished Jul 29 07:01:38 PM PDT 24
Peak memory 195064 kb
Host smart-82782f63-1790-4e2e-83bb-95efbbc807ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764140655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.764140655
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1850392908
Short name T686
Test name
Test status
Simulation time 19783836 ps
CPU time 0.71 seconds
Started Jul 29 07:01:38 PM PDT 24
Finished Jul 29 07:01:38 PM PDT 24
Peak memory 197404 kb
Host smart-7662c30d-d47b-4dd6-9430-588d5f157897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850392908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1850392908
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3462029731
Short name T675
Test name
Test status
Simulation time 182610238 ps
CPU time 2.12 seconds
Started Jul 29 07:01:27 PM PDT 24
Finished Jul 29 07:01:29 PM PDT 24
Peak memory 196432 kb
Host smart-46f001ca-371a-4184-8bcd-11c0fddc24c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462029731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3462029731
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.523636910
Short name T691
Test name
Test status
Simulation time 40717346 ps
CPU time 0.9 seconds
Started Jul 29 07:01:28 PM PDT 24
Finished Jul 29 07:01:29 PM PDT 24
Peak memory 195172 kb
Host smart-e7c48fef-143b-480f-8a11-d1f89aef3064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523636910 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.523636910
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2986391494
Short name T741
Test name
Test status
Simulation time 69235902 ps
CPU time 0.66 seconds
Started Jul 29 07:01:27 PM PDT 24
Finished Jul 29 07:01:28 PM PDT 24
Peak memory 197300 kb
Host smart-c5716843-f740-49ec-9152-14c05300fd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986391494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2986391494
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2495457971
Short name T669
Test name
Test status
Simulation time 20578924 ps
CPU time 0.64 seconds
Started Jul 29 07:01:29 PM PDT 24
Finished Jul 29 07:01:30 PM PDT 24
Peak memory 195100 kb
Host smart-e7b00369-e918-41db-a969-909d9606bc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495457971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2495457971
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.515206604
Short name T735
Test name
Test status
Simulation time 33305098 ps
CPU time 0.73 seconds
Started Jul 29 07:01:26 PM PDT 24
Finished Jul 29 07:01:27 PM PDT 24
Peak memory 197424 kb
Host smart-43d3342b-a6a8-4d0b-944e-8564c785bd75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515206604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.515206604
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2208227146
Short name T138
Test name
Test status
Simulation time 294210686 ps
CPU time 1.45 seconds
Started Jul 29 07:01:29 PM PDT 24
Finished Jul 29 07:01:31 PM PDT 24
Peak memory 195456 kb
Host smart-3550d6ec-fc74-4652-816a-2e16bc9a836d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208227146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2208227146
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2466570422
Short name T660
Test name
Test status
Simulation time 294625089 ps
CPU time 1.83 seconds
Started Jul 29 07:01:28 PM PDT 24
Finished Jul 29 07:01:30 PM PDT 24
Peak memory 200668 kb
Host smart-9f41f9d2-49f2-4e3d-869b-3bf0a3fd96aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466570422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2466570422
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1615790531
Short name T745
Test name
Test status
Simulation time 83626731 ps
CPU time 0.8 seconds
Started Jul 29 07:01:32 PM PDT 24
Finished Jul 29 07:01:32 PM PDT 24
Peak memory 195240 kb
Host smart-9b9ddbcf-1290-4084-9549-abb28916a3a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615790531 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1615790531
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.3701364853
Short name T727
Test name
Test status
Simulation time 22292686 ps
CPU time 0.69 seconds
Started Jul 29 07:01:31 PM PDT 24
Finished Jul 29 07:01:32 PM PDT 24
Peak memory 197296 kb
Host smart-8bfc91d6-580f-4998-acdd-12db4fa6424f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701364853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.3701364853
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1894873630
Short name T666
Test name
Test status
Simulation time 19483724 ps
CPU time 0.62 seconds
Started Jul 29 07:01:27 PM PDT 24
Finished Jul 29 07:01:28 PM PDT 24
Peak memory 195104 kb
Host smart-385f9146-3ebf-4dba-9179-e222c6b2decf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894873630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1894873630
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3170710776
Short name T700
Test name
Test status
Simulation time 66917319 ps
CPU time 0.87 seconds
Started Jul 29 07:01:33 PM PDT 24
Finished Jul 29 07:01:34 PM PDT 24
Peak memory 198416 kb
Host smart-8874e51d-d38e-4204-97f0-39ecd31efd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170710776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.3170710776
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.4243219614
Short name T684
Test name
Test status
Simulation time 189999343 ps
CPU time 2.35 seconds
Started Jul 29 07:01:37 PM PDT 24
Finished Jul 29 07:01:40 PM PDT 24
Peak memory 197472 kb
Host smart-84b9bf2d-343d-47ff-8b48-c12ba39b46bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243219614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.4243219614
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.791718902
Short name T80
Test name
Test status
Simulation time 107578732 ps
CPU time 1.19 seconds
Started Jul 29 07:01:29 PM PDT 24
Finished Jul 29 07:01:30 PM PDT 24
Peak memory 195316 kb
Host smart-c6e533f2-8fd6-49c3-8426-0898e30cf802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791718902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
791718902
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3436719155
Short name T56
Test name
Test status
Simulation time 112970464 ps
CPU time 0.81 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 200204 kb
Host smart-cd09515e-c5c4-4e09-9ac9-d507329c8956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436719155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3436719155
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.745679474
Short name T467
Test name
Test status
Simulation time 50663703 ps
CPU time 0.77 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 199172 kb
Host smart-30b3c20c-6822-4f11-ae15-c65ef52f54cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745679474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.745679474
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.435564693
Short name T230
Test name
Test status
Simulation time 30588303 ps
CPU time 0.64 seconds
Started Jul 29 07:06:33 PM PDT 24
Finished Jul 29 07:06:34 PM PDT 24
Peak memory 198028 kb
Host smart-a0fbc247-0f9e-460b-9033-8a8abf0878d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435564693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_m
alfunc.435564693
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.4047270617
Short name T238
Test name
Test status
Simulation time 422812434 ps
CPU time 1.01 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 198168 kb
Host smart-d780105b-09ef-457d-b209-a0dcc200c282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047270617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.4047270617
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3422868481
Short name T623
Test name
Test status
Simulation time 34193789 ps
CPU time 0.68 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 198408 kb
Host smart-c48a7e32-294c-48f8-91fb-686ddd9ce982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422868481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3422868481
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.4118435401
Short name T541
Test name
Test status
Simulation time 145996743 ps
CPU time 0.75 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 198276 kb
Host smart-e2d928ce-6835-431b-b8f8-492b6a5ec30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118435401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.4118435401
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3368493052
Short name T225
Test name
Test status
Simulation time 321007059 ps
CPU time 0.75 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 209484 kb
Host smart-3ca96647-efb1-415c-bab6-a3398638f582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368493052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3368493052
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3639156016
Short name T65
Test name
Test status
Simulation time 29566465 ps
CPU time 0.68 seconds
Started Jul 29 07:06:32 PM PDT 24
Finished Jul 29 07:06:33 PM PDT 24
Peak memory 199160 kb
Host smart-f2f0b63c-4d2a-4721-bdb5-8290293b1623
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639156016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.3639156016
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.682290855
Short name T448
Test name
Test status
Simulation time 72128051 ps
CPU time 0.89 seconds
Started Jul 29 07:06:33 PM PDT 24
Finished Jul 29 07:06:34 PM PDT 24
Peak memory 199396 kb
Host smart-ecd2b235-061e-482f-bf9f-67815a33a353
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682290855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.682290855
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.1258628574
Short name T572
Test name
Test status
Simulation time 36207586 ps
CPU time 0.65 seconds
Started Jul 29 07:06:33 PM PDT 24
Finished Jul 29 07:06:34 PM PDT 24
Peak memory 198536 kb
Host smart-dc3c0d4f-80e9-4e76-b3d3-eb004a3971dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258628574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1258628574
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.2107180232
Short name T99
Test name
Test status
Simulation time 48549359 ps
CPU time 0.68 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 199212 kb
Host smart-4d233e7b-72f6-4701-b12e-583784a33bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107180232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.2107180232
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.611415235
Short name T174
Test name
Test status
Simulation time 104718948 ps
CPU time 0.65 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 198504 kb
Host smart-d05d34fc-2ad7-4e18-8d9a-8e114c5676ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611415235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disab
le_rom_integrity_check.611415235
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.38576767
Short name T361
Test name
Test status
Simulation time 38746999 ps
CPU time 0.6 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 197336 kb
Host smart-bed1577d-961a-45fa-98fb-bf5f0c7b4f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_ma
lfunc.38576767
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2262884640
Short name T240
Test name
Test status
Simulation time 166659595 ps
CPU time 0.97 seconds
Started Jul 29 07:06:45 PM PDT 24
Finished Jul 29 07:06:46 PM PDT 24
Peak memory 198072 kb
Host smart-28aa7647-e0c2-4f22-89a8-368b5598c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262884640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2262884640
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.330275743
Short name T259
Test name
Test status
Simulation time 138108229 ps
CPU time 0.61 seconds
Started Jul 29 07:06:39 PM PDT 24
Finished Jul 29 07:06:40 PM PDT 24
Peak memory 198028 kb
Host smart-2be977f5-e833-4ecd-abce-a2fba1b0879f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330275743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.330275743
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1112085544
Short name T278
Test name
Test status
Simulation time 86911717 ps
CPU time 0.61 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 198116 kb
Host smart-f4708dff-e94c-4a89-8de4-4af86e32f7be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112085544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1112085544
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3346730932
Short name T368
Test name
Test status
Simulation time 174157603 ps
CPU time 0.69 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 201408 kb
Host smart-85a1baf9-d057-48b2-aa06-03cd08a7f1f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346730932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3346730932
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.971289681
Short name T153
Test name
Test status
Simulation time 37684911 ps
CPU time 0.64 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 198544 kb
Host smart-92bbc661-c5d0-4e0c-89a4-229193013675
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971289681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wak
eup_race.971289681
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2232744162
Short name T348
Test name
Test status
Simulation time 286217943 ps
CPU time 0.71 seconds
Started Jul 29 07:06:45 PM PDT 24
Finished Jul 29 07:06:46 PM PDT 24
Peak memory 198316 kb
Host smart-6658110f-0245-4ae5-af71-ab7811b73cb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232744162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2232744162
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.3723176447
Short name T500
Test name
Test status
Simulation time 118268913 ps
CPU time 0.89 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 209388 kb
Host smart-2f5d5fca-40f4-4e37-b803-7fd7a017fe6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723176447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.3723176447
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.443176644
Short name T19
Test name
Test status
Simulation time 380406280 ps
CPU time 1.22 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 216960 kb
Host smart-4fe8a586-4ee2-4b88-a44e-6e3f385df97b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443176644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.443176644
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2732960629
Short name T49
Test name
Test status
Simulation time 67862301 ps
CPU time 0.67 seconds
Started Jul 29 07:06:39 PM PDT 24
Finished Jul 29 07:06:40 PM PDT 24
Peak memory 198624 kb
Host smart-f25cff73-c3c2-4448-942d-32def9dfca41
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732960629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.2732960629
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2409530958
Short name T431
Test name
Test status
Simulation time 62482692 ps
CPU time 0.86 seconds
Started Jul 29 07:06:40 PM PDT 24
Finished Jul 29 07:06:41 PM PDT 24
Peak memory 198112 kb
Host smart-9e62050c-d1a7-4a5b-84d9-8b15211a1656
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409530958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2409530958
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1174196290
Short name T420
Test name
Test status
Simulation time 81317225 ps
CPU time 0.87 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 200088 kb
Host smart-d0dc571c-410b-471a-8769-8d822de952b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174196290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1174196290
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3894667500
Short name T486
Test name
Test status
Simulation time 65667691 ps
CPU time 0.81 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 199112 kb
Host smart-fb960386-13ab-4380-a151-9479c73c1c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894667500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.3894667500
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2542337283
Short name T313
Test name
Test status
Simulation time 28435153 ps
CPU time 0.63 seconds
Started Jul 29 07:07:13 PM PDT 24
Finished Jul 29 07:07:14 PM PDT 24
Peak memory 198076 kb
Host smart-cc2a09c9-d1e9-4226-bfd7-541a38caa457
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542337283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2542337283
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.2788600133
Short name T536
Test name
Test status
Simulation time 169978017 ps
CPU time 0.96 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 198408 kb
Host smart-9814c845-0cb3-47d6-878d-adf1d33524eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788600133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2788600133
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.992936904
Short name T337
Test name
Test status
Simulation time 40593467 ps
CPU time 0.59 seconds
Started Jul 29 07:07:10 PM PDT 24
Finished Jul 29 07:07:11 PM PDT 24
Peak memory 198120 kb
Host smart-76c03dec-7c9b-46fa-9bf7-9eb7cbebbaa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992936904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.992936904
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2213681787
Short name T524
Test name
Test status
Simulation time 56307950 ps
CPU time 0.64 seconds
Started Jul 29 07:07:12 PM PDT 24
Finished Jul 29 07:07:13 PM PDT 24
Peak memory 198116 kb
Host smart-1b9b990a-5069-47b7-9044-86438366e2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213681787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2213681787
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1505206146
Short name T495
Test name
Test status
Simulation time 57105512 ps
CPU time 0.69 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 201360 kb
Host smart-1b3594e7-c3d0-4325-84b7-9c996d82f05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505206146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1505206146
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.753801655
Short name T307
Test name
Test status
Simulation time 88523794 ps
CPU time 0.71 seconds
Started Jul 29 07:07:12 PM PDT 24
Finished Jul 29 07:07:13 PM PDT 24
Peak memory 199304 kb
Host smart-74dd7053-312b-4872-b45e-3c46b6c9c753
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753801655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.753801655
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1799481177
Short name T396
Test name
Test status
Simulation time 163220555 ps
CPU time 0.75 seconds
Started Jul 29 07:07:11 PM PDT 24
Finished Jul 29 07:07:12 PM PDT 24
Peak memory 201328 kb
Host smart-cb91d9d2-e1aa-4c83-93e8-8f5ca8f1ac94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799481177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1799481177
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3035006207
Short name T362
Test name
Test status
Simulation time 61372489 ps
CPU time 0.86 seconds
Started Jul 29 07:07:12 PM PDT 24
Finished Jul 29 07:07:12 PM PDT 24
Peak memory 199408 kb
Host smart-760f1ffe-060f-43f4-beb0-08271b743c7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035006207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3035006207
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1816428786
Short name T532
Test name
Test status
Simulation time 52930267 ps
CPU time 0.64 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 199432 kb
Host smart-2fd303be-a915-4a85-bd14-08b56c9ce23e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816428786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1816428786
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.892524891
Short name T311
Test name
Test status
Simulation time 53174641 ps
CPU time 0.69 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 199136 kb
Host smart-0e087edd-d487-4c4d-b6a7-6f624aedceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892524891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.892524891
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.553697929
Short name T23
Test name
Test status
Simulation time 178571737 ps
CPU time 0.67 seconds
Started Jul 29 07:07:11 PM PDT 24
Finished Jul 29 07:07:11 PM PDT 24
Peak memory 198368 kb
Host smart-1482d175-2c23-4189-9707-924342a354fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553697929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.553697929
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.4167021803
Short name T424
Test name
Test status
Simulation time 29805584 ps
CPU time 0.64 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 197348 kb
Host smart-5e736019-8d42-4bc7-97e6-e7b3f75db45e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167021803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.4167021803
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1685486420
Short name T469
Test name
Test status
Simulation time 165642306 ps
CPU time 1 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198104 kb
Host smart-b407c612-cfec-4bed-b0f2-057307d381d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685486420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1685486420
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1668951763
Short name T246
Test name
Test status
Simulation time 50120688 ps
CPU time 0.69 seconds
Started Jul 29 07:07:10 PM PDT 24
Finished Jul 29 07:07:11 PM PDT 24
Peak memory 198180 kb
Host smart-4488e0a4-191a-4b86-97f6-05ac57be29e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668951763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1668951763
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.2644424045
Short name T243
Test name
Test status
Simulation time 30171618 ps
CPU time 0.61 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198104 kb
Host smart-1e7b5370-2369-4e21-807c-598809a7c209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644424045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2644424045
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.941896870
Short name T91
Test name
Test status
Simulation time 73530816 ps
CPU time 0.66 seconds
Started Jul 29 07:07:11 PM PDT 24
Finished Jul 29 07:07:11 PM PDT 24
Peak memory 201388 kb
Host smart-dd17ae6a-3e30-46c4-8744-6ccbfbd7a7ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941896870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.941896870
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3485970736
Short name T387
Test name
Test status
Simulation time 78124580 ps
CPU time 0.66 seconds
Started Jul 29 07:07:10 PM PDT 24
Finished Jul 29 07:07:11 PM PDT 24
Peak memory 198416 kb
Host smart-ad08d440-d776-47e8-85d0-424a0c51b8b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485970736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3485970736
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1861612598
Short name T556
Test name
Test status
Simulation time 139216079 ps
CPU time 0.86 seconds
Started Jul 29 07:07:09 PM PDT 24
Finished Jul 29 07:07:10 PM PDT 24
Peak memory 209492 kb
Host smart-4dd11dfe-c93d-466d-8690-450bbd4ee096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861612598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1861612598
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1928368962
Short name T371
Test name
Test status
Simulation time 51385855 ps
CPU time 0.85 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198152 kb
Host smart-537fd7a8-9f81-4691-95a5-d7904e210b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928368962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1928368962
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.4019520610
Short name T268
Test name
Test status
Simulation time 54264700 ps
CPU time 0.63 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198544 kb
Host smart-3c3a5aee-f038-47aa-ad0e-d6a0461109ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019520610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.4019520610
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.1477447449
Short name T610
Test name
Test status
Simulation time 171664262 ps
CPU time 0.71 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 198888 kb
Host smart-6aae44dc-32e1-4371-ab81-065f9aef9ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477447449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1477447449
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3070027482
Short name T269
Test name
Test status
Simulation time 27554681 ps
CPU time 0.63 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 197364 kb
Host smart-a5b98819-2d51-457f-a79d-1915344ac771
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070027482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3070027482
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3290087194
Short name T85
Test name
Test status
Simulation time 555026925 ps
CPU time 0.97 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 198064 kb
Host smart-cd32b1d8-3693-457b-820f-408c2a847ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290087194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3290087194
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.816413172
Short name T294
Test name
Test status
Simulation time 67727870 ps
CPU time 0.62 seconds
Started Jul 29 07:07:20 PM PDT 24
Finished Jul 29 07:07:21 PM PDT 24
Peak memory 198160 kb
Host smart-8760d8b0-c180-4d60-8664-e1d5a01635f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816413172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.816413172
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3674733421
Short name T252
Test name
Test status
Simulation time 50977152 ps
CPU time 0.63 seconds
Started Jul 29 07:07:18 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 198360 kb
Host smart-3361fa19-3b16-4b2b-b1f6-56647a85e58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674733421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3674733421
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.30057795
Short name T462
Test name
Test status
Simulation time 37995955 ps
CPU time 0.69 seconds
Started Jul 29 07:07:15 PM PDT 24
Finished Jul 29 07:07:16 PM PDT 24
Peak memory 197908 kb
Host smart-ebbac1f1-49ce-43fe-90be-c966c81ea4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.30057795
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.550449953
Short name T367
Test name
Test status
Simulation time 127847183 ps
CPU time 0.78 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 209424 kb
Host smart-19c5c0a8-742c-43d0-bd20-50d7fa48116c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550449953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.550449953
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.331681476
Short name T563
Test name
Test status
Simulation time 81945723 ps
CPU time 0.74 seconds
Started Jul 29 07:07:19 PM PDT 24
Finished Jul 29 07:07:20 PM PDT 24
Peak memory 198140 kb
Host smart-1bb62f4d-6910-4efb-b351-a66cd6b83a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331681476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.331681476
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3522335737
Short name T370
Test name
Test status
Simulation time 39636142 ps
CPU time 0.66 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 199432 kb
Host smart-fc72ba5d-1f37-4a21-91ba-8ecd814a2f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522335737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3522335737
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2007053276
Short name T518
Test name
Test status
Simulation time 30537444 ps
CPU time 0.61 seconds
Started Jul 29 07:07:15 PM PDT 24
Finished Jul 29 07:07:15 PM PDT 24
Peak memory 198600 kb
Host smart-1a6e9201-6130-43f4-8a52-d7879bd1bc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007053276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2007053276
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.4168728360
Short name T176
Test name
Test status
Simulation time 89346189 ps
CPU time 0.71 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 198944 kb
Host smart-a04fe012-f21d-457f-a48b-c54623dd86bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168728360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.4168728360
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.271619022
Short name T45
Test name
Test status
Simulation time 33357716 ps
CPU time 0.61 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 198032 kb
Host smart-3a32b55a-848e-4082-8089-3fbb0f489843
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271619022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.271619022
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2702695647
Short name T617
Test name
Test status
Simulation time 165942532 ps
CPU time 0.99 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 198416 kb
Host smart-05527af1-b127-492c-a92d-f9d974c9958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702695647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2702695647
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2789327505
Short name T335
Test name
Test status
Simulation time 48310686 ps
CPU time 0.72 seconds
Started Jul 29 07:07:22 PM PDT 24
Finished Jul 29 07:07:23 PM PDT 24
Peak memory 198116 kb
Host smart-da3f38a3-c1bc-487d-a4dc-e58c4efd9d2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789327505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2789327505
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.422208819
Short name T540
Test name
Test status
Simulation time 42871021 ps
CPU time 0.64 seconds
Started Jul 29 07:07:18 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 198108 kb
Host smart-46c1bac9-c194-4e79-8fcf-6e0b3ed1c7b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422208819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.422208819
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.4189357587
Short name T415
Test name
Test status
Simulation time 55530865 ps
CPU time 0.62 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 199220 kb
Host smart-af234558-3e27-4cfb-87bd-4a77d3507009
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189357587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.4189357587
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.265930337
Short name T322
Test name
Test status
Simulation time 108431003 ps
CPU time 0.92 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 209480 kb
Host smart-188d49f4-f583-4ae6-99d8-d22b1e688779
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265930337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.265930337
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2935731478
Short name T218
Test name
Test status
Simulation time 39175403 ps
CPU time 0.65 seconds
Started Jul 29 07:07:18 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 198328 kb
Host smart-c2ff2ec6-1dc4-4369-bc6f-0d002ff82e08
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935731478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.2935731478
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.957744596
Short name T295
Test name
Test status
Simulation time 77265886 ps
CPU time 0.77 seconds
Started Jul 29 07:07:21 PM PDT 24
Finished Jul 29 07:07:22 PM PDT 24
Peak memory 198208 kb
Host smart-4ec04b6b-d5b9-446c-a0e2-a39e840ecd38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957744596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.957744596
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2370824388
Short name T288
Test name
Test status
Simulation time 30530757 ps
CPU time 0.64 seconds
Started Jul 29 07:07:19 PM PDT 24
Finished Jul 29 07:07:20 PM PDT 24
Peak memory 199388 kb
Host smart-c5a692c1-8761-4bd3-8061-64049bc60e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370824388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2370824388
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1034927726
Short name T305
Test name
Test status
Simulation time 21307542 ps
CPU time 0.78 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 200276 kb
Host smart-687f6a7f-226a-4e29-8bce-6c00cb988e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034927726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1034927726
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1027050893
Short name T146
Test name
Test status
Simulation time 58805569 ps
CPU time 0.78 seconds
Started Jul 29 07:07:16 PM PDT 24
Finished Jul 29 07:07:17 PM PDT 24
Peak memory 198508 kb
Host smart-751f341d-49c9-4c3f-852c-ec3ef8ed0797
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027050893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1027050893
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1765506768
Short name T325
Test name
Test status
Simulation time 30172422 ps
CPU time 0.68 seconds
Started Jul 29 07:07:22 PM PDT 24
Finished Jul 29 07:07:23 PM PDT 24
Peak memory 198044 kb
Host smart-559273b6-09af-486c-bc64-f814cd96397b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765506768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1765506768
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2985898353
Short name T37
Test name
Test status
Simulation time 604019311 ps
CPU time 0.94 seconds
Started Jul 29 07:07:19 PM PDT 24
Finished Jul 29 07:07:20 PM PDT 24
Peak memory 198324 kb
Host smart-2bc7f8cc-760a-42be-85b4-cf97b04f3e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985898353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2985898353
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2116237131
Short name T300
Test name
Test status
Simulation time 59558284 ps
CPU time 0.6 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 197980 kb
Host smart-ae097eb0-3fcc-42b7-ba47-940ad913b918
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116237131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2116237131
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.866259153
Short name T423
Test name
Test status
Simulation time 34335684 ps
CPU time 0.64 seconds
Started Jul 29 07:07:17 PM PDT 24
Finished Jul 29 07:07:18 PM PDT 24
Peak memory 198140 kb
Host smart-aa83e8d0-5d9a-4d2c-aacc-deb52df536e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866259153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.866259153
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.820892523
Short name T488
Test name
Test status
Simulation time 49726304 ps
CPU time 0.68 seconds
Started Jul 29 07:07:23 PM PDT 24
Finished Jul 29 07:07:24 PM PDT 24
Peak memory 198292 kb
Host smart-9310e620-3050-44f5-a658-7f365088461b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820892523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.820892523
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2880932011
Short name T528
Test name
Test status
Simulation time 143487190 ps
CPU time 0.84 seconds
Started Jul 29 07:07:18 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 209448 kb
Host smart-4e24e802-479e-4726-8b09-fa45a28d7f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880932011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2880932011
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3252340401
Short name T564
Test name
Test status
Simulation time 67923214 ps
CPU time 0.91 seconds
Started Jul 29 07:07:18 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 199396 kb
Host smart-a3140bba-3b62-4aa8-ae07-ff16933efd58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252340401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3252340401
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.3604042496
Short name T330
Test name
Test status
Simulation time 33511988 ps
CPU time 0.67 seconds
Started Jul 29 07:07:22 PM PDT 24
Finished Jul 29 07:07:23 PM PDT 24
Peak memory 199348 kb
Host smart-2ec9026a-f733-4bd7-859d-36a974652f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604042496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3604042496
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3424486017
Short name T98
Test name
Test status
Simulation time 28327883 ps
CPU time 0.9 seconds
Started Jul 29 07:07:36 PM PDT 24
Finished Jul 29 07:07:37 PM PDT 24
Peak memory 200804 kb
Host smart-cf73d454-1ebe-4c46-aabf-e39d0fb4f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424486017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3424486017
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1201512330
Short name T609
Test name
Test status
Simulation time 59883614 ps
CPU time 0.74 seconds
Started Jul 29 07:07:36 PM PDT 24
Finished Jul 29 07:07:37 PM PDT 24
Peak memory 198692 kb
Host smart-c59321f1-2e73-4f0d-b119-ae1a4ef9cafb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201512330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1201512330
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2399434870
Short name T407
Test name
Test status
Simulation time 33297294 ps
CPU time 0.62 seconds
Started Jul 29 07:07:37 PM PDT 24
Finished Jul 29 07:07:38 PM PDT 24
Peak memory 198092 kb
Host smart-72b6429c-4275-405b-b196-9d2b6a58b92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399434870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2399434870
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.3719962042
Short name T418
Test name
Test status
Simulation time 937022360 ps
CPU time 0.92 seconds
Started Jul 29 07:07:39 PM PDT 24
Finished Jul 29 07:07:40 PM PDT 24
Peak memory 198116 kb
Host smart-45886cca-28b4-43a8-8c1e-4f21cc350b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719962042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3719962042
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2043941449
Short name T86
Test name
Test status
Simulation time 50944648 ps
CPU time 0.68 seconds
Started Jul 29 07:07:36 PM PDT 24
Finished Jul 29 07:07:36 PM PDT 24
Peak memory 198112 kb
Host smart-98b1cd2a-7aa3-4f75-82e7-842ea59905e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043941449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2043941449
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.2673447224
Short name T8
Test name
Test status
Simulation time 58701323 ps
CPU time 0.61 seconds
Started Jul 29 07:07:38 PM PDT 24
Finished Jul 29 07:07:39 PM PDT 24
Peak memory 198044 kb
Host smart-3b0ad50f-be1f-4802-9c63-5946c0690be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673447224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.2673447224
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.1212688368
Short name T496
Test name
Test status
Simulation time 43204307 ps
CPU time 0.71 seconds
Started Jul 29 07:07:35 PM PDT 24
Finished Jul 29 07:07:36 PM PDT 24
Peak memory 201412 kb
Host smart-b544a29c-a033-4eb2-bf73-c1f04bf29430
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212688368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.1212688368
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3561365678
Short name T589
Test name
Test status
Simulation time 62743992 ps
CPU time 0.72 seconds
Started Jul 29 07:07:24 PM PDT 24
Finished Jul 29 07:07:25 PM PDT 24
Peak memory 199132 kb
Host smart-a2ad15b9-abe7-43a6-b6f2-3c6c220dfd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561365678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3561365678
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2052554848
Short name T353
Test name
Test status
Simulation time 94474155 ps
CPU time 0.9 seconds
Started Jul 29 07:07:36 PM PDT 24
Finished Jul 29 07:07:37 PM PDT 24
Peak memory 201364 kb
Host smart-268c12af-10e7-40ac-9825-b80048869617
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052554848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2052554848
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2240476077
Short name T631
Test name
Test status
Simulation time 78489567 ps
CPU time 0.75 seconds
Started Jul 29 07:07:40 PM PDT 24
Finished Jul 29 07:07:41 PM PDT 24
Peak memory 198024 kb
Host smart-bdbceae0-43dd-4ca9-b372-31fb0c755be5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240476077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2240476077
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.401671119
Short name T299
Test name
Test status
Simulation time 125407517 ps
CPU time 0.66 seconds
Started Jul 29 07:07:22 PM PDT 24
Finished Jul 29 07:07:23 PM PDT 24
Peak memory 198544 kb
Host smart-67d1c21b-5891-4b1b-9ed0-2e6fce7bfe99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401671119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.401671119
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.3085922769
Short name T154
Test name
Test status
Simulation time 66166439 ps
CPU time 0.82 seconds
Started Jul 29 07:07:25 PM PDT 24
Finished Jul 29 07:07:26 PM PDT 24
Peak memory 199168 kb
Host smart-186423da-68e6-4899-9751-2cf25ea91736
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085922769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.3085922769
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2251104486
Short name T478
Test name
Test status
Simulation time 59279723 ps
CPU time 0.86 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 198620 kb
Host smart-7603a412-6991-4053-86e6-4db0982e0f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251104486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2251104486
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2399717381
Short name T379
Test name
Test status
Simulation time 39243499 ps
CPU time 0.62 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 197248 kb
Host smart-5c872262-06c0-416c-9c5e-15005cb338ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399717381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2399717381
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.241418086
Short name T347
Test name
Test status
Simulation time 201653726 ps
CPU time 0.95 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 198068 kb
Host smart-9b9d47aa-1ab4-4895-b1b5-236bad87f475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241418086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.241418086
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3061768677
Short name T538
Test name
Test status
Simulation time 150086080 ps
CPU time 0.61 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 197440 kb
Host smart-5ce682a9-ef3a-4b67-a280-e6154adcd4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061768677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3061768677
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2661107724
Short name T533
Test name
Test status
Simulation time 102595361 ps
CPU time 0.64 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 198320 kb
Host smart-ec161704-94d8-4623-8157-20deae1d65f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661107724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2661107724
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.251314949
Short name T428
Test name
Test status
Simulation time 43644614 ps
CPU time 0.7 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 201452 kb
Host smart-d59b2328-1a72-41b7-8525-c277f7eb2c17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251314949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invali
d.251314949
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.455059572
Short name T231
Test name
Test status
Simulation time 27477267 ps
CPU time 0.63 seconds
Started Jul 29 07:07:38 PM PDT 24
Finished Jul 29 07:07:39 PM PDT 24
Peak memory 198136 kb
Host smart-b939aa7f-df0a-45da-ac2d-5ccc528b2832
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455059572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.455059572
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2552413105
Short name T360
Test name
Test status
Simulation time 107581029 ps
CPU time 0.94 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 209480 kb
Host smart-616a1c1f-2a35-4259-9ee9-d0173ee1d72e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552413105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2552413105
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1239962099
Short name T473
Test name
Test status
Simulation time 75353798 ps
CPU time 0.78 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 198404 kb
Host smart-ae172049-339f-4596-a1b8-3c7513d70cc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239962099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1239962099
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.205573986
Short name T624
Test name
Test status
Simulation time 29567107 ps
CPU time 0.73 seconds
Started Jul 29 07:07:37 PM PDT 24
Finished Jul 29 07:07:38 PM PDT 24
Peak memory 199388 kb
Host smart-b8d70d80-af9b-4f63-8c1c-9cad1630fdf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205573986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.205573986
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2656349101
Short name T101
Test name
Test status
Simulation time 19901604 ps
CPU time 0.69 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 199556 kb
Host smart-655868c9-6c82-4946-9b1f-3d4dd07c87db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656349101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2656349101
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.2852117837
Short name T516
Test name
Test status
Simulation time 59820273 ps
CPU time 0.69 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 199124 kb
Host smart-b1c0ac05-7e96-4004-a7ae-ada65bedef19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852117837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.2852117837
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.65907971
Short name T417
Test name
Test status
Simulation time 31107307 ps
CPU time 0.61 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:45 PM PDT 24
Peak memory 197304 kb
Host smart-43e3ab7d-bc0d-4aa2-916c-0eb6dbb179ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65907971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_m
alfunc.65907971
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.4149265847
Short name T449
Test name
Test status
Simulation time 630761536 ps
CPU time 0.96 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 198108 kb
Host smart-ef0655bf-16ad-4747-817c-ad43d4d7e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149265847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.4149265847
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.4043252889
Short name T438
Test name
Test status
Simulation time 37169691 ps
CPU time 0.63 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 198056 kb
Host smart-8ff150f3-7ed9-47a2-b6ef-1b9ab1df4324
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043252889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.4043252889
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3620558225
Short name T565
Test name
Test status
Simulation time 68079216 ps
CPU time 0.6 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 198444 kb
Host smart-4b976da5-881b-4015-8ba6-1b86f69a631f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620558225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3620558225
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2503750270
Short name T208
Test name
Test status
Simulation time 54385531 ps
CPU time 0.7 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 201404 kb
Host smart-c374b032-31bf-472e-8393-b5113a13ccc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503750270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2503750270
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2874941844
Short name T36
Test name
Test status
Simulation time 22294453 ps
CPU time 0.64 seconds
Started Jul 29 07:07:43 PM PDT 24
Finished Jul 29 07:07:44 PM PDT 24
Peak memory 199196 kb
Host smart-cc6358f3-4783-4970-a957-61846cae39a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874941844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2874941844
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.99178935
Short name T275
Test name
Test status
Simulation time 94705269 ps
CPU time 0.94 seconds
Started Jul 29 07:07:43 PM PDT 24
Finished Jul 29 07:07:44 PM PDT 24
Peak memory 209512 kb
Host smart-357a92de-312c-45c2-8c3d-4d06192a5664
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99178935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.99178935
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3228245256
Short name T381
Test name
Test status
Simulation time 29264398 ps
CPU time 0.69 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 198516 kb
Host smart-f226eaf8-1b42-448f-ab26-d4a9f2406a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228245256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3228245256
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1514698204
Short name T464
Test name
Test status
Simulation time 104228469 ps
CPU time 0.84 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 200240 kb
Host smart-b7e434bb-a841-44ec-ac9a-c6502b80b5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514698204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1514698204
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4180320814
Short name T237
Test name
Test status
Simulation time 30373522 ps
CPU time 0.65 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 198032 kb
Host smart-63a74fa2-073a-4ace-88a7-360525026382
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180320814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.4180320814
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.1129890576
Short name T411
Test name
Test status
Simulation time 169543619 ps
CPU time 0.99 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 198268 kb
Host smart-ed8db2e4-c5eb-4e94-bf18-4c4aab64f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129890576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.1129890576
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3524127810
Short name T628
Test name
Test status
Simulation time 51742743 ps
CPU time 0.61 seconds
Started Jul 29 07:07:45 PM PDT 24
Finished Jul 29 07:07:46 PM PDT 24
Peak memory 197452 kb
Host smart-036f48e7-1e5e-404d-bb0f-00533f493826
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524127810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3524127810
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3320151967
Short name T425
Test name
Test status
Simulation time 89540169 ps
CPU time 0.62 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 198104 kb
Host smart-37fd2bdd-b24e-48a8-84f9-2ac01cbccb97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320151967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3320151967
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.2944952819
Short name T202
Test name
Test status
Simulation time 66728170 ps
CPU time 0.66 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 201388 kb
Host smart-32ce880e-a3f7-45eb-b041-052369cafbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944952819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.2944952819
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.1847317626
Short name T302
Test name
Test status
Simulation time 61188746 ps
CPU time 0.83 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 198520 kb
Host smart-a8566be7-50db-476f-a5dd-caf57f3a6dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847317626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1847317626
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.3757487953
Short name T383
Test name
Test status
Simulation time 100747061 ps
CPU time 0.96 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 209596 kb
Host smart-9a6a682c-b28d-4e2b-92f8-47a991c32d62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757487953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3757487953
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2869442813
Short name T393
Test name
Test status
Simulation time 52908356 ps
CPU time 0.78 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 198168 kb
Host smart-522c1497-92bc-4da9-b96c-369a3a119d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869442813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2869442813
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3816407126
Short name T429
Test name
Test status
Simulation time 30502041 ps
CPU time 0.7 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 199388 kb
Host smart-04634569-e43e-435f-b1d5-a1c09f0a42b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816407126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3816407126
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1849558007
Short name T460
Test name
Test status
Simulation time 30080640 ps
CPU time 0.66 seconds
Started Jul 29 07:07:49 PM PDT 24
Finished Jul 29 07:07:50 PM PDT 24
Peak memory 197316 kb
Host smart-c4cc4f5a-7dae-4460-b86c-470985397b48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849558007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1849558007
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.3400096776
Short name T4
Test name
Test status
Simulation time 161389204 ps
CPU time 1 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 198404 kb
Host smart-e47a90af-2a57-4b42-bfda-68034009742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400096776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3400096776
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.303309779
Short name T543
Test name
Test status
Simulation time 26078784 ps
CPU time 0.62 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 198116 kb
Host smart-28a1c6ac-15e7-4382-937b-74eedf463dc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303309779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.303309779
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1809063936
Short name T242
Test name
Test status
Simulation time 23985284 ps
CPU time 0.6 seconds
Started Jul 29 07:07:48 PM PDT 24
Finished Jul 29 07:07:49 PM PDT 24
Peak memory 198096 kb
Host smart-007baa4a-fe8d-45f4-8678-37a1ab355bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809063936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1809063936
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1018839254
Short name T195
Test name
Test status
Simulation time 41681898 ps
CPU time 0.71 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 201500 kb
Host smart-bbec45eb-d66c-456f-82f9-205a3630beb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018839254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1018839254
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.979250154
Short name T226
Test name
Test status
Simulation time 120329132 ps
CPU time 0.77 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 198440 kb
Host smart-d434ded0-0c49-4af7-b55a-500c55d9fbb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979250154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.979250154
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.873118779
Short name T130
Test name
Test status
Simulation time 99218845 ps
CPU time 0.97 seconds
Started Jul 29 07:07:53 PM PDT 24
Finished Jul 29 07:07:54 PM PDT 24
Peak memory 209528 kb
Host smart-8a6f5683-00d2-4362-9ca9-01838dbb7482
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873118779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.873118779
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1666443970
Short name T507
Test name
Test status
Simulation time 63406003 ps
CPU time 0.77 seconds
Started Jul 29 07:07:46 PM PDT 24
Finished Jul 29 07:07:47 PM PDT 24
Peak memory 198164 kb
Host smart-1c86d720-f8d6-4b8e-ae3a-e19f95cf941d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666443970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1666443970
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.758671014
Short name T316
Test name
Test status
Simulation time 48080184 ps
CPU time 0.62 seconds
Started Jul 29 07:07:47 PM PDT 24
Finished Jul 29 07:07:48 PM PDT 24
Peak memory 199436 kb
Host smart-596fd639-f7ae-461d-a286-1095e2d8ec74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758671014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.758671014
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2829674197
Short name T453
Test name
Test status
Simulation time 107628190 ps
CPU time 0.86 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 200072 kb
Host smart-c293d142-b0ed-434a-bbdd-b61a41028f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829674197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2829674197
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2140718278
Short name T143
Test name
Test status
Simulation time 71236022 ps
CPU time 0.72 seconds
Started Jul 29 07:06:36 PM PDT 24
Finished Jul 29 07:06:37 PM PDT 24
Peak memory 199216 kb
Host smart-1f546e4d-5b92-4f65-ba06-568ea68a48f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140718278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2140718278
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3835835085
Short name T578
Test name
Test status
Simulation time 36533853 ps
CPU time 0.59 seconds
Started Jul 29 07:06:39 PM PDT 24
Finished Jul 29 07:06:40 PM PDT 24
Peak memory 197996 kb
Host smart-86dc102f-dd49-4ec7-8199-50715d62af4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835835085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3835835085
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.1705445595
Short name T409
Test name
Test status
Simulation time 158112318 ps
CPU time 0.99 seconds
Started Jul 29 07:06:40 PM PDT 24
Finished Jul 29 07:06:41 PM PDT 24
Peak memory 198128 kb
Host smart-72c7fab2-b72a-441d-ba76-78202c6fd3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705445595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1705445595
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3734835610
Short name T412
Test name
Test status
Simulation time 91319630 ps
CPU time 0.62 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:47 PM PDT 24
Peak memory 197368 kb
Host smart-9d761651-cb68-4dbb-b31e-7703012b6b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734835610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3734835610
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.3084447312
Short name T94
Test name
Test status
Simulation time 25755625 ps
CPU time 0.6 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 198436 kb
Host smart-fdd1b2f4-e9de-433c-9186-b057b48e166c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084447312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3084447312
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2800392054
Short name T189
Test name
Test status
Simulation time 43105766 ps
CPU time 0.73 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 201368 kb
Host smart-a1d7fcf1-ccc0-4176-b9e7-b442b85b8686
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800392054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2800392054
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3923978815
Short name T378
Test name
Test status
Simulation time 62541981 ps
CPU time 0.63 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 198256 kb
Host smart-532a8e26-d2dd-4109-90fa-4027e7ca14cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923978815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3923978815
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1785244698
Short name T629
Test name
Test status
Simulation time 90937142 ps
CPU time 1.07 seconds
Started Jul 29 07:06:46 PM PDT 24
Finished Jul 29 07:06:47 PM PDT 24
Peak memory 209468 kb
Host smart-1f7b5c44-c1c0-465b-a64c-46c071a560ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785244698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1785244698
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1171843485
Short name T33
Test name
Test status
Simulation time 636097419 ps
CPU time 2.13 seconds
Started Jul 29 07:06:40 PM PDT 24
Finished Jul 29 07:06:42 PM PDT 24
Peak memory 217924 kb
Host smart-4df7fdb1-300f-415b-a41f-cfe6b420569b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171843485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1171843485
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.323552028
Short name T64
Test name
Test status
Simulation time 49080422 ps
CPU time 0.7 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 198632 kb
Host smart-066bc8bd-2df3-426d-bfc6-cc3ce21a0334
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323552028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm
_ctrl_config_regwen.323552028
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.498264911
Short name T354
Test name
Test status
Simulation time 100131054 ps
CPU time 0.7 seconds
Started Jul 29 07:06:37 PM PDT 24
Finished Jul 29 07:06:38 PM PDT 24
Peak memory 197948 kb
Host smart-1b2c69df-4fbe-489f-81b4-ca7a2378962e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498264911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.498264911
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.731887432
Short name T443
Test name
Test status
Simulation time 30108543 ps
CPU time 0.69 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 199428 kb
Host smart-72687046-0d0d-48f9-bedc-b21918b9c667
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731887432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.731887432
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1802106901
Short name T620
Test name
Test status
Simulation time 32249929 ps
CPU time 0.78 seconds
Started Jul 29 07:07:54 PM PDT 24
Finished Jul 29 07:07:55 PM PDT 24
Peak memory 198756 kb
Host smart-8587906c-96b5-4af9-90a5-75b89f350d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802106901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1802106901
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3954040101
Short name T327
Test name
Test status
Simulation time 28816058 ps
CPU time 0.69 seconds
Started Jul 29 07:07:54 PM PDT 24
Finished Jul 29 07:07:55 PM PDT 24
Peak memory 198060 kb
Host smart-3368f846-d8e0-4441-8c34-404ef14795eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954040101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3954040101
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.3150839587
Short name T562
Test name
Test status
Simulation time 161906984 ps
CPU time 1 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198136 kb
Host smart-b147f05c-aaa4-483c-a769-c2ea9392e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150839587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.3150839587
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2480619392
Short name T395
Test name
Test status
Simulation time 39968565 ps
CPU time 0.58 seconds
Started Jul 29 07:07:54 PM PDT 24
Finished Jul 29 07:07:55 PM PDT 24
Peak memory 197944 kb
Host smart-c87e6ae4-95d1-4df4-b521-9501af27398a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480619392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2480619392
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2818749938
Short name T416
Test name
Test status
Simulation time 84507449 ps
CPU time 0.63 seconds
Started Jul 29 07:07:53 PM PDT 24
Finished Jul 29 07:07:54 PM PDT 24
Peak memory 198164 kb
Host smart-0d977dce-8ca1-46f2-9790-28082a0deee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818749938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2818749938
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1265076047
Short name T614
Test name
Test status
Simulation time 39804386 ps
CPU time 0.71 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 201392 kb
Host smart-e859af70-55a3-4930-a959-2531a83d3d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265076047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1265076047
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1600092858
Short name T291
Test name
Test status
Simulation time 68759748 ps
CPU time 0.71 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198364 kb
Host smart-5eec6c4d-4005-4855-8264-0ab946b12145
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600092858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1600092858
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.907565433
Short name T222
Test name
Test status
Simulation time 109007818 ps
CPU time 0.94 seconds
Started Jul 29 07:07:53 PM PDT 24
Finished Jul 29 07:07:54 PM PDT 24
Peak memory 209504 kb
Host smart-38b069bb-97e2-465d-b0e8-26d8543d7335
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907565433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.907565433
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3746354123
Short name T303
Test name
Test status
Simulation time 102815142 ps
CPU time 0.8 seconds
Started Jul 29 07:07:54 PM PDT 24
Finished Jul 29 07:07:55 PM PDT 24
Peak memory 199280 kb
Host smart-4b2c7b7b-80ac-482a-a985-a6932b71c341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746354123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3746354123
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.3297585293
Short name T301
Test name
Test status
Simulation time 29621292 ps
CPU time 0.66 seconds
Started Jul 29 07:07:52 PM PDT 24
Finished Jul 29 07:07:53 PM PDT 24
Peak memory 198528 kb
Host smart-640071e1-7d4b-4be8-96f5-27a78f14f48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297585293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3297585293
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3166356987
Short name T482
Test name
Test status
Simulation time 20518943 ps
CPU time 0.71 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 199192 kb
Host smart-5df18ab8-b124-46d8-b3da-ac53568087a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166356987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3166356987
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2883037394
Short name T529
Test name
Test status
Simulation time 58275040 ps
CPU time 0.83 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:08:00 PM PDT 24
Peak memory 199144 kb
Host smart-efeffb94-d427-476a-9cb3-3e9f3e3a107b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883037394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.2883037394
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3426812690
Short name T141
Test name
Test status
Simulation time 31201335 ps
CPU time 0.6 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 198008 kb
Host smart-8f0e9d03-df92-4293-8625-0143c0113692
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426812690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.3426812690
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.777370010
Short name T553
Test name
Test status
Simulation time 158114758 ps
CPU time 0.99 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 198172 kb
Host smart-b9b3c7d4-630b-4865-a4f7-3378d06b5112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777370010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.777370010
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.3492192732
Short name T280
Test name
Test status
Simulation time 38690815 ps
CPU time 0.62 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 198140 kb
Host smart-4ffa01e4-55d2-4bf3-b3ae-c846fe4bad22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492192732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3492192732
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1534796195
Short name T595
Test name
Test status
Simulation time 30392586 ps
CPU time 0.64 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 198112 kb
Host smart-fe604fcd-7bf4-4f53-91e4-e145e8e5dc4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534796195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1534796195
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.3707898253
Short name T183
Test name
Test status
Simulation time 70565969 ps
CPU time 0.72 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 201380 kb
Host smart-877eaecc-6286-4326-b34b-d438570bf078
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707898253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.3707898253
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3522865084
Short name T263
Test name
Test status
Simulation time 88373804 ps
CPU time 0.8 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 199100 kb
Host smart-56dbcd8c-8911-4147-804e-1c51a71983ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522865084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3522865084
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3614508733
Short name T318
Test name
Test status
Simulation time 99319095 ps
CPU time 0.93 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 209528 kb
Host smart-93e3706f-01e9-48fe-a492-b5b43bf5120a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614508733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3614508733
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1584990933
Short name T125
Test name
Test status
Simulation time 120631431 ps
CPU time 0.74 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:57 PM PDT 24
Peak memory 198108 kb
Host smart-f421d7df-9102-42c1-976f-e5d13ad251de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584990933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1584990933
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1980246263
Short name T53
Test name
Test status
Simulation time 46677811 ps
CPU time 0.63 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198544 kb
Host smart-38b26d1a-0bc8-4377-b664-1040ccbc90b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980246263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1980246263
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1929275589
Short name T96
Test name
Test status
Simulation time 20546127 ps
CPU time 0.63 seconds
Started Jul 29 07:08:00 PM PDT 24
Finished Jul 29 07:08:01 PM PDT 24
Peak memory 199200 kb
Host smart-d882d5bd-e141-4ad2-aa5a-85da6e8e81f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929275589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1929275589
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1673532118
Short name T179
Test name
Test status
Simulation time 63497604 ps
CPU time 0.71 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 199132 kb
Host smart-67e4bdd7-bf41-4014-8f64-47a3a59b6a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673532118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1673532118
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.937526601
Short name T557
Test name
Test status
Simulation time 30437095 ps
CPU time 0.65 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198072 kb
Host smart-531c641b-ed8d-4c5b-9cab-e08bb1e7f401
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937526601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_
malfunc.937526601
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.4152412954
Short name T309
Test name
Test status
Simulation time 602984078 ps
CPU time 0.96 seconds
Started Jul 29 07:07:53 PM PDT 24
Finished Jul 29 07:07:54 PM PDT 24
Peak memory 198028 kb
Host smart-2e8fd3e2-dc90-4a71-b8b4-2530bd5967d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152412954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.4152412954
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2197176495
Short name T523
Test name
Test status
Simulation time 50025425 ps
CPU time 0.64 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 197352 kb
Host smart-909d095a-4877-43dd-8e4d-057089aa14e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197176495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2197176495
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3924626841
Short name T372
Test name
Test status
Simulation time 75911614 ps
CPU time 0.59 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 198100 kb
Host smart-f1aa1743-208f-40de-8e34-84eaff636eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924626841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3924626841
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3153570147
Short name T209
Test name
Test status
Simulation time 86745074 ps
CPU time 0.69 seconds
Started Jul 29 07:07:56 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 201412 kb
Host smart-d50fe5ff-63a5-41e9-bd82-92a9133790e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153570147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3153570147
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2699844168
Short name T380
Test name
Test status
Simulation time 85055048 ps
CPU time 0.73 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:08:00 PM PDT 24
Peak memory 198188 kb
Host smart-c0f6c1e3-d1b9-4ea9-9969-3517ec2e00a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699844168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2699844168
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3149681293
Short name T388
Test name
Test status
Simulation time 111269025 ps
CPU time 0.91 seconds
Started Jul 29 07:07:53 PM PDT 24
Finished Jul 29 07:07:54 PM PDT 24
Peak memory 209408 kb
Host smart-e23c9027-45aa-4cec-9104-3148de8c5984
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149681293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3149681293
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2443773651
Short name T391
Test name
Test status
Simulation time 66401853 ps
CPU time 0.73 seconds
Started Jul 29 07:07:58 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198176 kb
Host smart-b967b2d2-79c3-4817-933e-0282a0e7f14f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443773651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2443773651
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3183443544
Short name T479
Test name
Test status
Simulation time 97193830 ps
CPU time 0.63 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 198552 kb
Host smart-fe9bda85-f89c-42a6-9207-953cb950efb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183443544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3183443544
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.98281497
Short name T598
Test name
Test status
Simulation time 41246287 ps
CPU time 0.68 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 198720 kb
Host smart-942e180d-e042-49a3-959a-caca2d4c99d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98281497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.98281497
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.438250475
Short name T166
Test name
Test status
Simulation time 73562144 ps
CPU time 0.67 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 199156 kb
Host smart-c9902379-70c8-46f0-838b-e1f44766dd05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438250475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disa
ble_rom_integrity_check.438250475
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1429587999
Short name T440
Test name
Test status
Simulation time 30876705 ps
CPU time 0.6 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:08:00 PM PDT 24
Peak memory 198076 kb
Host smart-15475bf1-a449-4524-9470-789f3671e895
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429587999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1429587999
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.2175298157
Short name T298
Test name
Test status
Simulation time 163732226 ps
CPU time 0.96 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 198108 kb
Host smart-4fd4da44-b77f-438e-974e-f03518abf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175298157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2175298157
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.805325291
Short name T535
Test name
Test status
Simulation time 21231435 ps
CPU time 0.6 seconds
Started Jul 29 07:08:00 PM PDT 24
Finished Jul 29 07:08:01 PM PDT 24
Peak memory 198032 kb
Host smart-dd06ec98-720d-4166-bea5-ed173ff1511a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805325291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.805325291
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.1085631334
Short name T312
Test name
Test status
Simulation time 64743422 ps
CPU time 0.67 seconds
Started Jul 29 07:07:52 PM PDT 24
Finished Jul 29 07:07:53 PM PDT 24
Peak memory 198436 kb
Host smart-4c0c95bf-133c-4269-b592-8d869bb1d473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085631334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.1085631334
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2275924177
Short name T32
Test name
Test status
Simulation time 77973964 ps
CPU time 0.69 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 201464 kb
Host smart-ce75a16a-f6ef-4d79-9817-152dd9dddc8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275924177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2275924177
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.3243080435
Short name T616
Test name
Test status
Simulation time 69878893 ps
CPU time 0.82 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 198348 kb
Host smart-91ce1cd1-1bbb-4ab6-89d7-f26ec89c5f72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243080435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.3243080435
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.2091541153
Short name T323
Test name
Test status
Simulation time 58646112 ps
CPU time 0.8 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:59 PM PDT 24
Peak memory 199168 kb
Host smart-2eb2aa6a-0d85-447f-809b-797054a32abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091541153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2091541153
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.2572566951
Short name T260
Test name
Test status
Simulation time 164579175 ps
CPU time 0.76 seconds
Started Jul 29 07:07:55 PM PDT 24
Finished Jul 29 07:07:56 PM PDT 24
Peak memory 209564 kb
Host smart-4593d380-3546-4c1a-b2c0-f7622ec4eb2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572566951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2572566951
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.281878517
Short name T549
Test name
Test status
Simulation time 83756486 ps
CPU time 0.74 seconds
Started Jul 29 07:07:59 PM PDT 24
Finished Jul 29 07:08:00 PM PDT 24
Peak memory 198200 kb
Host smart-382f4098-9b20-42fe-9f18-2b3e79aee529
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281878517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.281878517
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1957239383
Short name T129
Test name
Test status
Simulation time 30846894 ps
CPU time 0.67 seconds
Started Jul 29 07:07:57 PM PDT 24
Finished Jul 29 07:07:58 PM PDT 24
Peak memory 198548 kb
Host smart-e01e66fa-53da-4b20-862b-212172bb4ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957239383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1957239383
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.1400372291
Short name T401
Test name
Test status
Simulation time 79438071 ps
CPU time 0.87 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 200404 kb
Host smart-f3718650-0a1e-4811-90e0-2b3a983cd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400372291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1400372291
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2361098517
Short name T504
Test name
Test status
Simulation time 61996075 ps
CPU time 0.66 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 198488 kb
Host smart-2514dd1b-ab9f-4b3a-b797-6f51de301e83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361098517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2361098517
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.1573678577
Short name T355
Test name
Test status
Simulation time 32386908 ps
CPU time 0.64 seconds
Started Jul 29 07:08:01 PM PDT 24
Finished Jul 29 07:08:02 PM PDT 24
Peak memory 198036 kb
Host smart-20facc39-7d4f-435f-b6f1-57cb6cf2e84b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573678577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.1573678577
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.1655698666
Short name T494
Test name
Test status
Simulation time 465258931 ps
CPU time 1 seconds
Started Jul 29 07:08:02 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 198072 kb
Host smart-f19e45ba-c891-4ae4-9219-60ff0f8cdcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655698666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1655698666
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.2142816696
Short name T232
Test name
Test status
Simulation time 65160993 ps
CPU time 0.64 seconds
Started Jul 29 07:08:03 PM PDT 24
Finished Jul 29 07:08:04 PM PDT 24
Peak memory 198008 kb
Host smart-955db1d6-466f-47c8-9340-14a39751d551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142816696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.2142816696
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3100494822
Short name T410
Test name
Test status
Simulation time 261410997 ps
CPU time 0.61 seconds
Started Jul 29 07:08:00 PM PDT 24
Finished Jul 29 07:08:01 PM PDT 24
Peak memory 198124 kb
Host smart-33f9810c-aeff-4e59-ae45-1f75f6e1ea30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100494822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3100494822
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1504801918
Short name T196
Test name
Test status
Simulation time 43941634 ps
CPU time 0.73 seconds
Started Jul 29 07:08:02 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 201396 kb
Host smart-8652c0e7-8363-4322-9306-b9b50e07cb71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504801918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1504801918
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.849569633
Short name T472
Test name
Test status
Simulation time 70266987 ps
CPU time 0.89 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 198476 kb
Host smart-a5b7c0dd-e54b-42d7-bd33-5b367196d997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849569633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.849569633
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2082256054
Short name T575
Test name
Test status
Simulation time 187095879 ps
CPU time 0.83 seconds
Started Jul 29 07:08:03 PM PDT 24
Finished Jul 29 07:08:04 PM PDT 24
Peak memory 209564 kb
Host smart-80125050-775e-443d-9a19-605c4417c5db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082256054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2082256054
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2276877289
Short name T526
Test name
Test status
Simulation time 53842229 ps
CPU time 0.82 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 198176 kb
Host smart-cdb0b050-bedd-45a3-8687-a9caeabf0850
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276877289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2276877289
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3391165842
Short name T264
Test name
Test status
Simulation time 32904074 ps
CPU time 0.67 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 199368 kb
Host smart-bb1151ef-7e8c-4791-8fa2-2d7db9cc2073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391165842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3391165842
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3143170216
Short name T197
Test name
Test status
Simulation time 87171950 ps
CPU time 0.77 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 198880 kb
Host smart-90902f68-bc4c-4df4-b92e-05fd714a714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143170216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3143170216
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1955808518
Short name T165
Test name
Test status
Simulation time 60800554 ps
CPU time 0.88 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 199116 kb
Host smart-6a3cd1b9-de0f-4794-8384-a0dbc605d8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955808518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1955808518
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3377413699
Short name T139
Test name
Test status
Simulation time 31780215 ps
CPU time 0.66 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 197240 kb
Host smart-1e7cfd14-b14b-42f7-bf2f-c29c6a99af17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377413699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3377413699
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3831779613
Short name T600
Test name
Test status
Simulation time 681332387 ps
CPU time 0.97 seconds
Started Jul 29 07:08:02 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 198144 kb
Host smart-ca45439f-32d8-448c-bab0-01efa36b267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831779613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3831779613
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2501865996
Short name T458
Test name
Test status
Simulation time 40911030 ps
CPU time 0.61 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 198124 kb
Host smart-98398dca-fbeb-4f32-a34c-7bc000a68cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501865996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2501865996
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.212188910
Short name T559
Test name
Test status
Simulation time 43469229 ps
CPU time 0.63 seconds
Started Jul 29 07:08:03 PM PDT 24
Finished Jul 29 07:08:04 PM PDT 24
Peak memory 198356 kb
Host smart-2a0bd595-6d41-4c0e-9583-cb89ab2dd8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212188910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.212188910
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2016424764
Short name T599
Test name
Test status
Simulation time 75646837 ps
CPU time 0.76 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 201344 kb
Host smart-1fa498c6-1a6a-4100-a9a5-572f93dcd0d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016424764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2016424764
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.238099033
Short name T326
Test name
Test status
Simulation time 221225179 ps
CPU time 0.8 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 199112 kb
Host smart-47f61f9d-09b7-4c64-83a0-d2528585caf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238099033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.238099033
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.773942378
Short name T414
Test name
Test status
Simulation time 121593852 ps
CPU time 0.91 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 209388 kb
Host smart-29f163b1-5cb7-41b0-8f55-8ad0dd791522
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773942378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.773942378
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2625826005
Short name T35
Test name
Test status
Simulation time 378982979 ps
CPU time 0.8 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 199284 kb
Host smart-b7866fbf-e482-414e-9f42-3a104f61542e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625826005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2625826005
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3269288066
Short name T548
Test name
Test status
Simulation time 23739105 ps
CPU time 0.7 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 198656 kb
Host smart-4dac6803-c502-4dcc-bd82-7dd8a2cacc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269288066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3269288066
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3575587570
Short name T162
Test name
Test status
Simulation time 46214193 ps
CPU time 0.73 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 199172 kb
Host smart-95def8fc-5d60-4ea0-afb3-a525ed04e9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575587570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3575587570
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3431815880
Short name T351
Test name
Test status
Simulation time 28798143 ps
CPU time 0.65 seconds
Started Jul 29 07:08:03 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 198088 kb
Host smart-34234f2a-1642-4aa7-9061-50460b50a65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431815880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3431815880
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1656602404
Short name T474
Test name
Test status
Simulation time 167052981 ps
CPU time 0.94 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 198144 kb
Host smart-ae310b1d-b8df-490f-b6cb-16fc5223b650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656602404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1656602404
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.3269192600
Short name T310
Test name
Test status
Simulation time 46564540 ps
CPU time 0.7 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 197952 kb
Host smart-afce3a63-5526-4b2e-b2d4-1f89c38e5540
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269192600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3269192600
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3039318584
Short name T286
Test name
Test status
Simulation time 31523853 ps
CPU time 0.63 seconds
Started Jul 29 07:08:05 PM PDT 24
Finished Jul 29 07:08:06 PM PDT 24
Peak memory 198156 kb
Host smart-ff344352-4e96-473d-81a2-51b16ea11f4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039318584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3039318584
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.1076138050
Short name T198
Test name
Test status
Simulation time 84178230 ps
CPU time 0.66 seconds
Started Jul 29 07:08:03 PM PDT 24
Finished Jul 29 07:08:04 PM PDT 24
Peak memory 201400 kb
Host smart-fecfffaf-47e3-4247-85af-35766acc799e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076138050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.1076138050
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.1865512472
Short name T329
Test name
Test status
Simulation time 99849831 ps
CPU time 0.83 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 199112 kb
Host smart-ce4878b9-ae0f-44b7-a744-6b93859dd7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865512472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1865512472
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3788819009
Short name T593
Test name
Test status
Simulation time 94865233 ps
CPU time 0.95 seconds
Started Jul 29 07:08:02 PM PDT 24
Finished Jul 29 07:08:03 PM PDT 24
Peak memory 209616 kb
Host smart-6c404f63-d4b4-4265-a175-94b024d45516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788819009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3788819009
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2976085292
Short name T571
Test name
Test status
Simulation time 63567665 ps
CPU time 0.88 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 199236 kb
Host smart-df0bdef1-9896-42c7-9cda-86be86f8a28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976085292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2976085292
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.2110126852
Short name T583
Test name
Test status
Simulation time 52651451 ps
CPU time 0.62 seconds
Started Jul 29 07:08:04 PM PDT 24
Finished Jul 29 07:08:05 PM PDT 24
Peak memory 198736 kb
Host smart-467ccf89-d23b-4aac-aa98-9eee468b1f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110126852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.2110126852
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3390652505
Short name T430
Test name
Test status
Simulation time 59206032 ps
CPU time 0.7 seconds
Started Jul 29 07:08:09 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 198684 kb
Host smart-8df8ec4b-6bfb-4e33-a1cc-1fed8d03c441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390652505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3390652505
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.544248819
Short name T585
Test name
Test status
Simulation time 67682233 ps
CPU time 0.73 seconds
Started Jul 29 07:08:09 PM PDT 24
Finished Jul 29 07:08:10 PM PDT 24
Peak memory 198256 kb
Host smart-e678bf48-74dd-466c-8118-c0ea34422f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544248819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.544248819
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.897660200
Short name T461
Test name
Test status
Simulation time 37458922 ps
CPU time 0.59 seconds
Started Jul 29 07:08:09 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 198052 kb
Host smart-e4b66cde-6561-4b90-bc57-b86582a645a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897660200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_
malfunc.897660200
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1375113848
Short name T365
Test name
Test status
Simulation time 629117953 ps
CPU time 0.96 seconds
Started Jul 29 07:08:09 PM PDT 24
Finished Jul 29 07:08:10 PM PDT 24
Peak memory 198412 kb
Host smart-baa4563b-3644-4e1f-bff9-e9b193a44a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375113848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1375113848
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1724667863
Short name T134
Test name
Test status
Simulation time 57492304 ps
CPU time 0.64 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 198052 kb
Host smart-df0359b6-4bc9-471d-a49a-e1e8b7cf8f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724667863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1724667863
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3224253189
Short name T576
Test name
Test status
Simulation time 36418295 ps
CPU time 0.67 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:08 PM PDT 24
Peak memory 198076 kb
Host smart-11e7f503-f8d8-4e5e-b0fe-1e9721fa9df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224253189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3224253189
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.4151168298
Short name T214
Test name
Test status
Simulation time 45430359 ps
CPU time 0.75 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 201340 kb
Host smart-4dc19e57-f527-4788-acfe-229e35643efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151168298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.4151168298
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.625340529
Short name T511
Test name
Test status
Simulation time 52516753 ps
CPU time 0.72 seconds
Started Jul 29 07:08:06 PM PDT 24
Finished Jul 29 07:08:07 PM PDT 24
Peak memory 199160 kb
Host smart-13e8e04d-f453-46df-8360-250429f4ec5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625340529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.625340529
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2143877905
Short name T274
Test name
Test status
Simulation time 91879552 ps
CPU time 1.06 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:10 PM PDT 24
Peak memory 209544 kb
Host smart-fb6f2ae8-bcf7-4324-a105-5e231d8f7175
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143877905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2143877905
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.271701063
Short name T626
Test name
Test status
Simulation time 72797668 ps
CPU time 0.91 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 199180 kb
Host smart-a93784a4-cf44-42f9-a928-74d54d02a3e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271701063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.271701063
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.242544686
Short name T607
Test name
Test status
Simulation time 59804849 ps
CPU time 0.63 seconds
Started Jul 29 07:08:07 PM PDT 24
Finished Jul 29 07:08:08 PM PDT 24
Peak memory 198496 kb
Host smart-36c49e8e-f4b1-4f11-8571-ceab06542284
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242544686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.242544686
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3501983275
Short name T569
Test name
Test status
Simulation time 58957551 ps
CPU time 0.75 seconds
Started Jul 29 07:08:16 PM PDT 24
Finished Jul 29 07:08:17 PM PDT 24
Peak memory 198984 kb
Host smart-5a899d67-97bf-4a16-87ef-e2654ae49800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501983275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3501983275
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2044123114
Short name T382
Test name
Test status
Simulation time 67798399 ps
CPU time 0.66 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 199116 kb
Host smart-64426b99-cb7d-42b9-951d-c04469cbe28e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044123114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2044123114
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1286875203
Short name T465
Test name
Test status
Simulation time 32120200 ps
CPU time 0.59 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 197332 kb
Host smart-e8959542-f2ae-472a-a035-7321a254f8b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286875203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1286875203
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3208541560
Short name T374
Test name
Test status
Simulation time 158220266 ps
CPU time 0.99 seconds
Started Jul 29 07:08:23 PM PDT 24
Finished Jul 29 07:08:24 PM PDT 24
Peak memory 198388 kb
Host smart-ba1666d4-f860-42f4-b423-770bd487af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208541560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3208541560
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2485018089
Short name T446
Test name
Test status
Simulation time 152137027 ps
CPU time 0.62 seconds
Started Jul 29 07:08:13 PM PDT 24
Finished Jul 29 07:08:14 PM PDT 24
Peak memory 198140 kb
Host smart-d8d4541e-dee5-4480-ba30-2e2d2832c97a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485018089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2485018089
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3793591990
Short name T573
Test name
Test status
Simulation time 26420764 ps
CPU time 0.58 seconds
Started Jul 29 07:08:17 PM PDT 24
Finished Jul 29 07:08:18 PM PDT 24
Peak memory 198092 kb
Host smart-eee650e7-5db2-430e-9f32-2811228d8610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793591990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3793591990
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.864472390
Short name T364
Test name
Test status
Simulation time 69198035 ps
CPU time 0.67 seconds
Started Jul 29 07:08:23 PM PDT 24
Finished Jul 29 07:08:23 PM PDT 24
Peak memory 201340 kb
Host smart-e718fbcd-5bda-4bde-9425-759af376fa72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864472390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invali
d.864472390
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3044685140
Short name T615
Test name
Test status
Simulation time 66796338 ps
CPU time 0.65 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:08 PM PDT 24
Peak memory 199160 kb
Host smart-e9a34e09-f7d1-4778-bbb0-1ae033f5f52a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044685140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3044685140
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1452913745
Short name T489
Test name
Test status
Simulation time 92690051 ps
CPU time 0.92 seconds
Started Jul 29 07:08:16 PM PDT 24
Finished Jul 29 07:08:17 PM PDT 24
Peak memory 209620 kb
Host smart-38ff92b2-a1dd-4a22-997a-6bf4456c2252
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452913745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1452913745
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3012388743
Short name T605
Test name
Test status
Simulation time 104529518 ps
CPU time 0.66 seconds
Started Jul 29 07:08:14 PM PDT 24
Finished Jul 29 07:08:15 PM PDT 24
Peak memory 197972 kb
Host smart-c11bf331-15dd-47a3-aef4-4d9e333d1da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012388743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3012388743
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.1025986601
Short name T408
Test name
Test status
Simulation time 44845662 ps
CPU time 0.64 seconds
Started Jul 29 07:08:08 PM PDT 24
Finished Jul 29 07:08:09 PM PDT 24
Peak memory 198520 kb
Host smart-78a4c971-fed0-49f9-bead-182885dd6a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025986601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.1025986601
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2222031332
Short name T331
Test name
Test status
Simulation time 59004682 ps
CPU time 0.66 seconds
Started Jul 29 07:08:25 PM PDT 24
Finished Jul 29 07:08:26 PM PDT 24
Peak memory 198564 kb
Host smart-97535fd0-b0ff-4c41-9fc8-3be17d7e1557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222031332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2222031332
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.4166125528
Short name T442
Test name
Test status
Simulation time 63844769 ps
CPU time 0.71 seconds
Started Jul 29 07:08:21 PM PDT 24
Finished Jul 29 07:08:22 PM PDT 24
Peak memory 198616 kb
Host smart-c4c17293-d5ec-4edb-8c17-22c0ce9aa90c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166125528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.4166125528
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.675713311
Short name T306
Test name
Test status
Simulation time 39548285 ps
CPU time 0.61 seconds
Started Jul 29 07:08:23 PM PDT 24
Finished Jul 29 07:08:24 PM PDT 24
Peak memory 197296 kb
Host smart-22fe43e6-9921-4c48-b0ab-ca6beb5adab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675713311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.675713311
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3635220550
Short name T490
Test name
Test status
Simulation time 239657729 ps
CPU time 0.92 seconds
Started Jul 29 07:08:13 PM PDT 24
Finished Jul 29 07:08:14 PM PDT 24
Peak memory 198112 kb
Host smart-1ff5bd31-ae69-4f3c-90df-c71a07f5adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635220550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3635220550
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.881600600
Short name T317
Test name
Test status
Simulation time 50013749 ps
CPU time 0.6 seconds
Started Jul 29 07:08:15 PM PDT 24
Finished Jul 29 07:08:15 PM PDT 24
Peak memory 197352 kb
Host smart-79fa996c-d092-4509-afb1-f75112f0fef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881600600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.881600600
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3900832390
Short name T404
Test name
Test status
Simulation time 50628309 ps
CPU time 0.64 seconds
Started Jul 29 07:08:22 PM PDT 24
Finished Jul 29 07:08:22 PM PDT 24
Peak memory 198064 kb
Host smart-eb5b13a9-86a9-401e-8565-5f02b056c1e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900832390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3900832390
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.189352668
Short name T304
Test name
Test status
Simulation time 96492107 ps
CPU time 0.74 seconds
Started Jul 29 07:08:14 PM PDT 24
Finished Jul 29 07:08:14 PM PDT 24
Peak memory 198360 kb
Host smart-77beb2d5-3370-41d1-83a8-a70d0b702073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189352668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.189352668
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2869316379
Short name T297
Test name
Test status
Simulation time 210681911 ps
CPU time 0.79 seconds
Started Jul 29 07:08:22 PM PDT 24
Finished Jul 29 07:08:23 PM PDT 24
Peak memory 209492 kb
Host smart-a261c672-8108-482a-8d85-829906969a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869316379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2869316379
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1983319024
Short name T124
Test name
Test status
Simulation time 65477080 ps
CPU time 0.89 seconds
Started Jul 29 07:08:25 PM PDT 24
Finished Jul 29 07:08:26 PM PDT 24
Peak memory 198180 kb
Host smart-086c6e71-c136-43aa-bfb1-dafa425ebba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983319024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1983319024
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2608847692
Short name T151
Test name
Test status
Simulation time 40030937 ps
CPU time 0.64 seconds
Started Jul 29 07:08:21 PM PDT 24
Finished Jul 29 07:08:22 PM PDT 24
Peak memory 198440 kb
Host smart-c383491c-07e7-4439-aa00-ad6574dca156
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608847692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2608847692
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1395485515
Short name T102
Test name
Test status
Simulation time 42634906 ps
CPU time 0.8 seconds
Started Jul 29 07:06:39 PM PDT 24
Finished Jul 29 07:06:40 PM PDT 24
Peak memory 200160 kb
Host smart-4b77ba36-21ae-4068-bae4-afa53b2e4a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395485515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1395485515
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1213101097
Short name T579
Test name
Test status
Simulation time 71593977 ps
CPU time 0.68 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 198404 kb
Host smart-39521629-ea5e-41d6-8864-ff66d0444401
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213101097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1213101097
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3103033203
Short name T373
Test name
Test status
Simulation time 40798339 ps
CPU time 0.59 seconds
Started Jul 29 07:06:54 PM PDT 24
Finished Jul 29 07:06:54 PM PDT 24
Peak memory 198032 kb
Host smart-01955e82-074c-49d5-bb81-a37dfc035df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103033203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3103033203
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3704208256
Short name T314
Test name
Test status
Simulation time 324366121 ps
CPU time 1.02 seconds
Started Jul 29 07:06:49 PM PDT 24
Finished Jul 29 07:06:50 PM PDT 24
Peak memory 198448 kb
Host smart-0f5e2c6f-8b59-4289-9385-cb4b5c1c045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704208256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3704208256
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1880455624
Short name T546
Test name
Test status
Simulation time 57219066 ps
CPU time 0.63 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 197372 kb
Host smart-e4f76efe-d148-4869-9d9c-34a77e5f53d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880455624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1880455624
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3611889902
Short name T249
Test name
Test status
Simulation time 29956386 ps
CPU time 0.64 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 198120 kb
Host smart-4c136821-88d2-453b-baa2-19df0ef8382f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611889902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3611889902
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1114612827
Short name T188
Test name
Test status
Simulation time 74552398 ps
CPU time 0.69 seconds
Started Jul 29 07:06:54 PM PDT 24
Finished Jul 29 07:06:55 PM PDT 24
Peak memory 201444 kb
Host smart-85ea4e73-3d0a-47d8-a4c5-b1b4b2c24cc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114612827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1114612827
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.513187324
Short name T477
Test name
Test status
Simulation time 143058994 ps
CPU time 0.76 seconds
Started Jul 29 07:06:38 PM PDT 24
Finished Jul 29 07:06:39 PM PDT 24
Peak memory 198580 kb
Host smart-92298465-4907-4d9b-9f04-7049e8e2f943
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513187324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.513187324
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.22532592
Short name T552
Test name
Test status
Simulation time 155922945 ps
CPU time 0.84 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:48 PM PDT 24
Peak memory 209516 kb
Host smart-5653cac0-b12f-463b-9687-7dd8482216f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.22532592
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101209608
Short name T568
Test name
Test status
Simulation time 54130476 ps
CPU time 0.83 seconds
Started Jul 29 07:06:59 PM PDT 24
Finished Jul 29 07:07:00 PM PDT 24
Peak memory 199224 kb
Host smart-21a0fd2c-1d03-45dd-ae31-f687fad3479c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101209608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3101209608
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.799319630
Short name T52
Test name
Test status
Simulation time 57313490 ps
CPU time 0.63 seconds
Started Jul 29 07:06:41 PM PDT 24
Finished Jul 29 07:06:41 PM PDT 24
Peak memory 198476 kb
Host smart-659fbd3b-0d14-49f8-9d8a-42eee76b53cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799319630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.799319630
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.3766153671
Short name T100
Test name
Test status
Simulation time 267562359 ps
CPU time 0.76 seconds
Started Jul 29 07:08:22 PM PDT 24
Finished Jul 29 07:08:23 PM PDT 24
Peak memory 198812 kb
Host smart-52ccc6b1-52c8-4188-aa2e-7c010de0a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766153671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.3766153671
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.580444150
Short name T178
Test name
Test status
Simulation time 52129097 ps
CPU time 0.74 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 199128 kb
Host smart-99f3cd59-9cd2-487c-8bb1-650c206ee7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580444150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.580444150
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.591053337
Short name T618
Test name
Test status
Simulation time 38780022 ps
CPU time 0.61 seconds
Started Jul 29 07:08:24 PM PDT 24
Finished Jul 29 07:08:25 PM PDT 24
Peak memory 198056 kb
Host smart-ea89113f-fe82-49f9-b624-adf035777f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591053337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_
malfunc.591053337
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3567069274
Short name T352
Test name
Test status
Simulation time 314203642 ps
CPU time 0.99 seconds
Started Jul 29 07:08:25 PM PDT 24
Finished Jul 29 07:08:26 PM PDT 24
Peak memory 198440 kb
Host smart-a0ef4e08-2e6d-43b2-ab72-5fa6bdc7ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567069274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3567069274
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.570886248
Short name T510
Test name
Test status
Simulation time 25449582 ps
CPU time 0.61 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 197420 kb
Host smart-6db2e6a0-5789-4204-94dd-ee8ecad7a984
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570886248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.570886248
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3798673621
Short name T241
Test name
Test status
Simulation time 47866562 ps
CPU time 0.58 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 198392 kb
Host smart-d6baaf56-c7fc-4d67-89b8-c9aca0ba3505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798673621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3798673621
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2171066141
Short name T31
Test name
Test status
Simulation time 53857133 ps
CPU time 0.7 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 201452 kb
Host smart-3d3cb391-1e27-4397-ac04-583bc5a40044
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171066141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2171066141
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2368549509
Short name T266
Test name
Test status
Simulation time 62210894 ps
CPU time 0.83 seconds
Started Jul 29 07:08:25 PM PDT 24
Finished Jul 29 07:08:26 PM PDT 24
Peak memory 198396 kb
Host smart-0dcb842b-ae1f-4e0f-b8e7-917eb1533bb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368549509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2368549509
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.992990592
Short name T527
Test name
Test status
Simulation time 140044658 ps
CPU time 0.84 seconds
Started Jul 29 07:08:28 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 209532 kb
Host smart-e38a3507-a500-4c82-b4d1-5a26052be9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992990592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.992990592
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.442715069
Short name T239
Test name
Test status
Simulation time 76591610 ps
CPU time 0.89 seconds
Started Jul 29 07:08:23 PM PDT 24
Finished Jul 29 07:08:24 PM PDT 24
Peak memory 198152 kb
Host smart-3662282d-b405-4755-b6d0-5f3a39d1c903
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442715069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_
mubi.442715069
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.1654577020
Short name T476
Test name
Test status
Simulation time 68392470 ps
CPU time 0.66 seconds
Started Jul 29 07:08:22 PM PDT 24
Finished Jul 29 07:08:23 PM PDT 24
Peak memory 198524 kb
Host smart-73c18187-7cde-46ff-a188-f9a7e7fb1379
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654577020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1654577020
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.1400917866
Short name T439
Test name
Test status
Simulation time 35790436 ps
CPU time 1.21 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 200996 kb
Host smart-c1582a98-a2de-4e06-a39b-c6b545f71029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400917866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1400917866
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1471658621
Short name T147
Test name
Test status
Simulation time 54920122 ps
CPU time 0.69 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198268 kb
Host smart-d8059a13-132d-40c3-9883-548d7a808408
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471658621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1471658621
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1572982037
Short name T359
Test name
Test status
Simulation time 41254344 ps
CPU time 0.58 seconds
Started Jul 29 07:08:28 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 198036 kb
Host smart-62432f47-42e5-4c59-84f3-2846c723f1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572982037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1572982037
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1651740617
Short name T402
Test name
Test status
Simulation time 1483897138 ps
CPU time 0.97 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 198124 kb
Host smart-43c2cd6b-d19c-413f-850c-8677c30cb9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651740617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1651740617
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.4185846729
Short name T377
Test name
Test status
Simulation time 61331341 ps
CPU time 0.62 seconds
Started Jul 29 07:08:32 PM PDT 24
Finished Jul 29 07:08:33 PM PDT 24
Peak memory 198056 kb
Host smart-170f1df0-3b3e-4a36-8ab5-655f0902e96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185846729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.4185846729
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1080153022
Short name T625
Test name
Test status
Simulation time 129774033 ps
CPU time 0.6 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 198164 kb
Host smart-f0cc199b-b43e-45c7-9ca2-9efb6626f655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080153022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1080153022
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3871911953
Short name T390
Test name
Test status
Simulation time 79776840 ps
CPU time 0.68 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 201308 kb
Host smart-1f36c620-4db6-4838-91f4-2bdb1dd47575
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871911953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.3871911953
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3452273088
Short name T406
Test name
Test status
Simulation time 118262396 ps
CPU time 0.72 seconds
Started Jul 29 07:08:28 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 199204 kb
Host smart-e00924cc-0486-4423-abe0-0d2fd04a70bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452273088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3452273088
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.2877892370
Short name T501
Test name
Test status
Simulation time 457860900 ps
CPU time 0.75 seconds
Started Jul 29 07:08:28 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 209456 kb
Host smart-80afe0a2-5ac4-48c4-9aef-deb27609b9b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877892370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.2877892370
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2935576478
Short name T284
Test name
Test status
Simulation time 102054149 ps
CPU time 0.74 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 198168 kb
Host smart-ffd1df80-c882-4423-bb50-82b89af5d3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935576478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2935576478
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3897269990
Short name T89
Test name
Test status
Simulation time 35748140 ps
CPU time 0.69 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 199396 kb
Host smart-6b1fa250-453e-4e82-8fe7-626557c2adac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897269990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3897269990
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.4259437503
Short name T397
Test name
Test status
Simulation time 24341901 ps
CPU time 0.7 seconds
Started Jul 29 07:08:32 PM PDT 24
Finished Jul 29 07:08:33 PM PDT 24
Peak memory 198792 kb
Host smart-4fd9308f-b259-41bb-bfdb-23149a17d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259437503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.4259437503
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3479260574
Short name T514
Test name
Test status
Simulation time 152018177 ps
CPU time 0.68 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198460 kb
Host smart-16789456-7310-4c68-84d9-74536a719456
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479260574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3479260574
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2978121524
Short name T451
Test name
Test status
Simulation time 38239055 ps
CPU time 0.59 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 197348 kb
Host smart-722c7942-8ca9-41c0-98af-1d06128dc5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978121524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2978121524
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.1125555339
Short name T398
Test name
Test status
Simulation time 521931501 ps
CPU time 0.93 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198096 kb
Host smart-85ba6fb2-02b0-4fa0-bde0-be085728f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125555339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1125555339
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3175226385
Short name T366
Test name
Test status
Simulation time 87159837 ps
CPU time 0.61 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 198156 kb
Host smart-d7f15c59-4ea6-42a7-89ed-400e97118351
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175226385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3175226385
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3200961927
Short name T221
Test name
Test status
Simulation time 50608241 ps
CPU time 0.66 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198292 kb
Host smart-ac216295-0044-4ffb-8e93-86edaf6b0ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200961927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3200961927
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.2537900489
Short name T181
Test name
Test status
Simulation time 51199940 ps
CPU time 0.68 seconds
Started Jul 29 07:08:30 PM PDT 24
Finished Jul 29 07:08:31 PM PDT 24
Peak memory 201456 kb
Host smart-22aed940-7647-4bdc-a305-58a6a14f63fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537900489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.2537900489
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1101769358
Short name T338
Test name
Test status
Simulation time 79323715 ps
CPU time 0.8 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 199184 kb
Host smart-1554d510-2608-442f-96d1-25cec8068d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101769358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1101769358
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2017549929
Short name T517
Test name
Test status
Simulation time 160435794 ps
CPU time 0.78 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 209572 kb
Host smart-01dee42d-3ec0-4c6e-a8fd-0d7d6499b724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017549929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2017549929
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2898732137
Short name T61
Test name
Test status
Simulation time 41187128 ps
CPU time 0.63 seconds
Started Jul 29 07:08:32 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198544 kb
Host smart-22a115c0-4c17-4c02-883e-3043775b578c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898732137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.2898732137
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.161117277
Short name T450
Test name
Test status
Simulation time 153582610 ps
CPU time 0.81 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 199204 kb
Host smart-83a58bef-d9bd-45ee-b226-3bda9cce7643
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161117277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_
mubi.161117277
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2466118199
Short name T480
Test name
Test status
Simulation time 34071870 ps
CPU time 0.69 seconds
Started Jul 29 07:08:29 PM PDT 24
Finished Jul 29 07:08:30 PM PDT 24
Peak memory 199388 kb
Host smart-34cd3e8a-65e4-4277-9167-b993a11a6c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466118199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2466118199
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.287711576
Short name T459
Test name
Test status
Simulation time 50873318 ps
CPU time 0.74 seconds
Started Jul 29 07:08:28 PM PDT 24
Finished Jul 29 07:08:29 PM PDT 24
Peak memory 199192 kb
Host smart-047a89a7-06f0-4fcf-b519-f3dd0dec6ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287711576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.287711576
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.1258984120
Short name T219
Test name
Test status
Simulation time 62760813 ps
CPU time 0.69 seconds
Started Jul 29 07:08:31 PM PDT 24
Finished Jul 29 07:08:32 PM PDT 24
Peak memory 198232 kb
Host smart-4f5cf939-3905-4930-b6b0-6e8849da0460
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258984120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.1258984120
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.1684116227
Short name T611
Test name
Test status
Simulation time 27649068 ps
CPU time 0.88 seconds
Started Jul 29 07:08:33 PM PDT 24
Finished Jul 29 07:08:34 PM PDT 24
Peak memory 200340 kb
Host smart-5f5f54ba-c938-4124-bb25-aa760b0a45b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684116227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1684116227
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.4212243007
Short name T520
Test name
Test status
Simulation time 38027580 ps
CPU time 0.58 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198256 kb
Host smart-07eb7f4d-8656-4a33-8fe2-adfdab999dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212243007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.4212243007
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.3967553950
Short name T434
Test name
Test status
Simulation time 179834491 ps
CPU time 0.95 seconds
Started Jul 29 07:08:35 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198428 kb
Host smart-fc06db3a-eacc-43c0-9c97-82ce36cc1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967553950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.3967553950
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.4279178067
Short name T471
Test name
Test status
Simulation time 58074099 ps
CPU time 0.59 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 197332 kb
Host smart-9f8ea735-43c1-419a-8041-c722ac75207e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279178067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.4279178067
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.485970291
Short name T619
Test name
Test status
Simulation time 33047781 ps
CPU time 0.61 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 198136 kb
Host smart-8d60de19-34b9-4364-8ecc-b88b5368dd09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485970291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.485970291
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.17675127
Short name T503
Test name
Test status
Simulation time 39573431 ps
CPU time 0.67 seconds
Started Jul 29 07:08:32 PM PDT 24
Finished Jul 29 07:08:33 PM PDT 24
Peak memory 199168 kb
Host smart-a6e5a444-7ea2-4947-a6c8-5e58e435d612
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17675127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.17675127
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2467485804
Short name T245
Test name
Test status
Simulation time 183598466 ps
CPU time 0.81 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 209408 kb
Host smart-b1431dd9-8be4-4d27-9d00-5e13dbe28370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467485804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2467485804
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2297348377
Short name T38
Test name
Test status
Simulation time 50978124 ps
CPU time 0.84 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198112 kb
Host smart-9f98dbe4-1e85-4f4e-b4fe-18701a2647fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297348377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2297348377
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.1336601920
Short name T270
Test name
Test status
Simulation time 55782239 ps
CPU time 0.65 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 199372 kb
Host smart-bad6b761-ef2c-4c97-b93f-57d7259ae453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336601920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1336601920
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2244134028
Short name T389
Test name
Test status
Simulation time 44151525 ps
CPU time 0.63 seconds
Started Jul 29 07:08:37 PM PDT 24
Finished Jul 29 07:08:38 PM PDT 24
Peak memory 199196 kb
Host smart-ace8ce7d-90fc-4ea8-9c0b-69e2488d174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244134028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2244134028
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.902761697
Short name T144
Test name
Test status
Simulation time 65831400 ps
CPU time 0.71 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:34 PM PDT 24
Peak memory 199140 kb
Host smart-28505948-4efe-4dde-be1e-cf09d7dae170
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902761697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.902761697
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.496247039
Short name T235
Test name
Test status
Simulation time 31740246 ps
CPU time 0.61 seconds
Started Jul 29 07:08:33 PM PDT 24
Finished Jul 29 07:08:34 PM PDT 24
Peak memory 198052 kb
Host smart-fdd8206b-fcd2-4ef1-add4-91abf3fcade6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496247039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_
malfunc.496247039
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3248535090
Short name T613
Test name
Test status
Simulation time 166885080 ps
CPU time 1.03 seconds
Started Jul 29 07:08:37 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 198436 kb
Host smart-96f046e2-8c2f-48b8-b7f0-0507588bfe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248535090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3248535090
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.246586444
Short name T632
Test name
Test status
Simulation time 70075895 ps
CPU time 0.61 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 197440 kb
Host smart-1e3820ab-4a1e-4eb4-bcaf-17ef2e9b0d21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246586444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.246586444
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3105922048
Short name T483
Test name
Test status
Simulation time 38927716 ps
CPU time 0.59 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 198392 kb
Host smart-77e50b92-205b-4cbc-83e6-dec76ef417e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105922048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3105922048
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.405385373
Short name T205
Test name
Test status
Simulation time 111044864 ps
CPU time 0.72 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 201176 kb
Host smart-b234950e-7f4e-4ffc-88c9-9240375f7830
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405385373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invali
d.405385373
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.2646700757
Short name T470
Test name
Test status
Simulation time 66518119 ps
CPU time 0.83 seconds
Started Jul 29 07:08:37 PM PDT 24
Finished Jul 29 07:08:38 PM PDT 24
Peak memory 199108 kb
Host smart-88540394-f5ff-48f3-8cda-6ed6b41b48fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646700757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2646700757
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1986119322
Short name T267
Test name
Test status
Simulation time 110552633 ps
CPU time 1.05 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 209284 kb
Host smart-b015e8e8-09d7-437d-8f4c-a07669cae795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986119322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1986119322
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2055840089
Short name T258
Test name
Test status
Simulation time 72765855 ps
CPU time 0.77 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 198060 kb
Host smart-b6e668f9-ac4a-47c2-a7e4-c4f0137c5b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055840089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2055840089
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.3840981214
Short name T454
Test name
Test status
Simulation time 30839834 ps
CPU time 0.67 seconds
Started Jul 29 07:08:33 PM PDT 24
Finished Jul 29 07:08:34 PM PDT 24
Peak memory 199392 kb
Host smart-110ded7d-b3bc-4370-8160-b5db4e5dd863
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840981214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3840981214
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.2267475198
Short name T12
Test name
Test status
Simulation time 22440138 ps
CPU time 0.66 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198716 kb
Host smart-e21d33ac-4d5c-4dcc-845e-a70677f0f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267475198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.2267475198
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1513502299
Short name T161
Test name
Test status
Simulation time 67042641 ps
CPU time 0.67 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 198408 kb
Host smart-90e784cd-70ac-458e-8fb0-9bea0fd77864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513502299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1513502299
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1075093307
Short name T236
Test name
Test status
Simulation time 38286732 ps
CPU time 0.6 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 197344 kb
Host smart-588f26f0-ac3a-4926-9080-869268235135
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075093307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.1075093307
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3559941369
Short name T455
Test name
Test status
Simulation time 622738359 ps
CPU time 0.94 seconds
Started Jul 29 07:08:37 PM PDT 24
Finished Jul 29 07:08:38 PM PDT 24
Peak memory 198444 kb
Host smart-8ebfd133-c716-424c-8c51-bf4906dee6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559941369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3559941369
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3818669300
Short name T248
Test name
Test status
Simulation time 23440564 ps
CPU time 0.62 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198016 kb
Host smart-eb902912-b55b-4bf5-be50-87657a16ad69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818669300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3818669300
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1525573821
Short name T271
Test name
Test status
Simulation time 33180384 ps
CPU time 0.61 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:36 PM PDT 24
Peak memory 198052 kb
Host smart-9ff9d379-5e17-4055-b9c5-d39b87bdc33e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525573821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1525573821
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2421038742
Short name T560
Test name
Test status
Simulation time 83543478 ps
CPU time 0.61 seconds
Started Jul 29 07:08:34 PM PDT 24
Finished Jul 29 07:08:35 PM PDT 24
Peak memory 198312 kb
Host smart-af4e09b5-c075-40c9-92c8-04a419bae992
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421038742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2421038742
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.167612783
Short name T558
Test name
Test status
Simulation time 45267127 ps
CPU time 0.67 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198344 kb
Host smart-5f38c477-1b55-481f-bcc0-a2e098331dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167612783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.167612783
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1869485567
Short name T456
Test name
Test status
Simulation time 157766208 ps
CPU time 0.79 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 201100 kb
Host smart-c2a55511-5e37-4975-b80a-817f54337c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869485567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1869485567
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2133507931
Short name T447
Test name
Test status
Simulation time 50437964 ps
CPU time 0.86 seconds
Started Jul 29 07:08:35 PM PDT 24
Finished Jul 29 07:08:36 PM PDT 24
Peak memory 199348 kb
Host smart-40cf71d1-a9e1-4bdc-b8ff-d421fe741e8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133507931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2133507931
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1770680100
Short name T344
Test name
Test status
Simulation time 39913888 ps
CPU time 0.67 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 199340 kb
Host smart-1f61dcc0-1302-4282-818f-507efd198551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770680100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1770680100
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.3467699490
Short name T182
Test name
Test status
Simulation time 48477604 ps
CPU time 0.63 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:38 PM PDT 24
Peak memory 198208 kb
Host smart-0519734d-69a8-49ab-ab35-2c60f002bd18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467699490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.3467699490
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2224530435
Short name T521
Test name
Test status
Simulation time 64831103 ps
CPU time 0.63 seconds
Started Jul 29 07:08:36 PM PDT 24
Finished Jul 29 07:08:37 PM PDT 24
Peak memory 198584 kb
Host smart-99e08e62-4a54-4bf9-812c-970015fa474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224530435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2224530435
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2403823183
Short name T157
Test name
Test status
Simulation time 55240497 ps
CPU time 0.68 seconds
Started Jul 29 07:08:40 PM PDT 24
Finished Jul 29 07:08:41 PM PDT 24
Peak memory 198584 kb
Host smart-eb9bc0d4-0c20-4915-9789-e1287cb01522
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403823183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2403823183
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.96601184
Short name T233
Test name
Test status
Simulation time 43078231 ps
CPU time 0.57 seconds
Started Jul 29 07:08:40 PM PDT 24
Finished Jul 29 07:08:41 PM PDT 24
Peak memory 198016 kb
Host smart-df555a3f-d2fb-4913-b696-52ba78f4908b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96601184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_m
alfunc.96601184
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.621255657
Short name T508
Test name
Test status
Simulation time 170895094 ps
CPU time 0.97 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 198108 kb
Host smart-38c83e9a-b8c2-43e8-bee1-5d340b74a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621255657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.621255657
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3511519222
Short name T567
Test name
Test status
Simulation time 39340097 ps
CPU time 0.59 seconds
Started Jul 29 07:08:39 PM PDT 24
Finished Jul 29 07:08:40 PM PDT 24
Peak memory 198128 kb
Host smart-84c10fd7-4c14-45b7-8199-0ac25012167c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511519222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3511519222
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.828969088
Short name T481
Test name
Test status
Simulation time 82071630 ps
CPU time 0.61 seconds
Started Jul 29 07:08:38 PM PDT 24
Finished Jul 29 07:08:39 PM PDT 24
Peak memory 198096 kb
Host smart-ff44c6bc-939a-4bdc-a854-d13f59dcb300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828969088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.828969088
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2854896221
Short name T207
Test name
Test status
Simulation time 76323310 ps
CPU time 0.7 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 201364 kb
Host smart-3af17e92-637d-49ea-b017-825e632d0e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854896221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.2854896221
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1707949891
Short name T320
Test name
Test status
Simulation time 50484771 ps
CPU time 0.64 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 198184 kb
Host smart-38aeda87-9ad6-4a18-9e8c-29f5494a54f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707949891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1707949891
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1111922037
Short name T42
Test name
Test status
Simulation time 101954666 ps
CPU time 0.96 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 209568 kb
Host smart-aaf868af-c14f-4403-8726-7755b89bd61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111922037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1111922037
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1954989947
Short name T601
Test name
Test status
Simulation time 54930369 ps
CPU time 0.82 seconds
Started Jul 29 07:08:37 PM PDT 24
Finished Jul 29 07:08:38 PM PDT 24
Peak memory 199256 kb
Host smart-c19cb7a0-112f-44da-9f2c-1d1b0dd65abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954989947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1954989947
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2695355935
Short name T436
Test name
Test status
Simulation time 30255608 ps
CPU time 0.73 seconds
Started Jul 29 07:08:39 PM PDT 24
Finished Jul 29 07:08:40 PM PDT 24
Peak memory 199404 kb
Host smart-f512c47a-e08a-4ed7-bacc-349ba7feb974
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695355935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2695355935
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.305786778
Short name T122
Test name
Test status
Simulation time 99356267 ps
CPU time 0.79 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:44 PM PDT 24
Peak memory 199772 kb
Host smart-90a889b8-ade0-48a2-bf72-29034a109ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305786778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.305786778
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1322286227
Short name T160
Test name
Test status
Simulation time 82080788 ps
CPU time 0.68 seconds
Started Jul 29 07:08:42 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 199236 kb
Host smart-32c53dc5-3d8a-4673-9940-6445eae49b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322286227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.1322286227
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3439186450
Short name T592
Test name
Test status
Simulation time 61846051 ps
CPU time 0.58 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:45 PM PDT 24
Peak memory 198056 kb
Host smart-f7164805-d7fb-4c46-ba7e-0527c5836a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439186450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.3439186450
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.127515977
Short name T6
Test name
Test status
Simulation time 576997997 ps
CPU time 0.98 seconds
Started Jul 29 07:08:41 PM PDT 24
Finished Jul 29 07:08:42 PM PDT 24
Peak memory 198144 kb
Host smart-548a6567-7f8e-4a9e-9c1f-6837c7b06347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127515977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.127515977
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2927145081
Short name T586
Test name
Test status
Simulation time 51158049 ps
CPU time 0.62 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:44 PM PDT 24
Peak memory 197428 kb
Host smart-3fcf786f-8658-446c-91dd-fbd34dacabde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927145081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2927145081
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.3776837211
Short name T531
Test name
Test status
Simulation time 65217018 ps
CPU time 0.59 seconds
Started Jul 29 07:08:46 PM PDT 24
Finished Jul 29 07:08:47 PM PDT 24
Peak memory 198132 kb
Host smart-5cace8cf-7c6c-4cca-94e2-0d6c0ee90a43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776837211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3776837211
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.2467607511
Short name T83
Test name
Test status
Simulation time 54427643 ps
CPU time 0.73 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:44 PM PDT 24
Peak memory 201404 kb
Host smart-65f2958c-660a-4396-8543-ea525e98a398
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467607511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.2467607511
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1683425403
Short name T276
Test name
Test status
Simulation time 33434776 ps
CPU time 0.68 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:44 PM PDT 24
Peak memory 198548 kb
Host smart-01b68994-6573-45dc-b91e-f0779fd5df31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683425403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1683425403
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.4207319459
Short name T432
Test name
Test status
Simulation time 107055012 ps
CPU time 0.97 seconds
Started Jul 29 07:08:42 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 209480 kb
Host smart-62854c75-44da-4bf4-9132-58e889d84bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207319459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4207319459
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.981398228
Short name T127
Test name
Test status
Simulation time 57069576 ps
CPU time 0.8 seconds
Started Jul 29 07:08:42 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 198168 kb
Host smart-5434f6d9-f017-44b1-809c-41e91dcf08da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981398228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.981398228
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3014676256
Short name T265
Test name
Test status
Simulation time 34351782 ps
CPU time 0.65 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:44 PM PDT 24
Peak memory 198116 kb
Host smart-e4654514-e501-416a-8481-1eefdeff2a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014676256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3014676256
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2848796142
Short name T175
Test name
Test status
Simulation time 62100130 ps
CPU time 0.81 seconds
Started Jul 29 07:08:44 PM PDT 24
Finished Jul 29 07:08:45 PM PDT 24
Peak memory 198608 kb
Host smart-3366eb4e-81f7-47cd-af67-abe06ba3c3a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848796142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2848796142
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2490926572
Short name T324
Test name
Test status
Simulation time 31417574 ps
CPU time 0.67 seconds
Started Jul 29 07:08:46 PM PDT 24
Finished Jul 29 07:08:47 PM PDT 24
Peak memory 198076 kb
Host smart-724fdf0f-05b8-438c-8afa-5a5433245b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490926572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.2490926572
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.2666163982
Short name T457
Test name
Test status
Simulation time 624273792 ps
CPU time 0.94 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:47 PM PDT 24
Peak memory 198324 kb
Host smart-c81b3333-29c3-4f41-a429-d5da2fb27c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666163982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2666163982
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2987728197
Short name T293
Test name
Test status
Simulation time 56213989 ps
CPU time 0.69 seconds
Started Jul 29 07:08:42 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 198064 kb
Host smart-5d3838af-d484-4d9e-8c2a-6866e2797dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987728197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2987728197
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3362496565
Short name T93
Test name
Test status
Simulation time 73848726 ps
CPU time 0.59 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:45 PM PDT 24
Peak memory 198432 kb
Host smart-62771627-ca17-4d00-8bfc-8f22e9a44555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362496565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3362496565
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.598257181
Short name T206
Test name
Test status
Simulation time 45774714 ps
CPU time 0.71 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 201440 kb
Host smart-92c78c78-46bb-43af-9743-8e88c30ddf61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598257181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.598257181
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3730229661
Short name T333
Test name
Test status
Simulation time 66496208 ps
CPU time 0.85 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 199164 kb
Host smart-dcebdd95-bde4-421f-8253-0b15cf33b6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730229661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3730229661
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.2409391025
Short name T256
Test name
Test status
Simulation time 460903394 ps
CPU time 0.75 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 209544 kb
Host smart-83ddd89c-7566-4bec-8180-7b2d80645c32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409391025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.2409391025
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3491094303
Short name T594
Test name
Test status
Simulation time 63885168 ps
CPU time 0.72 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 198168 kb
Host smart-a52df194-af56-4332-b2db-e3a834956abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491094303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3491094303
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3513196185
Short name T413
Test name
Test status
Simulation time 59922277 ps
CPU time 0.62 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 198560 kb
Host smart-a98ef441-517e-4f80-addf-f7157ff2dd23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513196185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3513196185
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1127263656
Short name T437
Test name
Test status
Simulation time 174216304 ps
CPU time 0.74 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 198836 kb
Host smart-f248094b-2c42-4b51-87bb-dd476f05ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127263656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1127263656
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2573439456
Short name T505
Test name
Test status
Simulation time 65217847 ps
CPU time 0.81 seconds
Started Jul 29 07:08:50 PM PDT 24
Finished Jul 29 07:08:51 PM PDT 24
Peak memory 199472 kb
Host smart-9af629b4-e83d-45e1-8cbc-ef7bf759bbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573439456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2573439456
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.705935677
Short name T3
Test name
Test status
Simulation time 70467253 ps
CPU time 0.57 seconds
Started Jul 29 07:08:44 PM PDT 24
Finished Jul 29 07:08:45 PM PDT 24
Peak memory 197328 kb
Host smart-833c1941-e0a6-40ea-890d-0b2c66d02311
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705935677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.705935677
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.290702966
Short name T255
Test name
Test status
Simulation time 165250684 ps
CPU time 1.01 seconds
Started Jul 29 07:08:53 PM PDT 24
Finished Jul 29 07:08:55 PM PDT 24
Peak memory 198612 kb
Host smart-67c0c6f1-638e-4688-adc9-669fc2e3890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290702966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.290702966
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.4032360838
Short name T435
Test name
Test status
Simulation time 33244225 ps
CPU time 0.64 seconds
Started Jul 29 07:08:53 PM PDT 24
Finished Jul 29 07:08:54 PM PDT 24
Peak memory 198044 kb
Host smart-19d0b1a8-d793-44a3-9cfa-75fc6f2aaa73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032360838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.4032360838
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1031400275
Short name T363
Test name
Test status
Simulation time 53588786 ps
CPU time 0.58 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:09:00 PM PDT 24
Peak memory 198120 kb
Host smart-ee2872f5-34be-422a-83d4-42bf45ca0cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031400275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1031400275
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2617122549
Short name T194
Test name
Test status
Simulation time 39710369 ps
CPU time 0.68 seconds
Started Jul 29 07:09:00 PM PDT 24
Finished Jul 29 07:09:01 PM PDT 24
Peak memory 201408 kb
Host smart-00bde3ac-7391-4382-b383-f74c2fc62bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617122549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2617122549
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.874177701
Short name T261
Test name
Test status
Simulation time 96599518 ps
CPU time 0.81 seconds
Started Jul 29 07:08:46 PM PDT 24
Finished Jul 29 07:08:47 PM PDT 24
Peak memory 199140 kb
Host smart-554b183d-12ef-4956-a673-e68e0c035f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874177701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.874177701
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.536468287
Short name T223
Test name
Test status
Simulation time 112146796 ps
CPU time 0.91 seconds
Started Jul 29 07:08:54 PM PDT 24
Finished Jul 29 07:08:55 PM PDT 24
Peak memory 209396 kb
Host smart-de7c41af-59dc-4901-9840-044a375ee208
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536468287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.536468287
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3642524436
Short name T544
Test name
Test status
Simulation time 52277752 ps
CPU time 0.81 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 198312 kb
Host smart-064ee7a5-30af-47d7-8f4a-a0c507abb755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642524436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3642524436
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2013185630
Short name T551
Test name
Test status
Simulation time 240951642 ps
CPU time 0.63 seconds
Started Jul 29 07:08:43 PM PDT 24
Finished Jul 29 07:08:43 PM PDT 24
Peak memory 198540 kb
Host smart-1813464a-236e-498a-a7b1-dc3cca679543
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013185630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2013185630
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.2421509957
Short name T47
Test name
Test status
Simulation time 56042209 ps
CPU time 0.64 seconds
Started Jul 29 07:08:45 PM PDT 24
Finished Jul 29 07:08:46 PM PDT 24
Peak memory 198260 kb
Host smart-b554fed0-7d33-46de-8cba-f5e9aecf8327
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421509957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.2421509957
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.562654350
Short name T630
Test name
Test status
Simulation time 31013786 ps
CPU time 0.78 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:48 PM PDT 24
Peak memory 198868 kb
Host smart-c2b7ad68-e45b-4499-abea-9c1e14e5093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562654350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.562654350
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3905566536
Short name T148
Test name
Test status
Simulation time 63130728 ps
CPU time 0.72 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 198348 kb
Host smart-e3da1204-c364-4567-b00f-f93b372493cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905566536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3905566536
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3170050452
Short name T332
Test name
Test status
Simulation time 32788228 ps
CPU time 0.6 seconds
Started Jul 29 07:06:51 PM PDT 24
Finished Jul 29 07:06:52 PM PDT 24
Peak memory 198064 kb
Host smart-6234f565-2b05-4c15-9d31-c777328e1f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170050452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3170050452
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2653025310
Short name T580
Test name
Test status
Simulation time 319128835 ps
CPU time 0.94 seconds
Started Jul 29 07:06:50 PM PDT 24
Finished Jul 29 07:06:51 PM PDT 24
Peak memory 198108 kb
Host smart-75e51b57-85ea-4857-b05d-bdd588ab457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653025310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2653025310
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3531365044
Short name T9
Test name
Test status
Simulation time 75960972 ps
CPU time 0.63 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:56 PM PDT 24
Peak memory 197988 kb
Host smart-9cd83aec-c1fc-41cd-932e-ce07019d0c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531365044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3531365044
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.906811060
Short name T251
Test name
Test status
Simulation time 206538303 ps
CPU time 0.65 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:56 PM PDT 24
Peak memory 198316 kb
Host smart-52e801b9-04a5-4239-932e-7a2c1eeb85ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906811060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.906811060
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1348522381
Short name T193
Test name
Test status
Simulation time 68971062 ps
CPU time 0.69 seconds
Started Jul 29 07:06:49 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 201440 kb
Host smart-3b35cae7-bd45-4f73-854f-496750310619
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348522381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1348522381
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.4274856598
Short name T341
Test name
Test status
Simulation time 25358450 ps
CPU time 0.66 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 198404 kb
Host smart-ba2b1958-84fd-4c26-97f4-2cdee5f41bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274856598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.4274856598
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.3349628598
Short name T247
Test name
Test status
Simulation time 116576076 ps
CPU time 0.85 seconds
Started Jul 29 07:06:50 PM PDT 24
Finished Jul 29 07:06:51 PM PDT 24
Peak memory 209420 kb
Host smart-d502bba8-1357-4a77-a414-ffe3008ac2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349628598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.3349628598
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.985651156
Short name T18
Test name
Test status
Simulation time 348581557 ps
CPU time 1.38 seconds
Started Jul 29 07:06:50 PM PDT 24
Finished Jul 29 07:06:52 PM PDT 24
Peak memory 217512 kb
Host smart-6836c8b1-9aaf-4b7e-83e4-a16e639702a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985651156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.985651156
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.472153622
Short name T441
Test name
Test status
Simulation time 59600529 ps
CPU time 0.83 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:48 PM PDT 24
Peak memory 198160 kb
Host smart-c215f324-87c1-4756-880c-3506c7fe16cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472153622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.472153622
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.4152302235
Short name T385
Test name
Test status
Simulation time 37031767 ps
CPU time 0.68 seconds
Started Jul 29 07:06:49 PM PDT 24
Finished Jul 29 07:06:50 PM PDT 24
Peak memory 199404 kb
Host smart-cf4e28bb-9baf-4346-bc83-0bd148bb1de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152302235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.4152302235
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.752166424
Short name T522
Test name
Test status
Simulation time 24667617 ps
CPU time 0.67 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 199112 kb
Host smart-f53e5916-3fc8-4ebb-8acb-c53263377413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752166424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.752166424
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.1359056435
Short name T145
Test name
Test status
Simulation time 61909994 ps
CPU time 0.68 seconds
Started Jul 29 07:08:51 PM PDT 24
Finished Jul 29 07:08:52 PM PDT 24
Peak memory 199192 kb
Host smart-51ae4da3-5ff7-4abc-b2d3-14e44abeb4e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359056435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.1359056435
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.876842909
Short name T346
Test name
Test status
Simulation time 650933797 ps
CPU time 0.96 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:09:00 PM PDT 24
Peak memory 198108 kb
Host smart-b2d4c02f-271e-4f6a-a930-03cad38622e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876842909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.876842909
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2717651702
Short name T131
Test name
Test status
Simulation time 44510980 ps
CPU time 0.65 seconds
Started Jul 29 07:08:54 PM PDT 24
Finished Jul 29 07:08:54 PM PDT 24
Peak memory 198072 kb
Host smart-c0d38d87-692b-4611-a45e-83ec46817469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717651702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2717651702
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3024397800
Short name T250
Test name
Test status
Simulation time 31292294 ps
CPU time 0.6 seconds
Started Jul 29 07:08:56 PM PDT 24
Finished Jul 29 07:08:56 PM PDT 24
Peak memory 198092 kb
Host smart-dd026c10-59f6-4060-b2af-9aa2ae44f609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024397800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3024397800
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.759928426
Short name T561
Test name
Test status
Simulation time 24670642 ps
CPU time 0.71 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 198356 kb
Host smart-3e31a1e0-1a17-49a2-9dcf-8df5b9da62b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759928426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.759928426
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2247956088
Short name T612
Test name
Test status
Simulation time 123665107 ps
CPU time 0.87 seconds
Started Jul 29 07:08:51 PM PDT 24
Finished Jul 29 07:08:52 PM PDT 24
Peak memory 209500 kb
Host smart-564bee6e-d5ac-4d74-8b29-a7df5eabd705
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247956088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2247956088
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1096799332
Short name T340
Test name
Test status
Simulation time 56351999 ps
CPU time 0.8 seconds
Started Jul 29 07:08:50 PM PDT 24
Finished Jul 29 07:08:51 PM PDT 24
Peak memory 198116 kb
Host smart-95ef1a66-251d-41c3-96c8-40f901b8a969
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096799332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1096799332
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1846109861
Short name T336
Test name
Test status
Simulation time 65161602 ps
CPU time 0.64 seconds
Started Jul 29 07:08:50 PM PDT 24
Finished Jul 29 07:08:50 PM PDT 24
Peak memory 198588 kb
Host smart-0cdfe811-0f42-4664-950d-e79f483f86aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846109861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1846109861
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2271753526
Short name T587
Test name
Test status
Simulation time 46390391 ps
CPU time 0.97 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 200304 kb
Host smart-97257e04-d0ec-4bd8-b8bd-4a27c1f14c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271753526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2271753526
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1310978421
Short name T177
Test name
Test status
Simulation time 66090677 ps
CPU time 0.68 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 198244 kb
Host smart-955fbe54-3535-4290-b558-3b1bd407b975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310978421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1310978421
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3155070521
Short name T487
Test name
Test status
Simulation time 38523386 ps
CPU time 0.61 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 198064 kb
Host smart-512dcad5-6477-4365-ab86-fc0046e39f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155070521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3155070521
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1709199089
Short name T602
Test name
Test status
Simulation time 240809663 ps
CPU time 0.95 seconds
Started Jul 29 07:08:52 PM PDT 24
Finished Jul 29 07:08:54 PM PDT 24
Peak memory 198072 kb
Host smart-a4e8a7cd-5989-42f0-a543-64c9fb12afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709199089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1709199089
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3549394469
Short name T452
Test name
Test status
Simulation time 22863527 ps
CPU time 0.61 seconds
Started Jul 29 07:08:51 PM PDT 24
Finished Jul 29 07:08:52 PM PDT 24
Peak memory 198152 kb
Host smart-657eeab6-33d3-4bd4-8329-9c94d6f267f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549394469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3549394469
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1233161359
Short name T292
Test name
Test status
Simulation time 49285353 ps
CPU time 0.61 seconds
Started Jul 29 07:08:58 PM PDT 24
Finished Jul 29 07:08:59 PM PDT 24
Peak memory 198096 kb
Host smart-1bbe922e-9272-40c4-b609-7f6a375e7e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233161359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1233161359
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1857954208
Short name T212
Test name
Test status
Simulation time 53222835 ps
CPU time 0.74 seconds
Started Jul 29 07:09:02 PM PDT 24
Finished Jul 29 07:09:03 PM PDT 24
Peak memory 201432 kb
Host smart-7789818d-558a-4b41-873d-807bd2de3aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857954208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1857954208
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.1548943129
Short name T296
Test name
Test status
Simulation time 68878187 ps
CPU time 0.65 seconds
Started Jul 29 07:08:51 PM PDT 24
Finished Jul 29 07:08:52 PM PDT 24
Peak memory 199124 kb
Host smart-f104d373-8665-486e-b915-b509afe3e669
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548943129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1548943129
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.2502638166
Short name T419
Test name
Test status
Simulation time 124936624 ps
CPU time 0.86 seconds
Started Jul 29 07:08:53 PM PDT 24
Finished Jul 29 07:08:55 PM PDT 24
Peak memory 209456 kb
Host smart-8819332e-c716-41dc-a286-d6084c467cdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502638166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.2502638166
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2765527082
Short name T463
Test name
Test status
Simulation time 61276309 ps
CPU time 0.82 seconds
Started Jul 29 07:08:51 PM PDT 24
Finished Jul 29 07:08:53 PM PDT 24
Peak memory 198184 kb
Host smart-d29ff1cc-12c6-4fd0-b3c8-1704a24f2870
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765527082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2765527082
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3915437482
Short name T87
Test name
Test status
Simulation time 29686854 ps
CPU time 0.65 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 199356 kb
Host smart-9f4e671d-30cd-499d-9e70-2c1234e30aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915437482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3915437482
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.999684780
Short name T55
Test name
Test status
Simulation time 22214648 ps
CPU time 0.79 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:09:00 PM PDT 24
Peak memory 199168 kb
Host smart-bf57b5e5-a1aa-4e64-bca8-737969cfbcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999684780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.999684780
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2045228018
Short name T581
Test name
Test status
Simulation time 56026626 ps
CPU time 0.85 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 199192 kb
Host smart-271a77f1-ad6a-408d-96c2-00efd549df6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045228018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2045228018
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1903501167
Short name T566
Test name
Test status
Simulation time 46048142 ps
CPU time 0.62 seconds
Started Jul 29 07:08:57 PM PDT 24
Finished Jul 29 07:08:57 PM PDT 24
Peak memory 198056 kb
Host smart-9d67929e-5798-4696-a255-83592ad8257a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903501167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.1903501167
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.351246482
Short name T289
Test name
Test status
Simulation time 637330020 ps
CPU time 0.96 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 198140 kb
Host smart-7f50e185-8161-407e-9690-b7e40993e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351246482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.351246482
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2173700304
Short name T422
Test name
Test status
Simulation time 49768343 ps
CPU time 0.63 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:08:59 PM PDT 24
Peak memory 198088 kb
Host smart-708ef5dc-6e59-47b6-905e-f198787e884a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173700304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2173700304
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2524126642
Short name T502
Test name
Test status
Simulation time 49276057 ps
CPU time 0.61 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:09:00 PM PDT 24
Peak memory 198040 kb
Host smart-64523d74-7c39-4413-bd7c-ec2686c78b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524126642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2524126642
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.4220847307
Short name T376
Test name
Test status
Simulation time 45204523 ps
CPU time 0.69 seconds
Started Jul 29 07:08:57 PM PDT 24
Finished Jul 29 07:08:58 PM PDT 24
Peak memory 201388 kb
Host smart-309e3909-bf5b-4c80-92b6-e74dded67990
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220847307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.4220847307
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.4055481381
Short name T606
Test name
Test status
Simulation time 128237561 ps
CPU time 0.67 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 198504 kb
Host smart-8afc3331-7980-4c3e-8f77-11058b292034
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055481381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.4055481381
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.547565862
Short name T427
Test name
Test status
Simulation time 170820882 ps
CPU time 0.82 seconds
Started Jul 29 07:08:59 PM PDT 24
Finished Jul 29 07:09:00 PM PDT 24
Peak memory 209464 kb
Host smart-3c18097b-a1ee-4a4d-b120-660bd5c6d607
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547565862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.547565862
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1577694941
Short name T584
Test name
Test status
Simulation time 86209265 ps
CPU time 0.8 seconds
Started Jul 29 07:08:57 PM PDT 24
Finished Jul 29 07:08:58 PM PDT 24
Peak memory 198156 kb
Host smart-4c4834a9-2144-43b3-91b1-e0f1791f104e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577694941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1577694941
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.892257625
Short name T403
Test name
Test status
Simulation time 56115890 ps
CPU time 0.65 seconds
Started Jul 29 07:09:00 PM PDT 24
Finished Jul 29 07:09:01 PM PDT 24
Peak memory 198508 kb
Host smart-ab2e1daa-b8a7-43f7-987f-dc874a528671
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892257625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.892257625
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3292578020
Short name T349
Test name
Test status
Simulation time 115835037 ps
CPU time 0.8 seconds
Started Jul 29 07:09:00 PM PDT 24
Finished Jul 29 07:09:01 PM PDT 24
Peak memory 199992 kb
Host smart-6c094a67-b40b-414e-a3ba-b930f37c41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292578020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3292578020
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2858169442
Short name T149
Test name
Test status
Simulation time 258901387 ps
CPU time 0.65 seconds
Started Jul 29 07:09:04 PM PDT 24
Finished Jul 29 07:09:05 PM PDT 24
Peak memory 198460 kb
Host smart-c7fb2393-9011-42d0-8187-bdbabb638977
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858169442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2858169442
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2029031047
Short name T475
Test name
Test status
Simulation time 30729045 ps
CPU time 0.62 seconds
Started Jul 29 07:09:00 PM PDT 24
Finished Jul 29 07:09:01 PM PDT 24
Peak memory 198012 kb
Host smart-052fc340-c4d2-4267-b371-067f421e0c54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029031047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.2029031047
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3035572256
Short name T334
Test name
Test status
Simulation time 301640942 ps
CPU time 0.93 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 198132 kb
Host smart-8a1dde83-9aea-4111-9bb5-9a373a0a3707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035572256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3035572256
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2323496989
Short name T350
Test name
Test status
Simulation time 137556663 ps
CPU time 0.6 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 198112 kb
Host smart-b7d4bea7-f588-4c8a-8f5f-0146813e7085
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323496989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2323496989
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.2088086056
Short name T498
Test name
Test status
Simulation time 44951124 ps
CPU time 0.59 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:10 PM PDT 24
Peak memory 198372 kb
Host smart-29a69ba3-04df-4386-9c09-2c9850440944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088086056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2088086056
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2577309489
Short name T515
Test name
Test status
Simulation time 66136961 ps
CPU time 0.71 seconds
Started Jul 29 07:09:02 PM PDT 24
Finished Jul 29 07:09:03 PM PDT 24
Peak memory 201432 kb
Host smart-55dd0130-f41d-4c05-8782-d3e5f48cc682
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577309489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2577309489
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.4232235805
Short name T545
Test name
Test status
Simulation time 89700019 ps
CPU time 0.7 seconds
Started Jul 29 07:09:06 PM PDT 24
Finished Jul 29 07:09:08 PM PDT 24
Peak memory 199160 kb
Host smart-0c3f7abd-8498-46bb-af3a-742040285d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232235805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.4232235805
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2909833065
Short name T26
Test name
Test status
Simulation time 127065457 ps
CPU time 0.9 seconds
Started Jul 29 07:09:07 PM PDT 24
Finished Jul 29 07:09:08 PM PDT 24
Peak memory 209440 kb
Host smart-7be69775-b3f2-4c96-9216-9d28490fb92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909833065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2909833065
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2907697715
Short name T345
Test name
Test status
Simulation time 69046177 ps
CPU time 0.69 seconds
Started Jul 29 07:09:01 PM PDT 24
Finished Jul 29 07:09:02 PM PDT 24
Peak memory 198232 kb
Host smart-1a599a90-6161-43c6-b4fa-7512ef7794ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907697715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2907697715
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1135301588
Short name T542
Test name
Test status
Simulation time 69931451 ps
CPU time 0.64 seconds
Started Jul 29 07:09:02 PM PDT 24
Finished Jul 29 07:09:03 PM PDT 24
Peak memory 199360 kb
Host smart-e07c7e30-8cb5-4d4e-8a85-54aba2a64aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135301588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1135301588
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.4131125020
Short name T574
Test name
Test status
Simulation time 41851901 ps
CPU time 0.88 seconds
Started Jul 29 07:09:02 PM PDT 24
Finished Jul 29 07:09:03 PM PDT 24
Peak memory 200064 kb
Host smart-8d5a4397-7084-46c4-9b7b-1cfa7bf165a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131125020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4131125020
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.1420202538
Short name T555
Test name
Test status
Simulation time 81176169 ps
CPU time 0.65 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 199508 kb
Host smart-7dc17c62-4233-4023-b1e1-ef37a1a94642
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420202538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.1420202538
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1867751408
Short name T588
Test name
Test status
Simulation time 29816993 ps
CPU time 0.61 seconds
Started Jul 29 07:09:07 PM PDT 24
Finished Jul 29 07:09:08 PM PDT 24
Peak memory 198068 kb
Host smart-b0ca3f9a-de28-4a4d-82dc-8931d0b5ac27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867751408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1867751408
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3393901033
Short name T39
Test name
Test status
Simulation time 376080189 ps
CPU time 0.95 seconds
Started Jul 29 07:09:05 PM PDT 24
Finished Jul 29 07:09:06 PM PDT 24
Peak memory 198144 kb
Host smart-db1a9d6d-8ee4-4ecf-afaf-53b66d1f37c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393901033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3393901033
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1934665575
Short name T493
Test name
Test status
Simulation time 82752652 ps
CPU time 0.59 seconds
Started Jul 29 07:09:04 PM PDT 24
Finished Jul 29 07:09:05 PM PDT 24
Peak memory 198152 kb
Host smart-3083439e-0311-4292-bd44-ee1f37c7ec26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934665575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1934665575
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.532403842
Short name T539
Test name
Test status
Simulation time 36762017 ps
CPU time 0.61 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 198072 kb
Host smart-e0e37586-2210-4a41-b136-db7095d0d184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532403842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.532403842
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2827852002
Short name T2
Test name
Test status
Simulation time 140881119 ps
CPU time 0.78 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 199160 kb
Host smart-34121201-5448-4fda-a16f-739b2edb2315
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827852002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2827852002
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.924620164
Short name T357
Test name
Test status
Simulation time 108026573 ps
CPU time 0.98 seconds
Started Jul 29 07:09:05 PM PDT 24
Finished Jul 29 07:09:06 PM PDT 24
Peak memory 209556 kb
Host smart-f24771a0-9c5e-4a19-a3bc-0351cb22a777
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924620164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.924620164
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1784598075
Short name T220
Test name
Test status
Simulation time 83145746 ps
CPU time 0.8 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 198136 kb
Host smart-e91cf16d-cd62-4561-b630-51f457aa2c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784598075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1784598075
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1879146768
Short name T82
Test name
Test status
Simulation time 52081533 ps
CPU time 0.62 seconds
Started Jul 29 07:09:10 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 198484 kb
Host smart-c548da0c-f653-4b52-b599-3973109ac1a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879146768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1879146768
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2523493585
Short name T123
Test name
Test status
Simulation time 51324497 ps
CPU time 0.93 seconds
Started Jul 29 07:09:11 PM PDT 24
Finished Jul 29 07:09:12 PM PDT 24
Peak memory 200668 kb
Host smart-5e7477b3-a114-4d45-9231-2d990404336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523493585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2523493585
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3378124633
Short name T399
Test name
Test status
Simulation time 32964399 ps
CPU time 0.58 seconds
Started Jul 29 07:09:11 PM PDT 24
Finished Jul 29 07:09:11 PM PDT 24
Peak memory 198044 kb
Host smart-7d574bf9-dbad-4f0c-bba0-b04d962168d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378124633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3378124633
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1422562387
Short name T342
Test name
Test status
Simulation time 998094315 ps
CPU time 0.97 seconds
Started Jul 29 07:09:23 PM PDT 24
Finished Jul 29 07:09:24 PM PDT 24
Peak memory 198148 kb
Host smart-597d5762-9d3b-4560-bf03-658ad2466a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422562387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1422562387
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.3442848523
Short name T234
Test name
Test status
Simulation time 26091509 ps
CPU time 0.61 seconds
Started Jul 29 07:09:06 PM PDT 24
Finished Jul 29 07:09:07 PM PDT 24
Peak memory 197400 kb
Host smart-ef54e9f1-6172-4725-aa9b-0054500ae455
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442848523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3442848523
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1362855731
Short name T433
Test name
Test status
Simulation time 45162095 ps
CPU time 0.62 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:17 PM PDT 24
Peak memory 198424 kb
Host smart-8438876f-2373-4280-bac1-2ed2ec2e37dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362855731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1362855731
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2097450798
Short name T570
Test name
Test status
Simulation time 56596022 ps
CPU time 0.74 seconds
Started Jul 29 07:09:14 PM PDT 24
Finished Jul 29 07:09:15 PM PDT 24
Peak memory 201324 kb
Host smart-2e52f62d-ff87-431f-a277-4da739ed0ae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097450798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2097450798
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.3781057272
Short name T622
Test name
Test status
Simulation time 62369056 ps
CPU time 0.74 seconds
Started Jul 29 07:09:09 PM PDT 24
Finished Jul 29 07:09:10 PM PDT 24
Peak memory 199228 kb
Host smart-aa70f1d4-6db5-420f-a609-374f20416b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781057272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.3781057272
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2005854029
Short name T513
Test name
Test status
Simulation time 146920041 ps
CPU time 0.8 seconds
Started Jul 29 07:09:22 PM PDT 24
Finished Jul 29 07:09:23 PM PDT 24
Peak memory 201284 kb
Host smart-0fa93072-f519-43b9-a546-482522311412
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005854029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2005854029
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2418220440
Short name T328
Test name
Test status
Simulation time 117595121 ps
CPU time 0.72 seconds
Started Jul 29 07:09:12 PM PDT 24
Finished Jul 29 07:09:13 PM PDT 24
Peak memory 198036 kb
Host smart-c1a7ee6d-4e29-4f7c-a731-78e01aa5d20e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418220440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2418220440
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1045290029
Short name T308
Test name
Test status
Simulation time 154449583 ps
CPU time 0.62 seconds
Started Jul 29 07:09:07 PM PDT 24
Finished Jul 29 07:09:08 PM PDT 24
Peak memory 198560 kb
Host smart-197b4986-97e5-420f-a1de-251756e70ef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045290029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1045290029
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.1183034860
Short name T421
Test name
Test status
Simulation time 29882440 ps
CPU time 0.61 seconds
Started Jul 29 07:09:07 PM PDT 24
Finished Jul 29 07:09:08 PM PDT 24
Peak memory 198604 kb
Host smart-ad58386c-f842-43f6-af9f-e79dcf60f800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183034860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1183034860
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1857412083
Short name T180
Test name
Test status
Simulation time 56162045 ps
CPU time 0.66 seconds
Started Jul 29 07:09:09 PM PDT 24
Finished Jul 29 07:09:09 PM PDT 24
Peak memory 198188 kb
Host smart-4b99a622-b2bd-4955-9ff3-b53cb7be8e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857412083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1857412083
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3676610526
Short name T262
Test name
Test status
Simulation time 38470811 ps
CPU time 0.59 seconds
Started Jul 29 07:09:11 PM PDT 24
Finished Jul 29 07:09:12 PM PDT 24
Peak memory 198092 kb
Host smart-559cc56f-4f67-48ae-aa86-e7e8ffec44db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676610526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.3676610526
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2026819495
Short name T468
Test name
Test status
Simulation time 167077474 ps
CPU time 0.97 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198128 kb
Host smart-90a0293c-cdac-42ba-9b83-85dc7536a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026819495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2026819495
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.1994726173
Short name T15
Test name
Test status
Simulation time 47951836 ps
CPU time 0.65 seconds
Started Jul 29 07:09:23 PM PDT 24
Finished Jul 29 07:09:24 PM PDT 24
Peak memory 197372 kb
Host smart-c20b4991-95c6-4aa4-a1dd-7822d490363a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994726173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.1994726173
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.607125970
Short name T369
Test name
Test status
Simulation time 57678142 ps
CPU time 0.58 seconds
Started Jul 29 07:09:09 PM PDT 24
Finished Jul 29 07:09:09 PM PDT 24
Peak memory 198120 kb
Host smart-fb738534-df59-4f06-a351-6be46ce09da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607125970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.607125970
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1245834967
Short name T184
Test name
Test status
Simulation time 64275126 ps
CPU time 0.66 seconds
Started Jul 29 07:09:06 PM PDT 24
Finished Jul 29 07:09:07 PM PDT 24
Peak memory 201424 kb
Host smart-8ce937e9-5200-4b76-b17d-3ab5649a882c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245834967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1245834967
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3518193050
Short name T525
Test name
Test status
Simulation time 158158154 ps
CPU time 0.72 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 199140 kb
Host smart-c15b98f8-325d-4817-b664-0798c4bc3a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518193050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3518193050
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.632859333
Short name T547
Test name
Test status
Simulation time 155158159 ps
CPU time 0.78 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 209516 kb
Host smart-c95c5400-0a27-4eaa-b453-a52d31ff2092
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632859333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.632859333
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1857075704
Short name T227
Test name
Test status
Simulation time 76681129 ps
CPU time 0.72 seconds
Started Jul 29 07:09:06 PM PDT 24
Finished Jul 29 07:09:07 PM PDT 24
Peak memory 198084 kb
Host smart-c812ab53-e712-4995-bd31-22992dcb591b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857075704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1857075704
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2480976402
Short name T582
Test name
Test status
Simulation time 47173103 ps
CPU time 0.64 seconds
Started Jul 29 07:09:23 PM PDT 24
Finished Jul 29 07:09:24 PM PDT 24
Peak memory 199408 kb
Host smart-5e8c9500-1e22-4d60-bc48-4245307638a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480976402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2480976402
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3272698332
Short name T13
Test name
Test status
Simulation time 95228249 ps
CPU time 0.67 seconds
Started Jul 29 07:09:18 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198740 kb
Host smart-5514ccaf-4192-4e89-94ae-ff4cf12c2d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272698332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3272698332
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3954313238
Short name T591
Test name
Test status
Simulation time 71841922 ps
CPU time 0.68 seconds
Started Jul 29 07:09:18 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198312 kb
Host smart-f9cb039a-20cc-4e74-8ef6-249c170efb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954313238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3954313238
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.834850116
Short name T287
Test name
Test status
Simulation time 50607033 ps
CPU time 0.57 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 198064 kb
Host smart-95c9c6b5-1fd7-4bf2-8030-5f9f4ed1cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834850116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.834850116
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.1751173673
Short name T519
Test name
Test status
Simulation time 720620184 ps
CPU time 1 seconds
Started Jul 29 07:09:14 PM PDT 24
Finished Jul 29 07:09:15 PM PDT 24
Peak memory 198016 kb
Host smart-04e79c28-a52b-4316-86ec-27128b5cb4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751173673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1751173673
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1886781563
Short name T506
Test name
Test status
Simulation time 44151801 ps
CPU time 0.6 seconds
Started Jul 29 07:09:18 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198080 kb
Host smart-27cb7a56-4e2f-419a-a65b-8caf0b0dcdfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886781563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1886781563
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2445746005
Short name T554
Test name
Test status
Simulation time 37707474 ps
CPU time 0.58 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 198080 kb
Host smart-f711cc66-984e-4087-ab16-443802277033
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445746005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2445746005
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.4049902750
Short name T213
Test name
Test status
Simulation time 45024852 ps
CPU time 0.72 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 201356 kb
Host smart-b9c6b1fb-9c91-4db9-b547-ff2399d4d15a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049902750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.4049902750
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.3295052633
Short name T44
Test name
Test status
Simulation time 39036397 ps
CPU time 0.73 seconds
Started Jul 29 07:09:18 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198340 kb
Host smart-d0aff068-f9a7-446a-90d7-e5c657f1275f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295052633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.3295052633
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1399995905
Short name T358
Test name
Test status
Simulation time 150391201 ps
CPU time 0.82 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 209484 kb
Host smart-4e1ae574-1483-45f1-8372-177623b98ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399995905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1399995905
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.100771439
Short name T426
Test name
Test status
Simulation time 61163372 ps
CPU time 0.64 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 198504 kb
Host smart-e86bc1e7-4b75-488c-b720-0bc2eeb23d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100771439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.100771439
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.4266954372
Short name T499
Test name
Test status
Simulation time 93189259 ps
CPU time 0.69 seconds
Started Jul 29 07:09:14 PM PDT 24
Finished Jul 29 07:09:15 PM PDT 24
Peak memory 198336 kb
Host smart-bf5d65e9-2a26-470c-904f-991e5bb4760b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266954372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.4266954372
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.146868985
Short name T10
Test name
Test status
Simulation time 30302583 ps
CPU time 0.62 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 198024 kb
Host smart-cab4da74-feb4-4d68-81c3-4f9ee222e2f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146868985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.146868985
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2527968733
Short name T140
Test name
Test status
Simulation time 588893918 ps
CPU time 0.96 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:18 PM PDT 24
Peak memory 198092 kb
Host smart-c50f4380-e1c5-48f4-b2dd-4eea813fa473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527968733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2527968733
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3618651316
Short name T466
Test name
Test status
Simulation time 79229209 ps
CPU time 0.61 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:18 PM PDT 24
Peak memory 197412 kb
Host smart-5ad7f31b-d11e-46e0-ab08-bfa51b25c9b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618651316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3618651316
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.750230173
Short name T621
Test name
Test status
Simulation time 47334870 ps
CPU time 0.61 seconds
Started Jul 29 07:09:12 PM PDT 24
Finished Jul 29 07:09:13 PM PDT 24
Peak memory 198112 kb
Host smart-085b940a-e7aa-4f68-a9b5-c52048cea0fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750230173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.750230173
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1114649307
Short name T185
Test name
Test status
Simulation time 51293115 ps
CPU time 0.66 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 201364 kb
Host smart-8bd17274-302b-48f6-82ea-acd2e4d9c07d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114649307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1114649307
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1582378892
Short name T604
Test name
Test status
Simulation time 156979913 ps
CPU time 0.64 seconds
Started Jul 29 07:09:17 PM PDT 24
Finished Jul 29 07:09:18 PM PDT 24
Peak memory 199184 kb
Host smart-f89e4ed4-19c9-4ae9-8a03-3ca38614e36c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582378892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1582378892
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.4233922061
Short name T512
Test name
Test status
Simulation time 139346144 ps
CPU time 0.78 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 209484 kb
Host smart-905995b9-d22e-4a73-ba08-7575b0a0df26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233922061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.4233922061
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.406946140
Short name T228
Test name
Test status
Simulation time 57887033 ps
CPU time 0.84 seconds
Started Jul 29 07:09:14 PM PDT 24
Finished Jul 29 07:09:15 PM PDT 24
Peak memory 198100 kb
Host smart-f1d2bdab-dd91-491b-9db9-24940c527f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406946140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_
mubi.406946140
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3304930899
Short name T608
Test name
Test status
Simulation time 187359790 ps
CPU time 0.62 seconds
Started Jul 29 07:09:12 PM PDT 24
Finished Jul 29 07:09:13 PM PDT 24
Peak memory 198492 kb
Host smart-48edceb5-953d-4d57-9f18-9b39b76c4c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304930899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3304930899
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.308548843
Short name T534
Test name
Test status
Simulation time 22354144 ps
CPU time 0.73 seconds
Started Jul 29 07:09:12 PM PDT 24
Finished Jul 29 07:09:13 PM PDT 24
Peak memory 199200 kb
Host smart-4c9936c9-5cb0-4b89-87ce-487f315da71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308548843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.308548843
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1831691010
Short name T597
Test name
Test status
Simulation time 43646022 ps
CPU time 0.59 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 197268 kb
Host smart-4a3b2227-2204-4651-b8c5-01f2804ee22c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831691010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1831691010
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3950796110
Short name T81
Test name
Test status
Simulation time 522503046 ps
CPU time 0.9 seconds
Started Jul 29 07:09:42 PM PDT 24
Finished Jul 29 07:09:43 PM PDT 24
Peak memory 198084 kb
Host smart-c1db53a0-28e3-4cb7-a29c-0670603173cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950796110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3950796110
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.775770721
Short name T272
Test name
Test status
Simulation time 48298577 ps
CPU time 0.58 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:46 PM PDT 24
Peak memory 198052 kb
Host smart-6e6f2cc4-719c-47eb-b669-ff531306ce4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775770721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.775770721
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.2205806320
Short name T1
Test name
Test status
Simulation time 59709576 ps
CPU time 0.59 seconds
Started Jul 29 07:09:43 PM PDT 24
Finished Jul 29 07:09:44 PM PDT 24
Peak memory 198440 kb
Host smart-8a562182-5e17-466d-8821-1fb51b700c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205806320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2205806320
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1010463941
Short name T203
Test name
Test status
Simulation time 72422492 ps
CPU time 0.65 seconds
Started Jul 29 07:09:43 PM PDT 24
Finished Jul 29 07:09:44 PM PDT 24
Peak memory 201308 kb
Host smart-d5bbc76c-dd4c-47fd-a4ec-ff592f992054
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010463941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1010463941
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.4087751736
Short name T343
Test name
Test status
Simulation time 45308018 ps
CPU time 0.76 seconds
Started Jul 29 07:09:15 PM PDT 24
Finished Jul 29 07:09:16 PM PDT 24
Peak memory 198372 kb
Host smart-94696953-e8ef-4361-8632-dfdb220531b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087751736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.4087751736
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1482680258
Short name T257
Test name
Test status
Simulation time 109540880 ps
CPU time 0.79 seconds
Started Jul 29 07:09:42 PM PDT 24
Finished Jul 29 07:09:43 PM PDT 24
Peak memory 209556 kb
Host smart-f32992ac-19d5-4518-8dc8-09cbae704e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482680258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1482680258
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2888183041
Short name T229
Test name
Test status
Simulation time 51627988 ps
CPU time 0.84 seconds
Started Jul 29 07:09:13 PM PDT 24
Finished Jul 29 07:09:14 PM PDT 24
Peak memory 199368 kb
Host smart-077ff183-c318-45e5-9769-4e07fdf73374
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888183041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2888183041
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1807611358
Short name T128
Test name
Test status
Simulation time 29227151 ps
CPU time 0.68 seconds
Started Jul 29 07:09:18 PM PDT 24
Finished Jul 29 07:09:19 PM PDT 24
Peak memory 198560 kb
Host smart-96b18196-d5f4-4a0a-baed-7cb911b10828
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807611358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1807611358
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1623129690
Short name T394
Test name
Test status
Simulation time 46666022 ps
CPU time 0.71 seconds
Started Jul 29 07:06:50 PM PDT 24
Finished Jul 29 07:06:51 PM PDT 24
Peak memory 199172 kb
Host smart-045f6f4e-ff4e-459e-a6dd-5b95ac95db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623129690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1623129690
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1743536680
Short name T530
Test name
Test status
Simulation time 60855462 ps
CPU time 0.72 seconds
Started Jul 29 07:06:54 PM PDT 24
Finished Jul 29 07:06:55 PM PDT 24
Peak memory 198488 kb
Host smart-256cbc8c-98e0-4590-babf-65eee14324be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743536680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1743536680
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1480572227
Short name T400
Test name
Test status
Simulation time 28965655 ps
CPU time 0.66 seconds
Started Jul 29 07:06:48 PM PDT 24
Finished Jul 29 07:06:49 PM PDT 24
Peak memory 198040 kb
Host smart-715e46d6-09c2-4b50-9431-f45facacb89a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480572227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1480572227
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.4108384491
Short name T339
Test name
Test status
Simulation time 465147575 ps
CPU time 0.95 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 198348 kb
Host smart-7be5a516-dfa3-4ba9-96e6-fab32774c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108384491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.4108384491
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.994058822
Short name T405
Test name
Test status
Simulation time 51008981 ps
CPU time 0.6 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:55 PM PDT 24
Peak memory 198124 kb
Host smart-68babdc9-ea1a-40f4-90d1-05d8b84e4a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994058822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.994058822
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3637256319
Short name T315
Test name
Test status
Simulation time 31252661 ps
CPU time 0.64 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 198332 kb
Host smart-d3d284ad-acf6-4e5b-8eb5-da8b8170652b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637256319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3637256319
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.543977463
Short name T199
Test name
Test status
Simulation time 82179609 ps
CPU time 0.7 seconds
Started Jul 29 07:06:58 PM PDT 24
Finished Jul 29 07:06:59 PM PDT 24
Peak memory 201624 kb
Host smart-853b802e-09e2-43a8-bd00-d3d6e5d23d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543977463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.543977463
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.3655029812
Short name T217
Test name
Test status
Simulation time 37606364 ps
CPU time 0.65 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:48 PM PDT 24
Peak memory 198028 kb
Host smart-d7aba728-235f-4b31-9ae9-3368f6609279
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655029812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.3655029812
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2083903782
Short name T285
Test name
Test status
Simulation time 89079843 ps
CPU time 0.72 seconds
Started Jul 29 07:06:47 PM PDT 24
Finished Jul 29 07:06:48 PM PDT 24
Peak memory 198472 kb
Host smart-6b03c815-0016-49df-8417-9665bc676fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083903782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2083903782
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.4057034139
Short name T509
Test name
Test status
Simulation time 245841537 ps
CPU time 0.79 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:56 PM PDT 24
Peak memory 209500 kb
Host smart-21f429a2-9a36-46e4-9475-35cf1399910d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057034139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.4057034139
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3853059081
Short name T281
Test name
Test status
Simulation time 80723406 ps
CPU time 0.69 seconds
Started Jul 29 07:06:49 PM PDT 24
Finished Jul 29 07:06:50 PM PDT 24
Peak memory 198168 kb
Host smart-e40f4924-f4e4-4c7c-8391-9ae134c32ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853059081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3853059081
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1821275943
Short name T627
Test name
Test status
Simulation time 28195801 ps
CPU time 0.68 seconds
Started Jul 29 07:06:46 PM PDT 24
Finished Jul 29 07:06:47 PM PDT 24
Peak memory 198540 kb
Host smart-ddccec2a-55d5-40f5-a554-df272081ae67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821275943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1821275943
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.2082490886
Short name T50
Test name
Test status
Simulation time 45660341 ps
CPU time 0.62 seconds
Started Jul 29 07:06:46 PM PDT 24
Finished Jul 29 07:06:46 PM PDT 24
Peak memory 198264 kb
Host smart-fda70390-0f31-42ae-9d92-a549c4e1af3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082490886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.2082490886
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.954581609
Short name T550
Test name
Test status
Simulation time 56143359 ps
CPU time 0.84 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 200004 kb
Host smart-eaa4dd08-4511-4dbd-85ac-30101eca4d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954581609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.954581609
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.4242565948
Short name T28
Test name
Test status
Simulation time 49622971 ps
CPU time 0.76 seconds
Started Jul 29 07:06:57 PM PDT 24
Finished Jul 29 07:06:58 PM PDT 24
Peak memory 199184 kb
Host smart-2228d2b3-4589-47a3-ae60-b8bba3fd93e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242565948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.4242565948
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.646788524
Short name T253
Test name
Test status
Simulation time 29233575 ps
CPU time 0.62 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:56 PM PDT 24
Peak memory 197364 kb
Host smart-5d966445-3879-44ed-a06c-5ea765bcdffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646788524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_m
alfunc.646788524
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3967845352
Short name T283
Test name
Test status
Simulation time 679460421 ps
CPU time 0.96 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 198136 kb
Host smart-8df9b1a2-9185-4144-b910-7309cdbedcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967845352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3967845352
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3021066976
Short name T537
Test name
Test status
Simulation time 56963413 ps
CPU time 0.65 seconds
Started Jul 29 07:07:03 PM PDT 24
Finished Jul 29 07:07:04 PM PDT 24
Peak memory 198164 kb
Host smart-535233ea-c7b9-4a70-b525-1c41c570a9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021066976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3021066976
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.3080714470
Short name T445
Test name
Test status
Simulation time 73999623 ps
CPU time 0.62 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:56 PM PDT 24
Peak memory 198124 kb
Host smart-ab53a060-46b3-4ce5-88a0-e350948eed54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080714470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3080714470
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2247091986
Short name T30
Test name
Test status
Simulation time 82887000 ps
CPU time 0.69 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 201460 kb
Host smart-b0b43809-0e9c-4042-b64d-e7ca89146055
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247091986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2247091986
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1222452348
Short name T277
Test name
Test status
Simulation time 120862576 ps
CPU time 0.8 seconds
Started Jul 29 07:06:59 PM PDT 24
Finished Jul 29 07:07:00 PM PDT 24
Peak memory 199304 kb
Host smart-b5bfdc5b-a6fc-43bc-b92c-16031192c786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222452348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1222452348
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.3876792580
Short name T375
Test name
Test status
Simulation time 200853742 ps
CPU time 0.79 seconds
Started Jul 29 07:06:57 PM PDT 24
Finished Jul 29 07:06:58 PM PDT 24
Peak memory 209400 kb
Host smart-e5bcb406-57d5-4c33-a10a-1ec9c550b024
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876792580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.3876792580
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3895277482
Short name T273
Test name
Test status
Simulation time 96200932 ps
CPU time 0.71 seconds
Started Jul 29 07:06:57 PM PDT 24
Finished Jul 29 07:06:58 PM PDT 24
Peak memory 198292 kb
Host smart-d803e2a5-6e69-43fe-95a4-bbfe60daac21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895277482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3895277482
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1043494421
Short name T88
Test name
Test status
Simulation time 30721248 ps
CPU time 0.68 seconds
Started Jul 29 07:07:03 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 198572 kb
Host smart-4752060c-b6fa-487c-98ca-8fbeeaa27376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043494421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1043494421
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.570269801
Short name T497
Test name
Test status
Simulation time 78573382 ps
CPU time 0.74 seconds
Started Jul 29 07:06:57 PM PDT 24
Finished Jul 29 07:06:58 PM PDT 24
Peak memory 198720 kb
Host smart-60e70ed2-6ded-4a49-9927-e98d421d53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570269801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.570269801
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.523378913
Short name T290
Test name
Test status
Simulation time 55134232 ps
CPU time 0.85 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 198600 kb
Host smart-faffb633-f20c-4364-85df-f7c3de2a0a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523378913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.523378913
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2843757052
Short name T386
Test name
Test status
Simulation time 83281678 ps
CPU time 0.58 seconds
Started Jul 29 07:06:55 PM PDT 24
Finished Jul 29 07:06:55 PM PDT 24
Peak memory 198088 kb
Host smart-0aae7cc3-7f7d-4e6a-9e8f-a858dc2097f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843757052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2843757052
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.25188001
Short name T491
Test name
Test status
Simulation time 634372989 ps
CPU time 0.99 seconds
Started Jul 29 07:07:03 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 198328 kb
Host smart-922ed601-19e7-4710-aa71-690221add03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25188001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.25188001
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1807747911
Short name T282
Test name
Test status
Simulation time 41379298 ps
CPU time 0.66 seconds
Started Jul 29 07:07:03 PM PDT 24
Finished Jul 29 07:07:04 PM PDT 24
Peak memory 198108 kb
Host smart-a163783b-4c41-46d4-b111-ffc5460d9ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807747911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1807747911
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1367432299
Short name T356
Test name
Test status
Simulation time 23260514 ps
CPU time 0.61 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 197392 kb
Host smart-304628df-5276-408b-a77a-87f42392a8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367432299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1367432299
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.4257285938
Short name T29
Test name
Test status
Simulation time 57870616 ps
CPU time 0.71 seconds
Started Jul 29 07:07:02 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 201304 kb
Host smart-295729fb-b695-42ae-9384-05e41e0a547e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257285938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.4257285938
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.3674640102
Short name T244
Test name
Test status
Simulation time 80445157 ps
CPU time 0.66 seconds
Started Jul 29 07:06:56 PM PDT 24
Finished Jul 29 07:06:57 PM PDT 24
Peak memory 199112 kb
Host smart-8ebbcd2f-9bf1-4beb-af31-590692efb1b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674640102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3674640102
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2731351913
Short name T95
Test name
Test status
Simulation time 191218053 ps
CPU time 0.89 seconds
Started Jul 29 07:06:57 PM PDT 24
Finished Jul 29 07:06:58 PM PDT 24
Peak memory 199364 kb
Host smart-1f0a9ef1-d21a-4ebd-9858-1dea541e42b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731351913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2731351913
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.4001007109
Short name T392
Test name
Test status
Simulation time 24432214 ps
CPU time 0.68 seconds
Started Jul 29 07:07:02 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 199416 kb
Host smart-0233d40c-07ea-4adb-8b08-ead07770bd63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001007109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.4001007109
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.4103494379
Short name T485
Test name
Test status
Simulation time 38822224 ps
CPU time 0.86 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 200168 kb
Host smart-c442bc87-6a4e-4246-b0e2-77099376213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103494379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.4103494379
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.645172879
Short name T590
Test name
Test status
Simulation time 59469242 ps
CPU time 0.73 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 198496 kb
Host smart-e1289eb6-022e-4244-bf17-6f8a37072aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645172879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.645172879
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2538910974
Short name T132
Test name
Test status
Simulation time 34652329 ps
CPU time 0.64 seconds
Started Jul 29 07:07:02 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 198036 kb
Host smart-41d868e5-bc9b-4127-9515-cda064d517b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538910974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2538910974
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2579267785
Short name T444
Test name
Test status
Simulation time 332851344 ps
CPU time 0.96 seconds
Started Jul 29 07:07:02 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 198052 kb
Host smart-07876c43-689f-4aba-a1c7-bc0fadccb53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579267785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2579267785
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2497072752
Short name T150
Test name
Test status
Simulation time 59661240 ps
CPU time 0.63 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198048 kb
Host smart-7371c93d-6b85-4b8f-8b34-13f1836c4b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497072752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2497072752
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1142109532
Short name T279
Test name
Test status
Simulation time 80075282 ps
CPU time 0.63 seconds
Started Jul 29 07:07:01 PM PDT 24
Finished Jul 29 07:07:02 PM PDT 24
Peak memory 198132 kb
Host smart-ac86eba7-2708-42e2-a73f-1746e24b917a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142109532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1142109532
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.432852198
Short name T191
Test name
Test status
Simulation time 45311384 ps
CPU time 0.86 seconds
Started Jul 29 07:07:01 PM PDT 24
Finished Jul 29 07:07:02 PM PDT 24
Peak memory 201220 kb
Host smart-e75874d8-8ef6-443e-8f47-b6e7f2a1b53f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432852198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.432852198
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2067566212
Short name T41
Test name
Test status
Simulation time 74993253 ps
CPU time 0.68 seconds
Started Jul 29 07:07:01 PM PDT 24
Finished Jul 29 07:07:01 PM PDT 24
Peak memory 198500 kb
Host smart-f0fdecf8-c62d-4efb-aebc-4f62e1ca20e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067566212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2067566212
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3623756375
Short name T68
Test name
Test status
Simulation time 79774953 ps
CPU time 0.74 seconds
Started Jul 29 07:07:02 PM PDT 24
Finished Jul 29 07:07:03 PM PDT 24
Peak memory 198232 kb
Host smart-74ef782d-599d-4a8e-924f-3d59567fdae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623756375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3623756375
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2918887028
Short name T484
Test name
Test status
Simulation time 57170292 ps
CPU time 0.63 seconds
Started Jul 29 07:07:00 PM PDT 24
Finished Jul 29 07:07:01 PM PDT 24
Peak memory 198532 kb
Host smart-9b8c89fb-c46b-4f29-9a0f-cdf8ee78d8ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918887028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2918887028
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.4033076156
Short name T97
Test name
Test status
Simulation time 54187732 ps
CPU time 0.77 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 200060 kb
Host smart-1757e7e6-821e-4034-a077-84afad59a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033076156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.4033076156
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2652288592
Short name T577
Test name
Test status
Simulation time 56377151 ps
CPU time 0.73 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 197844 kb
Host smart-a69c77a9-4459-4cc5-8d0e-36a15ffa0c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652288592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2652288592
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.365087893
Short name T492
Test name
Test status
Simulation time 32749893 ps
CPU time 0.59 seconds
Started Jul 29 07:07:00 PM PDT 24
Finished Jul 29 07:07:01 PM PDT 24
Peak memory 197364 kb
Host smart-0683b01c-4b6f-47dd-a5b2-872c56557acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365087893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_m
alfunc.365087893
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2852664095
Short name T254
Test name
Test status
Simulation time 320123702 ps
CPU time 1.02 seconds
Started Jul 29 07:07:03 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 198092 kb
Host smart-130167fe-f8b1-432a-85e2-5af0cafe8dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852664095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2852664095
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2662336574
Short name T596
Test name
Test status
Simulation time 50048834 ps
CPU time 0.61 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:04 PM PDT 24
Peak memory 197372 kb
Host smart-ad79d570-0535-4098-9853-7a3a30f9f3b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662336574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2662336574
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2830521298
Short name T321
Test name
Test status
Simulation time 29045536 ps
CPU time 0.63 seconds
Started Jul 29 07:07:04 PM PDT 24
Finished Jul 29 07:07:05 PM PDT 24
Peak memory 198428 kb
Host smart-ce42e05f-b646-490e-b90c-82445a3ae799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830521298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2830521298
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.419802935
Short name T210
Test name
Test status
Simulation time 65037985 ps
CPU time 0.7 seconds
Started Jul 29 07:07:05 PM PDT 24
Finished Jul 29 07:07:06 PM PDT 24
Peak memory 201384 kb
Host smart-ddb69cb1-68a3-48ef-af4a-f1fa8785d85b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419802935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid
.419802935
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1280222232
Short name T384
Test name
Test status
Simulation time 79615001 ps
CPU time 0.71 seconds
Started Jul 29 07:07:05 PM PDT 24
Finished Jul 29 07:07:06 PM PDT 24
Peak memory 198420 kb
Host smart-a2e714a9-ba92-4edd-a786-46d68ebb4f56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280222232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1280222232
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2872496933
Short name T43
Test name
Test status
Simulation time 124705230 ps
CPU time 0.9 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 209528 kb
Host smart-aad6d5ee-10bc-4941-8379-add5ce5933b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872496933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2872496933
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.248916044
Short name T319
Test name
Test status
Simulation time 65950823 ps
CPU time 0.89 seconds
Started Jul 29 07:07:01 PM PDT 24
Finished Jul 29 07:07:02 PM PDT 24
Peak memory 199036 kb
Host smart-401c4ae4-a70d-480a-9179-44e790d864d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248916044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.248916044
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.1392261577
Short name T603
Test name
Test status
Simulation time 43377384 ps
CPU time 0.66 seconds
Started Jul 29 07:07:08 PM PDT 24
Finished Jul 29 07:07:09 PM PDT 24
Peak memory 198496 kb
Host smart-1dc27ae9-4ff5-4daa-b906-8e16048e556f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392261577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1392261577
Directory /workspace/9.pwrmgr_smoke/latest
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