Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.37 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 2 62 96.88


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 2 62 96.88 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 543 1 T4 2 T11 7 T12 7
auto[1] 461 1 T11 4 T12 1 T25 3


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 555 1 T4 2 T11 5 T12 7
auto[1] 449 1 T11 6 T12 1 T26 4


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 455 1 T11 7 T12 4 T25 6
auto[1] 549 1 T4 2 T11 4 T12 4


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 834 1 T4 1 T11 11 T12 8
auto[1] 170 1 T4 1 T25 2 T26 2


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 419 1 T11 5 T12 4 T25 3
auto[1] 585 1 T4 2 T11 6 T12 4


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 533 1 T4 2 T11 4 T12 4
auto[1] 471 1 T11 7 T12 4 T25 5


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 2 62 96.88 2


Automatically Generated Cross Bins for control_cross

Uncovered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] 0 1 1


Covered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 19 1 T11 1 T12 2 T41 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 2 1 T41 1 T151 1 - -
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 24 1 T26 1 T41 1 T80 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 3 1 T41 1 T80 1 T58 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 21 1 T12 1 T54 1 T53 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 70 1 T4 1 T11 1 T12 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 56 1 T4 1 T27 1 T54 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 23 1 T11 1 T13 1 T52 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 5 1 T22 1 T152 1 T153 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 23 1 T12 1 T50 1 T51 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T154 1 T58 1 T155 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 31 1 T12 1 T25 2 T53 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 5 1 T25 1 T156 1 T157 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 24 1 T54 1 T53 1 T87 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 4 1 T54 1 T152 1 T42 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 23 1 T13 1 T52 1 T158 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 3 1 T49 1 T159 1 T160 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 27 1 T13 1 T86 1 T53 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 6 1 T161 1 T43 1 T162 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 18 1 T11 1 T86 1 T155 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 2 1 T155 1 T161 1 - -
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 26 1 T26 1 T163 1 T53 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 4 1 T26 1 T163 1 T164 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 22 1 T11 1 T13 1 T165 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 4 1 T165 1 T166 1 T167 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 27 1 T11 1 T13 1 T50 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 4 1 T165 1 T168 1 T169 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 28 1 T50 1 T80 1 T170 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 5 1 T50 1 T170 1 T171 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 26 1 T11 1 T12 1 T26 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 3 1 T26 1 T172 1 T173 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 20 1 T25 1 T13 2 T51 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 2 1 T174 1 T175 1 - -
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 20 1 T54 1 T52 1 T89 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 21 1 T52 2 T88 2 T89 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 2 1 T22 1 T176 1 - -
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 31 1 T13 1 T52 1 T177 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 8 1 T178 1 T42 1 T43 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 26 1 T25 1 T51 1 T88 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 3 1 T25 1 T166 1 T179 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 28 1 T12 1 T26 1 T13 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 2 1 T180 1 T42 1 - -
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 37 1 T11 2 T13 3 T80 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 5 1 T80 1 T180 1 T181 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 31 1 T41 1 T51 1 T52 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 4 1 T43 1 T176 1 T182 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 32 1 T41 1 T163 1 T170 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 6 1 T183 1 T168 1 T46 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 17 1 T13 1 T53 1 T52 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 2 1 T184 1 T173 1 - -
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 33 1 T13 1 T86 1 T185 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 8 1 T185 2 T151 1 T186 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 23 1 T11 1 T50 1 T88 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 4 1 T50 1 T43 1 T44 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 22 1 T11 1 T13 1 T52 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 4 1 T154 1 T178 1 T187 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 13 1 T170 2 T89 1 T188 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 2 1 T170 1 T153 1 - -
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 21 1 T13 1 T51 1 T156 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 2 1 T156 1 T157 1 - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 27 1 T13 2 T163 1 T53 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 5 1 T43 1 T186 1 T171 1

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