Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.37 98.23 96.15 99.44 96.00 96.18 100.00 95.58


Total test records in report: 730
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T171 /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2368308263 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:15 PM PDT 24 41236034 ps
T565 /workspace/coverage/default/9.pwrmgr_global_esc.2067517397 Jul 31 05:16:04 PM PDT 24 Jul 31 05:16:05 PM PDT 24 22458926 ps
T566 /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1992832496 Jul 31 05:15:26 PM PDT 24 Jul 31 05:15:27 PM PDT 24 38367489 ps
T567 /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4085081459 Jul 31 05:17:06 PM PDT 24 Jul 31 05:17:06 PM PDT 24 84478518 ps
T568 /workspace/coverage/default/41.pwrmgr_escalation_timeout.888861955 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:01 PM PDT 24 605740814 ps
T569 /workspace/coverage/default/22.pwrmgr_reset_invalid.2081773492 Jul 31 05:16:53 PM PDT 24 Jul 31 05:16:54 PM PDT 24 115633149 ps
T570 /workspace/coverage/default/18.pwrmgr_aborted_low_power.645476841 Jul 31 05:16:37 PM PDT 24 Jul 31 05:16:38 PM PDT 24 33106668 ps
T571 /workspace/coverage/default/13.pwrmgr_global_esc.267315724 Jul 31 05:16:17 PM PDT 24 Jul 31 05:16:18 PM PDT 24 42869105 ps
T572 /workspace/coverage/default/23.pwrmgr_reset_invalid.3893871222 Jul 31 05:16:54 PM PDT 24 Jul 31 05:16:55 PM PDT 24 103365419 ps
T573 /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1314817403 Jul 31 05:17:21 PM PDT 24 Jul 31 05:17:22 PM PDT 24 30889358 ps
T574 /workspace/coverage/default/15.pwrmgr_glitch.2139319201 Jul 31 05:16:40 PM PDT 24 Jul 31 05:16:40 PM PDT 24 59204326 ps
T575 /workspace/coverage/default/8.pwrmgr_smoke.156576862 Jul 31 05:15:50 PM PDT 24 Jul 31 05:15:50 PM PDT 24 65498713 ps
T576 /workspace/coverage/default/38.pwrmgr_smoke.4002381327 Jul 31 05:17:39 PM PDT 24 Jul 31 05:17:39 PM PDT 24 82416443 ps
T577 /workspace/coverage/default/42.pwrmgr_escalation_timeout.3816455994 Jul 31 05:17:46 PM PDT 24 Jul 31 05:17:47 PM PDT 24 162158838 ps
T578 /workspace/coverage/default/21.pwrmgr_reset_invalid.2352363076 Jul 31 05:17:09 PM PDT 24 Jul 31 05:17:10 PM PDT 24 94312480 ps
T159 /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1766877707 Jul 31 05:17:46 PM PDT 24 Jul 31 05:17:46 PM PDT 24 44087485 ps
T579 /workspace/coverage/default/40.pwrmgr_glitch.1853473385 Jul 31 05:17:35 PM PDT 24 Jul 31 05:17:36 PM PDT 24 61598041 ps
T580 /workspace/coverage/default/30.pwrmgr_global_esc.2443747244 Jul 31 05:17:10 PM PDT 24 Jul 31 05:17:11 PM PDT 24 36228220 ps
T581 /workspace/coverage/default/17.pwrmgr_glitch.2072017620 Jul 31 05:16:21 PM PDT 24 Jul 31 05:16:27 PM PDT 24 53365845 ps
T582 /workspace/coverage/default/9.pwrmgr_glitch.3510062377 Jul 31 05:16:12 PM PDT 24 Jul 31 05:16:13 PM PDT 24 48222979 ps
T583 /workspace/coverage/default/47.pwrmgr_reset_invalid.1493807387 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:02 PM PDT 24 241021540 ps
T584 /workspace/coverage/default/37.pwrmgr_smoke.1702916878 Jul 31 05:17:17 PM PDT 24 Jul 31 05:17:18 PM PDT 24 36436346 ps
T206 /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2769641416 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:14 PM PDT 24 64680979 ps
T585 /workspace/coverage/default/40.pwrmgr_reset.3633497941 Jul 31 05:17:26 PM PDT 24 Jul 31 05:17:32 PM PDT 24 75160168 ps
T209 /workspace/coverage/default/6.pwrmgr_wakeup.2408565721 Jul 31 05:15:53 PM PDT 24 Jul 31 05:15:54 PM PDT 24 55315796 ps
T586 /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3892138118 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 62023499 ps
T160 /workspace/coverage/default/29.pwrmgr_lowpower_invalid.36553057 Jul 31 05:17:16 PM PDT 24 Jul 31 05:17:17 PM PDT 24 71886448 ps
T587 /workspace/coverage/default/40.pwrmgr_aborted_low_power.894949954 Jul 31 05:17:34 PM PDT 24 Jul 31 05:17:35 PM PDT 24 23301416 ps
T588 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2125453599 Jul 31 05:17:59 PM PDT 24 Jul 31 05:17:59 PM PDT 24 29176579 ps
T589 /workspace/coverage/default/5.pwrmgr_reset_invalid.1215376004 Jul 31 05:15:30 PM PDT 24 Jul 31 05:15:31 PM PDT 24 98406652 ps
T590 /workspace/coverage/default/27.pwrmgr_aborted_low_power.2744010175 Jul 31 05:16:59 PM PDT 24 Jul 31 05:17:00 PM PDT 24 54599865 ps
T591 /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.197615394 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:03 PM PDT 24 165407714 ps
T592 /workspace/coverage/default/40.pwrmgr_global_esc.220816140 Jul 31 05:17:46 PM PDT 24 Jul 31 05:17:47 PM PDT 24 37071078 ps
T593 /workspace/coverage/default/29.pwrmgr_reset.3049268202 Jul 31 05:17:14 PM PDT 24 Jul 31 05:17:15 PM PDT 24 87708792 ps
T594 /workspace/coverage/default/23.pwrmgr_reset.472904600 Jul 31 05:17:02 PM PDT 24 Jul 31 05:17:03 PM PDT 24 59043698 ps
T595 /workspace/coverage/default/32.pwrmgr_reset.4037654176 Jul 31 05:17:24 PM PDT 24 Jul 31 05:17:25 PM PDT 24 60672180 ps
T596 /workspace/coverage/default/26.pwrmgr_reset_invalid.3594133011 Jul 31 05:17:12 PM PDT 24 Jul 31 05:17:13 PM PDT 24 145681081 ps
T597 /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.13410991 Jul 31 05:16:59 PM PDT 24 Jul 31 05:17:00 PM PDT 24 198751022 ps
T29 /workspace/coverage/default/0.pwrmgr_sec_cm.3652087969 Jul 31 05:15:24 PM PDT 24 Jul 31 05:15:26 PM PDT 24 657345279 ps
T598 /workspace/coverage/default/26.pwrmgr_glitch.2151998711 Jul 31 05:17:03 PM PDT 24 Jul 31 05:17:03 PM PDT 24 35461154 ps
T599 /workspace/coverage/default/45.pwrmgr_reset.2256522727 Jul 31 05:17:47 PM PDT 24 Jul 31 05:17:48 PM PDT 24 69571658 ps
T600 /workspace/coverage/default/46.pwrmgr_reset.3339928952 Jul 31 05:17:58 PM PDT 24 Jul 31 05:17:59 PM PDT 24 110127179 ps
T601 /workspace/coverage/default/0.pwrmgr_reset_invalid.3350104872 Jul 31 05:15:09 PM PDT 24 Jul 31 05:15:10 PM PDT 24 98567592 ps
T602 /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1626176821 Jul 31 05:17:06 PM PDT 24 Jul 31 05:17:07 PM PDT 24 70825146 ps
T603 /workspace/coverage/default/4.pwrmgr_glitch.4198340283 Jul 31 05:15:20 PM PDT 24 Jul 31 05:15:21 PM PDT 24 67209815 ps
T604 /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2927855650 Jul 31 05:17:06 PM PDT 24 Jul 31 05:17:07 PM PDT 24 63662617 ps
T605 /workspace/coverage/default/4.pwrmgr_reset_invalid.1171205852 Jul 31 05:15:28 PM PDT 24 Jul 31 05:15:29 PM PDT 24 375546056 ps
T606 /workspace/coverage/default/13.pwrmgr_reset.3559798093 Jul 31 05:16:14 PM PDT 24 Jul 31 05:16:14 PM PDT 24 149033638 ps
T187 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3830403471 Jul 31 05:15:55 PM PDT 24 Jul 31 05:15:56 PM PDT 24 50725793 ps
T607 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.444645571 Jul 31 05:16:58 PM PDT 24 Jul 31 05:16:59 PM PDT 24 44650098 ps
T608 /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1334652197 Jul 31 05:17:57 PM PDT 24 Jul 31 05:17:58 PM PDT 24 91131658 ps
T609 /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1709038289 Jul 31 05:17:16 PM PDT 24 Jul 31 05:17:17 PM PDT 24 78711370 ps
T610 /workspace/coverage/default/41.pwrmgr_aborted_low_power.1454832766 Jul 31 05:17:52 PM PDT 24 Jul 31 05:17:52 PM PDT 24 98017015 ps
T611 /workspace/coverage/default/1.pwrmgr_glitch.4110485850 Jul 31 05:15:19 PM PDT 24 Jul 31 05:15:20 PM PDT 24 59110647 ps
T612 /workspace/coverage/default/38.pwrmgr_aborted_low_power.3142589538 Jul 31 05:17:32 PM PDT 24 Jul 31 05:17:32 PM PDT 24 113116683 ps
T613 /workspace/coverage/default/25.pwrmgr_reset_invalid.1492742107 Jul 31 05:16:59 PM PDT 24 Jul 31 05:17:00 PM PDT 24 112766963 ps
T614 /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1177238887 Jul 31 05:16:47 PM PDT 24 Jul 31 05:16:48 PM PDT 24 42756920 ps
T615 /workspace/coverage/default/28.pwrmgr_reset_invalid.4127868293 Jul 31 05:17:09 PM PDT 24 Jul 31 05:17:10 PM PDT 24 117360649 ps
T173 /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1916582329 Jul 31 05:17:37 PM PDT 24 Jul 31 05:17:38 PM PDT 24 84613006 ps
T616 /workspace/coverage/default/45.pwrmgr_smoke.388549366 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:03 PM PDT 24 37054140 ps
T617 /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.4103799262 Jul 31 05:17:16 PM PDT 24 Jul 31 05:17:16 PM PDT 24 93211532 ps
T618 /workspace/coverage/default/1.pwrmgr_reset.1859582821 Jul 31 05:15:10 PM PDT 24 Jul 31 05:15:11 PM PDT 24 54284189 ps
T619 /workspace/coverage/default/46.pwrmgr_aborted_low_power.1291736452 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:07 PM PDT 24 52892918 ps
T620 /workspace/coverage/default/36.pwrmgr_aborted_low_power.3660307224 Jul 31 05:17:38 PM PDT 24 Jul 31 05:17:39 PM PDT 24 22760077 ps
T621 /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4221600750 Jul 31 05:17:16 PM PDT 24 Jul 31 05:17:17 PM PDT 24 60838457 ps
T67 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3043605990 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:14 PM PDT 24 45942222 ps
T19 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1144235052 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:17 PM PDT 24 105505842 ps
T68 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.958680001 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:04 PM PDT 24 23667855 ps
T20 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2854309405 Jul 31 05:11:47 PM PDT 24 Jul 31 05:11:48 PM PDT 24 44926192 ps
T21 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1124830470 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 100161398 ps
T69 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3481174443 Jul 31 05:12:09 PM PDT 24 Jul 31 05:12:09 PM PDT 24 27364859 ps
T191 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1511444253 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:16 PM PDT 24 55682188 ps
T62 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.337200578 Jul 31 05:11:57 PM PDT 24 Jul 31 05:11:58 PM PDT 24 42406413 ps
T55 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.818752440 Jul 31 05:11:56 PM PDT 24 Jul 31 05:11:56 PM PDT 24 63401435 ps
T119 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1671826835 Jul 31 05:12:19 PM PDT 24 Jul 31 05:12:20 PM PDT 24 59553636 ps
T189 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.4047291041 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:04 PM PDT 24 54019201 ps
T192 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3943072151 Jul 31 05:11:48 PM PDT 24 Jul 31 05:11:50 PM PDT 24 197371401 ps
T190 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3879575053 Jul 31 05:11:46 PM PDT 24 Jul 31 05:11:47 PM PDT 24 98177883 ps
T134 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3283119026 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:01 PM PDT 24 21269584 ps
T120 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.612662663 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 68118132 ps
T56 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4078109935 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:04 PM PDT 24 166489091 ps
T193 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1105023998 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:02 PM PDT 24 46306124 ps
T57 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3492262056 Jul 31 05:12:05 PM PDT 24 Jul 31 05:12:06 PM PDT 24 229920293 ps
T60 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1108575201 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 156817461 ps
T90 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3312375896 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:55 PM PDT 24 58881857 ps
T622 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3812725978 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:05 PM PDT 24 18032974 ps
T121 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3738214877 Jul 31 05:12:11 PM PDT 24 Jul 31 05:12:12 PM PDT 24 137496713 ps
T59 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.815753578 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:55 PM PDT 24 29219709 ps
T61 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.376395281 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 79795468 ps
T135 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1290194349 Jul 31 05:11:47 PM PDT 24 Jul 31 05:11:48 PM PDT 24 58064971 ps
T64 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2464157613 Jul 31 05:12:19 PM PDT 24 Jul 31 05:12:20 PM PDT 24 53759253 ps
T623 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.183493639 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 21495899 ps
T65 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1373434907 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:14 PM PDT 24 35523798 ps
T624 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3354362983 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 18771337 ps
T66 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4102942731 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:55 PM PDT 24 99120503 ps
T105 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1710381819 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 19769813 ps
T122 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1991124819 Jul 31 05:12:10 PM PDT 24 Jul 31 05:12:10 PM PDT 24 30353061 ps
T73 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3348397568 Jul 31 05:12:06 PM PDT 24 Jul 31 05:12:07 PM PDT 24 136872771 ps
T137 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.4185788174 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:01 PM PDT 24 123870857 ps
T123 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2707633494 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:13 PM PDT 24 22396412 ps
T625 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3159018619 Jul 31 05:12:28 PM PDT 24 Jul 31 05:12:28 PM PDT 24 38016453 ps
T626 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1480006446 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:57 PM PDT 24 775048110 ps
T627 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.7837603 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 25562830 ps
T628 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1279614992 Jul 31 05:12:06 PM PDT 24 Jul 31 05:12:06 PM PDT 24 23823539 ps
T629 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1298420019 Jul 31 05:12:28 PM PDT 24 Jul 31 05:12:29 PM PDT 24 36248028 ps
T630 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2541627590 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:14 PM PDT 24 347219610 ps
T75 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.938927573 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:01 PM PDT 24 342430214 ps
T631 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2030274916 Jul 31 05:11:59 PM PDT 24 Jul 31 05:11:59 PM PDT 24 26578215 ps
T74 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.968278096 Jul 31 05:11:52 PM PDT 24 Jul 31 05:11:55 PM PDT 24 119974871 ps
T106 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3176568183 Jul 31 05:11:47 PM PDT 24 Jul 31 05:11:48 PM PDT 24 29985058 ps
T632 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2786913078 Jul 31 05:11:53 PM PDT 24 Jul 31 05:11:54 PM PDT 24 58429489 ps
T124 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3258334670 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:01 PM PDT 24 48345483 ps
T149 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.708804385 Jul 31 05:11:45 PM PDT 24 Jul 31 05:11:46 PM PDT 24 318659970 ps
T125 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1508274854 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:08 PM PDT 24 89969839 ps
T107 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1043685867 Jul 31 05:12:24 PM PDT 24 Jul 31 05:12:25 PM PDT 24 22213600 ps
T70 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1521801985 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:05 PM PDT 24 274991563 ps
T108 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3452197470 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:12 PM PDT 24 19949532 ps
T633 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4109739189 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:22 PM PDT 24 97434199 ps
T150 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3689926600 Jul 31 05:12:05 PM PDT 24 Jul 31 05:12:07 PM PDT 24 319843991 ps
T634 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1070479830 Jul 31 05:12:10 PM PDT 24 Jul 31 05:12:11 PM PDT 24 259084418 ps
T635 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2095151409 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:14 PM PDT 24 59700182 ps
T138 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2964289872 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:16 PM PDT 24 204927957 ps
T636 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1289236508 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:15 PM PDT 24 18678399 ps
T637 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.851034735 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:14 PM PDT 24 51189766 ps
T638 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4013268166 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 28745528 ps
T109 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2197077307 Jul 31 05:11:57 PM PDT 24 Jul 31 05:11:58 PM PDT 24 23062180 ps
T639 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1675546248 Jul 31 05:12:25 PM PDT 24 Jul 31 05:12:26 PM PDT 24 20876349 ps
T136 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2251491488 Jul 31 05:11:52 PM PDT 24 Jul 31 05:11:54 PM PDT 24 1048289115 ps
T640 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.245601869 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 36233942 ps
T641 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2511241031 Jul 31 05:12:35 PM PDT 24 Jul 31 05:12:36 PM PDT 24 56117612 ps
T642 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3912999769 Jul 31 05:11:48 PM PDT 24 Jul 31 05:11:49 PM PDT 24 18323812 ps
T643 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3021396144 Jul 31 05:11:56 PM PDT 24 Jul 31 05:11:58 PM PDT 24 45473747 ps
T644 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.705675114 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:15 PM PDT 24 34125779 ps
T645 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2027190358 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:06 PM PDT 24 46252043 ps
T646 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.535743368 Jul 31 05:11:59 PM PDT 24 Jul 31 05:11:59 PM PDT 24 45163121 ps
T110 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2643411970 Jul 31 05:11:48 PM PDT 24 Jul 31 05:11:48 PM PDT 24 25096751 ps
T647 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2830723365 Jul 31 05:11:58 PM PDT 24 Jul 31 05:12:00 PM PDT 24 100726181 ps
T648 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1773998568 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 20631559 ps
T649 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1734485157 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:08 PM PDT 24 26467125 ps
T115 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3697898577 Jul 31 05:11:47 PM PDT 24 Jul 31 05:11:49 PM PDT 24 75110292 ps
T650 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2496458274 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:19 PM PDT 24 75188300 ps
T651 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1806036584 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:05 PM PDT 24 18793069 ps
T652 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.800354856 Jul 31 05:12:10 PM PDT 24 Jul 31 05:12:11 PM PDT 24 105514093 ps
T653 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.665767199 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:16 PM PDT 24 21710520 ps
T111 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3761474495 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:00 PM PDT 24 18564629 ps
T654 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3960203725 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:13 PM PDT 24 41554182 ps
T71 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2329935035 Jul 31 05:11:58 PM PDT 24 Jul 31 05:12:00 PM PDT 24 321866229 ps
T655 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1672843143 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:00 PM PDT 24 289792161 ps
T656 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1317955795 Jul 31 05:12:08 PM PDT 24 Jul 31 05:12:09 PM PDT 24 19132517 ps
T657 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1985179923 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:17 PM PDT 24 41012101 ps
T658 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3619569166 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:04 PM PDT 24 50118082 ps
T659 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3752305633 Jul 31 05:12:08 PM PDT 24 Jul 31 05:12:08 PM PDT 24 26052925 ps
T660 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1301050758 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:08 PM PDT 24 17830467 ps
T661 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2363396324 Jul 31 05:11:56 PM PDT 24 Jul 31 05:11:57 PM PDT 24 93713236 ps
T662 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.851097235 Jul 31 05:12:09 PM PDT 24 Jul 31 05:12:12 PM PDT 24 104974861 ps
T112 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.819812644 Jul 31 05:11:46 PM PDT 24 Jul 31 05:11:47 PM PDT 24 43733845 ps
T113 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.4287525308 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:00 PM PDT 24 17168601 ps
T663 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.689327509 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:54 PM PDT 24 42394876 ps
T664 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.271620078 Jul 31 05:12:22 PM PDT 24 Jul 31 05:12:23 PM PDT 24 30193353 ps
T665 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.342845331 Jul 31 05:11:55 PM PDT 24 Jul 31 05:11:56 PM PDT 24 208925134 ps
T666 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1306944220 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:04 PM PDT 24 31945846 ps
T667 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.203028901 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:01 PM PDT 24 54520637 ps
T668 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3239951674 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 97327635 ps
T669 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2429845100 Jul 31 05:12:09 PM PDT 24 Jul 31 05:12:11 PM PDT 24 736951713 ps
T670 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1995013972 Jul 31 05:11:53 PM PDT 24 Jul 31 05:11:54 PM PDT 24 199585766 ps
T671 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.814599166 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 110755626 ps
T672 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.676367303 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:01 PM PDT 24 133962704 ps
T673 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3062281022 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:16 PM PDT 24 56777509 ps
T674 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3500886540 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:07 PM PDT 24 32296016 ps
T675 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3572366153 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:00 PM PDT 24 18378465 ps
T676 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3059843720 Jul 31 05:12:17 PM PDT 24 Jul 31 05:12:17 PM PDT 24 17711065 ps
T677 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.415546220 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:02 PM PDT 24 35394169 ps
T678 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1717926937 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:39 PM PDT 24 70218371 ps
T679 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2770338768 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:08 PM PDT 24 64487544 ps
T680 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3818514609 Jul 31 05:11:53 PM PDT 24 Jul 31 05:11:54 PM PDT 24 39718288 ps
T681 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2305650899 Jul 31 05:11:55 PM PDT 24 Jul 31 05:11:57 PM PDT 24 95359317 ps
T682 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2396327596 Jul 31 05:11:49 PM PDT 24 Jul 31 05:11:50 PM PDT 24 233675493 ps
T114 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3607152391 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:00 PM PDT 24 77981082 ps
T683 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4113722527 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:08 PM PDT 24 32252023 ps
T684 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3200564502 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:13 PM PDT 24 17600729 ps
T685 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.412722281 Jul 31 05:12:08 PM PDT 24 Jul 31 05:12:09 PM PDT 24 17824799 ps
T686 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1510282183 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:21 PM PDT 24 19130765 ps
T687 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3563713785 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:07 PM PDT 24 26530690 ps
T688 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1006054221 Jul 31 05:11:46 PM PDT 24 Jul 31 05:11:47 PM PDT 24 88284885 ps
T689 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3089201011 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:05 PM PDT 24 101028485 ps
T690 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2036834673 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:17 PM PDT 24 21435080 ps
T691 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3729421609 Jul 31 05:12:06 PM PDT 24 Jul 31 05:12:06 PM PDT 24 19518100 ps
T692 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.4214328569 Jul 31 05:11:57 PM PDT 24 Jul 31 05:11:59 PM PDT 24 420124506 ps
T693 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1161204276 Jul 31 05:11:48 PM PDT 24 Jul 31 05:11:49 PM PDT 24 83264922 ps
T694 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2078000137 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:09 PM PDT 24 155589615 ps
T695 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3996790424 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:04 PM PDT 24 18710061 ps
T696 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4148674213 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:08 PM PDT 24 95961198 ps
T697 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2984477742 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:09 PM PDT 24 51576017 ps
T698 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4025392155 Jul 31 05:12:05 PM PDT 24 Jul 31 05:12:06 PM PDT 24 132310136 ps
T699 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4130992589 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:21 PM PDT 24 26807990 ps
T700 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3459822192 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 42663730 ps
T72 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3532302036 Jul 31 05:12:07 PM PDT 24 Jul 31 05:12:09 PM PDT 24 275552235 ps
T116 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2138599891 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:13 PM PDT 24 42318589 ps
T701 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3382884599 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 329649236 ps
T702 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3041278595 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:15 PM PDT 24 39604968 ps
T703 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3068150313 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:16 PM PDT 24 38317764 ps
T704 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1621197507 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:58 PM PDT 24 20642260 ps
T705 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1261926739 Jul 31 05:11:56 PM PDT 24 Jul 31 05:11:57 PM PDT 24 27397937 ps
T117 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1934309722 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:02 PM PDT 24 47172519 ps
T706 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3011678213 Jul 31 05:12:31 PM PDT 24 Jul 31 05:12:32 PM PDT 24 24877391 ps
T707 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.305741580 Jul 31 05:12:03 PM PDT 24 Jul 31 05:12:03 PM PDT 24 18816338 ps
T708 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2118493372 Jul 31 05:12:00 PM PDT 24 Jul 31 05:12:01 PM PDT 24 36264557 ps
T709 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3191116940 Jul 31 05:11:46 PM PDT 24 Jul 31 05:11:47 PM PDT 24 28298131 ps
T710 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2151628670 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:15 PM PDT 24 57101346 ps
T711 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2337657491 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:04 PM PDT 24 108666185 ps
T712 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1756904619 Jul 31 05:11:52 PM PDT 24 Jul 31 05:11:53 PM PDT 24 22159446 ps
T713 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.637079319 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:00 PM PDT 24 43415776 ps
T714 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2194196010 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:16 PM PDT 24 418397238 ps
T118 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1317351883 Jul 31 05:11:54 PM PDT 24 Jul 31 05:11:54 PM PDT 24 42179823 ps
T715 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3536882519 Jul 31 05:12:01 PM PDT 24 Jul 31 05:12:03 PM PDT 24 228149515 ps
T716 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.195838999 Jul 31 05:11:58 PM PDT 24 Jul 31 05:11:59 PM PDT 24 45058314 ps
T717 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.4235403739 Jul 31 05:11:58 PM PDT 24 Jul 31 05:12:04 PM PDT 24 796918515 ps
T718 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1638385645 Jul 31 05:11:59 PM PDT 24 Jul 31 05:12:00 PM PDT 24 113747840 ps
T719 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1481816532 Jul 31 05:11:49 PM PDT 24 Jul 31 05:11:50 PM PDT 24 29253973 ps
T720 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1913383506 Jul 31 05:11:57 PM PDT 24 Jul 31 05:11:58 PM PDT 24 65798969 ps
T721 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2879202266 Jul 31 05:12:11 PM PDT 24 Jul 31 05:12:12 PM PDT 24 153261550 ps
T722 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.369669172 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:22 PM PDT 24 19490155 ps
T723 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2008662856 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 51983233 ps
T724 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.151805605 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:20 PM PDT 24 46921977 ps
T725 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2912728846 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:13 PM PDT 24 24184240 ps
T726 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3155807194 Jul 31 05:12:18 PM PDT 24 Jul 31 05:12:19 PM PDT 24 20251777 ps
T727 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1095171288 Jul 31 05:12:05 PM PDT 24 Jul 31 05:12:06 PM PDT 24 39155958 ps
T728 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3581290925 Jul 31 05:12:04 PM PDT 24 Jul 31 05:12:04 PM PDT 24 35522390 ps
T729 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2612045639 Jul 31 05:12:02 PM PDT 24 Jul 31 05:12:03 PM PDT 24 63405952 ps
T730 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.364716670 Jul 31 05:12:06 PM PDT 24 Jul 31 05:12:07 PM PDT 24 33973670 ps

Test location /workspace/coverage/default/21.pwrmgr_smoke.1670804332
Short name T4
Test name
Test status
Simulation time 36594923 ps
CPU time 0.65 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 199392 kb
Host smart-df8506f6-9492-451a-a493-dc411fcf3fe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670804332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1670804332
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3766913235
Short name T34
Test name
Test status
Simulation time 150479439 ps
CPU time 0.81 seconds
Started Jul 31 05:15:23 PM PDT 24
Finished Jul 31 05:15:24 PM PDT 24
Peak memory 209444 kb
Host smart-f463ab55-4a0d-44df-9044-f36cc8d42e59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766913235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3766913235
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.655230622
Short name T52
Test name
Test status
Simulation time 47323478 ps
CPU time 0.88 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 200788 kb
Host smart-96224158-d32b-4866-8024-2e5e4c145e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655230622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.655230622
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2020786320
Short name T16
Test name
Test status
Simulation time 883916714 ps
CPU time 1.44 seconds
Started Jul 31 05:15:31 PM PDT 24
Finished Jul 31 05:15:32 PM PDT 24
Peak memory 218044 kb
Host smart-1bf46b06-d38f-4010-b0eb-72142b61c2f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020786320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2020786320
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.818752440
Short name T55
Test name
Test status
Simulation time 63401435 ps
CPU time 0.69 seconds
Started Jul 31 05:11:56 PM PDT 24
Finished Jul 31 05:11:56 PM PDT 24
Peak memory 195220 kb
Host smart-6422c5f6-92ae-43e7-8007-d38247203a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818752440 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.818752440
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2687410618
Short name T41
Test name
Test status
Simulation time 44758366 ps
CPU time 0.69 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 201340 kb
Host smart-9ad3d3a3-0a33-4f42-a6ac-71bf3e9d357b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687410618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2687410618
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.840154078
Short name T2
Test name
Test status
Simulation time 69796708 ps
CPU time 0.64 seconds
Started Jul 31 05:15:56 PM PDT 24
Finished Jul 31 05:15:57 PM PDT 24
Peak memory 198328 kb
Host smart-b0464ea1-34de-4791-80c8-e49ad07c9fd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840154078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.840154078
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.901549619
Short name T43
Test name
Test status
Simulation time 90029049 ps
CPU time 0.92 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:51 PM PDT 24
Peak memory 198404 kb
Host smart-83d2a6ac-a46c-458a-b8de-58149e6d04c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901549619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wak
eup_race.901549619
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.4041457486
Short name T77
Test name
Test status
Simulation time 51748463 ps
CPU time 0.84 seconds
Started Jul 31 05:17:43 PM PDT 24
Finished Jul 31 05:17:44 PM PDT 24
Peak memory 199312 kb
Host smart-8287837a-f643-43f6-8c30-95c377b648e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041457486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4041457486
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3492262056
Short name T57
Test name
Test status
Simulation time 229920293 ps
CPU time 1.05 seconds
Started Jul 31 05:12:05 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 200620 kb
Host smart-0f2f5de7-5e3f-4337-a845-31fa5f779e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492262056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3492262056
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3879086486
Short name T5
Test name
Test status
Simulation time 324611769 ps
CPU time 0.91 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 198016 kb
Host smart-18f89e85-4758-44e3-9cad-bd495b4538ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879086486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3879086486
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.2961758273
Short name T22
Test name
Test status
Simulation time 95081877 ps
CPU time 0.62 seconds
Started Jul 31 05:15:11 PM PDT 24
Finished Jul 31 05:15:12 PM PDT 24
Peak memory 198260 kb
Host smart-0b8b7674-b7b3-4b50-9fb0-4c641ac902b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961758273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2961758273
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.183493639
Short name T623
Test name
Test status
Simulation time 21495899 ps
CPU time 0.63 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 195080 kb
Host smart-a96607e8-27cd-4fad-9b09-6dbca3f43174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183493639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.183493639
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1227338780
Short name T13
Test name
Test status
Simulation time 116798143 ps
CPU time 0.88 seconds
Started Jul 31 05:16:54 PM PDT 24
Finished Jul 31 05:16:55 PM PDT 24
Peak memory 200228 kb
Host smart-b5405e92-83fa-41c2-9e1a-e040d04aa0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227338780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1227338780
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.4085513377
Short name T82
Test name
Test status
Simulation time 75452633 ps
CPU time 0.61 seconds
Started Jul 31 05:16:21 PM PDT 24
Finished Jul 31 05:16:22 PM PDT 24
Peak memory 198556 kb
Host smart-0df8636b-30cf-4ee0-8703-27f60716547e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085513377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.4085513377
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4078109935
Short name T56
Test name
Test status
Simulation time 166489091 ps
CPU time 2.18 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 196332 kb
Host smart-c75c603c-f4be-4d4a-b1f2-42612815028f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078109935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.4078109935
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1710381819
Short name T105
Test name
Test status
Simulation time 19769813 ps
CPU time 0.65 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 195120 kb
Host smart-db72b95f-3fbb-4d30-a087-935e9834b53f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710381819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1710381819
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.828504840
Short name T204
Test name
Test status
Simulation time 63256986 ps
CPU time 0.72 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:02 PM PDT 24
Peak memory 198420 kb
Host smart-a1b1aa89-65d7-4cd8-afb1-76a9ec17e2ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828504840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.828504840
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2311224680
Short name T170
Test name
Test status
Simulation time 87532415 ps
CPU time 0.64 seconds
Started Jul 31 05:15:16 PM PDT 24
Finished Jul 31 05:15:17 PM PDT 24
Peak memory 201372 kb
Host smart-7bcea25f-25f0-43dc-90fe-05d1cbff2ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311224680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2311224680
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.958554
Short name T207
Test name
Test status
Simulation time 78183014 ps
CPU time 0.65 seconds
Started Jul 31 05:17:44 PM PDT 24
Finished Jul 31 05:17:44 PM PDT 24
Peak memory 198280 kb
Host smart-1e48e656-dba3-46fa-bbda-9d38b1b475f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integ
rity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable
_rom_integrity_check.958554
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.1304548557
Short name T165
Test name
Test status
Simulation time 76973720 ps
CPU time 0.7 seconds
Started Jul 31 05:15:13 PM PDT 24
Finished Jul 31 05:15:14 PM PDT 24
Peak memory 201356 kb
Host smart-83380f9e-0580-4f79-876f-c05e923c1382
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304548557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.1304548557
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2913493887
Short name T42
Test name
Test status
Simulation time 66193470 ps
CPU time 0.72 seconds
Started Jul 31 05:17:48 PM PDT 24
Finished Jul 31 05:17:49 PM PDT 24
Peak memory 198644 kb
Host smart-13c32d76-ce96-474a-85fa-338a7dea9333
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913493887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2913493887
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1284860379
Short name T51
Test name
Test status
Simulation time 58140354 ps
CPU time 0.67 seconds
Started Jul 31 05:16:25 PM PDT 24
Finished Jul 31 05:16:26 PM PDT 24
Peak memory 198272 kb
Host smart-da153575-12af-4aaf-a227-a7491f33e010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284860379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1284860379
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.2738404847
Short name T9
Test name
Test status
Simulation time 54196578 ps
CPU time 0.7 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198560 kb
Host smart-13ad20b5-1fb3-450c-820c-2a7d0f370830
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738404847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.2738404847
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3114444201
Short name T155
Test name
Test status
Simulation time 161820219 ps
CPU time 0.66 seconds
Started Jul 31 05:17:32 PM PDT 24
Finished Jul 31 05:17:33 PM PDT 24
Peak memory 201380 kb
Host smart-11119744-fe5c-40b2-968a-f7f3627ddff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114444201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3114444201
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.278479411
Short name T200
Test name
Test status
Simulation time 70094445 ps
CPU time 0.71 seconds
Started Jul 31 05:15:30 PM PDT 24
Finished Jul 31 05:15:31 PM PDT 24
Peak memory 199104 kb
Host smart-f6093ca2-1e64-4ab4-bb86-4bb2e3a1182a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278479411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.278479411
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.2408565721
Short name T209
Test name
Test status
Simulation time 55315796 ps
CPU time 0.61 seconds
Started Jul 31 05:15:53 PM PDT 24
Finished Jul 31 05:15:54 PM PDT 24
Peak memory 198112 kb
Host smart-90c7d182-5c53-41dc-8b20-c96b83d19bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408565721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.2408565721
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2329935035
Short name T71
Test name
Test status
Simulation time 321866229 ps
CPU time 1.55 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 195392 kb
Host smart-06423592-83aa-4cc3-9f3f-a195e7f31d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329935035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2329935035
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3573527806
Short name T45
Test name
Test status
Simulation time 28643676 ps
CPU time 0.65 seconds
Started Jul 31 05:16:29 PM PDT 24
Finished Jul 31 05:16:30 PM PDT 24
Peak memory 198492 kb
Host smart-cb30094e-62c9-4dda-af15-bf943a89bd3b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573527806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.3573527806
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.3110034795
Short name T312
Test name
Test status
Simulation time 36452974 ps
CPU time 0.69 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 199392 kb
Host smart-6aa30853-fea8-45c8-a3c4-580db8acbab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110034795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.3110034795
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3501156796
Short name T178
Test name
Test status
Simulation time 41280558 ps
CPU time 0.71 seconds
Started Jul 31 05:16:27 PM PDT 24
Finished Jul 31 05:16:28 PM PDT 24
Peak memory 201340 kb
Host smart-f28f30e0-8e20-4853-adae-56ae4923320d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501156796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3501156796
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1126175494
Short name T26
Test name
Test status
Simulation time 42471559 ps
CPU time 0.73 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 201036 kb
Host smart-616b59e0-d4b0-4af8-af4b-195ecf84c4b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126175494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1126175494
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.1957579307
Short name T25
Test name
Test status
Simulation time 41907238 ps
CPU time 0.68 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 201204 kb
Host smart-53ccafe7-d5a4-4159-97f3-9895c2602ef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957579307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.1957579307
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.2108105780
Short name T46
Test name
Test status
Simulation time 75901889 ps
CPU time 0.62 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:22 PM PDT 24
Peak memory 198248 kb
Host smart-2b7638ce-e0f8-4f24-96d7-8d515df9b4a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108105780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2108105780
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.1721368317
Short name T184
Test name
Test status
Simulation time 220708248 ps
CPU time 0.66 seconds
Started Jul 31 05:16:23 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 201396 kb
Host smart-13f86def-b75b-4b7c-8e2f-208e8beb3563
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721368317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.1721368317
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2414994116
Short name T497
Test name
Test status
Simulation time 71032045 ps
CPU time 0.66 seconds
Started Jul 31 05:17:50 PM PDT 24
Finished Jul 31 05:17:50 PM PDT 24
Peak memory 198464 kb
Host smart-d5e67357-fe08-455b-90f2-319d6c993851
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414994116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2414994116
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3176568183
Short name T106
Test name
Test status
Simulation time 29985058 ps
CPU time 0.75 seconds
Started Jul 31 05:11:47 PM PDT 24
Finished Jul 31 05:11:48 PM PDT 24
Peak memory 197292 kb
Host smart-71f97cb7-385a-4fd1-ae7e-1c2c8a2d55d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176568183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3
176568183
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3879575053
Short name T190
Test name
Test status
Simulation time 98177883 ps
CPU time 0.63 seconds
Started Jul 31 05:11:46 PM PDT 24
Finished Jul 31 05:11:47 PM PDT 24
Peak memory 194964 kb
Host smart-8bb4e6b2-4817-4529-9cc1-c6d1bdfcda45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879575053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3879575053
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1694467871
Short name T289
Test name
Test status
Simulation time 107773056 ps
CPU time 0.96 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:17 PM PDT 24
Peak memory 209216 kb
Host smart-56806f16-6020-4d63-b999-ac5956ffdbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694467871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1694467871
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.533550862
Short name T157
Test name
Test status
Simulation time 96147091 ps
CPU time 0.68 seconds
Started Jul 31 05:16:44 PM PDT 24
Finished Jul 31 05:16:44 PM PDT 24
Peak memory 201204 kb
Host smart-6a3401d2-0b4a-4627-976d-d4070a97b88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533550862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.533550862
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.36553057
Short name T160
Test name
Test status
Simulation time 71886448 ps
CPU time 0.65 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 201304 kb
Host smart-04388317-f8ac-41f7-9900-c2d25f5c4c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36553057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid
.36553057
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.4036275208
Short name T174
Test name
Test status
Simulation time 105919784 ps
CPU time 0.64 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 201404 kb
Host smart-dc69604d-decb-4027-995a-100c870913f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036275208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.4036275208
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2779447716
Short name T14
Test name
Test status
Simulation time 41770874 ps
CPU time 0.59 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 197448 kb
Host smart-a981c90e-a3ab-4478-956f-67f02413668d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779447716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2779447716
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3697898577
Short name T115
Test name
Test status
Simulation time 75110292 ps
CPU time 2.79 seconds
Started Jul 31 05:11:47 PM PDT 24
Finished Jul 31 05:11:49 PM PDT 24
Peak memory 195260 kb
Host smart-ba8aaf7d-6e49-44b2-81d6-59ef08bd6846
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697898577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
697898577
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.415546220
Short name T677
Test name
Test status
Simulation time 35394169 ps
CPU time 0.67 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 198336 kb
Host smart-03866545-c24c-440b-816f-7dba733005de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415546220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.415546220
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2854309405
Short name T20
Test name
Test status
Simulation time 44926192 ps
CPU time 0.72 seconds
Started Jul 31 05:11:47 PM PDT 24
Finished Jul 31 05:11:48 PM PDT 24
Peak memory 195260 kb
Host smart-f793b32c-3895-4706-8991-a871c06ef0a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854309405 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2854309405
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1481816532
Short name T719
Test name
Test status
Simulation time 29253973 ps
CPU time 0.67 seconds
Started Jul 31 05:11:49 PM PDT 24
Finished Jul 31 05:11:50 PM PDT 24
Peak memory 195052 kb
Host smart-2b898362-2527-4fd5-92e7-9d2f2c4ce2c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481816532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1481816532
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.195838999
Short name T716
Test name
Test status
Simulation time 45058314 ps
CPU time 0.89 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 195148 kb
Host smart-e86f2668-b87f-4e9e-a7a4-7030ecacc9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195838999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.195838999
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3021396144
Short name T643
Test name
Test status
Simulation time 45473747 ps
CPU time 1.91 seconds
Started Jul 31 05:11:56 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 196424 kb
Host smart-fb6370e6-23b6-4fa2-8832-2fe16b2695ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021396144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3021396144
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.708804385
Short name T149
Test name
Test status
Simulation time 318659970 ps
CPU time 1.37 seconds
Started Jul 31 05:11:45 PM PDT 24
Finished Jul 31 05:11:46 PM PDT 24
Peak memory 200564 kb
Host smart-672bcb12-cb35-44f6-a673-04ba16640590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708804385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
708804385
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3191116940
Short name T709
Test name
Test status
Simulation time 28298131 ps
CPU time 1 seconds
Started Jul 31 05:11:46 PM PDT 24
Finished Jul 31 05:11:47 PM PDT 24
Peak memory 198508 kb
Host smart-384b3f27-cc1c-4c68-8764-8f43fafe5a4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191116940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
191116940
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3943072151
Short name T192
Test name
Test status
Simulation time 197371401 ps
CPU time 1.65 seconds
Started Jul 31 05:11:48 PM PDT 24
Finished Jul 31 05:11:50 PM PDT 24
Peak memory 195280 kb
Host smart-81b1aa15-8225-4cef-b1e0-6f5bbdfb5895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943072151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
943072151
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1290194349
Short name T135
Test name
Test status
Simulation time 58064971 ps
CPU time 0.68 seconds
Started Jul 31 05:11:47 PM PDT 24
Finished Jul 31 05:11:48 PM PDT 24
Peak memory 197256 kb
Host smart-8eb15ac1-fd41-493e-853a-dfc65881bdc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290194349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1
290194349
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.819812644
Short name T112
Test name
Test status
Simulation time 43733845 ps
CPU time 0.66 seconds
Started Jul 31 05:11:46 PM PDT 24
Finished Jul 31 05:11:47 PM PDT 24
Peak memory 197324 kb
Host smart-6931125f-c320-4dd6-b7e4-a00250f4a2ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819812644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.819812644
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.689327509
Short name T663
Test name
Test status
Simulation time 42394876 ps
CPU time 0.59 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 195044 kb
Host smart-c33d14a3-e041-4ca6-a9f5-1ae8b897f651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689327509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.689327509
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.535743368
Short name T646
Test name
Test status
Simulation time 45163121 ps
CPU time 0.67 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 197352 kb
Host smart-1c02d8d8-f58b-42ba-99a0-9d3b5f185aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535743368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.535743368
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1161204276
Short name T693
Test name
Test status
Simulation time 83264922 ps
CPU time 1.24 seconds
Started Jul 31 05:11:48 PM PDT 24
Finished Jul 31 05:11:49 PM PDT 24
Peak memory 200736 kb
Host smart-4ce6cb06-39b5-494a-b96b-587101988807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161204276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.1161204276
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1006054221
Short name T688
Test name
Test status
Simulation time 88284885 ps
CPU time 1.12 seconds
Started Jul 31 05:11:46 PM PDT 24
Finished Jul 31 05:11:47 PM PDT 24
Peak memory 195184 kb
Host smart-7b481732-b2fa-42d4-9ccc-8be858f9489b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006054221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1006054221
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.938927573
Short name T75
Test name
Test status
Simulation time 342430214 ps
CPU time 0.9 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 195292 kb
Host smart-1bcc40e1-1a4d-458b-9881-6a6fc5c06ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938927573 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.938927573
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.305741580
Short name T707
Test name
Test status
Simulation time 18816338 ps
CPU time 0.66 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 197304 kb
Host smart-d6ad4bf7-f946-4352-8058-c6d4a03e6347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305741580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.305741580
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.412722281
Short name T685
Test name
Test status
Simulation time 17824799 ps
CPU time 0.6 seconds
Started Jul 31 05:12:08 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 195092 kb
Host smart-9bfa6c14-c081-45ff-916e-7e34cae193a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412722281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.412722281
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4148674213
Short name T696
Test name
Test status
Simulation time 95961198 ps
CPU time 0.84 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 198736 kb
Host smart-6bceb3f4-6b50-4c2c-af56-cbfdddbafd73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148674213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.4148674213
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.851097235
Short name T662
Test name
Test status
Simulation time 104974861 ps
CPU time 2.2 seconds
Started Jul 31 05:12:09 PM PDT 24
Finished Jul 31 05:12:12 PM PDT 24
Peak memory 196328 kb
Host smart-dc46a314-1133-4472-a8fe-d865778dae65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851097235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.851097235
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2429845100
Short name T669
Test name
Test status
Simulation time 736951713 ps
CPU time 1.04 seconds
Started Jul 31 05:12:09 PM PDT 24
Finished Jul 31 05:12:11 PM PDT 24
Peak memory 200344 kb
Host smart-76148cad-6c97-44b9-a03a-dbfde16b7327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429845100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2429845100
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2008662856
Short name T723
Test name
Test status
Simulation time 51983233 ps
CPU time 0.81 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 200572 kb
Host smart-3ec37780-3b82-4f4f-8bf8-95a6712db521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008662856 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.2008662856
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3996790424
Short name T695
Test name
Test status
Simulation time 18710061 ps
CPU time 0.66 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 197304 kb
Host smart-db8e3073-75a6-4136-9a86-42ce462d5232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996790424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3996790424
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1279614992
Short name T628
Test name
Test status
Simulation time 23823539 ps
CPU time 0.61 seconds
Started Jul 31 05:12:06 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 195040 kb
Host smart-cf4f3908-c5ff-46bf-bfbe-b10aa08cbf3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279614992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1279614992
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3382884599
Short name T701
Test name
Test status
Simulation time 329649236 ps
CPU time 0.87 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 198528 kb
Host smart-163684e8-58d6-42ff-92b2-97c8296fbfcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382884599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3382884599
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2078000137
Short name T694
Test name
Test status
Simulation time 155589615 ps
CPU time 1.08 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 195456 kb
Host smart-142c43a7-9d58-45ad-81c8-ecc7c9bf8be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078000137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2078000137
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1108575201
Short name T60
Test name
Test status
Simulation time 156817461 ps
CPU time 1.16 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 195436 kb
Host smart-4344e5fc-5a5c-41fa-87d3-9a944e8c5608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108575201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1108575201
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1144235052
Short name T19
Test name
Test status
Simulation time 105505842 ps
CPU time 1.15 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 197424 kb
Host smart-1c299a72-547b-4d89-8e55-4e14672a59a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144235052 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1144235052
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1934309722
Short name T117
Test name
Test status
Simulation time 47172519 ps
CPU time 0.62 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 196956 kb
Host smart-9b959afc-2102-48e5-adb9-aa5d4ff888aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934309722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1934309722
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3581290925
Short name T728
Test name
Test status
Simulation time 35522390 ps
CPU time 0.6 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 195036 kb
Host smart-924162ad-62ac-4452-918a-ffd1e777a041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581290925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3581290925
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3258334670
Short name T124
Test name
Test status
Simulation time 48345483 ps
CPU time 0.74 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 197344 kb
Host smart-b2769620-4376-4b31-b314-5789c69e1500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258334670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3258334670
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2194196010
Short name T714
Test name
Test status
Simulation time 418397238 ps
CPU time 2.57 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 197388 kb
Host smart-c094f5f4-0ac9-4350-8175-2cac10585e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194196010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2194196010
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4025392155
Short name T698
Test name
Test status
Simulation time 132310136 ps
CPU time 1.04 seconds
Started Jul 31 05:12:05 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 199800 kb
Host smart-96f0485f-5e8a-4c6d-8968-251b20f8f1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025392155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.4025392155
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2770338768
Short name T679
Test name
Test status
Simulation time 64487544 ps
CPU time 0.72 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 195288 kb
Host smart-e8178bf1-3293-491a-b6f6-ea653a318dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770338768 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.2770338768
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.705675114
Short name T644
Test name
Test status
Simulation time 34125779 ps
CPU time 0.6 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:15 PM PDT 24
Peak memory 195128 kb
Host smart-5907629d-f4de-4afc-a251-4743c6ef26a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705675114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.705675114
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.7837603
Short name T627
Test name
Test status
Simulation time 25562830 ps
CPU time 0.61 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 194960 kb
Host smart-61158d02-e002-4e23-b3d2-9c17d2b04f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7837603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.7837603
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3738214877
Short name T121
Test name
Test status
Simulation time 137496713 ps
CPU time 0.85 seconds
Started Jul 31 05:12:11 PM PDT 24
Finished Jul 31 05:12:12 PM PDT 24
Peak memory 195088 kb
Host smart-c2abaae5-f5cf-46ea-878b-11c4c71d8224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738214877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3738214877
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3089201011
Short name T689
Test name
Test status
Simulation time 101028485 ps
CPU time 1.82 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:05 PM PDT 24
Peak memory 196440 kb
Host smart-73e42f0d-39d0-4e16-9eb2-2246ad4262ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089201011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3089201011
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1672843143
Short name T655
Test name
Test status
Simulation time 289792161 ps
CPU time 1.12 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 195580 kb
Host smart-febdf871-2df0-4cef-856a-034f97bd363c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672843143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1672843143
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3239951674
Short name T668
Test name
Test status
Simulation time 97327635 ps
CPU time 0.8 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 195304 kb
Host smart-61bfd95b-2b81-4ced-af89-a3792546d254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239951674 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.3239951674
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2197077307
Short name T109
Test name
Test status
Simulation time 23062180 ps
CPU time 0.69 seconds
Started Jul 31 05:11:57 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 195108 kb
Host smart-6f8b9f91-c157-4826-8c5c-3e3f8a271a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197077307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.2197077307
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3354362983
Short name T624
Test name
Test status
Simulation time 18771337 ps
CPU time 0.62 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 195068 kb
Host smart-e6a6bef8-c2e6-4cc5-9f21-98af398601e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354362983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3354362983
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2095151409
Short name T635
Test name
Test status
Simulation time 59700182 ps
CPU time 0.76 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:14 PM PDT 24
Peak memory 198344 kb
Host smart-d51bf057-e2be-4d5e-b8dc-c7db1d48d0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095151409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2095151409
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3532302036
Short name T72
Test name
Test status
Simulation time 275552235 ps
CPU time 1.14 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 200660 kb
Host smart-454d316c-c902-41e9-a64c-9367a3fa14b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532302036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3532302036
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2511241031
Short name T641
Test name
Test status
Simulation time 56117612 ps
CPU time 1.07 seconds
Started Jul 31 05:12:35 PM PDT 24
Finished Jul 31 05:12:36 PM PDT 24
Peak memory 200600 kb
Host smart-b8c73788-8e85-42d4-b100-6a4956b4116e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511241031 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2511241031
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3452197470
Short name T108
Test name
Test status
Simulation time 19949532 ps
CPU time 0.65 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:12 PM PDT 24
Peak memory 195120 kb
Host smart-2a70c803-052a-4e4e-8966-40beda363677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452197470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3452197470
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3062281022
Short name T673
Test name
Test status
Simulation time 56777509 ps
CPU time 0.64 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 195036 kb
Host smart-589c3fd6-f543-47ed-8466-95ab98f85b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062281022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3062281022
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1985179923
Short name T657
Test name
Test status
Simulation time 41012101 ps
CPU time 0.91 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 198416 kb
Host smart-28ec4c90-c123-4ec3-8714-60396c986880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985179923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1985179923
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1373434907
Short name T65
Test name
Test status
Simulation time 35523798 ps
CPU time 1.55 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:14 PM PDT 24
Peak memory 196544 kb
Host smart-437d5dc8-360f-4996-ba21-392195897c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373434907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1373434907
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3689926600
Short name T150
Test name
Test status
Simulation time 319843991 ps
CPU time 1.49 seconds
Started Jul 31 05:12:05 PM PDT 24
Finished Jul 31 05:12:07 PM PDT 24
Peak memory 195364 kb
Host smart-2df8ca52-a96f-44ba-b3ff-fa9c2a908f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689926600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3689926600
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1717926937
Short name T678
Test name
Test status
Simulation time 70218371 ps
CPU time 1.09 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:39 PM PDT 24
Peak memory 200572 kb
Host smart-14ec5041-3f62-44ad-b4f2-8d48b1f1db70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717926937 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.1717926937
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2138599891
Short name T116
Test name
Test status
Simulation time 42318589 ps
CPU time 0.59 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 198320 kb
Host smart-e16eb2ce-dda1-4f78-8387-ea8812372c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138599891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2138599891
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3043605990
Short name T67
Test name
Test status
Simulation time 45942222 ps
CPU time 0.59 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:14 PM PDT 24
Peak memory 195032 kb
Host smart-136e6f38-c693-4257-b046-4e69b227942c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043605990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3043605990
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.271620078
Short name T664
Test name
Test status
Simulation time 30193353 ps
CPU time 0.68 seconds
Started Jul 31 05:12:22 PM PDT 24
Finished Jul 31 05:12:23 PM PDT 24
Peak memory 197540 kb
Host smart-012597b5-64f9-4ef6-ba96-2d81aee2a6c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271620078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.271620078
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.968278096
Short name T74
Test name
Test status
Simulation time 119974871 ps
CPU time 2.33 seconds
Started Jul 31 05:11:52 PM PDT 24
Finished Jul 31 05:11:55 PM PDT 24
Peak memory 196424 kb
Host smart-a325b678-5d6e-40f6-a8bc-4c4b6fb8f77b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968278096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.968278096
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4113722527
Short name T683
Test name
Test status
Simulation time 32252023 ps
CPU time 0.78 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 195244 kb
Host smart-a2a2a0b5-f21e-48cf-824f-a8926b184664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113722527 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.4113722527
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1043685867
Short name T107
Test name
Test status
Simulation time 22213600 ps
CPU time 0.67 seconds
Started Jul 31 05:12:24 PM PDT 24
Finished Jul 31 05:12:25 PM PDT 24
Peak memory 195076 kb
Host smart-a114a8d3-7711-47b7-aca2-cc9b666c7553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043685867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1043685867
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1317955795
Short name T656
Test name
Test status
Simulation time 19132517 ps
CPU time 0.6 seconds
Started Jul 31 05:12:08 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 194996 kb
Host smart-6d58e278-1e97-441d-8ca1-13bb91af9032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317955795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1317955795
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2151628670
Short name T710
Test name
Test status
Simulation time 57101346 ps
CPU time 0.71 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:15 PM PDT 24
Peak memory 195124 kb
Host smart-72942e10-37af-4792-bb43-276add7811b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151628670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2151628670
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1306944220
Short name T666
Test name
Test status
Simulation time 31945846 ps
CPU time 1.35 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 196432 kb
Host smart-f8a5a540-92f6-4730-83de-855a175849b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306944220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1306944220
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3348397568
Short name T73
Test name
Test status
Simulation time 136872771 ps
CPU time 1.06 seconds
Started Jul 31 05:12:06 PM PDT 24
Finished Jul 31 05:12:07 PM PDT 24
Peak memory 200448 kb
Host smart-49a39632-1908-4d6e-9155-bace85b1c029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348397568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3348397568
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2612045639
Short name T729
Test name
Test status
Simulation time 63405952 ps
CPU time 0.97 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 195284 kb
Host smart-1cef6fd6-d2bb-4d8c-8f48-751452d49bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612045639 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2612045639
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3283119026
Short name T134
Test name
Test status
Simulation time 21269584 ps
CPU time 0.65 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 195096 kb
Host smart-6d9bf8f3-1645-4cba-9aa0-455751c99f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283119026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3283119026
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1095171288
Short name T727
Test name
Test status
Simulation time 39155958 ps
CPU time 0.59 seconds
Started Jul 31 05:12:05 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 195016 kb
Host smart-baa54007-0749-433d-b818-73ac1d066f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095171288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1095171288
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1734485157
Short name T649
Test name
Test status
Simulation time 26467125 ps
CPU time 0.71 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 195096 kb
Host smart-1673dad8-7d18-4a15-88fe-7a9c322d8b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734485157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.1734485157
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4109739189
Short name T633
Test name
Test status
Simulation time 97434199 ps
CPU time 1.99 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:22 PM PDT 24
Peak memory 196356 kb
Host smart-c3cf04bd-1f13-40dc-aba3-6a01197e4662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109739189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.4109739189
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1521801985
Short name T70
Test name
Test status
Simulation time 274991563 ps
CPU time 1.52 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:05 PM PDT 24
Peak memory 195344 kb
Host smart-b9960cf0-81dd-44e2-b6f0-a63717516450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521801985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.1521801985
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2496458274
Short name T650
Test name
Test status
Simulation time 75188300 ps
CPU time 1.2 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:19 PM PDT 24
Peak memory 195256 kb
Host smart-3f25d9f4-b216-4a63-b3c6-31d7535ce9c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496458274 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2496458274
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2707633494
Short name T123
Test name
Test status
Simulation time 22396412 ps
CPU time 0.61 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 198300 kb
Host smart-5df03f2d-eb79-4322-8255-c1156b5888f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707633494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2707633494
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4130992589
Short name T699
Test name
Test status
Simulation time 26807990 ps
CPU time 0.61 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:21 PM PDT 24
Peak memory 195040 kb
Host smart-e6d81e8c-0ba0-47ac-b9cd-08b153e77549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130992589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4130992589
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1508274854
Short name T125
Test name
Test status
Simulation time 89969839 ps
CPU time 0.73 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 197364 kb
Host smart-9dbed592-dbb3-4f60-88c7-3780af2cabee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508274854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1508274854
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.203028901
Short name T667
Test name
Test status
Simulation time 54520637 ps
CPU time 1.23 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 195704 kb
Host smart-0a1f970c-ceec-4b27-a26b-5861b2c7ce14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203028901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.203028901
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1124830470
Short name T21
Test name
Test status
Simulation time 100161398 ps
CPU time 1.11 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 195196 kb
Host smart-2c5e4aca-d70a-4bf2-b668-88c0dbb639a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124830470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1124830470
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2643411970
Short name T110
Test name
Test status
Simulation time 25096751 ps
CPU time 0.75 seconds
Started Jul 31 05:11:48 PM PDT 24
Finished Jul 31 05:11:48 PM PDT 24
Peak memory 195048 kb
Host smart-828f71e3-843a-4ab1-80a9-040260510a96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643411970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
643411970
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1480006446
Short name T626
Test name
Test status
Simulation time 775048110 ps
CPU time 3.09 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:57 PM PDT 24
Peak memory 195280 kb
Host smart-e3338378-72f4-486d-b800-8388b2f116ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480006446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1
480006446
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.245601869
Short name T640
Test name
Test status
Simulation time 36233942 ps
CPU time 0.64 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 198324 kb
Host smart-bd9dc72c-41cd-4db2-86fe-082882da1f8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245601869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.245601869
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2786913078
Short name T632
Test name
Test status
Simulation time 58429489 ps
CPU time 0.88 seconds
Started Jul 31 05:11:53 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 200548 kb
Host smart-1fcda46c-a118-4129-a4e8-25483b7a896f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786913078 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.2786913078
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2396327596
Short name T682
Test name
Test status
Simulation time 233675493 ps
CPU time 0.66 seconds
Started Jul 31 05:11:49 PM PDT 24
Finished Jul 31 05:11:50 PM PDT 24
Peak memory 195064 kb
Host smart-515062a0-0e43-48bc-9df3-d5906bf7fca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396327596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2396327596
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3912999769
Short name T642
Test name
Test status
Simulation time 18323812 ps
CPU time 0.61 seconds
Started Jul 31 05:11:48 PM PDT 24
Finished Jul 31 05:11:49 PM PDT 24
Peak memory 195048 kb
Host smart-373a5e6b-7aa0-4e28-81a8-fad42362d2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912999769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3912999769
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3818514609
Short name T680
Test name
Test status
Simulation time 39718288 ps
CPU time 0.74 seconds
Started Jul 31 05:11:53 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 198708 kb
Host smart-40654099-c732-4bf6-9faf-e0e79c8047ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818514609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3818514609
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.4185788174
Short name T137
Test name
Test status
Simulation time 123870857 ps
CPU time 1.5 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 196400 kb
Host smart-deebd1d4-d08a-42c5-a35b-dd09fe749339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185788174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.4185788174
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1070479830
Short name T634
Test name
Test status
Simulation time 259084418 ps
CPU time 1.65 seconds
Started Jul 31 05:12:10 PM PDT 24
Finished Jul 31 05:12:11 PM PDT 24
Peak memory 200632 kb
Host smart-9a67cda6-5f24-4671-9955-08e9154e87b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070479830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1070479830
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3729421609
Short name T691
Test name
Test status
Simulation time 19518100 ps
CPU time 0.61 seconds
Started Jul 31 05:12:06 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 195060 kb
Host smart-bfc89dd7-b489-4bdb-8b84-4ccd1699bf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729421609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3729421609
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3960203725
Short name T654
Test name
Test status
Simulation time 41554182 ps
CPU time 0.57 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 195008 kb
Host smart-9dee2811-644c-405f-a55a-87d7f8092111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960203725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3960203725
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2036834673
Short name T690
Test name
Test status
Simulation time 21435080 ps
CPU time 0.57 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 195008 kb
Host smart-42ff8dbe-8ad8-43f9-8d17-4494cf4afdb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036834673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2036834673
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.665767199
Short name T653
Test name
Test status
Simulation time 21710520 ps
CPU time 0.58 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 195044 kb
Host smart-6b56c2bf-8c19-4dc0-9509-a99af8a13743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665767199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.665767199
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.958680001
Short name T68
Test name
Test status
Simulation time 23667855 ps
CPU time 0.64 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 195088 kb
Host smart-aea14988-b7c1-44b6-9e10-142399f97980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958680001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.958680001
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3563713785
Short name T687
Test name
Test status
Simulation time 26530690 ps
CPU time 0.6 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:07 PM PDT 24
Peak memory 195068 kb
Host smart-a905e133-0b75-4863-bd93-7ace4b042ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563713785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3563713785
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3752305633
Short name T659
Test name
Test status
Simulation time 26052925 ps
CPU time 0.62 seconds
Started Jul 31 05:12:08 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 195084 kb
Host smart-3c9b10ed-3c65-43a3-a9d2-05cdaee55a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752305633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3752305633
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3459822192
Short name T700
Test name
Test status
Simulation time 42663730 ps
CPU time 0.63 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 194972 kb
Host smart-2b8ed1cb-0bcd-442d-a14c-5a92ada5591a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459822192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3459822192
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3041278595
Short name T702
Test name
Test status
Simulation time 39604968 ps
CPU time 0.6 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:15 PM PDT 24
Peak memory 195048 kb
Host smart-fea98cdb-cdfd-4f45-a796-1aa2c41b0b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041278595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3041278595
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3607152391
Short name T114
Test name
Test status
Simulation time 77981082 ps
CPU time 0.98 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 195032 kb
Host smart-9e24b640-9681-4d8e-bd34-0c0d9a33007c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607152391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
607152391
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2027190358
Short name T645
Test name
Test status
Simulation time 46252043 ps
CPU time 1.67 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 195264 kb
Host smart-0ade9513-bc57-43c8-a516-74edfcb3c07d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027190358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
027190358
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1317351883
Short name T118
Test name
Test status
Simulation time 42179823 ps
CPU time 0.61 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 195108 kb
Host smart-2a7b3dab-107d-42d5-9889-618b22b4dc35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317351883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1
317351883
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2118493372
Short name T708
Test name
Test status
Simulation time 36264557 ps
CPU time 0.78 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 195272 kb
Host smart-63cf4fe8-355c-451b-aff6-d749d9d62a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118493372 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2118493372
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1773998568
Short name T648
Test name
Test status
Simulation time 20631559 ps
CPU time 0.63 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 197328 kb
Host smart-31bff87a-37fd-4259-9e9f-8e60a3c670e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773998568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1773998568
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3500886540
Short name T674
Test name
Test status
Simulation time 32296016 ps
CPU time 0.64 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:07 PM PDT 24
Peak memory 194976 kb
Host smart-fc83e727-00b0-4396-b349-7eb4214a6dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500886540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3500886540
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.637079319
Short name T713
Test name
Test status
Simulation time 43415776 ps
CPU time 0.7 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 197396 kb
Host smart-c460e2ab-a309-47fb-8c3a-590d94f1152e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637079319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.637079319
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2541627590
Short name T630
Test name
Test status
Simulation time 347219610 ps
CPU time 2.02 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:14 PM PDT 24
Peak memory 196416 kb
Host smart-c60ccb24-3386-47e1-b55c-4883992f40de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541627590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2541627590
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.342845331
Short name T665
Test name
Test status
Simulation time 208925134 ps
CPU time 1.06 seconds
Started Jul 31 05:11:55 PM PDT 24
Finished Jul 31 05:11:56 PM PDT 24
Peak memory 200312 kb
Host smart-050fc7fb-8380-4013-8807-52e6269e8ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342845331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.
342845331
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3572366153
Short name T675
Test name
Test status
Simulation time 18378465 ps
CPU time 0.6 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 194960 kb
Host smart-aaa37192-b355-458e-8786-1884059a4766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572366153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3572366153
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3200564502
Short name T684
Test name
Test status
Simulation time 17600729 ps
CPU time 0.61 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 195060 kb
Host smart-6aefba6d-e141-4286-bc09-2cf75c792223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200564502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3200564502
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.151805605
Short name T724
Test name
Test status
Simulation time 46921977 ps
CPU time 0.59 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 195108 kb
Host smart-4fb1192e-32e9-4960-8a90-09530fa25e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151805605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.151805605
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3011678213
Short name T706
Test name
Test status
Simulation time 24877391 ps
CPU time 0.57 seconds
Started Jul 31 05:12:31 PM PDT 24
Finished Jul 31 05:12:32 PM PDT 24
Peak memory 195056 kb
Host smart-494f38aa-5002-4cdb-8397-a6a8d564cbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011678213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3011678213
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3159018619
Short name T625
Test name
Test status
Simulation time 38016453 ps
CPU time 0.59 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:12:28 PM PDT 24
Peak memory 195084 kb
Host smart-3daf9e50-1e96-4834-acad-83f91f61ebe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159018619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3159018619
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1301050758
Short name T660
Test name
Test status
Simulation time 17830467 ps
CPU time 0.59 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:08 PM PDT 24
Peak memory 195084 kb
Host smart-83d12498-8efb-4793-9a53-c23e3ca0b24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301050758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1301050758
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3059843720
Short name T676
Test name
Test status
Simulation time 17711065 ps
CPU time 0.6 seconds
Started Jul 31 05:12:17 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 195032 kb
Host smart-a2b6fb87-0c3d-49d5-a6e6-f27fc79f6d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059843720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3059843720
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2879202266
Short name T721
Test name
Test status
Simulation time 153261550 ps
CPU time 0.63 seconds
Started Jul 31 05:12:11 PM PDT 24
Finished Jul 31 05:12:12 PM PDT 24
Peak memory 195048 kb
Host smart-7f628b7d-6cc4-41ea-a90a-612aa6c88c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879202266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2879202266
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3812725978
Short name T622
Test name
Test status
Simulation time 18032974 ps
CPU time 0.61 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:05 PM PDT 24
Peak memory 194960 kb
Host smart-c5e3a1b3-21e1-4180-90e3-33e845cacd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812725978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3812725978
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1675546248
Short name T639
Test name
Test status
Simulation time 20876349 ps
CPU time 0.62 seconds
Started Jul 31 05:12:25 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 195028 kb
Host smart-97997d98-d165-4174-b601-c7cb848ba143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675546248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1675546248
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.337200578
Short name T62
Test name
Test status
Simulation time 42406413 ps
CPU time 1 seconds
Started Jul 31 05:11:57 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 195056 kb
Host smart-cb9fbdbe-fdf0-45ec-99ce-6baf85cb6632
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337200578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.337200578
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1105023998
Short name T193
Test name
Test status
Simulation time 46306124 ps
CPU time 1.71 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 195220 kb
Host smart-eacd278f-524f-4e86-8cc8-9dc0be0be58e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105023998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
105023998
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1261926739
Short name T705
Test name
Test status
Simulation time 27397937 ps
CPU time 0.65 seconds
Started Jul 31 05:11:56 PM PDT 24
Finished Jul 31 05:11:57 PM PDT 24
Peak memory 198344 kb
Host smart-8b5ab71e-8c5a-47db-813f-acaca46c8e0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261926739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
261926739
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3312375896
Short name T90
Test name
Test status
Simulation time 58881857 ps
CPU time 1.06 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:55 PM PDT 24
Peak memory 196212 kb
Host smart-88280894-b2e3-4ad1-8789-42354956da85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312375896 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3312375896
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1991124819
Short name T122
Test name
Test status
Simulation time 30353061 ps
CPU time 0.58 seconds
Started Jul 31 05:12:10 PM PDT 24
Finished Jul 31 05:12:10 PM PDT 24
Peak memory 195128 kb
Host smart-da86a6da-ef7a-4395-ba0f-ab7d89b79255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991124819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1991124819
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1756904619
Short name T712
Test name
Test status
Simulation time 22159446 ps
CPU time 0.61 seconds
Started Jul 31 05:11:52 PM PDT 24
Finished Jul 31 05:11:53 PM PDT 24
Peak memory 195028 kb
Host smart-88cbe84d-5f4f-415c-98d8-33d632cdb46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756904619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1756904619
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1913383506
Short name T720
Test name
Test status
Simulation time 65798969 ps
CPU time 0.8 seconds
Started Jul 31 05:11:57 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 198616 kb
Host smart-9f5658ab-2599-4ebc-a73d-ba32e0ecebe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913383506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1913383506
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.815753578
Short name T59
Test name
Test status
Simulation time 29219709 ps
CPU time 1.21 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:55 PM PDT 24
Peak memory 196404 kb
Host smart-796e711c-c685-40eb-9e10-35cb343bcdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815753578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.815753578
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1995013972
Short name T670
Test name
Test status
Simulation time 199585766 ps
CPU time 1.04 seconds
Started Jul 31 05:11:53 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 199744 kb
Host smart-00408f0c-f1a8-4f98-9d71-32befb0f8545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995013972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1995013972
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.364716670
Short name T730
Test name
Test status
Simulation time 33973670 ps
CPU time 0.57 seconds
Started Jul 31 05:12:06 PM PDT 24
Finished Jul 31 05:12:07 PM PDT 24
Peak memory 195032 kb
Host smart-48a39a3c-0729-4ebc-9cab-2cc01ae69e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364716670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.364716670
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.369669172
Short name T722
Test name
Test status
Simulation time 19490155 ps
CPU time 0.61 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:22 PM PDT 24
Peak memory 195028 kb
Host smart-b134f104-3c64-41d8-b661-eda19e2f9b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369669172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.369669172
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2912728846
Short name T725
Test name
Test status
Simulation time 24184240 ps
CPU time 0.58 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 195064 kb
Host smart-0e1566ac-87ca-4564-ac7d-636b0148235c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912728846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.2912728846
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3155807194
Short name T726
Test name
Test status
Simulation time 20251777 ps
CPU time 0.62 seconds
Started Jul 31 05:12:18 PM PDT 24
Finished Jul 31 05:12:19 PM PDT 24
Peak memory 195028 kb
Host smart-6518a543-8d78-4c94-a820-6a0364d61761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155807194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.3155807194
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3068150313
Short name T703
Test name
Test status
Simulation time 38317764 ps
CPU time 0.58 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 195092 kb
Host smart-71d3d727-f436-4d8a-b826-495842c35b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068150313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3068150313
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1510282183
Short name T686
Test name
Test status
Simulation time 19130765 ps
CPU time 0.6 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:21 PM PDT 24
Peak memory 195012 kb
Host smart-a5beb9be-36fe-4181-88f6-5d1ab31eb2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510282183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1510282183
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.851034735
Short name T637
Test name
Test status
Simulation time 51189766 ps
CPU time 0.6 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:14 PM PDT 24
Peak memory 195044 kb
Host smart-36bdae40-08ff-40b1-a7d6-be142f86b566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851034735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.851034735
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1511444253
Short name T191
Test name
Test status
Simulation time 55682188 ps
CPU time 0.62 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 195012 kb
Host smart-5a5545f7-f0f5-41dd-8660-724d06c009f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511444253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1511444253
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1298420019
Short name T629
Test name
Test status
Simulation time 36248028 ps
CPU time 0.64 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:12:29 PM PDT 24
Peak memory 195036 kb
Host smart-70c7ecaf-fc55-4fba-a658-6a5a44a29d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298420019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1298420019
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1289236508
Short name T636
Test name
Test status
Simulation time 18678399 ps
CPU time 0.6 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:15 PM PDT 24
Peak memory 195068 kb
Host smart-35167f87-4d34-4efc-ac85-b2d01c424074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289236508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1289236508
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.376395281
Short name T61
Test name
Test status
Simulation time 79795468 ps
CPU time 0.98 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 196184 kb
Host smart-e7ce74e8-c46e-4954-9ce3-dae793f15359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376395281 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.376395281
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3761474495
Short name T111
Test name
Test status
Simulation time 18564629 ps
CPU time 0.65 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 197304 kb
Host smart-cba93fea-2024-4fc8-9cc5-f691fb1b4e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761474495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3761474495
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2030274916
Short name T631
Test name
Test status
Simulation time 26578215 ps
CPU time 0.6 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 194976 kb
Host smart-57719c39-8040-4999-8bb3-fdb0ded0c239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030274916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2030274916
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1671826835
Short name T119
Test name
Test status
Simulation time 59553636 ps
CPU time 0.82 seconds
Started Jul 31 05:12:19 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 198716 kb
Host smart-f106e5d5-2ac3-44f4-9abc-2ccb866a07a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671826835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.1671826835
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.4214328569
Short name T692
Test name
Test status
Simulation time 420124506 ps
CPU time 2.03 seconds
Started Jul 31 05:11:57 PM PDT 24
Finished Jul 31 05:11:59 PM PDT 24
Peak memory 197392 kb
Host smart-ac2d9b6b-71dc-414b-9657-9eaee34b368c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214328569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.4214328569
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.814599166
Short name T671
Test name
Test status
Simulation time 110755626 ps
CPU time 0.83 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 195220 kb
Host smart-c5b09959-c479-4c96-9c15-9f024a8bd37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814599166 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.814599166
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3481174443
Short name T69
Test name
Test status
Simulation time 27364859 ps
CPU time 0.62 seconds
Started Jul 31 05:12:09 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 195068 kb
Host smart-15a83939-afd0-48fe-831d-c8c602a94467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481174443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3481174443
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.676367303
Short name T672
Test name
Test status
Simulation time 133962704 ps
CPU time 0.91 seconds
Started Jul 31 05:12:00 PM PDT 24
Finished Jul 31 05:12:01 PM PDT 24
Peak memory 195048 kb
Host smart-55257e0d-50b2-4e21-9048-a882387fbfb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676367303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.676367303
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2464157613
Short name T64
Test name
Test status
Simulation time 53759253 ps
CPU time 1.27 seconds
Started Jul 31 05:12:19 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 196376 kb
Host smart-8803241f-ec26-4e01-8a29-4a1fa0ebe293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464157613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2464157613
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2305650899
Short name T681
Test name
Test status
Simulation time 95359317 ps
CPU time 1.13 seconds
Started Jul 31 05:11:55 PM PDT 24
Finished Jul 31 05:11:57 PM PDT 24
Peak memory 200492 kb
Host smart-2652a429-0a24-432c-98d3-850e1efcb086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305650899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.2305650899
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4102942731
Short name T66
Test name
Test status
Simulation time 99120503 ps
CPU time 0.72 seconds
Started Jul 31 05:11:54 PM PDT 24
Finished Jul 31 05:11:55 PM PDT 24
Peak memory 195256 kb
Host smart-e9e113ca-a0c7-4660-9fd7-27e007b2941b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102942731 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.4102942731
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.4287525308
Short name T113
Test name
Test status
Simulation time 17168601 ps
CPU time 0.62 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 195148 kb
Host smart-c112824b-e8c4-45f2-bb16-6bfae43bda8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287525308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.4287525308
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1806036584
Short name T651
Test name
Test status
Simulation time 18793069 ps
CPU time 0.65 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:05 PM PDT 24
Peak memory 195024 kb
Host smart-5224ee56-e991-411e-9324-fc929862cce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806036584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1806036584
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.612662663
Short name T120
Test name
Test status
Simulation time 68118132 ps
CPU time 0.84 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:02 PM PDT 24
Peak memory 198712 kb
Host smart-3fc81647-aa69-4b3a-9b2d-6e121fbf0a54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612662663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.612662663
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3536882519
Short name T715
Test name
Test status
Simulation time 228149515 ps
CPU time 1.42 seconds
Started Jul 31 05:12:01 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 200740 kb
Host smart-929cdc7e-cb77-46d5-89bc-bc3969ecd44b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536882519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3536882519
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2251491488
Short name T136
Test name
Test status
Simulation time 1048289115 ps
CPU time 1.18 seconds
Started Jul 31 05:11:52 PM PDT 24
Finished Jul 31 05:11:54 PM PDT 24
Peak memory 200652 kb
Host smart-e653965e-43ae-46ec-9e35-2c9c67418739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251491488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2251491488
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1638385645
Short name T718
Test name
Test status
Simulation time 113747840 ps
CPU time 1.44 seconds
Started Jul 31 05:11:59 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 200644 kb
Host smart-e446837b-752f-417f-96a8-4e8e818cbc19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638385645 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.1638385645
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4013268166
Short name T638
Test name
Test status
Simulation time 28745528 ps
CPU time 0.62 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:03 PM PDT 24
Peak memory 197360 kb
Host smart-e9e4afeb-cf34-4689-aa72-7f2fef7d700b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013268166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4013268166
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.4047291041
Short name T189
Test name
Test status
Simulation time 54019201 ps
CPU time 0.62 seconds
Started Jul 31 05:12:04 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 195056 kb
Host smart-734bf33b-225b-438c-b3a4-743c87826e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047291041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.4047291041
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3619569166
Short name T658
Test name
Test status
Simulation time 50118082 ps
CPU time 0.9 seconds
Started Jul 31 05:12:03 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 195148 kb
Host smart-57cb1ec2-3659-4f7f-a8d5-41fad9a83fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619569166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.3619569166
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2337657491
Short name T711
Test name
Test status
Simulation time 108666185 ps
CPU time 1.74 seconds
Started Jul 31 05:12:02 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 196480 kb
Host smart-49fb6e21-850a-471a-b613-e2042e7bf507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337657491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2337657491
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2830723365
Short name T647
Test name
Test status
Simulation time 100726181 ps
CPU time 1.13 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:12:00 PM PDT 24
Peak memory 200100 kb
Host smart-d76ada65-8438-4e0c-817a-6481a46e8ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830723365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2830723365
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2984477742
Short name T697
Test name
Test status
Simulation time 51576017 ps
CPU time 1.25 seconds
Started Jul 31 05:12:07 PM PDT 24
Finished Jul 31 05:12:09 PM PDT 24
Peak memory 197692 kb
Host smart-cbc53b74-f6ca-48ca-a327-b39793ca1621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984477742 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2984477742
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.800354856
Short name T652
Test name
Test status
Simulation time 105514093 ps
CPU time 0.63 seconds
Started Jul 31 05:12:10 PM PDT 24
Finished Jul 31 05:12:11 PM PDT 24
Peak memory 195140 kb
Host smart-1012b51a-2921-4855-9053-5ec5e591e390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800354856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.800354856
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1621197507
Short name T704
Test name
Test status
Simulation time 20642260 ps
CPU time 0.62 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 195016 kb
Host smart-35614867-0b67-4759-8e27-0f84fc81a16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621197507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1621197507
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2363396324
Short name T661
Test name
Test status
Simulation time 93713236 ps
CPU time 0.77 seconds
Started Jul 31 05:11:56 PM PDT 24
Finished Jul 31 05:11:57 PM PDT 24
Peak memory 198668 kb
Host smart-7a27725b-85f0-4f48-b58a-5a7cf66ed4e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363396324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2363396324
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2964289872
Short name T138
Test name
Test status
Simulation time 204927957 ps
CPU time 1.29 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 196380 kb
Host smart-cbd5f03c-12be-4c80-8d40-6b4be754ca0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964289872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2964289872
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.4235403739
Short name T717
Test name
Test status
Simulation time 796918515 ps
CPU time 1.52 seconds
Started Jul 31 05:11:58 PM PDT 24
Finished Jul 31 05:12:04 PM PDT 24
Peak memory 200504 kb
Host smart-ae51936d-9690-47ff-98e5-1f99fe172370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235403739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.4235403739
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3121857508
Short name T531
Test name
Test status
Simulation time 71750704 ps
CPU time 0.87 seconds
Started Jul 31 05:15:12 PM PDT 24
Finished Jul 31 05:15:13 PM PDT 24
Peak memory 200728 kb
Host smart-eef1d489-2d65-4283-a3a6-39357c826540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121857508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3121857508
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1119111743
Short name T23
Test name
Test status
Simulation time 54258618 ps
CPU time 0.72 seconds
Started Jul 31 05:15:07 PM PDT 24
Finished Jul 31 05:15:08 PM PDT 24
Peak memory 199096 kb
Host smart-78266ad0-bc8f-4d9e-bcf8-108b0102286a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119111743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1119111743
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3760972609
Short name T319
Test name
Test status
Simulation time 39860338 ps
CPU time 0.6 seconds
Started Jul 31 05:15:16 PM PDT 24
Finished Jul 31 05:15:17 PM PDT 24
Peak memory 197276 kb
Host smart-1f81fc37-4fc6-4b10-b90d-8e660da55d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760972609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3760972609
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3872907060
Short name T458
Test name
Test status
Simulation time 316704044 ps
CPU time 1.05 seconds
Started Jul 31 05:15:17 PM PDT 24
Finished Jul 31 05:15:18 PM PDT 24
Peak memory 198084 kb
Host smart-23878591-1a8d-4850-908a-50c2956348c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872907060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3872907060
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3130602268
Short name T409
Test name
Test status
Simulation time 23575253 ps
CPU time 0.66 seconds
Started Jul 31 05:15:08 PM PDT 24
Finished Jul 31 05:15:09 PM PDT 24
Peak memory 198120 kb
Host smart-9cb18f0e-1ccb-4640-a82d-df866c9162c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130602268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3130602268
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.760612204
Short name T562
Test name
Test status
Simulation time 38157635 ps
CPU time 0.63 seconds
Started Jul 31 05:15:18 PM PDT 24
Finished Jul 31 05:15:18 PM PDT 24
Peak memory 198080 kb
Host smart-d4d6e11d-0259-4eb3-a954-6f849655ad8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760612204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.760612204
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3608541143
Short name T261
Test name
Test status
Simulation time 86430207 ps
CPU time 0.74 seconds
Started Jul 31 05:15:14 PM PDT 24
Finished Jul 31 05:15:15 PM PDT 24
Peak memory 199108 kb
Host smart-e2a326d2-2563-4e72-8f82-bfb8cc93bd38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608541143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3608541143
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3350104872
Short name T601
Test name
Test status
Simulation time 98567592 ps
CPU time 1.07 seconds
Started Jul 31 05:15:09 PM PDT 24
Finished Jul 31 05:15:10 PM PDT 24
Peak memory 209548 kb
Host smart-8af0b5cd-aad2-4913-8a5f-c540169b7106
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350104872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3350104872
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3652087969
Short name T29
Test name
Test status
Simulation time 657345279 ps
CPU time 2.12 seconds
Started Jul 31 05:15:24 PM PDT 24
Finished Jul 31 05:15:26 PM PDT 24
Peak memory 218884 kb
Host smart-1b6f2cc6-4990-4cac-96d8-df8f323d9168
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652087969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3652087969
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3875579725
Short name T403
Test name
Test status
Simulation time 174541590 ps
CPU time 0.72 seconds
Started Jul 31 05:15:14 PM PDT 24
Finished Jul 31 05:15:15 PM PDT 24
Peak memory 199452 kb
Host smart-47f662a1-4ce6-44f6-ba5e-c60d4f1acea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875579725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3875579725
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.3535449428
Short name T545
Test name
Test status
Simulation time 94193137 ps
CPU time 0.62 seconds
Started Jul 31 05:15:17 PM PDT 24
Finished Jul 31 05:15:18 PM PDT 24
Peak memory 198532 kb
Host smart-9389692e-a291-4de0-a24a-f3f88c9a47f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535449428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3535449428
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.4292982547
Short name T489
Test name
Test status
Simulation time 42780434 ps
CPU time 0.61 seconds
Started Jul 31 05:15:07 PM PDT 24
Finished Jul 31 05:15:08 PM PDT 24
Peak memory 199192 kb
Host smart-7ed9b427-e766-4ba0-b592-1d01206d9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292982547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4292982547
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1663528920
Short name T544
Test name
Test status
Simulation time 59577750 ps
CPU time 0.68 seconds
Started Jul 31 05:15:15 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 198212 kb
Host smart-7da1fd4b-a3dc-416f-b6db-4824832d50dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663528920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1663528920
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1973373070
Short name T360
Test name
Test status
Simulation time 33719883 ps
CPU time 0.61 seconds
Started Jul 31 05:15:05 PM PDT 24
Finished Jul 31 05:15:06 PM PDT 24
Peak memory 197320 kb
Host smart-eee58254-510e-42a1-b0cd-a7fc763c9d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973373070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1973373070
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.3204670016
Short name T394
Test name
Test status
Simulation time 602830006 ps
CPU time 0.9 seconds
Started Jul 31 05:15:25 PM PDT 24
Finished Jul 31 05:15:26 PM PDT 24
Peak memory 198060 kb
Host smart-dab7dda1-a106-4026-a8f1-203382d71c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204670016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3204670016
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.4110485850
Short name T611
Test name
Test status
Simulation time 59110647 ps
CPU time 0.58 seconds
Started Jul 31 05:15:19 PM PDT 24
Finished Jul 31 05:15:20 PM PDT 24
Peak memory 197256 kb
Host smart-0bf70757-57f4-4664-a3a2-7e13d3be50dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110485850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.4110485850
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1940532043
Short name T347
Test name
Test status
Simulation time 24051861 ps
CPU time 0.62 seconds
Started Jul 31 05:15:15 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 198100 kb
Host smart-ee2f0377-2ddc-4721-b9f9-1ce9a3b43567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940532043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1940532043
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1472871502
Short name T163
Test name
Test status
Simulation time 63321780 ps
CPU time 0.68 seconds
Started Jul 31 05:15:18 PM PDT 24
Finished Jul 31 05:15:19 PM PDT 24
Peak memory 201396 kb
Host smart-1776ae92-eb6d-4b69-8e7d-8a341d05f6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472871502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1472871502
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1859582821
Short name T618
Test name
Test status
Simulation time 54284189 ps
CPU time 0.61 seconds
Started Jul 31 05:15:10 PM PDT 24
Finished Jul 31 05:15:11 PM PDT 24
Peak memory 198108 kb
Host smart-1cea19ed-f42b-4ad7-a1c7-bcf1bcc05565
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859582821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1859582821
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2307707609
Short name T428
Test name
Test status
Simulation time 133391157 ps
CPU time 0.89 seconds
Started Jul 31 05:15:39 PM PDT 24
Finished Jul 31 05:15:40 PM PDT 24
Peak memory 209400 kb
Host smart-4053fc32-7526-49ca-95e4-13faf6d0bb6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307707609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2307707609
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.954853392
Short name T17
Test name
Test status
Simulation time 530807091 ps
CPU time 1.09 seconds
Started Jul 31 05:15:19 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 216816 kb
Host smart-841487f0-2944-46f7-b10e-f3a9ad94d222
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954853392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.954853392
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3462419174
Short name T346
Test name
Test status
Simulation time 58734007 ps
CPU time 0.74 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 198008 kb
Host smart-b5b08802-ea75-486b-ae42-3205e4c3b1fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462419174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3462419174
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.4200074522
Short name T370
Test name
Test status
Simulation time 103866509 ps
CPU time 0.64 seconds
Started Jul 31 05:15:08 PM PDT 24
Finished Jul 31 05:15:08 PM PDT 24
Peak memory 198520 kb
Host smart-f4dfcd42-e594-4fb9-8acf-c50a695e693f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200074522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.4200074522
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.4234885626
Short name T430
Test name
Test status
Simulation time 134770443 ps
CPU time 0.8 seconds
Started Jul 31 05:16:10 PM PDT 24
Finished Jul 31 05:16:11 PM PDT 24
Peak memory 200252 kb
Host smart-da280608-fa32-4126-afc1-037aff7a7a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234885626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.4234885626
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.612817548
Short name T93
Test name
Test status
Simulation time 61470112 ps
CPU time 0.89 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:17 PM PDT 24
Peak memory 198536 kb
Host smart-15d85017-5e8f-457e-884d-5ebfff7e18da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612817548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disa
ble_rom_integrity_check.612817548
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2084354724
Short name T260
Test name
Test status
Simulation time 32396874 ps
CPU time 0.61 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 197776 kb
Host smart-34d420b0-38f4-424d-b9f5-689ca86322a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084354724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2084354724
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.1505293499
Short name T232
Test name
Test status
Simulation time 1014897316 ps
CPU time 0.99 seconds
Started Jul 31 05:16:13 PM PDT 24
Finished Jul 31 05:16:14 PM PDT 24
Peak memory 198312 kb
Host smart-d96e7cd1-fa6f-4a0e-867e-6a0438ccec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505293499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1505293499
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2040406047
Short name T412
Test name
Test status
Simulation time 40125637 ps
CPU time 0.64 seconds
Started Jul 31 05:16:21 PM PDT 24
Finished Jul 31 05:16:22 PM PDT 24
Peak memory 197356 kb
Host smart-5692e836-a901-49e4-8ed2-ead717414720
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040406047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2040406047
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.4289612230
Short name T421
Test name
Test status
Simulation time 54234480 ps
CPU time 0.57 seconds
Started Jul 31 05:16:08 PM PDT 24
Finished Jul 31 05:16:09 PM PDT 24
Peak memory 198084 kb
Host smart-44b6e445-94bb-4225-b164-3aff0ed20c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289612230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.4289612230
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1569993713
Short name T154
Test name
Test status
Simulation time 38784434 ps
CPU time 0.76 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 201404 kb
Host smart-89a1ec55-7b28-40f9-bd65-a80e3aa4af9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569993713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1569993713
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2596053843
Short name T407
Test name
Test status
Simulation time 41982034 ps
CPU time 0.65 seconds
Started Jul 31 05:16:09 PM PDT 24
Finished Jul 31 05:16:09 PM PDT 24
Peak memory 198296 kb
Host smart-0b6f578b-0d05-452f-a33c-8d0b2992b11a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596053843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2596053843
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2754948614
Short name T128
Test name
Test status
Simulation time 73463833 ps
CPU time 0.78 seconds
Started Jul 31 05:16:09 PM PDT 24
Finished Jul 31 05:16:10 PM PDT 24
Peak memory 198124 kb
Host smart-a79182c9-9b55-41d5-b9c7-672e733365b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754948614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2754948614
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1888296487
Short name T365
Test name
Test status
Simulation time 197789928 ps
CPU time 0.64 seconds
Started Jul 31 05:16:03 PM PDT 24
Finished Jul 31 05:16:04 PM PDT 24
Peak memory 198548 kb
Host smart-5404dd47-9260-4d7f-8b19-93f9fad6b060
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888296487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1888296487
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3415970256
Short name T101
Test name
Test status
Simulation time 102377720 ps
CPU time 0.63 seconds
Started Jul 31 05:16:29 PM PDT 24
Finished Jul 31 05:16:30 PM PDT 24
Peak memory 198572 kb
Host smart-d79f79aa-cd71-40fb-bbb7-c480f353f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415970256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3415970256
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.51696610
Short name T205
Test name
Test status
Simulation time 68975971 ps
CPU time 0.64 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:17 PM PDT 24
Peak memory 198292 kb
Host smart-0b8c113a-9ad9-40b4-8040-cdadbe90699d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51696610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disab
le_rom_integrity_check.51696610
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.762684953
Short name T243
Test name
Test status
Simulation time 32572976 ps
CPU time 0.6 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 197324 kb
Host smart-b12c0443-0708-4771-bbe6-e7aa25f510db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762684953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_
malfunc.762684953
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3550215552
Short name T468
Test name
Test status
Simulation time 559608855 ps
CPU time 0.93 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 198164 kb
Host smart-8c3c7d54-5a0e-45f2-ac99-38dd77b91258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550215552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3550215552
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1122623299
Short name T516
Test name
Test status
Simulation time 30235293 ps
CPU time 0.62 seconds
Started Jul 31 05:16:14 PM PDT 24
Finished Jul 31 05:16:15 PM PDT 24
Peak memory 198132 kb
Host smart-00fd5dd4-236d-4dd6-b05e-02ef78eeb48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122623299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1122623299
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1357794700
Short name T226
Test name
Test status
Simulation time 43394415 ps
CPU time 0.66 seconds
Started Jul 31 05:16:08 PM PDT 24
Finished Jul 31 05:16:09 PM PDT 24
Peak memory 198308 kb
Host smart-97cae0bd-b4a6-4fbf-b998-617af23cd6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357794700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1357794700
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1716023333
Short name T172
Test name
Test status
Simulation time 42900787 ps
CPU time 0.73 seconds
Started Jul 31 05:16:13 PM PDT 24
Finished Jul 31 05:16:13 PM PDT 24
Peak memory 201408 kb
Host smart-28dd930b-ebae-4f24-99b2-715e69e4831f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716023333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1716023333
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2642784622
Short name T345
Test name
Test status
Simulation time 85105811 ps
CPU time 0.67 seconds
Started Jul 31 05:16:13 PM PDT 24
Finished Jul 31 05:16:14 PM PDT 24
Peak memory 198412 kb
Host smart-c8c8c736-00a5-4133-aacf-c58c72e43272
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642784622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2642784622
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2855566079
Short name T395
Test name
Test status
Simulation time 102923500 ps
CPU time 0.98 seconds
Started Jul 31 05:16:12 PM PDT 24
Finished Jul 31 05:16:14 PM PDT 24
Peak memory 209472 kb
Host smart-e021ad3e-365f-46fc-a20e-e0c5541a5511
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855566079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2855566079
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2734266052
Short name T129
Test name
Test status
Simulation time 65158763 ps
CPU time 0.79 seconds
Started Jul 31 05:16:03 PM PDT 24
Finished Jul 31 05:16:04 PM PDT 24
Peak memory 198148 kb
Host smart-f83dc7ab-f911-45c3-a862-e7ee8c4ad773
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734266052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2734266052
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.140795860
Short name T396
Test name
Test status
Simulation time 30498682 ps
CPU time 0.67 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 198444 kb
Host smart-5513995d-c511-47b7-a85c-c45c3c4d9185
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140795860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.140795860
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.4001856247
Short name T127
Test name
Test status
Simulation time 24182162 ps
CPU time 0.68 seconds
Started Jul 31 05:16:09 PM PDT 24
Finished Jul 31 05:16:09 PM PDT 24
Peak memory 198644 kb
Host smart-fb6b5fa6-8420-4eb0-bbdf-0d415c4be2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001856247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4001856247
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2283323527
Short name T24
Test name
Test status
Simulation time 50324334 ps
CPU time 0.77 seconds
Started Jul 31 05:16:21 PM PDT 24
Finished Jul 31 05:16:22 PM PDT 24
Peak memory 199184 kb
Host smart-2cb0a707-a0b3-468e-b591-cb0672504d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283323527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2283323527
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2755527760
Short name T301
Test name
Test status
Simulation time 31651249 ps
CPU time 0.59 seconds
Started Jul 31 05:16:19 PM PDT 24
Finished Jul 31 05:16:20 PM PDT 24
Peak memory 198036 kb
Host smart-8ec76f59-ffe0-422b-ab84-413b5d02343b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755527760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.2755527760
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3351067839
Short name T275
Test name
Test status
Simulation time 310901872 ps
CPU time 0.97 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 198368 kb
Host smart-b0c0ed9d-558e-4775-8270-fa8a748b37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351067839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3351067839
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1514919120
Short name T323
Test name
Test status
Simulation time 56308002 ps
CPU time 0.65 seconds
Started Jul 31 05:16:15 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 198064 kb
Host smart-312084bb-2390-4985-b7c9-d84d0db04573
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514919120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1514919120
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.1587270254
Short name T240
Test name
Test status
Simulation time 52422890 ps
CPU time 0.59 seconds
Started Jul 31 05:16:18 PM PDT 24
Finished Jul 31 05:16:19 PM PDT 24
Peak memory 198156 kb
Host smart-0e605942-dd7e-47d2-b74b-8215a602883c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587270254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1587270254
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2898592635
Short name T168
Test name
Test status
Simulation time 71095074 ps
CPU time 0.66 seconds
Started Jul 31 05:16:15 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 201440 kb
Host smart-81f37dfd-4211-41f6-b43a-a5e5a6880d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898592635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2898592635
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.1262275214
Short name T560
Test name
Test status
Simulation time 41307538 ps
CPU time 0.73 seconds
Started Jul 31 05:16:08 PM PDT 24
Finished Jul 31 05:16:09 PM PDT 24
Peak memory 198432 kb
Host smart-ae322088-4da9-447d-bbf7-c5bb98c28ae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262275214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1262275214
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.1208933383
Short name T215
Test name
Test status
Simulation time 118075191 ps
CPU time 0.94 seconds
Started Jul 31 05:16:14 PM PDT 24
Finished Jul 31 05:16:15 PM PDT 24
Peak memory 209412 kb
Host smart-71a8e419-af97-41ac-864f-ee8376262e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208933383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1208933383
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.765818793
Short name T352
Test name
Test status
Simulation time 92160443 ps
CPU time 0.68 seconds
Started Jul 31 05:16:23 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 198084 kb
Host smart-e2413640-da9c-4d39-a230-78a90f664f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765818793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.765818793
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.4286100227
Short name T148
Test name
Test status
Simulation time 34342126 ps
CPU time 0.61 seconds
Started Jul 31 05:16:20 PM PDT 24
Finished Jul 31 05:16:21 PM PDT 24
Peak memory 198592 kb
Host smart-425bca58-3d1a-4a79-8272-d0ef4894decc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286100227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.4286100227
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.587135952
Short name T158
Test name
Test status
Simulation time 50879637 ps
CPU time 0.91 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 200740 kb
Host smart-18b6e7f4-04db-462b-9cdc-badca122fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587135952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.587135952
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3828420634
Short name T94
Test name
Test status
Simulation time 61261611 ps
CPU time 0.82 seconds
Started Jul 31 05:16:26 PM PDT 24
Finished Jul 31 05:16:27 PM PDT 24
Peak memory 199132 kb
Host smart-08688c75-ba4e-4f34-9665-2195f4b54669
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828420634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3828420634
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3523380464
Short name T327
Test name
Test status
Simulation time 29759710 ps
CPU time 0.62 seconds
Started Jul 31 05:16:25 PM PDT 24
Finished Jul 31 05:16:26 PM PDT 24
Peak memory 197300 kb
Host smart-e8e86e72-5717-4864-ab9f-71af1bb1c1db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523380464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3523380464
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.307323448
Short name T379
Test name
Test status
Simulation time 638389827 ps
CPU time 0.92 seconds
Started Jul 31 05:16:27 PM PDT 24
Finished Jul 31 05:16:28 PM PDT 24
Peak memory 198080 kb
Host smart-5ab0043d-b7c7-4714-8aef-b695c23de103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307323448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.307323448
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.267315724
Short name T571
Test name
Test status
Simulation time 42869105 ps
CPU time 0.63 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 198364 kb
Host smart-a5dbacfe-bca2-404e-8b21-102a28eeb5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267315724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.267315724
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3559798093
Short name T606
Test name
Test status
Simulation time 149033638 ps
CPU time 0.71 seconds
Started Jul 31 05:16:14 PM PDT 24
Finished Jul 31 05:16:14 PM PDT 24
Peak memory 199140 kb
Host smart-3308f5f9-4538-4890-83ec-4b565430976c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559798093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3559798093
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.490679722
Short name T251
Test name
Test status
Simulation time 122909886 ps
CPU time 0.86 seconds
Started Jul 31 05:16:33 PM PDT 24
Finished Jul 31 05:16:34 PM PDT 24
Peak memory 209524 kb
Host smart-27da6b77-86b8-41c8-9f0f-5a8ba381abf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490679722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.490679722
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2769116080
Short name T344
Test name
Test status
Simulation time 62962806 ps
CPU time 0.82 seconds
Started Jul 31 05:16:23 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 198156 kb
Host smart-e261769f-1827-4c04-bbe2-96d95be74377
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769116080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2769116080
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2666603524
Short name T511
Test name
Test status
Simulation time 87570384 ps
CPU time 0.61 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 198524 kb
Host smart-fa0c1223-c140-44cd-a0e1-174b8597e58e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666603524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2666603524
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3064802172
Short name T35
Test name
Test status
Simulation time 50866979 ps
CPU time 0.72 seconds
Started Jul 31 05:16:35 PM PDT 24
Finished Jul 31 05:16:36 PM PDT 24
Peak memory 198456 kb
Host smart-adb55137-9109-4985-a835-754e7fd998a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064802172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3064802172
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2292839480
Short name T434
Test name
Test status
Simulation time 31125213 ps
CPU time 0.6 seconds
Started Jul 31 05:16:25 PM PDT 24
Finished Jul 31 05:16:26 PM PDT 24
Peak memory 197348 kb
Host smart-3ae4518f-4426-4a2f-a60b-78bf294f06ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292839480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2292839480
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.372494518
Short name T368
Test name
Test status
Simulation time 165267600 ps
CPU time 0.98 seconds
Started Jul 31 05:16:19 PM PDT 24
Finished Jul 31 05:16:21 PM PDT 24
Peak memory 198132 kb
Host smart-aa04b54b-5d9b-4f3a-a09f-4738eda821b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372494518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.372494518
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2747684842
Short name T425
Test name
Test status
Simulation time 61621010 ps
CPU time 0.71 seconds
Started Jul 31 05:16:31 PM PDT 24
Finished Jul 31 05:16:32 PM PDT 24
Peak memory 198036 kb
Host smart-8087b4c1-031a-4ab8-b1bd-e44938662d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747684842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2747684842
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1147007019
Short name T485
Test name
Test status
Simulation time 47481139 ps
CPU time 0.6 seconds
Started Jul 31 05:16:26 PM PDT 24
Finished Jul 31 05:16:26 PM PDT 24
Peak memory 198136 kb
Host smart-d993c03e-967e-4286-a39d-fdc4c3d17046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147007019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1147007019
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2274295433
Short name T417
Test name
Test status
Simulation time 34562806 ps
CPU time 0.65 seconds
Started Jul 31 05:16:27 PM PDT 24
Finished Jul 31 05:16:28 PM PDT 24
Peak memory 199128 kb
Host smart-195214a7-dff2-4cf1-99ab-345b9c68da67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274295433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2274295433
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3912212299
Short name T221
Test name
Test status
Simulation time 148538535 ps
CPU time 0.8 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 209104 kb
Host smart-286b39b2-ddf0-4d1b-b25e-0b0bcf541a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912212299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3912212299
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4149663367
Short name T131
Test name
Test status
Simulation time 60968884 ps
CPU time 0.77 seconds
Started Jul 31 05:16:21 PM PDT 24
Finished Jul 31 05:16:21 PM PDT 24
Peak memory 198168 kb
Host smart-0c4efcaf-1367-40e7-83a7-14ce45ac05b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149663367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4149663367
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2382292029
Short name T533
Test name
Test status
Simulation time 51262185 ps
CPU time 0.63 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 198144 kb
Host smart-8808b8b0-c4b0-495a-8585-d5555baf25f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382292029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2382292029
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3184367033
Short name T89
Test name
Test status
Simulation time 78152479 ps
CPU time 0.95 seconds
Started Jul 31 05:16:33 PM PDT 24
Finished Jul 31 05:16:34 PM PDT 24
Peak memory 200744 kb
Host smart-c3de1e6f-e563-45bb-bd37-9da60d0492e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184367033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3184367033
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2826097920
Short name T195
Test name
Test status
Simulation time 91211935 ps
CPU time 0.68 seconds
Started Jul 31 05:16:30 PM PDT 24
Finished Jul 31 05:16:31 PM PDT 24
Peak memory 198476 kb
Host smart-b6f25c7e-6510-408d-b0d2-a55fd03b5595
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826097920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2826097920
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.571519508
Short name T244
Test name
Test status
Simulation time 39985740 ps
CPU time 0.59 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 197952 kb
Host smart-08cbdf0b-6011-4e01-8186-bb60bb7a2ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571519508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_
malfunc.571519508
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.3642910172
Short name T455
Test name
Test status
Simulation time 1480248971 ps
CPU time 0.92 seconds
Started Jul 31 05:16:36 PM PDT 24
Finished Jul 31 05:16:37 PM PDT 24
Peak memory 198396 kb
Host smart-d3f4c482-794e-4fbc-b631-6ac31e56fae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642910172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3642910172
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2139319201
Short name T574
Test name
Test status
Simulation time 59204326 ps
CPU time 0.58 seconds
Started Jul 31 05:16:40 PM PDT 24
Finished Jul 31 05:16:40 PM PDT 24
Peak memory 198036 kb
Host smart-a6c1463f-11cd-4fbf-9286-369240df6695
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139319201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2139319201
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3134200663
Short name T517
Test name
Test status
Simulation time 33794267 ps
CPU time 0.6 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 198036 kb
Host smart-d0402f4c-f0e1-4e77-b569-437bd00f499f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134200663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3134200663
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2196365227
Short name T488
Test name
Test status
Simulation time 59482576 ps
CPU time 0.6 seconds
Started Jul 31 05:16:16 PM PDT 24
Finished Jul 31 05:16:17 PM PDT 24
Peak memory 198216 kb
Host smart-f7f80ccc-6cf9-4a37-8bd3-6a24d8baed65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196365227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2196365227
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2919412729
Short name T437
Test name
Test status
Simulation time 115592560 ps
CPU time 0.93 seconds
Started Jul 31 05:16:41 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 209396 kb
Host smart-a2bdf7aa-6ac0-4802-9c08-928ee73476a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919412729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2919412729
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.1385931837
Short name T492
Test name
Test status
Simulation time 205074315 ps
CPU time 0.73 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 198104 kb
Host smart-5afb6020-b6a5-4992-96bb-5e73debb73f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385931837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1385931837
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1339108809
Short name T541
Test name
Test status
Simulation time 27681035 ps
CPU time 0.66 seconds
Started Jul 31 05:16:28 PM PDT 24
Finished Jul 31 05:16:29 PM PDT 24
Peak memory 199392 kb
Host smart-9e543612-e7cf-4338-a9af-3a42e9ac0b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339108809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1339108809
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.3832987012
Short name T99
Test name
Test status
Simulation time 43842379 ps
CPU time 0.83 seconds
Started Jul 31 05:16:23 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 200316 kb
Host smart-6f8032d9-9ceb-480d-9def-4191413eed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832987012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3832987012
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2337711704
Short name T144
Test name
Test status
Simulation time 81442073 ps
CPU time 0.68 seconds
Started Jul 31 05:16:34 PM PDT 24
Finished Jul 31 05:16:35 PM PDT 24
Peak memory 198248 kb
Host smart-d2321026-993e-4ac0-a063-06512edbdca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337711704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2337711704
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.1733911863
Short name T546
Test name
Test status
Simulation time 30138254 ps
CPU time 0.61 seconds
Started Jul 31 05:16:26 PM PDT 24
Finished Jul 31 05:16:27 PM PDT 24
Peak memory 197268 kb
Host smart-d7dbf384-ac4f-49a0-97e2-b40dd45c561c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733911863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.1733911863
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.706596181
Short name T392
Test name
Test status
Simulation time 926875852 ps
CPU time 0.92 seconds
Started Jul 31 05:16:13 PM PDT 24
Finished Jul 31 05:16:14 PM PDT 24
Peak memory 197996 kb
Host smart-0a5d4eba-3ab2-406d-93c9-e3194aa7e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706596181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.706596181
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.771083320
Short name T254
Test name
Test status
Simulation time 24415358 ps
CPU time 0.64 seconds
Started Jul 31 05:16:20 PM PDT 24
Finished Jul 31 05:16:21 PM PDT 24
Peak memory 198064 kb
Host smart-d0f9bdda-a213-4eb0-bda1-2a3f4a2135bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771083320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.771083320
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.554698628
Short name T259
Test name
Test status
Simulation time 22216130 ps
CPU time 0.6 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 198388 kb
Host smart-f22df489-2ef4-48d2-bd49-1c92456d0dc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554698628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.554698628
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1887067022
Short name T186
Test name
Test status
Simulation time 73534396 ps
CPU time 0.66 seconds
Started Jul 31 05:16:28 PM PDT 24
Finished Jul 31 05:16:29 PM PDT 24
Peak memory 201372 kb
Host smart-7c1908ac-b0fe-4d1b-a2b0-0f9e4f85fc6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887067022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1887067022
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3798532218
Short name T91
Test name
Test status
Simulation time 64645310 ps
CPU time 0.83 seconds
Started Jul 31 05:16:15 PM PDT 24
Finished Jul 31 05:16:16 PM PDT 24
Peak memory 198300 kb
Host smart-11b68498-b4b1-42b1-a5be-04121349ff5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798532218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3798532218
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3034862056
Short name T353
Test name
Test status
Simulation time 119677985 ps
CPU time 0.9 seconds
Started Jul 31 05:16:25 PM PDT 24
Finished Jul 31 05:16:26 PM PDT 24
Peak memory 209568 kb
Host smart-335e92f8-cdef-4114-96b2-a4e72a865520
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034862056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3034862056
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.668306772
Short name T561
Test name
Test status
Simulation time 74743604 ps
CPU time 0.81 seconds
Started Jul 31 05:16:38 PM PDT 24
Finished Jul 31 05:16:39 PM PDT 24
Peak memory 199312 kb
Host smart-c3ef9757-527d-4a96-8502-8212ee3f686e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668306772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.668306772
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.736840419
Short name T335
Test name
Test status
Simulation time 64036073 ps
CPU time 0.67 seconds
Started Jul 31 05:16:23 PM PDT 24
Finished Jul 31 05:16:24 PM PDT 24
Peak memory 198744 kb
Host smart-2f199221-4666-49ca-a9ff-ee1ebc53e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736840419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.736840419
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1960018386
Short name T202
Test name
Test status
Simulation time 50330335 ps
CPU time 0.76 seconds
Started Jul 31 05:16:28 PM PDT 24
Finished Jul 31 05:16:29 PM PDT 24
Peak memory 199180 kb
Host smart-b97c2fa8-77b1-4cae-a45f-6f587651ee26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960018386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1960018386
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3131722931
Short name T376
Test name
Test status
Simulation time 31123508 ps
CPU time 0.62 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:47 PM PDT 24
Peak memory 198060 kb
Host smart-59c89674-3e9b-4757-b4dd-b0f26c33a53f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131722931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3131722931
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3637138635
Short name T258
Test name
Test status
Simulation time 639990551 ps
CPU time 0.95 seconds
Started Jul 31 05:16:31 PM PDT 24
Finished Jul 31 05:16:32 PM PDT 24
Peak memory 198000 kb
Host smart-9ac1f301-e905-4631-a00c-ea0df07112c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637138635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3637138635
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2072017620
Short name T581
Test name
Test status
Simulation time 53365845 ps
CPU time 0.67 seconds
Started Jul 31 05:16:21 PM PDT 24
Finished Jul 31 05:16:27 PM PDT 24
Peak memory 198060 kb
Host smart-128940be-f6b8-4e4a-b490-34ae090be388
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072017620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2072017620
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2400870756
Short name T524
Test name
Test status
Simulation time 44084407 ps
CPU time 0.64 seconds
Started Jul 31 05:16:30 PM PDT 24
Finished Jul 31 05:16:30 PM PDT 24
Peak memory 198028 kb
Host smart-3a0d3d87-f354-4bf4-9801-be5b7ef52f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400870756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2400870756
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.1740839901
Short name T459
Test name
Test status
Simulation time 57029580 ps
CPU time 0.63 seconds
Started Jul 31 05:16:32 PM PDT 24
Finished Jul 31 05:16:33 PM PDT 24
Peak memory 198104 kb
Host smart-ed50e307-0ddf-442d-9ff4-b9299100ae11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740839901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1740839901
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2242102564
Short name T525
Test name
Test status
Simulation time 162056265 ps
CPU time 0.78 seconds
Started Jul 31 05:16:22 PM PDT 24
Finished Jul 31 05:16:28 PM PDT 24
Peak memory 209472 kb
Host smart-99f76eb7-25b3-4ae0-bf50-7361213f6b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242102564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2242102564
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.4176699825
Short name T130
Test name
Test status
Simulation time 66310353 ps
CPU time 0.9 seconds
Started Jul 31 05:16:17 PM PDT 24
Finished Jul 31 05:16:18 PM PDT 24
Peak memory 198956 kb
Host smart-75860470-0705-44a8-9212-570ed2f5a0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176699825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4176699825
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.1435989573
Short name T547
Test name
Test status
Simulation time 28930106 ps
CPU time 0.67 seconds
Started Jul 31 05:16:30 PM PDT 24
Finished Jul 31 05:16:30 PM PDT 24
Peak memory 199356 kb
Host smart-c5058d9e-b810-457c-a8c7-0acc4f6083e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435989573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.1435989573
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.645476841
Short name T570
Test name
Test status
Simulation time 33106668 ps
CPU time 1.08 seconds
Started Jul 31 05:16:37 PM PDT 24
Finished Jul 31 05:16:38 PM PDT 24
Peak memory 200956 kb
Host smart-550e3010-0b80-4f52-9843-e3f661850834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645476841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.645476841
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1056435828
Short name T197
Test name
Test status
Simulation time 56176789 ps
CPU time 0.83 seconds
Started Jul 31 05:16:34 PM PDT 24
Finished Jul 31 05:16:35 PM PDT 24
Peak memory 199092 kb
Host smart-b183b90d-cfe8-4264-b5c3-11a28949e46a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056435828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1056435828
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2451326634
Short name T286
Test name
Test status
Simulation time 32554423 ps
CPU time 0.61 seconds
Started Jul 31 05:16:41 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 198056 kb
Host smart-6d847c14-a6a2-42db-84f2-024b39e150a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451326634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.2451326634
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.3511484050
Short name T276
Test name
Test status
Simulation time 165251016 ps
CPU time 0.98 seconds
Started Jul 31 05:16:56 PM PDT 24
Finished Jul 31 05:16:57 PM PDT 24
Peak memory 198136 kb
Host smart-90ecfb8d-8b74-4deb-a5c0-85b02917f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511484050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3511484050
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3338741351
Short name T320
Test name
Test status
Simulation time 36363656 ps
CPU time 0.72 seconds
Started Jul 31 05:16:35 PM PDT 24
Finished Jul 31 05:16:35 PM PDT 24
Peak memory 198064 kb
Host smart-cdf835f9-8f60-41d1-95ff-6400e29cc937
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338741351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3338741351
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1113495258
Short name T432
Test name
Test status
Simulation time 84209771 ps
CPU time 0.61 seconds
Started Jul 31 05:16:40 PM PDT 24
Finished Jul 31 05:16:41 PM PDT 24
Peak memory 198052 kb
Host smart-bfadcf36-0974-4f55-90e2-f7daa352047c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113495258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1113495258
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3111585798
Short name T451
Test name
Test status
Simulation time 88256406 ps
CPU time 0.9 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:54 PM PDT 24
Peak memory 198656 kb
Host smart-7f45e699-2986-4094-ab61-435a34d82e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111585798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3111585798
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2489243875
Short name T416
Test name
Test status
Simulation time 178258678 ps
CPU time 0.82 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 209508 kb
Host smart-2173666d-456e-45bb-b5fd-77fc8850076d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489243875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2489243875
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2054855011
Short name T532
Test name
Test status
Simulation time 61748210 ps
CPU time 0.82 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:54 PM PDT 24
Peak memory 198088 kb
Host smart-a70de8a0-8c13-41a7-a144-f3a40d79a185
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054855011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2054855011
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2109245737
Short name T132
Test name
Test status
Simulation time 31282447 ps
CPU time 0.66 seconds
Started Jul 31 05:16:42 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 198504 kb
Host smart-89713959-557d-42b1-b79a-d387ce2cd2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109245737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2109245737
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1099506903
Short name T515
Test name
Test status
Simulation time 88110331 ps
CPU time 0.78 seconds
Started Jul 31 05:16:37 PM PDT 24
Finished Jul 31 05:16:38 PM PDT 24
Peak memory 199124 kb
Host smart-101ad3de-4a35-4d00-b258-98ec268d62bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099506903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1099506903
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2568269996
Short name T38
Test name
Test status
Simulation time 116410609 ps
CPU time 0.66 seconds
Started Jul 31 05:16:41 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 198496 kb
Host smart-5635453a-d168-4d17-ab31-16b0e81e2c50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568269996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2568269996
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3359338431
Short name T528
Test name
Test status
Simulation time 31178365 ps
CPU time 0.68 seconds
Started Jul 31 05:16:42 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 197324 kb
Host smart-82aa676e-b7d8-4a35-80d9-788161441009
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359338431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.3359338431
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.353735182
Short name T96
Test name
Test status
Simulation time 829274633 ps
CPU time 0.97 seconds
Started Jul 31 05:16:51 PM PDT 24
Finished Jul 31 05:16:52 PM PDT 24
Peak memory 198104 kb
Host smart-b5cafd50-e826-4f7b-a2c2-e3a78746ed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353735182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.353735182
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.39389338
Short name T460
Test name
Test status
Simulation time 34134420 ps
CPU time 0.62 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 197968 kb
Host smart-a91c7858-54b7-4e6e-a7b5-d7a639f23777
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39389338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.39389338
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.329000315
Short name T438
Test name
Test status
Simulation time 31642606 ps
CPU time 0.66 seconds
Started Jul 31 05:16:39 PM PDT 24
Finished Jul 31 05:16:39 PM PDT 24
Peak memory 198416 kb
Host smart-2e815bd6-4b62-4840-847f-9c8d5b964f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329000315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.329000315
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1500599470
Short name T179
Test name
Test status
Simulation time 93476279 ps
CPU time 0.69 seconds
Started Jul 31 05:16:32 PM PDT 24
Finished Jul 31 05:16:33 PM PDT 24
Peak memory 201616 kb
Host smart-ef3899cd-72dc-4f49-a848-f37cdda1c2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500599470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1500599470
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.4279508268
Short name T334
Test name
Test status
Simulation time 152513195 ps
CPU time 0.72 seconds
Started Jul 31 05:16:27 PM PDT 24
Finished Jul 31 05:16:28 PM PDT 24
Peak memory 199008 kb
Host smart-4ef1ee72-27ee-4af6-9abf-3dba2d50b63b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279508268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.4279508268
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3465218309
Short name T508
Test name
Test status
Simulation time 469080564 ps
CPU time 0.77 seconds
Started Jul 31 05:16:35 PM PDT 24
Finished Jul 31 05:16:36 PM PDT 24
Peak memory 209520 kb
Host smart-13e259c1-a56d-4c3c-a36a-7086f65c3d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465218309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3465218309
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.627606915
Short name T361
Test name
Test status
Simulation time 64273735 ps
CPU time 0.8 seconds
Started Jul 31 05:16:28 PM PDT 24
Finished Jul 31 05:16:29 PM PDT 24
Peak memory 198300 kb
Host smart-f4832337-6fbb-4dc7-ac36-35eb3aa8c519
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627606915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_
mubi.627606915
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.401265477
Short name T519
Test name
Test status
Simulation time 26902566 ps
CPU time 0.69 seconds
Started Jul 31 05:16:24 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 199348 kb
Host smart-59019ce7-4391-4aea-b559-9ee24739e18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401265477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.401265477
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2205377468
Short name T371
Test name
Test status
Simulation time 53414656 ps
CPU time 0.7 seconds
Started Jul 31 05:15:10 PM PDT 24
Finished Jul 31 05:15:11 PM PDT 24
Peak memory 199196 kb
Host smart-61b2b5ba-1818-451c-bbfa-fa8d332213d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205377468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2205377468
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2778081878
Short name T349
Test name
Test status
Simulation time 87364993 ps
CPU time 0.67 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 199124 kb
Host smart-5dfe0e5a-fa4c-4b20-9136-73a6c4fd3cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778081878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2778081878
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1401992453
Short name T551
Test name
Test status
Simulation time 38588613 ps
CPU time 0.6 seconds
Started Jul 31 05:15:17 PM PDT 24
Finished Jul 31 05:15:18 PM PDT 24
Peak memory 197936 kb
Host smart-8bfc74f4-1ff3-4fb6-8407-dabdeb54d97f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401992453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1401992453
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.1132600714
Short name T228
Test name
Test status
Simulation time 623886117 ps
CPU time 0.99 seconds
Started Jul 31 05:15:15 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 198404 kb
Host smart-10e3498f-adde-4353-a652-fbe6ac20b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132600714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1132600714
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3166923032
Short name T126
Test name
Test status
Simulation time 51020020 ps
CPU time 0.62 seconds
Started Jul 31 05:15:22 PM PDT 24
Finished Jul 31 05:15:23 PM PDT 24
Peak memory 198060 kb
Host smart-bf0b4964-a0e1-4cb7-b485-0377ab4d0362
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166923032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3166923032
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2613890849
Short name T372
Test name
Test status
Simulation time 48893265 ps
CPU time 0.62 seconds
Started Jul 31 05:15:15 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 198128 kb
Host smart-b1bea0fc-c0ee-4ee0-8eb5-39d7523fd5a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613890849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2613890849
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.27515287
Short name T37
Test name
Test status
Simulation time 142616774 ps
CPU time 0.82 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:24 PM PDT 24
Peak memory 198320 kb
Host smart-7a14183e-a217-4526-ba88-992ed203f3de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.27515287
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.935024814
Short name T257
Test name
Test status
Simulation time 125419125 ps
CPU time 0.79 seconds
Started Jul 31 05:15:10 PM PDT 24
Finished Jul 31 05:15:11 PM PDT 24
Peak memory 209504 kb
Host smart-f9355b3f-18ad-4761-a3cc-cc433e34076c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935024814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.935024814
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.3455079813
Short name T28
Test name
Test status
Simulation time 329091276 ps
CPU time 1.48 seconds
Started Jul 31 05:15:19 PM PDT 24
Finished Jul 31 05:15:20 PM PDT 24
Peak memory 216848 kb
Host smart-47f7e168-cf96-4602-abbf-1001190a7710
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455079813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3455079813
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2494452460
Short name T236
Test name
Test status
Simulation time 50295496 ps
CPU time 0.92 seconds
Started Jul 31 05:15:15 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 199352 kb
Host smart-a5053657-531f-4e67-9fcd-f193891f14a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494452460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2494452460
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.2032615693
Short name T520
Test name
Test status
Simulation time 31052530 ps
CPU time 0.69 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 199316 kb
Host smart-addf20fe-d068-4cd3-8c45-716ee33ebc73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032615693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2032615693
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3480019135
Short name T285
Test name
Test status
Simulation time 57331909 ps
CPU time 0.75 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 198392 kb
Host smart-6a6a474d-8eec-4f8a-b7d7-ad16735c6610
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480019135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3480019135
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2920819948
Short name T308
Test name
Test status
Simulation time 38883466 ps
CPU time 0.59 seconds
Started Jul 31 05:16:42 PM PDT 24
Finished Jul 31 05:16:42 PM PDT 24
Peak memory 198068 kb
Host smart-1e91f1e8-33c1-4a5e-954c-1889618b5a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920819948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2920819948
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.747088200
Short name T390
Test name
Test status
Simulation time 604007005 ps
CPU time 0.93 seconds
Started Jul 31 05:16:50 PM PDT 24
Finished Jul 31 05:16:51 PM PDT 24
Peak memory 198084 kb
Host smart-219ea584-2044-4dfc-85ac-c1a67c0dd4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747088200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.747088200
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1309082143
Short name T146
Test name
Test status
Simulation time 48231738 ps
CPU time 0.62 seconds
Started Jul 31 05:16:54 PM PDT 24
Finished Jul 31 05:16:55 PM PDT 24
Peak memory 198052 kb
Host smart-dee161eb-0bdd-4a6d-8e8f-70019ece1e19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309082143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1309082143
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.3769816260
Short name T282
Test name
Test status
Simulation time 25133810 ps
CPU time 0.63 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:01 PM PDT 24
Peak memory 198312 kb
Host smart-3306a125-506d-408d-8a7e-1172fec665cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769816260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3769816260
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1177238887
Short name T614
Test name
Test status
Simulation time 42756920 ps
CPU time 0.69 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 201396 kb
Host smart-e0e1215a-49b3-46d5-a4af-5f74921ca9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177238887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1177238887
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.3136688815
Short name T269
Test name
Test status
Simulation time 77089874 ps
CPU time 0.68 seconds
Started Jul 31 05:16:51 PM PDT 24
Finished Jul 31 05:16:51 PM PDT 24
Peak memory 199188 kb
Host smart-f6b824a5-47d7-40a4-977f-cb8b64be6775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136688815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3136688815
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3648346561
Short name T523
Test name
Test status
Simulation time 119852949 ps
CPU time 0.94 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 209552 kb
Host smart-bb909bfc-7e3f-46f4-93e2-2d7bcba4ed5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648346561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3648346561
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.497746106
Short name T307
Test name
Test status
Simulation time 94873896 ps
CPU time 0.78 seconds
Started Jul 31 05:16:58 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198256 kb
Host smart-4faebab7-85fe-4fdd-89fe-8106313e1eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497746106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_
mubi.497746106
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1709770145
Short name T467
Test name
Test status
Simulation time 26429154 ps
CPU time 0.66 seconds
Started Jul 31 05:16:51 PM PDT 24
Finished Jul 31 05:16:52 PM PDT 24
Peak memory 199304 kb
Host smart-1f77e747-7e31-41c0-b1a8-60bec22cd967
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709770145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1709770145
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3130214245
Short name T86
Test name
Test status
Simulation time 23471269 ps
CPU time 0.75 seconds
Started Jul 31 05:16:55 PM PDT 24
Finished Jul 31 05:16:56 PM PDT 24
Peak memory 199140 kb
Host smart-509f2d5f-bd40-4b00-992f-2e7b62b25dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130214245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3130214245
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.637201677
Short name T443
Test name
Test status
Simulation time 40771174 ps
CPU time 0.56 seconds
Started Jul 31 05:16:46 PM PDT 24
Finished Jul 31 05:16:47 PM PDT 24
Peak memory 198008 kb
Host smart-8e524141-c5ca-4c0a-9f95-80340c15e6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637201677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.637201677
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1208556345
Short name T471
Test name
Test status
Simulation time 636901202 ps
CPU time 0.95 seconds
Started Jul 31 05:16:55 PM PDT 24
Finished Jul 31 05:16:57 PM PDT 24
Peak memory 198388 kb
Host smart-9a3706bb-8a36-4bc7-af8e-3147e4add8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208556345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1208556345
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.550481028
Short name T381
Test name
Test status
Simulation time 61727276 ps
CPU time 0.7 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 197980 kb
Host smart-796747e1-b209-4610-b051-b8e6be6f12ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550481028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.550481028
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1270248489
Short name T237
Test name
Test status
Simulation time 103865088 ps
CPU time 0.59 seconds
Started Jul 31 05:16:51 PM PDT 24
Finished Jul 31 05:16:51 PM PDT 24
Peak memory 198084 kb
Host smart-7b5a0ab9-8b31-4237-8d60-52a842c4f59f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270248489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1270248489
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.4289713880
Short name T167
Test name
Test status
Simulation time 68492574 ps
CPU time 0.68 seconds
Started Jul 31 05:16:52 PM PDT 24
Finished Jul 31 05:16:53 PM PDT 24
Peak memory 201396 kb
Host smart-e96d4cd4-fb6c-498d-8933-c30e7b4847e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289713880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.4289713880
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2691245212
Short name T288
Test name
Test status
Simulation time 49825548 ps
CPU time 0.79 seconds
Started Jul 31 05:16:59 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 198356 kb
Host smart-c3c27523-1207-43c4-b993-eb96102db2c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691245212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2691245212
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2352363076
Short name T578
Test name
Test status
Simulation time 94312480 ps
CPU time 1.03 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 209560 kb
Host smart-50ff7e1b-e330-4667-852a-ad0e5bfa7fa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352363076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2352363076
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2927855650
Short name T604
Test name
Test status
Simulation time 63662617 ps
CPU time 0.84 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 198240 kb
Host smart-1c93e270-f673-4f77-aaf5-8511c2966b3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927855650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2927855650
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.539911702
Short name T177
Test name
Test status
Simulation time 108522272 ps
CPU time 0.84 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:53 PM PDT 24
Peak memory 200056 kb
Host smart-01b54347-8bb0-48d1-84ae-a0a52ebd4022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539911702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.539911702
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1247711358
Short name T484
Test name
Test status
Simulation time 65337448 ps
CPU time 0.72 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:54 PM PDT 24
Peak memory 199076 kb
Host smart-333d185a-b636-4c4a-a2a7-6016e4d46574
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247711358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1247711358
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1669833786
Short name T291
Test name
Test status
Simulation time 33016424 ps
CPU time 0.61 seconds
Started Jul 31 05:17:00 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 197976 kb
Host smart-8c19344e-7dc1-4969-a8bb-1b047c68d96a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669833786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1669833786
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2086063885
Short name T440
Test name
Test status
Simulation time 754606213 ps
CPU time 1 seconds
Started Jul 31 05:16:54 PM PDT 24
Finished Jul 31 05:16:55 PM PDT 24
Peak memory 198028 kb
Host smart-7ed27b0e-c9c7-4c88-8eff-9eec2f350d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086063885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2086063885
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2426713730
Short name T501
Test name
Test status
Simulation time 66376973 ps
CPU time 0.62 seconds
Started Jul 31 05:17:04 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 198032 kb
Host smart-47f213cb-8642-4072-8aec-523b485e2fa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426713730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2426713730
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3437055729
Short name T384
Test name
Test status
Simulation time 45967577 ps
CPU time 0.63 seconds
Started Jul 31 05:16:45 PM PDT 24
Finished Jul 31 05:16:46 PM PDT 24
Peak memory 198056 kb
Host smart-8df67450-5810-400a-a80a-18084907d5a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437055729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3437055729
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3624805376
Short name T182
Test name
Test status
Simulation time 45875536 ps
CPU time 0.71 seconds
Started Jul 31 05:16:47 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 201360 kb
Host smart-a13f8a5d-948b-4034-a3ad-2e1a047731ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624805376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3624805376
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2585288576
Short name T218
Test name
Test status
Simulation time 46620142 ps
CPU time 0.78 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 199116 kb
Host smart-784e289b-6b60-4a85-9c25-13a67bb456ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585288576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2585288576
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.2081773492
Short name T569
Test name
Test status
Simulation time 115633149 ps
CPU time 0.84 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:54 PM PDT 24
Peak memory 209520 kb
Host smart-ec908735-d9aa-44af-ae47-3cac78da48f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081773492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2081773492
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.512112940
Short name T303
Test name
Test status
Simulation time 65804457 ps
CPU time 0.84 seconds
Started Jul 31 05:16:55 PM PDT 24
Finished Jul 31 05:16:56 PM PDT 24
Peak memory 199328 kb
Host smart-cb3e047b-e13f-44ed-92a5-74a0a5755f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512112940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.512112940
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3283777895
Short name T553
Test name
Test status
Simulation time 88567740 ps
CPU time 0.64 seconds
Started Jul 31 05:16:54 PM PDT 24
Finished Jul 31 05:16:55 PM PDT 24
Peak memory 198532 kb
Host smart-133e3c0d-ddaa-4bba-b571-693ee5670ff8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283777895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3283777895
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2791133670
Short name T369
Test name
Test status
Simulation time 42831819 ps
CPU time 0.61 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 198444 kb
Host smart-bc82a268-27b5-4a89-b377-cdc945326f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791133670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2791133670
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2788381931
Short name T359
Test name
Test status
Simulation time 82608047 ps
CPU time 0.66 seconds
Started Jul 31 05:16:51 PM PDT 24
Finished Jul 31 05:16:52 PM PDT 24
Peak memory 199128 kb
Host smart-20b95137-08e5-4961-b79e-1a29ad7b3d68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788381931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2788381931
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3725405838
Short name T250
Test name
Test status
Simulation time 36595537 ps
CPU time 0.58 seconds
Started Jul 31 05:17:00 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 198052 kb
Host smart-9490081f-6fba-4b61-a59e-698dd6178071
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725405838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.3725405838
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1772944060
Short name T8
Test name
Test status
Simulation time 197727986 ps
CPU time 0.93 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 198420 kb
Host smart-87e9c3a1-fbdf-4728-8a22-5ecba7f59a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772944060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1772944060
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.4113343202
Short name T325
Test name
Test status
Simulation time 63408432 ps
CPU time 0.61 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198120 kb
Host smart-6d2b57b7-9772-4722-b538-6e390e7bd35e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113343202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.4113343202
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3785850421
Short name T97
Test name
Test status
Simulation time 49649408 ps
CPU time 0.64 seconds
Started Jul 31 05:16:56 PM PDT 24
Finished Jul 31 05:16:57 PM PDT 24
Peak memory 198156 kb
Host smart-cdb93851-702f-4f43-98dc-5a02b6a89b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785850421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3785850421
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1756905783
Short name T166
Test name
Test status
Simulation time 73173854 ps
CPU time 0.71 seconds
Started Jul 31 05:16:56 PM PDT 24
Finished Jul 31 05:16:57 PM PDT 24
Peak memory 201156 kb
Host smart-316c368a-a6a6-4f8c-aeed-bdfbc5797f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756905783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1756905783
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.472904600
Short name T594
Test name
Test status
Simulation time 59043698 ps
CPU time 0.86 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 199188 kb
Host smart-405602b9-9146-4027-9051-b910a08d8646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472904600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.472904600
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3893871222
Short name T572
Test name
Test status
Simulation time 103365419 ps
CPU time 1.07 seconds
Started Jul 31 05:16:54 PM PDT 24
Finished Jul 31 05:16:55 PM PDT 24
Peak memory 209464 kb
Host smart-08b9d6d8-f26e-4d98-9976-4c798af9e997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893871222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3893871222
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.13410991
Short name T597
Test name
Test status
Simulation time 198751022 ps
CPU time 0.75 seconds
Started Jul 31 05:16:59 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 198068 kb
Host smart-1150f0f5-fa50-4552-8dfd-73a0d0f92d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.13410991
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.3535370568
Short name T336
Test name
Test status
Simulation time 72867879 ps
CPU time 0.61 seconds
Started Jul 31 05:16:52 PM PDT 24
Finished Jul 31 05:16:53 PM PDT 24
Peak memory 198528 kb
Host smart-37d779ce-464e-4d1d-bd3d-312bed9cf540
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535370568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3535370568
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.348205022
Short name T53
Test name
Test status
Simulation time 44467821 ps
CPU time 0.74 seconds
Started Jul 31 05:16:53 PM PDT 24
Finished Jul 31 05:16:54 PM PDT 24
Peak memory 198824 kb
Host smart-9f594284-fce7-4464-befa-50db3dbf858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348205022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.348205022
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1367653589
Short name T196
Test name
Test status
Simulation time 114918239 ps
CPU time 0.66 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 199096 kb
Host smart-50008499-2951-4116-88ae-c49c81b91bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367653589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1367653589
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.145208619
Short name T233
Test name
Test status
Simulation time 39029173 ps
CPU time 0.58 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198084 kb
Host smart-7a9945f7-c393-4074-bce7-9d0a6f97bbc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145208619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_
malfunc.145208619
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3802764830
Short name T242
Test name
Test status
Simulation time 73186334 ps
CPU time 0.6 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198096 kb
Host smart-58149057-0740-4885-8e54-24b57887bca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802764830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3802764830
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.277684258
Short name T470
Test name
Test status
Simulation time 48733719 ps
CPU time 0.65 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198036 kb
Host smart-05289738-2f70-4b2b-91a1-c0e6768bdd1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277684258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.277684258
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.2325517956
Short name T382
Test name
Test status
Simulation time 81921366 ps
CPU time 0.69 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:02 PM PDT 24
Peak memory 201336 kb
Host smart-fb440588-045c-4741-ae64-f5a4a6c5e85c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325517956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.2325517956
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1374863412
Short name T363
Test name
Test status
Simulation time 76912953 ps
CPU time 0.8 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:02 PM PDT 24
Peak memory 198336 kb
Host smart-3194085e-1387-4154-9f36-5a528a1a555a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374863412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1374863412
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2680866866
Short name T564
Test name
Test status
Simulation time 98972039 ps
CPU time 0.89 seconds
Started Jul 31 05:16:50 PM PDT 24
Finished Jul 31 05:16:51 PM PDT 24
Peak memory 201296 kb
Host smart-aca32f89-0efd-4e3e-9d06-63804a1f28bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680866866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2680866866
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2867894722
Short name T411
Test name
Test status
Simulation time 56742860 ps
CPU time 0.83 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 198052 kb
Host smart-7138fdc5-aa14-4be9-b68f-ba854381b3e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867894722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2867894722
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2856845954
Short name T378
Test name
Test status
Simulation time 31771372 ps
CPU time 0.68 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:02 PM PDT 24
Peak memory 199364 kb
Host smart-f6ab6f93-5c76-4f22-8b0c-0f6076b9d9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856845954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2856845954
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1939903319
Short name T316
Test name
Test status
Simulation time 43847828 ps
CPU time 0.87 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 200224 kb
Host smart-8b334687-2ef4-463b-aeb1-6ce7d814132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939903319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1939903319
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3971019066
Short name T298
Test name
Test status
Simulation time 62138512 ps
CPU time 0.76 seconds
Started Jul 31 05:16:58 PM PDT 24
Finished Jul 31 05:16:59 PM PDT 24
Peak memory 198408 kb
Host smart-da4ad3e1-6611-48c0-b5bd-5add05a55341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971019066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3971019066
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.182267680
Short name T140
Test name
Test status
Simulation time 29741063 ps
CPU time 0.62 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 198008 kb
Host smart-ec62e027-aeac-4547-a788-9975d8e39243
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182267680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.182267680
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.766740079
Short name T33
Test name
Test status
Simulation time 161366634 ps
CPU time 1.01 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 198084 kb
Host smart-259e6af0-18c7-47d0-a01a-6041ea8e55e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766740079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.766740079
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.1899335264
Short name T439
Test name
Test status
Simulation time 104605570 ps
CPU time 0.6 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 198072 kb
Host smart-c1123ddf-f252-4332-9934-2cac31762403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899335264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1899335264
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2565119380
Short name T293
Test name
Test status
Simulation time 22421374 ps
CPU time 0.6 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 198396 kb
Host smart-814cfe4c-dfcf-459d-b7b2-8d9aebc59692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565119380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2565119380
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.444645571
Short name T607
Test name
Test status
Simulation time 44650098 ps
CPU time 0.69 seconds
Started Jul 31 05:16:58 PM PDT 24
Finished Jul 31 05:16:59 PM PDT 24
Peak memory 201404 kb
Host smart-e768128d-320c-41fe-a26a-7ca6e144987c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444645571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.444645571
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.2844581314
Short name T44
Test name
Test status
Simulation time 48641340 ps
CPU time 0.68 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 198324 kb
Host smart-34e070ff-d892-4e73-a8e3-2046c144fc19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844581314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.2844581314
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2296445910
Short name T300
Test name
Test status
Simulation time 27882502 ps
CPU time 0.75 seconds
Started Jul 31 05:17:01 PM PDT 24
Finished Jul 31 05:17:02 PM PDT 24
Peak memory 198400 kb
Host smart-658644b5-f1e3-40cb-bc2d-4c96e8330377
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296445910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2296445910
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1492742107
Short name T613
Test name
Test status
Simulation time 112766963 ps
CPU time 0.87 seconds
Started Jul 31 05:16:59 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 209436 kb
Host smart-ed7385ea-bc60-493f-8b56-77edd1211fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492742107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1492742107
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.688073627
Short name T402
Test name
Test status
Simulation time 70883319 ps
CPU time 0.82 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 199192 kb
Host smart-80efbb2a-3643-43f7-be0f-f7209d58577d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688073627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_
mubi.688073627
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.138677972
Short name T83
Test name
Test status
Simulation time 54595031 ps
CPU time 0.63 seconds
Started Jul 31 05:17:07 PM PDT 24
Finished Jul 31 05:17:08 PM PDT 24
Peak memory 198472 kb
Host smart-14b8f3e3-f62e-4ac1-aca2-a665b42b238a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138677972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.138677972
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3154921514
Short name T530
Test name
Test status
Simulation time 37301552 ps
CPU time 1.16 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 200928 kb
Host smart-0abc7001-693a-4bf2-845f-1f2090c29a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154921514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3154921514
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2198146478
Short name T387
Test name
Test status
Simulation time 61778696 ps
CPU time 0.7 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 198476 kb
Host smart-4eaa4b5a-61d1-422d-bfa9-6f582446c76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198146478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2198146478
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1145572178
Short name T374
Test name
Test status
Simulation time 32102071 ps
CPU time 0.61 seconds
Started Jul 31 05:17:07 PM PDT 24
Finished Jul 31 05:17:08 PM PDT 24
Peak memory 198056 kb
Host smart-da939d9d-ebd9-4bcb-9056-7647e6c264b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145572178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1145572178
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3690035001
Short name T317
Test name
Test status
Simulation time 567629072 ps
CPU time 0.9 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 197660 kb
Host smart-4389ad6a-5a09-46a5-a399-9f5d9f6da82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690035001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3690035001
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2151998711
Short name T598
Test name
Test status
Simulation time 35461154 ps
CPU time 0.62 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 197956 kb
Host smart-09045d69-0254-4769-aec1-a82a0d8c6ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151998711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2151998711
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.785434937
Short name T238
Test name
Test status
Simulation time 94129375 ps
CPU time 0.6 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 198324 kb
Host smart-97e57c4c-88e1-4c21-a220-d26c86c48b7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785434937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.785434937
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2510404135
Short name T156
Test name
Test status
Simulation time 45511756 ps
CPU time 0.73 seconds
Started Jul 31 05:16:58 PM PDT 24
Finished Jul 31 05:16:59 PM PDT 24
Peak memory 201436 kb
Host smart-7740a14b-2cbe-498f-a06c-c18ea7499123
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510404135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2510404135
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.2379152811
Short name T223
Test name
Test status
Simulation time 59373245 ps
CPU time 0.84 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 199076 kb
Host smart-434f7eeb-09d3-45c8-af21-4443d08536c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379152811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2379152811
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3594133011
Short name T596
Test name
Test status
Simulation time 145681081 ps
CPU time 0.81 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:13 PM PDT 24
Peak memory 209524 kb
Host smart-73eed215-adf7-4657-8a9a-54848d8c3560
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594133011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3594133011
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1733608088
Short name T481
Test name
Test status
Simulation time 75062974 ps
CPU time 0.78 seconds
Started Jul 31 05:16:58 PM PDT 24
Finished Jul 31 05:16:59 PM PDT 24
Peak memory 198068 kb
Host smart-d6f0fe9c-10c7-474f-8a9a-b6b303782b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733608088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1733608088
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3601220367
Short name T358
Test name
Test status
Simulation time 32180301 ps
CPU time 0.68 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:08 PM PDT 24
Peak memory 199348 kb
Host smart-bf9c80a6-174e-4304-ad32-3e6ed3562dde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601220367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3601220367
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2744010175
Short name T590
Test name
Test status
Simulation time 54599865 ps
CPU time 0.67 seconds
Started Jul 31 05:16:59 PM PDT 24
Finished Jul 31 05:17:00 PM PDT 24
Peak memory 198668 kb
Host smart-59d97370-230d-4ff1-a860-c14f8aeed71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744010175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2744010175
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2675305463
Short name T429
Test name
Test status
Simulation time 85300658 ps
CPU time 0.67 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 199160 kb
Host smart-3cb6ef59-a604-435c-ad7e-68032eafa434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675305463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.2675305463
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2725328751
Short name T245
Test name
Test status
Simulation time 39657025 ps
CPU time 0.58 seconds
Started Jul 31 05:17:22 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 197948 kb
Host smart-f4076b13-f83c-47ae-8291-af392981b9fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725328751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2725328751
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.560650095
Short name T265
Test name
Test status
Simulation time 686621165 ps
CPU time 0.91 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:13 PM PDT 24
Peak memory 198308 kb
Host smart-735b0f93-52bf-4497-a79a-4864a4e2d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560650095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.560650095
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1489436690
Short name T426
Test name
Test status
Simulation time 35344622 ps
CPU time 0.66 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 198100 kb
Host smart-14436105-a75c-42a1-a09f-00acd546c657
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489436690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1489436690
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1911180520
Short name T235
Test name
Test status
Simulation time 37040763 ps
CPU time 0.65 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198392 kb
Host smart-f318b1d0-d10b-4081-ba73-6578196eed97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911180520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1911180520
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1709038289
Short name T609
Test name
Test status
Simulation time 78711370 ps
CPU time 0.66 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 201364 kb
Host smart-0102c423-5b6f-4d60-9320-7c5bfb15e063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709038289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1709038289
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.2891557818
Short name T246
Test name
Test status
Simulation time 89088017 ps
CPU time 0.7 seconds
Started Jul 31 05:17:02 PM PDT 24
Finished Jul 31 05:17:03 PM PDT 24
Peak memory 198340 kb
Host smart-1f8c5e3a-d8d7-45b1-9cd5-4c10fba1739f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891557818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2891557818
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3755757471
Short name T210
Test name
Test status
Simulation time 96972279 ps
CPU time 0.94 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 209424 kb
Host smart-7f35144f-1595-4b43-89cb-0a24e51387e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755757471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3755757471
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4221600750
Short name T621
Test name
Test status
Simulation time 60838457 ps
CPU time 0.72 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198140 kb
Host smart-f3c9f7aa-ab7c-490b-922b-45e407393405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221600750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4221600750
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.4263196364
Short name T27
Test name
Test status
Simulation time 61918489 ps
CPU time 0.61 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198492 kb
Host smart-de0a870f-69c7-48b6-908b-6879c9038b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263196364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.4263196364
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.626319725
Short name T538
Test name
Test status
Simulation time 397400327 ps
CPU time 0.86 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 200152 kb
Host smart-91f1528b-f11c-424b-a722-78d0acd16c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626319725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.626319725
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2750088827
Short name T422
Test name
Test status
Simulation time 63251136 ps
CPU time 0.71 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 199148 kb
Host smart-8cb5b2c4-76dc-4414-9c27-9bad3e157822
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750088827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2750088827
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3118102440
Short name T450
Test name
Test status
Simulation time 80178803 ps
CPU time 0.59 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 198056 kb
Host smart-95875664-bf91-4c7f-b1b1-b201577a383f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118102440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3118102440
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.4245475197
Short name T537
Test name
Test status
Simulation time 158580063 ps
CPU time 0.97 seconds
Started Jul 31 05:16:57 PM PDT 24
Finished Jul 31 05:16:58 PM PDT 24
Peak memory 198368 kb
Host smart-3968bc40-e9eb-48d4-abf0-1bd6c43d70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245475197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.4245475197
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3345717440
Short name T435
Test name
Test status
Simulation time 56028102 ps
CPU time 0.69 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 197992 kb
Host smart-2a98a7ae-b430-43b3-99b4-4456d4f01b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345717440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3345717440
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.682849636
Short name T491
Test name
Test status
Simulation time 50680439 ps
CPU time 0.65 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198096 kb
Host smart-b8986a1b-ea88-47aa-9d67-ec754332245f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682849636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.682849636
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1626176821
Short name T602
Test name
Test status
Simulation time 70825146 ps
CPU time 0.73 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 201168 kb
Host smart-3d122107-8bd5-4085-b3f0-7b8ae412c3b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626176821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1626176821
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1450096428
Short name T521
Test name
Test status
Simulation time 25695117 ps
CPU time 0.66 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 198332 kb
Host smart-410bd66e-c7f2-48ac-9695-2b57d0908828
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450096428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1450096428
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.4127868293
Short name T615
Test name
Test status
Simulation time 117360649 ps
CPU time 0.84 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 209524 kb
Host smart-7399c983-15b9-4ca1-a3fb-f1a7f74be724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127868293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.4127868293
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4085081459
Short name T567
Test name
Test status
Simulation time 84478518 ps
CPU time 0.7 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198152 kb
Host smart-233d49e2-ac91-4d4f-850d-47c723228f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085081459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4085081459
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.4229339105
Short name T79
Test name
Test status
Simulation time 39799436 ps
CPU time 0.66 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198516 kb
Host smart-4deae201-dcbe-4c54-baa1-6bbc071a8d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229339105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.4229339105
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3347463257
Short name T552
Test name
Test status
Simulation time 19427947 ps
CPU time 0.66 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 199168 kb
Host smart-6006cd4c-a548-4257-8f77-c4a3c3e7f6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347463257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3347463257
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3918483558
Short name T512
Test name
Test status
Simulation time 69563121 ps
CPU time 0.75 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 199120 kb
Host smart-3c9c2b95-fd57-476f-9a91-a75b9465bd08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918483558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3918483558
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.245376164
Short name T277
Test name
Test status
Simulation time 30616905 ps
CPU time 0.65 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 197316 kb
Host smart-0d3edb29-2001-4943-8475-26c76173c5a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245376164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.245376164
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.417538997
Short name T495
Test name
Test status
Simulation time 308836305 ps
CPU time 0.96 seconds
Started Jul 31 05:17:21 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 198128 kb
Host smart-ea659a43-7e40-420e-a2bc-06bf658505bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417538997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.417538997
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1741072494
Short name T474
Test name
Test status
Simulation time 112267259 ps
CPU time 0.6 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 198244 kb
Host smart-b82bf88c-7a10-4e83-89bd-9d571372e458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741072494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1741072494
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2031249889
Short name T503
Test name
Test status
Simulation time 33530385 ps
CPU time 0.61 seconds
Started Jul 31 05:17:20 PM PDT 24
Finished Jul 31 05:17:21 PM PDT 24
Peak memory 198088 kb
Host smart-f44b56e8-0ae8-448a-aba2-48139cf3f64b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031249889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2031249889
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3049268202
Short name T593
Test name
Test status
Simulation time 87708792 ps
CPU time 0.72 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 199116 kb
Host smart-73a433de-554f-48c0-8810-1867774accf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049268202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3049268202
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1167440234
Short name T549
Test name
Test status
Simulation time 120433648 ps
CPU time 0.8 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 209424 kb
Host smart-ac3f8f44-14fa-4983-bff3-8df913fbe06a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167440234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1167440234
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.490368631
Short name T63
Test name
Test status
Simulation time 121459521 ps
CPU time 0.84 seconds
Started Jul 31 05:17:07 PM PDT 24
Finished Jul 31 05:17:08 PM PDT 24
Peak memory 199340 kb
Host smart-452fe584-2e81-4aae-bda0-56a69c853646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490368631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_
mubi.490368631
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.786275869
Short name T295
Test name
Test status
Simulation time 26860246 ps
CPU time 0.7 seconds
Started Jul 31 05:15:30 PM PDT 24
Finished Jul 31 05:15:31 PM PDT 24
Peak memory 198816 kb
Host smart-0695b5ef-dfd3-439e-8464-5fd42081c29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786275869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.786275869
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1283610946
Short name T208
Test name
Test status
Simulation time 43589959 ps
CPU time 0.73 seconds
Started Jul 31 05:15:31 PM PDT 24
Finished Jul 31 05:15:32 PM PDT 24
Peak memory 198468 kb
Host smart-b8933c1d-8e03-4b07-a161-f397d2be6451
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283610946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1283610946
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2916915095
Short name T518
Test name
Test status
Simulation time 29023665 ps
CPU time 0.62 seconds
Started Jul 31 05:15:24 PM PDT 24
Finished Jul 31 05:15:25 PM PDT 24
Peak memory 197968 kb
Host smart-d24263a6-b8aa-4f3a-877e-b48b72e799a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916915095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2916915095
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3743955940
Short name T465
Test name
Test status
Simulation time 648447906 ps
CPU time 0.91 seconds
Started Jul 31 05:15:18 PM PDT 24
Finished Jul 31 05:15:19 PM PDT 24
Peak memory 198132 kb
Host smart-42896c7b-1765-4fd6-999c-364d2684a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743955940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3743955940
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.2148985668
Short name T229
Test name
Test status
Simulation time 44005816 ps
CPU time 0.69 seconds
Started Jul 31 05:15:30 PM PDT 24
Finished Jul 31 05:15:36 PM PDT 24
Peak memory 198076 kb
Host smart-ee37bbda-5dbc-48a1-9cc3-7e7c48e037e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148985668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2148985668
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.1306587142
Short name T281
Test name
Test status
Simulation time 47009821 ps
CPU time 0.64 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:27 PM PDT 24
Peak memory 198420 kb
Host smart-c12d1cb5-aecd-4335-9786-5ee37c5afcfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306587142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1306587142
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.3952294161
Short name T483
Test name
Test status
Simulation time 234721436 ps
CPU time 0.63 seconds
Started Jul 31 05:15:20 PM PDT 24
Finished Jul 31 05:15:20 PM PDT 24
Peak memory 201420 kb
Host smart-e267f525-30d6-47d2-89e8-e7056f09cd22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952294161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.3952294161
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.2491665865
Short name T216
Test name
Test status
Simulation time 68973885 ps
CPU time 0.79 seconds
Started Jul 31 05:15:17 PM PDT 24
Finished Jul 31 05:15:18 PM PDT 24
Peak memory 199164 kb
Host smart-6a6b6358-2953-4772-a8f2-ef307b94d8ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491665865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2491665865
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3034688680
Short name T58
Test name
Test status
Simulation time 37002231 ps
CPU time 0.69 seconds
Started Jul 31 05:15:32 PM PDT 24
Finished Jul 31 05:15:32 PM PDT 24
Peak memory 198584 kb
Host smart-1ca6e52f-19a4-459b-8adb-7b7a4f425b06
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034688680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.3034688680
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.4199780723
Short name T391
Test name
Test status
Simulation time 60584064 ps
CPU time 0.8 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 197932 kb
Host smart-b39a58ed-9650-4776-b4f2-1f3607256b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199780723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4199780723
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.3459681161
Short name T373
Test name
Test status
Simulation time 115253001 ps
CPU time 0.64 seconds
Started Jul 31 05:15:18 PM PDT 24
Finished Jul 31 05:15:19 PM PDT 24
Peak memory 198520 kb
Host smart-52cf3066-29fb-4fc9-8762-d1bd8e0c4c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459681161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.3459681161
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2767644742
Short name T188
Test name
Test status
Simulation time 35527550 ps
CPU time 1.04 seconds
Started Jul 31 05:17:03 PM PDT 24
Finished Jul 31 05:17:04 PM PDT 24
Peak memory 200920 kb
Host smart-8ff7062d-12c6-48c5-91d6-f84f0d299a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767644742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2767644742
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3160250144
Short name T284
Test name
Test status
Simulation time 53423289 ps
CPU time 0.76 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 198664 kb
Host smart-416631f0-8ead-4ebb-b785-4d844720ffd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160250144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3160250144
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1280665132
Short name T527
Test name
Test status
Simulation time 32731588 ps
CPU time 0.59 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 198076 kb
Host smart-a120ed9e-e623-4894-bfd6-78f121181703
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280665132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1280665132
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.80184498
Short name T6
Test name
Test status
Simulation time 1004114408 ps
CPU time 0.92 seconds
Started Jul 31 05:17:08 PM PDT 24
Finished Jul 31 05:17:09 PM PDT 24
Peak memory 198020 kb
Host smart-ab7848c2-9faf-4c3a-a0be-54e9f6b67892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80184498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.80184498
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.406857425
Short name T464
Test name
Test status
Simulation time 69411908 ps
CPU time 0.63 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 197528 kb
Host smart-a6a85988-9407-4f67-9a90-cd4f8c400bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406857425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.406857425
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2443747244
Short name T580
Test name
Test status
Simulation time 36228220 ps
CPU time 0.58 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 198044 kb
Host smart-ef67b9f9-1531-46f8-bcca-583f1e44f1d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443747244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2443747244
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2816062549
Short name T555
Test name
Test status
Simulation time 57013297 ps
CPU time 0.68 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 201340 kb
Host smart-00168d65-b742-49af-bc2f-f48a77986c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816062549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2816062549
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.910022992
Short name T239
Test name
Test status
Simulation time 72732110 ps
CPU time 0.65 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 198328 kb
Host smart-e9c08f40-976c-4c7c-9d06-2552f67989b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910022992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.910022992
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.784426559
Short name T3
Test name
Test status
Simulation time 118282811 ps
CPU time 0.88 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 209456 kb
Host smart-cef07765-eeed-45c0-a926-e1405cd71ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784426559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.784426559
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2139885195
Short name T225
Test name
Test status
Simulation time 70396967 ps
CPU time 0.78 seconds
Started Jul 31 05:17:13 PM PDT 24
Finished Jul 31 05:17:14 PM PDT 24
Peak memory 198132 kb
Host smart-0bf1993e-7c4a-4761-937c-f831adc2971b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139885195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2139885195
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3403031727
Short name T356
Test name
Test status
Simulation time 31133278 ps
CPU time 0.69 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 199380 kb
Host smart-9e545cb4-fdf0-4dd3-bca7-91eb2cf4aba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403031727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3403031727
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3278590017
Short name T419
Test name
Test status
Simulation time 52730428 ps
CPU time 0.93 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 200332 kb
Host smart-2b6737f2-56fd-4bd6-a1a9-defc7240b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278590017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3278590017
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.323252680
Short name T252
Test name
Test status
Simulation time 28941459 ps
CPU time 0.66 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 197924 kb
Host smart-25eeef9d-977a-4c0b-bc00-76e7adc277ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323252680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_
malfunc.323252680
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.226569165
Short name T389
Test name
Test status
Simulation time 879343242 ps
CPU time 0.95 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:14 PM PDT 24
Peak memory 198376 kb
Host smart-448cc16d-fa07-4a58-a129-b1669e3cf6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226569165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.226569165
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3570978684
Short name T270
Test name
Test status
Simulation time 37381451 ps
CPU time 0.62 seconds
Started Jul 31 05:17:22 PM PDT 24
Finished Jul 31 05:17:23 PM PDT 24
Peak memory 197368 kb
Host smart-62b51026-6692-4f75-aaca-280c1c7c8645
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570978684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3570978684
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.2019171303
Short name T380
Test name
Test status
Simulation time 43371324 ps
CPU time 0.63 seconds
Started Jul 31 05:17:40 PM PDT 24
Finished Jul 31 05:17:40 PM PDT 24
Peak memory 198096 kb
Host smart-720c6902-3674-4b9e-abbe-1f10b2966b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019171303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2019171303
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1656158827
Short name T176
Test name
Test status
Simulation time 52780731 ps
CPU time 0.69 seconds
Started Jul 31 05:17:07 PM PDT 24
Finished Jul 31 05:17:08 PM PDT 24
Peak memory 201376 kb
Host smart-5370b1ff-5677-45ad-9fad-8f74e34b72bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656158827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.1656158827
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.527377454
Short name T220
Test name
Test status
Simulation time 55117412 ps
CPU time 0.61 seconds
Started Jul 31 05:17:22 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 197628 kb
Host smart-738accd4-2055-4fb7-b210-b6cf30e1deb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527377454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.527377454
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.700068419
Short name T214
Test name
Test status
Simulation time 158458916 ps
CPU time 0.8 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 209440 kb
Host smart-34e8b746-254c-4289-a310-acc8f4f76ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700068419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.700068419
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2130288845
Short name T230
Test name
Test status
Simulation time 154057448 ps
CPU time 0.67 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 198056 kb
Host smart-71ffbdcf-f6aa-4684-a5a2-812e7071ff1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130288845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2130288845
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.2438301334
Short name T433
Test name
Test status
Simulation time 40101445 ps
CPU time 0.63 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198360 kb
Host smart-f9bed03c-c905-449d-9e21-09a4d8b9d5cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438301334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.2438301334
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3717103451
Short name T463
Test name
Test status
Simulation time 79168728 ps
CPU time 0.73 seconds
Started Jul 31 05:17:25 PM PDT 24
Finished Jul 31 05:17:26 PM PDT 24
Peak memory 198844 kb
Host smart-6b803a4b-089a-4534-8f56-766f1231a536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717103451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3717103451
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.4052569097
Short name T199
Test name
Test status
Simulation time 61493348 ps
CPU time 0.62 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:14 PM PDT 24
Peak memory 198256 kb
Host smart-5e8e6247-feb4-492a-8273-e164ac83c3ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052569097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.4052569097
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.999053153
Short name T142
Test name
Test status
Simulation time 29418301 ps
CPU time 0.62 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 198020 kb
Host smart-e93737c3-9f96-47be-8b33-759ecbab1967
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999053153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.999053153
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.489343428
Short name T500
Test name
Test status
Simulation time 631356975 ps
CPU time 1.02 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 198108 kb
Host smart-d6400d24-decb-4353-b326-3d9a84f14db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489343428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.489343428
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1722223625
Short name T341
Test name
Test status
Simulation time 40353881 ps
CPU time 0.65 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:13 PM PDT 24
Peak memory 197044 kb
Host smart-70e7a3b2-2e6d-450a-99d5-f90b38eb0a55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722223625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1722223625
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3873204485
Short name T405
Test name
Test status
Simulation time 44362571 ps
CPU time 0.67 seconds
Started Jul 31 05:17:12 PM PDT 24
Finished Jul 31 05:17:13 PM PDT 24
Peak memory 197992 kb
Host smart-145ef717-a9e2-483b-82a4-ca517370409d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873204485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3873204485
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.1087872459
Short name T162
Test name
Test status
Simulation time 89490399 ps
CPU time 0.65 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 201336 kb
Host smart-255419c1-27e7-4eb9-9918-23da5efb2711
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087872459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.1087872459
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.4037654176
Short name T595
Test name
Test status
Simulation time 60672180 ps
CPU time 0.64 seconds
Started Jul 31 05:17:24 PM PDT 24
Finished Jul 31 05:17:25 PM PDT 24
Peak memory 198308 kb
Host smart-e22706d2-2400-494b-a4d0-c3f63aae12e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037654176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.4037654176
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2847542934
Short name T310
Test name
Test status
Simulation time 154533867 ps
CPU time 0.74 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 209480 kb
Host smart-7c8b8d5c-4e8d-4f99-8271-ea086dcea64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847542934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2847542934
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3376473352
Short name T431
Test name
Test status
Simulation time 99767363 ps
CPU time 0.78 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 199280 kb
Host smart-e11a6543-9ef6-4f1f-9582-9e4c81aacbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376473352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3376473352
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1082527058
Short name T311
Test name
Test status
Simulation time 57656950 ps
CPU time 0.67 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 199400 kb
Host smart-288a7eaa-d6bb-4e72-a4fb-b22821f1aecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082527058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1082527058
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.2670586581
Short name T504
Test name
Test status
Simulation time 26730333 ps
CPU time 0.91 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 200716 kb
Host smart-38621da0-fd89-4383-b6d0-86e21abeffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670586581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2670586581
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3564765032
Short name T418
Test name
Test status
Simulation time 50096788 ps
CPU time 0.75 seconds
Started Jul 31 05:17:29 PM PDT 24
Finished Jul 31 05:17:30 PM PDT 24
Peak memory 198632 kb
Host smart-9b0be9fd-aca5-4c4b-94a6-c8044214e38c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564765032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3564765032
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2993011999
Short name T367
Test name
Test status
Simulation time 30426120 ps
CPU time 0.61 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 197988 kb
Host smart-abacb4ce-bc25-47d6-b132-d63f61707657
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993011999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2993011999
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.156514533
Short name T262
Test name
Test status
Simulation time 165389478 ps
CPU time 0.96 seconds
Started Jul 31 05:17:25 PM PDT 24
Finished Jul 31 05:17:26 PM PDT 24
Peak memory 198068 kb
Host smart-8c5de291-ad10-4c00-a180-fe1dbeb7990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156514533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.156514533
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.1002913678
Short name T267
Test name
Test status
Simulation time 38449310 ps
CPU time 0.69 seconds
Started Jul 31 05:17:19 PM PDT 24
Finished Jul 31 05:17:20 PM PDT 24
Peak memory 197996 kb
Host smart-1b97f3c6-1206-4383-9cc2-a2ed52ff8920
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002913678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1002913678
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.623037687
Short name T219
Test name
Test status
Simulation time 88883872 ps
CPU time 0.58 seconds
Started Jul 31 05:17:06 PM PDT 24
Finished Jul 31 05:17:07 PM PDT 24
Peak memory 198012 kb
Host smart-3a65184f-858f-4253-9952-9527399169f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623037687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.623037687
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.1271574496
Short name T273
Test name
Test status
Simulation time 71005993 ps
CPU time 0.7 seconds
Started Jul 31 05:17:19 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 199152 kb
Host smart-9d89e492-f795-4c32-b47b-1651d3b1ff9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271574496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.1271574496
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1947434683
Short name T397
Test name
Test status
Simulation time 112956501 ps
CPU time 0.91 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 209404 kb
Host smart-9c1ba4c5-b89c-4f6a-bfbe-7c67c4089b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947434683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1947434683
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3615933191
Short name T449
Test name
Test status
Simulation time 67778709 ps
CPU time 0.88 seconds
Started Jul 31 05:17:09 PM PDT 24
Finished Jul 31 05:17:10 PM PDT 24
Peak memory 199172 kb
Host smart-5f290887-e1ad-4e27-8851-70f63e72b017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615933191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3615933191
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.4111618638
Short name T444
Test name
Test status
Simulation time 29653736 ps
CPU time 0.63 seconds
Started Jul 31 05:17:20 PM PDT 24
Finished Jul 31 05:17:20 PM PDT 24
Peak memory 198516 kb
Host smart-e97e22aa-2834-40e6-beee-832be7c0b758
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111618638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.4111618638
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2851221055
Short name T408
Test name
Test status
Simulation time 94997756 ps
CPU time 0.74 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:14 PM PDT 24
Peak memory 198816 kb
Host smart-b1694a05-1e5d-4d13-ab27-0811261b2b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851221055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2851221055
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1864505570
Short name T321
Test name
Test status
Simulation time 104228155 ps
CPU time 0.63 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 198404 kb
Host smart-ac4db9ae-ac06-4f31-b622-cf1da688ad01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864505570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1864505570
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3677230124
Short name T338
Test name
Test status
Simulation time 28020114 ps
CPU time 0.66 seconds
Started Jul 31 05:17:19 PM PDT 24
Finished Jul 31 05:17:20 PM PDT 24
Peak memory 197228 kb
Host smart-7bc9b205-0287-4980-80b9-e9c4e5bf5495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677230124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3677230124
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.496155253
Short name T329
Test name
Test status
Simulation time 597336321 ps
CPU time 0.91 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198432 kb
Host smart-5ad1e523-43cf-4e9b-8ce3-09d1bd4aac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496155253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.496155253
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.1724970941
Short name T529
Test name
Test status
Simulation time 68995087 ps
CPU time 0.64 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 197320 kb
Host smart-a63361b0-4c36-44c7-be84-db72710949b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724970941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1724970941
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3735932569
Short name T410
Test name
Test status
Simulation time 36336431 ps
CPU time 0.6 seconds
Started Jul 31 05:17:25 PM PDT 24
Finished Jul 31 05:17:31 PM PDT 24
Peak memory 198044 kb
Host smart-c1384ad6-603b-4995-b9d1-aa6af730695f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735932569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3735932569
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3040196069
Short name T248
Test name
Test status
Simulation time 187149581 ps
CPU time 0.68 seconds
Started Jul 31 05:17:30 PM PDT 24
Finished Jul 31 05:17:31 PM PDT 24
Peak memory 198380 kb
Host smart-7f6f3f36-8b52-4cdf-82fb-5d700abe8e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040196069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3040196069
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.4157768642
Short name T535
Test name
Test status
Simulation time 112938295 ps
CPU time 0.94 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 209372 kb
Host smart-840d4e44-0aa2-406e-97dc-0d77ced0c1c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157768642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.4157768642
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3726536270
Short name T499
Test name
Test status
Simulation time 105224676 ps
CPU time 0.87 seconds
Started Jul 31 05:17:23 PM PDT 24
Finished Jul 31 05:17:24 PM PDT 24
Peak memory 199224 kb
Host smart-e79eacf9-9d2b-42b3-9a5b-2e5efdd1cff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726536270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3726536270
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.3519232671
Short name T85
Test name
Test status
Simulation time 31317757 ps
CPU time 0.71 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 198488 kb
Host smart-c080ff13-805c-40ec-ad10-3d2a7a4f2b04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519232671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3519232671
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3761672465
Short name T102
Test name
Test status
Simulation time 32268434 ps
CPU time 0.99 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 200936 kb
Host smart-f2d5a667-9588-4802-ad76-122c8fbccf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761672465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3761672465
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2660181206
Short name T201
Test name
Test status
Simulation time 55883579 ps
CPU time 0.83 seconds
Started Jul 31 05:17:27 PM PDT 24
Finished Jul 31 05:17:28 PM PDT 24
Peak memory 199200 kb
Host smart-3dad64aa-9b21-4f1f-a299-00b6a50e6e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660181206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2660181206
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3912570226
Short name T385
Test name
Test status
Simulation time 31431745 ps
CPU time 0.61 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 198024 kb
Host smart-41d4d19e-2ebd-4cf0-b8c2-3cb56b95de76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912570226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3912570226
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2039869881
Short name T287
Test name
Test status
Simulation time 749763240 ps
CPU time 0.92 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 198136 kb
Host smart-825d8c36-48e2-4d95-84b2-8a8c9827e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039869881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2039869881
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3570352796
Short name T15
Test name
Test status
Simulation time 39961785 ps
CPU time 0.64 seconds
Started Jul 31 05:17:26 PM PDT 24
Finished Jul 31 05:17:31 PM PDT 24
Peak memory 198108 kb
Host smart-43b14602-e790-43f7-9e60-f3f5a28a26a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570352796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3570352796
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.2916378266
Short name T477
Test name
Test status
Simulation time 35708747 ps
CPU time 0.59 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198068 kb
Host smart-66e83537-a25b-41cd-95a9-5ce2d2aec6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916378266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2916378266
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1916582329
Short name T173
Test name
Test status
Simulation time 84613006 ps
CPU time 0.66 seconds
Started Jul 31 05:17:37 PM PDT 24
Finished Jul 31 05:17:38 PM PDT 24
Peak memory 201420 kb
Host smart-683f274f-6c98-4cd0-ae9b-9647bee779ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916582329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.1916582329
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.332121320
Short name T462
Test name
Test status
Simulation time 45284105 ps
CPU time 0.68 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 198364 kb
Host smart-bc2b216b-9541-4f26-981a-37edead4aa35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332121320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.332121320
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.3612158238
Short name T256
Test name
Test status
Simulation time 110016867 ps
CPU time 0.91 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 209500 kb
Host smart-f969e45a-8df7-471f-95f5-27fb2b65660d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612158238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3612158238
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.4103799262
Short name T617
Test name
Test status
Simulation time 93211532 ps
CPU time 0.7 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:16 PM PDT 24
Peak memory 197972 kb
Host smart-e2370967-7f7d-4eee-b456-537bd1ceda8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103799262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4103799262
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1304209900
Short name T522
Test name
Test status
Simulation time 29460941 ps
CPU time 0.62 seconds
Started Jul 31 05:17:26 PM PDT 24
Finished Jul 31 05:17:27 PM PDT 24
Peak memory 198492 kb
Host smart-587539cf-2848-40c2-8f81-17e056febd46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304209900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1304209900
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3660307224
Short name T620
Test name
Test status
Simulation time 22760077 ps
CPU time 0.71 seconds
Started Jul 31 05:17:38 PM PDT 24
Finished Jul 31 05:17:39 PM PDT 24
Peak memory 198832 kb
Host smart-6210a550-878e-49ca-aa0a-ec4253763a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660307224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3660307224
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.3592619215
Short name T498
Test name
Test status
Simulation time 58619967 ps
CPU time 0.68 seconds
Started Jul 31 05:17:34 PM PDT 24
Finished Jul 31 05:17:35 PM PDT 24
Peak memory 199176 kb
Host smart-43dd38c9-e2c1-4f34-8a28-6b9412f88c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592619215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.3592619215
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3722728035
Short name T383
Test name
Test status
Simulation time 85769559 ps
CPU time 0.59 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 198096 kb
Host smart-0d98eb83-d742-49d7-aa0e-5074fe19330b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722728035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3722728035
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.381392258
Short name T290
Test name
Test status
Simulation time 326211267 ps
CPU time 0.96 seconds
Started Jul 31 05:17:05 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 198060 kb
Host smart-029bc48e-5dfb-48df-96f4-cbeaab578895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381392258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.381392258
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.2018032774
Short name T280
Test name
Test status
Simulation time 70176641 ps
CPU time 0.58 seconds
Started Jul 31 05:17:15 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 198024 kb
Host smart-d772b773-1218-4abe-8bdd-7a5eca3a2074
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018032774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2018032774
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.416988420
Short name T350
Test name
Test status
Simulation time 55462748 ps
CPU time 0.64 seconds
Started Jul 31 05:17:10 PM PDT 24
Finished Jul 31 05:17:11 PM PDT 24
Peak memory 198064 kb
Host smart-5f766ac2-1556-4023-9af1-4ac649c331f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416988420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.416988420
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1085641199
Short name T152
Test name
Test status
Simulation time 260445343 ps
CPU time 0.63 seconds
Started Jul 31 05:17:48 PM PDT 24
Finished Jul 31 05:17:48 PM PDT 24
Peak memory 201384 kb
Host smart-9dc4a51c-6aa2-4fd7-95c9-47a6797fc6fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085641199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1085641199
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2060775072
Short name T453
Test name
Test status
Simulation time 57359528 ps
CPU time 0.63 seconds
Started Jul 31 05:17:28 PM PDT 24
Finished Jul 31 05:17:28 PM PDT 24
Peak memory 199164 kb
Host smart-398348c0-b8ec-4f45-ac1e-70e5f18bb7e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060775072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2060775072
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1604082366
Short name T375
Test name
Test status
Simulation time 104102610 ps
CPU time 0.92 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 209548 kb
Host smart-dcde9f8e-86c4-4292-9efe-d24f0081304f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604082366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1604082366
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.4150392460
Short name T217
Test name
Test status
Simulation time 57966424 ps
CPU time 0.7 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 198108 kb
Host smart-d8fde3e3-3ab0-4a29-8456-4693f61a4d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150392460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4150392460
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3640840293
Short name T340
Test name
Test status
Simulation time 60039847 ps
CPU time 0.69 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 199340 kb
Host smart-3861bc96-82c8-4bde-bec0-d9ed19374468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640840293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3640840293
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.580897828
Short name T103
Test name
Test status
Simulation time 32856928 ps
CPU time 1.02 seconds
Started Jul 31 05:17:11 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 200576 kb
Host smart-47d80c84-2896-4547-b212-6e94b15bdf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580897828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.580897828
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1833212419
Short name T198
Test name
Test status
Simulation time 60090242 ps
CPU time 0.76 seconds
Started Jul 31 05:17:21 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 199000 kb
Host smart-be395af8-76fd-42c9-b86c-e3f882b3db32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833212419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.1833212419
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1314817403
Short name T573
Test name
Test status
Simulation time 30889358 ps
CPU time 0.63 seconds
Started Jul 31 05:17:21 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 198004 kb
Host smart-47de13c4-575d-4542-9d94-633a52c725df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314817403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1314817403
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.2244730855
Short name T448
Test name
Test status
Simulation time 358699765 ps
CPU time 0.91 seconds
Started Jul 31 05:17:20 PM PDT 24
Finished Jul 31 05:17:21 PM PDT 24
Peak memory 198140 kb
Host smart-3ab22442-9969-438b-8a24-19c9b6919024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244730855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2244730855
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.824568598
Short name T1
Test name
Test status
Simulation time 149409403 ps
CPU time 0.55 seconds
Started Jul 31 05:17:31 PM PDT 24
Finished Jul 31 05:17:31 PM PDT 24
Peak memory 198108 kb
Host smart-1173d79e-2800-47d0-be5e-032aff7250e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824568598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.824568598
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2779940716
Short name T255
Test name
Test status
Simulation time 42656309 ps
CPU time 0.62 seconds
Started Jul 31 05:17:27 PM PDT 24
Finished Jul 31 05:17:28 PM PDT 24
Peak memory 198080 kb
Host smart-bfe48c34-2c2e-4e64-8643-24bb78b86454
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779940716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2779940716
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.889614643
Short name T161
Test name
Test status
Simulation time 43057378 ps
CPU time 0.71 seconds
Started Jul 31 05:17:34 PM PDT 24
Finished Jul 31 05:17:35 PM PDT 24
Peak memory 201412 kb
Host smart-dffd4c79-b36d-4fdf-8dca-5b3f30d43762
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889614643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.889614643
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.4011275406
Short name T540
Test name
Test status
Simulation time 138015167 ps
CPU time 0.69 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 198492 kb
Host smart-0b8690cf-298d-4118-8553-72ee934f8e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011275406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.4011275406
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.250029104
Short name T264
Test name
Test status
Simulation time 145202242 ps
CPU time 0.83 seconds
Started Jul 31 05:17:40 PM PDT 24
Finished Jul 31 05:17:41 PM PDT 24
Peak memory 209476 kb
Host smart-6f6b4761-1b33-4075-92eb-08a7e243545e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250029104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.250029104
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3954499800
Short name T513
Test name
Test status
Simulation time 54912433 ps
CPU time 0.74 seconds
Started Jul 31 05:17:47 PM PDT 24
Finished Jul 31 05:17:48 PM PDT 24
Peak memory 198124 kb
Host smart-39cf5f54-64dd-4870-95af-c52ebe5f5c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954499800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3954499800
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1702916878
Short name T584
Test name
Test status
Simulation time 36436346 ps
CPU time 0.63 seconds
Started Jul 31 05:17:17 PM PDT 24
Finished Jul 31 05:17:18 PM PDT 24
Peak memory 198396 kb
Host smart-8b436ffa-bcd6-4c2b-911f-ccc088fc3837
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702916878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1702916878
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.3142589538
Short name T612
Test name
Test status
Simulation time 113116683 ps
CPU time 0.77 seconds
Started Jul 31 05:17:32 PM PDT 24
Finished Jul 31 05:17:32 PM PDT 24
Peak memory 199008 kb
Host smart-16d5668b-1fac-4c4f-a67b-59395f9e037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142589538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.3142589538
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2369673475
Short name T494
Test name
Test status
Simulation time 82021284 ps
CPU time 0.66 seconds
Started Jul 31 05:17:16 PM PDT 24
Finished Jul 31 05:17:17 PM PDT 24
Peak memory 199176 kb
Host smart-9526c741-9f55-4fec-a8b6-4969e37285b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369673475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2369673475
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3976660839
Short name T304
Test name
Test status
Simulation time 39263621 ps
CPU time 0.56 seconds
Started Jul 31 05:17:18 PM PDT 24
Finished Jul 31 05:17:19 PM PDT 24
Peak memory 197984 kb
Host smart-f00b7e85-d0b1-4c28-8f54-bba32843eeaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976660839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3976660839
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3347707638
Short name T355
Test name
Test status
Simulation time 463250865 ps
CPU time 0.93 seconds
Started Jul 31 05:17:39 PM PDT 24
Finished Jul 31 05:17:40 PM PDT 24
Peak memory 198140 kb
Host smart-955f4ca7-9fc4-474f-ba53-f2e57c78d366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347707638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3347707638
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.1332455182
Short name T506
Test name
Test status
Simulation time 155094108 ps
CPU time 0.63 seconds
Started Jul 31 05:17:19 PM PDT 24
Finished Jul 31 05:17:20 PM PDT 24
Peak memory 198084 kb
Host smart-c075b5db-ca76-4bf9-bfc0-f260a73e0927
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332455182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1332455182
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2530646306
Short name T404
Test name
Test status
Simulation time 31510463 ps
CPU time 0.62 seconds
Started Jul 31 05:17:37 PM PDT 24
Finished Jul 31 05:17:37 PM PDT 24
Peak memory 198084 kb
Host smart-0b048b1d-3948-4913-8872-3c9131fd870c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530646306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2530646306
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3435584901
Short name T337
Test name
Test status
Simulation time 127168325 ps
CPU time 0.74 seconds
Started Jul 31 05:17:31 PM PDT 24
Finished Jul 31 05:17:32 PM PDT 24
Peak memory 198280 kb
Host smart-7847d822-6d71-4cec-940d-d1fb4a500d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435584901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3435584901
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3634775572
Short name T452
Test name
Test status
Simulation time 89540843 ps
CPU time 1.01 seconds
Started Jul 31 05:17:21 PM PDT 24
Finished Jul 31 05:17:22 PM PDT 24
Peak memory 209536 kb
Host smart-7abc88fb-70e4-4b83-a912-4472e48e5970
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634775572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3634775572
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.12014576
Short name T266
Test name
Test status
Simulation time 54190235 ps
CPU time 0.82 seconds
Started Jul 31 05:17:33 PM PDT 24
Finished Jul 31 05:17:34 PM PDT 24
Peak memory 198116 kb
Host smart-74d31198-c68c-40b9-b110-9acb1a367096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.12014576
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.4002381327
Short name T576
Test name
Test status
Simulation time 82416443 ps
CPU time 0.62 seconds
Started Jul 31 05:17:39 PM PDT 24
Finished Jul 31 05:17:39 PM PDT 24
Peak memory 198576 kb
Host smart-4d1d3243-8dfd-494a-b7f4-00ee3a115c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002381327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.4002381327
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.2498979675
Short name T466
Test name
Test status
Simulation time 31366855 ps
CPU time 0.6 seconds
Started Jul 31 05:17:29 PM PDT 24
Finished Jul 31 05:17:35 PM PDT 24
Peak memory 198636 kb
Host smart-47600997-a8a8-46f1-a941-f9a092861108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498979675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2498979675
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.4213980373
Short name T469
Test name
Test status
Simulation time 44634132 ps
CPU time 0.75 seconds
Started Jul 31 05:17:44 PM PDT 24
Finished Jul 31 05:17:45 PM PDT 24
Peak memory 199176 kb
Host smart-95156579-88a8-4587-bc4e-9b3cd9ecf7e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213980373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.4213980373
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.2339823167
Short name T292
Test name
Test status
Simulation time 31161209 ps
CPU time 0.62 seconds
Started Jul 31 05:17:38 PM PDT 24
Finished Jul 31 05:17:39 PM PDT 24
Peak memory 197992 kb
Host smart-bd3a4ee5-9d46-478a-8d7e-052c1449a0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339823167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.2339823167
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1349125830
Short name T274
Test name
Test status
Simulation time 178774010 ps
CPU time 0.97 seconds
Started Jul 31 05:17:42 PM PDT 24
Finished Jul 31 05:17:43 PM PDT 24
Peak memory 198104 kb
Host smart-42d66f78-2699-42ee-a863-89e53e3b3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349125830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1349125830
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1253537530
Short name T234
Test name
Test status
Simulation time 21542361 ps
CPU time 0.6 seconds
Started Jul 31 05:17:56 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 197436 kb
Host smart-a0895191-adb6-4968-95e5-0586b53f11d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253537530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1253537530
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2819996965
Short name T536
Test name
Test status
Simulation time 28088848 ps
CPU time 0.6 seconds
Started Jul 31 05:17:41 PM PDT 24
Finished Jul 31 05:17:41 PM PDT 24
Peak memory 198080 kb
Host smart-feddbf6e-0f74-4c83-879c-c809bc32cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819996965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2819996965
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.1043075577
Short name T80
Test name
Test status
Simulation time 75767106 ps
CPU time 0.67 seconds
Started Jul 31 05:17:48 PM PDT 24
Finished Jul 31 05:17:49 PM PDT 24
Peak memory 201420 kb
Host smart-bc7461fe-9ded-48e6-b010-e084dcbc3462
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043075577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.1043075577
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1714014642
Short name T554
Test name
Test status
Simulation time 33117987 ps
CPU time 0.68 seconds
Started Jul 31 05:17:14 PM PDT 24
Finished Jul 31 05:17:15 PM PDT 24
Peak memory 199172 kb
Host smart-74e77e91-faaa-4bd4-a5cd-10a6905f13c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714014642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1714014642
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.87950717
Short name T364
Test name
Test status
Simulation time 170008796 ps
CPU time 0.76 seconds
Started Jul 31 05:17:51 PM PDT 24
Finished Jul 31 05:17:52 PM PDT 24
Peak memory 209552 kb
Host smart-afe8e540-fbf0-4f87-a9fa-61fce654e39f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87950717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.87950717
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.455868541
Short name T502
Test name
Test status
Simulation time 215589166 ps
CPU time 0.66 seconds
Started Jul 31 05:17:21 PM PDT 24
Finished Jul 31 05:17:21 PM PDT 24
Peak memory 198472 kb
Host smart-91722468-5c26-454d-8fe3-085e79a8c542
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455868541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.455868541
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.3296794614
Short name T454
Test name
Test status
Simulation time 40132279 ps
CPU time 0.87 seconds
Started Jul 31 05:15:20 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 200300 kb
Host smart-dfef6291-136b-4964-866b-b4d48ba4c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296794614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.3296794614
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1992832496
Short name T566
Test name
Test status
Simulation time 38367489 ps
CPU time 0.59 seconds
Started Jul 31 05:15:26 PM PDT 24
Finished Jul 31 05:15:27 PM PDT 24
Peak memory 198004 kb
Host smart-b60c03b7-bd0d-458b-b48e-af48f165cfcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992832496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1992832496
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.3930529562
Short name T482
Test name
Test status
Simulation time 601641010 ps
CPU time 0.94 seconds
Started Jul 31 05:15:20 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 198124 kb
Host smart-a0935da6-350b-4e5b-b8f2-ddb52ac60510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930529562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3930529562
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.4198340283
Short name T603
Test name
Test status
Simulation time 67209815 ps
CPU time 0.65 seconds
Started Jul 31 05:15:20 PM PDT 24
Finished Jul 31 05:15:21 PM PDT 24
Peak memory 197352 kb
Host smart-adc11283-6606-445b-87cb-55e081ed7ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198340283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.4198340283
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2421311633
Short name T283
Test name
Test status
Simulation time 78274925 ps
CPU time 0.61 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 198432 kb
Host smart-48e3712a-349e-4f25-bee3-ef5a326d09c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421311633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2421311633
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2944030541
Short name T557
Test name
Test status
Simulation time 44684045 ps
CPU time 0.74 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 201136 kb
Host smart-92263da2-cfb8-4f50-9e68-d2e1e95d9ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944030541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2944030541
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1351814074
Short name T241
Test name
Test status
Simulation time 69591372 ps
CPU time 0.72 seconds
Started Jul 31 05:15:23 PM PDT 24
Finished Jul 31 05:15:24 PM PDT 24
Peak memory 198344 kb
Host smart-0150e693-629e-4ffb-806e-352f4f47ff06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351814074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1351814074
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1171205852
Short name T605
Test name
Test status
Simulation time 375546056 ps
CPU time 0.78 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 209572 kb
Host smart-6fbd7dea-61a7-426c-980d-695b3e8629f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171205852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1171205852
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2345655738
Short name T18
Test name
Test status
Simulation time 911040100 ps
CPU time 1.51 seconds
Started Jul 31 05:15:38 PM PDT 24
Finished Jul 31 05:15:40 PM PDT 24
Peak memory 218024 kb
Host smart-730e0838-08ba-4679-894a-61da485c74d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345655738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2345655738
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.159954658
Short name T388
Test name
Test status
Simulation time 64708889 ps
CPU time 0.89 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:22 PM PDT 24
Peak memory 198252 kb
Host smart-20654567-f14f-4888-b054-181a0bfc8be4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159954658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.159954658
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.3697915982
Short name T81
Test name
Test status
Simulation time 60707085 ps
CPU time 0.62 seconds
Started Jul 31 05:15:21 PM PDT 24
Finished Jul 31 05:15:22 PM PDT 24
Peak memory 199332 kb
Host smart-a6d92214-965a-4ab0-8050-527721d68f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697915982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3697915982
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.894949954
Short name T587
Test name
Test status
Simulation time 23301416 ps
CPU time 0.64 seconds
Started Jul 31 05:17:34 PM PDT 24
Finished Jul 31 05:17:35 PM PDT 24
Peak memory 198748 kb
Host smart-e18cc18f-0340-4e58-b6f4-64534cd372d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894949954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.894949954
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3490585500
Short name T326
Test name
Test status
Simulation time 39066869 ps
CPU time 0.57 seconds
Started Jul 31 05:17:48 PM PDT 24
Finished Jul 31 05:17:49 PM PDT 24
Peak memory 198060 kb
Host smart-35f76635-14d6-488b-bfc8-122bee537058
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490585500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3490585500
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3457864984
Short name T139
Test name
Test status
Simulation time 164667699 ps
CPU time 0.98 seconds
Started Jul 31 05:17:43 PM PDT 24
Finished Jul 31 05:17:44 PM PDT 24
Peak memory 198104 kb
Host smart-37e3df21-809f-48e4-8192-36089552329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457864984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3457864984
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1853473385
Short name T579
Test name
Test status
Simulation time 61598041 ps
CPU time 0.63 seconds
Started Jul 31 05:17:35 PM PDT 24
Finished Jul 31 05:17:36 PM PDT 24
Peak memory 198092 kb
Host smart-ce340c2f-6246-4c6e-94d8-f1d5543ae65e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853473385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1853473385
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.220816140
Short name T592
Test name
Test status
Simulation time 37071078 ps
CPU time 0.61 seconds
Started Jul 31 05:17:46 PM PDT 24
Finished Jul 31 05:17:47 PM PDT 24
Peak memory 198400 kb
Host smart-ff9438c8-018a-4036-ae44-a42f393a89a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220816140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.220816140
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1766877707
Short name T159
Test name
Test status
Simulation time 44087485 ps
CPU time 0.72 seconds
Started Jul 31 05:17:46 PM PDT 24
Finished Jul 31 05:17:46 PM PDT 24
Peak memory 201368 kb
Host smart-001e5f62-8fe2-4e58-ab36-1c5bd867c12a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766877707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1766877707
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3633497941
Short name T585
Test name
Test status
Simulation time 75160168 ps
CPU time 0.76 seconds
Started Jul 31 05:17:26 PM PDT 24
Finished Jul 31 05:17:32 PM PDT 24
Peak memory 198404 kb
Host smart-97bf16b4-3ecb-4e36-8eb0-4c66bc2bd8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633497941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3633497941
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2319532871
Short name T330
Test name
Test status
Simulation time 103072445 ps
CPU time 0.95 seconds
Started Jul 31 05:17:40 PM PDT 24
Finished Jul 31 05:17:41 PM PDT 24
Peak memory 209424 kb
Host smart-85ea8d96-6ac1-47ff-91fc-1aacaefb226b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319532871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2319532871
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.3480273466
Short name T445
Test name
Test status
Simulation time 100299712 ps
CPU time 0.74 seconds
Started Jul 31 05:17:33 PM PDT 24
Finished Jul 31 05:17:34 PM PDT 24
Peak memory 197932 kb
Host smart-bd3e5592-7a36-459c-80b4-e20c47a02a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480273466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3480273466
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.583042947
Short name T313
Test name
Test status
Simulation time 32697709 ps
CPU time 0.69 seconds
Started Jul 31 05:17:37 PM PDT 24
Finished Jul 31 05:17:38 PM PDT 24
Peak memory 198544 kb
Host smart-ab6e8397-5b19-4786-a84c-94953820b063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583042947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.583042947
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1454832766
Short name T610
Test name
Test status
Simulation time 98017015 ps
CPU time 0.74 seconds
Started Jul 31 05:17:52 PM PDT 24
Finished Jul 31 05:17:52 PM PDT 24
Peak memory 198752 kb
Host smart-e2cddf76-4467-4d5a-901e-142839620feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454832766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1454832766
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3605752349
Short name T362
Test name
Test status
Simulation time 30070105 ps
CPU time 0.61 seconds
Started Jul 31 05:17:53 PM PDT 24
Finished Jul 31 05:17:54 PM PDT 24
Peak memory 197332 kb
Host smart-7b55d7eb-e57a-4161-bdd0-82f025269a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605752349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3605752349
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.888861955
Short name T568
Test name
Test status
Simulation time 605740814 ps
CPU time 0.97 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 198120 kb
Host smart-90a01b4c-b3ff-42cc-aaaa-a8dd54b30733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888861955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.888861955
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1376471207
Short name T278
Test name
Test status
Simulation time 57543845 ps
CPU time 0.65 seconds
Started Jul 31 05:17:43 PM PDT 24
Finished Jul 31 05:17:44 PM PDT 24
Peak memory 197316 kb
Host smart-41b8145b-a8dd-4864-93b1-9149cfcf0305
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376471207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1376471207
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.701220851
Short name T263
Test name
Test status
Simulation time 48950437 ps
CPU time 0.62 seconds
Started Jul 31 05:17:49 PM PDT 24
Finished Jul 31 05:17:50 PM PDT 24
Peak memory 198124 kb
Host smart-c1ff318d-b5a7-4ab9-99a3-cac6cd81323c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701220851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.701220851
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.695974927
Short name T169
Test name
Test status
Simulation time 44836611 ps
CPU time 0.72 seconds
Started Jul 31 05:17:44 PM PDT 24
Finished Jul 31 05:17:44 PM PDT 24
Peak memory 201396 kb
Host smart-d6cfe934-880c-4254-a4ba-53c854cb8e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695974927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invali
d.695974927
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.1894941676
Short name T423
Test name
Test status
Simulation time 69862066 ps
CPU time 0.89 seconds
Started Jul 31 05:17:46 PM PDT 24
Finished Jul 31 05:17:47 PM PDT 24
Peak memory 198460 kb
Host smart-bfdadbcf-d36a-46e4-9cb8-f00a6eb9071d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894941676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1894941676
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1486587141
Short name T253
Test name
Test status
Simulation time 144204377 ps
CPU time 0.85 seconds
Started Jul 31 05:17:56 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 209472 kb
Host smart-7f169e4d-976d-4728-a31f-88ccba7408a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486587141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1486587141
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.3749602674
Short name T49
Test name
Test status
Simulation time 66547185 ps
CPU time 0.61 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:58 PM PDT 24
Peak memory 198432 kb
Host smart-3f5a0411-1f66-478e-893d-d0f5e2fe633b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749602674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.3749602674
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.4015091829
Short name T76
Test name
Test status
Simulation time 51774099 ps
CPU time 0.69 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198116 kb
Host smart-d72f0351-852d-4ed7-bbf8-6ab54c914e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015091829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4015091829
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.2230480172
Short name T442
Test name
Test status
Simulation time 31371686 ps
CPU time 0.65 seconds
Started Jul 31 05:17:40 PM PDT 24
Finished Jul 31 05:17:41 PM PDT 24
Peak memory 199268 kb
Host smart-8472c206-c69c-4990-a67d-f75b2a32085b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230480172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2230480172
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1968375404
Short name T472
Test name
Test status
Simulation time 44963491 ps
CPU time 0.63 seconds
Started Jul 31 05:17:51 PM PDT 24
Finished Jul 31 05:17:52 PM PDT 24
Peak memory 198580 kb
Host smart-663f96c4-6443-4225-a75c-71d9809bb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968375404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1968375404
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2769641416
Short name T206
Test name
Test status
Simulation time 64680979 ps
CPU time 0.7 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 198376 kb
Host smart-07802c8c-6c83-43d9-a504-f1d26384618a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769641416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2769641416
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1194990331
Short name T406
Test name
Test status
Simulation time 31698506 ps
CPU time 0.6 seconds
Started Jul 31 05:17:45 PM PDT 24
Finished Jul 31 05:17:46 PM PDT 24
Peak memory 197332 kb
Host smart-0e755ffb-8854-4aa5-8910-7b1ba88abaeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194990331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.1194990331
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3816455994
Short name T577
Test name
Test status
Simulation time 162158838 ps
CPU time 0.99 seconds
Started Jul 31 05:17:46 PM PDT 24
Finished Jul 31 05:17:47 PM PDT 24
Peak memory 198104 kb
Host smart-c7b8744a-0672-415b-8a59-d390a6e35f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816455994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3816455994
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.4067889526
Short name T441
Test name
Test status
Simulation time 51980659 ps
CPU time 0.59 seconds
Started Jul 31 05:17:50 PM PDT 24
Finished Jul 31 05:17:50 PM PDT 24
Peak memory 198100 kb
Host smart-b80536cc-99d0-499e-b133-d67da901de1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067889526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.4067889526
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.758623716
Short name T479
Test name
Test status
Simulation time 69626008 ps
CPU time 0.63 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198104 kb
Host smart-48b5ad0b-9573-4e50-ae26-7bfb8a84b973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758623716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.758623716
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.2418451752
Short name T559
Test name
Test status
Simulation time 234283437 ps
CPU time 0.66 seconds
Started Jul 31 05:17:49 PM PDT 24
Finished Jul 31 05:17:49 PM PDT 24
Peak memory 201368 kb
Host smart-226be9c0-6e5d-41a8-bf6e-634b76833710
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418451752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.2418451752
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.460179091
Short name T487
Test name
Test status
Simulation time 54164660 ps
CPU time 0.68 seconds
Started Jul 31 05:17:36 PM PDT 24
Finished Jul 31 05:17:37 PM PDT 24
Peak memory 198360 kb
Host smart-7a5ca9b0-15ca-4276-95d6-dae80c8205ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460179091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.460179091
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1140697723
Short name T302
Test name
Test status
Simulation time 187747326 ps
CPU time 0.81 seconds
Started Jul 31 05:17:55 PM PDT 24
Finished Jul 31 05:17:56 PM PDT 24
Peak memory 209472 kb
Host smart-934b76c4-b772-457d-a216-d925969543d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140697723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1140697723
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1294221857
Short name T486
Test name
Test status
Simulation time 80795336 ps
CPU time 0.77 seconds
Started Jul 31 05:17:45 PM PDT 24
Finished Jul 31 05:17:46 PM PDT 24
Peak memory 199156 kb
Host smart-a7ee05ae-dcc4-47be-8f11-0a5292ff3579
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294221857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1294221857
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.1378814749
Short name T342
Test name
Test status
Simulation time 28582364 ps
CPU time 0.7 seconds
Started Jul 31 05:17:48 PM PDT 24
Finished Jul 31 05:17:49 PM PDT 24
Peak memory 199384 kb
Host smart-66561251-b2da-4580-a09f-1c045ddb44d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378814749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1378814749
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3728098457
Short name T324
Test name
Test status
Simulation time 64007825 ps
CPU time 0.67 seconds
Started Jul 31 05:17:54 PM PDT 24
Finished Jul 31 05:17:54 PM PDT 24
Peak memory 198684 kb
Host smart-17d9cf35-6fe4-405d-827f-2953717eb70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728098457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3728098457
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.4087101074
Short name T543
Test name
Test status
Simulation time 56497627 ps
CPU time 0.81 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 198552 kb
Host smart-65721311-cfb5-4f45-a889-79acad96ed74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087101074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.4087101074
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3161886537
Short name T424
Test name
Test status
Simulation time 39164380 ps
CPU time 0.58 seconds
Started Jul 31 05:17:52 PM PDT 24
Finished Jul 31 05:17:53 PM PDT 24
Peak memory 198056 kb
Host smart-f6b1f527-4d34-4a36-815b-f168e71fc0a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161886537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3161886537
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.817142916
Short name T92
Test name
Test status
Simulation time 602664541 ps
CPU time 1.01 seconds
Started Jul 31 05:17:51 PM PDT 24
Finished Jul 31 05:17:52 PM PDT 24
Peak memory 198088 kb
Host smart-d2dbbfaf-dba8-4101-96f8-7bad3ec520b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817142916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.817142916
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.285380900
Short name T514
Test name
Test status
Simulation time 47373048 ps
CPU time 0.57 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198036 kb
Host smart-93eb179b-718c-4f2a-be4b-976dbff7e96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285380900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.285380900
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3093879440
Short name T309
Test name
Test status
Simulation time 61733308 ps
CPU time 0.64 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198420 kb
Host smart-173c43e7-7ad8-4473-a294-08f1aa74a49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093879440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3093879440
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.107372453
Short name T164
Test name
Test status
Simulation time 56832371 ps
CPU time 0.66 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 201264 kb
Host smart-eee6debf-e9d8-402c-9a6d-82e7b8feccb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107372453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.107372453
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1105219223
Short name T415
Test name
Test status
Simulation time 83880629 ps
CPU time 0.88 seconds
Started Jul 31 05:17:56 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 198520 kb
Host smart-7b57a137-b728-43ee-943f-04d0e1fde96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105219223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1105219223
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1329791803
Short name T213
Test name
Test status
Simulation time 109735015 ps
CPU time 1.08 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 201216 kb
Host smart-3e7b391f-86a7-472f-a64c-0700d24bc229
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329791803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1329791803
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4244662516
Short name T133
Test name
Test status
Simulation time 107085167 ps
CPU time 0.88 seconds
Started Jul 31 05:17:54 PM PDT 24
Finished Jul 31 05:17:55 PM PDT 24
Peak memory 199340 kb
Host smart-13091971-9407-4778-a858-1b261d8402fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244662516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4244662516
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1857202356
Short name T322
Test name
Test status
Simulation time 39859670 ps
CPU time 0.63 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 199380 kb
Host smart-716a1d65-6741-4e1e-aa40-f8c676d10dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857202356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1857202356
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2621352562
Short name T87
Test name
Test status
Simulation time 40060910 ps
CPU time 0.8 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:00 PM PDT 24
Peak memory 200132 kb
Host smart-0083eae4-a6ea-450f-9de1-88f89a6466fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621352562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2621352562
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.261893244
Short name T194
Test name
Test status
Simulation time 59423510 ps
CPU time 0.81 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 199104 kb
Host smart-455e3ed7-49c9-4dbc-91f1-e0b4ed8688f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261893244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa
ble_rom_integrity_check.261893244
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.365604975
Short name T401
Test name
Test status
Simulation time 34307958 ps
CPU time 0.57 seconds
Started Jul 31 05:17:57 PM PDT 24
Finished Jul 31 05:17:58 PM PDT 24
Peak memory 197928 kb
Host smart-a31b485f-ce29-4e14-8fee-2a6408075f4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365604975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_
malfunc.365604975
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3401530620
Short name T306
Test name
Test status
Simulation time 163883566 ps
CPU time 1.12 seconds
Started Jul 31 05:17:49 PM PDT 24
Finished Jul 31 05:17:50 PM PDT 24
Peak memory 198092 kb
Host smart-2e2708fd-fd4e-4789-9222-0928886b2110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401530620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3401530620
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.3564079294
Short name T427
Test name
Test status
Simulation time 35273019 ps
CPU time 0.67 seconds
Started Jul 31 05:17:57 PM PDT 24
Finished Jul 31 05:17:58 PM PDT 24
Peak memory 198284 kb
Host smart-8f52b248-0dd7-4432-9bf5-38ddc83e7f42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564079294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3564079294
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3440216812
Short name T461
Test name
Test status
Simulation time 48188609 ps
CPU time 0.62 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198132 kb
Host smart-343b450f-188a-422f-bef8-66c538f3ec0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440216812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3440216812
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.4050972870
Short name T54
Test name
Test status
Simulation time 45406105 ps
CPU time 0.7 seconds
Started Jul 31 05:17:54 PM PDT 24
Finished Jul 31 05:17:55 PM PDT 24
Peak memory 201380 kb
Host smart-f1e84594-231f-4911-8145-f0919480650a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050972870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.4050972870
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.767461748
Short name T413
Test name
Test status
Simulation time 66996025 ps
CPU time 0.81 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:00 PM PDT 24
Peak memory 198420 kb
Host smart-33b913f0-1b30-4a4f-835f-58567a5958e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767461748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.767461748
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.2320524585
Short name T98
Test name
Test status
Simulation time 125146319 ps
CPU time 0.82 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 209484 kb
Host smart-4c4ac30c-6d2c-4653-9cc9-9e87eaad68a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320524585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2320524585
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1334652197
Short name T608
Test name
Test status
Simulation time 91131658 ps
CPU time 0.74 seconds
Started Jul 31 05:17:57 PM PDT 24
Finished Jul 31 05:17:58 PM PDT 24
Peak memory 199304 kb
Host smart-f62cecaf-5ad1-4830-85c0-a05c601d0ecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334652197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1334652197
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.524390058
Short name T84
Test name
Test status
Simulation time 62292514 ps
CPU time 0.64 seconds
Started Jul 31 05:17:54 PM PDT 24
Finished Jul 31 05:17:55 PM PDT 24
Peak memory 198488 kb
Host smart-f85ed087-5f6c-48fe-81c3-230187a8d724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524390058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.524390058
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3784171216
Short name T393
Test name
Test status
Simulation time 32707647 ps
CPU time 0.78 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 200184 kb
Host smart-64655bbc-41f6-47b5-b484-847266bc065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784171216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3784171216
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.33694839
Short name T357
Test name
Test status
Simulation time 59565069 ps
CPU time 0.82 seconds
Started Jul 31 05:17:55 PM PDT 24
Finished Jul 31 05:17:56 PM PDT 24
Peak memory 198700 kb
Host smart-13c6e635-bce4-40ea-8f1a-55f9dedf4246
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disab
le_rom_integrity_check.33694839
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1112247390
Short name T332
Test name
Test status
Simulation time 33473072 ps
CPU time 0.59 seconds
Started Jul 31 05:17:57 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 197276 kb
Host smart-dd022bd3-394d-4715-8243-3a3ba70b5f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112247390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.1112247390
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.662404793
Short name T333
Test name
Test status
Simulation time 163934180 ps
CPU time 0.95 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 198092 kb
Host smart-71bb8b5e-caf1-43f4-934f-86f587fde679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662404793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.662404793
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.3056740792
Short name T10
Test name
Test status
Simulation time 103079051 ps
CPU time 0.57 seconds
Started Jul 31 05:17:53 PM PDT 24
Finished Jul 31 05:17:54 PM PDT 24
Peak memory 198100 kb
Host smart-453b1e24-1ae8-4254-bdc6-50d914acae88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056740792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3056740792
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.849489327
Short name T457
Test name
Test status
Simulation time 78455734 ps
CPU time 0.6 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 198072 kb
Host smart-2181442a-74db-4a96-9784-ef7c8d2135e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849489327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.849489327
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1727419999
Short name T180
Test name
Test status
Simulation time 43783108 ps
CPU time 0.68 seconds
Started Jul 31 05:17:53 PM PDT 24
Finished Jul 31 05:17:54 PM PDT 24
Peak memory 201376 kb
Host smart-ff85ec24-bb8d-4bd8-95d9-9f234d0f75d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727419999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1727419999
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2256522727
Short name T599
Test name
Test status
Simulation time 69571658 ps
CPU time 0.87 seconds
Started Jul 31 05:17:47 PM PDT 24
Finished Jul 31 05:17:48 PM PDT 24
Peak memory 198568 kb
Host smart-2e2aecef-eb5b-475b-8e42-3e31962b8a12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256522727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2256522727
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.1844449102
Short name T473
Test name
Test status
Simulation time 117500699 ps
CPU time 0.93 seconds
Started Jul 31 05:17:49 PM PDT 24
Finished Jul 31 05:17:50 PM PDT 24
Peak memory 209388 kb
Host smart-4eeff11e-805a-4a1b-97e1-ece8bf7b2721
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844449102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1844449102
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1397731585
Short name T272
Test name
Test status
Simulation time 62717277 ps
CPU time 0.86 seconds
Started Jul 31 05:17:56 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 199308 kb
Host smart-16656437-01c9-4b0b-9a3a-060a7b62dab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397731585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1397731585
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.388549366
Short name T616
Test name
Test status
Simulation time 37054140 ps
CPU time 0.65 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 198548 kb
Host smart-c86d9c9c-c9fc-4dcc-8700-66aff35acb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388549366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.388549366
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.1291736452
Short name T619
Test name
Test status
Simulation time 52892918 ps
CPU time 0.74 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 198916 kb
Host smart-87ff963a-552c-45bc-9c8e-5a765bdd240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291736452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1291736452
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1184824290
Short name T414
Test name
Test status
Simulation time 61913045 ps
CPU time 0.78 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 199088 kb
Host smart-c8f5bbdf-55e2-4a95-92e8-3edb9e3079ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184824290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1184824290
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2890895178
Short name T30
Test name
Test status
Simulation time 37798468 ps
CPU time 0.6 seconds
Started Jul 31 05:17:57 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 198000 kb
Host smart-ca0ff033-53f5-4591-8e3a-f0ed6a57ad3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890895178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.2890895178
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3178961676
Short name T141
Test name
Test status
Simulation time 1893694839 ps
CPU time 0.99 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198348 kb
Host smart-2a31e7e9-c244-49ec-846f-d8c211eb9924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178961676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3178961676
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.847939770
Short name T331
Test name
Test status
Simulation time 35507891 ps
CPU time 0.67 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 197384 kb
Host smart-c968e06e-d7a9-42e6-9128-34ed38fb819e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847939770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.847939770
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.692744977
Short name T475
Test name
Test status
Simulation time 78439405 ps
CPU time 0.58 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198104 kb
Host smart-23e319a9-5a26-4190-b582-4a5951df4dfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692744977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.692744977
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.130106061
Short name T151
Test name
Test status
Simulation time 62430148 ps
CPU time 0.68 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 201360 kb
Host smart-d57770ee-fea9-48b1-9fad-03a08dd0b443
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130106061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.130106061
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3339928952
Short name T600
Test name
Test status
Simulation time 110127179 ps
CPU time 0.7 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198424 kb
Host smart-c36609eb-dd10-46de-a655-530271b33953
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339928952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3339928952
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3420582601
Short name T542
Test name
Test status
Simulation time 163695362 ps
CPU time 0.78 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 209516 kb
Host smart-bb2c1bb6-afe1-4a7b-810c-f82eac1d2b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420582601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3420582601
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2824618423
Short name T249
Test name
Test status
Simulation time 56660772 ps
CPU time 0.72 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198092 kb
Host smart-fa81b4af-e78c-483e-9c5c-8f473a25d088
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824618423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2824618423
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.3039615084
Short name T509
Test name
Test status
Simulation time 29152074 ps
CPU time 0.7 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 199356 kb
Host smart-81e5d469-a90f-4bd6-84fd-50911f93137d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039615084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.3039615084
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3683254876
Short name T305
Test name
Test status
Simulation time 19866192 ps
CPU time 0.64 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 198652 kb
Host smart-affc25f8-0dcf-45f3-8cb8-7abe6e548ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683254876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3683254876
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3609099343
Short name T558
Test name
Test status
Simulation time 69414236 ps
CPU time 0.68 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198312 kb
Host smart-3310ba6b-c52e-4d5e-9861-cf9a6f02fa61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609099343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3609099343
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2125453599
Short name T588
Test name
Test status
Simulation time 29176579 ps
CPU time 0.62 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:17:59 PM PDT 24
Peak memory 198000 kb
Host smart-01b4a6ff-6579-4656-a0c5-be8bf308090c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125453599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.2125453599
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2596505890
Short name T478
Test name
Test status
Simulation time 165852070 ps
CPU time 0.94 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 198384 kb
Host smart-a7f496ec-bede-4af7-8baf-4e9af9097e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596505890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2596505890
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.3697183013
Short name T351
Test name
Test status
Simulation time 56092461 ps
CPU time 0.64 seconds
Started Jul 31 05:17:53 PM PDT 24
Finished Jul 31 05:17:54 PM PDT 24
Peak memory 198000 kb
Host smart-daac06ca-2f19-4fdc-9c47-c39607b58cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697183013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3697183013
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.1954192203
Short name T343
Test name
Test status
Simulation time 80206867 ps
CPU time 0.61 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 198116 kb
Host smart-a045e127-2672-4112-bb62-ec7c914d26da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954192203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1954192203
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.554604974
Short name T183
Test name
Test status
Simulation time 111111650 ps
CPU time 0.68 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 201324 kb
Host smart-659d6805-de4c-4b2d-a386-18d012dd637f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554604974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invali
d.554604974
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.195277492
Short name T447
Test name
Test status
Simulation time 56959083 ps
CPU time 0.72 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 198280 kb
Host smart-5c53acd7-7cdc-4594-ae18-177219e135c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195277492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.195277492
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1493807387
Short name T583
Test name
Test status
Simulation time 241021540 ps
CPU time 0.83 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 209436 kb
Host smart-24924346-477f-4b49-b363-eb34b394dc85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493807387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1493807387
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3935070937
Short name T490
Test name
Test status
Simulation time 54536552 ps
CPU time 0.8 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 198092 kb
Host smart-dc057c46-e7f2-4265-b4f7-1d615dc0d49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935070937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3935070937
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.4281560450
Short name T47
Test name
Test status
Simulation time 61731807 ps
CPU time 0.63 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 199340 kb
Host smart-27209505-059d-4321-9322-fc9c54fcd57a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281560450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.4281560450
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1626969661
Short name T314
Test name
Test status
Simulation time 73419302 ps
CPU time 0.74 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198520 kb
Host smart-c94b3462-5322-43ac-acdd-d4ae67d2b7b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626969661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1626969661
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1177800154
Short name T493
Test name
Test status
Simulation time 32442247 ps
CPU time 0.6 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 198016 kb
Host smart-f40a4edc-deab-4e79-98c2-831daa8e686a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177800154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.1177800154
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2044582915
Short name T271
Test name
Test status
Simulation time 165969527 ps
CPU time 1.01 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198052 kb
Host smart-cbd3a7ce-de95-443a-94b2-eed641867ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044582915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2044582915
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1428381482
Short name T328
Test name
Test status
Simulation time 31246158 ps
CPU time 0.61 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 198024 kb
Host smart-43a82a96-d6e9-48d0-a6ee-8bcd59437ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428381482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1428381482
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.1155607654
Short name T505
Test name
Test status
Simulation time 85310751 ps
CPU time 0.62 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 198056 kb
Host smart-f76903f5-c205-400a-a7a2-344ff573fccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155607654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1155607654
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3333003548
Short name T175
Test name
Test status
Simulation time 50437182 ps
CPU time 0.71 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 201368 kb
Host smart-a4736c66-007c-42e2-b2ea-93d5880a1b21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333003548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3333003548
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.4069150785
Short name T279
Test name
Test status
Simulation time 81134681 ps
CPU time 0.78 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 199172 kb
Host smart-8e1e8e26-93d4-4c92-a091-fbf590acc960
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069150785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.4069150785
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.3725305546
Short name T212
Test name
Test status
Simulation time 110521632 ps
CPU time 0.93 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 209500 kb
Host smart-34e4c8bd-7194-4d97-8c2f-371ed499a402
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725305546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3725305546
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1480484692
Short name T231
Test name
Test status
Simulation time 64877044 ps
CPU time 0.78 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 197912 kb
Host smart-150b7683-2e08-465c-920d-535133ecd4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480484692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1480484692
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1087664811
Short name T294
Test name
Test status
Simulation time 44839143 ps
CPU time 0.63 seconds
Started Jul 31 05:18:34 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 199352 kb
Host smart-8fd4d543-4243-4f0b-8c90-d9c7ce480dfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087664811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1087664811
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.4179960444
Short name T11
Test name
Test status
Simulation time 99656518 ps
CPU time 0.75 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198788 kb
Host smart-4a417c16-0069-4491-aebf-8f6bdbfbd343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179960444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.4179960444
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3892138118
Short name T586
Test name
Test status
Simulation time 62023499 ps
CPU time 0.72 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 199248 kb
Host smart-a39050e1-65e1-4378-bc85-e51c876347a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892138118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3892138118
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2369186359
Short name T143
Test name
Test status
Simulation time 39253778 ps
CPU time 0.55 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:00 PM PDT 24
Peak memory 198060 kb
Host smart-4b6dbba1-b854-4b00-baf8-5a3738b4bf68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369186359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.2369186359
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1241196871
Short name T550
Test name
Test status
Simulation time 310963152 ps
CPU time 0.99 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198064 kb
Host smart-3aa25ba7-2fa9-4336-9931-1eed278de642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241196871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1241196871
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.3566717503
Short name T400
Test name
Test status
Simulation time 47921014 ps
CPU time 0.66 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 197400 kb
Host smart-966157ce-793e-4cdc-88fa-97d3d214605e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566717503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3566717503
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.329743585
Short name T224
Test name
Test status
Simulation time 25250741 ps
CPU time 0.57 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198364 kb
Host smart-a0c18d3f-2f80-4c06-b800-96014afe4b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329743585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.329743585
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2368308263
Short name T171
Test name
Test status
Simulation time 41236034 ps
CPU time 0.68 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:15 PM PDT 24
Peak memory 201332 kb
Host smart-1dae0a1c-9e46-4191-8196-55d5b20b791d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368308263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2368308263
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.4167153240
Short name T556
Test name
Test status
Simulation time 71733485 ps
CPU time 0.88 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 199128 kb
Host smart-905af819-829d-4e27-b225-036d8f175c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167153240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.4167153240
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3095307228
Short name T386
Test name
Test status
Simulation time 112497356 ps
CPU time 0.87 seconds
Started Jul 31 05:18:20 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 209552 kb
Host smart-5b5fee5f-0c85-4e61-95c2-d0aad4f02b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095307228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3095307228
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.197615394
Short name T591
Test name
Test status
Simulation time 165407714 ps
CPU time 0.78 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 198940 kb
Host smart-57d43f15-f5e2-428a-82a9-eb50d712a857
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197615394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.197615394
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3457153742
Short name T297
Test name
Test status
Simulation time 29475396 ps
CPU time 0.67 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 199268 kb
Host smart-381e966a-6e2e-4e8f-8526-ac3a3e66c41d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457153742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3457153742
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3258518718
Short name T12
Test name
Test status
Simulation time 32406471 ps
CPU time 0.74 seconds
Started Jul 31 05:15:38 PM PDT 24
Finished Jul 31 05:15:39 PM PDT 24
Peak memory 198612 kb
Host smart-a64edc86-176a-45af-9d89-99e5ffb08b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258518718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3258518718
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1458427337
Short name T145
Test name
Test status
Simulation time 63250137 ps
CPU time 0.63 seconds
Started Jul 31 05:15:32 PM PDT 24
Finished Jul 31 05:15:33 PM PDT 24
Peak memory 198212 kb
Host smart-4372d247-ee81-423d-b876-de256c2fc486
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458427337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1458427337
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.893320978
Short name T95
Test name
Test status
Simulation time 34121614 ps
CPU time 0.63 seconds
Started Jul 31 05:15:27 PM PDT 24
Finished Jul 31 05:15:27 PM PDT 24
Peak memory 198032 kb
Host smart-62c78ef0-f2db-40d4-b359-2b64828473cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893320978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.893320978
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2502383829
Short name T318
Test name
Test status
Simulation time 304551707 ps
CPU time 0.97 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:51 PM PDT 24
Peak memory 198376 kb
Host smart-75481279-77ae-4f81-aa1f-83aa28c72002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502383829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2502383829
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2156839220
Short name T268
Test name
Test status
Simulation time 65313262 ps
CPU time 0.59 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 198052 kb
Host smart-b7369e5c-cc67-476b-86eb-4fe08a384cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156839220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2156839220
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.2408319650
Short name T339
Test name
Test status
Simulation time 76601045 ps
CPU time 0.59 seconds
Started Jul 31 05:15:27 PM PDT 24
Finished Jul 31 05:15:28 PM PDT 24
Peak memory 198080 kb
Host smart-b3e5f926-7fe7-4453-8dfa-4f9fc0afbcc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408319650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2408319650
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.774266277
Short name T185
Test name
Test status
Simulation time 68830342 ps
CPU time 0.65 seconds
Started Jul 31 05:15:51 PM PDT 24
Finished Jul 31 05:15:52 PM PDT 24
Peak memory 201272 kb
Host smart-0e7eb34c-8d0c-4d38-80db-a6a26f23db53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774266277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.774266277
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.1971282417
Short name T296
Test name
Test status
Simulation time 52643805 ps
CPU time 0.62 seconds
Started Jul 31 05:15:27 PM PDT 24
Finished Jul 31 05:15:27 PM PDT 24
Peak memory 199056 kb
Host smart-726976de-e07a-47ab-9cca-87108c9f2148
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971282417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1971282417
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1215376004
Short name T589
Test name
Test status
Simulation time 98406652 ps
CPU time 0.94 seconds
Started Jul 31 05:15:30 PM PDT 24
Finished Jul 31 05:15:31 PM PDT 24
Peak memory 209508 kb
Host smart-85dc4b8d-bd5a-44cb-89e6-ad2ca644fd38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215376004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1215376004
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.420442679
Short name T510
Test name
Test status
Simulation time 58607328 ps
CPU time 0.78 seconds
Started Jul 31 05:15:42 PM PDT 24
Finished Jul 31 05:15:43 PM PDT 24
Peak memory 198204 kb
Host smart-f8373af2-3a45-459f-b4d9-a6676ed3f1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420442679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.420442679
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.158226845
Short name T366
Test name
Test status
Simulation time 32646609 ps
CPU time 0.65 seconds
Started Jul 31 05:15:22 PM PDT 24
Finished Jul 31 05:15:23 PM PDT 24
Peak memory 198528 kb
Host smart-e961b61f-1856-4073-9e0c-f1b73d368c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158226845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.158226845
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.436919094
Short name T88
Test name
Test status
Simulation time 96759832 ps
CPU time 0.77 seconds
Started Jul 31 05:15:40 PM PDT 24
Finished Jul 31 05:15:41 PM PDT 24
Peak memory 200040 kb
Host smart-8b45edd8-1518-44fd-845a-fc449ad7ecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436919094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.436919094
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.24980179
Short name T456
Test name
Test status
Simulation time 57340713 ps
CPU time 0.79 seconds
Started Jul 31 05:15:49 PM PDT 24
Finished Jul 31 05:15:50 PM PDT 24
Peak memory 198516 kb
Host smart-61ec09e9-a15b-466c-a6cb-46da58ced38e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disabl
e_rom_integrity_check.24980179
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3824885024
Short name T7
Test name
Test status
Simulation time 28578106 ps
CPU time 0.64 seconds
Started Jul 31 05:15:37 PM PDT 24
Finished Jul 31 05:15:38 PM PDT 24
Peak memory 197212 kb
Host smart-b6ec787d-bd86-4455-9890-6862001bb427
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824885024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.3824885024
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.4086133928
Short name T222
Test name
Test status
Simulation time 165319205 ps
CPU time 0.94 seconds
Started Jul 31 05:15:35 PM PDT 24
Finished Jul 31 05:15:36 PM PDT 24
Peak memory 198076 kb
Host smart-68223813-9635-4400-9e0e-83e139c6bf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086133928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4086133928
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3684806692
Short name T247
Test name
Test status
Simulation time 41758690 ps
CPU time 0.65 seconds
Started Jul 31 05:15:41 PM PDT 24
Finished Jul 31 05:15:42 PM PDT 24
Peak memory 198032 kb
Host smart-622f2523-ea87-4aec-ac2b-3c17a03334a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684806692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3684806692
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2862798351
Short name T420
Test name
Test status
Simulation time 61889768 ps
CPU time 0.58 seconds
Started Jul 31 05:15:44 PM PDT 24
Finished Jul 31 05:15:45 PM PDT 24
Peak memory 198360 kb
Host smart-0fe0e714-e4a1-4299-84f2-5fbfa4d005a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862798351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2862798351
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1926880771
Short name T50
Test name
Test status
Simulation time 56018520 ps
CPU time 0.7 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 201392 kb
Host smart-3cb4c4c6-9c6e-4677-a50d-ecf5a926184a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926880771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1926880771
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.4138511883
Short name T398
Test name
Test status
Simulation time 100454833 ps
CPU time 0.79 seconds
Started Jul 31 05:15:28 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 199096 kb
Host smart-c3a20fc0-dcbd-420e-885f-17a4b722688c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138511883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.4138511883
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1880545674
Short name T563
Test name
Test status
Simulation time 106248508 ps
CPU time 1 seconds
Started Jul 31 05:15:45 PM PDT 24
Finished Jul 31 05:15:46 PM PDT 24
Peak memory 209472 kb
Host smart-5d934b97-22e8-4ae4-b732-0369c847f1bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880545674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1880545674
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.730617244
Short name T315
Test name
Test status
Simulation time 63876212 ps
CPU time 0.78 seconds
Started Jul 31 05:15:53 PM PDT 24
Finished Jul 31 05:15:54 PM PDT 24
Peak memory 198108 kb
Host smart-7ec6a2ad-d2cb-486e-b87d-6466d050ac52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730617244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.730617244
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.344934498
Short name T436
Test name
Test status
Simulation time 29434688 ps
CPU time 0.65 seconds
Started Jul 31 05:15:40 PM PDT 24
Finished Jul 31 05:15:41 PM PDT 24
Peak memory 199340 kb
Host smart-36e1aeef-8134-40a1-9196-ce7699680d5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344934498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.344934498
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.3267860790
Short name T100
Test name
Test status
Simulation time 28243982 ps
CPU time 0.81 seconds
Started Jul 31 05:15:42 PM PDT 24
Finished Jul 31 05:15:43 PM PDT 24
Peak memory 200320 kb
Host smart-d7f36ebf-49a4-477c-ada0-bcfb0d51cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267860790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3267860790
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.4088981414
Short name T496
Test name
Test status
Simulation time 75474496 ps
CPU time 0.67 seconds
Started Jul 31 05:15:57 PM PDT 24
Finished Jul 31 05:15:58 PM PDT 24
Peak memory 198272 kb
Host smart-62ec2060-0ce2-4ffe-960f-0f933e379952
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088981414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.4088981414
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2269723031
Short name T476
Test name
Test status
Simulation time 30128555 ps
CPU time 0.6 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:50 PM PDT 24
Peak memory 198016 kb
Host smart-33d5da66-93f6-4832-9925-2619cb265e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269723031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2269723031
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.1783718620
Short name T539
Test name
Test status
Simulation time 166138381 ps
CPU time 1.01 seconds
Started Jul 31 05:15:55 PM PDT 24
Finished Jul 31 05:15:56 PM PDT 24
Peak memory 198372 kb
Host smart-ab2b6638-216f-4a23-a625-67d71651b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783718620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1783718620
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.2623319541
Short name T354
Test name
Test status
Simulation time 63796746 ps
CPU time 0.63 seconds
Started Jul 31 05:15:38 PM PDT 24
Finished Jul 31 05:15:38 PM PDT 24
Peak memory 198116 kb
Host smart-6552bb53-fa75-4152-ae0b-6bdeac1ab1b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623319541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2623319541
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.4173330454
Short name T32
Test name
Test status
Simulation time 25799039 ps
CPU time 0.62 seconds
Started Jul 31 05:15:56 PM PDT 24
Finished Jul 31 05:15:57 PM PDT 24
Peak memory 198140 kb
Host smart-076eadf0-a749-4d6e-8c03-bc98ce07d3a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173330454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.4173330454
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2617962555
Short name T153
Test name
Test status
Simulation time 42586469 ps
CPU time 0.72 seconds
Started Jul 31 05:15:45 PM PDT 24
Finished Jul 31 05:15:45 PM PDT 24
Peak memory 201416 kb
Host smart-80512df2-ad95-46cf-a90d-10a9be1a297d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617962555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2617962555
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.105848036
Short name T48
Test name
Test status
Simulation time 62594228 ps
CPU time 0.58 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:50 PM PDT 24
Peak memory 198024 kb
Host smart-8a173e1a-e664-4531-8777-81c2d1d56c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105848036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wak
eup_race.105848036
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.1977275308
Short name T31
Test name
Test status
Simulation time 139651021 ps
CPU time 0.8 seconds
Started Jul 31 05:15:38 PM PDT 24
Finished Jul 31 05:15:39 PM PDT 24
Peak memory 199056 kb
Host smart-b3d0a44f-1dd5-475c-8270-85090ccce2a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977275308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.1977275308
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2388625287
Short name T36
Test name
Test status
Simulation time 101461799 ps
CPU time 0.88 seconds
Started Jul 31 05:15:54 PM PDT 24
Finished Jul 31 05:15:55 PM PDT 24
Peak memory 209524 kb
Host smart-26e036c8-a8bb-4731-9c60-f774dd084b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388625287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2388625287
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.657278884
Short name T377
Test name
Test status
Simulation time 62017229 ps
CPU time 0.78 seconds
Started Jul 31 05:15:54 PM PDT 24
Finished Jul 31 05:15:55 PM PDT 24
Peak memory 198092 kb
Host smart-afa1ac63-172c-40e2-9870-d0eae878becd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657278884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.657278884
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1684958381
Short name T147
Test name
Test status
Simulation time 60514140 ps
CPU time 0.62 seconds
Started Jul 31 05:15:29 PM PDT 24
Finished Jul 31 05:15:29 PM PDT 24
Peak memory 198520 kb
Host smart-65cfd743-ea8f-4b00-ae2d-659bf5e329c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684958381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1684958381
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3068657465
Short name T534
Test name
Test status
Simulation time 38338130 ps
CPU time 0.87 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:51 PM PDT 24
Peak memory 200228 kb
Host smart-71157f1c-196a-48d4-9f9d-dfd251f5696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068657465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3068657465
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1836066900
Short name T203
Test name
Test status
Simulation time 58319980 ps
CPU time 0.74 seconds
Started Jul 31 05:15:57 PM PDT 24
Finished Jul 31 05:15:58 PM PDT 24
Peak memory 198492 kb
Host smart-4b1568ae-a3d9-4bf3-8c61-7e9a94b22684
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836066900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1836066900
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.98698222
Short name T507
Test name
Test status
Simulation time 64993757 ps
CPU time 0.63 seconds
Started Jul 31 05:16:04 PM PDT 24
Finished Jul 31 05:16:05 PM PDT 24
Peak memory 198080 kb
Host smart-5b3149f9-c18b-409c-95ec-7d0de38177ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98698222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_ma
lfunc.98698222
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.1259081867
Short name T526
Test name
Test status
Simulation time 161643161 ps
CPU time 0.95 seconds
Started Jul 31 05:15:51 PM PDT 24
Finished Jul 31 05:15:52 PM PDT 24
Peak memory 198100 kb
Host smart-66e45262-6013-4131-9af8-f8346c63eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259081867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1259081867
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2053812657
Short name T40
Test name
Test status
Simulation time 37336820 ps
CPU time 0.64 seconds
Started Jul 31 05:16:05 PM PDT 24
Finished Jul 31 05:16:06 PM PDT 24
Peak memory 198128 kb
Host smart-78369b40-60ff-46b8-81e5-f207649206bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053812657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2053812657
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.437291152
Short name T399
Test name
Test status
Simulation time 82269593 ps
CPU time 0.57 seconds
Started Jul 31 05:15:59 PM PDT 24
Finished Jul 31 05:16:00 PM PDT 24
Peak memory 198080 kb
Host smart-c1b13e1f-7116-4ef7-9037-de273c6214db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437291152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.437291152
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3830403471
Short name T187
Test name
Test status
Simulation time 50725793 ps
CPU time 0.68 seconds
Started Jul 31 05:15:55 PM PDT 24
Finished Jul 31 05:15:56 PM PDT 24
Peak memory 201444 kb
Host smart-91ae1f53-f8e6-4b3e-b36e-9365004eff33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830403471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.3830403471
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2585192503
Short name T299
Test name
Test status
Simulation time 90782043 ps
CPU time 0.76 seconds
Started Jul 31 05:15:57 PM PDT 24
Finished Jul 31 05:15:58 PM PDT 24
Peak memory 199048 kb
Host smart-d577c955-c67b-4a65-baba-d6fae52641b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585192503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2585192503
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2444930435
Short name T548
Test name
Test status
Simulation time 119202981 ps
CPU time 0.94 seconds
Started Jul 31 05:16:07 PM PDT 24
Finished Jul 31 05:16:08 PM PDT 24
Peak memory 209528 kb
Host smart-87e45647-b332-4ed9-8b70-11ae87ee166c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444930435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2444930435
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2718786144
Short name T446
Test name
Test status
Simulation time 56750105 ps
CPU time 0.77 seconds
Started Jul 31 05:16:00 PM PDT 24
Finished Jul 31 05:16:01 PM PDT 24
Peak memory 198148 kb
Host smart-4a161639-5c3f-493a-b624-2da1dd028234
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718786144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2718786144
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.156576862
Short name T575
Test name
Test status
Simulation time 65498713 ps
CPU time 0.66 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:50 PM PDT 24
Peak memory 198496 kb
Host smart-b55ee34b-a834-4806-a580-a31a0afab9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156576862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.156576862
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1667132969
Short name T104
Test name
Test status
Simulation time 137465095 ps
CPU time 0.89 seconds
Started Jul 31 05:15:52 PM PDT 24
Finished Jul 31 05:15:53 PM PDT 24
Peak memory 199836 kb
Host smart-47d74e76-fbeb-4944-84c8-619e7366bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667132969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1667132969
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3135315032
Short name T348
Test name
Test status
Simulation time 37693759 ps
CPU time 0.6 seconds
Started Jul 31 05:16:11 PM PDT 24
Finished Jul 31 05:16:12 PM PDT 24
Peak memory 197976 kb
Host smart-1d2518bf-7633-4052-889a-8b48761420dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135315032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3135315032
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2862240600
Short name T39
Test name
Test status
Simulation time 162788701 ps
CPU time 0.99 seconds
Started Jul 31 05:16:07 PM PDT 24
Finished Jul 31 05:16:08 PM PDT 24
Peak memory 198388 kb
Host smart-8d7ae9e1-0849-4922-a117-7903b82d8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862240600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2862240600
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.3510062377
Short name T582
Test name
Test status
Simulation time 48222979 ps
CPU time 0.64 seconds
Started Jul 31 05:16:12 PM PDT 24
Finished Jul 31 05:16:13 PM PDT 24
Peak memory 198084 kb
Host smart-df3625d8-8a45-4e37-b926-b1e387b8ff9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510062377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3510062377
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2067517397
Short name T565
Test name
Test status
Simulation time 22458926 ps
CPU time 0.63 seconds
Started Jul 31 05:16:04 PM PDT 24
Finished Jul 31 05:16:05 PM PDT 24
Peak memory 198092 kb
Host smart-4a0d92a4-cbfe-4179-8b59-73dd1a39a024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067517397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2067517397
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3897565411
Short name T181
Test name
Test status
Simulation time 55173000 ps
CPU time 0.69 seconds
Started Jul 31 05:16:04 PM PDT 24
Finished Jul 31 05:16:05 PM PDT 24
Peak memory 201360 kb
Host smart-2447640f-2209-4bdc-8b85-771ebf923c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897565411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3897565411
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3366769001
Short name T227
Test name
Test status
Simulation time 182642813 ps
CPU time 0.78 seconds
Started Jul 31 05:15:57 PM PDT 24
Finished Jul 31 05:15:58 PM PDT 24
Peak memory 198592 kb
Host smart-319728d6-d10b-4e10-a929-013e37a4043e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366769001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3366769001
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2943659502
Short name T211
Test name
Test status
Simulation time 120562989 ps
CPU time 0.88 seconds
Started Jul 31 05:16:10 PM PDT 24
Finished Jul 31 05:16:11 PM PDT 24
Peak memory 209464 kb
Host smart-616263cb-a5c8-4042-81c4-c3a92c10262e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943659502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2943659502
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.166510545
Short name T480
Test name
Test status
Simulation time 106202789 ps
CPU time 0.87 seconds
Started Jul 31 05:16:01 PM PDT 24
Finished Jul 31 05:16:02 PM PDT 24
Peak memory 199296 kb
Host smart-02f13ae4-aa00-4c89-aeb0-1e08c30dfe63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166510545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.166510545
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3645886302
Short name T78
Test name
Test status
Simulation time 32251636 ps
CPU time 0.7 seconds
Started Jul 31 05:15:50 PM PDT 24
Finished Jul 31 05:15:51 PM PDT 24
Peak memory 199392 kb
Host smart-7d01f0fe-e23a-4c12-9c03-103830f32b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645886302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3645886302
Directory /workspace/9.pwrmgr_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%