Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.37 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 2 62 96.88


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 2 62 96.88 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 575 1 T4 12 T7 2 T13 2
auto[1] 468 1 T4 8 T29 2 T14 1


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 547 1 T4 6 T7 2 T13 2
auto[1] 496 1 T4 14 T29 4 T14 1


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 437 1 T4 8 T29 4 T14 1
auto[1] 606 1 T4 12 T7 2 T13 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 864 1 T4 20 T7 1 T13 1
auto[1] 179 1 T7 1 T13 1 T29 2


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 494 1 T4 8 T29 2 T14 1
auto[1] 549 1 T4 12 T7 2 T13 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 575 1 T4 10 T7 2 T13 2
auto[1] 468 1 T4 10 T29 3 T15 6


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 2 62 96.88 2


Automatically Generated Cross Bins for control_cross

Uncovered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 24 1 T52 1 T24 1 T44 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 5 1 T23 1 T148 1 T149 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 31 1 T4 1 T50 3 T51 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 3 1 T150 1 T151 1 T152 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 19 1 T4 2 T15 1 T24 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 3 1 T148 1 T153 1 T59 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 72 1 T7 1 T13 1 T52 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 54 1 T7 1 T13 1 T49 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 22 1 T44 1 T90 1 T92 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 4 1 T44 1 T154 1 T155 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 27 1 T4 2 T15 1 T50 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 4 1 T22 1 T156 1 T59 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 27 1 T52 1 T50 1 T89 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 39 1 T50 1 T51 1 T84 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 7 1 T22 1 T135 2 T157 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 24 1 T52 1 T50 1 T84 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T156 1 T158 1 - -
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 25 1 T4 1 T29 1 T24 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 4 1 T29 1 T48 1 T159 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 30 1 T4 1 T29 1 T15 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 8 1 T23 1 T160 1 T161 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 31 1 T15 1 T24 1 T51 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 2 1 T162 1 T46 1 - -
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 24 1 T24 1 T48 1 T50 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 3 1 T22 1 T151 1 T163 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 20 1 T4 1 T15 1 T24 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 3 1 T137 1 T164 1 T165 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 18 1 T4 1 T29 1 T51 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 2 1 T166 1 T162 1 - -
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 30 1 T4 3 T51 2 T89 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 8 1 T167 1 T168 1 T54 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 20 1 T50 1 T51 1 T89 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 1 1 T169 1 - - - -
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 24 1 T15 2 T84 1 T23 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 5 1 T23 1 T170 1 T161 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 20 1 T84 2 T85 1 T89 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 24 1 T85 1 T167 1 T171 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 7 1 T167 1 T171 1 T172 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 29 1 T48 1 T84 1 T173 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 6 1 T48 1 T174 1 T150 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 26 1 T24 1 T84 1 T173 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 6 1 T171 1 T175 1 T176 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 18 1 T4 1 T29 1 T15 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 1 1 T29 1 - - - -
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 18 1 T15 1 T44 1 T84 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 1 1 T22 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 28 1 T4 2 T14 1 T43 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 4 1 T43 1 T168 1 T47 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 40 1 T4 1 T15 1 T83 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 10 1 T22 1 T23 1 T177 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 24 1 T51 1 T174 1 T178 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 5 1 T174 1 T179 1 T180 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 24 1 T4 2 T43 1 T51 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 2 1 T181 1 T158 1 - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 30 1 T15 1 T52 1 T24 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 4 1 T181 1 T172 1 T149 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 28 1 T15 1 T50 1 T85 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 8 1 T45 1 T182 1 T166 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 27 1 T4 1 T44 1 T50 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 5 1 T44 1 T183 1 T164 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 21 1 T4 1 T83 1 T51 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 2 1 T159 1 T184 1 - -

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