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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 98.23 96.15 99.44 96.00 96.18 100.00 94.93


Total test records in report: 737
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T563 /workspace/coverage/default/40.pwrmgr_aborted_low_power.47886617 Aug 01 06:31:41 PM PDT 24 Aug 01 06:31:42 PM PDT 24 60277106 ps
T564 /workspace/coverage/default/18.pwrmgr_escalation_timeout.759782228 Aug 01 06:30:32 PM PDT 24 Aug 01 06:30:33 PM PDT 24 608859322 ps
T565 /workspace/coverage/default/26.pwrmgr_glitch.241775735 Aug 01 06:31:01 PM PDT 24 Aug 01 06:31:01 PM PDT 24 111039749 ps
T566 /workspace/coverage/default/6.pwrmgr_reset_invalid.1345890613 Aug 01 06:29:49 PM PDT 24 Aug 01 06:29:50 PM PDT 24 244995457 ps
T567 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2621244717 Aug 01 06:30:02 PM PDT 24 Aug 01 06:30:03 PM PDT 24 76714881 ps
T165 /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3836826620 Aug 01 06:31:14 PM PDT 24 Aug 01 06:31:15 PM PDT 24 47059455 ps
T568 /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2342648446 Aug 01 06:30:18 PM PDT 24 Aug 01 06:30:19 PM PDT 24 79443931 ps
T569 /workspace/coverage/default/11.pwrmgr_glitch.2872298069 Aug 01 06:30:02 PM PDT 24 Aug 01 06:30:02 PM PDT 24 124573250 ps
T570 /workspace/coverage/default/42.pwrmgr_glitch.4025086551 Aug 01 06:31:44 PM PDT 24 Aug 01 06:31:45 PM PDT 24 75940401 ps
T571 /workspace/coverage/default/39.pwrmgr_reset.3347039123 Aug 01 06:31:40 PM PDT 24 Aug 01 06:31:41 PM PDT 24 70581477 ps
T572 /workspace/coverage/default/36.pwrmgr_smoke.106360144 Aug 01 06:31:23 PM PDT 24 Aug 01 06:31:24 PM PDT 24 28833587 ps
T573 /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2675123412 Aug 01 06:31:41 PM PDT 24 Aug 01 06:31:42 PM PDT 24 55099603 ps
T574 /workspace/coverage/default/11.pwrmgr_reset_invalid.3209249854 Aug 01 06:30:15 PM PDT 24 Aug 01 06:30:17 PM PDT 24 100418212 ps
T575 /workspace/coverage/default/42.pwrmgr_reset.2353681020 Aug 01 06:31:36 PM PDT 24 Aug 01 06:31:38 PM PDT 24 96588735 ps
T576 /workspace/coverage/default/19.pwrmgr_aborted_low_power.926000288 Aug 01 06:30:34 PM PDT 24 Aug 01 06:30:36 PM PDT 24 29743264 ps
T577 /workspace/coverage/default/8.pwrmgr_smoke.1130706923 Aug 01 06:29:50 PM PDT 24 Aug 01 06:29:51 PM PDT 24 63162336 ps
T578 /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1793459421 Aug 01 06:29:38 PM PDT 24 Aug 01 06:29:38 PM PDT 24 30535904 ps
T579 /workspace/coverage/default/42.pwrmgr_lowpower_invalid.840202651 Aug 01 06:31:55 PM PDT 24 Aug 01 06:31:56 PM PDT 24 39472656 ps
T580 /workspace/coverage/default/48.pwrmgr_escalation_timeout.2712875542 Aug 01 06:32:03 PM PDT 24 Aug 01 06:32:04 PM PDT 24 603056237 ps
T581 /workspace/coverage/default/2.pwrmgr_glitch.328833799 Aug 01 06:29:32 PM PDT 24 Aug 01 06:29:32 PM PDT 24 74395450 ps
T582 /workspace/coverage/default/49.pwrmgr_smoke.3296097355 Aug 01 06:32:12 PM PDT 24 Aug 01 06:32:13 PM PDT 24 52783146 ps
T583 /workspace/coverage/default/5.pwrmgr_reset_invalid.961719563 Aug 01 06:29:43 PM PDT 24 Aug 01 06:29:44 PM PDT 24 172522942 ps
T584 /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2730751541 Aug 01 06:30:42 PM PDT 24 Aug 01 06:30:43 PM PDT 24 67615197 ps
T585 /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3249781325 Aug 01 06:30:19 PM PDT 24 Aug 01 06:30:20 PM PDT 24 104658528 ps
T586 /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3119167116 Aug 01 06:30:28 PM PDT 24 Aug 01 06:30:29 PM PDT 24 56773452 ps
T152 /workspace/coverage/default/24.pwrmgr_lowpower_invalid.69811598 Aug 01 06:30:59 PM PDT 24 Aug 01 06:31:00 PM PDT 24 53262626 ps
T587 /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.459331196 Aug 01 06:30:33 PM PDT 24 Aug 01 06:30:35 PM PDT 24 50416212 ps
T588 /workspace/coverage/default/36.pwrmgr_global_esc.2189951103 Aug 01 06:31:24 PM PDT 24 Aug 01 06:31:25 PM PDT 24 33551379 ps
T589 /workspace/coverage/default/13.pwrmgr_reset.97350263 Aug 01 06:30:20 PM PDT 24 Aug 01 06:30:21 PM PDT 24 95686573 ps
T590 /workspace/coverage/default/34.pwrmgr_escalation_timeout.896425000 Aug 01 06:31:26 PM PDT 24 Aug 01 06:31:28 PM PDT 24 606288578 ps
T591 /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2204734644 Aug 01 06:30:00 PM PDT 24 Aug 01 06:30:01 PM PDT 24 149157000 ps
T592 /workspace/coverage/default/30.pwrmgr_reset_invalid.3836325920 Aug 01 06:31:04 PM PDT 24 Aug 01 06:31:05 PM PDT 24 113407891 ps
T593 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1705119659 Aug 01 06:31:47 PM PDT 24 Aug 01 06:31:47 PM PDT 24 30402252 ps
T594 /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.482474562 Aug 01 06:31:14 PM PDT 24 Aug 01 06:31:15 PM PDT 24 57284356 ps
T163 /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2647211357 Aug 01 06:30:31 PM PDT 24 Aug 01 06:30:32 PM PDT 24 43375721 ps
T595 /workspace/coverage/default/30.pwrmgr_escalation_timeout.3401158615 Aug 01 06:31:04 PM PDT 24 Aug 01 06:31:05 PM PDT 24 162758697 ps
T596 /workspace/coverage/default/8.pwrmgr_escalation_timeout.3457074652 Aug 01 06:29:57 PM PDT 24 Aug 01 06:29:59 PM PDT 24 344514215 ps
T31 /workspace/coverage/default/3.pwrmgr_sec_cm.430022915 Aug 01 06:29:33 PM PDT 24 Aug 01 06:29:35 PM PDT 24 683680103 ps
T597 /workspace/coverage/default/18.pwrmgr_reset.2605395530 Aug 01 06:30:33 PM PDT 24 Aug 01 06:30:35 PM PDT 24 51949899 ps
T598 /workspace/coverage/default/6.pwrmgr_escalation_timeout.106467137 Aug 01 06:29:47 PM PDT 24 Aug 01 06:29:48 PM PDT 24 164622063 ps
T599 /workspace/coverage/default/32.pwrmgr_lowpower_invalid.384174799 Aug 01 06:31:15 PM PDT 24 Aug 01 06:31:16 PM PDT 24 226735532 ps
T600 /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3648028939 Aug 01 06:29:50 PM PDT 24 Aug 01 06:29:51 PM PDT 24 28706844 ps
T601 /workspace/coverage/default/11.pwrmgr_reset.372357139 Aug 01 06:30:01 PM PDT 24 Aug 01 06:30:02 PM PDT 24 57590223 ps
T169 /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1477322443 Aug 01 06:29:50 PM PDT 24 Aug 01 06:29:51 PM PDT 24 43105512 ps
T46 /workspace/coverage/default/4.pwrmgr_wakeup_reset.3347433439 Aug 01 06:29:39 PM PDT 24 Aug 01 06:29:40 PM PDT 24 33576037 ps
T602 /workspace/coverage/default/38.pwrmgr_glitch.3119215825 Aug 01 06:31:28 PM PDT 24 Aug 01 06:31:29 PM PDT 24 55094448 ps
T603 /workspace/coverage/default/13.pwrmgr_glitch.4044927698 Aug 01 06:30:18 PM PDT 24 Aug 01 06:30:19 PM PDT 24 43875955 ps
T604 /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.4184847693 Aug 01 06:31:19 PM PDT 24 Aug 01 06:31:20 PM PDT 24 90573705 ps
T605 /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.710973846 Aug 01 06:31:00 PM PDT 24 Aug 01 06:31:01 PM PDT 24 45689056 ps
T606 /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3696700666 Aug 01 06:29:49 PM PDT 24 Aug 01 06:29:50 PM PDT 24 139687281 ps
T607 /workspace/coverage/default/5.pwrmgr_reset.1282929978 Aug 01 06:29:50 PM PDT 24 Aug 01 06:29:51 PM PDT 24 88927618 ps
T608 /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2782667445 Aug 01 06:31:28 PM PDT 24 Aug 01 06:31:28 PM PDT 24 48592451 ps
T144 /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.47053909 Aug 01 06:30:02 PM PDT 24 Aug 01 06:30:03 PM PDT 24 47263699 ps
T609 /workspace/coverage/default/13.pwrmgr_smoke.1775573744 Aug 01 06:30:17 PM PDT 24 Aug 01 06:30:18 PM PDT 24 28971281 ps
T610 /workspace/coverage/default/10.pwrmgr_reset_invalid.2745565322 Aug 01 06:30:00 PM PDT 24 Aug 01 06:30:01 PM PDT 24 97678075 ps
T611 /workspace/coverage/default/15.pwrmgr_glitch.2650863968 Aug 01 06:30:31 PM PDT 24 Aug 01 06:30:32 PM PDT 24 78925907 ps
T612 /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3365899130 Aug 01 06:29:16 PM PDT 24 Aug 01 06:29:17 PM PDT 24 29809646 ps
T613 /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3113008625 Aug 01 06:31:15 PM PDT 24 Aug 01 06:31:16 PM PDT 24 30046353 ps
T614 /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.86154898 Aug 01 06:31:39 PM PDT 24 Aug 01 06:31:40 PM PDT 24 29831725 ps
T615 /workspace/coverage/default/44.pwrmgr_global_esc.1278360362 Aug 01 06:31:52 PM PDT 24 Aug 01 06:31:52 PM PDT 24 49173746 ps
T616 /workspace/coverage/default/0.pwrmgr_aborted_low_power.3880243277 Aug 01 06:29:18 PM PDT 24 Aug 01 06:29:19 PM PDT 24 31754372 ps
T617 /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4073317748 Aug 01 06:30:15 PM PDT 24 Aug 01 06:30:16 PM PDT 24 342167841 ps
T618 /workspace/coverage/default/25.pwrmgr_smoke.980801505 Aug 01 06:30:49 PM PDT 24 Aug 01 06:30:50 PM PDT 24 59090594 ps
T619 /workspace/coverage/default/9.pwrmgr_escalation_timeout.2292801782 Aug 01 06:29:59 PM PDT 24 Aug 01 06:30:01 PM PDT 24 636514025 ps
T620 /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2187540155 Aug 01 06:31:41 PM PDT 24 Aug 01 06:31:42 PM PDT 24 33165920 ps
T621 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1511606601 Aug 01 06:30:16 PM PDT 24 Aug 01 06:30:17 PM PDT 24 29327857 ps
T622 /workspace/coverage/default/38.pwrmgr_reset.3460887792 Aug 01 06:31:28 PM PDT 24 Aug 01 06:31:29 PM PDT 24 130739684 ps
T623 /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3905514720 Aug 01 06:29:27 PM PDT 24 Aug 01 06:29:28 PM PDT 24 29768184 ps
T32 /workspace/coverage/default/4.pwrmgr_sec_cm.147362582 Aug 01 06:29:49 PM PDT 24 Aug 01 06:29:50 PM PDT 24 948996111 ps
T624 /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2946882202 Aug 01 06:31:30 PM PDT 24 Aug 01 06:31:31 PM PDT 24 29312411 ps
T625 /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4077821565 Aug 01 06:30:39 PM PDT 24 Aug 01 06:30:40 PM PDT 24 69627144 ps
T626 /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1449477010 Aug 01 06:31:49 PM PDT 24 Aug 01 06:31:50 PM PDT 24 43908567 ps
T69 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2206555116 Aug 01 06:26:12 PM PDT 24 Aug 01 06:26:13 PM PDT 24 57885270 ps
T62 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.220711984 Aug 01 06:25:34 PM PDT 24 Aug 01 06:25:35 PM PDT 24 23684141 ps
T19 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.98937399 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:38 PM PDT 24 37820805 ps
T20 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.4277627954 Aug 01 06:26:03 PM PDT 24 Aug 01 06:26:05 PM PDT 24 41217871 ps
T21 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2600943674 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:47 PM PDT 24 411959032 ps
T66 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3334392207 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:45 PM PDT 24 40027408 ps
T60 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.648363367 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 24578093 ps
T67 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3459024263 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:44 PM PDT 24 46948660 ps
T61 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1204944500 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:41 PM PDT 24 25656960 ps
T96 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3502639597 Aug 01 06:25:48 PM PDT 24 Aug 01 06:25:49 PM PDT 24 95070777 ps
T53 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.4097857922 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:07 PM PDT 24 227887329 ps
T68 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3808056341 Aug 01 06:26:00 PM PDT 24 Aug 01 06:26:00 PM PDT 24 22275487 ps
T185 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.290418317 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:44 PM PDT 24 47439816 ps
T97 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.447806079 Aug 01 06:25:39 PM PDT 24 Aug 01 06:25:39 PM PDT 24 27033319 ps
T72 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3338381214 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:44 PM PDT 24 86608798 ps
T186 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3375139187 Aug 01 06:25:54 PM PDT 24 Aug 01 06:25:54 PM PDT 24 59779688 ps
T56 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1026854642 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:11 PM PDT 24 94395586 ps
T55 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1988883518 Aug 01 06:26:07 PM PDT 24 Aug 01 06:26:08 PM PDT 24 75741650 ps
T110 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.276149253 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:11 PM PDT 24 20626188 ps
T73 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3930732716 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:10 PM PDT 24 129645413 ps
T98 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.585553445 Aug 01 06:25:58 PM PDT 24 Aug 01 06:25:59 PM PDT 24 188812562 ps
T86 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.721836543 Aug 01 06:25:54 PM PDT 24 Aug 01 06:25:55 PM PDT 24 51939768 ps
T63 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3294699945 Aug 01 06:25:44 PM PDT 24 Aug 01 06:25:45 PM PDT 24 75217333 ps
T111 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4040836824 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:46 PM PDT 24 311563544 ps
T64 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4226355442 Aug 01 06:25:33 PM PDT 24 Aug 01 06:25:35 PM PDT 24 90519314 ps
T74 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2515119762 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:53 PM PDT 24 293742067 ps
T187 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2613618659 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:10 PM PDT 24 20536604 ps
T188 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3150644560 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 59966470 ps
T65 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.738902216 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:11 PM PDT 24 201679914 ps
T627 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1884306219 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:06 PM PDT 24 18097298 ps
T112 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.127762658 Aug 01 06:25:47 PM PDT 24 Aug 01 06:25:48 PM PDT 24 68883786 ps
T57 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3609878244 Aug 01 06:25:42 PM PDT 24 Aug 01 06:25:44 PM PDT 24 796471047 ps
T628 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.578810304 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:48 PM PDT 24 253371125 ps
T629 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3711149957 Aug 01 06:26:02 PM PDT 24 Aug 01 06:26:02 PM PDT 24 119169139 ps
T139 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2238014862 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:45 PM PDT 24 345517486 ps
T99 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2461342012 Aug 01 06:26:05 PM PDT 24 Aug 01 06:26:05 PM PDT 24 22592511 ps
T630 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1690447463 Aug 01 06:26:08 PM PDT 24 Aug 01 06:26:08 PM PDT 24 17705713 ps
T120 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2404676966 Aug 01 06:25:38 PM PDT 24 Aug 01 06:25:44 PM PDT 24 33750089 ps
T113 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3499613511 Aug 01 06:25:50 PM PDT 24 Aug 01 06:25:51 PM PDT 24 21835976 ps
T631 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2710318520 Aug 01 06:25:48 PM PDT 24 Aug 01 06:25:49 PM PDT 24 30383475 ps
T632 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2915689005 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:47 PM PDT 24 327324747 ps
T633 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3861579237 Aug 01 06:26:15 PM PDT 24 Aug 01 06:26:15 PM PDT 24 29360535 ps
T117 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1975352459 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:46 PM PDT 24 298753108 ps
T114 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.66888234 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:07 PM PDT 24 122777254 ps
T189 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3229112315 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:17 PM PDT 24 43005486 ps
T634 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3487608750 Aug 01 06:26:11 PM PDT 24 Aug 01 06:26:12 PM PDT 24 17352123 ps
T118 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3944271406 Aug 01 06:26:03 PM PDT 24 Aug 01 06:26:04 PM PDT 24 78420136 ps
T635 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1330596082 Aug 01 06:25:57 PM PDT 24 Aug 01 06:25:58 PM PDT 24 67894577 ps
T636 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.747262139 Aug 01 06:25:48 PM PDT 24 Aug 01 06:25:50 PM PDT 24 55270244 ps
T637 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4021836023 Aug 01 06:25:41 PM PDT 24 Aug 01 06:25:42 PM PDT 24 72644693 ps
T638 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2704418377 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:07 PM PDT 24 126761099 ps
T639 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2591938537 Aug 01 06:26:21 PM PDT 24 Aug 01 06:26:22 PM PDT 24 52886436 ps
T119 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1283231975 Aug 01 06:25:50 PM PDT 24 Aug 01 06:25:52 PM PDT 24 200781469 ps
T640 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1067726714 Aug 01 06:26:03 PM PDT 24 Aug 01 06:26:04 PM PDT 24 23574572 ps
T641 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3501941407 Aug 01 06:26:07 PM PDT 24 Aug 01 06:26:07 PM PDT 24 22212040 ps
T642 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1206343444 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:48 PM PDT 24 275469585 ps
T643 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.330913549 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:10 PM PDT 24 28578242 ps
T644 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3245917145 Aug 01 06:26:13 PM PDT 24 Aug 01 06:26:14 PM PDT 24 41204963 ps
T645 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1226624105 Aug 01 06:25:55 PM PDT 24 Aug 01 06:25:56 PM PDT 24 39199131 ps
T646 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.4282300486 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 129939888 ps
T647 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1331997808 Aug 01 06:26:13 PM PDT 24 Aug 01 06:26:14 PM PDT 24 31699976 ps
T648 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3175179635 Aug 01 06:26:03 PM PDT 24 Aug 01 06:26:03 PM PDT 24 36896610 ps
T649 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3945155661 Aug 01 06:25:50 PM PDT 24 Aug 01 06:25:51 PM PDT 24 68353478 ps
T650 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1760414391 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:41 PM PDT 24 20322943 ps
T651 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4110955726 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 36622089 ps
T652 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.822635080 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:38 PM PDT 24 40591045 ps
T653 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2563009953 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 47623772 ps
T654 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1074011373 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:47 PM PDT 24 96523904 ps
T100 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1331865375 Aug 01 06:25:59 PM PDT 24 Aug 01 06:26:00 PM PDT 24 22284517 ps
T70 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1211427090 Aug 01 06:25:49 PM PDT 24 Aug 01 06:25:50 PM PDT 24 390388289 ps
T655 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3173979452 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:10 PM PDT 24 29674193 ps
T656 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1971674856 Aug 01 06:26:11 PM PDT 24 Aug 01 06:26:13 PM PDT 24 283117416 ps
T657 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.4257629307 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 96601313 ps
T658 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2554210543 Aug 01 06:26:01 PM PDT 24 Aug 01 06:26:02 PM PDT 24 17751035 ps
T659 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2199916267 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:38 PM PDT 24 42274569 ps
T660 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3956430978 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:09 PM PDT 24 46534329 ps
T661 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3934000312 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:45 PM PDT 24 226236983 ps
T662 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1477712556 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:47 PM PDT 24 159482638 ps
T101 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2883603200 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:43 PM PDT 24 21516611 ps
T663 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1832651098 Aug 01 06:26:11 PM PDT 24 Aug 01 06:26:12 PM PDT 24 43137139 ps
T664 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3825687850 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:10 PM PDT 24 21025648 ps
T102 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2817710679 Aug 01 06:26:16 PM PDT 24 Aug 01 06:26:17 PM PDT 24 20717644 ps
T665 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2030285459 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:05 PM PDT 24 71563454 ps
T666 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.82355997 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:05 PM PDT 24 24771059 ps
T667 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2525378935 Aug 01 06:25:55 PM PDT 24 Aug 01 06:25:57 PM PDT 24 98426997 ps
T668 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3107525004 Aug 01 06:25:56 PM PDT 24 Aug 01 06:25:57 PM PDT 24 58348900 ps
T669 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3564039939 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:46 PM PDT 24 34146943 ps
T670 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.720270909 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:10 PM PDT 24 46618800 ps
T671 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1818593192 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:48 PM PDT 24 328620141 ps
T103 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.218519057 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:41 PM PDT 24 25371871 ps
T672 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.261410492 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:05 PM PDT 24 44504127 ps
T140 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1111802093 Aug 01 06:25:39 PM PDT 24 Aug 01 06:25:40 PM PDT 24 201537010 ps
T673 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.444777048 Aug 01 06:26:13 PM PDT 24 Aug 01 06:26:14 PM PDT 24 30692523 ps
T674 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2121840597 Aug 01 06:26:02 PM PDT 24 Aug 01 06:26:03 PM PDT 24 61402325 ps
T104 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3318197551 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:07 PM PDT 24 19675619 ps
T675 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.734976563 Aug 01 06:25:54 PM PDT 24 Aug 01 06:25:54 PM PDT 24 38240577 ps
T676 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.176601427 Aug 01 06:25:54 PM PDT 24 Aug 01 06:25:55 PM PDT 24 31137978 ps
T677 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3134695263 Aug 01 06:25:38 PM PDT 24 Aug 01 06:25:40 PM PDT 24 145793368 ps
T678 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.431758501 Aug 01 06:26:06 PM PDT 24 Aug 01 06:26:06 PM PDT 24 21882886 ps
T679 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3882298862 Aug 01 06:25:53 PM PDT 24 Aug 01 06:25:54 PM PDT 24 67054477 ps
T680 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2198298964 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:44 PM PDT 24 127217364 ps
T681 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2006754494 Aug 01 06:26:08 PM PDT 24 Aug 01 06:26:09 PM PDT 24 76636632 ps
T682 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2764988001 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:11 PM PDT 24 35152235 ps
T683 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3134073513 Aug 01 06:26:07 PM PDT 24 Aug 01 06:26:09 PM PDT 24 150691898 ps
T684 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3896701455 Aug 01 06:25:57 PM PDT 24 Aug 01 06:25:58 PM PDT 24 31017111 ps
T685 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3229320074 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 31609995 ps
T75 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1715809974 Aug 01 06:26:02 PM PDT 24 Aug 01 06:26:04 PM PDT 24 210161866 ps
T686 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.325279997 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:04 PM PDT 24 151515926 ps
T687 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.113463320 Aug 01 06:26:05 PM PDT 24 Aug 01 06:26:06 PM PDT 24 20047005 ps
T688 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.275545066 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 38737889 ps
T689 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2537664632 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:11 PM PDT 24 19927038 ps
T690 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3246061503 Aug 01 06:25:59 PM PDT 24 Aug 01 06:26:01 PM PDT 24 206664147 ps
T691 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1488013361 Aug 01 06:26:03 PM PDT 24 Aug 01 06:26:04 PM PDT 24 323121673 ps
T692 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3544877939 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:04 PM PDT 24 21896177 ps
T693 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2259320062 Aug 01 06:26:05 PM PDT 24 Aug 01 06:26:06 PM PDT 24 121560087 ps
T694 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.930348144 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:41 PM PDT 24 40173561 ps
T109 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2531696187 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:46 PM PDT 24 28478795 ps
T695 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.397159895 Aug 01 06:26:00 PM PDT 24 Aug 01 06:26:01 PM PDT 24 125289574 ps
T696 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3838114072 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:11 PM PDT 24 242644761 ps
T697 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1777038709 Aug 01 06:25:50 PM PDT 24 Aug 01 06:25:51 PM PDT 24 33665526 ps
T698 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4020157930 Aug 01 06:25:33 PM PDT 24 Aug 01 06:25:37 PM PDT 24 564932112 ps
T699 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1486936189 Aug 01 06:25:49 PM PDT 24 Aug 01 06:25:52 PM PDT 24 220035167 ps
T700 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1640079499 Aug 01 06:25:44 PM PDT 24 Aug 01 06:25:45 PM PDT 24 66980122 ps
T701 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.754657440 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:41 PM PDT 24 53642416 ps
T702 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1267714163 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:18 PM PDT 24 30162172 ps
T703 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2405997539 Aug 01 06:26:16 PM PDT 24 Aug 01 06:26:16 PM PDT 24 20909958 ps
T704 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.415044925 Aug 01 06:25:54 PM PDT 24 Aug 01 06:25:54 PM PDT 24 18883875 ps
T705 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3424302309 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:46 PM PDT 24 170279620 ps
T706 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3495914446 Aug 01 06:25:42 PM PDT 24 Aug 01 06:25:44 PM PDT 24 119887740 ps
T71 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3890403047 Aug 01 06:25:43 PM PDT 24 Aug 01 06:25:45 PM PDT 24 112408517 ps
T707 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1716181784 Aug 01 06:25:42 PM PDT 24 Aug 01 06:25:43 PM PDT 24 95931387 ps
T708 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4016861644 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:10 PM PDT 24 21531262 ps
T709 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1917030568 Aug 01 06:25:48 PM PDT 24 Aug 01 06:25:48 PM PDT 24 126614259 ps
T710 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3303655666 Aug 01 06:26:08 PM PDT 24 Aug 01 06:26:09 PM PDT 24 19196173 ps
T711 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1193387366 Aug 01 06:25:48 PM PDT 24 Aug 01 06:25:49 PM PDT 24 52723280 ps
T712 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3919789205 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:47 PM PDT 24 49694323 ps
T713 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.649304428 Aug 01 06:26:02 PM PDT 24 Aug 01 06:26:03 PM PDT 24 473544202 ps
T714 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1647923463 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 66196717 ps
T715 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.976856453 Aug 01 06:25:47 PM PDT 24 Aug 01 06:25:47 PM PDT 24 71599483 ps
T716 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3299971220 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:17 PM PDT 24 25887502 ps
T105 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3643206512 Aug 01 06:26:04 PM PDT 24 Aug 01 06:26:04 PM PDT 24 23790083 ps
T717 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2457632702 Aug 01 06:26:05 PM PDT 24 Aug 01 06:26:06 PM PDT 24 62374140 ps
T718 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.414003911 Aug 01 06:26:07 PM PDT 24 Aug 01 06:26:08 PM PDT 24 29712030 ps
T719 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3189841521 Aug 01 06:25:44 PM PDT 24 Aug 01 06:25:45 PM PDT 24 24260658 ps
T106 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4239111484 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:38 PM PDT 24 47772931 ps
T720 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1326872314 Aug 01 06:25:56 PM PDT 24 Aug 01 06:25:57 PM PDT 24 45322788 ps
T721 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.472446710 Aug 01 06:26:02 PM PDT 24 Aug 01 06:26:04 PM PDT 24 351854774 ps
T722 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2091732758 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:09 PM PDT 24 27836599 ps
T723 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2678319780 Aug 01 06:25:52 PM PDT 24 Aug 01 06:25:54 PM PDT 24 84091394 ps
T724 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2019559880 Aug 01 06:26:14 PM PDT 24 Aug 01 06:26:15 PM PDT 24 15969201 ps
T725 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.899865605 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:10 PM PDT 24 265844667 ps
T107 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3400307443 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:38 PM PDT 24 66535962 ps
T726 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3733363021 Aug 01 06:25:55 PM PDT 24 Aug 01 06:25:56 PM PDT 24 102096956 ps
T727 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3214303137 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 124836506 ps
T728 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2860721142 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:48 PM PDT 24 97931027 ps
T729 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1536427025 Aug 01 06:25:45 PM PDT 24 Aug 01 06:25:46 PM PDT 24 118152213 ps
T730 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.4264046210 Aug 01 06:25:46 PM PDT 24 Aug 01 06:25:48 PM PDT 24 37047203 ps
T731 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3671234032 Aug 01 06:25:37 PM PDT 24 Aug 01 06:25:39 PM PDT 24 211475753 ps
T732 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2200686733 Aug 01 06:25:47 PM PDT 24 Aug 01 06:25:47 PM PDT 24 20362765 ps
T733 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.294572278 Aug 01 06:25:56 PM PDT 24 Aug 01 06:25:57 PM PDT 24 28732427 ps
T734 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2704088496 Aug 01 06:25:51 PM PDT 24 Aug 01 06:25:52 PM PDT 24 75371268 ps
T735 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4210503313 Aug 01 06:25:58 PM PDT 24 Aug 01 06:25:59 PM PDT 24 37618541 ps
T108 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1862196118 Aug 01 06:25:42 PM PDT 24 Aug 01 06:25:43 PM PDT 24 30917794 ps
T736 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2148120238 Aug 01 06:25:56 PM PDT 24 Aug 01 06:25:56 PM PDT 24 19819566 ps
T737 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3859676974 Aug 01 06:25:40 PM PDT 24 Aug 01 06:25:42 PM PDT 24 183610091 ps

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.351980426
Short name T1
Test name
Test status
Simulation time 100280477 ps
CPU time 1.06 seconds
Started Aug 01 06:30:27 PM PDT 24
Finished Aug 01 06:30:28 PM PDT 24
Peak memory 209512 kb
Host smart-9d3cfc69-a865-42ff-b587-1302ffc9b351
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351980426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.351980426
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3340653901
Short name T13
Test name
Test status
Simulation time 30485405 ps
CPU time 0.67 seconds
Started Aug 01 06:31:05 PM PDT 24
Finished Aug 01 06:31:06 PM PDT 24
Peak memory 198500 kb
Host smart-0e7fed0f-53b6-48c0-88b2-b1ade3dc9836
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340653901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3340653901
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1312621388
Short name T16
Test name
Test status
Simulation time 425716735 ps
CPU time 1.28 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 216972 kb
Host smart-0a9df80f-bddd-448b-8fda-5c9e663a5e24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312621388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1312621388
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1404688810
Short name T24
Test name
Test status
Simulation time 60384023 ps
CPU time 0.72 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 198988 kb
Host smart-151ceb3e-02c1-4c16-831d-17d15aed1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404688810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1404688810
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2600943674
Short name T21
Test name
Test status
Simulation time 411959032 ps
CPU time 1.54 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 200456 kb
Host smart-9fdf95d9-869e-4625-9139-f4abaa1181b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600943674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2600943674
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2952427694
Short name T29
Test name
Test status
Simulation time 46426669 ps
CPU time 0.75 seconds
Started Aug 01 06:31:49 PM PDT 24
Finished Aug 01 06:31:50 PM PDT 24
Peak memory 201400 kb
Host smart-8a40d72e-e0a8-43a7-86a2-d163ab84edf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952427694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2952427694
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.613529292
Short name T22
Test name
Test status
Simulation time 81888325 ps
CPU time 0.84 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 198576 kb
Host smart-9ebdcf82-52e6-45d9-95e9-a661484f2159
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613529292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.613529292
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.4237301363
Short name T130
Test name
Test status
Simulation time 59172933 ps
CPU time 0.82 seconds
Started Aug 01 06:31:54 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 199124 kb
Host smart-e72fe874-4f3d-48c1-9ffa-1ae18c144797
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237301363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.4237301363
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1988883518
Short name T55
Test name
Test status
Simulation time 75741650 ps
CPU time 1.43 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:08 PM PDT 24
Peak memory 197456 kb
Host smart-e0377506-b29c-4df9-b1e6-4e7345521737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988883518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1988883518
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.2270367387
Short name T89
Test name
Test status
Simulation time 45378044 ps
CPU time 0.96 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 200284 kb
Host smart-8c53888b-ae5c-407d-892d-52238277f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270367387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2270367387
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.4165235370
Short name T23
Test name
Test status
Simulation time 71288496 ps
CPU time 0.74 seconds
Started Aug 01 06:29:30 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 198300 kb
Host smart-cd4b1772-31c6-4fe9-81a7-c3818d3756ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165235370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.4165235370
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2952780439
Short name T76
Test name
Test status
Simulation time 51996427 ps
CPU time 0.8 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 198176 kb
Host smart-2c56d497-b692-4dba-af17-c236a7dfc283
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952780439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2952780439
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3808056341
Short name T68
Test name
Test status
Simulation time 22275487 ps
CPU time 0.62 seconds
Started Aug 01 06:26:00 PM PDT 24
Finished Aug 01 06:26:00 PM PDT 24
Peak memory 195036 kb
Host smart-e7290593-7d78-475f-b47c-a6e5c0430c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808056341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3808056341
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3502639597
Short name T96
Test name
Test status
Simulation time 95070777 ps
CPU time 0.71 seconds
Started Aug 01 06:25:48 PM PDT 24
Finished Aug 01 06:25:49 PM PDT 24
Peak memory 197288 kb
Host smart-1c09bd84-a3e9-4c98-ba11-6216e76c975e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502639597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3502639597
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.2652288820
Short name T5
Test name
Test status
Simulation time 605680261 ps
CPU time 1.08 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:03 PM PDT 24
Peak memory 198128 kb
Host smart-4fa1738c-8cbc-435a-a758-ef032cbae0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652288820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2652288820
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.1824346162
Short name T25
Test name
Test status
Simulation time 64097789 ps
CPU time 0.73 seconds
Started Aug 01 06:30:16 PM PDT 24
Finished Aug 01 06:30:17 PM PDT 24
Peak memory 199112 kb
Host smart-86736e9b-12d3-4c6a-9d84-c529c4bf4272
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824346162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.1824346162
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.1755953638
Short name T128
Test name
Test status
Simulation time 138084562 ps
CPU time 0.68 seconds
Started Aug 01 06:30:28 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 198484 kb
Host smart-36684058-6f9b-4d73-b27f-9c52b625b526
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755953638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.1755953638
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.285910467
Short name T59
Test name
Test status
Simulation time 48353605 ps
CPU time 0.78 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 198556 kb
Host smart-c9413a70-2ecc-42e1-bf7b-9fcb7f21e647
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285910467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_c
m_ctrl_config_regwen.285910467
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.3347433439
Short name T46
Test name
Test status
Simulation time 33576037 ps
CPU time 0.68 seconds
Started Aug 01 06:29:39 PM PDT 24
Finished Aug 01 06:29:40 PM PDT 24
Peak memory 199136 kb
Host smart-017435bf-e246-4729-b0da-9fb86e82a600
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347433439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3347433439
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2172454323
Short name T174
Test name
Test status
Simulation time 80145663 ps
CPU time 0.66 seconds
Started Aug 01 06:30:43 PM PDT 24
Finished Aug 01 06:30:44 PM PDT 24
Peak memory 201404 kb
Host smart-2c1f986a-6df4-491b-9aa3-68627be74a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172454323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2172454323
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.690893018
Short name T131
Test name
Test status
Simulation time 55224282 ps
CPU time 0.82 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 199208 kb
Host smart-b9270f87-7dc5-4e4c-8126-d7e47afccc25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690893018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.690893018
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.1093104721
Short name T172
Test name
Test status
Simulation time 45493143 ps
CPU time 0.7 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 201420 kb
Host smart-0b8e17ef-1896-4143-ae5d-9e5c0739fc2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093104721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.1093104721
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3155854669
Short name T132
Test name
Test status
Simulation time 58608648 ps
CPU time 0.75 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 199140 kb
Host smart-eebea806-2782-4558-ad03-52a280f578b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155854669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3155854669
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3930732716
Short name T73
Test name
Test status
Simulation time 129645413 ps
CPU time 1.14 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 200764 kb
Host smart-3beb6d3c-6d87-40d4-806c-0e38c34907d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930732716 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3930732716
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3768459873
Short name T44
Test name
Test status
Simulation time 60923394 ps
CPU time 0.66 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 201344 kb
Host smart-eb343c67-007b-4261-9f5a-797b958bd30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768459873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.3768459873
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.1846890814
Short name T45
Test name
Test status
Simulation time 23219070 ps
CPU time 0.69 seconds
Started Aug 01 06:31:00 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 198728 kb
Host smart-75383631-53a2-4a6d-bcf5-c48bacef2927
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846890814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.1846890814
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3942771981
Short name T168
Test name
Test status
Simulation time 44460958 ps
CPU time 0.72 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 201400 kb
Host smart-7f3cb8cc-249d-4d27-82a7-8c0282c8dad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942771981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3942771981
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1760414391
Short name T650
Test name
Test status
Simulation time 20322943 ps
CPU time 0.62 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:41 PM PDT 24
Peak memory 195092 kb
Host smart-bf80057e-97eb-4b8e-9cb3-64646e754974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760414391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1760414391
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3985428895
Short name T147
Test name
Test status
Simulation time 75101736 ps
CPU time 0.69 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 198312 kb
Host smart-77d9ee9b-a9af-4c1e-8d09-e51603800f37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985428895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.3985428895
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2743983903
Short name T158
Test name
Test status
Simulation time 304320513 ps
CPU time 0.65 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 201424 kb
Host smart-2edc1729-4414-418c-bc00-874cce647833
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743983903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2743983903
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.355000524
Short name T197
Test name
Test status
Simulation time 56587035 ps
CPU time 0.68 seconds
Started Aug 01 06:31:32 PM PDT 24
Finished Aug 01 06:31:33 PM PDT 24
Peak memory 198300 kb
Host smart-78fb1138-02cd-47ad-b49e-79ce6a51f7a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355000524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wa
keup_race.355000524
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2976443530
Short name T50
Test name
Test status
Simulation time 72189759 ps
CPU time 0.83 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 200120 kb
Host smart-9f70ce14-19d3-4936-8e85-4d225f74686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976443530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2976443530
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2238014862
Short name T139
Test name
Test status
Simulation time 345517486 ps
CPU time 1.55 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 200728 kb
Host smart-4e64448d-2fa9-4d4b-a0d9-18d4ce2b439d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238014862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2238014862
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.47053909
Short name T144
Test name
Test status
Simulation time 47263699 ps
CPU time 0.79 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:03 PM PDT 24
Peak memory 198576 kb
Host smart-d13f4344-e36c-49d4-bb1d-bf7c4c81ed44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47053909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disab
le_rom_integrity_check.47053909
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.256313093
Short name T192
Test name
Test status
Simulation time 67940657 ps
CPU time 0.79 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 198448 kb
Host smart-3c07d770-f65d-45e6-b15c-707979b0ded0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256313093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa
ble_rom_integrity_check.256313093
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.911234829
Short name T333
Test name
Test status
Simulation time 28494029 ps
CPU time 0.66 seconds
Started Aug 01 06:30:20 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 199396 kb
Host smart-2f2f02f9-d157-4a7c-9736-f7f3a3c72bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911234829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.911234829
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3231400886
Short name T166
Test name
Test status
Simulation time 55394080 ps
CPU time 0.7 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 201488 kb
Host smart-290f4854-a4cf-48cc-bc97-c11addaa8823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231400886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3231400886
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.69811598
Short name T152
Test name
Test status
Simulation time 53262626 ps
CPU time 0.72 seconds
Started Aug 01 06:30:59 PM PDT 24
Finished Aug 01 06:31:00 PM PDT 24
Peak memory 201436 kb
Host smart-f12806b4-87db-416b-b02c-88a7fc04b746
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69811598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid
.69811598
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2089402547
Short name T159
Test name
Test status
Simulation time 38755018 ps
CPU time 0.7 seconds
Started Aug 01 06:30:50 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 201484 kb
Host smart-ef1dc32b-4cc7-4baf-8b87-afa9b7e51166
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089402547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2089402547
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.2703999271
Short name T135
Test name
Test status
Simulation time 74542628 ps
CPU time 0.67 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 198284 kb
Host smart-c40aa2b1-043a-47e7-87c0-9ccf025d0299
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703999271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2703999271
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3836826620
Short name T165
Test name
Test status
Simulation time 47059455 ps
CPU time 0.74 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 201440 kb
Host smart-78900dc9-9671-4998-8a82-356cc7ffde92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836826620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.3836826620
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.2211398118
Short name T138
Test name
Test status
Simulation time 91286303 ps
CPU time 0.97 seconds
Started Aug 01 06:31:18 PM PDT 24
Finished Aug 01 06:31:19 PM PDT 24
Peak memory 200928 kb
Host smart-05a8df34-315b-4535-9417-08c50c209e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211398118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.2211398118
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1477322443
Short name T169
Test name
Test status
Simulation time 43105512 ps
CPU time 0.76 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 201460 kb
Host smart-28da7b6f-812f-4231-a32a-806453af4bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477322443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1477322443
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3214303137
Short name T727
Test name
Test status
Simulation time 124836506 ps
CPU time 1.15 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 200460 kb
Host smart-1e839d0a-dee9-4714-9fdd-8d4cc7e967ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214303137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.3214303137
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.763588756
Short name T210
Test name
Test status
Simulation time 79383143 ps
CPU time 0.63 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 198076 kb
Host smart-c81df163-51f1-484d-bc24-551da2c25e6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763588756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.763588756
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.218519057
Short name T103
Test name
Test status
Simulation time 25371871 ps
CPU time 0.94 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:41 PM PDT 24
Peak memory 195072 kb
Host smart-2836ed18-aea0-46a6-b612-dff15e05e371
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218519057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.218519057
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3859676974
Short name T737
Test name
Test status
Simulation time 183610091 ps
CPU time 1.72 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:42 PM PDT 24
Peak memory 195132 kb
Host smart-be1fe5ad-dd9b-408b-be22-846bbecfab2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859676974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
859676974
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2404676966
Short name T120
Test name
Test status
Simulation time 33750089 ps
CPU time 0.62 seconds
Started Aug 01 06:25:38 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 195156 kb
Host smart-2e021b2b-0d39-410f-8601-7cf0e170e565
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404676966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
404676966
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.822635080
Short name T652
Test name
Test status
Simulation time 40591045 ps
CPU time 0.85 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 195300 kb
Host smart-f60dbc72-8d40-42ad-a782-6d14c13025d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822635080 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.822635080
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.220711984
Short name T62
Test name
Test status
Simulation time 23684141 ps
CPU time 0.64 seconds
Started Aug 01 06:25:34 PM PDT 24
Finished Aug 01 06:25:35 PM PDT 24
Peak memory 195100 kb
Host smart-83904c0a-7aad-417d-834c-dabdde450026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220711984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.220711984
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2199916267
Short name T659
Test name
Test status
Simulation time 42274569 ps
CPU time 0.84 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 200060 kb
Host smart-4728db58-db34-4b9e-8089-f7e6122cd435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199916267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2199916267
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.754657440
Short name T701
Test name
Test status
Simulation time 53642416 ps
CPU time 1.24 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:41 PM PDT 24
Peak memory 196512 kb
Host smart-55931631-66c3-45f6-90db-52994a58005d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754657440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.754657440
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3609878244
Short name T57
Test name
Test status
Simulation time 796471047 ps
CPU time 1.48 seconds
Started Aug 01 06:25:42 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 200504 kb
Host smart-0ec5b8cd-22c9-49ee-9c76-fa1b3416c078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609878244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.3609878244
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.176601427
Short name T676
Test name
Test status
Simulation time 31137978 ps
CPU time 0.81 seconds
Started Aug 01 06:25:54 PM PDT 24
Finished Aug 01 06:25:55 PM PDT 24
Peak memory 195064 kb
Host smart-8bb578b4-ea2d-413c-90a1-de7c62b92437
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176601427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.176601427
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3134695263
Short name T677
Test name
Test status
Simulation time 145793368 ps
CPU time 1.9 seconds
Started Aug 01 06:25:38 PM PDT 24
Finished Aug 01 06:25:40 PM PDT 24
Peak memory 195260 kb
Host smart-83003c10-6c3f-4b6c-bcea-f9960246dbb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134695263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
134695263
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4021836023
Short name T637
Test name
Test status
Simulation time 72644693 ps
CPU time 0.67 seconds
Started Aug 01 06:25:41 PM PDT 24
Finished Aug 01 06:25:42 PM PDT 24
Peak memory 198344 kb
Host smart-c3843673-538a-4fb6-94b6-6aa338c38491
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021836023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.4
021836023
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.98937399
Short name T19
Test name
Test status
Simulation time 37820805 ps
CPU time 0.76 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 195184 kb
Host smart-3df57c70-c6e2-49e4-a8a2-cea7501c4df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98937399 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.98937399
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4239111484
Short name T106
Test name
Test status
Simulation time 47772931 ps
CPU time 0.63 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 195100 kb
Host smart-869defb7-f739-486b-8f64-b24d4dc577ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239111484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.4239111484
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.930348144
Short name T694
Test name
Test status
Simulation time 40173561 ps
CPU time 0.58 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:41 PM PDT 24
Peak memory 195052 kb
Host smart-89371ed8-7620-42ec-bfee-5c0d5b64915c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930348144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.930348144
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3229320074
Short name T685
Test name
Test status
Simulation time 31609995 ps
CPU time 0.79 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195188 kb
Host smart-a797e25b-cd1a-40ba-bd7d-eb78c7ca06cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229320074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3229320074
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3294699945
Short name T63
Test name
Test status
Simulation time 75217333 ps
CPU time 1.09 seconds
Started Aug 01 06:25:44 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 197224 kb
Host smart-6ed13d87-a585-4672-b0d2-e60355870452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294699945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3294699945
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3671234032
Short name T731
Test name
Test status
Simulation time 211475753 ps
CPU time 1.79 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:39 PM PDT 24
Peak memory 195356 kb
Host smart-34ea132c-f1b7-49fb-a17e-160d981bd3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671234032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3671234032
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2121840597
Short name T674
Test name
Test status
Simulation time 61402325 ps
CPU time 0.89 seconds
Started Aug 01 06:26:02 PM PDT 24
Finished Aug 01 06:26:03 PM PDT 24
Peak memory 195236 kb
Host smart-ecf73afc-3ff0-4572-8508-51f5d768a3c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121840597 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2121840597
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2200686733
Short name T732
Test name
Test status
Simulation time 20362765 ps
CPU time 0.65 seconds
Started Aug 01 06:25:47 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195148 kb
Host smart-b8abfef6-9f2f-4c98-acf5-026fbde7e251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200686733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2200686733
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3825687850
Short name T664
Test name
Test status
Simulation time 21025648 ps
CPU time 0.61 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195044 kb
Host smart-bd0d1b75-5471-48ff-86da-ed9754d63fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825687850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3825687850
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2704418377
Short name T638
Test name
Test status
Simulation time 126761099 ps
CPU time 1.01 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:07 PM PDT 24
Peak memory 198668 kb
Host smart-55652aa2-71cb-4442-8808-3663f6c5b4a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704418377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.2704418377
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.472446710
Short name T721
Test name
Test status
Simulation time 351854774 ps
CPU time 1.92 seconds
Started Aug 01 06:26:02 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 197532 kb
Host smart-710d26d5-8a27-4b7c-a91c-b4da28c391fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472446710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.472446710
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3919789205
Short name T712
Test name
Test status
Simulation time 49694323 ps
CPU time 0.74 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195288 kb
Host smart-0864dfe8-da07-430e-a3e3-e38a5c89c911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919789205 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.3919789205
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2883603200
Short name T101
Test name
Test status
Simulation time 21516611 ps
CPU time 0.64 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:43 PM PDT 24
Peak memory 195148 kb
Host smart-516e47f0-c297-4c61-a486-bbbd27a1baa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883603200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2883603200
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.976856453
Short name T715
Test name
Test status
Simulation time 71599483 ps
CPU time 0.59 seconds
Started Aug 01 06:25:47 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195056 kb
Host smart-e7e494ca-458b-42f6-a048-64c363fcd697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976856453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.976856453
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4040836824
Short name T111
Test name
Test status
Simulation time 311563544 ps
CPU time 0.91 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 198664 kb
Host smart-f2dadc74-d53c-4713-8ce8-c23561dcfb66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040836824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.4040836824
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.747262139
Short name T636
Test name
Test status
Simulation time 55270244 ps
CPU time 1.51 seconds
Started Aug 01 06:25:48 PM PDT 24
Finished Aug 01 06:25:50 PM PDT 24
Peak memory 199296 kb
Host smart-289b9dce-8e1c-43a1-88f3-3b50cf671f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747262139 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.747262139
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2704088496
Short name T734
Test name
Test status
Simulation time 75371268 ps
CPU time 0.65 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 197728 kb
Host smart-491989d4-dd12-40d6-a576-38b649e172ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704088496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2704088496
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2710318520
Short name T631
Test name
Test status
Simulation time 30383475 ps
CPU time 0.61 seconds
Started Aug 01 06:25:48 PM PDT 24
Finished Aug 01 06:25:49 PM PDT 24
Peak memory 195060 kb
Host smart-37bd429b-5462-4964-bd4e-5ae5f1a37a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710318520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2710318520
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3134073513
Short name T683
Test name
Test status
Simulation time 150691898 ps
CPU time 0.89 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:09 PM PDT 24
Peak memory 198640 kb
Host smart-8a031427-cab3-4ab0-bdbe-4103678a0710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134073513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3134073513
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2860721142
Short name T728
Test name
Test status
Simulation time 97931027 ps
CPU time 1.49 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 197412 kb
Host smart-64913074-11d7-4fb2-add1-73f49e170af5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860721142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2860721142
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1715809974
Short name T75
Test name
Test status
Simulation time 210161866 ps
CPU time 1.1 seconds
Started Aug 01 06:26:02 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 200632 kb
Host smart-9aff7e0a-32fb-4add-80e4-88ac8cefe8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715809974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1715809974
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1193387366
Short name T711
Test name
Test status
Simulation time 52723280 ps
CPU time 0.92 seconds
Started Aug 01 06:25:48 PM PDT 24
Finished Aug 01 06:25:49 PM PDT 24
Peak memory 195272 kb
Host smart-b0d18875-af28-47f3-b3ee-4746b8c8a7fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193387366 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.1193387366
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1777038709
Short name T697
Test name
Test status
Simulation time 33665526 ps
CPU time 0.63 seconds
Started Aug 01 06:25:50 PM PDT 24
Finished Aug 01 06:25:51 PM PDT 24
Peak memory 195060 kb
Host smart-3a34daf7-873f-4bd3-bc0a-216ab667f1d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777038709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1777038709
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1330596082
Short name T635
Test name
Test status
Simulation time 67894577 ps
CPU time 0.83 seconds
Started Aug 01 06:25:57 PM PDT 24
Finished Aug 01 06:25:58 PM PDT 24
Peak memory 199952 kb
Host smart-3cf93b6d-3e85-419b-a82d-99d0ddd72a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330596082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1330596082
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3944271406
Short name T118
Test name
Test status
Simulation time 78420136 ps
CPU time 1.53 seconds
Started Aug 01 06:26:03 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 196508 kb
Host smart-26e0273d-3b7f-4209-99e4-fb1c65588669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944271406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3944271406
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1283231975
Short name T119
Test name
Test status
Simulation time 200781469 ps
CPU time 1.65 seconds
Started Aug 01 06:25:50 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 195420 kb
Host smart-c257d81e-9712-45e5-abf3-e4d45ec64fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283231975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1283231975
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1226624105
Short name T645
Test name
Test status
Simulation time 39199131 ps
CPU time 0.95 seconds
Started Aug 01 06:25:55 PM PDT 24
Finished Aug 01 06:25:56 PM PDT 24
Peak memory 195264 kb
Host smart-3a94f673-5837-4af5-afb7-7b1ad3f46ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226624105 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1226624105
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1331865375
Short name T100
Test name
Test status
Simulation time 22284517 ps
CPU time 0.67 seconds
Started Aug 01 06:25:59 PM PDT 24
Finished Aug 01 06:26:00 PM PDT 24
Peak memory 197232 kb
Host smart-ceabe779-4d58-4ae4-ba36-74ac899420d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331865375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1331865375
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2554210543
Short name T658
Test name
Test status
Simulation time 17751035 ps
CPU time 0.66 seconds
Started Aug 01 06:26:01 PM PDT 24
Finished Aug 01 06:26:02 PM PDT 24
Peak memory 195080 kb
Host smart-cc02c88c-83a7-42ac-a108-b94afc90bd87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554210543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2554210543
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.330913549
Short name T643
Test name
Test status
Simulation time 28578242 ps
CPU time 0.75 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195132 kb
Host smart-d2a0d011-4334-4b1b-be60-78981fd32222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330913549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.330913549
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3495914446
Short name T706
Test name
Test status
Simulation time 119887740 ps
CPU time 1.74 seconds
Started Aug 01 06:25:42 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 197492 kb
Host smart-bae1ba4d-5c15-4cc8-bb9c-383940eb5bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495914446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3495914446
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1716181784
Short name T707
Test name
Test status
Simulation time 95931387 ps
CPU time 1.09 seconds
Started Aug 01 06:25:42 PM PDT 24
Finished Aug 01 06:25:43 PM PDT 24
Peak memory 200164 kb
Host smart-ffcfbb01-0326-4b95-a0b8-2b5787f04cab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716181784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1716181784
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3318197551
Short name T104
Test name
Test status
Simulation time 19675619 ps
CPU time 0.66 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:07 PM PDT 24
Peak memory 195112 kb
Host smart-913f0065-39d2-4733-8f4c-fc8e20022e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318197551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3318197551
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1832651098
Short name T663
Test name
Test status
Simulation time 43137139 ps
CPU time 0.61 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:12 PM PDT 24
Peak memory 195100 kb
Host smart-2016549f-3fa3-4b1e-8556-fcad9cda5ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832651098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1832651098
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1267714163
Short name T702
Test name
Test status
Simulation time 30162172 ps
CPU time 0.78 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:18 PM PDT 24
Peak memory 197364 kb
Host smart-5da550be-1850-4228-80c6-529b8dc578ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267714163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1267714163
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.578810304
Short name T628
Test name
Test status
Simulation time 253371125 ps
CPU time 1.74 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 196292 kb
Host smart-f4ff3f4c-0662-4cb1-893c-e18dfa7b9dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578810304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.578810304
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3246061503
Short name T690
Test name
Test status
Simulation time 206664147 ps
CPU time 1.73 seconds
Started Aug 01 06:25:59 PM PDT 24
Finished Aug 01 06:26:01 PM PDT 24
Peak memory 200664 kb
Host smart-052ccff6-789f-45e9-87f2-12af9f7ee576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246061503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3246061503
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.721836543
Short name T86
Test name
Test status
Simulation time 51939768 ps
CPU time 0.85 seconds
Started Aug 01 06:25:54 PM PDT 24
Finished Aug 01 06:25:55 PM PDT 24
Peak memory 195292 kb
Host smart-901edc5d-db5d-4440-8681-7004b8a6370c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721836543 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.721836543
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2817710679
Short name T102
Test name
Test status
Simulation time 20717644 ps
CPU time 0.7 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:17 PM PDT 24
Peak memory 195136 kb
Host smart-60715171-51a2-41e7-99f1-8a9982766a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817710679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2817710679
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.294572278
Short name T733
Test name
Test status
Simulation time 28732427 ps
CPU time 0.61 seconds
Started Aug 01 06:25:56 PM PDT 24
Finished Aug 01 06:25:57 PM PDT 24
Peak memory 195000 kb
Host smart-50e33381-53a9-452a-8363-7e84191f0ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294572278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.294572278
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3245917145
Short name T644
Test name
Test status
Simulation time 41204963 ps
CPU time 0.88 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:14 PM PDT 24
Peak memory 195116 kb
Host smart-902fdd9c-cb1f-4222-926a-aef83a4b32c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245917145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3245917145
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.4277627954
Short name T20
Test name
Test status
Simulation time 41217871 ps
CPU time 1.86 seconds
Started Aug 01 06:26:03 PM PDT 24
Finished Aug 01 06:26:05 PM PDT 24
Peak memory 196340 kb
Host smart-e6f3db86-5088-46e6-aca2-58e4f97f0212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277627954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.4277627954
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2525378935
Short name T667
Test name
Test status
Simulation time 98426997 ps
CPU time 1.08 seconds
Started Aug 01 06:25:55 PM PDT 24
Finished Aug 01 06:25:57 PM PDT 24
Peak memory 200472 kb
Host smart-7396a4f3-7541-4625-a514-c0f209fb79cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525378935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2525378935
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2006754494
Short name T681
Test name
Test status
Simulation time 76636632 ps
CPU time 0.95 seconds
Started Aug 01 06:26:08 PM PDT 24
Finished Aug 01 06:26:09 PM PDT 24
Peak memory 195244 kb
Host smart-be57165b-f08b-409c-91be-f33a78316605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006754494 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.2006754494
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2457632702
Short name T717
Test name
Test status
Simulation time 62374140 ps
CPU time 0.68 seconds
Started Aug 01 06:26:05 PM PDT 24
Finished Aug 01 06:26:06 PM PDT 24
Peak memory 198428 kb
Host smart-a9576e36-1f52-4706-a6c3-11e9c0c9040d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457632702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2457632702
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3375139187
Short name T186
Test name
Test status
Simulation time 59779688 ps
CPU time 0.57 seconds
Started Aug 01 06:25:54 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 195044 kb
Host smart-ffd89a37-c897-45c9-bcd4-c29456def458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375139187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3375139187
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4210503313
Short name T735
Test name
Test status
Simulation time 37618541 ps
CPU time 0.91 seconds
Started Aug 01 06:25:58 PM PDT 24
Finished Aug 01 06:25:59 PM PDT 24
Peak memory 198416 kb
Host smart-409c09a5-1126-4292-af09-f88f9a51e94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210503313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.4210503313
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.261410492
Short name T672
Test name
Test status
Simulation time 44504127 ps
CPU time 1.2 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:05 PM PDT 24
Peak memory 197264 kb
Host smart-3501e5b4-e8ee-403f-96b8-a2957ccdb886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261410492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.261410492
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1026854642
Short name T56
Test name
Test status
Simulation time 94395586 ps
CPU time 1.06 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 200176 kb
Host smart-b7787a2c-f70b-4491-a907-fee8d8cc3e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026854642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.1026854642
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2259320062
Short name T693
Test name
Test status
Simulation time 121560087 ps
CPU time 0.96 seconds
Started Aug 01 06:26:05 PM PDT 24
Finished Aug 01 06:26:06 PM PDT 24
Peak memory 196192 kb
Host smart-5c52f083-a1a4-49c9-a8de-144a07df3620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259320062 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2259320062
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2206555116
Short name T69
Test name
Test status
Simulation time 57885270 ps
CPU time 0.63 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:13 PM PDT 24
Peak memory 195140 kb
Host smart-af197d88-8626-401b-a9cf-f7a97aa81ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206555116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2206555116
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.720270909
Short name T670
Test name
Test status
Simulation time 46618800 ps
CPU time 0.62 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195104 kb
Host smart-0ee2591f-a3bd-4680-ae9d-33e722ce0f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720270909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.720270909
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.66888234
Short name T114
Test name
Test status
Simulation time 122777254 ps
CPU time 0.9 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:07 PM PDT 24
Peak memory 195192 kb
Host smart-5a0e5aa4-171f-4b16-a164-19ec8379a7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66888234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sam
e_csr_outstanding.66888234
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1971674856
Short name T656
Test name
Test status
Simulation time 283117416 ps
CPU time 2.06 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:13 PM PDT 24
Peak memory 196644 kb
Host smart-e49977c1-88c0-4b43-ac4b-199c5e63736e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971674856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1971674856
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.899865605
Short name T725
Test name
Test status
Simulation time 265844667 ps
CPU time 1.69 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 200564 kb
Host smart-c552e995-6c13-46e4-b72f-dfbca9ca14ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899865605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.899865605
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3107525004
Short name T668
Test name
Test status
Simulation time 58348900 ps
CPU time 0.73 seconds
Started Aug 01 06:25:56 PM PDT 24
Finished Aug 01 06:25:57 PM PDT 24
Peak memory 195184 kb
Host smart-6bbe5634-984f-47e0-960a-451b03b2d3a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107525004 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3107525004
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2405997539
Short name T703
Test name
Test status
Simulation time 20909958 ps
CPU time 0.66 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:16 PM PDT 24
Peak memory 195116 kb
Host smart-ace85f20-b4a6-4226-935a-169baf18b82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405997539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2405997539
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1067726714
Short name T640
Test name
Test status
Simulation time 23574572 ps
CPU time 0.62 seconds
Started Aug 01 06:26:03 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 195084 kb
Host smart-1be5fff2-aaa7-47b6-bc31-bc6b7579666e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067726714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1067726714
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.276149253
Short name T110
Test name
Test status
Simulation time 20626188 ps
CPU time 0.83 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 195176 kb
Host smart-1d41ac8e-c5df-49a5-b439-02f2baa82190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276149253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sa
me_csr_outstanding.276149253
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3838114072
Short name T696
Test name
Test status
Simulation time 242644761 ps
CPU time 2.54 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 197476 kb
Host smart-8d77f21b-3afe-4b7e-abf4-99f0c1c8b58b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838114072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3838114072
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.397159895
Short name T695
Test name
Test status
Simulation time 125289574 ps
CPU time 1.15 seconds
Started Aug 01 06:26:00 PM PDT 24
Finished Aug 01 06:26:01 PM PDT 24
Peak memory 200500 kb
Host smart-4b5bb0ad-3238-4925-a6e4-4f788d82f5de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397159895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err
.397159895
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3400307443
Short name T107
Test name
Test status
Simulation time 66535962 ps
CPU time 0.93 seconds
Started Aug 01 06:25:37 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 194980 kb
Host smart-bfbac82b-1cbd-4671-8722-0e9ae101c7be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400307443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
400307443
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4020157930
Short name T698
Test name
Test status
Simulation time 564932112 ps
CPU time 3.46 seconds
Started Aug 01 06:25:33 PM PDT 24
Finished Aug 01 06:25:37 PM PDT 24
Peak memory 195248 kb
Host smart-2bc971aa-4d6b-4360-9e7c-d511b2e7d71d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020157930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.4
020157930
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1862196118
Short name T108
Test name
Test status
Simulation time 30917794 ps
CPU time 0.67 seconds
Started Aug 01 06:25:42 PM PDT 24
Finished Aug 01 06:25:43 PM PDT 24
Peak memory 195128 kb
Host smart-f3a91491-932e-46cb-90d4-1f70b1ea0d88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862196118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
862196118
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1818593192
Short name T671
Test name
Test status
Simulation time 328620141 ps
CPU time 1.13 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 196400 kb
Host smart-3548dddb-95fc-4dc5-853e-6f85b15c115b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818593192 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1818593192
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.447806079
Short name T97
Test name
Test status
Simulation time 27033319 ps
CPU time 0.66 seconds
Started Aug 01 06:25:39 PM PDT 24
Finished Aug 01 06:25:39 PM PDT 24
Peak memory 197264 kb
Host smart-50f1235f-a6c2-4031-b52f-b44774ced25d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447806079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.447806079
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2198298964
Short name T680
Test name
Test status
Simulation time 127217364 ps
CPU time 0.58 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 195040 kb
Host smart-202ab6d3-6c1d-4a41-8974-b8c31a0eac05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198298964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2198298964
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2563009953
Short name T653
Test name
Test status
Simulation time 47623772 ps
CPU time 0.7 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 195092 kb
Host smart-62875daa-9b98-448d-afb2-760e5545560b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563009953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2563009953
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2678319780
Short name T723
Test name
Test status
Simulation time 84091394 ps
CPU time 2.11 seconds
Started Aug 01 06:25:52 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 196396 kb
Host smart-86e868ba-883b-4859-b314-97657c2a7d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678319780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2678319780
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1211427090
Short name T70
Test name
Test status
Simulation time 390388289 ps
CPU time 1.41 seconds
Started Aug 01 06:25:49 PM PDT 24
Finished Aug 01 06:25:50 PM PDT 24
Peak memory 195380 kb
Host smart-6ee39d43-bcf1-44ef-b785-43c4beecea9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211427090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1211427090
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3956430978
Short name T660
Test name
Test status
Simulation time 46534329 ps
CPU time 0.64 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:09 PM PDT 24
Peak memory 195056 kb
Host smart-720b92bd-b04d-468f-a02f-12fd63b91a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956430978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3956430978
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3299971220
Short name T716
Test name
Test status
Simulation time 25887502 ps
CPU time 0.59 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:17 PM PDT 24
Peak memory 195032 kb
Host smart-2783def6-5247-4bfc-b712-f723beb48101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299971220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3299971220
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3303655666
Short name T710
Test name
Test status
Simulation time 19196173 ps
CPU time 0.68 seconds
Started Aug 01 06:26:08 PM PDT 24
Finished Aug 01 06:26:09 PM PDT 24
Peak memory 195036 kb
Host smart-724f207c-58f4-48bf-91eb-d1ac6056fe79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303655666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3303655666
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2613618659
Short name T187
Test name
Test status
Simulation time 20536604 ps
CPU time 0.6 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195032 kb
Host smart-7de37dd4-2290-4be5-ad31-bcf415676e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613618659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2613618659
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1884306219
Short name T627
Test name
Test status
Simulation time 18097298 ps
CPU time 0.62 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:06 PM PDT 24
Peak memory 195080 kb
Host smart-2234613b-8d6a-48f6-b955-3fda643f7c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884306219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1884306219
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1326872314
Short name T720
Test name
Test status
Simulation time 45322788 ps
CPU time 0.61 seconds
Started Aug 01 06:25:56 PM PDT 24
Finished Aug 01 06:25:57 PM PDT 24
Peak memory 195064 kb
Host smart-2da4a41f-74df-403d-9ae0-8609129856d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326872314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1326872314
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.444777048
Short name T673
Test name
Test status
Simulation time 30692523 ps
CPU time 0.64 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:14 PM PDT 24
Peak memory 195036 kb
Host smart-7c19a400-3bfb-41bf-831d-ef8bcdfd20a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444777048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.444777048
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.113463320
Short name T687
Test name
Test status
Simulation time 20047005 ps
CPU time 0.62 seconds
Started Aug 01 06:26:05 PM PDT 24
Finished Aug 01 06:26:06 PM PDT 24
Peak memory 195024 kb
Host smart-0c3af6ab-1bb8-4933-8a35-8fe6dc3f2c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113463320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.113463320
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.431758501
Short name T678
Test name
Test status
Simulation time 21882886 ps
CPU time 0.6 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:06 PM PDT 24
Peak memory 195060 kb
Host smart-740dd1d9-bff9-46a4-93d3-6cc71358a6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431758501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.431758501
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1477712556
Short name T662
Test name
Test status
Simulation time 159482638 ps
CPU time 1 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 198796 kb
Host smart-debcc04c-9863-41ce-b486-d99a2a272638
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477712556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1
477712556
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1486936189
Short name T699
Test name
Test status
Simulation time 220035167 ps
CPU time 3.17 seconds
Started Aug 01 06:25:49 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 195232 kb
Host smart-578a6b8f-1695-4e43-a232-0dad41872533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486936189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
486936189
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.4257629307
Short name T657
Test name
Test status
Simulation time 96601313 ps
CPU time 0.66 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 197632 kb
Host smart-f4687dcb-2f1e-48cc-a60a-4264a0f35706
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257629307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.4
257629307
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3424302309
Short name T705
Test name
Test status
Simulation time 170279620 ps
CPU time 0.99 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 195276 kb
Host smart-d97bc207-9dd4-42eb-91d8-471785dfaf3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424302309 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.3424302309
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1204944500
Short name T61
Test name
Test status
Simulation time 25656960 ps
CPU time 0.61 seconds
Started Aug 01 06:25:40 PM PDT 24
Finished Aug 01 06:25:41 PM PDT 24
Peak memory 197264 kb
Host smart-69278f18-367e-48c9-8d7e-42d4e64cd324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204944500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1204944500
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.734976563
Short name T675
Test name
Test status
Simulation time 38240577 ps
CPU time 0.6 seconds
Started Aug 01 06:25:54 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 195024 kb
Host smart-59135741-3b93-4808-9e69-cd19d27987f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734976563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.734976563
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.127762658
Short name T112
Test name
Test status
Simulation time 68883786 ps
CPU time 0.87 seconds
Started Aug 01 06:25:47 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 199972 kb
Host smart-952ef30b-96b2-4e56-a306-61b8f8ba646e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127762658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.127762658
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4226355442
Short name T64
Test name
Test status
Simulation time 90519314 ps
CPU time 1.3 seconds
Started Aug 01 06:25:33 PM PDT 24
Finished Aug 01 06:25:35 PM PDT 24
Peak memory 195540 kb
Host smart-a566861d-29e3-4eed-b7b4-5c0a7c662ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226355442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.4226355442
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3934000312
Short name T661
Test name
Test status
Simulation time 226236983 ps
CPU time 1.69 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 200652 kb
Host smart-d10a5129-8105-4c48-95a7-501b90781ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934000312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3934000312
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.325279997
Short name T686
Test name
Test status
Simulation time 151515926 ps
CPU time 0.61 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 195084 kb
Host smart-d9c4cc26-ddad-4916-9415-acf849d158f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325279997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.325279997
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2537664632
Short name T689
Test name
Test status
Simulation time 19927038 ps
CPU time 0.64 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 195084 kb
Host smart-ccd09e3e-efa1-44fb-874e-567dc0aae8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537664632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2537664632
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3861579237
Short name T633
Test name
Test status
Simulation time 29360535 ps
CPU time 0.65 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:15 PM PDT 24
Peak memory 195100 kb
Host smart-fe430fca-076b-4219-9019-9f4b71d0a969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861579237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3861579237
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4016861644
Short name T708
Test name
Test status
Simulation time 21531262 ps
CPU time 0.61 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195088 kb
Host smart-360dc0cb-aeb2-4650-a346-088adb1c2814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016861644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4016861644
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2030285459
Short name T665
Test name
Test status
Simulation time 71563454 ps
CPU time 0.59 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:05 PM PDT 24
Peak memory 195076 kb
Host smart-b89d2377-4768-4047-9e29-ac01497a5032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030285459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2030285459
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3711149957
Short name T629
Test name
Test status
Simulation time 119169139 ps
CPU time 0.58 seconds
Started Aug 01 06:26:02 PM PDT 24
Finished Aug 01 06:26:02 PM PDT 24
Peak memory 195084 kb
Host smart-453c6931-4929-4beb-9ee7-522611ed29df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711149957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3711149957
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.415044925
Short name T704
Test name
Test status
Simulation time 18883875 ps
CPU time 0.58 seconds
Started Aug 01 06:25:54 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 195076 kb
Host smart-9d9cadea-5e41-4837-8625-8e19865803be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415044925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.415044925
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3487608750
Short name T634
Test name
Test status
Simulation time 17352123 ps
CPU time 0.61 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:12 PM PDT 24
Peak memory 195092 kb
Host smart-692b7d36-960d-4fca-aa25-f010c3861149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487608750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3487608750
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2091732758
Short name T722
Test name
Test status
Simulation time 27836599 ps
CPU time 0.59 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:09 PM PDT 24
Peak memory 195052 kb
Host smart-895bbcc1-60c3-4bff-b7b4-2c2c8a95682b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091732758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2091732758
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3173979452
Short name T655
Test name
Test status
Simulation time 29674193 ps
CPU time 0.59 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 195056 kb
Host smart-51d87721-6659-47bd-8a03-9166403bbf22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173979452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3173979452
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.275545066
Short name T688
Test name
Test status
Simulation time 38737889 ps
CPU time 0.96 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 200056 kb
Host smart-75208494-b7f5-47d1-b6da-e49aef091d67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275545066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.275545066
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1975352459
Short name T117
Test name
Test status
Simulation time 298753108 ps
CPU time 3.36 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 195304 kb
Host smart-d9e8cabf-1d01-4ef6-bd26-1f2bf97929d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975352459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
975352459
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.585553445
Short name T98
Test name
Test status
Simulation time 188812562 ps
CPU time 0.66 seconds
Started Aug 01 06:25:58 PM PDT 24
Finished Aug 01 06:25:59 PM PDT 24
Peak memory 196348 kb
Host smart-025f1881-de6e-45c5-b37b-1ffc12f2e116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585553445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.585553445
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1536427025
Short name T729
Test name
Test status
Simulation time 118152213 ps
CPU time 0.91 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 195368 kb
Host smart-2d7799e1-ee26-449e-8978-40255034ff4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536427025 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1536427025
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2461342012
Short name T99
Test name
Test status
Simulation time 22592511 ps
CPU time 0.61 seconds
Started Aug 01 06:26:05 PM PDT 24
Finished Aug 01 06:26:05 PM PDT 24
Peak memory 195084 kb
Host smart-83982bad-8af6-4635-8db4-9fede90eaa91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461342012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2461342012
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.290418317
Short name T185
Test name
Test status
Simulation time 47439816 ps
CPU time 0.62 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 195108 kb
Host smart-bac1ec51-5bc4-4af0-a06c-f6926b8eb234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290418317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.290418317
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3499613511
Short name T113
Test name
Test status
Simulation time 21835976 ps
CPU time 0.74 seconds
Started Aug 01 06:25:50 PM PDT 24
Finished Aug 01 06:25:51 PM PDT 24
Peak memory 197380 kb
Host smart-c04806ad-9346-415f-bb38-81ac121a052a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499613511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3499613511
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.738902216
Short name T65
Test name
Test status
Simulation time 201679914 ps
CPU time 2.16 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 200756 kb
Host smart-32984727-7a5f-4d30-be7f-2ac12559e529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738902216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.738902216
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3501941407
Short name T641
Test name
Test status
Simulation time 22212040 ps
CPU time 0.61 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:07 PM PDT 24
Peak memory 195032 kb
Host smart-aa843059-5ebd-46bb-ad32-cda1a19824f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501941407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3501941407
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1690447463
Short name T630
Test name
Test status
Simulation time 17705713 ps
CPU time 0.61 seconds
Started Aug 01 06:26:08 PM PDT 24
Finished Aug 01 06:26:08 PM PDT 24
Peak memory 195084 kb
Host smart-7de9bfd7-389a-482a-a21e-d8f17bcd296e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690447463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1690447463
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2148120238
Short name T736
Test name
Test status
Simulation time 19819566 ps
CPU time 0.61 seconds
Started Aug 01 06:25:56 PM PDT 24
Finished Aug 01 06:25:56 PM PDT 24
Peak memory 195032 kb
Host smart-833dd208-a111-4c04-8a21-56c7f36107fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148120238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.2148120238
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2591938537
Short name T639
Test name
Test status
Simulation time 52886436 ps
CPU time 0.59 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:22 PM PDT 24
Peak memory 195032 kb
Host smart-417b0280-2783-4aa6-9411-e6b24710b575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591938537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2591938537
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3175179635
Short name T648
Test name
Test status
Simulation time 36896610 ps
CPU time 0.64 seconds
Started Aug 01 06:26:03 PM PDT 24
Finished Aug 01 06:26:03 PM PDT 24
Peak memory 195076 kb
Host smart-1718c619-b42b-460a-afc1-3c89bb87da28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175179635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3175179635
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2764988001
Short name T682
Test name
Test status
Simulation time 35152235 ps
CPU time 0.62 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 195024 kb
Host smart-1d1eb515-0c0d-4a5a-9c34-bbaf075bfecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764988001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.2764988001
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1331997808
Short name T647
Test name
Test status
Simulation time 31699976 ps
CPU time 0.63 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:14 PM PDT 24
Peak memory 195040 kb
Host smart-1ed90e74-146c-4c41-80a2-a31d297b5ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331997808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1331997808
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.414003911
Short name T718
Test name
Test status
Simulation time 29712030 ps
CPU time 0.6 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:08 PM PDT 24
Peak memory 195092 kb
Host smart-de06c189-73fb-44b0-9683-db8622f1dde8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414003911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.414003911
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3229112315
Short name T189
Test name
Test status
Simulation time 43005486 ps
CPU time 0.61 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:17 PM PDT 24
Peak memory 195040 kb
Host smart-f97cc85a-f3b3-4621-a758-8c0644752884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229112315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3229112315
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2019559880
Short name T724
Test name
Test status
Simulation time 15969201 ps
CPU time 0.63 seconds
Started Aug 01 06:26:14 PM PDT 24
Finished Aug 01 06:26:15 PM PDT 24
Peak memory 195052 kb
Host smart-f446d4c0-f4fb-42bb-be2f-b3fa148f997e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019559880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2019559880
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1640079499
Short name T700
Test name
Test status
Simulation time 66980122 ps
CPU time 0.93 seconds
Started Aug 01 06:25:44 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 195284 kb
Host smart-deaeaf28-742b-4a37-9456-36bd40ea23de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640079499 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1640079499
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.82355997
Short name T666
Test name
Test status
Simulation time 24771059 ps
CPU time 0.66 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:05 PM PDT 24
Peak memory 195152 kb
Host smart-d1999111-74c5-46d8-940f-175e5887b783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82355997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.82355997
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3544877939
Short name T692
Test name
Test status
Simulation time 21896177 ps
CPU time 0.6 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 195080 kb
Host smart-bcee8934-b95e-4b5b-9d93-2100bdc5b829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544877939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3544877939
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.4282300486
Short name T646
Test name
Test status
Simulation time 129939888 ps
CPU time 0.87 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 198324 kb
Host smart-a2e71a02-f0d3-43f1-8dd0-599ced294477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282300486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.4282300486
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3945155661
Short name T649
Test name
Test status
Simulation time 68353478 ps
CPU time 1.48 seconds
Started Aug 01 06:25:50 PM PDT 24
Finished Aug 01 06:25:51 PM PDT 24
Peak memory 196460 kb
Host smart-d50e564a-ba49-4347-975a-3b9b47204b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945155661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3945155661
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1111802093
Short name T140
Test name
Test status
Simulation time 201537010 ps
CPU time 1.61 seconds
Started Aug 01 06:25:39 PM PDT 24
Finished Aug 01 06:25:40 PM PDT 24
Peak memory 200728 kb
Host smart-de3d4706-1fab-4c98-b2d4-1ff9b5ed0b60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111802093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.1111802093
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3338381214
Short name T72
Test name
Test status
Simulation time 86608798 ps
CPU time 0.77 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 200592 kb
Host smart-a9685705-5797-4b3d-8ea4-2356fb5373a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338381214 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.3338381214
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3896701455
Short name T684
Test name
Test status
Simulation time 31017111 ps
CPU time 0.67 seconds
Started Aug 01 06:25:57 PM PDT 24
Finished Aug 01 06:25:58 PM PDT 24
Peak memory 197260 kb
Host smart-35160517-03fe-49fd-ac6a-7fd0d3e5f801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896701455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3896701455
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3733363021
Short name T726
Test name
Test status
Simulation time 102096956 ps
CPU time 0.59 seconds
Started Aug 01 06:25:55 PM PDT 24
Finished Aug 01 06:25:56 PM PDT 24
Peak memory 195076 kb
Host smart-d6ce6945-0897-416d-9f3c-97248044ff2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733363021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3733363021
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1917030568
Short name T709
Test name
Test status
Simulation time 126614259 ps
CPU time 0.83 seconds
Started Aug 01 06:25:48 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 195156 kb
Host smart-01369173-7da0-443f-bebf-258530c2f4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917030568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1917030568
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.4097857922
Short name T53
Test name
Test status
Simulation time 227887329 ps
CPU time 1.48 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:07 PM PDT 24
Peak memory 196436 kb
Host smart-6bc62ee0-12f4-4447-9b93-55ddd48ff938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097857922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.4097857922
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1074011373
Short name T654
Test name
Test status
Simulation time 96523904 ps
CPU time 1.14 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 200440 kb
Host smart-e28f370f-f061-495a-ac6e-a60e35d49125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074011373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1074011373
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1488013361
Short name T691
Test name
Test status
Simulation time 323121673 ps
CPU time 0.92 seconds
Started Aug 01 06:26:03 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 195264 kb
Host smart-c67e2680-8de6-435f-b5eb-f7fed88c470f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488013361 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1488013361
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3564039939
Short name T669
Test name
Test status
Simulation time 34146943 ps
CPU time 0.67 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 197300 kb
Host smart-cb67dcd8-7124-4fd8-a690-b5b8783d2ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564039939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3564039939
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3459024263
Short name T67
Test name
Test status
Simulation time 46948660 ps
CPU time 0.6 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:44 PM PDT 24
Peak memory 195036 kb
Host smart-2c3badc7-c0e9-4cea-987c-1e7d0ff97390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459024263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3459024263
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.648363367
Short name T60
Test name
Test status
Simulation time 24578093 ps
CPU time 0.91 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195068 kb
Host smart-fea0e2f2-a035-4e99-abf7-918937b3fa85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648363367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.648363367
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.4264046210
Short name T730
Test name
Test status
Simulation time 37047203 ps
CPU time 1.66 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 197648 kb
Host smart-2e83cc72-3674-43a0-8997-d76e4e525625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264046210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.4264046210
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1206343444
Short name T642
Test name
Test status
Simulation time 275469585 ps
CPU time 1.6 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 200436 kb
Host smart-9ae2995a-8aef-4054-b00d-8fb9d1c34a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206343444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1206343444
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4110955726
Short name T651
Test name
Test status
Simulation time 36622089 ps
CPU time 0.8 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195284 kb
Host smart-a7229a9f-222e-4dbb-a3d7-ca91ba60d96a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110955726 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.4110955726
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3643206512
Short name T105
Test name
Test status
Simulation time 23790083 ps
CPU time 0.66 seconds
Started Aug 01 06:26:04 PM PDT 24
Finished Aug 01 06:26:04 PM PDT 24
Peak memory 197304 kb
Host smart-d9947c0a-aecb-4be6-9594-3ba0d54b1238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643206512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3643206512
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3334392207
Short name T66
Test name
Test status
Simulation time 40027408 ps
CPU time 0.65 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 195036 kb
Host smart-cbdb883c-510b-43c5-8436-d7495177f0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334392207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3334392207
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3189841521
Short name T719
Test name
Test status
Simulation time 24260658 ps
CPU time 0.76 seconds
Started Aug 01 06:25:44 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 198428 kb
Host smart-2b72f6ff-c6c0-4e27-ba12-0d4a4b7249d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189841521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.3189841521
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.649304428
Short name T713
Test name
Test status
Simulation time 473544202 ps
CPU time 1.3 seconds
Started Aug 01 06:26:02 PM PDT 24
Finished Aug 01 06:26:03 PM PDT 24
Peak memory 196396 kb
Host smart-390b1c46-1fd7-4c03-a248-0c996d430e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649304428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.649304428
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2915689005
Short name T632
Test name
Test status
Simulation time 327324747 ps
CPU time 1.49 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 200408 kb
Host smart-b8270e55-b81f-4d9c-aa31-55187b2df16b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915689005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2915689005
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2515119762
Short name T74
Test name
Test status
Simulation time 293742067 ps
CPU time 1.44 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:53 PM PDT 24
Peak memory 200744 kb
Host smart-54b1078a-6478-4fe2-95b6-5c43180fe54f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515119762 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2515119762
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2531696187
Short name T109
Test name
Test status
Simulation time 28478795 ps
CPU time 0.68 seconds
Started Aug 01 06:25:45 PM PDT 24
Finished Aug 01 06:25:46 PM PDT 24
Peak memory 197288 kb
Host smart-12ec3806-61e3-4c21-9f90-e3413578a217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531696187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2531696187
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3150644560
Short name T188
Test name
Test status
Simulation time 59966470 ps
CPU time 0.64 seconds
Started Aug 01 06:25:46 PM PDT 24
Finished Aug 01 06:25:47 PM PDT 24
Peak memory 195060 kb
Host smart-e436fadf-a661-43bd-b46d-c348699bfa22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150644560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3150644560
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1647923463
Short name T714
Test name
Test status
Simulation time 66196717 ps
CPU time 0.76 seconds
Started Aug 01 06:25:51 PM PDT 24
Finished Aug 01 06:25:52 PM PDT 24
Peak memory 197368 kb
Host smart-80f50df7-8ab6-4853-ac42-2fee70dea34f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647923463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.1647923463
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3882298862
Short name T679
Test name
Test status
Simulation time 67054477 ps
CPU time 1.39 seconds
Started Aug 01 06:25:53 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 196392 kb
Host smart-3ec5fba9-8986-4d19-aac9-f591e64e237d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882298862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3882298862
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3890403047
Short name T71
Test name
Test status
Simulation time 112408517 ps
CPU time 1.18 seconds
Started Aug 01 06:25:43 PM PDT 24
Finished Aug 01 06:25:45 PM PDT 24
Peak memory 200420 kb
Host smart-1feea772-84ee-4afc-a3fc-c855eed043e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890403047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.3890403047
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3880243277
Short name T616
Test name
Test status
Simulation time 31754372 ps
CPU time 1.07 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 200988 kb
Host smart-7c2fae23-9f8f-4c19-98c1-271e7e75a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880243277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3880243277
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3365899130
Short name T612
Test name
Test status
Simulation time 29809646 ps
CPU time 0.65 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 198056 kb
Host smart-c384ec9b-512a-4247-ba8a-5a75b5e1e982
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365899130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3365899130
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3151824489
Short name T363
Test name
Test status
Simulation time 213584340 ps
CPU time 0.94 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 198108 kb
Host smart-53267506-ba7e-44c3-a551-3bbd701ec146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151824489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3151824489
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3625705462
Short name T378
Test name
Test status
Simulation time 28980657 ps
CPU time 0.59 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 198100 kb
Host smart-2431c57e-2567-4248-b97c-1988b67abbb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625705462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3625705462
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3412779482
Short name T208
Test name
Test status
Simulation time 97153016 ps
CPU time 0.65 seconds
Started Aug 01 06:29:19 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 198384 kb
Host smart-f754b8df-4d07-45e2-811f-d157633094e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412779482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3412779482
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.4182813169
Short name T303
Test name
Test status
Simulation time 110250257 ps
CPU time 0.9 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:15 PM PDT 24
Peak memory 209500 kb
Host smart-19c65218-d758-4d71-a509-e66566eb7c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182813169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.4182813169
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1584410122
Short name T228
Test name
Test status
Simulation time 58687099 ps
CPU time 0.82 seconds
Started Aug 01 06:29:39 PM PDT 24
Finished Aug 01 06:29:40 PM PDT 24
Peak memory 198184 kb
Host smart-852a283d-09fb-48cb-be96-53c65c81ec18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584410122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1584410122
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.3651286701
Short name T244
Test name
Test status
Simulation time 53036043 ps
CPU time 0.67 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 198560 kb
Host smart-b6a8802b-c806-404e-9366-6d7ddd68ee12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651286701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3651286701
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.2952501890
Short name T92
Test name
Test status
Simulation time 35839720 ps
CPU time 0.87 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 200188 kb
Host smart-192ffc3b-6c4c-46a0-9d08-12f9a84fa048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952501890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.2952501890
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2985874707
Short name T474
Test name
Test status
Simulation time 64895885 ps
CPU time 0.69 seconds
Started Aug 01 06:29:35 PM PDT 24
Finished Aug 01 06:29:36 PM PDT 24
Peak memory 199116 kb
Host smart-311e6d01-980b-412e-81df-ae9b670aa076
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985874707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2985874707
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.396498339
Short name T254
Test name
Test status
Simulation time 33141434 ps
CPU time 0.6 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 198048 kb
Host smart-6ac28355-c91f-4fa7-9921-03a3ce7f492b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396498339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.396498339
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1985123054
Short name T262
Test name
Test status
Simulation time 510545183 ps
CPU time 1 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 198448 kb
Host smart-e364c4b3-54a1-42a6-ae24-f93e53236214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985123054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1985123054
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1053565109
Short name T561
Test name
Test status
Simulation time 52845224 ps
CPU time 0.64 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 198064 kb
Host smart-8dfeec03-b5d6-4754-9580-7139f6e17aa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053565109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1053565109
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.108620030
Short name T218
Test name
Test status
Simulation time 152271649 ps
CPU time 0.59 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 198152 kb
Host smart-e7f68371-e04e-4586-821b-6e0ba3464000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108620030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.108620030
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.294232406
Short name T425
Test name
Test status
Simulation time 58382673 ps
CPU time 0.89 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 199204 kb
Host smart-6296a585-edd5-4d14-8429-5a6871d45ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294232406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.294232406
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.3168950243
Short name T440
Test name
Test status
Simulation time 124955142 ps
CPU time 0.9 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:34 PM PDT 24
Peak memory 209536 kb
Host smart-3d17afd9-c4c1-48f6-a9de-57394ecc8012
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168950243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.3168950243
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2430610550
Short name T18
Test name
Test status
Simulation time 658748038 ps
CPU time 1.71 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 217972 kb
Host smart-5112936d-1fbc-438a-a414-f10bda619e8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430610550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2430610550
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2073943946
Short name T221
Test name
Test status
Simulation time 54188478 ps
CPU time 0.76 seconds
Started Aug 01 06:29:30 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 198072 kb
Host smart-b77a9014-e149-40f2-b8e0-3e1119296ec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073943946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2073943946
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2647755766
Short name T351
Test name
Test status
Simulation time 93065424 ps
CPU time 0.64 seconds
Started Aug 01 06:29:34 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 198500 kb
Host smart-a2230332-fb3e-4c0a-93b3-e023f22c95aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647755766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2647755766
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3800519441
Short name T4
Test name
Test status
Simulation time 47182543 ps
CPU time 0.95 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 200320 kb
Host smart-48afd3ac-fd60-4eaa-b58a-a1ea9e7ca938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800519441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3800519441
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.672571231
Short name T286
Test name
Test status
Simulation time 31015834 ps
CPU time 0.68 seconds
Started Aug 01 06:30:01 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198040 kb
Host smart-ade4a8a3-ad63-4826-b351-242a5a2b87f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672571231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_
malfunc.672571231
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.967088668
Short name T123
Test name
Test status
Simulation time 311107796 ps
CPU time 0.99 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:03 PM PDT 24
Peak memory 198420 kb
Host smart-6b88a45b-1134-4451-9ee0-5259e535799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967088668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.967088668
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2234719376
Short name T209
Test name
Test status
Simulation time 62417182 ps
CPU time 0.7 seconds
Started Aug 01 06:29:58 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 198064 kb
Host smart-36ca4d47-e79e-4476-bf8d-255f26b32af6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234719376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2234719376
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.327860822
Short name T275
Test name
Test status
Simulation time 68552256 ps
CPU time 0.64 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198412 kb
Host smart-3052638e-ba72-4fe9-a03b-591aa2ddd22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327860822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.327860822
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3931985213
Short name T156
Test name
Test status
Simulation time 85960295 ps
CPU time 0.66 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 201372 kb
Host smart-01988e87-1dbb-4fd6-b407-268dadeb4afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931985213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3931985213
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.1435067420
Short name T329
Test name
Test status
Simulation time 62427219 ps
CPU time 0.83 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:03 PM PDT 24
Peak memory 199044 kb
Host smart-54ae4ae2-ae0b-4e27-9262-87e099be937a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435067420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1435067420
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2745565322
Short name T610
Test name
Test status
Simulation time 97678075 ps
CPU time 1.1 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 209500 kb
Host smart-46296da3-a165-4548-90f1-f9434a7e5008
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745565322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2745565322
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2204734644
Short name T591
Test name
Test status
Simulation time 149157000 ps
CPU time 0.82 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 199208 kb
Host smart-b5453599-f624-4194-b033-1f6de73440d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204734644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2204734644
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2151544843
Short name T252
Test name
Test status
Simulation time 48669927 ps
CPU time 0.66 seconds
Started Aug 01 06:29:58 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 199332 kb
Host smart-d36b1623-fd22-403c-aade-0e9948d11275
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151544843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2151544843
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.1612130873
Short name T348
Test name
Test status
Simulation time 51167542 ps
CPU time 0.83 seconds
Started Aug 01 06:30:01 PM PDT 24
Finished Aug 01 06:30:02 PM PDT 24
Peak memory 198908 kb
Host smart-34d925ef-3ff3-4b73-b56f-1a67567568d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612130873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1612130873
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1154497245
Short name T288
Test name
Test status
Simulation time 94190522 ps
CPU time 0.68 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 199132 kb
Host smart-46d8682d-f894-472c-aac3-559f93c0a667
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154497245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.1154497245
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1012500529
Short name T274
Test name
Test status
Simulation time 38913903 ps
CPU time 0.58 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 197368 kb
Host smart-369ca494-5510-4537-9def-64e91007125b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012500529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1012500529
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2872298069
Short name T569
Test name
Test status
Simulation time 124573250 ps
CPU time 0.67 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:02 PM PDT 24
Peak memory 197360 kb
Host smart-4141bb5d-047d-4bec-927e-8cee2badafa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872298069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2872298069
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.2083167448
Short name T204
Test name
Test status
Simulation time 32486487 ps
CPU time 0.63 seconds
Started Aug 01 06:29:57 PM PDT 24
Finished Aug 01 06:29:58 PM PDT 24
Peak memory 198396 kb
Host smart-7e3bd5fe-e8bc-4680-bc4b-07136c5739fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083167448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2083167448
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.372357139
Short name T601
Test name
Test status
Simulation time 57590223 ps
CPU time 0.68 seconds
Started Aug 01 06:30:01 PM PDT 24
Finished Aug 01 06:30:02 PM PDT 24
Peak memory 198356 kb
Host smart-42d663fa-0f8a-4342-bec4-5d24b1c36d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372357139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.372357139
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3209249854
Short name T574
Test name
Test status
Simulation time 100418212 ps
CPU time 1.13 seconds
Started Aug 01 06:30:15 PM PDT 24
Finished Aug 01 06:30:17 PM PDT 24
Peak memory 209480 kb
Host smart-860b3ef4-5f65-4244-a89f-d0e345f30c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209249854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3209249854
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.812541969
Short name T479
Test name
Test status
Simulation time 165177225 ps
CPU time 0.89 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 199284 kb
Host smart-a7679294-3be4-41bd-aa60-6c08dc58c2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812541969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.812541969
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.4161224723
Short name T313
Test name
Test status
Simulation time 34888308 ps
CPU time 0.74 seconds
Started Aug 01 06:30:01 PM PDT 24
Finished Aug 01 06:30:02 PM PDT 24
Peak memory 198536 kb
Host smart-8992c6b0-2568-4603-9e37-74e4dfb948ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161224723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.4161224723
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.676864201
Short name T466
Test name
Test status
Simulation time 57565439 ps
CPU time 0.71 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198668 kb
Host smart-ee41c41b-e644-4783-b74b-295931423b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676864201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.676864201
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1511606601
Short name T621
Test name
Test status
Simulation time 29327857 ps
CPU time 0.64 seconds
Started Aug 01 06:30:16 PM PDT 24
Finished Aug 01 06:30:17 PM PDT 24
Peak memory 198060 kb
Host smart-0dd37dfb-3596-46de-ab81-2925637dd0df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511606601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1511606601
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.913489675
Short name T347
Test name
Test status
Simulation time 166922729 ps
CPU time 0.99 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198152 kb
Host smart-937c7663-7ec1-4173-83af-bbf972e308e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913489675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.913489675
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1482148628
Short name T292
Test name
Test status
Simulation time 87425722 ps
CPU time 0.6 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198040 kb
Host smart-e73b28ed-5972-40c2-a9d2-fd51e76f3029
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482148628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1482148628
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3950507457
Short name T205
Test name
Test status
Simulation time 28748515 ps
CPU time 0.64 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198072 kb
Host smart-2ce607a1-3ac4-419d-af78-36138d141b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950507457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3950507457
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2342648446
Short name T568
Test name
Test status
Simulation time 79443931 ps
CPU time 0.73 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 201316 kb
Host smart-a0c96bce-5fdb-412c-a255-140eb720da63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342648446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2342648446
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.3288522914
Short name T507
Test name
Test status
Simulation time 82599530 ps
CPU time 1.02 seconds
Started Aug 01 06:30:15 PM PDT 24
Finished Aug 01 06:30:17 PM PDT 24
Peak memory 199128 kb
Host smart-fcf46126-bc29-49bd-b5fb-ac20343cd1b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288522914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.3288522914
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.485972385
Short name T528
Test name
Test status
Simulation time 172879823 ps
CPU time 0.76 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 209432 kb
Host smart-c00f3ea8-0b70-41c6-b1b6-2767e3a7c0ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485972385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.485972385
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4073317748
Short name T617
Test name
Test status
Simulation time 342167841 ps
CPU time 0.84 seconds
Started Aug 01 06:30:15 PM PDT 24
Finished Aug 01 06:30:16 PM PDT 24
Peak memory 199240 kb
Host smart-fc031c51-891b-4712-a333-b56c60ddb948
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073317748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4073317748
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1494535873
Short name T80
Test name
Test status
Simulation time 33833511 ps
CPU time 0.67 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 198440 kb
Host smart-067466d9-a82a-420b-afe4-648be423e24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494535873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1494535873
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.1011578693
Short name T509
Test name
Test status
Simulation time 395377748 ps
CPU time 0.72 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198724 kb
Host smart-c8b59455-08b1-4f63-a6c1-902423561b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011578693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.1011578693
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2846824036
Short name T523
Test name
Test status
Simulation time 31579504 ps
CPU time 0.74 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 199184 kb
Host smart-9501710a-1e68-4f85-b677-94b755d077f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846824036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2846824036
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3794550269
Short name T134
Test name
Test status
Simulation time 56525615 ps
CPU time 0.81 seconds
Started Aug 01 06:30:20 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 199156 kb
Host smart-93cbb662-cab0-41e8-a465-ea454a8e8c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794550269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3794550269
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3882959355
Short name T449
Test name
Test status
Simulation time 29134810 ps
CPU time 0.65 seconds
Started Aug 01 06:30:15 PM PDT 24
Finished Aug 01 06:30:16 PM PDT 24
Peak memory 197544 kb
Host smart-892c521b-9d5d-46d0-a037-e8655778bc3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882959355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3882959355
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.1589208521
Short name T232
Test name
Test status
Simulation time 1006989946 ps
CPU time 0.98 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 198428 kb
Host smart-f80bd845-d692-4fc2-83f2-6f3a09808a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589208521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.1589208521
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.4044927698
Short name T603
Test name
Test status
Simulation time 43875955 ps
CPU time 0.63 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198024 kb
Host smart-00bb7119-51f1-4fa8-90a0-f74daaaf4f4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044927698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.4044927698
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.721389471
Short name T331
Test name
Test status
Simulation time 50116886 ps
CPU time 0.62 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198408 kb
Host smart-2e5d6bd3-9593-4733-b4e7-060bb31731d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721389471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.721389471
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3974952488
Short name T176
Test name
Test status
Simulation time 42969629 ps
CPU time 0.74 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 201348 kb
Host smart-c7f5e91f-71b8-4365-95c2-9059aaeb96d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974952488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3974952488
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.97350263
Short name T589
Test name
Test status
Simulation time 95686573 ps
CPU time 0.72 seconds
Started Aug 01 06:30:20 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 198372 kb
Host smart-f0844024-05ea-4de9-b0d3-536f4c1c3efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97350263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.97350263
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1591362863
Short name T550
Test name
Test status
Simulation time 160044656 ps
CPU time 0.79 seconds
Started Aug 01 06:30:21 PM PDT 24
Finished Aug 01 06:30:22 PM PDT 24
Peak memory 209504 kb
Host smart-c4f0991d-7159-4e22-a84b-65edbc4945ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591362863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1591362863
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3156083361
Short name T215
Test name
Test status
Simulation time 65820675 ps
CPU time 0.75 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 198200 kb
Host smart-f53a349c-e21e-4aa6-a3a1-f99b36a363ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156083361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3156083361
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1775573744
Short name T609
Test name
Test status
Simulation time 28971281 ps
CPU time 0.68 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198524 kb
Host smart-cfde2e77-aa25-4369-b6f4-1cdce30facef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775573744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1775573744
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.416880083
Short name T15
Test name
Test status
Simulation time 70130093 ps
CPU time 0.81 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 200172 kb
Host smart-51efdf79-8fc3-4c04-8778-bc2e044d0e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416880083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.416880083
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3249781325
Short name T585
Test name
Test status
Simulation time 104658528 ps
CPU time 0.67 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 199128 kb
Host smart-82963109-8936-48b2-b08b-a4397d10c59c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249781325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3249781325
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.982968327
Short name T35
Test name
Test status
Simulation time 40355004 ps
CPU time 0.59 seconds
Started Aug 01 06:30:20 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 197324 kb
Host smart-bb102857-92de-447c-96dc-b3f47ec9c0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982968327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_
malfunc.982968327
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.3987616335
Short name T246
Test name
Test status
Simulation time 161570741 ps
CPU time 0.99 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 198088 kb
Host smart-a107dadf-e59b-4bbb-9f98-87a9fb655088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987616335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3987616335
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1397462158
Short name T355
Test name
Test status
Simulation time 44376032 ps
CPU time 0.6 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198116 kb
Host smart-e6ab0947-d77c-4ed2-87cb-d6bd5a3ff0d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397462158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1397462158
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1435322457
Short name T451
Test name
Test status
Simulation time 95157134 ps
CPU time 0.62 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198100 kb
Host smart-90c1823a-9e03-49c3-81b6-dfe4389890ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435322457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1435322457
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.304428320
Short name T183
Test name
Test status
Simulation time 57174102 ps
CPU time 0.68 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 201336 kb
Host smart-05d97a01-5eba-481f-b8c0-4f1f13f1f814
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304428320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invali
d.304428320
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1869583476
Short name T223
Test name
Test status
Simulation time 43832519 ps
CPU time 0.68 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 199064 kb
Host smart-cde74444-9b69-4aef-91a0-d0dfc5dc0df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869583476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1869583476
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2157277111
Short name T504
Test name
Test status
Simulation time 115104224 ps
CPU time 0.81 seconds
Started Aug 01 06:30:18 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 201276 kb
Host smart-92587d84-cf09-4d47-8cea-2118ad49d2f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157277111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2157277111
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3002450526
Short name T270
Test name
Test status
Simulation time 128139523 ps
CPU time 0.73 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198064 kb
Host smart-7d15bdbb-7a43-4c8d-b706-4da418d1d14f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002450526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3002450526
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2375139774
Short name T396
Test name
Test status
Simulation time 29660633 ps
CPU time 0.65 seconds
Started Aug 01 06:30:17 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 198536 kb
Host smart-65a438d6-f381-4538-9e74-cc020b5adba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375139774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2375139774
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.2076294548
Short name T463
Test name
Test status
Simulation time 29623677 ps
CPU time 0.96 seconds
Started Aug 01 06:30:29 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 200792 kb
Host smart-60213541-a5c7-490c-a64c-e42f16df4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076294548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.2076294548
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2133680889
Short name T300
Test name
Test status
Simulation time 40242270 ps
CPU time 0.62 seconds
Started Aug 01 06:30:28 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 197980 kb
Host smart-e0cd702c-86fe-422e-ad0a-5c373e3ea5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133680889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2133680889
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2541967010
Short name T462
Test name
Test status
Simulation time 310925950 ps
CPU time 0.96 seconds
Started Aug 01 06:30:27 PM PDT 24
Finished Aug 01 06:30:28 PM PDT 24
Peak memory 198120 kb
Host smart-8d0e8518-78ef-468f-86ad-bc76e3971493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541967010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2541967010
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2650863968
Short name T611
Test name
Test status
Simulation time 78925907 ps
CPU time 0.64 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 196724 kb
Host smart-b3601cb4-c806-4727-99d0-0934b4598ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650863968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2650863968
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1486092412
Short name T514
Test name
Test status
Simulation time 36416056 ps
CPU time 0.66 seconds
Started Aug 01 06:30:25 PM PDT 24
Finished Aug 01 06:30:26 PM PDT 24
Peak memory 198132 kb
Host smart-72a4551a-7621-4c03-98ae-a086b9dcbd42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486092412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1486092412
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3889093777
Short name T298
Test name
Test status
Simulation time 47544887 ps
CPU time 0.68 seconds
Started Aug 01 06:30:27 PM PDT 24
Finished Aug 01 06:30:27 PM PDT 24
Peak memory 201380 kb
Host smart-e824bc32-6526-4a91-8bae-1dbf482f9099
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889093777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3889093777
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3914460932
Short name T226
Test name
Test status
Simulation time 244934256 ps
CPU time 0.72 seconds
Started Aug 01 06:30:19 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 198504 kb
Host smart-58e55a40-c832-43fd-a0da-002afeff40cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914460932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3914460932
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.117569278
Short name T302
Test name
Test status
Simulation time 130286035 ps
CPU time 0.82 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 209468 kb
Host smart-8c0eefac-9c2c-4b02-a6b9-79800fd677f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117569278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.117569278
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2766005425
Short name T43
Test name
Test status
Simulation time 49394115 ps
CPU time 0.61 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 199224 kb
Host smart-7844707a-53bd-4e5e-b8c9-364255f03459
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766005425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.2766005425
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3119167116
Short name T586
Test name
Test status
Simulation time 56773452 ps
CPU time 0.73 seconds
Started Aug 01 06:30:28 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 198060 kb
Host smart-03a1c5c6-7784-49a7-8b31-6cf964c94cb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119167116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3119167116
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2350870254
Short name T196
Test name
Test status
Simulation time 72426808 ps
CPU time 0.74 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 198716 kb
Host smart-b1927baf-f43e-4ffa-9f7e-c2f81b3e6bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350870254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2350870254
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2296799157
Short name T251
Test name
Test status
Simulation time 38558678 ps
CPU time 0.62 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 197980 kb
Host smart-e6f58573-dd72-4f90-b2b6-35a628712189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296799157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2296799157
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.2401742959
Short name T306
Test name
Test status
Simulation time 306705402 ps
CPU time 0.96 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:34 PM PDT 24
Peak memory 198116 kb
Host smart-6f362385-fac5-4631-80ac-ba8b563178c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401742959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.2401742959
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3373307177
Short name T295
Test name
Test status
Simulation time 28331582 ps
CPU time 0.64 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 197356 kb
Host smart-32a6f1e6-1b6e-4b49-afc8-281e4c12b3f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373307177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3373307177
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.314869645
Short name T284
Test name
Test status
Simulation time 39409326 ps
CPU time 0.64 seconds
Started Aug 01 06:30:27 PM PDT 24
Finished Aug 01 06:30:28 PM PDT 24
Peak memory 198372 kb
Host smart-0e67011a-f40a-4629-bb9b-089775c852b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314869645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.314869645
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1042208547
Short name T495
Test name
Test status
Simulation time 78229453 ps
CPU time 0.69 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 201024 kb
Host smart-4a9393a2-5a6d-4b55-8c02-ff11ff8c5afb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042208547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1042208547
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2469189557
Short name T311
Test name
Test status
Simulation time 71939815 ps
CPU time 0.68 seconds
Started Aug 01 06:30:28 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 198256 kb
Host smart-250d81fa-b55a-425c-b075-2d8da661acb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469189557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2469189557
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2551658718
Short name T269
Test name
Test status
Simulation time 64422048 ps
CPU time 0.85 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 198204 kb
Host smart-46db5a11-2bef-4ac7-a5ca-ef5908b82e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551658718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2551658718
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2600459287
Short name T467
Test name
Test status
Simulation time 47242311 ps
CPU time 0.66 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 199392 kb
Host smart-53c73c57-837e-4c34-96ca-70c5d405936d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600459287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2600459287
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1753316065
Short name T173
Test name
Test status
Simulation time 26865004 ps
CPU time 0.77 seconds
Started Aug 01 06:30:29 PM PDT 24
Finished Aug 01 06:30:30 PM PDT 24
Peak memory 198716 kb
Host smart-f4bd158f-a745-4437-b9aa-1da101352696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753316065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1753316065
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.2125340336
Short name T380
Test name
Test status
Simulation time 90579290 ps
CPU time 0.66 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 198508 kb
Host smart-f10c1be1-c303-476a-8a0c-cf67071f5e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125340336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.2125340336
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.864419496
Short name T493
Test name
Test status
Simulation time 32198581 ps
CPU time 0.62 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 198052 kb
Host smart-ec2406c5-7498-4308-a99e-356830b2ef91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864419496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.864419496
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3909564247
Short name T496
Test name
Test status
Simulation time 167046266 ps
CPU time 1.01 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 198056 kb
Host smart-4ea2fb12-c806-47eb-ae4f-15c3ecdbb06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909564247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3909564247
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2711001185
Short name T3
Test name
Test status
Simulation time 39920706 ps
CPU time 0.59 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 197412 kb
Host smart-855081a5-e2a8-4c2e-8887-31ce3f4188df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711001185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2711001185
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3509597348
Short name T522
Test name
Test status
Simulation time 94442012 ps
CPU time 0.6 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 197860 kb
Host smart-457acb47-c9fc-48b0-90a8-ff1a9264fc09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509597348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3509597348
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2647211357
Short name T163
Test name
Test status
Simulation time 43375721 ps
CPU time 0.71 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 201368 kb
Host smart-e34c9ade-ed6e-46a2-ad79-d5709f5ea5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647211357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2647211357
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.1742194597
Short name T170
Test name
Test status
Simulation time 77894913 ps
CPU time 0.61 seconds
Started Aug 01 06:30:28 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 198340 kb
Host smart-efa8c58f-b271-432b-97da-da969536b509
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742194597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.1742194597
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.109621791
Short name T323
Test name
Test status
Simulation time 29528579 ps
CPU time 0.7 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 198364 kb
Host smart-b8bbfd0f-0f99-4d10-b09a-0b4ee0b5fb58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109621791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.109621791
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1405638872
Short name T420
Test name
Test status
Simulation time 514757434 ps
CPU time 0.71 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 209436 kb
Host smart-2eaaef59-e309-4cf8-bd11-d425524afe37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405638872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1405638872
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1776827634
Short name T416
Test name
Test status
Simulation time 116663023 ps
CPU time 0.7 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 198216 kb
Host smart-4e3a0bea-fe91-4015-bbce-8f3ee000ae6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776827634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1776827634
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2198650033
Short name T82
Test name
Test status
Simulation time 56599135 ps
CPU time 0.69 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 198488 kb
Host smart-5def490b-569a-41b5-8d0b-0dfb1baf27c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198650033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2198650033
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1175549245
Short name T330
Test name
Test status
Simulation time 24113175 ps
CPU time 0.85 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 199900 kb
Host smart-4605739e-d4ab-4e77-9a92-cd0d379e2c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175549245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1175549245
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2861626111
Short name T26
Test name
Test status
Simulation time 61586387 ps
CPU time 0.66 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 198432 kb
Host smart-f86fc95d-0a80-4ecc-b461-74c5e9fe463d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861626111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2861626111
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.338188983
Short name T257
Test name
Test status
Simulation time 35254584 ps
CPU time 0.58 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 197348 kb
Host smart-de72cc35-44cc-45ac-b437-92b62b34614c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338188983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.338188983
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.759782228
Short name T564
Test name
Test status
Simulation time 608859322 ps
CPU time 0.94 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 198396 kb
Host smart-4ab35bce-e1ba-43ed-b540-337d56c93ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759782228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.759782228
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.103320822
Short name T264
Test name
Test status
Simulation time 42943104 ps
CPU time 0.67 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 197420 kb
Host smart-6b325845-af30-410f-a566-81f71c654489
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103320822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.103320822
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1281381588
Short name T241
Test name
Test status
Simulation time 176397009 ps
CPU time 0.59 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 198132 kb
Host smart-f1610b5a-5b85-4654-bf58-2e174bc05cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281381588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1281381588
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.383744543
Short name T307
Test name
Test status
Simulation time 41797041 ps
CPU time 0.71 seconds
Started Aug 01 06:30:35 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 201424 kb
Host smart-785f9c10-b126-48ea-89f5-a63488dd542f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383744543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.383744543
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.2605395530
Short name T597
Test name
Test status
Simulation time 51949899 ps
CPU time 0.8 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 199012 kb
Host smart-e78366ea-e47a-4fb7-bb8a-1156d6cb9cec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605395530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2605395530
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.3150708814
Short name T225
Test name
Test status
Simulation time 313555979 ps
CPU time 0.8 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 209560 kb
Host smart-8197cc01-f255-4c5c-98a5-0fda3638241f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150708814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3150708814
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.349084256
Short name T299
Test name
Test status
Simulation time 58080713 ps
CPU time 0.79 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 198076 kb
Host smart-a6d7785c-f5b4-4fd7-9ca5-835967044eee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349084256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.349084256
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.733333920
Short name T458
Test name
Test status
Simulation time 52569800 ps
CPU time 0.67 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 198532 kb
Host smart-02a11ac9-b086-49db-9d26-d0d00589a530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733333920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.733333920
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.156051367
Short name T415
Test name
Test status
Simulation time 89649358 ps
CPU time 0.74 seconds
Started Aug 01 06:30:31 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 199196 kb
Host smart-4b6fdcc6-55b7-4f1d-b248-25340f6328f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156051367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.156051367
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.926000288
Short name T576
Test name
Test status
Simulation time 29743264 ps
CPU time 0.87 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 200048 kb
Host smart-4c5772ca-7aba-4dc0-9de8-d127cf6d1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926000288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.926000288
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.459331196
Short name T587
Test name
Test status
Simulation time 50416212 ps
CPU time 0.6 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 198028 kb
Host smart-ed1d4b15-14a2-46ae-b86a-806dc11bc5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459331196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_
malfunc.459331196
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2246797637
Short name T242
Test name
Test status
Simulation time 585107078 ps
CPU time 0.98 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:34 PM PDT 24
Peak memory 198116 kb
Host smart-be872e1e-46ef-4833-86dc-fd3cd9e4bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246797637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2246797637
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1991232513
Short name T9
Test name
Test status
Simulation time 76749510 ps
CPU time 0.66 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 197424 kb
Host smart-2f14961c-e485-43b8-9abf-a95e35f1994c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991232513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1991232513
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.4198194231
Short name T413
Test name
Test status
Simulation time 22803675 ps
CPU time 0.64 seconds
Started Aug 01 06:30:32 PM PDT 24
Finished Aug 01 06:30:33 PM PDT 24
Peak memory 198084 kb
Host smart-2d1c546d-9b3b-486a-9420-e53246e94377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198194231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.4198194231
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.3267727229
Short name T540
Test name
Test status
Simulation time 48053767 ps
CPU time 0.79 seconds
Started Aug 01 06:30:34 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 198588 kb
Host smart-5cad77a1-2536-4f53-a42d-efc027402c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267727229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3267727229
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.843426558
Short name T315
Test name
Test status
Simulation time 101017038 ps
CPU time 0.94 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 209532 kb
Host smart-21cf10df-cecf-4284-88b3-c32fc6e6a4ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843426558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.843426558
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1863965573
Short name T312
Test name
Test status
Simulation time 102280306 ps
CPU time 0.73 seconds
Started Aug 01 06:30:30 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 197912 kb
Host smart-45f751ad-8859-4cb7-b049-4c099653bfcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863965573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1863965573
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3294754057
Short name T438
Test name
Test status
Simulation time 29017147 ps
CPU time 0.7 seconds
Started Aug 01 06:30:29 PM PDT 24
Finished Aug 01 06:30:29 PM PDT 24
Peak memory 198736 kb
Host smart-7d2a7a71-caaf-4531-b7d5-e8a9035f0f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294754057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3294754057
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2775833346
Short name T84
Test name
Test status
Simulation time 44874149 ps
CPU time 0.91 seconds
Started Aug 01 06:29:26 PM PDT 24
Finished Aug 01 06:29:27 PM PDT 24
Peak memory 200132 kb
Host smart-57a530e4-506c-4e8f-ba05-78e518f78ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775833346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2775833346
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2331968867
Short name T432
Test name
Test status
Simulation time 60294397 ps
CPU time 0.71 seconds
Started Aug 01 06:29:34 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 199144 kb
Host smart-707cdfc2-e8af-42ae-be06-41be1cb3a6ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331968867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2331968867
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3820695056
Short name T558
Test name
Test status
Simulation time 29740566 ps
CPU time 0.62 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 198008 kb
Host smart-9eb2c038-203c-4dfc-b815-1e0ce134f13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820695056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3820695056
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3207694981
Short name T321
Test name
Test status
Simulation time 166341155 ps
CPU time 0.96 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 198100 kb
Host smart-28b5d8a1-5493-4bd2-b9c7-512188afbead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207694981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3207694981
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.328833799
Short name T581
Test name
Test status
Simulation time 74395450 ps
CPU time 0.59 seconds
Started Aug 01 06:29:32 PM PDT 24
Finished Aug 01 06:29:32 PM PDT 24
Peak memory 198036 kb
Host smart-b7a09785-f499-45b8-bc80-7ab8bfafab75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328833799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.328833799
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.3477681079
Short name T394
Test name
Test status
Simulation time 66123947 ps
CPU time 0.59 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:33 PM PDT 24
Peak memory 198444 kb
Host smart-47caf74f-0754-49e4-a008-5e81356fff70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477681079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3477681079
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.3296546707
Short name T180
Test name
Test status
Simulation time 54083977 ps
CPU time 0.71 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 201412 kb
Host smart-9c036a20-799b-44a4-bf09-02e12e649e78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296546707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.3296546707
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1869896702
Short name T511
Test name
Test status
Simulation time 115915161 ps
CPU time 0.75 seconds
Started Aug 01 06:29:31 PM PDT 24
Finished Aug 01 06:29:32 PM PDT 24
Peak memory 199176 kb
Host smart-9435b502-01ac-4ee0-8d63-70cfc5ba6ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869896702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1869896702
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.2269974404
Short name T41
Test name
Test status
Simulation time 262904810 ps
CPU time 0.78 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 209524 kb
Host smart-65efe78b-1938-4af6-bf3a-c3c9a68b2f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269974404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2269974404
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.3536067889
Short name T17
Test name
Test status
Simulation time 609558290 ps
CPU time 2.18 seconds
Started Aug 01 06:29:30 PM PDT 24
Finished Aug 01 06:29:32 PM PDT 24
Peak memory 218004 kb
Host smart-45802a6d-7be1-4054-ac27-490c74f01b8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536067889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3536067889
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1115008311
Short name T58
Test name
Test status
Simulation time 58101543 ps
CPU time 0.66 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 198572 kb
Host smart-3d4ded6f-d8ad-4abf-880d-1148f8762296
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115008311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.1115008311
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.870509579
Short name T562
Test name
Test status
Simulation time 125145015 ps
CPU time 0.82 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 199160 kb
Host smart-ce3d2e87-b323-46d6-9902-6bf2ab84b3ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870509579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.870509579
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3574693518
Short name T360
Test name
Test status
Simulation time 29269338 ps
CPU time 0.66 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 199400 kb
Host smart-0af8dad2-92fc-4c84-b1cd-b824de4c62bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574693518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3574693518
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3987429781
Short name T234
Test name
Test status
Simulation time 92228036 ps
CPU time 0.76 seconds
Started Aug 01 06:30:36 PM PDT 24
Finished Aug 01 06:30:37 PM PDT 24
Peak memory 199968 kb
Host smart-7068349a-b4fd-4406-8292-8d2d3ad1a7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987429781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3987429781
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1237364162
Short name T191
Test name
Test status
Simulation time 45286366 ps
CPU time 0.72 seconds
Started Aug 01 06:30:43 PM PDT 24
Finished Aug 01 06:30:44 PM PDT 24
Peak memory 198464 kb
Host smart-f4c1560f-7412-4c7f-a0e4-ac4baea8f95d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237364162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1237364162
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.657373119
Short name T447
Test name
Test status
Simulation time 29738610 ps
CPU time 0.68 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 198064 kb
Host smart-2cabc5f8-91d9-43d3-9ba4-e4450364f9c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657373119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_
malfunc.657373119
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2350158152
Short name T276
Test name
Test status
Simulation time 2472234570 ps
CPU time 1.03 seconds
Started Aug 01 06:30:45 PM PDT 24
Finished Aug 01 06:30:47 PM PDT 24
Peak memory 198224 kb
Host smart-9f1c27b4-0369-4b11-8d40-227deef2bc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350158152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2350158152
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1453147234
Short name T475
Test name
Test status
Simulation time 62966541 ps
CPU time 0.62 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 197372 kb
Host smart-6ece2d28-9390-4dd0-8af6-5f99847048f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453147234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1453147234
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2374913121
Short name T443
Test name
Test status
Simulation time 48811538 ps
CPU time 0.61 seconds
Started Aug 01 06:30:38 PM PDT 24
Finished Aug 01 06:30:39 PM PDT 24
Peak memory 198380 kb
Host smart-2af7b011-f4a0-4195-9208-7e3b2d7518f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374913121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2374913121
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.736211534
Short name T249
Test name
Test status
Simulation time 60638040 ps
CPU time 0.64 seconds
Started Aug 01 06:30:35 PM PDT 24
Finished Aug 01 06:30:36 PM PDT 24
Peak memory 199260 kb
Host smart-1b81696a-21a4-4955-88d1-628b66cb0cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736211534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.736211534
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1877679158
Short name T40
Test name
Test status
Simulation time 118600099 ps
CPU time 0.92 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 209452 kb
Host smart-8a876549-7b24-4f35-9add-d631ea0f2277
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877679158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1877679158
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1487740670
Short name T36
Test name
Test status
Simulation time 64718118 ps
CPU time 0.81 seconds
Started Aug 01 06:30:39 PM PDT 24
Finished Aug 01 06:30:40 PM PDT 24
Peak memory 198080 kb
Host smart-e208a7cd-ab57-4bde-beeb-4490822b51fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487740670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1487740670
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1235524024
Short name T448
Test name
Test status
Simulation time 55078005 ps
CPU time 0.63 seconds
Started Aug 01 06:30:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 198576 kb
Host smart-de664e1f-b74a-4203-84b8-b200850566cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235524024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1235524024
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4077821565
Short name T625
Test name
Test status
Simulation time 69627144 ps
CPU time 0.75 seconds
Started Aug 01 06:30:39 PM PDT 24
Finished Aug 01 06:30:40 PM PDT 24
Peak memory 198584 kb
Host smart-b6c56322-6630-42cc-9765-48bd23749db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077821565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.4077821565
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2109024927
Short name T268
Test name
Test status
Simulation time 29680563 ps
CPU time 0.64 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 198080 kb
Host smart-c78fc477-d379-4fab-9b63-fc1f19371c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109024927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2109024927
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1691768828
Short name T124
Test name
Test status
Simulation time 425370063 ps
CPU time 0.94 seconds
Started Aug 01 06:30:43 PM PDT 24
Finished Aug 01 06:30:44 PM PDT 24
Peak memory 198096 kb
Host smart-5c163d4a-5a09-41d5-85f9-8994b61d6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691768828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1691768828
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.1144367403
Short name T361
Test name
Test status
Simulation time 119862972 ps
CPU time 0.61 seconds
Started Aug 01 06:30:39 PM PDT 24
Finished Aug 01 06:30:40 PM PDT 24
Peak memory 198096 kb
Host smart-09f25a6e-aa29-4d83-8623-708045f7872f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144367403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1144367403
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.323946832
Short name T383
Test name
Test status
Simulation time 144639504 ps
CPU time 0.61 seconds
Started Aug 01 06:30:39 PM PDT 24
Finished Aug 01 06:30:40 PM PDT 24
Peak memory 198120 kb
Host smart-fe89eadb-1c25-4f03-a50a-3581f5cb5d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323946832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.323946832
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.844035476
Short name T154
Test name
Test status
Simulation time 80264088 ps
CPU time 0.68 seconds
Started Aug 01 06:30:46 PM PDT 24
Finished Aug 01 06:30:47 PM PDT 24
Peak memory 201328 kb
Host smart-b181760b-2d12-435a-af3f-32fa77c52cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844035476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.844035476
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.1815197233
Short name T349
Test name
Test status
Simulation time 70415823 ps
CPU time 0.76 seconds
Started Aug 01 06:30:39 PM PDT 24
Finished Aug 01 06:30:40 PM PDT 24
Peak memory 198596 kb
Host smart-8780d1f0-3ecc-4c6b-b8dc-4ba48243ddfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815197233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.1815197233
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2015646434
Short name T291
Test name
Test status
Simulation time 149256250 ps
CPU time 0.91 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:44 PM PDT 24
Peak memory 209512 kb
Host smart-a8659f14-6fae-4b10-9578-f3a76fa2076d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015646434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2015646434
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3907984658
Short name T472
Test name
Test status
Simulation time 52489873 ps
CPU time 0.86 seconds
Started Aug 01 06:30:43 PM PDT 24
Finished Aug 01 06:30:44 PM PDT 24
Peak memory 199184 kb
Host smart-59023dd8-c462-4aac-b761-86e46c409878
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907984658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3907984658
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3196788730
Short name T517
Test name
Test status
Simulation time 40963236 ps
CPU time 0.64 seconds
Started Aug 01 06:30:41 PM PDT 24
Finished Aug 01 06:30:42 PM PDT 24
Peak memory 198616 kb
Host smart-4c9d6c88-4b2a-4fd4-a5e2-c17ddbc47c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196788730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3196788730
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.2167012931
Short name T531
Test name
Test status
Simulation time 70672914 ps
CPU time 0.87 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 200276 kb
Host smart-d2c1d4ed-fa98-47d5-85ec-ec2451c14986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167012931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2167012931
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2460941847
Short name T555
Test name
Test status
Simulation time 81963975 ps
CPU time 0.69 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 198400 kb
Host smart-87dfd9f7-16b6-4505-b022-1bf856fa4cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460941847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2460941847
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3167336737
Short name T547
Test name
Test status
Simulation time 36545385 ps
CPU time 0.6 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 197360 kb
Host smart-b275b3c5-fb55-40e9-842f-9ee424407466
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167336737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3167336737
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2423746512
Short name T12
Test name
Test status
Simulation time 795065084 ps
CPU time 1.05 seconds
Started Aug 01 06:30:44 PM PDT 24
Finished Aug 01 06:30:45 PM PDT 24
Peak memory 198136 kb
Host smart-720d517a-b000-405c-9a87-91bc443c1eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423746512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2423746512
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.40206788
Short name T326
Test name
Test status
Simulation time 147641731 ps
CPU time 0.61 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 198076 kb
Host smart-45b8d31b-d5f7-47b3-9419-ca3cde948696
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40206788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.40206788
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1777800613
Short name T309
Test name
Test status
Simulation time 88983884 ps
CPU time 0.59 seconds
Started Aug 01 06:30:40 PM PDT 24
Finished Aug 01 06:30:41 PM PDT 24
Peak memory 198128 kb
Host smart-13cc66a3-4e88-4ab4-be05-4dd7f8cabb38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777800613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1777800613
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2730751541
Short name T584
Test name
Test status
Simulation time 67615197 ps
CPU time 0.69 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 201140 kb
Host smart-fa91ae31-616d-4585-9534-d3ae70717f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730751541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2730751541
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1106291531
Short name T37
Test name
Test status
Simulation time 49078851 ps
CPU time 0.8 seconds
Started Aug 01 06:30:41 PM PDT 24
Finished Aug 01 06:30:42 PM PDT 24
Peak memory 199124 kb
Host smart-b5a447c4-89aa-49ed-8ee4-10fd84645813
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106291531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1106291531
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.2741022574
Short name T260
Test name
Test status
Simulation time 113175450 ps
CPU time 0.9 seconds
Started Aug 01 06:30:45 PM PDT 24
Finished Aug 01 06:30:46 PM PDT 24
Peak memory 209568 kb
Host smart-6d1c6cd9-edc4-40fa-a1ca-246a093a9c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741022574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2741022574
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1207061514
Short name T281
Test name
Test status
Simulation time 55083212 ps
CPU time 0.78 seconds
Started Aug 01 06:30:46 PM PDT 24
Finished Aug 01 06:30:47 PM PDT 24
Peak memory 198240 kb
Host smart-0dcfd547-20eb-4785-99a3-f8a6d0ed2dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207061514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1207061514
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1602362071
Short name T136
Test name
Test status
Simulation time 26811293 ps
CPU time 0.67 seconds
Started Aug 01 06:30:43 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 199360 kb
Host smart-f47d5067-ad8f-4f8e-8ad4-4753f5076ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602362071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1602362071
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.1081926849
Short name T512
Test name
Test status
Simulation time 35132407 ps
CPU time 0.85 seconds
Started Aug 01 06:30:46 PM PDT 24
Finished Aug 01 06:30:47 PM PDT 24
Peak memory 200108 kb
Host smart-e492da46-9ab7-496f-bb87-04ba47310048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081926849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1081926849
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2231620383
Short name T142
Test name
Test status
Simulation time 68159365 ps
CPU time 0.66 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:53 PM PDT 24
Peak memory 198268 kb
Host smart-91a1477b-0982-4b0e-88bb-08fe3bd32c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231620383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2231620383
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.9346855
Short name T427
Test name
Test status
Simulation time 29951798 ps
CPU time 0.62 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 198080 kb
Host smart-8ffccb3e-d4a3-418c-b1bb-d28a9dd2e36a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9346855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malf
unc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_ma
lfunc.9346855
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.510481920
Short name T385
Test name
Test status
Simulation time 290908507 ps
CPU time 0.93 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:53 PM PDT 24
Peak memory 198448 kb
Host smart-4de71537-eb56-4026-9cc2-9655fda8e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510481920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.510481920
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2350211613
Short name T408
Test name
Test status
Simulation time 28108772 ps
CPU time 0.64 seconds
Started Aug 01 06:30:49 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 197424 kb
Host smart-88721c20-480e-4a84-a25d-361d2f3d2483
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350211613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2350211613
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3043513679
Short name T457
Test name
Test status
Simulation time 34056503 ps
CPU time 0.61 seconds
Started Aug 01 06:30:52 PM PDT 24
Finished Aug 01 06:30:53 PM PDT 24
Peak memory 198444 kb
Host smart-6a75769e-792c-4dc9-96a2-ed28ea31a83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043513679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3043513679
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1554012045
Short name T161
Test name
Test status
Simulation time 75792472 ps
CPU time 0.65 seconds
Started Aug 01 06:30:49 PM PDT 24
Finished Aug 01 06:30:50 PM PDT 24
Peak memory 201356 kb
Host smart-6e4541f2-714f-49ac-83c5-ac846b32d3ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554012045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1554012045
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.2025616092
Short name T490
Test name
Test status
Simulation time 83014144 ps
CPU time 0.75 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 198184 kb
Host smart-a32db0a8-6f00-403d-85a4-46f5d7d791bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025616092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2025616092
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3122523986
Short name T367
Test name
Test status
Simulation time 158311360 ps
CPU time 0.78 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 209536 kb
Host smart-1c9c8f1c-1cd0-4384-ba98-6aa51630d68f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122523986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3122523986
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.4100355787
Short name T247
Test name
Test status
Simulation time 53471361 ps
CPU time 0.81 seconds
Started Aug 01 06:30:42 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 198324 kb
Host smart-0760bce5-aa54-40f6-91de-69f948d2170a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100355787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4100355787
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1052842502
Short name T297
Test name
Test status
Simulation time 90304673 ps
CPU time 0.63 seconds
Started Aug 01 06:30:45 PM PDT 24
Finished Aug 01 06:30:45 PM PDT 24
Peak memory 198572 kb
Host smart-09f376f7-41c3-46b6-80c3-e06331cde687
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052842502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1052842502
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.3890560773
Short name T429
Test name
Test status
Simulation time 32297762 ps
CPU time 0.98 seconds
Started Aug 01 06:30:53 PM PDT 24
Finished Aug 01 06:30:54 PM PDT 24
Peak memory 200932 kb
Host smart-e0ec955a-7dd6-4171-af93-b81c719604c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890560773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3890560773
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1136927240
Short name T129
Test name
Test status
Simulation time 57114523 ps
CPU time 0.71 seconds
Started Aug 01 06:30:57 PM PDT 24
Finished Aug 01 06:30:57 PM PDT 24
Peak memory 199144 kb
Host smart-593620ee-06c3-4af3-893e-8cf6529dba3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136927240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1136927240
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3831593962
Short name T543
Test name
Test status
Simulation time 36820304 ps
CPU time 0.6 seconds
Started Aug 01 06:30:50 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 198024 kb
Host smart-8b67d605-06b6-49d8-a17c-7c969889bcb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831593962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3831593962
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.755876440
Short name T485
Test name
Test status
Simulation time 1684328436 ps
CPU time 0.97 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 198396 kb
Host smart-42c11d97-eecd-497f-a6c3-859292a34196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755876440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.755876440
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.4265648996
Short name T256
Test name
Test status
Simulation time 71397970 ps
CPU time 0.61 seconds
Started Aug 01 06:30:49 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 198076 kb
Host smart-2dca20ed-e842-4fca-8093-3ba90b44f1a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265648996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.4265648996
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2414029140
Short name T338
Test name
Test status
Simulation time 49982217 ps
CPU time 0.67 seconds
Started Aug 01 06:30:49 PM PDT 24
Finished Aug 01 06:30:50 PM PDT 24
Peak memory 198436 kb
Host smart-d168a218-b1a8-4408-a2fa-63d2936b031c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414029140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2414029140
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1503473336
Short name T263
Test name
Test status
Simulation time 68493353 ps
CPU time 0.83 seconds
Started Aug 01 06:30:52 PM PDT 24
Finished Aug 01 06:30:53 PM PDT 24
Peak memory 198448 kb
Host smart-d61251d6-c18f-4606-9774-e1d9cf67d8b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503473336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1503473336
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3963616665
Short name T39
Test name
Test status
Simulation time 104660542 ps
CPU time 1.02 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 209572 kb
Host smart-24daf0d9-ba83-4d08-807e-114031eacfa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963616665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3963616665
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2874394601
Short name T115
Test name
Test status
Simulation time 113618957 ps
CPU time 0.76 seconds
Started Aug 01 06:30:50 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 197936 kb
Host smart-478b166e-aa7b-4ece-9126-9553c3375e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874394601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2874394601
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2469083133
Short name T494
Test name
Test status
Simulation time 59078615 ps
CPU time 0.68 seconds
Started Aug 01 06:30:53 PM PDT 24
Finished Aug 01 06:30:54 PM PDT 24
Peak memory 199432 kb
Host smart-24906209-4f26-42af-aacb-624f84775d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469083133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2469083133
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1303267286
Short name T515
Test name
Test status
Simulation time 82064898 ps
CPU time 0.85 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 200060 kb
Host smart-54a471fa-d94c-4260-a13a-8cb567aed213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303267286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1303267286
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2679912611
Short name T456
Test name
Test status
Simulation time 59166882 ps
CPU time 0.82 seconds
Started Aug 01 06:30:52 PM PDT 24
Finished Aug 01 06:30:53 PM PDT 24
Peak memory 199112 kb
Host smart-c3249be6-2c29-47d5-b15c-014cc7e48b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679912611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2679912611
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3777391593
Short name T88
Test name
Test status
Simulation time 40208010 ps
CPU time 0.63 seconds
Started Aug 01 06:30:50 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 198080 kb
Host smart-3fdfaeee-f171-4c4f-939a-221f92820be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777391593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3777391593
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2406681877
Short name T233
Test name
Test status
Simulation time 162613575 ps
CPU time 0.98 seconds
Started Aug 01 06:30:52 PM PDT 24
Finished Aug 01 06:30:54 PM PDT 24
Peak memory 198072 kb
Host smart-0c20d639-8c02-4bbe-802e-1fd5ebf2fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406681877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2406681877
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3733695417
Short name T217
Test name
Test status
Simulation time 39432229 ps
CPU time 0.66 seconds
Started Aug 01 06:30:50 PM PDT 24
Finished Aug 01 06:30:51 PM PDT 24
Peak memory 197952 kb
Host smart-cb2e1ba2-4568-492b-9012-f6ac39ceee3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733695417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3733695417
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2496738809
Short name T497
Test name
Test status
Simulation time 51157786 ps
CPU time 0.67 seconds
Started Aug 01 06:30:48 PM PDT 24
Finished Aug 01 06:30:49 PM PDT 24
Peak memory 198320 kb
Host smart-ec952f1b-5ef3-4ff9-bc38-ea186d59ff03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496738809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2496738809
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2132585672
Short name T243
Test name
Test status
Simulation time 126963691 ps
CPU time 0.69 seconds
Started Aug 01 06:30:53 PM PDT 24
Finished Aug 01 06:30:54 PM PDT 24
Peak memory 199120 kb
Host smart-c335705f-33ab-4906-ac37-c1a7bb2e376d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132585672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2132585672
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.2026209676
Short name T377
Test name
Test status
Simulation time 118716595 ps
CPU time 0.95 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 209500 kb
Host smart-9bf2684e-4c84-41c5-9750-9fa0e631b0d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026209676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2026209676
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2282310075
Short name T230
Test name
Test status
Simulation time 154482494 ps
CPU time 0.9 seconds
Started Aug 01 06:30:51 PM PDT 24
Finished Aug 01 06:30:52 PM PDT 24
Peak memory 199536 kb
Host smart-455e5e48-ebd7-43c3-9684-f3a12de952e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282310075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2282310075
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.980801505
Short name T618
Test name
Test status
Simulation time 59090594 ps
CPU time 0.63 seconds
Started Aug 01 06:30:49 PM PDT 24
Finished Aug 01 06:30:50 PM PDT 24
Peak memory 198520 kb
Host smart-daa082de-648e-4ac7-96f1-492afec2db36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980801505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.980801505
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.1427799556
Short name T500
Test name
Test status
Simulation time 52526745 ps
CPU time 0.69 seconds
Started Aug 01 06:30:54 PM PDT 24
Finished Aug 01 06:30:55 PM PDT 24
Peak memory 198696 kb
Host smart-98eef024-36d8-4192-8eb6-8faa2a970e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427799556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1427799556
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2197444475
Short name T146
Test name
Test status
Simulation time 83438251 ps
CPU time 0.67 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 198308 kb
Host smart-f4a1528b-8f61-4fdc-a4f1-c7685b240ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197444475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2197444475
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.710973846
Short name T605
Test name
Test status
Simulation time 45689056 ps
CPU time 0.62 seconds
Started Aug 01 06:31:00 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 198028 kb
Host smart-4de3262f-44ea-47b1-abf3-065289c0d219
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710973846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_
malfunc.710973846
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3209922311
Short name T539
Test name
Test status
Simulation time 313306409 ps
CPU time 0.96 seconds
Started Aug 01 06:30:56 PM PDT 24
Finished Aug 01 06:30:57 PM PDT 24
Peak memory 198128 kb
Host smart-a1c3c5bf-5603-450c-99ca-7ba37f1854aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209922311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3209922311
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.241775735
Short name T565
Test name
Test status
Simulation time 111039749 ps
CPU time 0.6 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 198140 kb
Host smart-925dfde8-2902-4820-80fd-c6985f57e444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241775735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.241775735
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1909291881
Short name T350
Test name
Test status
Simulation time 135946289 ps
CPU time 0.63 seconds
Started Aug 01 06:30:56 PM PDT 24
Finished Aug 01 06:30:57 PM PDT 24
Peak memory 198428 kb
Host smart-b2f01fa4-99ef-4d44-9389-6464eb55cbcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909291881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1909291881
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.22950056
Short name T179
Test name
Test status
Simulation time 46974105 ps
CPU time 0.79 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 201412 kb
Host smart-0bda4fe8-5ffe-440a-b59e-07ff93b34dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid
.22950056
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.2302826589
Short name T376
Test name
Test status
Simulation time 70026709 ps
CPU time 0.95 seconds
Started Aug 01 06:30:57 PM PDT 24
Finished Aug 01 06:30:58 PM PDT 24
Peak memory 199196 kb
Host smart-7f74d0dc-3d15-46f3-bfcf-4e3c26a6d6de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302826589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2302826589
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1258728874
Short name T334
Test name
Test status
Simulation time 97442045 ps
CPU time 0.88 seconds
Started Aug 01 06:31:07 PM PDT 24
Finished Aug 01 06:31:08 PM PDT 24
Peak memory 209524 kb
Host smart-84076242-c706-4a7b-8a09-a136e4cab2b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258728874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1258728874
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.176505015
Short name T216
Test name
Test status
Simulation time 90086894 ps
CPU time 0.79 seconds
Started Aug 01 06:30:59 PM PDT 24
Finished Aug 01 06:31:00 PM PDT 24
Peak memory 199308 kb
Host smart-f175f889-5430-44ae-8985-acc871b0316c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176505015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.176505015
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3920378737
Short name T372
Test name
Test status
Simulation time 32274493 ps
CPU time 0.68 seconds
Started Aug 01 06:30:57 PM PDT 24
Finished Aug 01 06:30:58 PM PDT 24
Peak memory 198568 kb
Host smart-afd2c268-013a-4a3d-9fde-1129532d4502
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920378737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3920378737
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.1803618554
Short name T552
Test name
Test status
Simulation time 108657737 ps
CPU time 0.86 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 200264 kb
Host smart-4a5c2c88-e67c-4d7f-ae6b-8fd785ba3f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803618554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1803618554
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.910696118
Short name T133
Test name
Test status
Simulation time 65769891 ps
CPU time 0.86 seconds
Started Aug 01 06:31:08 PM PDT 24
Finished Aug 01 06:31:09 PM PDT 24
Peak memory 199144 kb
Host smart-8d3f9daa-5183-4932-a6a2-74c6fdbcaec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910696118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.910696118
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1117027394
Short name T328
Test name
Test status
Simulation time 29355658 ps
CPU time 0.68 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198036 kb
Host smart-8bb4a772-0959-4117-a960-f664b7f70512
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117027394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1117027394
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2857976504
Short name T290
Test name
Test status
Simulation time 230019425 ps
CPU time 0.98 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 198096 kb
Host smart-94d37560-20bf-497d-9061-ef57502215ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857976504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2857976504
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1780822392
Short name T534
Test name
Test status
Simulation time 61873796 ps
CPU time 0.62 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 197320 kb
Host smart-60583ac3-5be5-4297-b980-86c9e076bca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780822392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1780822392
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1228843515
Short name T489
Test name
Test status
Simulation time 87546047 ps
CPU time 0.61 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198104 kb
Host smart-67d528d4-4346-49c0-8d17-b405d789a9e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228843515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1228843515
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3229956057
Short name T157
Test name
Test status
Simulation time 47893668 ps
CPU time 0.7 seconds
Started Aug 01 06:30:59 PM PDT 24
Finished Aug 01 06:31:00 PM PDT 24
Peak memory 201396 kb
Host smart-30eaf72f-f1ba-4402-ba11-94ad5ea5babb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229956057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3229956057
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.4134623421
Short name T34
Test name
Test status
Simulation time 34369929 ps
CPU time 0.71 seconds
Started Aug 01 06:31:09 PM PDT 24
Finished Aug 01 06:31:10 PM PDT 24
Peak memory 199176 kb
Host smart-28178186-7889-4a8f-88ec-ec130e0b4adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134623421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.4134623421
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3732180684
Short name T235
Test name
Test status
Simulation time 112061130 ps
CPU time 0.92 seconds
Started Aug 01 06:31:05 PM PDT 24
Finished Aug 01 06:31:07 PM PDT 24
Peak memory 209460 kb
Host smart-d05df9f6-5ad0-4dec-ab69-12a1bf673a00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732180684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3732180684
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2785054794
Short name T116
Test name
Test status
Simulation time 118964975 ps
CPU time 0.72 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 198108 kb
Host smart-2bf3f4f7-eb4c-4bda-8509-2eb94a981691
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785054794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2785054794
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.757502363
Short name T245
Test name
Test status
Simulation time 50724518 ps
CPU time 0.63 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 198516 kb
Host smart-d6e6f2db-32ec-4d6f-8959-9131ea6f21bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757502363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.757502363
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.4038193776
Short name T51
Test name
Test status
Simulation time 45709293 ps
CPU time 0.96 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 200212 kb
Host smart-34029a59-83ad-4c43-990b-49f5e9655d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038193776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.4038193776
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1714233409
Short name T414
Test name
Test status
Simulation time 64003597 ps
CPU time 0.79 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 199104 kb
Host smart-e6a1e850-85e4-450b-b7ea-b91905b19c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714233409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.1714233409
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2745692166
Short name T127
Test name
Test status
Simulation time 29489156 ps
CPU time 0.67 seconds
Started Aug 01 06:31:00 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 197984 kb
Host smart-64e78e57-1c81-4eab-a0dc-c862bb3caa62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745692166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.2745692166
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.2463529136
Short name T42
Test name
Test status
Simulation time 159002894 ps
CPU time 1 seconds
Started Aug 01 06:31:08 PM PDT 24
Finished Aug 01 06:31:09 PM PDT 24
Peak memory 198028 kb
Host smart-2c1dfa78-837b-4f5c-93da-7ecad69e366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463529136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.2463529136
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.1526672728
Short name T345
Test name
Test status
Simulation time 47602716 ps
CPU time 0.62 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 198032 kb
Host smart-4c3fb6f1-1a5a-4e22-bc0c-f53069fad450
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526672728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1526672728
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.1893454706
Short name T505
Test name
Test status
Simulation time 24549741 ps
CPU time 0.62 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 198440 kb
Host smart-1dd35b39-178e-40bf-8afd-f45227d94e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893454706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1893454706
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2082369496
Short name T182
Test name
Test status
Simulation time 42573499 ps
CPU time 0.81 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 201416 kb
Host smart-89da307c-2926-4d0e-91af-4996426f3411
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082369496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2082369496
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2612098248
Short name T287
Test name
Test status
Simulation time 61742695 ps
CPU time 0.87 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198340 kb
Host smart-f148cc99-22a1-4340-a610-70e2a212bcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612098248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2612098248
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.359340282
Short name T370
Test name
Test status
Simulation time 99135369 ps
CPU time 0.95 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 209468 kb
Host smart-12ef8314-ec78-46d9-8a24-c9f6ecd5caca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359340282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.359340282
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2397919829
Short name T212
Test name
Test status
Simulation time 364728157 ps
CPU time 0.84 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:02 PM PDT 24
Peak memory 199272 kb
Host smart-2618ff8e-18e9-4734-8ef2-5c7d2ea32c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397919829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2397919829
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3302083599
Short name T379
Test name
Test status
Simulation time 209829528 ps
CPU time 0.61 seconds
Started Aug 01 06:31:00 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 198488 kb
Host smart-ff146b39-609b-4b0e-b0b3-4df7d68f6a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302083599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3302083599
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3726684984
Short name T444
Test name
Test status
Simulation time 33541498 ps
CPU time 0.72 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 199164 kb
Host smart-b38860ea-550f-4ed4-8b8b-c1e4b0d4eb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726684984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3726684984
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2874497292
Short name T491
Test name
Test status
Simulation time 53090719 ps
CPU time 0.73 seconds
Started Aug 01 06:31:05 PM PDT 24
Finished Aug 01 06:31:06 PM PDT 24
Peak memory 199124 kb
Host smart-8373f66c-42bc-432e-b2e2-35abe103b685
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874497292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2874497292
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.1845831969
Short name T248
Test name
Test status
Simulation time 31746920 ps
CPU time 0.62 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 197956 kb
Host smart-f5cc1809-7a1c-45d6-901c-84885940182e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845831969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.1845831969
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1326320890
Short name T556
Test name
Test status
Simulation time 307944724 ps
CPU time 1 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 198088 kb
Host smart-c8fef887-ec18-435b-b8d9-6ca7e151e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326320890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1326320890
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.3014771909
Short name T498
Test name
Test status
Simulation time 65538847 ps
CPU time 0.65 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 198044 kb
Host smart-26f026e8-20c1-4043-8d03-8529f10d9628
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014771909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.3014771909
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1660599727
Short name T530
Test name
Test status
Simulation time 44301356 ps
CPU time 0.66 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198408 kb
Host smart-4a19a022-932a-4187-b97f-94f4ead545c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660599727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1660599727
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3597643862
Short name T177
Test name
Test status
Simulation time 82189357 ps
CPU time 0.68 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 201416 kb
Host smart-d3cc3c7b-6ead-4517-9bdf-8c6be0b4184d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597643862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3597643862
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3703372986
Short name T266
Test name
Test status
Simulation time 38866515 ps
CPU time 0.65 seconds
Started Aug 01 06:31:00 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 198220 kb
Host smart-e3ce8dbf-8ade-439b-b0a2-a9d7e3026216
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703372986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3703372986
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.649255267
Short name T220
Test name
Test status
Simulation time 121587602 ps
CPU time 0.93 seconds
Started Aug 01 06:31:01 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 209404 kb
Host smart-23c40cdb-3ca3-4bfd-8267-5d0778377136
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649255267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.649255267
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2942325936
Short name T316
Test name
Test status
Simulation time 51558227 ps
CPU time 0.84 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198180 kb
Host smart-65aa2f67-d2b0-4d44-abfd-f6ffa65f530b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942325936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2942325936
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2372002697
Short name T79
Test name
Test status
Simulation time 29620583 ps
CPU time 0.81 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 199400 kb
Host smart-553d4b6c-3555-468c-b9bf-8a902f686ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372002697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2372002697
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.4021129331
Short name T410
Test name
Test status
Simulation time 20652735 ps
CPU time 0.71 seconds
Started Aug 01 06:29:29 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 198564 kb
Host smart-21e7123e-1799-41bc-99b3-36341315a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021129331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4021129331
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.337928418
Short name T401
Test name
Test status
Simulation time 39219191 ps
CPU time 0.71 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:34 PM PDT 24
Peak memory 199208 kb
Host smart-12d56653-4f2c-46e9-8626-fc210c71c38f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337928418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.337928418
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3905514720
Short name T623
Test name
Test status
Simulation time 29768184 ps
CPU time 0.63 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 198024 kb
Host smart-c3187ffb-729f-4451-abef-0a34fe4a956b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905514720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3905514720
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2647394762
Short name T409
Test name
Test status
Simulation time 321429988 ps
CPU time 0.98 seconds
Started Aug 01 06:29:32 PM PDT 24
Finished Aug 01 06:29:33 PM PDT 24
Peak memory 198100 kb
Host smart-6d56b851-b9af-4077-8047-19832d3859ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647394762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2647394762
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.534171727
Short name T423
Test name
Test status
Simulation time 56396120 ps
CPU time 0.59 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 198112 kb
Host smart-aebec8d1-34b7-4387-b1a9-fa8fda0535ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534171727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.534171727
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.1186878873
Short name T258
Test name
Test status
Simulation time 32155372 ps
CPU time 0.63 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 198064 kb
Host smart-720bd709-00fb-4b70-8bd2-3e695146f0e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186878873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1186878873
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.82038790
Short name T160
Test name
Test status
Simulation time 103163435 ps
CPU time 0.69 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:34 PM PDT 24
Peak memory 201392 kb
Host smart-3b0c161b-5b91-4f51-bb55-f0a2494b8af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82038790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.82038790
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.818961475
Short name T222
Test name
Test status
Simulation time 68642687 ps
CPU time 0.86 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:30 PM PDT 24
Peak memory 199396 kb
Host smart-03d856ac-85fc-4551-a8d0-1c537b57ed6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818961475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.818961475
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1846440460
Short name T318
Test name
Test status
Simulation time 115036024 ps
CPU time 0.95 seconds
Started Aug 01 06:29:32 PM PDT 24
Finished Aug 01 06:29:33 PM PDT 24
Peak memory 209424 kb
Host smart-a68865c3-3982-4eba-991c-4d787495fd2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846440460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1846440460
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.430022915
Short name T31
Test name
Test status
Simulation time 683680103 ps
CPU time 2.18 seconds
Started Aug 01 06:29:33 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 218020 kb
Host smart-5869924a-b51d-4795-ac46-c78005c45eca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430022915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.430022915
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3231470188
Short name T468
Test name
Test status
Simulation time 125359697 ps
CPU time 0.77 seconds
Started Aug 01 06:29:27 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 199172 kb
Host smart-34dc0c75-dd2f-469f-8a5b-2d8039ab5f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231470188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3231470188
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2258778766
Short name T7
Test name
Test status
Simulation time 32775944 ps
CPU time 0.67 seconds
Started Aug 01 06:29:28 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 198524 kb
Host smart-83dcd78c-683b-4587-abfc-44cb5ab41189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258778766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2258778766
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1530231468
Short name T90
Test name
Test status
Simulation time 51545043 ps
CPU time 0.8 seconds
Started Aug 01 06:31:03 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 198848 kb
Host smart-81acb81b-9deb-4b4e-b13b-1d492c2ddbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530231468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1530231468
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3873072469
Short name T310
Test name
Test status
Simulation time 54350473 ps
CPU time 0.8 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 199212 kb
Host smart-8acf9f07-2d3d-4856-8b08-fcee7bf119b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873072469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3873072469
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3707304453
Short name T261
Test name
Test status
Simulation time 29621610 ps
CPU time 0.67 seconds
Started Aug 01 06:31:02 PM PDT 24
Finished Aug 01 06:31:03 PM PDT 24
Peak memory 198052 kb
Host smart-024eff98-c6b1-4c0a-9aa4-1f606e7b6395
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707304453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3707304453
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3401158615
Short name T595
Test name
Test status
Simulation time 162758697 ps
CPU time 1.01 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 198120 kb
Host smart-ddc47645-62c8-4778-a8d6-cf9bed2001ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401158615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3401158615
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.548832417
Short name T442
Test name
Test status
Simulation time 64245384 ps
CPU time 0.59 seconds
Started Aug 01 06:31:06 PM PDT 24
Finished Aug 01 06:31:06 PM PDT 24
Peak memory 198020 kb
Host smart-d523ddac-0669-42fd-b0fb-0c86e19c57c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548832417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.548832417
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.1485771474
Short name T532
Test name
Test status
Simulation time 49337906 ps
CPU time 0.61 seconds
Started Aug 01 06:31:08 PM PDT 24
Finished Aug 01 06:31:09 PM PDT 24
Peak memory 198100 kb
Host smart-6c4033a9-2fe7-422f-8927-4540de3b77e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485771474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1485771474
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.1177628459
Short name T501
Test name
Test status
Simulation time 96735009 ps
CPU time 1.03 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 198360 kb
Host smart-6fecd805-a926-40c9-98c5-211b4883713a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177628459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.1177628459
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3836325920
Short name T592
Test name
Test status
Simulation time 113407891 ps
CPU time 0.87 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 209560 kb
Host smart-517c28ef-54cf-4784-9d39-93ccc1ecc111
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836325920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3836325920
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1295364620
Short name T337
Test name
Test status
Simulation time 50408883 ps
CPU time 0.85 seconds
Started Aug 01 06:31:04 PM PDT 24
Finished Aug 01 06:31:05 PM PDT 24
Peak memory 198304 kb
Host smart-d68db297-47b9-4195-857c-17803fa52454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295364620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1295364620
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3223138944
Short name T52
Test name
Test status
Simulation time 31775304 ps
CPU time 0.78 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 199160 kb
Host smart-fc0ef375-c35f-4027-8b82-d86569140589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223138944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3223138944
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.482474562
Short name T594
Test name
Test status
Simulation time 57284356 ps
CPU time 0.8 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 199180 kb
Host smart-17f2b9f5-3169-4cff-9d87-e545bf9e8718
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482474562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.482474562
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1598102388
Short name T125
Test name
Test status
Simulation time 32561890 ps
CPU time 0.62 seconds
Started Aug 01 06:31:11 PM PDT 24
Finished Aug 01 06:31:11 PM PDT 24
Peak memory 197292 kb
Host smart-4c1ac919-b0ea-4cfe-8d85-3232571a148d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598102388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1598102388
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.599948261
Short name T526
Test name
Test status
Simulation time 306150251 ps
CPU time 0.98 seconds
Started Aug 01 06:31:13 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 198124 kb
Host smart-010f2523-2644-4521-8168-86c75f64f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599948261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.599948261
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3717122566
Short name T553
Test name
Test status
Simulation time 36405986 ps
CPU time 0.64 seconds
Started Aug 01 06:31:10 PM PDT 24
Finished Aug 01 06:31:11 PM PDT 24
Peak memory 198028 kb
Host smart-dac6b0d3-ecee-4924-8170-ab8f1ebfc61c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717122566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3717122566
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.104301063
Short name T405
Test name
Test status
Simulation time 65212870 ps
CPU time 0.59 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 198332 kb
Host smart-db840e5f-c45b-4eb0-9c12-9577ec878758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104301063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.104301063
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2120580317
Short name T164
Test name
Test status
Simulation time 83426213 ps
CPU time 0.71 seconds
Started Aug 01 06:31:11 PM PDT 24
Finished Aug 01 06:31:11 PM PDT 24
Peak memory 201400 kb
Host smart-3fb47224-7b22-4cce-9a14-1ffd5a5da556
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120580317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2120580317
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.914985729
Short name T359
Test name
Test status
Simulation time 58961945 ps
CPU time 0.82 seconds
Started Aug 01 06:31:12 PM PDT 24
Finished Aug 01 06:31:13 PM PDT 24
Peak memory 199116 kb
Host smart-82485fb5-875c-4378-a79f-1f3ef0702077
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914985729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.914985729
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.524681019
Short name T231
Test name
Test status
Simulation time 412472619 ps
CPU time 0.77 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 209532 kb
Host smart-227f0c4d-227c-4ebf-b91a-717fa00f4ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524681019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.524681019
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.336736092
Short name T395
Test name
Test status
Simulation time 66043354 ps
CPU time 0.95 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 199312 kb
Host smart-89a3ae01-5148-4856-8514-c88fc70ede4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336736092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_
mubi.336736092
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.2649059384
Short name T271
Test name
Test status
Simulation time 144742250 ps
CPU time 0.63 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 198540 kb
Host smart-911ee54c-5de1-4f88-a060-2bfd56a0b748
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649059384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.2649059384
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2125416952
Short name T535
Test name
Test status
Simulation time 89418526 ps
CPU time 0.83 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:16 PM PDT 24
Peak memory 198916 kb
Host smart-0e9775d8-1a22-4d69-ab54-bf20f296aa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125416952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2125416952
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1804484421
Short name T437
Test name
Test status
Simulation time 31031848 ps
CPU time 0.66 seconds
Started Aug 01 06:31:18 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 198084 kb
Host smart-f5171838-9cc4-4116-9c04-5ba96ac65ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804484421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1804484421
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.1220043980
Short name T487
Test name
Test status
Simulation time 157994462 ps
CPU time 1.01 seconds
Started Aug 01 06:31:20 PM PDT 24
Finished Aug 01 06:31:21 PM PDT 24
Peak memory 198084 kb
Host smart-2f8732ed-b929-4044-9950-6905f7ab27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220043980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1220043980
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1485501288
Short name T375
Test name
Test status
Simulation time 49222646 ps
CPU time 0.63 seconds
Started Aug 01 06:31:16 PM PDT 24
Finished Aug 01 06:31:17 PM PDT 24
Peak memory 198080 kb
Host smart-6966005a-f727-42af-bf80-2430e73ae342
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485501288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1485501288
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1522371522
Short name T352
Test name
Test status
Simulation time 61373761 ps
CPU time 0.58 seconds
Started Aug 01 06:31:12 PM PDT 24
Finished Aug 01 06:31:13 PM PDT 24
Peak memory 198092 kb
Host smart-47e6c43e-5960-443b-a285-2879015d02aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522371522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1522371522
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.384174799
Short name T599
Test name
Test status
Simulation time 226735532 ps
CPU time 0.67 seconds
Started Aug 01 06:31:15 PM PDT 24
Finished Aug 01 06:31:16 PM PDT 24
Peak memory 201656 kb
Host smart-4e71a041-b18a-4cc0-9e13-2a385d683ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384174799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.384174799
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.410130501
Short name T430
Test name
Test status
Simulation time 107346824 ps
CPU time 0.71 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 199196 kb
Host smart-f6b5794a-38e9-490c-a558-f8dcb608df8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410130501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.410130501
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2968248594
Short name T346
Test name
Test status
Simulation time 482560398 ps
CPU time 0.84 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 209496 kb
Host smart-09ff7069-efd5-4789-9227-4d8555cf0ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968248594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2968248594
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3745298975
Short name T398
Test name
Test status
Simulation time 74326288 ps
CPU time 0.81 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 198128 kb
Host smart-28d291b4-943c-4947-9a33-188febadd06e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745298975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3745298975
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.200522884
Short name T77
Test name
Test status
Simulation time 62322479 ps
CPU time 0.63 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 199388 kb
Host smart-9763eaa1-f987-4407-8c89-38cebd91791d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200522884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.200522884
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.940126465
Short name T412
Test name
Test status
Simulation time 59526626 ps
CPU time 0.81 seconds
Started Aug 01 06:31:20 PM PDT 24
Finished Aug 01 06:31:21 PM PDT 24
Peak memory 200076 kb
Host smart-5264850e-1311-4dba-a3cc-7574e6022a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940126465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.940126465
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2577734261
Short name T143
Test name
Test status
Simulation time 67422348 ps
CPU time 0.72 seconds
Started Aug 01 06:31:15 PM PDT 24
Finished Aug 01 06:31:16 PM PDT 24
Peak memory 198460 kb
Host smart-ad20be68-f29b-488e-8a34-a92643c30171
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577734261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2577734261
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3113008625
Short name T613
Test name
Test status
Simulation time 30046353 ps
CPU time 0.64 seconds
Started Aug 01 06:31:15 PM PDT 24
Finished Aug 01 06:31:16 PM PDT 24
Peak memory 197980 kb
Host smart-11994c33-10d1-4afd-8f7a-fc0774d2031e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113008625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3113008625
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2495233305
Short name T400
Test name
Test status
Simulation time 158075887 ps
CPU time 1.04 seconds
Started Aug 01 06:31:19 PM PDT 24
Finished Aug 01 06:31:20 PM PDT 24
Peak memory 198388 kb
Host smart-5be2837e-3681-4bd7-8134-e88f7178ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495233305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2495233305
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2780279849
Short name T340
Test name
Test status
Simulation time 76015889 ps
CPU time 0.64 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 198120 kb
Host smart-89e6455f-7138-4a02-8cdb-2cbad893c9ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780279849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2780279849
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3605206728
Short name T213
Test name
Test status
Simulation time 24048383 ps
CPU time 0.61 seconds
Started Aug 01 06:31:14 PM PDT 24
Finished Aug 01 06:31:15 PM PDT 24
Peak memory 198088 kb
Host smart-a464d90f-5335-4e7d-9d96-4069f51a07d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605206728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3605206728
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1437357597
Short name T153
Test name
Test status
Simulation time 41214664 ps
CPU time 0.73 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 201424 kb
Host smart-e01ec8e1-0214-4668-a5fb-8ab2d869a470
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437357597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1437357597
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.715270719
Short name T544
Test name
Test status
Simulation time 93302273 ps
CPU time 0.71 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 198348 kb
Host smart-63f2c4ac-5163-4b51-9103-5668fc967849
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715270719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.715270719
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.3374676885
Short name T207
Test name
Test status
Simulation time 115408374 ps
CPU time 0.91 seconds
Started Aug 01 06:31:13 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 209396 kb
Host smart-225b547d-b1f0-4ebd-a56a-a99946fdd2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374676885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3374676885
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.4184847693
Short name T604
Test name
Test status
Simulation time 90573705 ps
CPU time 0.73 seconds
Started Aug 01 06:31:19 PM PDT 24
Finished Aug 01 06:31:20 PM PDT 24
Peak memory 198060 kb
Host smart-ff861266-2d07-4b29-9244-bbe32bdb1285
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184847693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4184847693
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.1431806077
Short name T471
Test name
Test status
Simulation time 29787781 ps
CPU time 0.72 seconds
Started Aug 01 06:31:13 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 199380 kb
Host smart-61a47a0e-504a-4cea-af6f-0eb87f387386
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431806077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1431806077
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2036272694
Short name T178
Test name
Test status
Simulation time 35164171 ps
CPU time 1.01 seconds
Started Aug 01 06:31:13 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 200940 kb
Host smart-500eda8a-627f-46d5-b26b-8e138b2bc2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036272694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2036272694
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3791539146
Short name T445
Test name
Test status
Simulation time 124476028 ps
CPU time 0.63 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 198464 kb
Host smart-7d30cfa8-f721-446e-876a-4f34256f54aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791539146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3791539146
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1041493444
Short name T357
Test name
Test status
Simulation time 30253742 ps
CPU time 0.65 seconds
Started Aug 01 06:31:22 PM PDT 24
Finished Aug 01 06:31:23 PM PDT 24
Peak memory 198004 kb
Host smart-731da57e-d93b-4161-8053-11a9b0f421d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041493444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1041493444
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.896425000
Short name T590
Test name
Test status
Simulation time 606288578 ps
CPU time 0.99 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:28 PM PDT 24
Peak memory 198136 kb
Host smart-ab697ff4-251b-4902-9cca-d54f6883243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896425000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.896425000
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.26869400
Short name T341
Test name
Test status
Simulation time 214028460 ps
CPU time 0.62 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 198128 kb
Host smart-8edced8f-b1cc-4516-9fa2-bd26399e470f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26869400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.26869400
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2034604239
Short name T282
Test name
Test status
Simulation time 42542788 ps
CPU time 0.66 seconds
Started Aug 01 06:31:22 PM PDT 24
Finished Aug 01 06:31:23 PM PDT 24
Peak memory 198040 kb
Host smart-9778393e-d3e0-415d-bd47-4ed927c67156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034604239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2034604239
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2229700152
Short name T171
Test name
Test status
Simulation time 49419357 ps
CPU time 0.71 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 201372 kb
Host smart-45aa05b3-52c4-4229-9264-d6744e99d030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229700152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2229700152
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.453847020
Short name T527
Test name
Test status
Simulation time 108633040 ps
CPU time 0.69 seconds
Started Aug 01 06:31:17 PM PDT 24
Finished Aug 01 06:31:17 PM PDT 24
Peak memory 198400 kb
Host smart-826fb3c1-d41a-44fb-8934-0b86434a2237
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453847020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.453847020
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.4199163834
Short name T426
Test name
Test status
Simulation time 181354653 ps
CPU time 0.78 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 209400 kb
Host smart-fe4c89d2-5709-49df-9d04-c92a6029ce85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199163834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.4199163834
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2424161798
Short name T203
Test name
Test status
Simulation time 56787668 ps
CPU time 0.86 seconds
Started Aug 01 06:31:21 PM PDT 24
Finished Aug 01 06:31:22 PM PDT 24
Peak memory 198096 kb
Host smart-e9d9d71f-8495-419a-865f-e824097642e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424161798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2424161798
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.551975639
Short name T322
Test name
Test status
Simulation time 31379821 ps
CPU time 0.69 seconds
Started Aug 01 06:31:20 PM PDT 24
Finished Aug 01 06:31:21 PM PDT 24
Peak memory 198532 kb
Host smart-3daf8a0a-3792-4ac1-8e32-a3968904754a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551975639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.551975639
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3909495073
Short name T480
Test name
Test status
Simulation time 68073703 ps
CPU time 0.7 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198688 kb
Host smart-4c659c29-18e3-44e8-890c-a0bead490273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909495073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3909495073
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.376156708
Short name T308
Test name
Test status
Simulation time 29192524 ps
CPU time 0.64 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 198068 kb
Host smart-1b5e44f4-cd88-43ad-9ef5-c02a16e194d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376156708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.376156708
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2232362110
Short name T460
Test name
Test status
Simulation time 652211801 ps
CPU time 0.98 seconds
Started Aug 01 06:31:22 PM PDT 24
Finished Aug 01 06:31:23 PM PDT 24
Peak memory 198392 kb
Host smart-be4170d6-2568-49b3-8e19-691c0ba39f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232362110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2232362110
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.4012156192
Short name T267
Test name
Test status
Simulation time 53762760 ps
CPU time 0.63 seconds
Started Aug 01 06:31:30 PM PDT 24
Finished Aug 01 06:31:31 PM PDT 24
Peak memory 198088 kb
Host smart-a8a0730a-1526-45a2-a9ae-71d00a46e245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012156192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.4012156192
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.232398122
Short name T484
Test name
Test status
Simulation time 54976536 ps
CPU time 0.62 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 198092 kb
Host smart-717defdb-f450-4abc-9f94-221eaf2bc8a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232398122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.232398122
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1622416642
Short name T529
Test name
Test status
Simulation time 82656080 ps
CPU time 0.68 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 201292 kb
Host smart-9a1d76f7-b7e7-4b29-a7b7-a33f93d34c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622416642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.1622416642
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.4134810413
Short name T538
Test name
Test status
Simulation time 72407617 ps
CPU time 0.69 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 198212 kb
Host smart-479dd396-37fb-4954-bfd5-de054c1417fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134810413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.4134810413
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1983687418
Short name T371
Test name
Test status
Simulation time 149321857 ps
CPU time 0.86 seconds
Started Aug 01 06:31:29 PM PDT 24
Finished Aug 01 06:31:31 PM PDT 24
Peak memory 209460 kb
Host smart-3d1bb2d8-2f68-4e46-a94e-747ded30174f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983687418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1983687418
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1613194314
Short name T10
Test name
Test status
Simulation time 62557460 ps
CPU time 0.83 seconds
Started Aug 01 06:31:27 PM PDT 24
Finished Aug 01 06:31:28 PM PDT 24
Peak memory 198188 kb
Host smart-3a4b9fcb-4f82-479e-85fc-d7910a13fbec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613194314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1613194314
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.3526154500
Short name T461
Test name
Test status
Simulation time 30162860 ps
CPU time 0.7 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 199384 kb
Host smart-1cdba449-c0e0-4cbc-a17d-fa2cd50113d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526154500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3526154500
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.408635409
Short name T521
Test name
Test status
Simulation time 81331360 ps
CPU time 0.76 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 198860 kb
Host smart-43054320-7d3b-42f8-9312-27209deaf0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408635409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.408635409
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1256422240
Short name T145
Test name
Test status
Simulation time 66255695 ps
CPU time 0.68 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 198532 kb
Host smart-13e63adf-8483-40f6-a2b3-fd473d2b72ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256422240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1256422240
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2946882202
Short name T624
Test name
Test status
Simulation time 29312411 ps
CPU time 0.63 seconds
Started Aug 01 06:31:30 PM PDT 24
Finished Aug 01 06:31:31 PM PDT 24
Peak memory 198032 kb
Host smart-d2e4fe7a-5793-4512-a9c5-25837baebeee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946882202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2946882202
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.1023551792
Short name T238
Test name
Test status
Simulation time 602744838 ps
CPU time 0.97 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 198176 kb
Host smart-dcc82360-b9eb-453b-92ea-2b6f81295e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023551792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1023551792
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3879757912
Short name T506
Test name
Test status
Simulation time 63408160 ps
CPU time 0.69 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 198084 kb
Host smart-19247429-736d-4031-8e1b-4c6b337b049e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879757912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3879757912
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2189951103
Short name T588
Test name
Test status
Simulation time 33551379 ps
CPU time 0.61 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 198352 kb
Host smart-21bf6943-fae1-4e70-b4df-db4faab56ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189951103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2189951103
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1148564126
Short name T476
Test name
Test status
Simulation time 75086432 ps
CPU time 0.66 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 201344 kb
Host smart-3309e18e-cf59-41eb-bb44-d500206a800d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148564126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1148564126
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2306193366
Short name T336
Test name
Test status
Simulation time 50770293 ps
CPU time 0.72 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 199204 kb
Host smart-94b0d443-1100-4f73-bb67-961785397d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306193366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2306193366
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.661607935
Short name T283
Test name
Test status
Simulation time 125142619 ps
CPU time 0.88 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 209504 kb
Host smart-8731f02a-7f0e-4001-a4df-772e4ccce587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661607935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.661607935
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3542516119
Short name T516
Test name
Test status
Simulation time 86970162 ps
CPU time 0.68 seconds
Started Aug 01 06:31:22 PM PDT 24
Finished Aug 01 06:31:23 PM PDT 24
Peak memory 198140 kb
Host smart-a4a42a1d-de73-469e-a24e-bba390c5c743
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542516119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3542516119
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.106360144
Short name T572
Test name
Test status
Simulation time 28833587 ps
CPU time 0.72 seconds
Started Aug 01 06:31:23 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 198580 kb
Host smart-754aa50d-d611-4684-8245-4c6e96646987
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106360144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.106360144
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.1273880602
Short name T91
Test name
Test status
Simulation time 21139131 ps
CPU time 0.69 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 199196 kb
Host smart-4a2715d0-e495-4a39-ac42-391dfa251592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273880602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1273880602
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2254399989
Short name T28
Test name
Test status
Simulation time 65431324 ps
CPU time 0.73 seconds
Started Aug 01 06:31:29 PM PDT 24
Finished Aug 01 06:31:30 PM PDT 24
Peak memory 198504 kb
Host smart-4979417e-435e-4209-bac4-29d07acfa759
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254399989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2254399989
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2782667445
Short name T608
Test name
Test status
Simulation time 48592451 ps
CPU time 0.6 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:28 PM PDT 24
Peak memory 198068 kb
Host smart-f9e275f5-bf5e-44f5-94e2-ec0bd572771c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782667445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.2782667445
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.240221010
Short name T250
Test name
Test status
Simulation time 631638048 ps
CPU time 0.99 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198344 kb
Host smart-ec8cce04-2cb8-40f6-97e8-e2b112c48157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240221010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.240221010
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2516737284
Short name T224
Test name
Test status
Simulation time 106778600 ps
CPU time 0.61 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198052 kb
Host smart-e759ef82-38a5-47e5-830b-86fad7e6d700
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516737284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2516737284
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2030047212
Short name T265
Test name
Test status
Simulation time 180458433 ps
CPU time 0.62 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198140 kb
Host smart-21195253-29a5-451b-9303-016d5d7381aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030047212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2030047212
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1684367270
Short name T434
Test name
Test status
Simulation time 88095524 ps
CPU time 0.66 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 198944 kb
Host smart-1055f7c5-a6eb-46a3-916f-db55dc35ccb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684367270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1684367270
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.4291148662
Short name T421
Test name
Test status
Simulation time 147226540 ps
CPU time 0.82 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 209472 kb
Host smart-46d8e1fb-6935-4729-ab09-d7a693ec0d77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291148662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4291148662
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2771986624
Short name T546
Test name
Test status
Simulation time 102610612 ps
CPU time 0.71 seconds
Started Aug 01 06:31:25 PM PDT 24
Finished Aug 01 06:31:26 PM PDT 24
Peak memory 198120 kb
Host smart-3d9404ab-9893-4c68-b8a4-aacdee09c56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771986624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2771986624
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3463568096
Short name T49
Test name
Test status
Simulation time 53773516 ps
CPU time 0.62 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198472 kb
Host smart-bf7b7aea-ab6a-458a-b8cb-94fb2c4ebcf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463568096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3463568096
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.69569868
Short name T54
Test name
Test status
Simulation time 67084892 ps
CPU time 0.7 seconds
Started Aug 01 06:31:26 PM PDT 24
Finished Aug 01 06:31:27 PM PDT 24
Peak memory 198276 kb
Host smart-11c0ee45-b1a4-45dc-b593-467fb9ccd189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69569868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.69569868
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.860234601
Short name T473
Test name
Test status
Simulation time 72584477 ps
CPU time 0.69 seconds
Started Aug 01 06:31:29 PM PDT 24
Finished Aug 01 06:31:30 PM PDT 24
Peak memory 198760 kb
Host smart-97f03835-8732-4f3c-b80c-22705349453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860234601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.860234601
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1340736591
Short name T510
Test name
Test status
Simulation time 64626392 ps
CPU time 0.72 seconds
Started Aug 01 06:31:43 PM PDT 24
Finished Aug 01 06:31:44 PM PDT 24
Peak memory 198488 kb
Host smart-726ecb1f-04da-48a0-b6d8-e1777f4bdf94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340736591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.1340736591
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1192023270
Short name T126
Test name
Test status
Simulation time 38675691 ps
CPU time 0.57 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 198020 kb
Host smart-e8379302-97a8-44d2-b4cb-d0db1130151a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192023270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1192023270
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.1712544999
Short name T465
Test name
Test status
Simulation time 307775795 ps
CPU time 0.96 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198096 kb
Host smart-0c7a81cc-706f-4797-a350-47ffdcd046b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712544999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1712544999
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3119215825
Short name T602
Test name
Test status
Simulation time 55094448 ps
CPU time 0.7 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198036 kb
Host smart-1de08437-3b15-4595-b6b8-2443e6051160
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119215825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3119215825
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2785016521
Short name T273
Test name
Test status
Simulation time 46012420 ps
CPU time 0.66 seconds
Started Aug 01 06:31:32 PM PDT 24
Finished Aug 01 06:31:33 PM PDT 24
Peak memory 198124 kb
Host smart-e4a8ed66-8002-4fe5-aae9-2bc5ea574252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785016521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2785016521
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3148335715
Short name T362
Test name
Test status
Simulation time 81393196 ps
CPU time 0.66 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 201440 kb
Host smart-a879d677-40c3-440b-8779-c167605d0557
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148335715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3148335715
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3460887792
Short name T622
Test name
Test status
Simulation time 130739684 ps
CPU time 0.72 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 198284 kb
Host smart-ec4c035d-efac-4cd9-bb92-030e331c5151
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460887792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3460887792
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.2412750945
Short name T470
Test name
Test status
Simulation time 153562293 ps
CPU time 0.81 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 209472 kb
Host smart-9c619643-a04b-4b3a-8335-865e07bdfb73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412750945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.2412750945
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2058324595
Short name T533
Test name
Test status
Simulation time 51463195 ps
CPU time 0.76 seconds
Started Aug 01 06:31:24 PM PDT 24
Finished Aug 01 06:31:25 PM PDT 24
Peak memory 198132 kb
Host smart-af590144-46cc-4132-a573-bec988d1283e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058324595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2058324595
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.1535736757
Short name T404
Test name
Test status
Simulation time 31977650 ps
CPU time 0.71 seconds
Started Aug 01 06:31:28 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 199400 kb
Host smart-22503aa3-e800-4580-a862-3c8d7ef698ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535736757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1535736757
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1226121979
Short name T417
Test name
Test status
Simulation time 90159920 ps
CPU time 0.8 seconds
Started Aug 01 06:31:42 PM PDT 24
Finished Aug 01 06:31:43 PM PDT 24
Peak memory 200140 kb
Host smart-d7a90d1b-33ce-4212-9c7f-8ceec99ac70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226121979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1226121979
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1680232017
Short name T317
Test name
Test status
Simulation time 52457433 ps
CPU time 0.81 seconds
Started Aug 01 06:31:37 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 199204 kb
Host smart-ae437bee-81c3-4459-a64a-241b4a3b5bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680232017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.1680232017
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3321341663
Short name T481
Test name
Test status
Simulation time 31792021 ps
CPU time 0.62 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 198028 kb
Host smart-c6de4f7a-c69c-4fcb-ab32-69f3477b2cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321341663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3321341663
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.347088111
Short name T486
Test name
Test status
Simulation time 318345101 ps
CPU time 1.02 seconds
Started Aug 01 06:31:42 PM PDT 24
Finished Aug 01 06:31:43 PM PDT 24
Peak memory 198096 kb
Host smart-9446c6ed-df2f-4a94-850e-f1833767ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347088111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.347088111
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3656127945
Short name T6
Test name
Test status
Simulation time 33722270 ps
CPU time 0.58 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 198080 kb
Host smart-3098c164-88cf-4035-bf7f-76fc248f0bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656127945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3656127945
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2131679782
Short name T382
Test name
Test status
Simulation time 91470279 ps
CPU time 0.61 seconds
Started Aug 01 06:31:40 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 198124 kb
Host smart-2e3309be-2f50-45aa-8bd4-719c9c2f998f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131679782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2131679782
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2265531494
Short name T184
Test name
Test status
Simulation time 48172630 ps
CPU time 0.73 seconds
Started Aug 01 06:31:35 PM PDT 24
Finished Aug 01 06:31:36 PM PDT 24
Peak memory 201340 kb
Host smart-931bd35c-63c2-4c8c-9dd8-abd9a7062de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265531494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2265531494
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.3347039123
Short name T571
Test name
Test status
Simulation time 70581477 ps
CPU time 0.75 seconds
Started Aug 01 06:31:40 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 199144 kb
Host smart-02c8e94d-4827-474b-8037-b44418569d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347039123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3347039123
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.4106160404
Short name T469
Test name
Test status
Simulation time 117631335 ps
CPU time 0.82 seconds
Started Aug 01 06:31:37 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 209540 kb
Host smart-78677489-da04-4404-b0b5-c7de4513935c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106160404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.4106160404
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.435601519
Short name T344
Test name
Test status
Simulation time 87193409 ps
CPU time 0.81 seconds
Started Aug 01 06:31:37 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 199212 kb
Host smart-21695f61-3307-49e0-9ab1-3861978fd418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435601519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.435601519
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2800026978
Short name T353
Test name
Test status
Simulation time 29755629 ps
CPU time 0.66 seconds
Started Aug 01 06:31:38 PM PDT 24
Finished Aug 01 06:31:39 PM PDT 24
Peak memory 198512 kb
Host smart-155cc606-3fc8-4932-bc59-e7a0ab60f327
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800026978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2800026978
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.1375644536
Short name T95
Test name
Test status
Simulation time 33044047 ps
CPU time 1.08 seconds
Started Aug 01 06:29:41 PM PDT 24
Finished Aug 01 06:29:42 PM PDT 24
Peak memory 200916 kb
Host smart-2b14355e-805e-4333-b348-9d884f1daff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375644536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1375644536
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2429781620
Short name T459
Test name
Test status
Simulation time 67999157 ps
CPU time 0.82 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 198548 kb
Host smart-555a9018-2042-4eba-ad3e-55a7bbf31656
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429781620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.2429781620
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3683016597
Short name T278
Test name
Test status
Simulation time 29053295 ps
CPU time 0.65 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 198000 kb
Host smart-1c7f138b-c008-49ac-bd8d-b2a55630b3a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683016597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3683016597
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1277029409
Short name T431
Test name
Test status
Simulation time 566730576 ps
CPU time 0.96 seconds
Started Aug 01 06:29:40 PM PDT 24
Finished Aug 01 06:29:42 PM PDT 24
Peak memory 198096 kb
Host smart-3ab35a25-c1d5-48fb-bf30-814cb86d08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277029409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1277029409
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2942763859
Short name T304
Test name
Test status
Simulation time 116694994 ps
CPU time 0.6 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 198156 kb
Host smart-5ae4407b-1418-4f4a-ba0a-7936a90ee327
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942763859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2942763859
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2788234596
Short name T239
Test name
Test status
Simulation time 23210851 ps
CPU time 0.63 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 198428 kb
Host smart-97b7f33a-29b8-4e56-ab27-238ea8547305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788234596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2788234596
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2016359830
Short name T148
Test name
Test status
Simulation time 96433423 ps
CPU time 0.68 seconds
Started Aug 01 06:29:48 PM PDT 24
Finished Aug 01 06:29:49 PM PDT 24
Peak memory 201364 kb
Host smart-01e495e9-8164-405a-b70f-adba2424fd2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016359830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2016359830
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1716278667
Short name T255
Test name
Test status
Simulation time 82483607 ps
CPU time 0.77 seconds
Started Aug 01 06:29:41 PM PDT 24
Finished Aug 01 06:29:42 PM PDT 24
Peak memory 198328 kb
Host smart-a3981925-d74d-4c07-8848-73d5ef9aba7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716278667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1716278667
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.4209052276
Short name T206
Test name
Test status
Simulation time 174897550 ps
CPU time 0.83 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 209552 kb
Host smart-d9f40f16-09f5-449a-aaf6-c3bb071f2afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209052276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.4209052276
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.147362582
Short name T32
Test name
Test status
Simulation time 948996111 ps
CPU time 1.45 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 217996 kb
Host smart-579191d9-3e8d-4d37-a99d-38e6b5e967b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147362582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.147362582
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1183052020
Short name T87
Test name
Test status
Simulation time 54945753 ps
CPU time 0.79 seconds
Started Aug 01 06:29:39 PM PDT 24
Finished Aug 01 06:29:40 PM PDT 24
Peak memory 198176 kb
Host smart-391eb380-e42d-4cfd-a179-889392faf55b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183052020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1183052020
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.3825186323
Short name T545
Test name
Test status
Simulation time 126220754 ps
CPU time 0.64 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 198512 kb
Host smart-9c8d1ee1-34b2-454f-82f4-c83679f92699
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825186323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3825186323
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.47886617
Short name T563
Test name
Test status
Simulation time 60277106 ps
CPU time 0.82 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 200208 kb
Host smart-b71faca6-5df6-4991-8fc8-f79d266394a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47886617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.47886617
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2022928574
Short name T193
Test name
Test status
Simulation time 61071416 ps
CPU time 0.71 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 198300 kb
Host smart-fdb3a38b-e1cd-4d4a-87fb-fbe1cec92c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022928574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2022928574
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.86154898
Short name T614
Test name
Test status
Simulation time 29831725 ps
CPU time 0.63 seconds
Started Aug 01 06:31:39 PM PDT 24
Finished Aug 01 06:31:40 PM PDT 24
Peak memory 198020 kb
Host smart-4d094a2a-7781-4ccd-b9db-2c181005d42b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86154898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_m
alfunc.86154898
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3629890947
Short name T435
Test name
Test status
Simulation time 600033218 ps
CPU time 0.97 seconds
Started Aug 01 06:31:40 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 198116 kb
Host smart-dfc6d837-0dec-45e2-a378-27bd76ba6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629890947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3629890947
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1501157560
Short name T354
Test name
Test status
Simulation time 70656755 ps
CPU time 0.64 seconds
Started Aug 01 06:31:44 PM PDT 24
Finished Aug 01 06:31:44 PM PDT 24
Peak memory 197452 kb
Host smart-6dd90274-0a5e-4234-a15c-adf5397b0514
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501157560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1501157560
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.1621935815
Short name T253
Test name
Test status
Simulation time 60473851 ps
CPU time 0.59 seconds
Started Aug 01 06:31:35 PM PDT 24
Finished Aug 01 06:31:36 PM PDT 24
Peak memory 198108 kb
Host smart-8afe28e7-8b0c-439f-ba6a-ae0656931ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621935815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1621935815
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2520286169
Short name T149
Test name
Test status
Simulation time 44083709 ps
CPU time 0.84 seconds
Started Aug 01 06:31:51 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 201472 kb
Host smart-fb1cb2ad-48b4-4ff4-88c4-f8ad54b01e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520286169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2520286169
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3358956155
Short name T198
Test name
Test status
Simulation time 89086129 ps
CPU time 0.93 seconds
Started Aug 01 06:31:35 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 198388 kb
Host smart-cea9406b-6fa1-4e7f-a59f-093fe1126e2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358956155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3358956155
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.479684862
Short name T358
Test name
Test status
Simulation time 111034135 ps
CPU time 0.94 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 209516 kb
Host smart-952ee607-00e5-488b-8f7f-d223e09f185b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479684862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.479684862
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2956402517
Short name T397
Test name
Test status
Simulation time 61300046 ps
CPU time 0.81 seconds
Started Aug 01 06:31:42 PM PDT 24
Finished Aug 01 06:31:43 PM PDT 24
Peak memory 198136 kb
Host smart-21e1f24b-cfad-4e39-b9e2-7406f07984e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956402517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2956402517
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2664746028
Short name T549
Test name
Test status
Simulation time 54339288 ps
CPU time 0.63 seconds
Started Aug 01 06:31:42 PM PDT 24
Finished Aug 01 06:31:43 PM PDT 24
Peak memory 198532 kb
Host smart-708f4898-1203-477d-b85c-1dad4fcf6fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664746028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2664746028
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2542641559
Short name T477
Test name
Test status
Simulation time 144259771 ps
CPU time 0.89 seconds
Started Aug 01 06:31:39 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 200312 kb
Host smart-8f279c61-8080-468c-83e6-d482d80df860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542641559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2542641559
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1352425903
Short name T548
Test name
Test status
Simulation time 68984847 ps
CPU time 0.76 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 198516 kb
Host smart-c7510865-459c-4d57-884d-8446f07f6635
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352425903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1352425903
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2187540155
Short name T620
Test name
Test status
Simulation time 33165920 ps
CPU time 0.61 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 198120 kb
Host smart-df19084b-a58c-42e4-b04e-995748379ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187540155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2187540155
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2597707370
Short name T236
Test name
Test status
Simulation time 160261977 ps
CPU time 1.05 seconds
Started Aug 01 06:31:40 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 198040 kb
Host smart-a3508644-2e00-4f3a-9a75-744747a32f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597707370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2597707370
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.2761253569
Short name T464
Test name
Test status
Simulation time 49112952 ps
CPU time 0.63 seconds
Started Aug 01 06:31:40 PM PDT 24
Finished Aug 01 06:31:40 PM PDT 24
Peak memory 198080 kb
Host smart-2537f87f-7328-41de-8e53-be2830c925d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761253569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2761253569
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1874110962
Short name T219
Test name
Test status
Simulation time 66884049 ps
CPU time 0.59 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 198092 kb
Host smart-8a3cecf7-7d30-4719-83a7-fec7ea770a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874110962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1874110962
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2675123412
Short name T573
Test name
Test status
Simulation time 55099603 ps
CPU time 0.72 seconds
Started Aug 01 06:31:41 PM PDT 24
Finished Aug 01 06:31:42 PM PDT 24
Peak memory 201436 kb
Host smart-ce20406b-fae8-46e5-a43f-514b75bc2df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675123412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2675123412
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.877895753
Short name T441
Test name
Test status
Simulation time 362437463 ps
CPU time 0.72 seconds
Started Aug 01 06:31:42 PM PDT 24
Finished Aug 01 06:31:43 PM PDT 24
Peak memory 198472 kb
Host smart-b43f6d42-5e44-492c-b4f8-8fe78391eed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877895753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.877895753
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1160159862
Short name T201
Test name
Test status
Simulation time 167215371 ps
CPU time 0.81 seconds
Started Aug 01 06:31:37 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 209500 kb
Host smart-e9bbc636-8a19-4155-9c0d-6d6acc66778d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160159862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1160159862
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2528829648
Short name T387
Test name
Test status
Simulation time 52772401 ps
CPU time 0.8 seconds
Started Aug 01 06:31:37 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 198068 kb
Host smart-3ab19cbb-1ed8-4da8-a383-a04269416ba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528829648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2528829648
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.45043515
Short name T356
Test name
Test status
Simulation time 68955859 ps
CPU time 0.63 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:37 PM PDT 24
Peak memory 198444 kb
Host smart-22030049-7f22-46cd-b27d-c55fe31651d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45043515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.45043515
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.2312187949
Short name T542
Test name
Test status
Simulation time 27186975 ps
CPU time 0.71 seconds
Started Aug 01 06:31:51 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 198732 kb
Host smart-5a230052-1e55-4358-8d9e-27ad67e0f2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312187949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2312187949
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.457074128
Short name T27
Test name
Test status
Simulation time 51092120 ps
CPU time 0.79 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 199208 kb
Host smart-abbc1278-7134-48bb-95fa-2850dafc0885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457074128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.457074128
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1705119659
Short name T593
Test name
Test status
Simulation time 30402252 ps
CPU time 0.65 seconds
Started Aug 01 06:31:47 PM PDT 24
Finished Aug 01 06:31:47 PM PDT 24
Peak memory 197928 kb
Host smart-76a31e02-dc3d-4c35-a12e-1fc395e426e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705119659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.1705119659
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1444394146
Short name T11
Test name
Test status
Simulation time 167097760 ps
CPU time 0.96 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 198348 kb
Host smart-d93b652e-870c-4fcf-adb9-b8ba3ed659b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444394146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1444394146
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.4025086551
Short name T570
Test name
Test status
Simulation time 75940401 ps
CPU time 0.65 seconds
Started Aug 01 06:31:44 PM PDT 24
Finished Aug 01 06:31:45 PM PDT 24
Peak memory 198088 kb
Host smart-1fcf0f4d-3e94-4427-bb5e-0eecaa4ab7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025086551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.4025086551
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.932516345
Short name T446
Test name
Test status
Simulation time 47226046 ps
CPU time 0.64 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 198044 kb
Host smart-26fa692a-b14f-4fab-9504-0952427e9b29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932516345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.932516345
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.840202651
Short name T579
Test name
Test status
Simulation time 39472656 ps
CPU time 0.72 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 201444 kb
Host smart-e6e32d2d-c47d-43fb-b35e-73b68f7e7e2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840202651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.840202651
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2353681020
Short name T575
Test name
Test status
Simulation time 96588735 ps
CPU time 0.79 seconds
Started Aug 01 06:31:36 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 199112 kb
Host smart-f2037d1d-ebe4-4433-b39a-c50360719ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353681020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2353681020
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2310308380
Short name T386
Test name
Test status
Simulation time 183241684 ps
CPU time 0.81 seconds
Started Aug 01 06:31:48 PM PDT 24
Finished Aug 01 06:31:49 PM PDT 24
Peak memory 209548 kb
Host smart-ae8446a9-aadf-49bf-b6e2-76ce50f06c16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310308380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2310308380
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.24716251
Short name T175
Test name
Test status
Simulation time 55171935 ps
CPU time 0.6 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 199168 kb
Host smart-7116ba2b-09f2-48ea-b125-ada06a6ce01d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24716251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm
_ctrl_config_regwen.24716251
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.3043252048
Short name T537
Test name
Test status
Simulation time 71969305 ps
CPU time 0.98 seconds
Started Aug 01 06:32:01 PM PDT 24
Finished Aug 01 06:32:03 PM PDT 24
Peak memory 199600 kb
Host smart-f328fc3a-1a52-4dab-ac26-be30be533765
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043252048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3043252048
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.2756234660
Short name T551
Test name
Test status
Simulation time 58300732 ps
CPU time 0.64 seconds
Started Aug 01 06:31:39 PM PDT 24
Finished Aug 01 06:31:40 PM PDT 24
Peak memory 199388 kb
Host smart-87d30c59-bab7-403b-9fdc-2edbe143a4e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756234660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2756234660
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.646515650
Short name T195
Test name
Test status
Simulation time 46343444 ps
CPU time 0.74 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 199216 kb
Host smart-cf544079-6908-48d2-940a-cc7be3be3c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646515650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.646515650
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.158791097
Short name T399
Test name
Test status
Simulation time 64257355 ps
CPU time 0.59 seconds
Started Aug 01 06:31:50 PM PDT 24
Finished Aug 01 06:31:51 PM PDT 24
Peak memory 198260 kb
Host smart-1af16a11-48ed-455b-921f-3ee5163fcd1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158791097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.158791097
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.582713251
Short name T384
Test name
Test status
Simulation time 3032966896 ps
CPU time 0.96 seconds
Started Aug 01 06:31:54 PM PDT 24
Finished Aug 01 06:31:55 PM PDT 24
Peak memory 198164 kb
Host smart-95d70e8e-1393-4155-b5c0-1ab646178179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582713251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.582713251
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2821856709
Short name T324
Test name
Test status
Simulation time 40637264 ps
CPU time 0.6 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 198068 kb
Host smart-1ef6d4d6-c099-4267-9b40-f6e0772e2fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821856709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2821856709
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.2000434441
Short name T30
Test name
Test status
Simulation time 86885587 ps
CPU time 0.61 seconds
Started Aug 01 06:31:57 PM PDT 24
Finished Aug 01 06:31:57 PM PDT 24
Peak memory 198408 kb
Host smart-ca174d17-9f42-455a-a055-ebce32c24740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000434441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2000434441
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.412732129
Short name T502
Test name
Test status
Simulation time 43464612 ps
CPU time 0.74 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 201396 kb
Host smart-29cd9b28-b48d-42c4-9adb-c245fc84d345
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412732129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.412732129
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1561533915
Short name T8
Test name
Test status
Simulation time 84573888 ps
CPU time 0.92 seconds
Started Aug 01 06:32:02 PM PDT 24
Finished Aug 01 06:32:03 PM PDT 24
Peak memory 199080 kb
Host smart-f1d78b79-1a51-4ff8-9238-40e40cb88ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561533915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1561533915
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3902807470
Short name T402
Test name
Test status
Simulation time 194296309 ps
CPU time 0.77 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 209436 kb
Host smart-094ee3aa-c4f4-442e-aba6-d399224d2fd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902807470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3902807470
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1595622693
Short name T202
Test name
Test status
Simulation time 53010067 ps
CPU time 0.91 seconds
Started Aug 01 06:31:45 PM PDT 24
Finished Aug 01 06:31:46 PM PDT 24
Peak memory 199312 kb
Host smart-35c95bb2-3ae4-4cd6-8dc2-a5f4786fbc28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595622693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1595622693
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.874836216
Short name T78
Test name
Test status
Simulation time 83038393 ps
CPU time 0.64 seconds
Started Aug 01 06:31:44 PM PDT 24
Finished Aug 01 06:31:45 PM PDT 24
Peak memory 198456 kb
Host smart-2e588617-eac4-4679-a160-912d863897e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874836216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.874836216
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.730397036
Short name T47
Test name
Test status
Simulation time 53842436 ps
CPU time 0.62 seconds
Started Aug 01 06:31:49 PM PDT 24
Finished Aug 01 06:31:50 PM PDT 24
Peak memory 198180 kb
Host smart-888aca8a-3e08-4687-a8b1-fea45ba84202
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730397036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.730397036
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.946057794
Short name T422
Test name
Test status
Simulation time 260677253 ps
CPU time 0.73 seconds
Started Aug 01 06:31:51 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 199916 kb
Host smart-22bce421-bb98-4456-bfa1-26f1adc5466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946057794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.946057794
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3123858354
Short name T194
Test name
Test status
Simulation time 52602570 ps
CPU time 0.74 seconds
Started Aug 01 06:31:46 PM PDT 24
Finished Aug 01 06:31:47 PM PDT 24
Peak memory 198592 kb
Host smart-ba2938ff-dfb3-4f71-89ff-060390f2c071
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123858354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3123858354
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1132446637
Short name T499
Test name
Test status
Simulation time 29841937 ps
CPU time 0.67 seconds
Started Aug 01 06:31:54 PM PDT 24
Finished Aug 01 06:31:55 PM PDT 24
Peak memory 198052 kb
Host smart-42bf340d-5b62-4c81-beee-2c3fa9881b52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132446637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1132446637
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2852968452
Short name T319
Test name
Test status
Simulation time 159145207 ps
CPU time 1.01 seconds
Started Aug 01 06:31:58 PM PDT 24
Finished Aug 01 06:31:59 PM PDT 24
Peak memory 198148 kb
Host smart-4584dbab-a552-4c20-9d4e-cda4813142d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852968452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2852968452
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1756685902
Short name T259
Test name
Test status
Simulation time 44140604 ps
CPU time 0.63 seconds
Started Aug 01 06:32:01 PM PDT 24
Finished Aug 01 06:32:02 PM PDT 24
Peak memory 198100 kb
Host smart-de1882ff-9a52-4e3f-be5e-dadfe758d00d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756685902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1756685902
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1278360362
Short name T615
Test name
Test status
Simulation time 49173746 ps
CPU time 0.58 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 198112 kb
Host smart-1187b4f9-b65f-4884-82d3-7ff2496953a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278360362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1278360362
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3228188544
Short name T368
Test name
Test status
Simulation time 76792275 ps
CPU time 0.6 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 198200 kb
Host smart-65a5ed82-b700-4fd9-bf27-6829f5e0b1f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228188544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3228188544
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3951360679
Short name T200
Test name
Test status
Simulation time 121181143 ps
CPU time 0.89 seconds
Started Aug 01 06:32:01 PM PDT 24
Finished Aug 01 06:32:02 PM PDT 24
Peak memory 209436 kb
Host smart-7e3a2300-16a5-4a5d-acff-6b1af98fa81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951360679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3951360679
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2029034922
Short name T293
Test name
Test status
Simulation time 73715010 ps
CPU time 0.77 seconds
Started Aug 01 06:31:51 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 198112 kb
Host smart-4a9e0212-9440-403c-9347-42c5314a4159
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029034922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2029034922
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1657087554
Short name T483
Test name
Test status
Simulation time 29924385 ps
CPU time 0.68 seconds
Started Aug 01 06:31:59 PM PDT 24
Finished Aug 01 06:32:00 PM PDT 24
Peak memory 199320 kb
Host smart-865d17e5-d67d-469e-9d5d-01a69dde83a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657087554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1657087554
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.213351985
Short name T525
Test name
Test status
Simulation time 107358922 ps
CPU time 0.62 seconds
Started Aug 01 06:31:46 PM PDT 24
Finished Aug 01 06:31:47 PM PDT 24
Peak memory 198580 kb
Host smart-96de6eb8-ff50-4b42-ba4b-a1ced11e277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213351985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.213351985
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.1573267999
Short name T339
Test name
Test status
Simulation time 58871252 ps
CPU time 0.81 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 199028 kb
Host smart-e117d0c2-75bb-46db-9819-ef8aadb992a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573267999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.1573267999
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1779149165
Short name T314
Test name
Test status
Simulation time 30257638 ps
CPU time 0.63 seconds
Started Aug 01 06:31:54 PM PDT 24
Finished Aug 01 06:31:55 PM PDT 24
Peak memory 198092 kb
Host smart-ceab32e4-bfea-459f-9d53-ff6fde9fd326
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779149165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.1779149165
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1939685582
Short name T541
Test name
Test status
Simulation time 183976071 ps
CPU time 0.98 seconds
Started Aug 01 06:31:51 PM PDT 24
Finished Aug 01 06:31:52 PM PDT 24
Peak memory 198108 kb
Host smart-99f7cc94-509d-4838-aa03-06bd4f88faf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939685582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1939685582
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2198884439
Short name T240
Test name
Test status
Simulation time 45182593 ps
CPU time 0.61 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 197988 kb
Host smart-bf318c69-8cfd-4dfc-aebf-b5e2b0b96bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198884439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2198884439
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1552829196
Short name T320
Test name
Test status
Simulation time 24808535 ps
CPU time 0.63 seconds
Started Aug 01 06:32:00 PM PDT 24
Finished Aug 01 06:32:00 PM PDT 24
Peak memory 198420 kb
Host smart-47406c4f-b14a-419e-9046-3dbadf783dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552829196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1552829196
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1449477010
Short name T626
Test name
Test status
Simulation time 43908567 ps
CPU time 0.73 seconds
Started Aug 01 06:31:49 PM PDT 24
Finished Aug 01 06:31:50 PM PDT 24
Peak memory 201444 kb
Host smart-e5d7c730-12c3-40d8-a628-8e7481cd3b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449477010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1449477010
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.3971030486
Short name T38
Test name
Test status
Simulation time 207042592 ps
CPU time 0.71 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:55 PM PDT 24
Peak memory 199144 kb
Host smart-699bf629-6c03-4442-a631-ae6afcbb8f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971030486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.3971030486
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.1898798063
Short name T277
Test name
Test status
Simulation time 152990957 ps
CPU time 0.86 seconds
Started Aug 01 06:31:57 PM PDT 24
Finished Aug 01 06:31:57 PM PDT 24
Peak memory 209512 kb
Host smart-101d4e98-76c4-479c-9789-76b47eb1095c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898798063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1898798063
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2452952638
Short name T237
Test name
Test status
Simulation time 120874968 ps
CPU time 0.72 seconds
Started Aug 01 06:31:46 PM PDT 24
Finished Aug 01 06:31:47 PM PDT 24
Peak memory 198092 kb
Host smart-c60b697f-6de2-4be6-b933-d444d812094d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452952638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2452952638
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1950007073
Short name T81
Test name
Test status
Simulation time 67593590 ps
CPU time 0.68 seconds
Started Aug 01 06:31:58 PM PDT 24
Finished Aug 01 06:31:59 PM PDT 24
Peak memory 198524 kb
Host smart-0c39b713-46da-46b5-9db3-28fd610c3cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950007073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1950007073
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2244157889
Short name T83
Test name
Test status
Simulation time 23869336 ps
CPU time 0.67 seconds
Started Aug 01 06:32:06 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 198744 kb
Host smart-4c5f88ea-38f8-4d7f-be38-7ee242b18597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244157889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2244157889
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1228735207
Short name T285
Test name
Test status
Simulation time 38634500 ps
CPU time 0.56 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 198000 kb
Host smart-0899add5-1050-4dc9-95b0-0a4b95df219f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228735207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1228735207
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.1424941495
Short name T342
Test name
Test status
Simulation time 164820017 ps
CPU time 0.94 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 198124 kb
Host smart-8c72c195-53a2-4c57-afc9-fa77729e37e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424941495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1424941495
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2256772860
Short name T455
Test name
Test status
Simulation time 41880893 ps
CPU time 0.66 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 197260 kb
Host smart-80a26d26-24df-4d44-b1ba-22af08bfc130
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256772860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2256772860
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2671914622
Short name T452
Test name
Test status
Simulation time 123140210 ps
CPU time 0.6 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 198072 kb
Host smart-12cbe0e5-e7ae-4626-9f8c-2bd9bcd3d61c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671914622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2671914622
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3624463075
Short name T155
Test name
Test status
Simulation time 45636847 ps
CPU time 0.75 seconds
Started Aug 01 06:32:03 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 201384 kb
Host smart-e2b800b6-5840-4795-91c6-0d802d2d9ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624463075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3624463075
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3732932363
Short name T229
Test name
Test status
Simulation time 106166286 ps
CPU time 0.68 seconds
Started Aug 01 06:31:57 PM PDT 24
Finished Aug 01 06:31:58 PM PDT 24
Peak memory 199152 kb
Host smart-cf2b2906-8b14-42ab-bf2a-5bbd733c4c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732932363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3732932363
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.740057778
Short name T518
Test name
Test status
Simulation time 216223484 ps
CPU time 0.82 seconds
Started Aug 01 06:32:07 PM PDT 24
Finished Aug 01 06:32:08 PM PDT 24
Peak memory 209384 kb
Host smart-8a834f48-b149-4d47-9f9e-691ed979dbfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740057778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.740057778
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2499152459
Short name T554
Test name
Test status
Simulation time 60832647 ps
CPU time 0.76 seconds
Started Aug 01 06:31:58 PM PDT 24
Finished Aug 01 06:31:59 PM PDT 24
Peak memory 199168 kb
Host smart-0950704d-26b7-4d1d-909a-d2fbb10cdf89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499152459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2499152459
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.115349847
Short name T503
Test name
Test status
Simulation time 125404747 ps
CPU time 0.65 seconds
Started Aug 01 06:31:52 PM PDT 24
Finished Aug 01 06:31:53 PM PDT 24
Peak memory 198508 kb
Host smart-9a9dbd3d-fb07-493f-af90-29dfa35a827b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115349847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.115349847
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3927321922
Short name T93
Test name
Test status
Simulation time 81563580 ps
CPU time 0.85 seconds
Started Aug 01 06:32:01 PM PDT 24
Finished Aug 01 06:32:02 PM PDT 24
Peak memory 200208 kb
Host smart-78917a84-7263-43a6-bbf6-5e2fd439256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927321922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3927321922
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.594183798
Short name T392
Test name
Test status
Simulation time 110196909 ps
CPU time 0.69 seconds
Started Aug 01 06:32:05 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 198588 kb
Host smart-655817a8-1695-47fa-bd9a-14e9d2abee6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594183798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disa
ble_rom_integrity_check.594183798
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1497744087
Short name T121
Test name
Test status
Simulation time 30990898 ps
CPU time 0.64 seconds
Started Aug 01 06:31:57 PM PDT 24
Finished Aug 01 06:31:58 PM PDT 24
Peak memory 198068 kb
Host smart-55fb17dc-705c-415a-8e2a-2210f37bd7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497744087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.1497744087
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2124349139
Short name T296
Test name
Test status
Simulation time 2116887652 ps
CPU time 0.91 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 198136 kb
Host smart-491991a5-a698-4ca3-aa28-a74c87d29c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124349139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2124349139
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.929370962
Short name T436
Test name
Test status
Simulation time 48411027 ps
CPU time 0.68 seconds
Started Aug 01 06:32:01 PM PDT 24
Finished Aug 01 06:32:02 PM PDT 24
Peak memory 197372 kb
Host smart-bf542eb5-1c0f-41cc-b93a-b6ab22c840e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929370962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.929370962
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.3729799043
Short name T381
Test name
Test status
Simulation time 38813832 ps
CPU time 0.65 seconds
Started Aug 01 06:32:07 PM PDT 24
Finished Aug 01 06:32:08 PM PDT 24
Peak memory 198388 kb
Host smart-c83b8b45-8d9c-4e02-bcfc-c5b00db7d008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729799043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3729799043
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2692792206
Short name T167
Test name
Test status
Simulation time 43869624 ps
CPU time 0.71 seconds
Started Aug 01 06:32:06 PM PDT 24
Finished Aug 01 06:32:07 PM PDT 24
Peak memory 201360 kb
Host smart-7f6e9806-9b6c-44ed-926d-5e0ef45ff2bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692792206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2692792206
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2721254178
Short name T453
Test name
Test status
Simulation time 110855790 ps
CPU time 0.72 seconds
Started Aug 01 06:31:53 PM PDT 24
Finished Aug 01 06:31:54 PM PDT 24
Peak memory 198348 kb
Host smart-1ac5eb43-f726-4716-8163-0fd419912f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721254178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2721254178
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.4055097069
Short name T364
Test name
Test status
Simulation time 111831155 ps
CPU time 0.91 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 209552 kb
Host smart-2191d20e-2e77-4cc5-ac8c-88f8bf9bd48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055097069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.4055097069
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.2488496754
Short name T439
Test name
Test status
Simulation time 279066573 ps
CPU time 0.83 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 199140 kb
Host smart-0d8f7e18-5050-4e16-b4a4-98d7cb0694ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488496754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2488496754
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.562397638
Short name T450
Test name
Test status
Simulation time 67130205 ps
CPU time 0.64 seconds
Started Aug 01 06:31:57 PM PDT 24
Finished Aug 01 06:31:58 PM PDT 24
Peak memory 198544 kb
Host smart-81f284d4-d454-4371-9d9b-75cfab64b580
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562397638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.562397638
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1750665183
Short name T424
Test name
Test status
Simulation time 36315345 ps
CPU time 1.15 seconds
Started Aug 01 06:31:56 PM PDT 24
Finished Aug 01 06:31:57 PM PDT 24
Peak memory 200968 kb
Host smart-b5e58c97-a82e-49cb-8e1d-f1e032e0125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750665183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1750665183
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.731927317
Short name T190
Test name
Test status
Simulation time 57171095 ps
CPU time 0.81 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 198580 kb
Host smart-937111f5-10c8-4467-9d75-ce92582c42b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731927317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disa
ble_rom_integrity_check.731927317
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.756341151
Short name T492
Test name
Test status
Simulation time 59248596 ps
CPU time 0.6 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:04 PM PDT 24
Peak memory 198088 kb
Host smart-7958a5fc-d0d0-4d04-b758-b631aa7298f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756341151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.756341151
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2712875542
Short name T580
Test name
Test status
Simulation time 603056237 ps
CPU time 0.98 seconds
Started Aug 01 06:32:03 PM PDT 24
Finished Aug 01 06:32:04 PM PDT 24
Peak memory 198104 kb
Host smart-f84df83e-aa47-4e2c-8b15-aab86e56d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712875542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2712875542
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.2491420459
Short name T366
Test name
Test status
Simulation time 36343397 ps
CPU time 0.61 seconds
Started Aug 01 06:32:05 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 198052 kb
Host smart-df992a1f-c7f9-4f59-b08a-3618d18ebb95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491420459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2491420459
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.1565676624
Short name T388
Test name
Test status
Simulation time 56380814 ps
CPU time 0.63 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 198088 kb
Host smart-7c6a1f41-1324-4477-82ab-546b4796a386
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565676624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1565676624
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3465401669
Short name T151
Test name
Test status
Simulation time 76622452 ps
CPU time 0.69 seconds
Started Aug 01 06:31:58 PM PDT 24
Finished Aug 01 06:31:59 PM PDT 24
Peak memory 201376 kb
Host smart-883674fb-194e-4bfa-88f7-0050a092c11e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465401669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3465401669
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3096532533
Short name T418
Test name
Test status
Simulation time 106234792 ps
CPU time 0.74 seconds
Started Aug 01 06:31:55 PM PDT 24
Finished Aug 01 06:31:56 PM PDT 24
Peak memory 198384 kb
Host smart-27b6ff28-08bd-476a-98e1-6701b419a9a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096532533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3096532533
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2014782514
Short name T559
Test name
Test status
Simulation time 151249879 ps
CPU time 0.86 seconds
Started Aug 01 06:32:05 PM PDT 24
Finished Aug 01 06:32:07 PM PDT 24
Peak memory 209464 kb
Host smart-ab6f5b0f-f954-48bf-8aac-9195f6731a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014782514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2014782514
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3798500765
Short name T520
Test name
Test status
Simulation time 88106973 ps
CPU time 0.71 seconds
Started Aug 01 06:32:03 PM PDT 24
Finished Aug 01 06:32:04 PM PDT 24
Peak memory 197752 kb
Host smart-cba0765e-e0b7-4b55-b797-acc4d5c6ad7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798500765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3798500765
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3969774327
Short name T557
Test name
Test status
Simulation time 41952816 ps
CPU time 0.7 seconds
Started Aug 01 06:32:02 PM PDT 24
Finished Aug 01 06:32:03 PM PDT 24
Peak memory 198744 kb
Host smart-995ef5c1-6fe0-49a9-8147-6091cf8737b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969774327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3969774327
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1572958217
Short name T85
Test name
Test status
Simulation time 374076206 ps
CPU time 0.75 seconds
Started Aug 01 06:32:06 PM PDT 24
Finished Aug 01 06:32:07 PM PDT 24
Peak memory 198752 kb
Host smart-4423e007-ba83-4f79-bf64-8e13755d2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572958217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1572958217
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2558727236
Short name T403
Test name
Test status
Simulation time 62941874 ps
CPU time 0.68 seconds
Started Aug 01 06:32:15 PM PDT 24
Finished Aug 01 06:32:16 PM PDT 24
Peak memory 198336 kb
Host smart-30781d58-0a39-4c57-ae78-230fe74f833c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558727236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2558727236
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.254272176
Short name T488
Test name
Test status
Simulation time 38347527 ps
CPU time 0.61 seconds
Started Aug 01 06:32:06 PM PDT 24
Finished Aug 01 06:32:07 PM PDT 24
Peak memory 198040 kb
Host smart-06dc2f9f-1c7c-4b0f-9b76-5eaa0149dc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254272176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.254272176
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.897347945
Short name T122
Test name
Test status
Simulation time 309219798 ps
CPU time 0.99 seconds
Started Aug 01 06:31:58 PM PDT 24
Finished Aug 01 06:31:59 PM PDT 24
Peak memory 198144 kb
Host smart-8c3dea51-1eda-4010-aea5-9e15ad7b3f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897347945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.897347945
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.4078550988
Short name T214
Test name
Test status
Simulation time 49289949 ps
CPU time 0.66 seconds
Started Aug 01 06:32:07 PM PDT 24
Finished Aug 01 06:32:07 PM PDT 24
Peak memory 197360 kb
Host smart-d8175f61-b6bd-4a3b-b2ca-9be5a13a1e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078550988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.4078550988
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3045099643
Short name T390
Test name
Test status
Simulation time 29904499 ps
CPU time 0.6 seconds
Started Aug 01 06:32:02 PM PDT 24
Finished Aug 01 06:32:03 PM PDT 24
Peak memory 198052 kb
Host smart-9e569e8e-960d-47f8-9e50-10b02d2b776c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045099643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3045099643
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2312246046
Short name T181
Test name
Test status
Simulation time 43021807 ps
CPU time 0.67 seconds
Started Aug 01 06:32:12 PM PDT 24
Finished Aug 01 06:32:13 PM PDT 24
Peak memory 201348 kb
Host smart-219832c9-c72c-4844-b829-f8e92f6d4ce2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312246046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2312246046
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.4120730241
Short name T137
Test name
Test status
Simulation time 27331583 ps
CPU time 0.67 seconds
Started Aug 01 06:31:59 PM PDT 24
Finished Aug 01 06:32:00 PM PDT 24
Peak memory 198512 kb
Host smart-1a600782-5b9e-4d83-af2c-814456cd0b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120730241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w
akeup_race.4120730241
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.426841200
Short name T325
Test name
Test status
Simulation time 51467852 ps
CPU time 0.78 seconds
Started Aug 01 06:31:56 PM PDT 24
Finished Aug 01 06:31:57 PM PDT 24
Peak memory 199080 kb
Host smart-5710d85f-7e0f-4583-9cad-5ac5cdaa2770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426841200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.426841200
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.825858069
Short name T279
Test name
Test status
Simulation time 111879229 ps
CPU time 0.9 seconds
Started Aug 01 06:32:04 PM PDT 24
Finished Aug 01 06:32:05 PM PDT 24
Peak memory 209468 kb
Host smart-70932099-ac77-471f-a7ff-37b7cc855ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825858069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.825858069
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.959733019
Short name T478
Test name
Test status
Simulation time 79315248 ps
CPU time 0.76 seconds
Started Aug 01 06:32:07 PM PDT 24
Finished Aug 01 06:32:08 PM PDT 24
Peak memory 198108 kb
Host smart-7e781f23-aa8e-4758-a2ec-be58663d40db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959733019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.959733019
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3296097355
Short name T582
Test name
Test status
Simulation time 52783146 ps
CPU time 0.67 seconds
Started Aug 01 06:32:12 PM PDT 24
Finished Aug 01 06:32:13 PM PDT 24
Peak memory 198528 kb
Host smart-4bdb2a9c-838a-4f59-9d26-5c30842650f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296097355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3296097355
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1469249458
Short name T14
Test name
Test status
Simulation time 19239228 ps
CPU time 0.6 seconds
Started Aug 01 06:29:39 PM PDT 24
Finished Aug 01 06:29:39 PM PDT 24
Peak memory 198584 kb
Host smart-2c147bfa-fe26-49bd-add4-ad5c7ab47e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469249458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1469249458
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.514681986
Short name T454
Test name
Test status
Simulation time 54990525 ps
CPU time 0.76 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 199212 kb
Host smart-6c40f786-ea0e-44bd-bbb6-3fb7e625cc80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514681986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disab
le_rom_integrity_check.514681986
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1793459421
Short name T578
Test name
Test status
Simulation time 30535904 ps
CPU time 0.63 seconds
Started Aug 01 06:29:38 PM PDT 24
Finished Aug 01 06:29:38 PM PDT 24
Peak memory 197996 kb
Host smart-c8fa0c3b-24f5-4f8a-8a6b-cdd1a378ce59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793459421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1793459421
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.1709439346
Short name T513
Test name
Test status
Simulation time 843722040 ps
CPU time 0.97 seconds
Started Aug 01 06:29:41 PM PDT 24
Finished Aug 01 06:29:42 PM PDT 24
Peak memory 198128 kb
Host smart-2b392897-fae5-48b5-ba38-ffc6fcb18b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709439346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.1709439346
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.1548177408
Short name T374
Test name
Test status
Simulation time 45823453 ps
CPU time 0.58 seconds
Started Aug 01 06:29:48 PM PDT 24
Finished Aug 01 06:29:49 PM PDT 24
Peak memory 198100 kb
Host smart-cc496a20-0e8f-4872-b303-3c31b7c6d8b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548177408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1548177408
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3534557591
Short name T369
Test name
Test status
Simulation time 75011194 ps
CPU time 0.61 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 198100 kb
Host smart-b6dffa30-4f32-435e-9a0f-26d07eee1e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534557591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3534557591
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1707827465
Short name T162
Test name
Test status
Simulation time 50360014 ps
CPU time 0.73 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 201484 kb
Host smart-a3e1181b-6383-4b23-bdc2-ec1c24de69e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707827465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1707827465
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.1282929978
Short name T607
Test name
Test status
Simulation time 88927618 ps
CPU time 0.91 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 199088 kb
Host smart-576e7ec1-7ab6-4110-b4f7-3d3ca4dc7bed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282929978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1282929978
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.961719563
Short name T583
Test name
Test status
Simulation time 172522942 ps
CPU time 0.82 seconds
Started Aug 01 06:29:43 PM PDT 24
Finished Aug 01 06:29:44 PM PDT 24
Peak memory 209600 kb
Host smart-6a100120-9fc7-4017-ba76-5ff60c2dbe9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961719563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.961719563
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3544622545
Short name T33
Test name
Test status
Simulation time 96737847 ps
CPU time 0.92 seconds
Started Aug 01 06:29:42 PM PDT 24
Finished Aug 01 06:29:43 PM PDT 24
Peak memory 199108 kb
Host smart-bed60e16-f9c1-4d4a-b646-733ec0983c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544622545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3544622545
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.877276178
Short name T365
Test name
Test status
Simulation time 27082182 ps
CPU time 0.65 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 199340 kb
Host smart-31f97cb1-0516-4613-8a0b-2fdc8ec4dbb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877276178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.877276178
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.2434272749
Short name T391
Test name
Test status
Simulation time 29737583 ps
CPU time 0.74 seconds
Started Aug 01 06:29:39 PM PDT 24
Finished Aug 01 06:29:40 PM PDT 24
Peak memory 198808 kb
Host smart-1d9fd57a-1c29-4a2b-8af0-79b9de16dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434272749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2434272749
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3833844926
Short name T482
Test name
Test status
Simulation time 63305206 ps
CPU time 0.68 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 198212 kb
Host smart-6ed71234-f55d-4a6d-b65e-98e41ce56789
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833844926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.3833844926
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1015505119
Short name T411
Test name
Test status
Simulation time 44388932 ps
CPU time 0.6 seconds
Started Aug 01 06:29:57 PM PDT 24
Finished Aug 01 06:29:58 PM PDT 24
Peak memory 198072 kb
Host smart-d51278cc-84a2-4a2f-819d-3e1e2c8a44b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015505119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1015505119
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.106467137
Short name T598
Test name
Test status
Simulation time 164622063 ps
CPU time 0.91 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 198156 kb
Host smart-6c53a60a-1499-4cef-8c0c-b23b714acc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106467137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.106467137
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3905925480
Short name T280
Test name
Test status
Simulation time 54732690 ps
CPU time 0.66 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:47 PM PDT 24
Peak memory 197360 kb
Host smart-660a0c58-8061-4888-9c57-a467d40ae6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905925480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3905925480
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1278079644
Short name T433
Test name
Test status
Simulation time 31751033 ps
CPU time 0.61 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 198068 kb
Host smart-df80056a-3354-4f8d-83ce-c746d1c39bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278079644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1278079644
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.3189784443
Short name T289
Test name
Test status
Simulation time 36503153 ps
CPU time 0.69 seconds
Started Aug 01 06:29:41 PM PDT 24
Finished Aug 01 06:29:41 PM PDT 24
Peak memory 198348 kb
Host smart-727b30ae-8a8e-43d7-912d-8af694acc08e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189784443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3189784443
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1345890613
Short name T566
Test name
Test status
Simulation time 244995457 ps
CPU time 0.77 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 209464 kb
Host smart-78b076a7-876c-4b73-824d-b9a9aedec54a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345890613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1345890613
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2844039899
Short name T199
Test name
Test status
Simulation time 82235182 ps
CPU time 0.77 seconds
Started Aug 01 06:29:51 PM PDT 24
Finished Aug 01 06:29:52 PM PDT 24
Peak memory 198104 kb
Host smart-118e0c80-afd4-4de1-8acb-3c002bb71014
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844039899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2844039899
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.4171396853
Short name T327
Test name
Test status
Simulation time 54485841 ps
CPU time 0.64 seconds
Started Aug 01 06:29:38 PM PDT 24
Finished Aug 01 06:29:39 PM PDT 24
Peak memory 198500 kb
Host smart-8ebb225d-fa24-4789-82d8-648710484d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171396853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.4171396853
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.4000388693
Short name T536
Test name
Test status
Simulation time 97119794 ps
CPU time 0.88 seconds
Started Aug 01 06:29:57 PM PDT 24
Finished Aug 01 06:29:58 PM PDT 24
Peak memory 200248 kb
Host smart-226751cb-bf6a-4e68-b008-a005a8bd18d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000388693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.4000388693
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3901553080
Short name T141
Test name
Test status
Simulation time 71246528 ps
CPU time 0.69 seconds
Started Aug 01 06:29:54 PM PDT 24
Finished Aug 01 06:29:55 PM PDT 24
Peak memory 198484 kb
Host smart-374f33e5-d80d-470e-9bca-77662d5b6afc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901553080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.3901553080
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2649029627
Short name T524
Test name
Test status
Simulation time 32908760 ps
CPU time 0.62 seconds
Started Aug 01 06:29:55 PM PDT 24
Finished Aug 01 06:29:55 PM PDT 24
Peak memory 198056 kb
Host smart-01ff7acd-0246-4da4-9ec2-60f435974a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649029627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2649029627
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.3619554246
Short name T335
Test name
Test status
Simulation time 604317140 ps
CPU time 1.02 seconds
Started Aug 01 06:29:53 PM PDT 24
Finished Aug 01 06:29:54 PM PDT 24
Peak memory 198440 kb
Host smart-0f752a0b-e19e-4860-9446-7a3ae645b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619554246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3619554246
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3723554151
Short name T560
Test name
Test status
Simulation time 37065747 ps
CPU time 0.63 seconds
Started Aug 01 06:29:57 PM PDT 24
Finished Aug 01 06:29:58 PM PDT 24
Peak memory 197356 kb
Host smart-22230ff7-58fd-44dc-965d-ca8290cb1abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723554151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3723554151
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.3576523585
Short name T272
Test name
Test status
Simulation time 28849004 ps
CPU time 0.63 seconds
Started Aug 01 06:29:47 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 198144 kb
Host smart-c139c44c-10a0-4f1d-b34b-e2c9208afb41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576523585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3576523585
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2806399016
Short name T150
Test name
Test status
Simulation time 51494501 ps
CPU time 0.66 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 201400 kb
Host smart-6e9d6f73-b25a-4225-95db-ef797f3ee710
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806399016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2806399016
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.1685919689
Short name T343
Test name
Test status
Simulation time 484205224 ps
CPU time 0.73 seconds
Started Aug 01 06:29:51 PM PDT 24
Finished Aug 01 06:29:52 PM PDT 24
Peak memory 198464 kb
Host smart-7fa2195f-5faf-4b23-969b-c924b2e65367
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685919689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.1685919689
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.113173076
Short name T227
Test name
Test status
Simulation time 105634166 ps
CPU time 0.9 seconds
Started Aug 01 06:29:48 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 209520 kb
Host smart-931d2ad1-7c81-4f9c-9859-bb8fc65b8dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113173076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.113173076
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3696700666
Short name T606
Test name
Test status
Simulation time 139687281 ps
CPU time 0.88 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 199356 kb
Host smart-509eecd0-9d4a-4c7d-bfa9-deaba57629d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696700666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3696700666
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1660633035
Short name T508
Test name
Test status
Simulation time 29447797 ps
CPU time 0.67 seconds
Started Aug 01 06:29:46 PM PDT 24
Finished Aug 01 06:29:47 PM PDT 24
Peak memory 199404 kb
Host smart-8b38bb77-040f-47c0-aa30-376beb0de431
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660633035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1660633035
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3097861223
Short name T94
Test name
Test status
Simulation time 48366881 ps
CPU time 0.94 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 200124 kb
Host smart-003a04e8-a875-413d-a6f0-f278d139f7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097861223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3097861223
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3961886953
Short name T519
Test name
Test status
Simulation time 73552081 ps
CPU time 0.68 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 199152 kb
Host smart-025273fb-ad5a-4f9c-a257-a3751f5901eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961886953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3961886953
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3648028939
Short name T600
Test name
Test status
Simulation time 28706844 ps
CPU time 0.69 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 198044 kb
Host smart-9ee17806-03eb-4322-847d-50bc66619c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648028939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3648028939
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3457074652
Short name T596
Test name
Test status
Simulation time 344514215 ps
CPU time 0.97 seconds
Started Aug 01 06:29:57 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 198136 kb
Host smart-c67ee880-631e-4586-9b11-d8e6ab324caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457074652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3457074652
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3020377067
Short name T419
Test name
Test status
Simulation time 64602234 ps
CPU time 0.64 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 197352 kb
Host smart-29769797-165b-42ca-828f-b6b30f2fdfd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020377067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3020377067
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.875068532
Short name T211
Test name
Test status
Simulation time 52843976 ps
CPU time 0.64 seconds
Started Aug 01 06:29:51 PM PDT 24
Finished Aug 01 06:29:52 PM PDT 24
Peak memory 198020 kb
Host smart-6129abcb-f6af-44ef-80c8-cc23739a7f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875068532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.875068532
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2621244717
Short name T567
Test name
Test status
Simulation time 76714881 ps
CPU time 0.7 seconds
Started Aug 01 06:30:02 PM PDT 24
Finished Aug 01 06:30:03 PM PDT 24
Peak memory 201416 kb
Host smart-9fa0ecaa-211d-48c7-8d68-b970de91f8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621244717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2621244717
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1753914781
Short name T294
Test name
Test status
Simulation time 110463870 ps
CPU time 0.82 seconds
Started Aug 01 06:29:49 PM PDT 24
Finished Aug 01 06:29:50 PM PDT 24
Peak memory 199112 kb
Host smart-4d2894f4-89dc-49c2-a742-3311cf4fac0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753914781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1753914781
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.386870197
Short name T406
Test name
Test status
Simulation time 174228870 ps
CPU time 0.83 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 209604 kb
Host smart-041b6d60-9c4f-4c05-a8dc-d27eee52e125
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386870197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.386870197
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1130706923
Short name T577
Test name
Test status
Simulation time 63162336 ps
CPU time 0.61 seconds
Started Aug 01 06:29:50 PM PDT 24
Finished Aug 01 06:29:51 PM PDT 24
Peak memory 198516 kb
Host smart-af9545ea-95d7-443f-bece-461af41088b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130706923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1130706923
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2180986794
Short name T407
Test name
Test status
Simulation time 102732882 ps
CPU time 0.77 seconds
Started Aug 01 06:30:05 PM PDT 24
Finished Aug 01 06:30:06 PM PDT 24
Peak memory 198880 kb
Host smart-a0bc957d-a7e8-4cf1-8110-91b8e2cee193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180986794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2180986794
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3114089071
Short name T428
Test name
Test status
Simulation time 58321500 ps
CPU time 0.81 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198412 kb
Host smart-8f666a1a-f39c-4828-a9c2-5f4082e03c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114089071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3114089071
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2163411513
Short name T305
Test name
Test status
Simulation time 38459718 ps
CPU time 0.58 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198036 kb
Host smart-c87f1804-9a7f-4c62-b48b-6d237a638f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163411513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2163411513
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2292801782
Short name T619
Test name
Test status
Simulation time 636514025 ps
CPU time 0.96 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198140 kb
Host smart-17c36a73-9a02-4c1f-b85a-200e1e6babd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292801782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2292801782
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2439331798
Short name T2
Test name
Test status
Simulation time 83570319 ps
CPU time 0.64 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 198188 kb
Host smart-e5eef671-16ed-4623-9ff9-03f6cd2b8b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439331798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2439331798
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.3310598401
Short name T373
Test name
Test status
Simulation time 93514276 ps
CPU time 0.6 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 198096 kb
Host smart-bc719aa2-1a70-4ce9-a259-7ec3c6b6f19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310598401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3310598401
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3493074995
Short name T48
Test name
Test status
Simulation time 262446084 ps
CPU time 0.66 seconds
Started Aug 01 06:29:58 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 201364 kb
Host smart-b265b6a8-f4a1-46d2-9ec8-89b98166d4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493074995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3493074995
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1819315824
Short name T332
Test name
Test status
Simulation time 71245550 ps
CPU time 0.88 seconds
Started Aug 01 06:29:58 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 198416 kb
Host smart-56dc59d2-18a0-4885-bf01-e3b3c22a98fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819315824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1819315824
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2707803761
Short name T393
Test name
Test status
Simulation time 114308150 ps
CPU time 0.91 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 209504 kb
Host smart-53fff78a-143a-401c-bb6c-80fc52492c1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707803761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2707803761
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1376515033
Short name T389
Test name
Test status
Simulation time 56704342 ps
CPU time 0.75 seconds
Started Aug 01 06:29:59 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 198096 kb
Host smart-7c8df7b6-a0d5-4b61-9fe5-7e725bb18ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376515033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1376515033
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.140984165
Short name T301
Test name
Test status
Simulation time 29231908 ps
CPU time 0.66 seconds
Started Aug 01 06:30:00 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 199368 kb
Host smart-bb244e0c-944b-4d08-bf95-9bcc4ebc32a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140984165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.140984165
Directory /workspace/9.pwrmgr_smoke/latest
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