Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 584 1 T1 8 T2 2 T6 2
auto[1] 462 1 T1 8 T8 3 T14 1


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 571 1 T1 10 T6 2 T8 1
auto[1] 475 1 T1 6 T2 2 T8 5


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 461 1 T1 10 T8 4 T9 1
auto[1] 585 1 T1 6 T2 2 T6 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 850 1 T1 16 T2 1 T6 1
auto[1] 196 1 T2 1 T6 1 T8 2


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 457 1 T1 7 T8 4 T9 4
auto[1] 589 1 T1 9 T2 2 T6 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 603 1 T1 8 T2 2 T6 2
auto[1] 443 1 T1 8 T8 1 T9 2


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 24 1 T9 1 T29 1 T30 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 3 1 T163 1 T164 1 T165 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 22 1 T1 1 T29 1 T30 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 6 1 T166 1 T167 1 T168 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 34 1 T1 1 T30 1 T94 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 8 1 T94 1 T169 1 T166 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 78 1 T6 1 T59 1 T60 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 60 1 T6 1 T59 1 T60 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 24 1 T1 1 T97 1 T124 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 1 1 T170 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 24 1 T34 1 T30 2 T95 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 3 1 T64 1 T171 1 T172 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 22 1 T1 2 T27 1 T121 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 4 1 T27 1 T173 1 T174 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 20 1 T1 1 T34 1 T28 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 6 1 T34 1 T28 1 T175 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 29 1 T35 1 T29 1 T30 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 5 1 T176 1 T177 1 T178 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 22 1 T1 1 T8 1 T9 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 7 1 T8 1 T94 1 T179 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 26 1 T35 1 T30 1 T72 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 2 1 T35 1 T180 1 - -
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 26 1 T2 1 T9 1 T29 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 10 1 T2 1 T169 1 T179 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 24 1 T1 1 T91 1 T181 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 2 1 T182 1 T183 1 - -
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 31 1 T9 1 T34 1 T91 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 9 1 T91 1 T27 1 T58 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 26 1 T8 1 T35 1 T91 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T35 1 T91 1 T184 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 21 1 T9 1 T29 1 T95 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 1 1 T64 1 - - - -
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 29 1 T1 2 T29 1 T97 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 4 1 T28 1 T185 1 T186 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 28 1 T95 1 T124 1 T101 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 3 1 T187 1 T168 1 T140 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 24 1 T8 1 T35 1 T29 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 2 1 T176 1 T188 1 - -
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 22 1 T1 1 T30 1 T95 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 2 1 T189 1 T190 1 - -
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 18 1 T96 1 T124 1 T101 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 2 1 T191 1 T164 1 - -
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 23 1 T29 1 T87 1 T30 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T175 1 T64 1 T192 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 30 1 T34 1 T29 1 T87 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 6 1 T34 1 T87 1 T184 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 29 1 T1 1 T27 1 T97 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 5 1 T27 1 T143 1 T163 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 22 1 T1 1 T8 1 T29 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T8 1 T193 1 - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 32 1 T94 1 T95 3 T96 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 6 1 T194 2 T142 1 T195 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 30 1 T29 1 T26 1 T95 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 5 1 T26 1 T193 1 T196 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 22 1 T1 1 T14 1 T173 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 8 1 T173 1 T64 2 T197 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 15 1 T72 1 T198 1 T174 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T189 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 25 1 T12 1 T94 1 T96 3
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 6 1 T12 1 T58 1 T142 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 28 1 T1 2 T29 2 T87 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 5 1 T87 1 T196 1 T188 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 20 1 T12 2 T29 3 T87 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 3 1 T12 2 T144 1 - -

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