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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.23 96.15 99.44 96.00 96.18 100.00 95.74


Total test records in report: 741
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T558 /workspace/coverage/default/22.pwrmgr_aborted_low_power.1071732305 Aug 02 05:15:56 PM PDT 24 Aug 02 05:15:57 PM PDT 24 24420395 ps
T559 /workspace/coverage/default/42.pwrmgr_global_esc.511833092 Aug 02 05:16:40 PM PDT 24 Aug 02 05:16:40 PM PDT 24 50112512 ps
T560 /workspace/coverage/default/21.pwrmgr_aborted_low_power.2857059968 Aug 02 05:15:51 PM PDT 24 Aug 02 05:15:52 PM PDT 24 30477787 ps
T561 /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1606128119 Aug 02 05:15:59 PM PDT 24 Aug 02 05:16:00 PM PDT 24 94330529 ps
T562 /workspace/coverage/default/35.pwrmgr_aborted_low_power.3109727657 Aug 02 05:16:14 PM PDT 24 Aug 02 05:16:15 PM PDT 24 95828617 ps
T563 /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2752575516 Aug 02 05:16:39 PM PDT 24 Aug 02 05:16:40 PM PDT 24 29133161 ps
T201 /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3077692533 Aug 02 05:16:06 PM PDT 24 Aug 02 05:16:07 PM PDT 24 64734469 ps
T564 /workspace/coverage/default/25.pwrmgr_escalation_timeout.3145956917 Aug 02 05:15:59 PM PDT 24 Aug 02 05:16:00 PM PDT 24 170222947 ps
T565 /workspace/coverage/default/27.pwrmgr_glitch.984762548 Aug 02 05:16:12 PM PDT 24 Aug 02 05:16:13 PM PDT 24 88679325 ps
T566 /workspace/coverage/default/13.pwrmgr_reset_invalid.3186063414 Aug 02 05:15:05 PM PDT 24 Aug 02 05:15:06 PM PDT 24 187460574 ps
T567 /workspace/coverage/default/0.pwrmgr_aborted_low_power.479823485 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:00 PM PDT 24 68886984 ps
T568 /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3226208220 Aug 02 05:15:31 PM PDT 24 Aug 02 05:15:32 PM PDT 24 39244946 ps
T569 /workspace/coverage/default/35.pwrmgr_smoke.3108796790 Aug 02 05:16:33 PM PDT 24 Aug 02 05:16:34 PM PDT 24 28731497 ps
T570 /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.4265748551 Aug 02 05:15:42 PM PDT 24 Aug 02 05:15:43 PM PDT 24 250114815 ps
T571 /workspace/coverage/default/19.pwrmgr_reset.2511166158 Aug 02 05:15:44 PM PDT 24 Aug 02 05:15:45 PM PDT 24 18206199 ps
T572 /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2081544010 Aug 02 05:16:17 PM PDT 24 Aug 02 05:16:18 PM PDT 24 91772957 ps
T573 /workspace/coverage/default/2.pwrmgr_reset_invalid.1711347064 Aug 02 05:14:56 PM PDT 24 Aug 02 05:14:56 PM PDT 24 315147557 ps
T574 /workspace/coverage/default/11.pwrmgr_reset.3136833402 Aug 02 05:15:31 PM PDT 24 Aug 02 05:15:32 PM PDT 24 60376243 ps
T575 /workspace/coverage/default/24.pwrmgr_global_esc.1117517405 Aug 02 05:16:08 PM PDT 24 Aug 02 05:16:09 PM PDT 24 78634210 ps
T576 /workspace/coverage/default/7.pwrmgr_glitch.3386326284 Aug 02 05:15:04 PM PDT 24 Aug 02 05:15:05 PM PDT 24 46622704 ps
T577 /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1538855334 Aug 02 05:16:47 PM PDT 24 Aug 02 05:16:48 PM PDT 24 44718610 ps
T578 /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1167089288 Aug 02 05:15:13 PM PDT 24 Aug 02 05:15:14 PM PDT 24 64301449 ps
T579 /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3104317922 Aug 02 05:16:05 PM PDT 24 Aug 02 05:16:06 PM PDT 24 57013359 ps
T580 /workspace/coverage/default/31.pwrmgr_global_esc.1514602103 Aug 02 05:16:01 PM PDT 24 Aug 02 05:16:01 PM PDT 24 41582198 ps
T581 /workspace/coverage/default/23.pwrmgr_global_esc.206303400 Aug 02 05:16:02 PM PDT 24 Aug 02 05:16:03 PM PDT 24 41367368 ps
T165 /workspace/coverage/default/7.pwrmgr_lowpower_invalid.801275898 Aug 02 05:15:07 PM PDT 24 Aug 02 05:15:08 PM PDT 24 75270413 ps
T582 /workspace/coverage/default/35.pwrmgr_reset_invalid.3908111599 Aug 02 05:16:27 PM PDT 24 Aug 02 05:16:28 PM PDT 24 126071628 ps
T583 /workspace/coverage/default/4.pwrmgr_glitch.1863863609 Aug 02 05:14:55 PM PDT 24 Aug 02 05:14:56 PM PDT 24 31744940 ps
T584 /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.21978869 Aug 02 05:17:04 PM PDT 24 Aug 02 05:17:15 PM PDT 24 96957521 ps
T585 /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3935233745 Aug 02 05:16:11 PM PDT 24 Aug 02 05:16:12 PM PDT 24 96450637 ps
T586 /workspace/coverage/default/33.pwrmgr_smoke.626170128 Aug 02 05:16:23 PM PDT 24 Aug 02 05:16:24 PM PDT 24 26719070 ps
T587 /workspace/coverage/default/48.pwrmgr_stress_all.940958122 Aug 02 05:16:48 PM PDT 24 Aug 02 05:16:49 PM PDT 24 41654767 ps
T588 /workspace/coverage/default/2.pwrmgr_smoke.763140883 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:00 PM PDT 24 104102552 ps
T170 /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1710652253 Aug 02 05:16:03 PM PDT 24 Aug 02 05:16:04 PM PDT 24 52805113 ps
T589 /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1323011502 Aug 02 05:15:17 PM PDT 24 Aug 02 05:15:18 PM PDT 24 66271359 ps
T590 /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3414937549 Aug 02 05:16:22 PM PDT 24 Aug 02 05:16:23 PM PDT 24 181727827 ps
T591 /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.684490 Aug 02 05:16:04 PM PDT 24 Aug 02 05:16:05 PM PDT 24 83392089 ps
T592 /workspace/coverage/default/43.pwrmgr_reset.4087591447 Aug 02 05:16:37 PM PDT 24 Aug 02 05:16:38 PM PDT 24 54703406 ps
T593 /workspace/coverage/default/32.pwrmgr_reset.169976966 Aug 02 05:16:14 PM PDT 24 Aug 02 05:16:19 PM PDT 24 67791828 ps
T594 /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1885721632 Aug 02 05:16:13 PM PDT 24 Aug 02 05:16:14 PM PDT 24 86852225 ps
T595 /workspace/coverage/default/5.pwrmgr_reset_invalid.335221589 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:01 PM PDT 24 144644520 ps
T596 /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.964238356 Aug 02 05:15:44 PM PDT 24 Aug 02 05:15:44 PM PDT 24 228407462 ps
T597 /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.709511023 Aug 02 05:15:46 PM PDT 24 Aug 02 05:15:47 PM PDT 24 32208723 ps
T598 /workspace/coverage/default/19.pwrmgr_escalation_timeout.2758320140 Aug 02 05:15:57 PM PDT 24 Aug 02 05:15:58 PM PDT 24 312013267 ps
T599 /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.427453925 Aug 02 05:15:52 PM PDT 24 Aug 02 05:15:53 PM PDT 24 38078069 ps
T600 /workspace/coverage/default/13.pwrmgr_reset.3904117926 Aug 02 05:15:35 PM PDT 24 Aug 02 05:15:35 PM PDT 24 130381167 ps
T601 /workspace/coverage/default/49.pwrmgr_global_esc.322704339 Aug 02 05:17:05 PM PDT 24 Aug 02 05:17:06 PM PDT 24 108856387 ps
T602 /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2102092884 Aug 02 05:14:57 PM PDT 24 Aug 02 05:14:58 PM PDT 24 139967820 ps
T603 /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1204113851 Aug 02 05:15:50 PM PDT 24 Aug 02 05:15:50 PM PDT 24 39876412 ps
T604 /workspace/coverage/default/7.pwrmgr_escalation_timeout.36697396 Aug 02 05:15:06 PM PDT 24 Aug 02 05:15:07 PM PDT 24 622699609 ps
T605 /workspace/coverage/default/7.pwrmgr_global_esc.1135947761 Aug 02 05:15:08 PM PDT 24 Aug 02 05:15:09 PM PDT 24 29958319 ps
T606 /workspace/coverage/default/7.pwrmgr_reset_invalid.1426598751 Aug 02 05:15:36 PM PDT 24 Aug 02 05:15:37 PM PDT 24 109490184 ps
T607 /workspace/coverage/default/14.pwrmgr_reset_invalid.3295267866 Aug 02 05:15:41 PM PDT 24 Aug 02 05:15:42 PM PDT 24 326310606 ps
T608 /workspace/coverage/default/26.pwrmgr_global_esc.1132165330 Aug 02 05:16:03 PM PDT 24 Aug 02 05:16:04 PM PDT 24 152602517 ps
T609 /workspace/coverage/default/29.pwrmgr_aborted_low_power.1441206146 Aug 02 05:16:30 PM PDT 24 Aug 02 05:16:31 PM PDT 24 45025138 ps
T610 /workspace/coverage/default/47.pwrmgr_aborted_low_power.2545214477 Aug 02 05:16:44 PM PDT 24 Aug 02 05:16:44 PM PDT 24 41178519 ps
T611 /workspace/coverage/default/8.pwrmgr_escalation_timeout.3064263270 Aug 02 05:15:08 PM PDT 24 Aug 02 05:15:09 PM PDT 24 632001542 ps
T612 /workspace/coverage/default/32.pwrmgr_escalation_timeout.2257904510 Aug 02 05:16:10 PM PDT 24 Aug 02 05:16:11 PM PDT 24 628728153 ps
T202 /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1616596486 Aug 02 05:17:10 PM PDT 24 Aug 02 05:17:10 PM PDT 24 94260575 ps
T613 /workspace/coverage/default/41.pwrmgr_glitch.1306805835 Aug 02 05:16:44 PM PDT 24 Aug 02 05:16:45 PM PDT 24 57446494 ps
T614 /workspace/coverage/default/25.pwrmgr_smoke.2796218784 Aug 02 05:16:01 PM PDT 24 Aug 02 05:16:02 PM PDT 24 30252000 ps
T615 /workspace/coverage/default/38.pwrmgr_wakeup.2480841268 Aug 02 05:16:35 PM PDT 24 Aug 02 05:16:36 PM PDT 24 29899681 ps
T616 /workspace/coverage/default/34.pwrmgr_aborted_low_power.4285160566 Aug 02 05:16:27 PM PDT 24 Aug 02 05:16:28 PM PDT 24 31207419 ps
T617 /workspace/coverage/default/9.pwrmgr_reset.2414567000 Aug 02 05:15:13 PM PDT 24 Aug 02 05:15:14 PM PDT 24 70597837 ps
T618 /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2274549134 Aug 02 05:16:25 PM PDT 24 Aug 02 05:16:25 PM PDT 24 28922431 ps
T619 /workspace/coverage/default/9.pwrmgr_glitch.660350152 Aug 02 05:15:03 PM PDT 24 Aug 02 05:15:04 PM PDT 24 90755878 ps
T620 /workspace/coverage/default/23.pwrmgr_escalation_timeout.1983417721 Aug 02 05:16:28 PM PDT 24 Aug 02 05:16:29 PM PDT 24 622370190 ps
T621 /workspace/coverage/default/8.pwrmgr_reset.3859557947 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:02 PM PDT 24 80389459 ps
T622 /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3604037942 Aug 02 05:16:52 PM PDT 24 Aug 02 05:16:58 PM PDT 24 39341044 ps
T623 /workspace/coverage/default/37.pwrmgr_aborted_low_power.2823328894 Aug 02 05:16:31 PM PDT 24 Aug 02 05:16:32 PM PDT 24 43001348 ps
T624 /workspace/coverage/default/31.pwrmgr_reset.3895497584 Aug 02 05:16:11 PM PDT 24 Aug 02 05:16:12 PM PDT 24 75127514 ps
T625 /workspace/coverage/default/18.pwrmgr_reset.1527252637 Aug 02 05:15:29 PM PDT 24 Aug 02 05:15:30 PM PDT 24 53724728 ps
T626 /workspace/coverage/default/22.pwrmgr_reset.1573896259 Aug 02 05:15:59 PM PDT 24 Aug 02 05:16:00 PM PDT 24 120376262 ps
T627 /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2768623301 Aug 02 05:15:46 PM PDT 24 Aug 02 05:15:47 PM PDT 24 66100828 ps
T628 /workspace/coverage/default/30.pwrmgr_escalation_timeout.4163546608 Aug 02 05:16:09 PM PDT 24 Aug 02 05:16:10 PM PDT 24 605136994 ps
T629 /workspace/coverage/default/41.pwrmgr_escalation_timeout.2525438692 Aug 02 05:16:39 PM PDT 24 Aug 02 05:16:41 PM PDT 24 159227224 ps
T69 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2665374188 Aug 02 05:11:37 PM PDT 24 Aug 02 05:11:39 PM PDT 24 119579373 ps
T76 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2436943206 Aug 02 05:11:29 PM PDT 24 Aug 02 05:11:30 PM PDT 24 21571699 ps
T77 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2232830320 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 18223018 ps
T79 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2142280548 Aug 02 05:11:38 PM PDT 24 Aug 02 05:11:39 PM PDT 24 20563805 ps
T22 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.335629219 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:48 PM PDT 24 104116888 ps
T23 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3119061325 Aug 02 05:11:43 PM PDT 24 Aug 02 05:11:44 PM PDT 24 86508661 ps
T78 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1604115048 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 18422385 ps
T147 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2613538780 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 31172920 ps
T148 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.769930550 Aug 02 05:11:52 PM PDT 24 Aug 02 05:11:53 PM PDT 24 40933897 ps
T70 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3571466372 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:45 PM PDT 24 22170146 ps
T115 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1003123139 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:46 PM PDT 24 20983196 ps
T149 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2294408023 Aug 02 05:11:55 PM PDT 24 Aug 02 05:11:55 PM PDT 24 34914613 ps
T24 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3470758181 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:01 PM PDT 24 105189495 ps
T98 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3290161646 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:59 PM PDT 24 18932707 ps
T104 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3484705133 Aug 02 05:11:32 PM PDT 24 Aug 02 05:11:33 PM PDT 24 32896327 ps
T116 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.994457219 Aug 02 05:11:27 PM PDT 24 Aug 02 05:11:28 PM PDT 24 44647628 ps
T117 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3615094831 Aug 02 05:11:25 PM PDT 24 Aug 02 05:11:26 PM PDT 24 57371548 ps
T150 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2727986531 Aug 02 05:12:10 PM PDT 24 Aug 02 05:12:11 PM PDT 24 20126973 ps
T151 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.484773208 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 24414371 ps
T152 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1721858949 Aug 02 05:11:49 PM PDT 24 Aug 02 05:11:49 PM PDT 24 48782742 ps
T630 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1852844236 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:48 PM PDT 24 161168273 ps
T61 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.863689459 Aug 02 05:12:08 PM PDT 24 Aug 02 05:12:10 PM PDT 24 532845930 ps
T81 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1350248372 Aug 02 05:11:26 PM PDT 24 Aug 02 05:11:27 PM PDT 24 34730876 ps
T631 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3767872399 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:46 PM PDT 24 32131614 ps
T62 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2317470888 Aug 02 05:11:42 PM PDT 24 Aug 02 05:11:44 PM PDT 24 760340366 ps
T63 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.4144183655 Aug 02 05:11:37 PM PDT 24 Aug 02 05:11:40 PM PDT 24 52690030 ps
T66 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3738918252 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 168005569 ps
T73 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.749876999 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:48 PM PDT 24 230726386 ps
T632 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1821171069 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:01 PM PDT 24 24830665 ps
T99 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.945324473 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 148126059 ps
T65 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3940737446 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:48 PM PDT 24 199188064 ps
T118 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2199911821 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:47 PM PDT 24 26102989 ps
T633 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3912640213 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:01 PM PDT 24 124741237 ps
T83 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4118365406 Aug 02 05:11:34 PM PDT 24 Aug 02 05:11:35 PM PDT 24 96716184 ps
T119 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2299422787 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 29822842 ps
T105 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.516762601 Aug 02 05:11:35 PM PDT 24 Aug 02 05:11:36 PM PDT 24 23905500 ps
T74 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.830170086 Aug 02 05:11:26 PM PDT 24 Aug 02 05:11:28 PM PDT 24 39063327 ps
T80 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3134984512 Aug 02 05:11:29 PM PDT 24 Aug 02 05:11:34 PM PDT 24 172167069 ps
T82 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1035637314 Aug 02 05:11:39 PM PDT 24 Aug 02 05:11:40 PM PDT 24 53088956 ps
T120 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3766735326 Aug 02 05:11:52 PM PDT 24 Aug 02 05:11:53 PM PDT 24 39813015 ps
T634 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1402042719 Aug 02 05:11:43 PM PDT 24 Aug 02 05:11:44 PM PDT 24 184721761 ps
T635 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.66593708 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:34 PM PDT 24 22889759 ps
T636 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2715687214 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 19511014 ps
T153 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2770291777 Aug 02 05:11:49 PM PDT 24 Aug 02 05:11:49 PM PDT 24 61164115 ps
T100 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2297182322 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:54 PM PDT 24 42356134 ps
T637 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2986490698 Aug 02 05:12:03 PM PDT 24 Aug 02 05:12:05 PM PDT 24 65187290 ps
T106 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1341084948 Aug 02 05:11:54 PM PDT 24 Aug 02 05:11:55 PM PDT 24 58080325 ps
T638 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3119648287 Aug 02 05:12:06 PM PDT 24 Aug 02 05:12:07 PM PDT 24 95868613 ps
T113 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2036490981 Aug 02 05:11:40 PM PDT 24 Aug 02 05:11:43 PM PDT 24 282476544 ps
T639 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1310342446 Aug 02 05:11:39 PM PDT 24 Aug 02 05:11:39 PM PDT 24 23022058 ps
T640 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3991874545 Aug 02 05:11:35 PM PDT 24 Aug 02 05:11:37 PM PDT 24 376704112 ps
T641 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1128727160 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:46 PM PDT 24 70904959 ps
T642 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.958900384 Aug 02 05:12:09 PM PDT 24 Aug 02 05:12:09 PM PDT 24 40814566 ps
T643 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.592068802 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:59 PM PDT 24 45974454 ps
T644 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3369350240 Aug 02 05:11:25 PM PDT 24 Aug 02 05:11:26 PM PDT 24 67979950 ps
T75 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2283550679 Aug 02 05:11:34 PM PDT 24 Aug 02 05:11:35 PM PDT 24 86442825 ps
T107 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.678011151 Aug 02 05:11:52 PM PDT 24 Aug 02 05:11:53 PM PDT 24 44669947 ps
T645 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.928677058 Aug 02 05:11:26 PM PDT 24 Aug 02 05:11:29 PM PDT 24 131494763 ps
T646 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3507222311 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:48 PM PDT 24 41897939 ps
T647 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.831399272 Aug 02 05:12:01 PM PDT 24 Aug 02 05:12:01 PM PDT 24 26988770 ps
T648 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2870447250 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:45 PM PDT 24 21872963 ps
T649 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3838299919 Aug 02 05:11:54 PM PDT 24 Aug 02 05:11:55 PM PDT 24 20689368 ps
T650 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3827223828 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:48 PM PDT 24 20283884 ps
T651 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2931042636 Aug 02 05:11:28 PM PDT 24 Aug 02 05:11:28 PM PDT 24 20591505 ps
T652 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1544843220 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 57612163 ps
T653 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1082353169 Aug 02 05:11:32 PM PDT 24 Aug 02 05:11:33 PM PDT 24 47345921 ps
T654 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1517924106 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:58 PM PDT 24 21230845 ps
T655 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2161281180 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:34 PM PDT 24 78052577 ps
T656 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1606659622 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:34 PM PDT 24 54612568 ps
T657 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.700468282 Aug 02 05:11:22 PM PDT 24 Aug 02 05:11:23 PM PDT 24 63687962 ps
T658 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3615975022 Aug 02 05:12:05 PM PDT 24 Aug 02 05:12:05 PM PDT 24 21505823 ps
T84 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1371929508 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:48 PM PDT 24 415759029 ps
T659 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2106284811 Aug 02 05:12:08 PM PDT 24 Aug 02 05:12:09 PM PDT 24 18154258 ps
T660 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.116637203 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:49 PM PDT 24 144970321 ps
T661 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2411806977 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:01 PM PDT 24 445624996 ps
T662 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2604055758 Aug 02 05:11:40 PM PDT 24 Aug 02 05:11:41 PM PDT 24 131052170 ps
T145 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.891187712 Aug 02 05:11:32 PM PDT 24 Aug 02 05:11:38 PM PDT 24 199804076 ps
T663 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1030661169 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 51495866 ps
T664 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2025788603 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:59 PM PDT 24 86664323 ps
T114 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1702818564 Aug 02 05:11:43 PM PDT 24 Aug 02 05:11:45 PM PDT 24 152651636 ps
T665 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2400337710 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:47 PM PDT 24 16365425 ps
T666 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.693653529 Aug 02 05:11:28 PM PDT 24 Aug 02 05:11:29 PM PDT 24 58900522 ps
T667 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1002975079 Aug 02 05:11:42 PM PDT 24 Aug 02 05:11:43 PM PDT 24 32615142 ps
T668 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.654877515 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 60640682 ps
T669 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2665108312 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 27059582 ps
T670 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.956564550 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:50 PM PDT 24 121705830 ps
T671 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1421973744 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 19524067 ps
T672 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.544788571 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 44613767 ps
T673 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2827639925 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:59 PM PDT 24 84565387 ps
T674 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2263777899 Aug 02 05:11:56 PM PDT 24 Aug 02 05:11:56 PM PDT 24 18473103 ps
T675 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4123941608 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:47 PM PDT 24 96474591 ps
T676 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3826063020 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:50 PM PDT 24 20444502 ps
T677 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.4068918087 Aug 02 05:11:29 PM PDT 24 Aug 02 05:11:38 PM PDT 24 55918397 ps
T678 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1101428081 Aug 02 05:11:49 PM PDT 24 Aug 02 05:11:50 PM PDT 24 27965884 ps
T679 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.344356563 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:47 PM PDT 24 22051135 ps
T680 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2689297527 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:35 PM PDT 24 116472921 ps
T681 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3746120746 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:01 PM PDT 24 21519808 ps
T682 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1309859619 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 30880254 ps
T683 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2605762334 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 20273560 ps
T684 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3376619205 Aug 02 05:11:30 PM PDT 24 Aug 02 05:11:31 PM PDT 24 16440161 ps
T685 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1729133300 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:01 PM PDT 24 42477148 ps
T686 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1350332956 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:33 PM PDT 24 37201298 ps
T687 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3942388047 Aug 02 05:12:02 PM PDT 24 Aug 02 05:12:03 PM PDT 24 53343987 ps
T688 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1414599339 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 91260511 ps
T689 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.468252660 Aug 02 05:11:53 PM PDT 24 Aug 02 05:11:54 PM PDT 24 37481177 ps
T690 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1840598963 Aug 02 05:11:36 PM PDT 24 Aug 02 05:11:37 PM PDT 24 20938933 ps
T691 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3800581497 Aug 02 05:12:06 PM PDT 24 Aug 02 05:12:08 PM PDT 24 31648890 ps
T692 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2770889440 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:34 PM PDT 24 31886640 ps
T693 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2693613027 Aug 02 05:12:05 PM PDT 24 Aug 02 05:12:06 PM PDT 24 195760910 ps
T694 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2548203171 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:46 PM PDT 24 41565671 ps
T695 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1786792750 Aug 02 05:11:43 PM PDT 24 Aug 02 05:11:49 PM PDT 24 86584639 ps
T696 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4070636755 Aug 02 05:11:33 PM PDT 24 Aug 02 05:11:34 PM PDT 24 46983493 ps
T697 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.812165682 Aug 02 05:11:43 PM PDT 24 Aug 02 05:11:44 PM PDT 24 46418754 ps
T698 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.475877975 Aug 02 05:11:56 PM PDT 24 Aug 02 05:11:57 PM PDT 24 50105877 ps
T699 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3977963485 Aug 02 05:11:59 PM PDT 24 Aug 02 05:12:00 PM PDT 24 47014162 ps
T108 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3785694601 Aug 02 05:11:42 PM PDT 24 Aug 02 05:11:43 PM PDT 24 42473605 ps
T700 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2008276217 Aug 02 05:11:53 PM PDT 24 Aug 02 05:11:53 PM PDT 24 41210037 ps
T701 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.455923327 Aug 02 05:11:39 PM PDT 24 Aug 02 05:11:40 PM PDT 24 41843247 ps
T702 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2070788746 Aug 02 05:11:50 PM PDT 24 Aug 02 05:11:52 PM PDT 24 394608892 ps
T85 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1771511793 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:47 PM PDT 24 169866881 ps
T703 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3131889253 Aug 02 05:11:28 PM PDT 24 Aug 02 05:11:29 PM PDT 24 17877251 ps
T704 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.963618096 Aug 02 05:11:58 PM PDT 24 Aug 02 05:11:59 PM PDT 24 429246942 ps
T705 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3430622776 Aug 02 05:12:15 PM PDT 24 Aug 02 05:12:16 PM PDT 24 241036347 ps
T706 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4174895798 Aug 02 05:11:31 PM PDT 24 Aug 02 05:11:32 PM PDT 24 94984699 ps
T707 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2376343400 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 23437387 ps
T708 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.595052265 Aug 02 05:11:35 PM PDT 24 Aug 02 05:11:36 PM PDT 24 64428566 ps
T709 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2203212526 Aug 02 05:11:36 PM PDT 24 Aug 02 05:11:37 PM PDT 24 60680155 ps
T710 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2781590361 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 189398266 ps
T711 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.709647765 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:46 PM PDT 24 52633718 ps
T712 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2091880746 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:45 PM PDT 24 52752219 ps
T713 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3139771829 Aug 02 05:11:52 PM PDT 24 Aug 02 05:11:52 PM PDT 24 21152973 ps
T714 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.4003978932 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:48 PM PDT 24 30378201 ps
T109 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3176329555 Aug 02 05:12:00 PM PDT 24 Aug 02 05:12:00 PM PDT 24 22603085 ps
T110 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1239043805 Aug 02 05:11:36 PM PDT 24 Aug 02 05:11:37 PM PDT 24 28414676 ps
T146 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1824161916 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:49 PM PDT 24 387824340 ps
T715 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.810022902 Aug 02 05:12:01 PM PDT 24 Aug 02 05:12:03 PM PDT 24 188162366 ps
T716 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1694141783 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 20144268 ps
T717 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1648055283 Aug 02 05:11:47 PM PDT 24 Aug 02 05:11:48 PM PDT 24 180803958 ps
T86 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.4108491300 Aug 02 05:11:36 PM PDT 24 Aug 02 05:11:37 PM PDT 24 100675715 ps
T718 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3719732319 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 28351299 ps
T719 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1984373810 Aug 02 05:12:02 PM PDT 24 Aug 02 05:12:05 PM PDT 24 109964724 ps
T720 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2143907892 Aug 02 05:11:42 PM PDT 24 Aug 02 05:11:43 PM PDT 24 22579845 ps
T721 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.851327404 Aug 02 05:11:39 PM PDT 24 Aug 02 05:11:40 PM PDT 24 38029089 ps
T722 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2925275760 Aug 02 05:11:34 PM PDT 24 Aug 02 05:11:35 PM PDT 24 253743068 ps
T723 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1355063165 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:47 PM PDT 24 16781511 ps
T724 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3806600279 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:46 PM PDT 24 229053257 ps
T725 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3886284431 Aug 02 05:11:53 PM PDT 24 Aug 02 05:11:54 PM PDT 24 45107030 ps
T726 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.882850096 Aug 02 05:12:21 PM PDT 24 Aug 02 05:12:22 PM PDT 24 20841928 ps
T727 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1845685448 Aug 02 05:12:10 PM PDT 24 Aug 02 05:12:11 PM PDT 24 31310220 ps
T728 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2589566587 Aug 02 05:11:39 PM PDT 24 Aug 02 05:11:40 PM PDT 24 673222121 ps
T729 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1024345367 Aug 02 05:11:57 PM PDT 24 Aug 02 05:11:58 PM PDT 24 18583395 ps
T111 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2298893118 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:49 PM PDT 24 266340181 ps
T730 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2188292470 Aug 02 05:11:46 PM PDT 24 Aug 02 05:11:47 PM PDT 24 33751509 ps
T731 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4063969709 Aug 02 05:11:44 PM PDT 24 Aug 02 05:11:44 PM PDT 24 16772045 ps
T732 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1582069297 Aug 02 05:11:45 PM PDT 24 Aug 02 05:11:47 PM PDT 24 190008602 ps
T112 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2683899530 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 49678644 ps
T733 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.851461183 Aug 02 05:12:11 PM PDT 24 Aug 02 05:12:12 PM PDT 24 73770587 ps
T734 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2308532165 Aug 02 05:11:30 PM PDT 24 Aug 02 05:11:31 PM PDT 24 21063725 ps
T735 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3244237865 Aug 02 05:12:03 PM PDT 24 Aug 02 05:12:04 PM PDT 24 24999029 ps
T736 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3201154283 Aug 02 05:11:42 PM PDT 24 Aug 02 05:11:43 PM PDT 24 23667042 ps
T737 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.205082941 Aug 02 05:11:50 PM PDT 24 Aug 02 05:11:51 PM PDT 24 22382449 ps
T738 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1522822328 Aug 02 05:11:36 PM PDT 24 Aug 02 05:11:37 PM PDT 24 121420819 ps
T739 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4218307018 Aug 02 05:11:31 PM PDT 24 Aug 02 05:11:32 PM PDT 24 64274819 ps
T740 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3659839152 Aug 02 05:11:48 PM PDT 24 Aug 02 05:11:49 PM PDT 24 28547651 ps
T741 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1409165876 Aug 02 05:11:51 PM PDT 24 Aug 02 05:11:53 PM PDT 24 69001228 ps

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.3837772289
Short name T2
Test name
Test status
Simulation time 29189864 ps
CPU time 0.65 seconds
Started Aug 02 05:16:08 PM PDT 24
Finished Aug 02 05:16:09 PM PDT 24
Peak memory 198352 kb
Host smart-26dfff51-7fbf-4db6-bf30-78a92653c2ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837772289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.3837772289
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1853754093
Short name T4
Test name
Test status
Simulation time 99867415 ps
CPU time 1.05 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 209472 kb
Host smart-40734854-383e-4408-9ba2-a38023166a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853754093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1853754093
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3285532170
Short name T95
Test name
Test status
Simulation time 75508139 ps
CPU time 0.91 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 200224 kb
Host smart-7d5fe2ef-df6e-4790-9dec-9d459522b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285532170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3285532170
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.792464495
Short name T20
Test name
Test status
Simulation time 3010745424 ps
CPU time 1.34 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:50 PM PDT 24
Peak memory 218288 kb
Host smart-9c4c5966-3a18-4e12-9440-b5109852abfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792464495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.792464495
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3119061325
Short name T23
Test name
Test status
Simulation time 86508661 ps
CPU time 0.84 seconds
Started Aug 02 05:11:43 PM PDT 24
Finished Aug 02 05:11:44 PM PDT 24
Peak memory 196060 kb
Host smart-23271072-1a21-4e79-aa40-5a433a3308fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119061325 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3119061325
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.330606316
Short name T8
Test name
Test status
Simulation time 41933432 ps
CPU time 0.73 seconds
Started Aug 02 05:14:57 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 201424 kb
Host smart-4734b4c0-e768-4826-961d-08e313cb6637
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330606316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid
.330606316
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.442731957
Short name T27
Test name
Test status
Simulation time 165285296 ps
CPU time 0.66 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 199332 kb
Host smart-dfa434e0-77fb-4b83-ac20-f72681c87720
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442731957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.442731957
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3613886087
Short name T64
Test name
Test status
Simulation time 109249506 ps
CPU time 0.99 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 198624 kb
Host smart-d0a4a34c-5f91-4933-814a-44ba15c5b439
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613886087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3613886087
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3940737446
Short name T65
Test name
Test status
Simulation time 199188064 ps
CPU time 1.66 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 200612 kb
Host smart-6c5a3813-df8a-4f0d-ba11-49572f751d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940737446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3940737446
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1416012059
Short name T31
Test name
Test status
Simulation time 77659590 ps
CPU time 0.68 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 199216 kb
Host smart-52490a5f-90c8-4483-a0fc-5e3bb6848d77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416012059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1416012059
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2452821782
Short name T1
Test name
Test status
Simulation time 69279009 ps
CPU time 0.81 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 200176 kb
Host smart-0a2065f6-8ae8-4c85-bc67-011830e1eb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452821782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2452821782
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.2368299416
Short name T12
Test name
Test status
Simulation time 56212839 ps
CPU time 0.75 seconds
Started Aug 02 05:15:18 PM PDT 24
Finished Aug 02 05:15:19 PM PDT 24
Peak memory 198376 kb
Host smart-004db2e9-b2e4-4222-adce-88f64a208ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368299416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.2368299416
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1721858949
Short name T152
Test name
Test status
Simulation time 48782742 ps
CPU time 0.61 seconds
Started Aug 02 05:11:49 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195072 kb
Host smart-1706be88-34c1-4aab-b746-19ab44c7e985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721858949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1721858949
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.4144183655
Short name T63
Test name
Test status
Simulation time 52690030 ps
CPU time 2.32 seconds
Started Aug 02 05:11:37 PM PDT 24
Finished Aug 02 05:11:40 PM PDT 24
Peak memory 196912 kb
Host smart-3dfde7fd-4ca2-49c7-b015-66a7d48b76fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144183655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.4144183655
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3531952223
Short name T128
Test name
Test status
Simulation time 29556978 ps
CPU time 0.63 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 197356 kb
Host smart-513034fc-9444-4ccd-9438-ce618f572e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531952223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.3531952223
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3176329555
Short name T109
Test name
Test status
Simulation time 22603085 ps
CPU time 0.64 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 197340 kb
Host smart-778039fd-4640-4ab9-9afd-a7617a33eab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176329555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3176329555
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2497997809
Short name T138
Test name
Test status
Simulation time 55041607 ps
CPU time 0.78 seconds
Started Aug 02 05:16:19 PM PDT 24
Finished Aug 02 05:16:20 PM PDT 24
Peak memory 198616 kb
Host smart-e77255d2-b965-4e6f-9218-2f8fa5135658
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497997809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2497997809
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1314112665
Short name T101
Test name
Test status
Simulation time 26837631 ps
CPU time 0.88 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 200372 kb
Host smart-d9eaaec4-074e-4f73-aba8-13bfb5259776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314112665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1314112665
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3444955758
Short name T68
Test name
Test status
Simulation time 55395979 ps
CPU time 0.75 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:53 PM PDT 24
Peak memory 198800 kb
Host smart-cc673c0b-6f25-4fa0-9958-4ae7ccada68b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444955758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.3444955758
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.4283538566
Short name T135
Test name
Test status
Simulation time 70205303 ps
CPU time 0.65 seconds
Started Aug 02 05:14:57 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 199140 kb
Host smart-82e64b5e-36fe-4aa9-aaad-a98cfb548904
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283538566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.4283538566
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1686983539
Short name T9
Test name
Test status
Simulation time 28947746 ps
CPU time 0.75 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 198760 kb
Host smart-11b4e275-9757-4e85-ba84-7a2819207c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686983539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1686983539
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2805082787
Short name T60
Test name
Test status
Simulation time 233196582 ps
CPU time 0.6 seconds
Started Aug 02 05:16:50 PM PDT 24
Finished Aug 02 05:16:51 PM PDT 24
Peak memory 198580 kb
Host smart-1c91e2dd-7e8e-4c9c-95a9-d650f3c3a494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805082787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2805082787
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3087070500
Short name T140
Test name
Test status
Simulation time 160773996 ps
CPU time 0.68 seconds
Started Aug 02 05:15:50 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 198644 kb
Host smart-53493143-67fd-4f19-93d7-17292589a20d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087070500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.3087070500
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3448868231
Short name T205
Test name
Test status
Simulation time 62037135 ps
CPU time 0.76 seconds
Started Aug 02 05:15:42 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 198572 kb
Host smart-753a51c6-ce68-4f4d-94d9-f235a02d2397
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448868231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3448868231
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3192015852
Short name T188
Test name
Test status
Simulation time 84686724 ps
CPU time 0.67 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 201396 kb
Host smart-8ba43409-fdd0-4ed2-ac32-7383d983e687
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192015852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3192015852
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2658630812
Short name T189
Test name
Test status
Simulation time 154333292 ps
CPU time 0.67 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 201520 kb
Host smart-140a6b62-9535-423e-90fb-0bd54c5ed8c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658630812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2658630812
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1371929508
Short name T84
Test name
Test status
Simulation time 415759029 ps
CPU time 1.57 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 195384 kb
Host smart-199aa92f-f21b-4837-8ba2-e8d44d3ef129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371929508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1371929508
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.3902945117
Short name T185
Test name
Test status
Simulation time 77070712 ps
CPU time 0.66 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 201392 kb
Host smart-b2166e5a-fc77-4f29-9ee7-4ebfcc520312
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902945117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.3902945117
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3244471179
Short name T139
Test name
Test status
Simulation time 152951699 ps
CPU time 0.64 seconds
Started Aug 02 05:15:32 PM PDT 24
Finished Aug 02 05:15:33 PM PDT 24
Peak memory 198388 kb
Host smart-ee0f74f6-2311-4190-8cc3-1fb250b643e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244471179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.3244471179
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.356970297
Short name T32
Test name
Test status
Simulation time 54715408 ps
CPU time 0.8 seconds
Started Aug 02 05:15:29 PM PDT 24
Finished Aug 02 05:15:30 PM PDT 24
Peak memory 198468 kb
Host smart-887e0219-89a9-4fc3-8b1c-913429b37763
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356970297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.356970297
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3150013431
Short name T166
Test name
Test status
Simulation time 73019640 ps
CPU time 0.67 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 201484 kb
Host smart-74168924-a271-411d-910d-91ce43878fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150013431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3150013431
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1998227884
Short name T164
Test name
Test status
Simulation time 45478067 ps
CPU time 0.74 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 201380 kb
Host smart-c7b415a4-7244-4fc5-9c88-dae2d48c178e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998227884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1998227884
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3444373262
Short name T402
Test name
Test status
Simulation time 81932093 ps
CPU time 0.67 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 199224 kb
Host smart-084c37b5-1b3c-4540-8758-4d000a68eeb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444373262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.3444373262
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.4031159601
Short name T35
Test name
Test status
Simulation time 44288605 ps
CPU time 0.71 seconds
Started Aug 02 05:15:46 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 201264 kb
Host smart-406de3e4-a16b-4448-8c97-8c82d3174cf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031159601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.4031159601
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3615094831
Short name T117
Test name
Test status
Simulation time 57371548 ps
CPU time 0.64 seconds
Started Aug 02 05:11:25 PM PDT 24
Finished Aug 02 05:11:26 PM PDT 24
Peak memory 195176 kb
Host smart-2ff2da02-6bbc-4d5c-ae02-6315780f5f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615094831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3615094831
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2436943206
Short name T76
Test name
Test status
Simulation time 21571699 ps
CPU time 0.63 seconds
Started Aug 02 05:11:29 PM PDT 24
Finished Aug 02 05:11:30 PM PDT 24
Peak memory 195072 kb
Host smart-0d219986-f864-421c-a1f9-43f36ab46938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436943206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2436943206
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1402042719
Short name T634
Test name
Test status
Simulation time 184721761 ps
CPU time 0.59 seconds
Started Aug 02 05:11:43 PM PDT 24
Finished Aug 02 05:11:44 PM PDT 24
Peak memory 195036 kb
Host smart-c169e329-dcfc-479a-ac21-ff595929d632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402042719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1402042719
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.562245854
Short name T177
Test name
Test status
Simulation time 32607069 ps
CPU time 0.68 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:14:59 PM PDT 24
Peak memory 198180 kb
Host smart-11514a09-154e-48d1-a094-9cbec136da16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562245854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.562245854
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3195102520
Short name T192
Test name
Test status
Simulation time 98655228 ps
CPU time 0.66 seconds
Started Aug 02 05:15:31 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 201456 kb
Host smart-74b0927b-d67a-49fc-8cb7-ac75c1138075
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195102520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3195102520
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.493197507
Short name T183
Test name
Test status
Simulation time 51408239 ps
CPU time 0.7 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 201180 kb
Host smart-f22392d1-e9ad-438f-a936-466f6d14d4af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493197507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invali
d.493197507
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.108755099
Short name T122
Test name
Test status
Simulation time 73544110 ps
CPU time 0.93 seconds
Started Aug 02 05:15:45 PM PDT 24
Finished Aug 02 05:15:46 PM PDT 24
Peak memory 199312 kb
Host smart-4742caea-c523-4b47-8489-8ded81fdfa03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108755099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.108755099
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1710652253
Short name T170
Test name
Test status
Simulation time 52805113 ps
CPU time 0.69 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 201376 kb
Host smart-3a7d4454-a5e5-4197-8dd9-51ca2903b10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710652253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1710652253
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3738918252
Short name T66
Test name
Test status
Simulation time 168005569 ps
CPU time 1.08 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195292 kb
Host smart-69dc84f5-9e35-4539-8f11-089c54613b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738918252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3738918252
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.4077210589
Short name T228
Test name
Test status
Simulation time 40484633 ps
CPU time 0.59 seconds
Started Aug 02 05:15:30 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 198148 kb
Host smart-ee7edbba-54ae-4621-8862-ee6c24dce5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077210589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.4077210589
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.66593708
Short name T635
Test name
Test status
Simulation time 22889759 ps
CPU time 0.82 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 195124 kb
Host smart-e6b98162-e5ff-4afe-b8f7-2ad10b8e26d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66593708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.66593708
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2665374188
Short name T69
Test name
Test status
Simulation time 119579373 ps
CPU time 1.88 seconds
Started Aug 02 05:11:37 PM PDT 24
Finished Aug 02 05:11:39 PM PDT 24
Peak memory 195288 kb
Host smart-6d699c7e-a15d-4f80-8b07-f3197fc1a0ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665374188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.2
665374188
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3369350240
Short name T644
Test name
Test status
Simulation time 67979950 ps
CPU time 0.62 seconds
Started Aug 02 05:11:25 PM PDT 24
Finished Aug 02 05:11:26 PM PDT 24
Peak memory 195100 kb
Host smart-a6f519ed-5cf0-4d91-9e4d-3c92ed21515f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369350240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
369350240
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1606659622
Short name T656
Test name
Test status
Simulation time 54612568 ps
CPU time 0.82 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 195228 kb
Host smart-a35e7c64-01c8-4608-bfda-66edcf1a6947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606659622 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1606659622
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4070636755
Short name T696
Test name
Test status
Simulation time 46983493 ps
CPU time 0.75 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 195272 kb
Host smart-08d580bf-8bae-4f37-bc02-2d0325d5200d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070636755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.4070636755
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2589566587
Short name T728
Test name
Test status
Simulation time 673222121 ps
CPU time 1.07 seconds
Started Aug 02 05:11:39 PM PDT 24
Finished Aug 02 05:11:40 PM PDT 24
Peak memory 200500 kb
Host smart-f7ee004a-1e31-43f8-8518-bf053ff08c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589566587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.2589566587
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1002975079
Short name T667
Test name
Test status
Simulation time 32615142 ps
CPU time 0.77 seconds
Started Aug 02 05:11:42 PM PDT 24
Finished Aug 02 05:11:43 PM PDT 24
Peak memory 195076 kb
Host smart-03c2b3ef-ce74-44f2-b8b0-619cbbbaf8ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002975079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
002975079
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2036490981
Short name T113
Test name
Test status
Simulation time 282476544 ps
CPU time 3.25 seconds
Started Aug 02 05:11:40 PM PDT 24
Finished Aug 02 05:11:43 PM PDT 24
Peak memory 195292 kb
Host smart-525b6b85-eee0-4856-8e4a-4b39974d628d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036490981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
036490981
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.700468282
Short name T657
Test name
Test status
Simulation time 63687962 ps
CPU time 0.64 seconds
Started Aug 02 05:11:22 PM PDT 24
Finished Aug 02 05:11:23 PM PDT 24
Peak memory 197688 kb
Host smart-be9c68bb-d79f-4562-8e70-b957ac5d86c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700468282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.700468282
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2203212526
Short name T709
Test name
Test status
Simulation time 60680155 ps
CPU time 1 seconds
Started Aug 02 05:11:36 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 195276 kb
Host smart-f0651734-3b56-4d04-af10-3a6fde2e09dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203212526 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2203212526
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3131889253
Short name T703
Test name
Test status
Simulation time 17877251 ps
CPU time 0.63 seconds
Started Aug 02 05:11:28 PM PDT 24
Finished Aug 02 05:11:29 PM PDT 24
Peak memory 197288 kb
Host smart-b65be6f5-2560-4f75-a72f-3a7f7aa62466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131889253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3131889253
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2931042636
Short name T651
Test name
Test status
Simulation time 20591505 ps
CPU time 0.62 seconds
Started Aug 02 05:11:28 PM PDT 24
Finished Aug 02 05:11:28 PM PDT 24
Peak memory 195068 kb
Host smart-bb7baaff-1b2f-4568-ac8e-64967b49a7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931042636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2931042636
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.994457219
Short name T116
Test name
Test status
Simulation time 44647628 ps
CPU time 0.79 seconds
Started Aug 02 05:11:27 PM PDT 24
Finished Aug 02 05:11:28 PM PDT 24
Peak memory 195040 kb
Host smart-effc41f8-2dbc-491e-9ac9-c92ab0207a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994457219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.994457219
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3991874545
Short name T640
Test name
Test status
Simulation time 376704112 ps
CPU time 1.83 seconds
Started Aug 02 05:11:35 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 197556 kb
Host smart-a0dbdf82-4c76-409b-819e-6d40d7cff94f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991874545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3991874545
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3134984512
Short name T80
Test name
Test status
Simulation time 172167069 ps
CPU time 1.64 seconds
Started Aug 02 05:11:29 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 200528 kb
Host smart-1e1e44fa-c26d-4243-a645-58c936181b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134984512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3134984512
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1035637314
Short name T82
Test name
Test status
Simulation time 53088956 ps
CPU time 0.95 seconds
Started Aug 02 05:11:39 PM PDT 24
Finished Aug 02 05:11:40 PM PDT 24
Peak memory 195200 kb
Host smart-3009807f-ecdf-46fa-8276-892beb0c6574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035637314 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.1035637314
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1239043805
Short name T110
Test name
Test status
Simulation time 28414676 ps
CPU time 0.66 seconds
Started Aug 02 05:11:36 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 195144 kb
Host smart-fdf2be0f-62e7-4f85-868e-64c2d6877036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239043805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1239043805
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2188292470
Short name T730
Test name
Test status
Simulation time 33751509 ps
CPU time 0.62 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 195116 kb
Host smart-29a4e2c6-741b-41ee-86af-67322dd57b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188292470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2188292470
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1082353169
Short name T653
Test name
Test status
Simulation time 47345921 ps
CPU time 0.82 seconds
Started Aug 02 05:11:32 PM PDT 24
Finished Aug 02 05:11:33 PM PDT 24
Peak memory 198388 kb
Host smart-fa2ecc4d-298c-4064-b0f9-6d6a79d022eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082353169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1082353169
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.335629219
Short name T22
Test name
Test status
Simulation time 104116888 ps
CPU time 2.35 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 197376 kb
Host smart-f86a1a8b-ca6e-48e3-9924-c32a6eeb8fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335629219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.335629219
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1522822328
Short name T738
Test name
Test status
Simulation time 121420819 ps
CPU time 1 seconds
Started Aug 02 05:11:36 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 200244 kb
Host smart-3d77e89d-01cc-4301-9196-eee2a1eddb51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522822328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1522822328
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.945324473
Short name T99
Test name
Test status
Simulation time 148126059 ps
CPU time 0.88 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195308 kb
Host smart-fa3a4d4b-1b49-45a1-a9c1-a1fb0bffbc5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945324473 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.945324473
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3719732319
Short name T718
Test name
Test status
Simulation time 28351299 ps
CPU time 0.62 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195144 kb
Host smart-3738bc2e-e04e-42c4-84bf-109318063f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719732319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3719732319
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1101428081
Short name T678
Test name
Test status
Simulation time 27965884 ps
CPU time 0.71 seconds
Started Aug 02 05:11:49 PM PDT 24
Finished Aug 02 05:11:50 PM PDT 24
Peak memory 195204 kb
Host smart-7be41316-8635-445b-a81b-f687ff7f6d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101428081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1101428081
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4118365406
Short name T83
Test name
Test status
Simulation time 96716184 ps
CPU time 1.15 seconds
Started Aug 02 05:11:34 PM PDT 24
Finished Aug 02 05:11:35 PM PDT 24
Peak memory 200424 kb
Host smart-4e10b3e4-fa2c-4a9b-acd7-a51ccd35d63d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118365406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.4118365406
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3470758181
Short name T24
Test name
Test status
Simulation time 105189495 ps
CPU time 0.86 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 200600 kb
Host smart-b464ccba-bf59-466e-9ac3-2ea43428b02c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470758181 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3470758181
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.344356563
Short name T679
Test name
Test status
Simulation time 22051135 ps
CPU time 0.64 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 195172 kb
Host smart-3b8ad341-881a-4a72-8cdc-6bf5278bd672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344356563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.344356563
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3838299919
Short name T649
Test name
Test status
Simulation time 20689368 ps
CPU time 0.63 seconds
Started Aug 02 05:11:54 PM PDT 24
Finished Aug 02 05:11:55 PM PDT 24
Peak memory 194984 kb
Host smart-f1dd235f-b879-4cdf-84c8-247be2ed8415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838299919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3838299919
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3827223828
Short name T650
Test name
Test status
Simulation time 20283884 ps
CPU time 0.71 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 197412 kb
Host smart-70966972-bff0-452d-8a17-ba7d343ea7d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827223828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3827223828
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.595052265
Short name T708
Test name
Test status
Simulation time 64428566 ps
CPU time 1.48 seconds
Started Aug 02 05:11:35 PM PDT 24
Finished Aug 02 05:11:36 PM PDT 24
Peak memory 197404 kb
Host smart-c0565559-c2f4-4c5e-be85-7641c892d643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595052265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.595052265
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1824161916
Short name T146
Test name
Test status
Simulation time 387824340 ps
CPU time 1.51 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 200624 kb
Host smart-38ee00de-f9f0-48d4-b407-7b7ace830c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824161916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1824161916
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2400337710
Short name T665
Test name
Test status
Simulation time 16365425 ps
CPU time 0.67 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 197328 kb
Host smart-e469ae55-f0ae-4db1-8fc8-a6c1febc3f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400337710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2400337710
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2727986531
Short name T150
Test name
Test status
Simulation time 20126973 ps
CPU time 0.62 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 195060 kb
Host smart-aab96171-e9e3-41dc-8c41-b1e893c69edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727986531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2727986531
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3826063020
Short name T676
Test name
Test status
Simulation time 20444502 ps
CPU time 0.73 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:50 PM PDT 24
Peak memory 197436 kb
Host smart-35fb8f37-49bc-49dc-b72a-a8d61dd8ff8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826063020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3826063020
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.956564550
Short name T670
Test name
Test status
Simulation time 121705830 ps
CPU time 2.56 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:50 PM PDT 24
Peak memory 197408 kb
Host smart-24129ff9-261f-4e8a-b88e-1c288de7943b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956564550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.956564550
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1648055283
Short name T717
Test name
Test status
Simulation time 180803958 ps
CPU time 1.65 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 200668 kb
Host smart-7e9174a4-bc6c-49f9-a18e-1fbc7a362691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648055283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1648055283
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4123941608
Short name T675
Test name
Test status
Simulation time 96474591 ps
CPU time 0.73 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 200008 kb
Host smart-a0760bcb-3119-4ccc-85fa-0eaae968e9aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123941608 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.4123941608
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2143907892
Short name T720
Test name
Test status
Simulation time 22579845 ps
CPU time 0.71 seconds
Started Aug 02 05:11:42 PM PDT 24
Finished Aug 02 05:11:43 PM PDT 24
Peak memory 198324 kb
Host smart-9430abf4-7530-45ae-9ad1-67aacec8e7be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143907892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.2143907892
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2605762334
Short name T683
Test name
Test status
Simulation time 20273560 ps
CPU time 0.67 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195108 kb
Host smart-68e903fa-85df-4793-babe-cfd029688092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605762334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2605762334
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2665108312
Short name T669
Test name
Test status
Simulation time 27059582 ps
CPU time 0.76 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195180 kb
Host smart-23aa1224-0bb3-4b8f-a63b-a5a47fc60b12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665108312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2665108312
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2070788746
Short name T702
Test name
Test status
Simulation time 394608892 ps
CPU time 1.91 seconds
Started Aug 02 05:11:50 PM PDT 24
Finished Aug 02 05:11:52 PM PDT 24
Peak memory 196452 kb
Host smart-a213b74d-7810-4881-9ea8-70f5b12ae236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070788746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2070788746
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.654877515
Short name T668
Test name
Test status
Simulation time 60640682 ps
CPU time 0.69 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 195328 kb
Host smart-7717aa28-3493-4176-93f3-07e90261ab2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654877515 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.654877515
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.882850096
Short name T726
Test name
Test status
Simulation time 20841928 ps
CPU time 0.67 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 195184 kb
Host smart-bb79ea6c-80b7-48c0-b349-fefa74002373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882850096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.882850096
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.205082941
Short name T737
Test name
Test status
Simulation time 22382449 ps
CPU time 0.63 seconds
Started Aug 02 05:11:50 PM PDT 24
Finished Aug 02 05:11:51 PM PDT 24
Peak memory 195104 kb
Host smart-63bedb86-7554-4315-a09f-c00ee899f7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205082941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.205082941
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.831399272
Short name T647
Test name
Test status
Simulation time 26988770 ps
CPU time 0.73 seconds
Started Aug 02 05:12:01 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 197372 kb
Host smart-eb47a2f7-155d-4e36-8e81-35010f74f786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831399272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.831399272
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3430622776
Short name T705
Test name
Test status
Simulation time 241036347 ps
CPU time 1.14 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:16 PM PDT 24
Peak memory 196244 kb
Host smart-806535fd-659b-493a-a94a-4bee13a7c128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430622776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3430622776
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.963618096
Short name T704
Test name
Test status
Simulation time 429246942 ps
CPU time 1.6 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 200512 kb
Host smart-ab868579-7297-44a1-a8cc-0b5715537927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963618096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err
.963618096
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.475877975
Short name T698
Test name
Test status
Simulation time 50105877 ps
CPU time 0.91 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:11:57 PM PDT 24
Peak memory 195308 kb
Host smart-970389de-a8e7-476a-84aa-dab62012b031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475877975 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.475877975
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.851461183
Short name T733
Test name
Test status
Simulation time 73770587 ps
CPU time 0.67 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 195180 kb
Host smart-160bc409-4a6c-425a-95b6-8a7d21b5a44c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851461183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.851461183
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2106284811
Short name T659
Test name
Test status
Simulation time 18154258 ps
CPU time 0.62 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 195096 kb
Host smart-6f32730e-a8f4-49dc-8faa-265a1930d53a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106284811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.2106284811
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3615975022
Short name T658
Test name
Test status
Simulation time 21505823 ps
CPU time 0.81 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 195236 kb
Host smart-8d8d304e-6fb6-428f-b95c-aa1d56c9d9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615975022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3615975022
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1409165876
Short name T741
Test name
Test status
Simulation time 69001228 ps
CPU time 1.65 seconds
Started Aug 02 05:11:51 PM PDT 24
Finished Aug 02 05:11:53 PM PDT 24
Peak memory 197452 kb
Host smart-bb245186-5796-4108-a2a1-a52e24c924d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409165876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1409165876
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2693613027
Short name T693
Test name
Test status
Simulation time 195760910 ps
CPU time 1.2 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:06 PM PDT 24
Peak memory 195416 kb
Host smart-16df6b2d-bb58-47fe-b833-24e0140ba6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693613027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2693613027
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1030661169
Short name T663
Test name
Test status
Simulation time 51495866 ps
CPU time 1.43 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 196416 kb
Host smart-8c7845c8-06e5-4994-a803-f720ed4d45ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030661169 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1030661169
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3139771829
Short name T713
Test name
Test status
Simulation time 21152973 ps
CPU time 0.62 seconds
Started Aug 02 05:11:52 PM PDT 24
Finished Aug 02 05:11:52 PM PDT 24
Peak memory 195108 kb
Host smart-26ff0937-226e-40b2-97f2-0792b884fc48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139771829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3139771829
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3942388047
Short name T687
Test name
Test status
Simulation time 53343987 ps
CPU time 0.72 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:03 PM PDT 24
Peak memory 197392 kb
Host smart-be080a1a-d15e-4ee1-a0be-18964bb8c41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942388047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.3942388047
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2025788603
Short name T664
Test name
Test status
Simulation time 86664323 ps
CPU time 1.52 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 196516 kb
Host smart-80b47ff5-99d4-4c80-aa4c-0a92add4a778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025788603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2025788603
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.863689459
Short name T61
Test name
Test status
Simulation time 532845930 ps
CPU time 1.56 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 200688 kb
Host smart-68cb8e06-f026-4ada-b9d4-826945deb99f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863689459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err
.863689459
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1414599339
Short name T688
Test name
Test status
Simulation time 91260511 ps
CPU time 0.78 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 195292 kb
Host smart-f9250e67-0614-45d8-9f83-cd52d92ca90b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414599339 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1414599339
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.678011151
Short name T107
Test name
Test status
Simulation time 44669947 ps
CPU time 0.63 seconds
Started Aug 02 05:11:52 PM PDT 24
Finished Aug 02 05:11:53 PM PDT 24
Peak memory 195192 kb
Host smart-f682bb3a-1307-41f4-ab04-375833e8c5a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678011151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.678011151
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1821171069
Short name T632
Test name
Test status
Simulation time 24830665 ps
CPU time 0.6 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 195000 kb
Host smart-57f87be7-6eb6-440c-b505-4704508ded83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821171069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1821171069
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.592068802
Short name T643
Test name
Test status
Simulation time 45974454 ps
CPU time 0.89 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 198304 kb
Host smart-ee298fd1-cbe2-42cf-9383-e4f7e275a2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592068802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.592068802
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1984373810
Short name T719
Test name
Test status
Simulation time 109964724 ps
CPU time 2.09 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 196560 kb
Host smart-3f08d94c-12b6-43d9-a936-46453c447156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984373810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1984373810
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3119648287
Short name T638
Test name
Test status
Simulation time 95868613 ps
CPU time 1.1 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:07 PM PDT 24
Peak memory 200240 kb
Host smart-ca765212-eb7d-4828-89f4-0fa7572af422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119648287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3119648287
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.468252660
Short name T689
Test name
Test status
Simulation time 37481177 ps
CPU time 0.89 seconds
Started Aug 02 05:11:53 PM PDT 24
Finished Aug 02 05:11:54 PM PDT 24
Peak memory 195300 kb
Host smart-eb97c767-e996-454e-8ee9-8bb441bb52ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468252660 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.468252660
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3290161646
Short name T98
Test name
Test status
Simulation time 18932707 ps
CPU time 0.64 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 197336 kb
Host smart-9988fade-5b4b-49a1-8c35-81727b761ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290161646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3290161646
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3977963485
Short name T699
Test name
Test status
Simulation time 47014162 ps
CPU time 0.67 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 195036 kb
Host smart-2c136e45-1469-4ff3-ac70-195c4d7a6b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977963485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3977963485
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3766735326
Short name T120
Test name
Test status
Simulation time 39813015 ps
CPU time 0.86 seconds
Started Aug 02 05:11:52 PM PDT 24
Finished Aug 02 05:11:53 PM PDT 24
Peak memory 195188 kb
Host smart-4ed4cf88-c53d-43ed-82d6-61170ca4e939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766735326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3766735326
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.116637203
Short name T660
Test name
Test status
Simulation time 144970321 ps
CPU time 1.1 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 200460 kb
Host smart-bdf9899a-a912-47e7-97f7-41840ff3b9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116637203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.116637203
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2411806977
Short name T661
Test name
Test status
Simulation time 445624996 ps
CPU time 1.58 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 200728 kb
Host smart-8ee84c54-c519-4b90-9d94-d23f43ecea0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411806977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2411806977
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3785694601
Short name T108
Test name
Test status
Simulation time 42473605 ps
CPU time 1 seconds
Started Aug 02 05:11:42 PM PDT 24
Finished Aug 02 05:11:43 PM PDT 24
Peak memory 198776 kb
Host smart-e5dc40bd-a489-4083-a203-1a282fa6dbb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785694601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
785694601
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1702818564
Short name T114
Test name
Test status
Simulation time 152651636 ps
CPU time 1.74 seconds
Started Aug 02 05:11:43 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195228 kb
Host smart-0dfbf7db-9875-43d9-b25c-9dd6ef50c434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702818564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1
702818564
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1350248372
Short name T81
Test name
Test status
Simulation time 34730876 ps
CPU time 0.7 seconds
Started Aug 02 05:11:26 PM PDT 24
Finished Aug 02 05:11:27 PM PDT 24
Peak memory 196208 kb
Host smart-ab825c4f-41ab-4a2d-8095-fe5565624560
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350248372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
350248372
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.693653529
Short name T666
Test name
Test status
Simulation time 58900522 ps
CPU time 1 seconds
Started Aug 02 05:11:28 PM PDT 24
Finished Aug 02 05:11:29 PM PDT 24
Peak memory 195376 kb
Host smart-cf8fa837-493a-404d-83c8-e74b3cb80ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693653529 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.693653529
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2308532165
Short name T734
Test name
Test status
Simulation time 21063725 ps
CPU time 0.75 seconds
Started Aug 02 05:11:30 PM PDT 24
Finished Aug 02 05:11:31 PM PDT 24
Peak memory 197364 kb
Host smart-60122482-85d2-4c09-9515-3c4bab04ab75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308532165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2308532165
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3376619205
Short name T684
Test name
Test status
Simulation time 16440161 ps
CPU time 0.62 seconds
Started Aug 02 05:11:30 PM PDT 24
Finished Aug 02 05:11:31 PM PDT 24
Peak memory 195068 kb
Host smart-4973b01b-b7a2-4df0-8e29-3c9e3c8da957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376619205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3376619205
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2770889440
Short name T692
Test name
Test status
Simulation time 31886640 ps
CPU time 0.86 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 199872 kb
Host smart-29f50594-75ae-4a61-8923-c4754c9a6228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770889440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2770889440
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.928677058
Short name T645
Test name
Test status
Simulation time 131494763 ps
CPU time 1.96 seconds
Started Aug 02 05:11:26 PM PDT 24
Finished Aug 02 05:11:29 PM PDT 24
Peak memory 200764 kb
Host smart-8786c2a3-126c-41f6-b562-2a0ad88ce8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928677058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.928677058
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.891187712
Short name T145
Test name
Test status
Simulation time 199804076 ps
CPU time 1.08 seconds
Started Aug 02 05:11:32 PM PDT 24
Finished Aug 02 05:11:38 PM PDT 24
Peak memory 200420 kb
Host smart-6e1b307a-5272-4db5-9309-2755f66ea8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891187712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
891187712
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2376343400
Short name T707
Test name
Test status
Simulation time 23437387 ps
CPU time 0.62 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195052 kb
Host smart-6caa1edf-7386-4496-9ede-e1826b1ec120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376343400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2376343400
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2715687214
Short name T636
Test name
Test status
Simulation time 19511014 ps
CPU time 0.65 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 195096 kb
Host smart-736cbd7e-f68c-4f47-aa81-3f30733b7710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715687214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2715687214
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.484773208
Short name T151
Test name
Test status
Simulation time 24414371 ps
CPU time 0.61 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195056 kb
Host smart-0fbe3f10-005c-4338-88d2-08cfc173d402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484773208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.484773208
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.4003978932
Short name T714
Test name
Test status
Simulation time 30378201 ps
CPU time 0.58 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 195092 kb
Host smart-84a3f99e-5810-4c20-9c74-00804c032d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003978932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.4003978932
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2232830320
Short name T77
Test name
Test status
Simulation time 18223018 ps
CPU time 0.62 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 194976 kb
Host smart-e83b8f92-42bc-4f56-ac8f-97a6841bc305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232830320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2232830320
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1421973744
Short name T671
Test name
Test status
Simulation time 19524067 ps
CPU time 0.61 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 195096 kb
Host smart-eb57161a-8ada-4bf8-9bc3-cac1b5aab540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421973744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1421973744
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1694141783
Short name T716
Test name
Test status
Simulation time 20144268 ps
CPU time 0.63 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195096 kb
Host smart-318d35e9-e100-4810-a43b-45b58ef449bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694141783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1694141783
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1355063165
Short name T723
Test name
Test status
Simulation time 16781511 ps
CPU time 0.59 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 195084 kb
Host smart-c63dbb62-5211-4a4d-a6f4-0ac717f9af5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355063165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.1355063165
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.544788571
Short name T672
Test name
Test status
Simulation time 44613767 ps
CPU time 0.65 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 195036 kb
Host smart-92c89a7a-ff5a-45ba-844c-2e37e197e7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544788571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.544788571
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1729133300
Short name T685
Test name
Test status
Simulation time 42477148 ps
CPU time 0.6 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 195080 kb
Host smart-2e41feb6-1f72-42e7-ad72-77c88a23ef27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729133300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1729133300
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2142280548
Short name T79
Test name
Test status
Simulation time 20563805 ps
CPU time 0.76 seconds
Started Aug 02 05:11:38 PM PDT 24
Finished Aug 02 05:11:39 PM PDT 24
Peak memory 195072 kb
Host smart-b78edc4f-e75a-4775-ae25-ae031112c6e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142280548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2
142280548
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2689297527
Short name T680
Test name
Test status
Simulation time 116472921 ps
CPU time 1.99 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:35 PM PDT 24
Peak memory 195296 kb
Host smart-0caf505c-cabe-4196-861f-df57c85ac99f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689297527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
689297527
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2925275760
Short name T722
Test name
Test status
Simulation time 253743068 ps
CPU time 0.67 seconds
Started Aug 02 05:11:34 PM PDT 24
Finished Aug 02 05:11:35 PM PDT 24
Peak memory 197292 kb
Host smart-ce929b33-011b-437f-a1e5-060b731e9e36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925275760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
925275760
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.455923327
Short name T701
Test name
Test status
Simulation time 41843247 ps
CPU time 0.85 seconds
Started Aug 02 05:11:39 PM PDT 24
Finished Aug 02 05:11:40 PM PDT 24
Peak memory 195312 kb
Host smart-cb20860f-0ba3-4061-b0ea-ad6f7c04b824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455923327 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.455923327
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.4068918087
Short name T677
Test name
Test status
Simulation time 55918397 ps
CPU time 0.61 seconds
Started Aug 02 05:11:29 PM PDT 24
Finished Aug 02 05:11:38 PM PDT 24
Peak memory 197296 kb
Host smart-def7f6ae-6d35-48e7-a694-b64ba1a01a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068918087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.4068918087
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1310342446
Short name T639
Test name
Test status
Simulation time 23022058 ps
CPU time 0.62 seconds
Started Aug 02 05:11:39 PM PDT 24
Finished Aug 02 05:11:39 PM PDT 24
Peak memory 195096 kb
Host smart-32508787-4144-48e0-b896-2f9f9dc32dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310342446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1310342446
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1350332956
Short name T686
Test name
Test status
Simulation time 37201298 ps
CPU time 0.72 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:33 PM PDT 24
Peak memory 197368 kb
Host smart-33f5917f-7a72-4611-a334-8672ce036d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350332956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.1350332956
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2283550679
Short name T75
Test name
Test status
Simulation time 86442825 ps
CPU time 1.35 seconds
Started Aug 02 05:11:34 PM PDT 24
Finished Aug 02 05:11:35 PM PDT 24
Peak memory 195524 kb
Host smart-363e64ad-2346-4455-87ec-c3a534dccc66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283550679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2283550679
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2604055758
Short name T662
Test name
Test status
Simulation time 131052170 ps
CPU time 1.06 seconds
Started Aug 02 05:11:40 PM PDT 24
Finished Aug 02 05:11:41 PM PDT 24
Peak memory 200108 kb
Host smart-b650062e-5107-4e0e-a8c5-ca712265dc39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604055758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2604055758
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2827639925
Short name T673
Test name
Test status
Simulation time 84565387 ps
CPU time 0.63 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 194996 kb
Host smart-6a4b8eee-b9a0-47de-b30a-ea4a5b862f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827639925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.2827639925
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4063969709
Short name T731
Test name
Test status
Simulation time 16772045 ps
CPU time 0.62 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:44 PM PDT 24
Peak memory 195108 kb
Host smart-b72dbac5-d669-4978-b011-599631bcecb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063969709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.4063969709
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1309859619
Short name T682
Test name
Test status
Simulation time 30880254 ps
CPU time 0.63 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 194996 kb
Host smart-cba25c57-7a48-44b6-9665-6513a0d5c0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309859619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1309859619
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3746120746
Short name T681
Test name
Test status
Simulation time 21519808 ps
CPU time 0.63 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 195084 kb
Host smart-4348febb-00e0-47b3-b3ec-e9505a0c1809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746120746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3746120746
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3201154283
Short name T736
Test name
Test status
Simulation time 23667042 ps
CPU time 0.6 seconds
Started Aug 02 05:11:42 PM PDT 24
Finished Aug 02 05:11:43 PM PDT 24
Peak memory 195080 kb
Host smart-b26fdb62-5fdd-4e25-a986-18580dc78ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201154283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3201154283
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2770291777
Short name T153
Test name
Test status
Simulation time 61164115 ps
CPU time 0.63 seconds
Started Aug 02 05:11:49 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195100 kb
Host smart-a3564034-861d-4f01-9b85-ddef6f87a45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770291777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2770291777
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2294408023
Short name T149
Test name
Test status
Simulation time 34914613 ps
CPU time 0.61 seconds
Started Aug 02 05:11:55 PM PDT 24
Finished Aug 02 05:11:55 PM PDT 24
Peak memory 195100 kb
Host smart-46ef973d-fd97-4c7d-9e50-9e984ba6c492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294408023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2294408023
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2008276217
Short name T700
Test name
Test status
Simulation time 41210037 ps
CPU time 0.6 seconds
Started Aug 02 05:11:53 PM PDT 24
Finished Aug 02 05:11:53 PM PDT 24
Peak memory 195096 kb
Host smart-7a4d249d-325f-4f62-a72f-aa8cf361865b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008276217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2008276217
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1852844236
Short name T630
Test name
Test status
Simulation time 161168273 ps
CPU time 0.63 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 195088 kb
Host smart-fe3aef63-a826-4ef2-94d7-836b20ad8116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852844236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1852844236
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3886284431
Short name T725
Test name
Test status
Simulation time 45107030 ps
CPU time 0.61 seconds
Started Aug 02 05:11:53 PM PDT 24
Finished Aug 02 05:11:54 PM PDT 24
Peak memory 195072 kb
Host smart-f3a0e69a-a0da-47cd-bf30-0e49179151b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886284431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3886284431
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2683899530
Short name T112
Test name
Test status
Simulation time 49678644 ps
CPU time 1 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 198900 kb
Host smart-8a2067f5-745c-41c5-80af-1a1f65e263bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683899530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2
683899530
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2298893118
Short name T111
Test name
Test status
Simulation time 266340181 ps
CPU time 2.86 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 195332 kb
Host smart-b0e87ccf-5a32-47a0-b5d3-faea52c9f93e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298893118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2
298893118
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.516762601
Short name T105
Test name
Test status
Simulation time 23905500 ps
CPU time 0.65 seconds
Started Aug 02 05:11:35 PM PDT 24
Finished Aug 02 05:11:36 PM PDT 24
Peak memory 198328 kb
Host smart-baefb52f-e446-40d5-bde6-f0ece7aad35c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516762601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.516762601
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3507222311
Short name T646
Test name
Test status
Simulation time 41897939 ps
CPU time 0.77 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 195252 kb
Host smart-5efe4e28-c1d7-45de-86e2-2cdf39a1f624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507222311 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3507222311
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3571466372
Short name T70
Test name
Test status
Simulation time 22170146 ps
CPU time 0.67 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195192 kb
Host smart-258185a0-5deb-4b0b-9691-42aa97979dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571466372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3571466372
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3659839152
Short name T740
Test name
Test status
Simulation time 28547651 ps
CPU time 0.79 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 199908 kb
Host smart-3d95cb6f-db95-4770-8c39-cdba2249b40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659839152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3659839152
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.830170086
Short name T74
Test name
Test status
Simulation time 39063327 ps
CPU time 1.74 seconds
Started Aug 02 05:11:26 PM PDT 24
Finished Aug 02 05:11:28 PM PDT 24
Peak memory 197548 kb
Host smart-cb5ad612-7115-496b-a595-abf3dad8321d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830170086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.830170086
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.810022902
Short name T715
Test name
Test status
Simulation time 188162366 ps
CPU time 1.61 seconds
Started Aug 02 05:12:01 PM PDT 24
Finished Aug 02 05:12:03 PM PDT 24
Peak memory 200684 kb
Host smart-f984836f-2326-4118-a493-cbb78fa2e891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810022902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
810022902
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1517924106
Short name T654
Test name
Test status
Simulation time 21230845 ps
CPU time 0.62 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 194996 kb
Host smart-cb55e020-926b-4938-a428-ecf6548c18ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517924106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1517924106
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1544843220
Short name T652
Test name
Test status
Simulation time 57612163 ps
CPU time 0.62 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 194976 kb
Host smart-ee996008-43bf-4206-93e0-fc62943eb37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544843220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1544843220
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1845685448
Short name T727
Test name
Test status
Simulation time 31310220 ps
CPU time 0.62 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 195036 kb
Host smart-9c975a6f-5a7e-4deb-b0be-c083dd8d04f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845685448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1845685448
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1604115048
Short name T78
Test name
Test status
Simulation time 18422385 ps
CPU time 0.59 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 195076 kb
Host smart-1532a492-b8a6-4e01-a1a0-fa80bd4a341f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604115048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1604115048
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3912640213
Short name T633
Test name
Test status
Simulation time 124741237 ps
CPU time 0.62 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 195036 kb
Host smart-3549a68d-f1dc-4944-a21b-c4badd7055f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912640213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3912640213
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2263777899
Short name T674
Test name
Test status
Simulation time 18473103 ps
CPU time 0.61 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:11:56 PM PDT 24
Peak memory 195164 kb
Host smart-4b239364-554a-4fd3-a8b0-a6d583172ad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263777899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.2263777899
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2613538780
Short name T147
Test name
Test status
Simulation time 31172920 ps
CPU time 0.6 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 194972 kb
Host smart-03b7e9dc-40d5-460e-a5d6-843c28a9bfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613538780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.2613538780
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1128727160
Short name T641
Test name
Test status
Simulation time 70904959 ps
CPU time 0.59 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 195100 kb
Host smart-c9f0672f-19db-4e61-a4a9-ccd0b1683c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128727160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1128727160
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3244237865
Short name T735
Test name
Test status
Simulation time 24999029 ps
CPU time 0.59 seconds
Started Aug 02 05:12:03 PM PDT 24
Finished Aug 02 05:12:04 PM PDT 24
Peak memory 195120 kb
Host smart-03736697-8a99-4209-96a5-eb53e3222804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244237865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3244237865
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.958900384
Short name T642
Test name
Test status
Simulation time 40814566 ps
CPU time 0.62 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 195052 kb
Host smart-990ecda7-df8d-4238-a95f-e915940d98f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958900384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.958900384
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.851327404
Short name T721
Test name
Test status
Simulation time 38029089 ps
CPU time 0.97 seconds
Started Aug 02 05:11:39 PM PDT 24
Finished Aug 02 05:11:40 PM PDT 24
Peak memory 195288 kb
Host smart-3a32fc75-5482-4302-a2f0-b0991d460439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851327404 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.851327404
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1840598963
Short name T690
Test name
Test status
Simulation time 20938933 ps
CPU time 0.66 seconds
Started Aug 02 05:11:36 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 195140 kb
Host smart-8224a239-5ac7-4887-a6d2-91eb12e3653f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840598963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1840598963
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.769930550
Short name T148
Test name
Test status
Simulation time 40933897 ps
CPU time 0.59 seconds
Started Aug 02 05:11:52 PM PDT 24
Finished Aug 02 05:11:53 PM PDT 24
Peak memory 195000 kb
Host smart-eb336af6-a3e1-476f-befb-60d9e8852829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769930550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.769930550
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2161281180
Short name T655
Test name
Test status
Simulation time 78052577 ps
CPU time 0.73 seconds
Started Aug 02 05:11:33 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 198676 kb
Host smart-a3ae4a51-6e69-4fa4-9f5c-f290037d732c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161281180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2161281180
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2986490698
Short name T637
Test name
Test status
Simulation time 65187290 ps
CPU time 1.61 seconds
Started Aug 02 05:12:03 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 196732 kb
Host smart-460519b8-54b9-423c-ad81-22eb52b4c889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986490698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2986490698
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2317470888
Short name T62
Test name
Test status
Simulation time 760340366 ps
CPU time 1.52 seconds
Started Aug 02 05:11:42 PM PDT 24
Finished Aug 02 05:11:44 PM PDT 24
Peak memory 200608 kb
Host smart-7e5109a2-5b9a-4995-a5dd-badc1af51885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317470888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2317470888
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1786792750
Short name T695
Test name
Test status
Simulation time 86584639 ps
CPU time 0.85 seconds
Started Aug 02 05:11:43 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 200536 kb
Host smart-c86c6920-6920-47c9-8957-c14ae7e1d168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786792750 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1786792750
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3484705133
Short name T104
Test name
Test status
Simulation time 32896327 ps
CPU time 0.61 seconds
Started Aug 02 05:11:32 PM PDT 24
Finished Aug 02 05:11:33 PM PDT 24
Peak memory 197280 kb
Host smart-7937c3d4-dcd0-4592-ba4c-3702969d1c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484705133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3484705133
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2870447250
Short name T648
Test name
Test status
Simulation time 21872963 ps
CPU time 0.63 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195092 kb
Host smart-99f28f5e-4d80-4169-aff1-9a32c4d98842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870447250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2870447250
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.709647765
Short name T711
Test name
Test status
Simulation time 52633718 ps
CPU time 0.77 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 195112 kb
Host smart-feeb8c3f-7326-4803-bc2f-19d5b1edb386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709647765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.709647765
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.749876999
Short name T73
Test name
Test status
Simulation time 230726386 ps
CPU time 1.42 seconds
Started Aug 02 05:11:46 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 195380 kb
Host smart-5e50cc64-9deb-4db3-acce-49c46d01d947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749876999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.749876999
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1771511793
Short name T85
Test name
Test status
Simulation time 169866881 ps
CPU time 1.64 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 200480 kb
Host smart-8b6f1fc4-545f-4721-bb34-3c91eac92c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771511793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1771511793
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4174895798
Short name T706
Test name
Test status
Simulation time 94984699 ps
CPU time 1.1 seconds
Started Aug 02 05:11:31 PM PDT 24
Finished Aug 02 05:11:32 PM PDT 24
Peak memory 200568 kb
Host smart-192a8108-d6fd-42ce-a2c5-a4befff9218a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174895798 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.4174895798
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1024345367
Short name T729
Test name
Test status
Simulation time 18583395 ps
CPU time 0.64 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 197364 kb
Host smart-6dc5a6b6-6a15-42b4-986c-38db65957f4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024345367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1024345367
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2091880746
Short name T712
Test name
Test status
Simulation time 52752219 ps
CPU time 0.6 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:45 PM PDT 24
Peak memory 195080 kb
Host smart-4dac7873-fdb0-46d3-89c6-7e537ef7e3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091880746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2091880746
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1003123139
Short name T115
Test name
Test status
Simulation time 20983196 ps
CPU time 0.69 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 195104 kb
Host smart-717bc69e-4f01-4291-b1db-b047aad8cd62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003123139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1003123139
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3800581497
Short name T691
Test name
Test status
Simulation time 31648890 ps
CPU time 1.36 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:08 PM PDT 24
Peak memory 196380 kb
Host smart-81bf7fc1-ba42-4164-97f1-676ba41666f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800581497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3800581497
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.4108491300
Short name T86
Test name
Test status
Simulation time 100675715 ps
CPU time 1.08 seconds
Started Aug 02 05:11:36 PM PDT 24
Finished Aug 02 05:11:37 PM PDT 24
Peak memory 200348 kb
Host smart-bd62da65-ab90-4530-9946-3a0ba6f4b249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108491300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.4108491300
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2297182322
Short name T100
Test name
Test status
Simulation time 42356134 ps
CPU time 0.84 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:54 PM PDT 24
Peak memory 195208 kb
Host smart-d1fa32ca-02ca-40bd-8baf-c566896a330e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297182322 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2297182322
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2548203171
Short name T694
Test name
Test status
Simulation time 41565671 ps
CPU time 0.61 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 195140 kb
Host smart-c6034033-e845-4089-b052-7da6fb787963
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548203171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2548203171
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.812165682
Short name T697
Test name
Test status
Simulation time 46418754 ps
CPU time 0.59 seconds
Started Aug 02 05:11:43 PM PDT 24
Finished Aug 02 05:11:44 PM PDT 24
Peak memory 194992 kb
Host smart-870de788-8878-4ebb-ba96-05e42ce258cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812165682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.812165682
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2299422787
Short name T119
Test name
Test status
Simulation time 29822842 ps
CPU time 0.85 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:00 PM PDT 24
Peak memory 195036 kb
Host smart-3d1dc2b0-f8f1-4831-8bd2-6ab05c973258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299422787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2299422787
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3806600279
Short name T724
Test name
Test status
Simulation time 229053257 ps
CPU time 1.53 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 196468 kb
Host smart-3fe09065-1d1e-49ba-96f7-5bb331803e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806600279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3806600279
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1582069297
Short name T732
Test name
Test status
Simulation time 190008602 ps
CPU time 1.62 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 200688 kb
Host smart-ed5f6fe0-fb3f-489a-829d-da9cb7348bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582069297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.1582069297
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4218307018
Short name T739
Test name
Test status
Simulation time 64274819 ps
CPU time 0.93 seconds
Started Aug 02 05:11:31 PM PDT 24
Finished Aug 02 05:11:32 PM PDT 24
Peak memory 195264 kb
Host smart-1de235db-a464-4231-82dc-20a2a2263115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218307018 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.4218307018
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1341084948
Short name T106
Test name
Test status
Simulation time 58080325 ps
CPU time 0.62 seconds
Started Aug 02 05:11:54 PM PDT 24
Finished Aug 02 05:11:55 PM PDT 24
Peak memory 195132 kb
Host smart-4c0bfd73-98dc-4375-9c84-c8bc35705cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341084948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1341084948
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3767872399
Short name T631
Test name
Test status
Simulation time 32131614 ps
CPU time 0.61 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:46 PM PDT 24
Peak memory 195048 kb
Host smart-f1efcd0d-fd17-4c97-a452-8a81192ca09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767872399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3767872399
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2199911821
Short name T118
Test name
Test status
Simulation time 26102989 ps
CPU time 0.77 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 198604 kb
Host smart-217c14a5-dda9-484a-9840-2eedca7d3b5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199911821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2199911821
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2781590361
Short name T710
Test name
Test status
Simulation time 189398266 ps
CPU time 1.46 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:49 PM PDT 24
Peak memory 196384 kb
Host smart-51de79ef-d4d5-46a9-b29c-1af3fc56dd28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781590361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2781590361
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.479823485
Short name T567
Test name
Test status
Simulation time 68886984 ps
CPU time 0.85 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 200372 kb
Host smart-87fc2ea0-d816-4579-b1f6-fdf47be47f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479823485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.479823485
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.208876660
Short name T310
Test name
Test status
Simulation time 30642281 ps
CPU time 0.58 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 197380 kb
Host smart-bdb19e38-f346-41d8-bafb-aae10de870f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208876660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_m
alfunc.208876660
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.1981604111
Short name T488
Test name
Test status
Simulation time 567339452 ps
CPU time 0.96 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 198168 kb
Host smart-081d21ee-57e9-4ea7-8013-38a60a88ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981604111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.1981604111
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.801637522
Short name T404
Test name
Test status
Simulation time 63393003 ps
CPU time 0.64 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 198108 kb
Host smart-e726a603-73d6-430b-8667-cc79fdfba0da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801637522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.801637522
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3495420834
Short name T393
Test name
Test status
Simulation time 45092320 ps
CPU time 0.62 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 198076 kb
Host smart-0ee227e8-2dd7-4123-86df-561a432930a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495420834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3495420834
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3240485741
Short name T314
Test name
Test status
Simulation time 97057908 ps
CPU time 0.7 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 199256 kb
Host smart-3190cb48-ae51-4f3c-8652-5c145f00730c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240485741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3240485741
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3463773606
Short name T345
Test name
Test status
Simulation time 109078155 ps
CPU time 0.92 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:06 PM PDT 24
Peak memory 209392 kb
Host smart-ba6601e8-95af-4277-ab8c-dfdaee30e467
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463773606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3463773606
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2480976009
Short name T38
Test name
Test status
Simulation time 869863556 ps
CPU time 1.47 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 217936 kb
Host smart-a023978d-b1f4-419a-bfdf-a432df827f52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480976009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2480976009
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.4111839741
Short name T347
Test name
Test status
Simulation time 102390554 ps
CPU time 0.72 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 198024 kb
Host smart-295dca17-41e8-48b1-a17c-538d515b2255
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111839741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4111839741
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2322354649
Short name T344
Test name
Test status
Simulation time 30652338 ps
CPU time 0.64 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 198600 kb
Host smart-280e5561-6ff9-4c4b-b228-2e69adcb041a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322354649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2322354649
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.850127602
Short name T124
Test name
Test status
Simulation time 26711483 ps
CPU time 0.81 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 198908 kb
Host smart-cd5bea68-16a8-4c87-b13c-0d22e29c6e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850127602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.850127602
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1252891906
Short name T412
Test name
Test status
Simulation time 38284893 ps
CPU time 0.59 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 198016 kb
Host smart-3e2bd3d6-0a4d-493b-9197-3ddeacf6e38d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252891906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1252891906
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1494147854
Short name T514
Test name
Test status
Simulation time 1066824286 ps
CPU time 0.93 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 198080 kb
Host smart-7d1e27d3-42a1-4aeb-bca2-e46bf5dfd074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494147854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1494147854
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3524782892
Short name T408
Test name
Test status
Simulation time 60169402 ps
CPU time 0.6 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198184 kb
Host smart-0aac3542-0452-4d06-84aa-1b41f0f78348
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524782892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3524782892
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2238657387
Short name T55
Test name
Test status
Simulation time 42453469 ps
CPU time 0.66 seconds
Started Aug 02 05:14:52 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 198020 kb
Host smart-cc376d19-767f-421b-ac35-c3e2cb05f62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238657387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2238657387
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1890355256
Short name T91
Test name
Test status
Simulation time 43433371 ps
CPU time 0.7 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 201400 kb
Host smart-72db94c6-ec3d-408d-b586-37e86e8990c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890355256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1890355256
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.133128126
Short name T339
Test name
Test status
Simulation time 38377576 ps
CPU time 0.67 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 199128 kb
Host smart-67fc8644-c060-4e71-8509-c352f2f2c9de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133128126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.133128126
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2754332958
Short name T388
Test name
Test status
Simulation time 418658755 ps
CPU time 0.77 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 209512 kb
Host smart-167d044b-cbef-4ecb-83bc-6e3b8fb9587b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754332958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2754332958
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3027441312
Short name T141
Test name
Test status
Simulation time 30218289 ps
CPU time 0.7 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:50 PM PDT 24
Peak memory 199512 kb
Host smart-5f89aad3-0883-43e2-91d7-e332bf45cc2c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027441312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.3027441312
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3445454613
Short name T365
Test name
Test status
Simulation time 57985537 ps
CPU time 0.82 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 198320 kb
Host smart-cb58f2e0-7367-40e5-9d67-73152be2d4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445454613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3445454613
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3044892835
Short name T357
Test name
Test status
Simulation time 32656915 ps
CPU time 0.64 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:45 PM PDT 24
Peak memory 198568 kb
Host smart-4e1b8149-d0f7-419f-935a-d644c6224ecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044892835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3044892835
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.2074688164
Short name T293
Test name
Test status
Simulation time 43379141 ps
CPU time 0.68 seconds
Started Aug 02 05:15:05 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 199184 kb
Host smart-ed1d4fd4-ceb7-466a-8a86-f4badce78902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074688164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.2074688164
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.817005883
Short name T337
Test name
Test status
Simulation time 51764182 ps
CPU time 0.75 seconds
Started Aug 02 05:15:09 PM PDT 24
Finished Aug 02 05:15:10 PM PDT 24
Peak memory 198912 kb
Host smart-def5b5cf-6de2-4c61-8fbd-2042642f63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817005883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.817005883
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.2054776505
Short name T379
Test name
Test status
Simulation time 161800784 ps
CPU time 0.95 seconds
Started Aug 02 05:15:17 PM PDT 24
Finished Aug 02 05:15:18 PM PDT 24
Peak memory 198120 kb
Host smart-3bdf2e35-1d91-4007-bda2-096b6c406b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054776505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2054776505
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.1522984354
Short name T541
Test name
Test status
Simulation time 52547730 ps
CPU time 0.61 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:08 PM PDT 24
Peak memory 197464 kb
Host smart-511db74e-e3f3-4307-a942-548c67906b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522984354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1522984354
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2030365901
Short name T230
Test name
Test status
Simulation time 48231517 ps
CPU time 0.61 seconds
Started Aug 02 05:15:47 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 198128 kb
Host smart-864c8114-c953-4c72-bd48-10e7afecde28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030365901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2030365901
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2731314738
Short name T326
Test name
Test status
Simulation time 152302400 ps
CPU time 0.72 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 198412 kb
Host smart-20ebcf4b-5683-4e3b-9c5c-066a9056258e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731314738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2731314738
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2406604688
Short name T224
Test name
Test status
Simulation time 96157085 ps
CPU time 1.01 seconds
Started Aug 02 05:15:13 PM PDT 24
Finished Aug 02 05:15:15 PM PDT 24
Peak memory 209556 kb
Host smart-e4e84ece-7933-4847-9ac3-9caba88593f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406604688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2406604688
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2268316702
Short name T511
Test name
Test status
Simulation time 78691032 ps
CPU time 0.75 seconds
Started Aug 02 05:15:06 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 197968 kb
Host smart-a528d0ba-3cbb-438e-bbfe-f6d71c597d85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268316702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2268316702
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2000159087
Short name T250
Test name
Test status
Simulation time 109808824 ps
CPU time 0.6 seconds
Started Aug 02 05:14:57 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 198592 kb
Host smart-477ed9a6-ce4e-4c58-87af-c7b5ac01b60a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000159087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2000159087
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.367749554
Short name T498
Test name
Test status
Simulation time 65642833 ps
CPU time 0.89 seconds
Started Aug 02 05:15:24 PM PDT 24
Finished Aug 02 05:15:25 PM PDT 24
Peak memory 200092 kb
Host smart-ffbee6c3-44fb-4357-ba4a-7946d902cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367749554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.367749554
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.798579335
Short name T159
Test name
Test status
Simulation time 100367359 ps
CPU time 0.69 seconds
Started Aug 02 05:15:32 PM PDT 24
Finished Aug 02 05:15:33 PM PDT 24
Peak memory 198468 kb
Host smart-195ea6a3-be27-468f-9834-8d30ad9cc9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798579335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.798579335
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.4132192789
Short name T369
Test name
Test status
Simulation time 37529674 ps
CPU time 0.59 seconds
Started Aug 02 05:15:12 PM PDT 24
Finished Aug 02 05:15:13 PM PDT 24
Peak memory 198028 kb
Host smart-2f78fcdc-8f22-4026-81bc-f8731f944e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132192789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.4132192789
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1291240680
Short name T220
Test name
Test status
Simulation time 163536158 ps
CPU time 0.96 seconds
Started Aug 02 05:15:16 PM PDT 24
Finished Aug 02 05:15:17 PM PDT 24
Peak memory 198456 kb
Host smart-5c6ce9e3-d47b-4274-9b16-39ab60fd8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291240680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1291240680
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1724439737
Short name T315
Test name
Test status
Simulation time 30695378 ps
CPU time 0.64 seconds
Started Aug 02 05:15:11 PM PDT 24
Finished Aug 02 05:15:12 PM PDT 24
Peak memory 198020 kb
Host smart-0ff2afc7-7249-4b23-bf1a-ab4664be0065
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724439737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1724439737
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1000608144
Short name T323
Test name
Test status
Simulation time 47436502 ps
CPU time 0.6 seconds
Started Aug 02 05:15:26 PM PDT 24
Finished Aug 02 05:15:26 PM PDT 24
Peak memory 198428 kb
Host smart-862caccb-8728-4a57-8ca3-6bb99ecc59d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000608144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1000608144
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.371653675
Short name T167
Test name
Test status
Simulation time 62526109 ps
CPU time 0.64 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 201444 kb
Host smart-6e7106e5-ffea-4971-8900-71c32d6fc9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371653675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.371653675
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3136833402
Short name T574
Test name
Test status
Simulation time 60376243 ps
CPU time 0.87 seconds
Started Aug 02 05:15:31 PM PDT 24
Finished Aug 02 05:15:32 PM PDT 24
Peak memory 198492 kb
Host smart-089654c1-1caa-43cf-83e1-5628a7d2d9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136833402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3136833402
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3754598688
Short name T419
Test name
Test status
Simulation time 119255998 ps
CPU time 0.88 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 209444 kb
Host smart-ba409301-807c-4814-a73d-4632dbfacad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754598688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3754598688
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.5003428
Short name T469
Test name
Test status
Simulation time 301282585 ps
CPU time 0.77 seconds
Started Aug 02 05:15:15 PM PDT 24
Finished Aug 02 05:15:16 PM PDT 24
Peak memory 198136 kb
Host smart-a156d8d2-7967-4b8d-a52a-902684066864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5003428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mu
bi.5003428
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1506948142
Short name T375
Test name
Test status
Simulation time 45781361 ps
CPU time 0.64 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:36 PM PDT 24
Peak memory 198500 kb
Host smart-603b0bd9-c10c-4e5e-91a2-7a14b1438d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506948142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1506948142
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.1092418202
Short name T425
Test name
Test status
Simulation time 144227664 ps
CPU time 0.9 seconds
Started Aug 02 05:15:06 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 200292 kb
Host smart-7ea708e6-ce07-4f16-9a01-eef7147a7cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092418202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1092418202
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1294375054
Short name T500
Test name
Test status
Simulation time 32124614 ps
CPU time 0.59 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 198084 kb
Host smart-8a9bf428-c79d-478e-a2dc-f67e46a05b41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294375054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1294375054
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.24448219
Short name T391
Test name
Test status
Simulation time 157128612 ps
CPU time 0.96 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 198096 kb
Host smart-cfc17764-2c85-49d2-a4fc-34667bad2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24448219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.24448219
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.4065164432
Short name T384
Test name
Test status
Simulation time 286893618 ps
CPU time 0.58 seconds
Started Aug 02 05:15:24 PM PDT 24
Finished Aug 02 05:15:25 PM PDT 24
Peak memory 197472 kb
Host smart-312c2342-c45f-4f5f-bc2c-31a6bbce54a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065164432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.4065164432
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.845881806
Short name T495
Test name
Test status
Simulation time 97249818 ps
CPU time 0.6 seconds
Started Aug 02 05:15:05 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 198160 kb
Host smart-cda8fafb-819d-4abb-95e3-7ebbdd5c8e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845881806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.845881806
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.126910585
Short name T172
Test name
Test status
Simulation time 79470248 ps
CPU time 0.71 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:36 PM PDT 24
Peak memory 201448 kb
Host smart-f33731de-9014-4f7e-bd2a-20931b2e1ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126910585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.126910585
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.599027636
Short name T549
Test name
Test status
Simulation time 108862528 ps
CPU time 0.72 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 199068 kb
Host smart-4ea421d4-306c-4a09-b369-b2b3286510f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599027636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.599027636
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.748772966
Short name T434
Test name
Test status
Simulation time 111446870 ps
CPU time 0.87 seconds
Started Aug 02 05:15:06 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 201360 kb
Host smart-5eadbf73-96e0-46ca-8649-1f302a190bd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748772966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.748772966
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1228019146
Short name T329
Test name
Test status
Simulation time 116575764 ps
CPU time 0.73 seconds
Started Aug 02 05:15:28 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 198128 kb
Host smart-4e3cb376-a42d-4546-b6cc-ab37790f1965
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228019146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1228019146
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3522638223
Short name T41
Test name
Test status
Simulation time 62045328 ps
CPU time 0.64 seconds
Started Aug 02 05:15:15 PM PDT 24
Finished Aug 02 05:15:16 PM PDT 24
Peak memory 199440 kb
Host smart-26d5093a-565c-41c3-91da-e289ca712840
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522638223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3522638223
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.3798729293
Short name T200
Test name
Test status
Simulation time 115687713 ps
CPU time 1.07 seconds
Started Aug 02 05:15:27 PM PDT 24
Finished Aug 02 05:15:28 PM PDT 24
Peak memory 200944 kb
Host smart-37815083-eccd-43e6-ae46-a79c2da5bc48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798729293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.3798729293
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.3292051879
Short name T467
Test name
Test status
Simulation time 36802941 ps
CPU time 1.15 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:35 PM PDT 24
Peak memory 201004 kb
Host smart-39428b35-1343-42cf-bc33-ac72e4d50449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292051879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3292051879
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3809613333
Short name T377
Test name
Test status
Simulation time 109370952 ps
CPU time 0.63 seconds
Started Aug 02 05:15:15 PM PDT 24
Finished Aug 02 05:15:16 PM PDT 24
Peak memory 198336 kb
Host smart-524bd106-c211-46d9-a98e-2709a0b19f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809613333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3809613333
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3152589793
Short name T480
Test name
Test status
Simulation time 31143359 ps
CPU time 0.64 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 197296 kb
Host smart-36c757ef-6d8a-41ad-b30f-8f5bdf1e747f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152589793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3152589793
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.3801494909
Short name T131
Test name
Test status
Simulation time 164848061 ps
CPU time 0.97 seconds
Started Aug 02 05:15:25 PM PDT 24
Finished Aug 02 05:15:26 PM PDT 24
Peak memory 198108 kb
Host smart-a7cd21b1-5f38-482a-8351-18cb66ad44af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801494909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.3801494909
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.749571479
Short name T428
Test name
Test status
Simulation time 62659987 ps
CPU time 0.59 seconds
Started Aug 02 05:15:14 PM PDT 24
Finished Aug 02 05:15:15 PM PDT 24
Peak memory 198124 kb
Host smart-8b2e24f0-77c8-45a0-ae4a-c43d843b1249
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749571479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.749571479
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.1497018148
Short name T333
Test name
Test status
Simulation time 66886855 ps
CPU time 0.59 seconds
Started Aug 02 05:15:14 PM PDT 24
Finished Aug 02 05:15:15 PM PDT 24
Peak memory 198120 kb
Host smart-022cb8c5-6318-4835-b233-d672ca1ec5f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497018148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1497018148
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1597274529
Short name T195
Test name
Test status
Simulation time 77048099 ps
CPU time 0.67 seconds
Started Aug 02 05:15:17 PM PDT 24
Finished Aug 02 05:15:18 PM PDT 24
Peak memory 201412 kb
Host smart-a2d0b4e6-02bc-4bd4-a659-5e8c21b093de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597274529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1597274529
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3904117926
Short name T600
Test name
Test status
Simulation time 130381167 ps
CPU time 0.75 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:35 PM PDT 24
Peak memory 199112 kb
Host smart-4d7cee6a-9b4d-46e9-86e0-7c913bd0de56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904117926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3904117926
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.3186063414
Short name T566
Test name
Test status
Simulation time 187460574 ps
CPU time 0.85 seconds
Started Aug 02 05:15:05 PM PDT 24
Finished Aug 02 05:15:06 PM PDT 24
Peak memory 209572 kb
Host smart-6cfb651b-9807-4d13-8c5e-60ab5fab3a42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186063414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3186063414
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.1869289907
Short name T26
Test name
Test status
Simulation time 71633633 ps
CPU time 0.61 seconds
Started Aug 02 05:15:11 PM PDT 24
Finished Aug 02 05:15:12 PM PDT 24
Peak memory 198356 kb
Host smart-b7cac49e-45ce-4d11-9bd2-b1aa8badc776
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869289907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.1869289907
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.964238356
Short name T596
Test name
Test status
Simulation time 228407462 ps
CPU time 0.67 seconds
Started Aug 02 05:15:44 PM PDT 24
Finished Aug 02 05:15:44 PM PDT 24
Peak memory 198120 kb
Host smart-7c2fbd1c-2e75-4139-a7db-bf4c27da6a64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964238356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.964238356
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.892788173
Short name T424
Test name
Test status
Simulation time 66751169 ps
CPU time 0.62 seconds
Started Aug 02 05:15:05 PM PDT 24
Finished Aug 02 05:15:06 PM PDT 24
Peak memory 198580 kb
Host smart-0564c4a4-ab89-4f1f-9d5c-3b25efae21e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892788173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.892788173
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2539205854
Short name T473
Test name
Test status
Simulation time 30320642 ps
CPU time 0.98 seconds
Started Aug 02 05:15:31 PM PDT 24
Finished Aug 02 05:15:32 PM PDT 24
Peak memory 200780 kb
Host smart-5dd76690-c012-44b1-bd3c-62e8289b44cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539205854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2539205854
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2215691456
Short name T134
Test name
Test status
Simulation time 59786348 ps
CPU time 0.69 seconds
Started Aug 02 05:15:14 PM PDT 24
Finished Aug 02 05:15:15 PM PDT 24
Peak memory 199088 kb
Host smart-d49f629f-11fa-4040-97f8-fee7076fa4b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215691456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2215691456
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1323011502
Short name T589
Test name
Test status
Simulation time 66271359 ps
CPU time 0.57 seconds
Started Aug 02 05:15:17 PM PDT 24
Finished Aug 02 05:15:18 PM PDT 24
Peak memory 197348 kb
Host smart-46c27330-d82b-4c62-821d-08f2fd427f52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323011502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1323011502
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2666290287
Short name T460
Test name
Test status
Simulation time 639285454 ps
CPU time 1 seconds
Started Aug 02 05:15:30 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 198088 kb
Host smart-d44993f2-30a6-4a95-821b-f3c2fffdf346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666290287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2666290287
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.4068611691
Short name T538
Test name
Test status
Simulation time 61302556 ps
CPU time 0.63 seconds
Started Aug 02 05:15:34 PM PDT 24
Finished Aug 02 05:15:35 PM PDT 24
Peak memory 198152 kb
Host smart-92b3cd91-8f4c-4711-b927-7a36af19d10a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068611691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.4068611691
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.145900174
Short name T277
Test name
Test status
Simulation time 24882807 ps
CPU time 0.6 seconds
Started Aug 02 05:15:29 PM PDT 24
Finished Aug 02 05:15:30 PM PDT 24
Peak memory 198084 kb
Host smart-9b0cf7ac-9018-4388-81a5-a60415cec0e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145900174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.145900174
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3673104201
Short name T382
Test name
Test status
Simulation time 44448519 ps
CPU time 0.69 seconds
Started Aug 02 05:15:26 PM PDT 24
Finished Aug 02 05:15:27 PM PDT 24
Peak memory 199024 kb
Host smart-2b4f4398-64f0-4008-baaf-d1b25e55b0d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673104201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3673104201
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3295267866
Short name T607
Test name
Test status
Simulation time 326310606 ps
CPU time 0.83 seconds
Started Aug 02 05:15:41 PM PDT 24
Finished Aug 02 05:15:42 PM PDT 24
Peak memory 209508 kb
Host smart-c1ceae6e-aa1d-43c4-a42a-f6a13e5df963
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295267866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3295267866
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.3119163089
Short name T90
Test name
Test status
Simulation time 27700650 ps
CPU time 0.67 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 199304 kb
Host smart-396b71e9-e65b-40c5-b447-371355f173e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119163089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3119163089
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1262803692
Short name T14
Test name
Test status
Simulation time 21782331 ps
CPU time 0.7 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:36 PM PDT 24
Peak memory 198576 kb
Host smart-8c93b105-55d7-4621-9fac-d399233ed5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262803692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1262803692
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.4265748551
Short name T570
Test name
Test status
Simulation time 250114815 ps
CPU time 0.64 seconds
Started Aug 02 05:15:42 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 198260 kb
Host smart-86f5c9e0-a761-47e0-b5d2-a19c72617a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265748551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.4265748551
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3226208220
Short name T568
Test name
Test status
Simulation time 39244946 ps
CPU time 0.64 seconds
Started Aug 02 05:15:31 PM PDT 24
Finished Aug 02 05:15:32 PM PDT 24
Peak memory 198088 kb
Host smart-f67d10ad-eedb-47c3-8f70-85cb49b4e669
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226208220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.3226208220
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.3764107748
Short name T11
Test name
Test status
Simulation time 319344166 ps
CPU time 0.93 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 198456 kb
Host smart-c5d22851-7677-4776-98e4-3c177bb1fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764107748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3764107748
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.758089385
Short name T334
Test name
Test status
Simulation time 57309366 ps
CPU time 0.62 seconds
Started Aug 02 05:15:32 PM PDT 24
Finished Aug 02 05:15:33 PM PDT 24
Peak memory 197408 kb
Host smart-0727247b-bf62-4d65-aab1-9aaaee973848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758089385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.758089385
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.783602988
Short name T214
Test name
Test status
Simulation time 51376429 ps
CPU time 0.66 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 198080 kb
Host smart-b8debef6-45e9-4147-88e1-6c96c19fd683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783602988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.783602988
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3228847727
Short name T176
Test name
Test status
Simulation time 73157178 ps
CPU time 0.69 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 201228 kb
Host smart-d6e60a35-1a6a-4eea-83e5-8a69e7ebf021
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228847727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3228847727
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2451752617
Short name T501
Test name
Test status
Simulation time 81188925 ps
CPU time 0.86 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 198540 kb
Host smart-cfd49653-0770-4e3c-afda-716b3e76878f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451752617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2451752617
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2754491913
Short name T232
Test name
Test status
Simulation time 157334030 ps
CPU time 0.79 seconds
Started Aug 02 05:15:28 PM PDT 24
Finished Aug 02 05:15:29 PM PDT 24
Peak memory 209508 kb
Host smart-c87160d9-5a73-4392-85ab-8290143210d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754491913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2754491913
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4104882943
Short name T242
Test name
Test status
Simulation time 249174106 ps
CPU time 0.66 seconds
Started Aug 02 05:15:37 PM PDT 24
Finished Aug 02 05:15:38 PM PDT 24
Peak memory 197752 kb
Host smart-97e07b72-84a0-4ceb-b814-a616f5e01ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104882943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4104882943
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1041436496
Short name T516
Test name
Test status
Simulation time 35835098 ps
CPU time 0.66 seconds
Started Aug 02 05:15:24 PM PDT 24
Finished Aug 02 05:15:24 PM PDT 24
Peak memory 199440 kb
Host smart-18f6dd74-dd13-4aa9-b075-2ffe6f3d5271
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041436496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1041436496
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1115669758
Short name T505
Test name
Test status
Simulation time 302141852 ps
CPU time 0.82 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 200136 kb
Host smart-43838561-4116-4c53-a2ab-d7c41908c6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115669758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1115669758
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3885049274
Short name T517
Test name
Test status
Simulation time 64248124 ps
CPU time 0.82 seconds
Started Aug 02 05:15:27 PM PDT 24
Finished Aug 02 05:15:28 PM PDT 24
Peak memory 199012 kb
Host smart-04bfe02f-ee0d-425b-90c8-2b75f0fed510
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885049274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3885049274
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4077072710
Short name T368
Test name
Test status
Simulation time 30009111 ps
CPU time 0.63 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:36 PM PDT 24
Peak memory 198108 kb
Host smart-b56b31e1-54b5-4a60-a21a-95e5a292f1f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077072710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.4077072710
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.1013777022
Short name T317
Test name
Test status
Simulation time 322488004 ps
CPU time 1.01 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:44 PM PDT 24
Peak memory 198156 kb
Host smart-ad5d9759-1592-4e5c-be0f-be3f5a89ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013777022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1013777022
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.549668598
Short name T406
Test name
Test status
Simulation time 44166779 ps
CPU time 0.65 seconds
Started Aug 02 05:15:32 PM PDT 24
Finished Aug 02 05:15:33 PM PDT 24
Peak memory 198056 kb
Host smart-b86e3b14-aa61-4bc6-8351-6fce12850ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549668598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.549668598
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.306173943
Short name T94
Test name
Test status
Simulation time 45113497 ps
CPU time 0.77 seconds
Started Aug 02 05:15:37 PM PDT 24
Finished Aug 02 05:15:38 PM PDT 24
Peak memory 201400 kb
Host smart-e242dee5-d197-42d9-a66e-03cef56aa310
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306173943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invali
d.306173943
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3949753771
Short name T458
Test name
Test status
Simulation time 43376495 ps
CPU time 0.75 seconds
Started Aug 02 05:15:38 PM PDT 24
Finished Aug 02 05:15:39 PM PDT 24
Peak memory 199156 kb
Host smart-d16fe0a3-ed79-4210-8cb1-7c4868c47814
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949753771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3949753771
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2757011298
Short name T453
Test name
Test status
Simulation time 177685380 ps
CPU time 0.76 seconds
Started Aug 02 05:15:22 PM PDT 24
Finished Aug 02 05:15:23 PM PDT 24
Peak memory 209528 kb
Host smart-b05443c8-6e17-4df4-a76a-38671d1aaecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757011298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2757011298
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.980462878
Short name T435
Test name
Test status
Simulation time 83055061 ps
CPU time 0.72 seconds
Started Aug 02 05:15:30 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 198184 kb
Host smart-1dbe59fd-42b0-47a2-b28e-4ba959ffcbf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980462878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.980462878
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.68105163
Short name T221
Test name
Test status
Simulation time 30430892 ps
CPU time 0.68 seconds
Started Aug 02 05:15:38 PM PDT 24
Finished Aug 02 05:15:39 PM PDT 24
Peak memory 199440 kb
Host smart-eb6a41da-eb7a-41c6-b5df-b76574855d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68105163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.68105163
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.523741961
Short name T537
Test name
Test status
Simulation time 29484152 ps
CPU time 0.86 seconds
Started Aug 02 05:15:30 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 200032 kb
Host smart-31e92287-73ee-4731-9e23-bff740ccce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523741961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.523741961
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3764548450
Short name T157
Test name
Test status
Simulation time 57850627 ps
CPU time 0.79 seconds
Started Aug 02 05:15:47 PM PDT 24
Finished Aug 02 05:15:48 PM PDT 24
Peak memory 198592 kb
Host smart-21869675-32a8-49b8-852a-2c2de59959d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764548450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3764548450
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2626901783
Short name T353
Test name
Test status
Simulation time 38263815 ps
CPU time 0.6 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 198084 kb
Host smart-c031b246-572a-4e8a-b5c5-57d3cef7bcb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626901783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2626901783
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.2913948533
Short name T3
Test name
Test status
Simulation time 2489565403 ps
CPU time 0.97 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 198220 kb
Host smart-cbfaf835-693f-4a5f-b964-fbc0433f4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913948533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2913948533
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.1541897643
Short name T295
Test name
Test status
Simulation time 68044477 ps
CPU time 0.64 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 198140 kb
Host smart-fee152ed-eae3-43ee-bda6-509d00e39e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541897643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1541897643
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2083191230
Short name T362
Test name
Test status
Simulation time 25332428 ps
CPU time 0.61 seconds
Started Aug 02 05:15:42 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 198056 kb
Host smart-a6b94128-4c97-4e8c-ad64-29641c38e186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083191230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2083191230
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.4107336505
Short name T216
Test name
Test status
Simulation time 95384682 ps
CPU time 0.69 seconds
Started Aug 02 05:15:29 PM PDT 24
Finished Aug 02 05:15:30 PM PDT 24
Peak memory 198496 kb
Host smart-684fa14a-ece9-4e40-8898-8873cca299e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107336505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.4107336505
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.3661661158
Short name T44
Test name
Test status
Simulation time 113850619 ps
CPU time 0.91 seconds
Started Aug 02 05:15:30 PM PDT 24
Finished Aug 02 05:15:31 PM PDT 24
Peak memory 201312 kb
Host smart-47be0693-2572-419a-a762-4ce69a55e370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661661158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3661661158
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.935384518
Short name T512
Test name
Test status
Simulation time 155638812 ps
CPU time 0.86 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 199152 kb
Host smart-aa56deb4-0f4d-42fa-b148-6115c5a9d9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935384518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_
mubi.935384518
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2420540249
Short name T302
Test name
Test status
Simulation time 41267979 ps
CPU time 0.69 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 198596 kb
Host smart-80bd7f5c-0d4f-4061-877c-2a0049aa1358
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420540249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2420540249
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.3994139932
Short name T431
Test name
Test status
Simulation time 58219391 ps
CPU time 0.75 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 198600 kb
Host smart-a4d385b4-6d21-42a3-bbd9-3de491988c16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994139932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.3994139932
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.709511023
Short name T597
Test name
Test status
Simulation time 32208723 ps
CPU time 0.57 seconds
Started Aug 02 05:15:46 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 197992 kb
Host smart-875ad5ec-2c49-4bc4-b17d-ee8517bf80f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709511023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.709511023
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.511061870
Short name T254
Test name
Test status
Simulation time 325351480 ps
CPU time 0.94 seconds
Started Aug 02 05:15:36 PM PDT 24
Finished Aug 02 05:15:37 PM PDT 24
Peak memory 198172 kb
Host smart-e6570eb9-3402-4d6f-94f9-fd33b2dc089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511061870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.511061870
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.447970487
Short name T294
Test name
Test status
Simulation time 38429020 ps
CPU time 0.65 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 197484 kb
Host smart-75fc5848-e336-4ce4-8bdf-b9406e30192f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447970487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.447970487
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3911655471
Short name T551
Test name
Test status
Simulation time 30917111 ps
CPU time 0.6 seconds
Started Aug 02 05:15:41 PM PDT 24
Finished Aug 02 05:15:42 PM PDT 24
Peak memory 198176 kb
Host smart-a5f12409-c029-4055-b94e-b5c57a77cd3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911655471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3911655471
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.1527252637
Short name T625
Test name
Test status
Simulation time 53724728 ps
CPU time 0.8 seconds
Started Aug 02 05:15:29 PM PDT 24
Finished Aug 02 05:15:30 PM PDT 24
Peak memory 199248 kb
Host smart-330cd9e4-bd76-437b-8c06-ad376a5e3bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527252637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1527252637
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1595580508
Short name T394
Test name
Test status
Simulation time 159157656 ps
CPU time 0.85 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:44 PM PDT 24
Peak memory 209564 kb
Host smart-d263e9bd-38b4-4fe1-af07-3878674e3675
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595580508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1595580508
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1559907079
Short name T423
Test name
Test status
Simulation time 52582719 ps
CPU time 0.78 seconds
Started Aug 02 05:15:38 PM PDT 24
Finished Aug 02 05:15:39 PM PDT 24
Peak memory 198236 kb
Host smart-ebd7caed-0e59-4dc0-943f-8f57dd3d6351
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559907079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1559907079
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2938657159
Short name T396
Test name
Test status
Simulation time 56019091 ps
CPU time 0.67 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:44 PM PDT 24
Peak memory 199436 kb
Host smart-ed713c5a-d65c-43ca-9778-87cc91e30d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938657159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2938657159
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.1184343453
Short name T58
Test name
Test status
Simulation time 67950431 ps
CPU time 0.65 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:52 PM PDT 24
Peak memory 198188 kb
Host smart-1d8aa5f2-05b1-4eeb-88f1-64cd5c64f388
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184343453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1184343453
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1112726011
Short name T102
Test name
Test status
Simulation time 91537958 ps
CPU time 0.64 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:35 PM PDT 24
Peak memory 198624 kb
Host smart-dbfcd29b-fc43-480b-a7f1-3e1c75465b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112726011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1112726011
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4282614843
Short name T137
Test name
Test status
Simulation time 75162094 ps
CPU time 0.68 seconds
Started Aug 02 05:15:35 PM PDT 24
Finished Aug 02 05:15:36 PM PDT 24
Peak memory 198308 kb
Host smart-0f280dfd-2131-49c4-8cb5-3096f542d76f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282614843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.4282614843
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2856938635
Short name T468
Test name
Test status
Simulation time 33557718 ps
CPU time 0.63 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:52 PM PDT 24
Peak memory 198068 kb
Host smart-203be039-1869-4245-9003-7e64ad00c75c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856938635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2856938635
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2758320140
Short name T598
Test name
Test status
Simulation time 312013267 ps
CPU time 1 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198232 kb
Host smart-602584d1-b501-440a-a302-e2dce4b7a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758320140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2758320140
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.407174249
Short name T552
Test name
Test status
Simulation time 55638467 ps
CPU time 0.68 seconds
Started Aug 02 05:15:49 PM PDT 24
Finished Aug 02 05:15:50 PM PDT 24
Peak memory 197416 kb
Host smart-86ffe6d8-ecd1-4f34-9ab5-fd9c604cb733
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407174249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.407174249
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.371080692
Short name T54
Test name
Test status
Simulation time 63022780 ps
CPU time 0.62 seconds
Started Aug 02 05:15:39 PM PDT 24
Finished Aug 02 05:15:40 PM PDT 24
Peak memory 198384 kb
Host smart-cba72266-f546-40e0-915f-27495be90178
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371080692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.371080692
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1626409270
Short name T484
Test name
Test status
Simulation time 52079496 ps
CPU time 0.69 seconds
Started Aug 02 05:15:34 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 201428 kb
Host smart-e53fbaf3-ada7-4597-a1fd-c57d8ea01721
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626409270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1626409270
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.1695172522
Short name T144
Test name
Test status
Simulation time 130517866 ps
CPU time 0.73 seconds
Started Aug 02 05:15:49 PM PDT 24
Finished Aug 02 05:15:50 PM PDT 24
Peak memory 198416 kb
Host smart-13b0aafd-848b-4b38-a458-45d40ce2c361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695172522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.1695172522
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2511166158
Short name T571
Test name
Test status
Simulation time 18206199 ps
CPU time 0.65 seconds
Started Aug 02 05:15:44 PM PDT 24
Finished Aug 02 05:15:45 PM PDT 24
Peak memory 198108 kb
Host smart-2ff935b6-e0eb-47c9-8375-289c06a06607
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511166158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2511166158
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1393171444
Short name T508
Test name
Test status
Simulation time 161833904 ps
CPU time 0.77 seconds
Started Aug 02 05:15:33 PM PDT 24
Finished Aug 02 05:15:34 PM PDT 24
Peak memory 209428 kb
Host smart-ee838275-2e4e-4355-a314-00b599e5b073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393171444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1393171444
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.4171176599
Short name T313
Test name
Test status
Simulation time 179112542 ps
CPU time 0.73 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 198320 kb
Host smart-ffc0de46-635e-4a85-8916-ef790eeeddef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171176599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4171176599
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1616924683
Short name T236
Test name
Test status
Simulation time 178477953 ps
CPU time 0.63 seconds
Started Aug 02 05:15:40 PM PDT 24
Finished Aug 02 05:15:41 PM PDT 24
Peak memory 198468 kb
Host smart-47c5f59c-0935-47fc-996f-c41e95d28a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616924683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1616924683
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.4005946818
Short name T29
Test name
Test status
Simulation time 49737811 ps
CPU time 0.97 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 200892 kb
Host smart-c9df0a5d-0828-4a23-9995-e60940a26b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005946818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.4005946818
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2590348483
Short name T273
Test name
Test status
Simulation time 51957058 ps
CPU time 0.78 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 198228 kb
Host smart-978c4e8d-2f84-408e-99d4-d008077b097b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590348483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2590348483
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.943789935
Short name T364
Test name
Test status
Simulation time 39375251 ps
CPU time 0.59 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 197364 kb
Host smart-55d6fb9a-0c1c-4e64-933b-ac6dab3b5ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943789935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_m
alfunc.943789935
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.758251281
Short name T455
Test name
Test status
Simulation time 633672768 ps
CPU time 0.91 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198168 kb
Host smart-e5bb6110-e299-44e4-bf3c-ffc42c107680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758251281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.758251281
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3673097570
Short name T439
Test name
Test status
Simulation time 32522223 ps
CPU time 0.62 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 198088 kb
Host smart-8888360d-b861-47ed-adec-45dffa2944b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673097570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3673097570
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2573853985
Short name T235
Test name
Test status
Simulation time 85621814 ps
CPU time 0.62 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198356 kb
Host smart-6ae3fb20-ea01-434f-a7f0-eed310afd261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573853985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2573853985
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.407403484
Short name T461
Test name
Test status
Simulation time 51061864 ps
CPU time 0.67 seconds
Started Aug 02 05:15:11 PM PDT 24
Finished Aug 02 05:15:12 PM PDT 24
Peak memory 201224 kb
Host smart-80bbfcaa-5a3e-45fb-ae50-36decabe335e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407403484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid
.407403484
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3977797222
Short name T258
Test name
Test status
Simulation time 91810451 ps
CPU time 0.77 seconds
Started Aug 02 05:14:57 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 199124 kb
Host smart-60a9be52-5ea7-4727-81e4-d367fb31b639
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977797222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3977797222
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1711347064
Short name T573
Test name
Test status
Simulation time 315147557 ps
CPU time 0.74 seconds
Started Aug 02 05:14:56 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 209500 kb
Host smart-9588e003-66ca-4c10-9525-18d8c8dbd96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711347064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1711347064
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.2137036369
Short name T37
Test name
Test status
Simulation time 461699783 ps
CPU time 1.06 seconds
Started Aug 02 05:15:09 PM PDT 24
Finished Aug 02 05:15:10 PM PDT 24
Peak memory 216884 kb
Host smart-8d400655-4c97-4f03-a697-940ce695de8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137036369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2137036369
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2102092884
Short name T602
Test name
Test status
Simulation time 139967820 ps
CPU time 0.76 seconds
Started Aug 02 05:14:57 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 198200 kb
Host smart-ea04b216-1d26-473a-aff2-6a8473ab67f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102092884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2102092884
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.763140883
Short name T588
Test name
Test status
Simulation time 104102552 ps
CPU time 0.61 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 198536 kb
Host smart-2a6e8f56-6d59-407a-a2d1-38268aa3f3ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763140883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.763140883
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2039292229
Short name T433
Test name
Test status
Simulation time 195824463 ps
CPU time 0.66 seconds
Started Aug 02 05:15:29 PM PDT 24
Finished Aug 02 05:15:29 PM PDT 24
Peak memory 198640 kb
Host smart-fa98e74d-0de4-404e-8e81-fb6b02ca95fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039292229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2039292229
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3543757818
Short name T526
Test name
Test status
Simulation time 29769018 ps
CPU time 0.62 seconds
Started Aug 02 05:15:55 PM PDT 24
Finished Aug 02 05:15:56 PM PDT 24
Peak memory 197448 kb
Host smart-61bb3ff0-55d0-4b4e-a266-b7dc3398c281
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543757818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3543757818
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2043947267
Short name T539
Test name
Test status
Simulation time 167103266 ps
CPU time 0.98 seconds
Started Aug 02 05:15:55 PM PDT 24
Finished Aug 02 05:15:56 PM PDT 24
Peak memory 198336 kb
Host smart-46396ded-9580-42b1-8dde-71b1fbd8af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043947267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2043947267
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.907442391
Short name T25
Test name
Test status
Simulation time 96878858 ps
CPU time 0.59 seconds
Started Aug 02 05:15:38 PM PDT 24
Finished Aug 02 05:15:39 PM PDT 24
Peak memory 198128 kb
Host smart-cd53f1ce-6737-462c-bd1e-b7ca325af4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907442391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.907442391
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.780868583
Short name T486
Test name
Test status
Simulation time 33688385 ps
CPU time 0.61 seconds
Started Aug 02 05:15:42 PM PDT 24
Finished Aug 02 05:15:43 PM PDT 24
Peak memory 198128 kb
Host smart-d6b5e28b-4b2e-444a-861d-654e5f04ed5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780868583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.780868583
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2747139031
Short name T87
Test name
Test status
Simulation time 41701191 ps
CPU time 0.67 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 201404 kb
Host smart-c9c58d2e-edae-46c1-9edc-c122193580cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747139031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2747139031
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.618079573
Short name T443
Test name
Test status
Simulation time 81654119 ps
CPU time 0.65 seconds
Started Aug 02 05:15:46 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 199060 kb
Host smart-796b775e-99bf-4d6d-abc4-e974b4006385
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618079573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.618079573
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3078467774
Short name T416
Test name
Test status
Simulation time 85880967 ps
CPU time 1 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 209468 kb
Host smart-a57102b4-287e-4b27-ac2d-398e7bf0c113
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078467774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3078467774
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1355477376
Short name T126
Test name
Test status
Simulation time 94624209 ps
CPU time 0.72 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 198188 kb
Host smart-d78ec18c-f101-4495-a8bf-aee26c5a276a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355477376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1355477376
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.3699939451
Short name T40
Test name
Test status
Simulation time 65787943 ps
CPU time 0.64 seconds
Started Aug 02 05:15:41 PM PDT 24
Finished Aug 02 05:15:42 PM PDT 24
Peak memory 198584 kb
Host smart-14921a89-248a-4614-963a-92c833b72bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699939451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3699939451
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.2857059968
Short name T560
Test name
Test status
Simulation time 30477787 ps
CPU time 0.75 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:52 PM PDT 24
Peak memory 198748 kb
Host smart-e4e97093-fc9e-44dd-86ec-c2bab4712974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857059968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2857059968
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3266517106
Short name T160
Test name
Test status
Simulation time 57489050 ps
CPU time 0.68 seconds
Started Aug 02 05:15:40 PM PDT 24
Finished Aug 02 05:15:41 PM PDT 24
Peak memory 199176 kb
Host smart-bc80cb60-d001-48c7-bb40-29dcc8c87743
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266517106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3266517106
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.95406589
Short name T531
Test name
Test status
Simulation time 39043882 ps
CPU time 0.6 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198036 kb
Host smart-38e4d881-67be-4061-b5de-98e66860fbd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95406589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_m
alfunc.95406589
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.619982054
Short name T52
Test name
Test status
Simulation time 714725519 ps
CPU time 0.96 seconds
Started Aug 02 05:15:49 PM PDT 24
Finished Aug 02 05:15:50 PM PDT 24
Peak memory 198104 kb
Host smart-5238104e-a063-4f5d-ac83-7e4e53152718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619982054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.619982054
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2402381256
Short name T251
Test name
Test status
Simulation time 41971851 ps
CPU time 0.65 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 197420 kb
Host smart-f5ee4444-2c78-4666-8939-4c9363f1c108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402381256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2402381256
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2533762512
Short name T234
Test name
Test status
Simulation time 68509139 ps
CPU time 0.58 seconds
Started Aug 02 05:15:47 PM PDT 24
Finished Aug 02 05:15:48 PM PDT 24
Peak memory 198124 kb
Host smart-d8c53c8a-251a-4dfb-ad6e-60be1ef172ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533762512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2533762512
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1545147921
Short name T206
Test name
Test status
Simulation time 91007383 ps
CPU time 0.65 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 201456 kb
Host smart-b93821c2-fffa-4a1a-8cec-5a48fe46ce63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545147921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1545147921
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3589277824
Short name T336
Test name
Test status
Simulation time 82923960 ps
CPU time 0.91 seconds
Started Aug 02 05:15:45 PM PDT 24
Finished Aug 02 05:15:46 PM PDT 24
Peak memory 198420 kb
Host smart-31bd2953-3357-482a-96b8-442a421b2e98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589277824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3589277824
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2695693422
Short name T271
Test name
Test status
Simulation time 113606289 ps
CPU time 0.95 seconds
Started Aug 02 05:15:50 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 209472 kb
Host smart-61c10b84-56a9-44be-87d1-62da06b57c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695693422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2695693422
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2768623301
Short name T627
Test name
Test status
Simulation time 66100828 ps
CPU time 0.94 seconds
Started Aug 02 05:15:46 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 199032 kb
Host smart-5df3f4b9-01e3-4781-8beb-eaa503cde7e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768623301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2768623301
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2920477709
Short name T59
Test name
Test status
Simulation time 56314418 ps
CPU time 0.63 seconds
Started Aug 02 05:15:37 PM PDT 24
Finished Aug 02 05:15:38 PM PDT 24
Peak memory 199424 kb
Host smart-ec82a335-e3b6-4190-86e2-5e9940ded284
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920477709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2920477709
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1071732305
Short name T558
Test name
Test status
Simulation time 24420395 ps
CPU time 0.69 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 198752 kb
Host smart-89bae142-0e0d-453a-8a96-751cbd24db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071732305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1071732305
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1442191887
Short name T130
Test name
Test status
Simulation time 35046267 ps
CPU time 0.6 seconds
Started Aug 02 05:15:43 PM PDT 24
Finished Aug 02 05:15:44 PM PDT 24
Peak memory 198016 kb
Host smart-bc63e02a-1dc3-480e-a8f2-2a84cc8b18ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442191887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1442191887
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.3293494443
Short name T410
Test name
Test status
Simulation time 545470660 ps
CPU time 0.94 seconds
Started Aug 02 05:15:49 PM PDT 24
Finished Aug 02 05:15:50 PM PDT 24
Peak memory 198376 kb
Host smart-5aabb499-fa7b-499c-ba92-34477ca55a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293494443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3293494443
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2220856165
Short name T16
Test name
Test status
Simulation time 33107657 ps
CPU time 0.68 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198032 kb
Host smart-aafaafcb-4a10-451d-8ffb-8d102bd9fe91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220856165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2220856165
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1243045571
Short name T211
Test name
Test status
Simulation time 85034253 ps
CPU time 0.59 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 197956 kb
Host smart-0bbfc085-6c3e-4a9e-aad4-604ae124c015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243045571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1243045571
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1573896259
Short name T626
Test name
Test status
Simulation time 120376262 ps
CPU time 0.75 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 198424 kb
Host smart-ecddec6e-3e01-4e64-b62b-07155f614528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573896259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1573896259
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.72729410
Short name T422
Test name
Test status
Simulation time 92451376 ps
CPU time 1.03 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 209412 kb
Host smart-35ce662b-368b-4b45-8448-6501d1ed87f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72729410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.72729410
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2906664379
Short name T7
Test name
Test status
Simulation time 52421024 ps
CPU time 0.86 seconds
Started Aug 02 05:15:46 PM PDT 24
Finished Aug 02 05:15:47 PM PDT 24
Peak memory 199320 kb
Host smart-93e18069-96d5-412b-90d6-17fd7bbebae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906664379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2906664379
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.400448862
Short name T6
Test name
Test status
Simulation time 30936556 ps
CPU time 0.65 seconds
Started Aug 02 05:15:50 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 199348 kb
Host smart-3bf01ad5-3d7c-4427-a6f6-95371066f509
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400448862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.400448862
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3518430496
Short name T155
Test name
Test status
Simulation time 57912023 ps
CPU time 0.74 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:52 PM PDT 24
Peak memory 198472 kb
Host smart-ea091937-51e4-49ab-a4cb-d74206b909f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518430496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3518430496
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.427453925
Short name T599
Test name
Test status
Simulation time 38078069 ps
CPU time 0.59 seconds
Started Aug 02 05:15:52 PM PDT 24
Finished Aug 02 05:15:53 PM PDT 24
Peak memory 198052 kb
Host smart-52a6c637-5d9c-4039-a7b7-3f63fce9e2bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427453925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.427453925
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1983417721
Short name T620
Test name
Test status
Simulation time 622370190 ps
CPU time 0.93 seconds
Started Aug 02 05:16:28 PM PDT 24
Finished Aug 02 05:16:29 PM PDT 24
Peak memory 198132 kb
Host smart-e526fefe-4857-4cdc-9709-a96ce298db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983417721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1983417721
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2681493272
Short name T265
Test name
Test status
Simulation time 73592410 ps
CPU time 0.62 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 198080 kb
Host smart-f74b9474-55cb-4d52-87dc-62cf677738d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681493272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2681493272
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.206303400
Short name T581
Test name
Test status
Simulation time 41367368 ps
CPU time 0.61 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 198456 kb
Host smart-86596b8b-d03c-42cd-b49a-9fa1cc1f3357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206303400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.206303400
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.3466359967
Short name T238
Test name
Test status
Simulation time 84146616 ps
CPU time 0.7 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:05 PM PDT 24
Peak memory 199216 kb
Host smart-769439c8-9226-4d94-92ea-d54a21f7dbb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466359967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3466359967
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3926091536
Short name T208
Test name
Test status
Simulation time 122099723 ps
CPU time 0.93 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 209472 kb
Host smart-1d2e03a1-dfd2-4f35-87ac-8a33cdab56b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926091536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3926091536
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2429720532
Short name T46
Test name
Test status
Simulation time 83255009 ps
CPU time 0.77 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 198276 kb
Host smart-700b15b2-751e-4e4f-affd-8b2d9f0b655d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429720532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2429720532
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.554018796
Short name T43
Test name
Test status
Simulation time 29619942 ps
CPU time 0.67 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 199480 kb
Host smart-91a40317-b3ab-4323-b549-be430e692d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554018796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.554018796
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.9739263
Short name T28
Test name
Test status
Simulation time 44359671 ps
CPU time 0.68 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 199140 kb
Host smart-77311465-594f-443d-824b-401e7e31dac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9739263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.9739263
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.58509893
Short name T547
Test name
Test status
Simulation time 36564229 ps
CPU time 0.84 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 200296 kb
Host smart-094dc1bb-8e9b-49d1-a1d8-72a9f5b584c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58509893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.58509893
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2855395264
Short name T156
Test name
Test status
Simulation time 76345102 ps
CPU time 0.66 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 199152 kb
Host smart-0532a493-7520-46c9-b540-fb5157352688
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855395264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2855395264
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2981165630
Short name T253
Test name
Test status
Simulation time 38896931 ps
CPU time 0.6 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 197308 kb
Host smart-d75711f7-243e-4db9-ab63-1ce7a14bd5b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981165630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.2981165630
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.322916327
Short name T291
Test name
Test status
Simulation time 321428355 ps
CPU time 0.97 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 198336 kb
Host smart-7340cf11-116f-4a33-892d-3957a65943b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322916327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.322916327
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.4294865495
Short name T324
Test name
Test status
Simulation time 55301954 ps
CPU time 0.68 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 197992 kb
Host smart-b70a0fb0-974f-4bec-aad3-90b609169997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294865495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.4294865495
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.1117517405
Short name T575
Test name
Test status
Simulation time 78634210 ps
CPU time 0.6 seconds
Started Aug 02 05:16:08 PM PDT 24
Finished Aug 02 05:16:09 PM PDT 24
Peak memory 198108 kb
Host smart-f7060160-e2b1-4523-ab8b-84168d2e5f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117517405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1117517405
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1686118807
Short name T182
Test name
Test status
Simulation time 71075546 ps
CPU time 0.66 seconds
Started Aug 02 05:16:11 PM PDT 24
Finished Aug 02 05:16:11 PM PDT 24
Peak memory 201348 kb
Host smart-d8f4be7a-84d8-4f2d-9c60-fb6275fd13ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686118807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1686118807
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.912561898
Short name T548
Test name
Test status
Simulation time 28941849 ps
CPU time 0.65 seconds
Started Aug 02 05:15:50 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 198064 kb
Host smart-c1b7c35b-da8c-44df-a3f9-ef1f23fa7324
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912561898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.912561898
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.1720386398
Short name T335
Test name
Test status
Simulation time 138658144 ps
CPU time 0.78 seconds
Started Aug 02 05:15:53 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 209500 kb
Host smart-037dafc4-0751-4e42-bad5-3a953c024902
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720386398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1720386398
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1949484966
Short name T518
Test name
Test status
Simulation time 95097464 ps
CPU time 0.75 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 199048 kb
Host smart-f3de5e7f-7d17-48cc-8639-e62e9f4a7cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949484966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1949484966
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2217791242
Short name T523
Test name
Test status
Simulation time 54577148 ps
CPU time 0.62 seconds
Started Aug 02 05:16:00 PM PDT 24
Finished Aug 02 05:16:01 PM PDT 24
Peak memory 198512 kb
Host smart-7fae01a0-260e-47e9-92d6-77d9637f2b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217791242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2217791242
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3125189706
Short name T381
Test name
Test status
Simulation time 134896522 ps
CPU time 0.85 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 200096 kb
Host smart-3302055e-6495-469b-b546-14785d156f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125189706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3125189706
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1204113851
Short name T603
Test name
Test status
Simulation time 39876412 ps
CPU time 0.61 seconds
Started Aug 02 05:15:50 PM PDT 24
Finished Aug 02 05:15:50 PM PDT 24
Peak memory 198080 kb
Host smart-6141f32c-fe17-487f-8a38-4991f7fac245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204113851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1204113851
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3145956917
Short name T564
Test name
Test status
Simulation time 170222947 ps
CPU time 0.92 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 198072 kb
Host smart-29ac1ff5-d38d-48c0-bc8d-319c727424a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145956917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3145956917
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3706400859
Short name T229
Test name
Test status
Simulation time 39782186 ps
CPU time 0.63 seconds
Started Aug 02 05:15:53 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 197440 kb
Host smart-91900c31-5962-48e0-89f0-9b521e1e6e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706400859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3706400859
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2278959465
Short name T447
Test name
Test status
Simulation time 72562001 ps
CPU time 0.6 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198516 kb
Host smart-b4b57f79-5027-45e3-a665-6646580f1947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278959465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2278959465
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.4051395212
Short name T180
Test name
Test status
Simulation time 38585573 ps
CPU time 0.72 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 201428 kb
Host smart-3809e4c3-abb4-4347-9769-ef1b0b4d59da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051395212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.4051395212
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2888582155
Short name T42
Test name
Test status
Simulation time 44562651 ps
CPU time 0.74 seconds
Started Aug 02 05:16:00 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 198424 kb
Host smart-80175154-f274-402b-8485-815740f663cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888582155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2888582155
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3566471461
Short name T50
Test name
Test status
Simulation time 108996097 ps
CPU time 1.09 seconds
Started Aug 02 05:16:10 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 209500 kb
Host smart-94289d5d-f351-4d8d-b11e-6046582bac4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566471461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3566471461
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2731324970
Short name T306
Test name
Test status
Simulation time 78765804 ps
CPU time 0.74 seconds
Started Aug 02 05:15:55 PM PDT 24
Finished Aug 02 05:15:56 PM PDT 24
Peak memory 198164 kb
Host smart-1891cd46-64b4-4ceb-b418-581c48d90ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731324970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2731324970
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2796218784
Short name T614
Test name
Test status
Simulation time 30252000 ps
CPU time 0.67 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 198508 kb
Host smart-8d185652-ff7a-41f4-a649-45d35ddd6841
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796218784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2796218784
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.1092367167
Short name T198
Test name
Test status
Simulation time 179520140 ps
CPU time 0.72 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 198820 kb
Host smart-07a1d295-1bd5-4f8b-89c6-77bb9aa88ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092367167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1092367167
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.704899279
Short name T429
Test name
Test status
Simulation time 58564460 ps
CPU time 0.85 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 199052 kb
Host smart-d709d237-469c-4a2f-9b3a-19157f659a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704899279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disa
ble_rom_integrity_check.704899279
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.45185125
Short name T219
Test name
Test status
Simulation time 56890804 ps
CPU time 0.59 seconds
Started Aug 02 05:15:51 PM PDT 24
Finished Aug 02 05:15:51 PM PDT 24
Peak memory 198012 kb
Host smart-88b8dcee-c7be-42b3-aed1-ef59754aa20f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45185125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_m
alfunc.45185125
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.649387336
Short name T411
Test name
Test status
Simulation time 164914262 ps
CPU time 0.99 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 198132 kb
Host smart-f77e8388-59d1-49ff-afdd-00bc876305a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649387336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.649387336
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2337539255
Short name T451
Test name
Test status
Simulation time 50895989 ps
CPU time 0.67 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 198140 kb
Host smart-e9c742e1-1f45-48f5-8335-2a0a509bd68c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337539255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2337539255
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1132165330
Short name T608
Test name
Test status
Simulation time 152602517 ps
CPU time 0.6 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 198132 kb
Host smart-ec3cb1cd-d4e1-4b18-99c2-9b93d3e908eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132165330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1132165330
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.392928729
Short name T169
Test name
Test status
Simulation time 72855137 ps
CPU time 0.67 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 201416 kb
Host smart-f9e8392e-0b1a-42c4-b044-2f0c8fcebce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392928729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invali
d.392928729
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3723381573
Short name T348
Test name
Test status
Simulation time 47609892 ps
CPU time 0.67 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:02 PM PDT 24
Peak memory 199144 kb
Host smart-419d5c82-25dd-4e94-8aa4-ea5a8ea98b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723381573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3723381573
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3541707178
Short name T241
Test name
Test status
Simulation time 159339119 ps
CPU time 0.81 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 209468 kb
Host smart-7069b944-01fa-4672-8313-a932270f5368
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541707178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3541707178
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3662165654
Short name T252
Test name
Test status
Simulation time 63582597 ps
CPU time 0.87 seconds
Started Aug 02 05:16:09 PM PDT 24
Finished Aug 02 05:16:10 PM PDT 24
Peak memory 199224 kb
Host smart-cdc26126-6705-4112-9f65-4c8ba23b7f3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662165654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3662165654
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3397011678
Short name T366
Test name
Test status
Simulation time 44070610 ps
CPU time 0.64 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 199388 kb
Host smart-2845b44d-200d-4f26-8a4b-0af4bdf1b968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397011678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3397011678
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2094375761
Short name T296
Test name
Test status
Simulation time 241386290 ps
CPU time 0.7 seconds
Started Aug 02 05:16:16 PM PDT 24
Finished Aug 02 05:16:21 PM PDT 24
Peak memory 198620 kb
Host smart-ffe093f8-a841-4e6f-819e-7fc34dfc9889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094375761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2094375761
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1998744553
Short name T533
Test name
Test status
Simulation time 60366917 ps
CPU time 0.8 seconds
Started Aug 02 05:16:15 PM PDT 24
Finished Aug 02 05:16:16 PM PDT 24
Peak memory 199168 kb
Host smart-49966263-642b-4db1-9a29-264bb8977f6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998744553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1998744553
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1904008800
Short name T354
Test name
Test status
Simulation time 53429683 ps
CPU time 0.6 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:15 PM PDT 24
Peak memory 198088 kb
Host smart-ddba3bf6-ad72-4854-9355-3f6e10a7d3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904008800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1904008800
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3604237696
Short name T45
Test name
Test status
Simulation time 624379660 ps
CPU time 0.95 seconds
Started Aug 02 05:16:00 PM PDT 24
Finished Aug 02 05:16:01 PM PDT 24
Peak memory 198424 kb
Host smart-947d64ec-11d9-480e-939b-62bc23f2c441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604237696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3604237696
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.984762548
Short name T565
Test name
Test status
Simulation time 88679325 ps
CPU time 0.6 seconds
Started Aug 02 05:16:12 PM PDT 24
Finished Aug 02 05:16:13 PM PDT 24
Peak memory 198112 kb
Host smart-e569f7a7-c455-48f8-b67d-79054c90072f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984762548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.984762548
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2733829325
Short name T462
Test name
Test status
Simulation time 44780540 ps
CPU time 0.61 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:13 PM PDT 24
Peak memory 198420 kb
Host smart-3475138a-f429-4018-a31b-27591000b32f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733829325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2733829325
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.2295696414
Short name T330
Test name
Test status
Simulation time 56864078 ps
CPU time 0.61 seconds
Started Aug 02 05:15:55 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 198116 kb
Host smart-a099fd45-91d1-46ed-8307-6d35ded8edd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295696414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2295696414
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.1305164283
Short name T392
Test name
Test status
Simulation time 163033853 ps
CPU time 0.79 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 209508 kb
Host smart-4890a447-4974-4861-8a5a-49b0454e9983
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305164283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1305164283
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.1428865755
Short name T270
Test name
Test status
Simulation time 53150112 ps
CPU time 0.82 seconds
Started Aug 02 05:15:55 PM PDT 24
Finished Aug 02 05:15:56 PM PDT 24
Peak memory 197992 kb
Host smart-76879c20-a142-491d-baa2-5e146e52ce58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428865755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1428865755
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2019160793
Short name T502
Test name
Test status
Simulation time 30886878 ps
CPU time 0.63 seconds
Started Aug 02 05:16:08 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198460 kb
Host smart-bf9cb1d1-d729-446a-8f73-f68d460956c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019160793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2019160793
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.375752747
Short name T30
Test name
Test status
Simulation time 48510008 ps
CPU time 0.94 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 200692 kb
Host smart-b70294be-2064-4411-9120-a54b29f6f119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375752747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.375752747
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2081544010
Short name T572
Test name
Test status
Simulation time 91772957 ps
CPU time 0.66 seconds
Started Aug 02 05:16:17 PM PDT 24
Finished Aug 02 05:16:18 PM PDT 24
Peak memory 198228 kb
Host smart-23398d39-6523-440a-af02-4390cba3c60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081544010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2081544010
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2922628813
Short name T546
Test name
Test status
Simulation time 36654985 ps
CPU time 0.59 seconds
Started Aug 02 05:16:31 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 198108 kb
Host smart-c426fe14-6bc9-4dd4-8dd8-532115e2553f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922628813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.2922628813
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.2964661640
Short name T304
Test name
Test status
Simulation time 166309313 ps
CPU time 0.92 seconds
Started Aug 02 05:16:05 PM PDT 24
Finished Aug 02 05:16:06 PM PDT 24
Peak memory 198144 kb
Host smart-b13e7f35-695a-47cb-97d8-9067670998a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964661640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.2964661640
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.1687246785
Short name T466
Test name
Test status
Simulation time 52679327 ps
CPU time 0.68 seconds
Started Aug 02 05:16:21 PM PDT 24
Finished Aug 02 05:16:21 PM PDT 24
Peak memory 198216 kb
Host smart-86cb02b5-14b2-4a83-aa93-43296ebd5572
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687246785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1687246785
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3945939805
Short name T445
Test name
Test status
Simulation time 83719240 ps
CPU time 0.6 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 198152 kb
Host smart-503974be-2d14-4171-bb5a-65ad48f9df5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945939805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3945939805
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.600734064
Short name T34
Test name
Test status
Simulation time 158882404 ps
CPU time 0.7 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 201252 kb
Host smart-e4fe8e19-3067-41c8-ae16-7abe38e7328e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600734064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invali
d.600734064
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.549403678
Short name T427
Test name
Test status
Simulation time 74434857 ps
CPU time 0.69 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 199100 kb
Host smart-2006ca7e-f2fd-4ecb-a544-82b27f200615
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549403678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.549403678
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3577191790
Short name T483
Test name
Test status
Simulation time 95856572 ps
CPU time 1.07 seconds
Started Aug 02 05:16:29 PM PDT 24
Finished Aug 02 05:16:30 PM PDT 24
Peak memory 209492 kb
Host smart-061cafa2-a1d1-4653-9191-9937826becae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577191790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3577191790
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.235727328
Short name T515
Test name
Test status
Simulation time 59422321 ps
CPU time 0.8 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 198124 kb
Host smart-b6b6981b-9f26-4ae8-807b-8b85575c2d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235727328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_
mubi.235727328
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3110052876
Short name T370
Test name
Test status
Simulation time 31890507 ps
CPU time 0.65 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 199320 kb
Host smart-c38a24f9-e97e-4072-ab22-257ae4aeb56f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110052876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3110052876
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.1441206146
Short name T609
Test name
Test status
Simulation time 45025138 ps
CPU time 0.92 seconds
Started Aug 02 05:16:30 PM PDT 24
Finished Aug 02 05:16:31 PM PDT 24
Peak memory 200188 kb
Host smart-9d655f85-b457-4830-a804-7f48be266a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441206146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1441206146
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1670340450
Short name T325
Test name
Test status
Simulation time 57696464 ps
CPU time 0.82 seconds
Started Aug 02 05:15:53 PM PDT 24
Finished Aug 02 05:15:54 PM PDT 24
Peak memory 198512 kb
Host smart-e78a20e2-16d1-4dc3-93e6-9b2ac0677e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670340450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.1670340450
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2330557995
Short name T341
Test name
Test status
Simulation time 33767632 ps
CPU time 0.6 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 197952 kb
Host smart-84e9c606-d095-4e8b-bbfc-74f87eabe5cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330557995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2330557995
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.2412852139
Short name T417
Test name
Test status
Simulation time 158619469 ps
CPU time 0.95 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198148 kb
Host smart-9e6d6e04-5171-4892-a325-5c86650b07ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412852139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2412852139
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1844109939
Short name T15
Test name
Test status
Simulation time 66103882 ps
CPU time 0.58 seconds
Started Aug 02 05:15:54 PM PDT 24
Finished Aug 02 05:15:55 PM PDT 24
Peak memory 197312 kb
Host smart-ba948ee4-b1e9-4cd2-92fb-7a699c8491a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844109939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1844109939
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1279423125
Short name T401
Test name
Test status
Simulation time 74625086 ps
CPU time 0.61 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198092 kb
Host smart-91bc478c-be41-4e3f-a594-db97a46c1749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279423125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1279423125
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.602266183
Short name T196
Test name
Test status
Simulation time 69499569 ps
CPU time 0.67 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 201420 kb
Host smart-6ea4c253-b7d9-4239-9a4f-2de137e00b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602266183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.602266183
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1704152606
Short name T316
Test name
Test status
Simulation time 71201230 ps
CPU time 0.59 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:56 PM PDT 24
Peak memory 198136 kb
Host smart-595b8161-ff95-4235-91cf-0ef4644b73f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704152606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1704152606
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.131860249
Short name T49
Test name
Test status
Simulation time 111312489 ps
CPU time 0.91 seconds
Started Aug 02 05:16:04 PM PDT 24
Finished Aug 02 05:16:06 PM PDT 24
Peak memory 209508 kb
Host smart-e991f3cf-a4ac-41e8-8f81-661d40deb472
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131860249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.131860249
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1981197568
Short name T307
Test name
Test status
Simulation time 86211938 ps
CPU time 0.8 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 199400 kb
Host smart-a25602b2-e526-4680-940f-e71ecb66df03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981197568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1981197568
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2886753435
Short name T446
Test name
Test status
Simulation time 153128119 ps
CPU time 0.66 seconds
Started Aug 02 05:15:57 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198512 kb
Host smart-99316265-34c5-472f-921f-6bbc71e72ba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886753435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2886753435
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.2840039684
Short name T181
Test name
Test status
Simulation time 27585583 ps
CPU time 0.84 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 200112 kb
Host smart-fb3256ab-44ec-4aca-b014-8aa39f42026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840039684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2840039684
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3435093140
Short name T372
Test name
Test status
Simulation time 59692686 ps
CPU time 0.78 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 198396 kb
Host smart-2d604502-f97b-4173-b031-3dea1995c638
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435093140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3435093140
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2588184876
Short name T438
Test name
Test status
Simulation time 29382018 ps
CPU time 0.64 seconds
Started Aug 02 05:15:37 PM PDT 24
Finished Aug 02 05:15:38 PM PDT 24
Peak memory 198028 kb
Host smart-5f2d03b3-9995-4365-aa1d-86954fe2106f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588184876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2588184876
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.1018257515
Short name T327
Test name
Test status
Simulation time 610779934 ps
CPU time 0.98 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198124 kb
Host smart-5577cd03-e355-41dc-8030-96fd591f0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018257515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1018257515
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.731311503
Short name T352
Test name
Test status
Simulation time 45674613 ps
CPU time 0.65 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 197104 kb
Host smart-e9d367c2-721b-410b-be52-44f2b0ccd26c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731311503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.731311503
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.843150785
Short name T476
Test name
Test status
Simulation time 25261322 ps
CPU time 0.62 seconds
Started Aug 02 05:15:20 PM PDT 24
Finished Aug 02 05:15:21 PM PDT 24
Peak memory 198456 kb
Host smart-e42a4272-6031-4770-82ff-7d0305072b97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843150785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.843150785
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.3355092834
Short name T173
Test name
Test status
Simulation time 51762427 ps
CPU time 0.71 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 201420 kb
Host smart-8fa5356b-5581-4d2a-9d86-e8996b843696
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355092834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.3355092834
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.4164416408
Short name T332
Test name
Test status
Simulation time 61940949 ps
CPU time 0.73 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 199044 kb
Host smart-534adf2e-8957-408a-8708-5189457cb0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164416408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.4164416408
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2236407836
Short name T19
Test name
Test status
Simulation time 395132849 ps
CPU time 1.21 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 216920 kb
Host smart-614475b6-49d5-4ec0-b260-99dca2dddaeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236407836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2236407836
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3746834130
Short name T530
Test name
Test status
Simulation time 61229685 ps
CPU time 0.72 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 198268 kb
Host smart-df19e4ba-ec0f-4eed-b274-4e09cc7cc10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746834130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3746834130
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.3030806481
Short name T280
Test name
Test status
Simulation time 52535636 ps
CPU time 0.62 seconds
Started Aug 02 05:14:56 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 198564 kb
Host smart-62735151-ea6c-426a-934c-1078e8aeb663
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030806481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.3030806481
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1843992334
Short name T97
Test name
Test status
Simulation time 29440804 ps
CPU time 0.77 seconds
Started Aug 02 05:16:10 PM PDT 24
Finished Aug 02 05:16:11 PM PDT 24
Peak memory 200176 kb
Host smart-5e9b885e-1007-4b8f-a714-8acd680f093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843992334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1843992334
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1606128119
Short name T561
Test name
Test status
Simulation time 94330529 ps
CPU time 0.65 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:00 PM PDT 24
Peak memory 199172 kb
Host smart-2df17474-5b81-4e4a-8fe0-9fcdafec37b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606128119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1606128119
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3818910881
Short name T129
Test name
Test status
Simulation time 29645300 ps
CPU time 0.62 seconds
Started Aug 02 05:16:10 PM PDT 24
Finished Aug 02 05:16:11 PM PDT 24
Peak memory 198076 kb
Host smart-8ef72893-8e11-49bd-849a-f38d924256e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818910881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3818910881
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.4163546608
Short name T628
Test name
Test status
Simulation time 605136994 ps
CPU time 0.97 seconds
Started Aug 02 05:16:09 PM PDT 24
Finished Aug 02 05:16:10 PM PDT 24
Peak memory 198160 kb
Host smart-7021740d-60aa-4f92-8ee4-edbef18b5e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163546608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.4163546608
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.1278241793
Short name T17
Test name
Test status
Simulation time 60437314 ps
CPU time 0.6 seconds
Started Aug 02 05:15:56 PM PDT 24
Finished Aug 02 05:15:57 PM PDT 24
Peak memory 198092 kb
Host smart-6b64f97d-fb81-4ac7-bcdc-47e9f2aae02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278241793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.1278241793
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.99790170
Short name T210
Test name
Test status
Simulation time 39718874 ps
CPU time 0.62 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198088 kb
Host smart-b414e038-dd83-4f2c-9ed3-25e871a3b037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99790170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.99790170
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.4177498768
Short name T191
Test name
Test status
Simulation time 72992875 ps
CPU time 0.66 seconds
Started Aug 02 05:16:20 PM PDT 24
Finished Aug 02 05:16:20 PM PDT 24
Peak memory 201336 kb
Host smart-9c0b9c84-7b3c-45e0-bdd1-0660a7a39f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177498768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.4177498768
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.2914906464
Short name T190
Test name
Test status
Simulation time 74799540 ps
CPU time 0.64 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198312 kb
Host smart-dc5886ba-ec0e-44ee-8d98-83d6cc7e5fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914906464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.2914906464
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.136909278
Short name T557
Test name
Test status
Simulation time 91509638 ps
CPU time 0.67 seconds
Started Aug 02 05:16:24 PM PDT 24
Finished Aug 02 05:16:25 PM PDT 24
Peak memory 199228 kb
Host smart-1a298281-f9d8-4480-aa89-fd8ecd2d3606
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136909278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.136909278
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3205846123
Short name T312
Test name
Test status
Simulation time 103810577 ps
CPU time 1.04 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:15 PM PDT 24
Peak memory 209488 kb
Host smart-5eb66108-7de8-4671-ac0c-f64c4aa8097c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205846123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3205846123
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2180755656
Short name T71
Test name
Test status
Simulation time 173667690 ps
CPU time 0.82 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 199164 kb
Host smart-af93b45e-2e56-4f66-b594-5cc13c401ad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180755656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2180755656
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.13108292
Short name T387
Test name
Test status
Simulation time 29108872 ps
CPU time 0.67 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 199408 kb
Host smart-a2ce9a5d-688c-424f-8d1f-ee9a298e24d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.13108292
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.1393477311
Short name T494
Test name
Test status
Simulation time 67114783 ps
CPU time 0.8 seconds
Started Aug 02 05:16:26 PM PDT 24
Finished Aug 02 05:16:27 PM PDT 24
Peak memory 200108 kb
Host smart-12e21320-7791-46aa-bc6f-57a3a9cd1ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393477311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1393477311
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.684490
Short name T591
Test name
Test status
Simulation time 83392089 ps
CPU time 0.62 seconds
Started Aug 02 05:16:04 PM PDT 24
Finished Aug 02 05:16:05 PM PDT 24
Peak memory 198320 kb
Host smart-835ea643-91d1-495d-8caa-6b9e8150a60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integ
rity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable
_rom_integrity_check.684490
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3337197500
Short name T378
Test name
Test status
Simulation time 30070032 ps
CPU time 0.62 seconds
Started Aug 02 05:16:11 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 197940 kb
Host smart-4a0c37f6-253e-4d03-b112-aff1afedff15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337197500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.3337197500
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.3889819324
Short name T53
Test name
Test status
Simulation time 168357403 ps
CPU time 0.98 seconds
Started Aug 02 05:16:19 PM PDT 24
Finished Aug 02 05:16:25 PM PDT 24
Peak memory 198448 kb
Host smart-4cbe98f2-c448-4257-827c-c7f14c1f69ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889819324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3889819324
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.897729897
Short name T481
Test name
Test status
Simulation time 47668872 ps
CPU time 0.67 seconds
Started Aug 02 05:15:59 PM PDT 24
Finished Aug 02 05:16:06 PM PDT 24
Peak memory 198092 kb
Host smart-e5ba64c1-d783-4cf1-801f-a956a9ba8a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897729897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.897729897
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1514602103
Short name T580
Test name
Test status
Simulation time 41582198 ps
CPU time 0.59 seconds
Started Aug 02 05:16:01 PM PDT 24
Finished Aug 02 05:16:01 PM PDT 24
Peak memory 198428 kb
Host smart-b2120742-ad1b-4f87-a637-b833b8fb571c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514602103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1514602103
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1074895752
Short name T171
Test name
Test status
Simulation time 67046896 ps
CPU time 0.66 seconds
Started Aug 02 05:16:03 PM PDT 24
Finished Aug 02 05:16:04 PM PDT 24
Peak memory 201420 kb
Host smart-80dad583-f8f6-49ea-b3f4-72251ab9e4ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074895752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.1074895752
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3895497584
Short name T624
Test name
Test status
Simulation time 75127514 ps
CPU time 0.86 seconds
Started Aug 02 05:16:11 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 199160 kb
Host smart-cc23827f-5f09-4270-9642-b7981ba7ca9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895497584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3895497584
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4245794796
Short name T237
Test name
Test status
Simulation time 243627706 ps
CPU time 0.77 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:13 PM PDT 24
Peak memory 209556 kb
Host smart-2c73d60a-6ca2-4e32-ac6c-bfb7d7829544
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245794796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4245794796
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1692349924
Short name T386
Test name
Test status
Simulation time 56365602 ps
CPU time 0.78 seconds
Started Aug 02 05:16:09 PM PDT 24
Finished Aug 02 05:16:10 PM PDT 24
Peak memory 198120 kb
Host smart-d0d80474-29c0-40e5-ba36-2fa80919574a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692349924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1692349924
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3469869706
Short name T281
Test name
Test status
Simulation time 59031073 ps
CPU time 0.61 seconds
Started Aug 02 05:16:00 PM PDT 24
Finished Aug 02 05:16:01 PM PDT 24
Peak memory 198436 kb
Host smart-74467431-beb7-4799-848d-f45fb2256c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469869706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3469869706
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.706676017
Short name T103
Test name
Test status
Simulation time 46502269 ps
CPU time 0.87 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 200244 kb
Host smart-db7f7a9d-1635-4f91-ad9f-37cb9d434cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706676017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.706676017
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3077692533
Short name T201
Test name
Test status
Simulation time 64734469 ps
CPU time 0.66 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 199168 kb
Host smart-17c60628-d365-4ba7-be3d-55682349414f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077692533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3077692533
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1472964974
Short name T510
Test name
Test status
Simulation time 43311358 ps
CPU time 0.62 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:58 PM PDT 24
Peak memory 198092 kb
Host smart-4151077e-d830-48e2-9ac8-93e1501804ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472964974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1472964974
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2257904510
Short name T612
Test name
Test status
Simulation time 628728153 ps
CPU time 0.9 seconds
Started Aug 02 05:16:10 PM PDT 24
Finished Aug 02 05:16:11 PM PDT 24
Peak memory 198052 kb
Host smart-7197a132-7ad9-4c8b-92fd-9edd5c356079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257904510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2257904510
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.856099766
Short name T414
Test name
Test status
Simulation time 150480418 ps
CPU time 0.61 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 198220 kb
Host smart-facc2656-7d84-4462-b18e-69b5fd4d7ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856099766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.856099766
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1926141009
Short name T390
Test name
Test status
Simulation time 80944020 ps
CPU time 0.6 seconds
Started Aug 02 05:16:17 PM PDT 24
Finished Aug 02 05:16:18 PM PDT 24
Peak memory 198432 kb
Host smart-f69cfc62-240e-41fe-bf0a-7b35c59a9161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926141009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1926141009
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.97391072
Short name T437
Test name
Test status
Simulation time 80311471 ps
CPU time 0.66 seconds
Started Aug 02 05:16:12 PM PDT 24
Finished Aug 02 05:16:13 PM PDT 24
Peak memory 201368 kb
Host smart-49e40f61-74ea-4d50-a77f-27174ee34c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97391072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid
.97391072
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.169976966
Short name T593
Test name
Test status
Simulation time 67791828 ps
CPU time 0.71 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:19 PM PDT 24
Peak memory 199100 kb
Host smart-40c8479a-fd98-44c9-bee7-7f19477c8e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169976966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.169976966
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.4039171465
Short name T532
Test name
Test status
Simulation time 100765142 ps
CPU time 1.06 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 209384 kb
Host smart-daf3a5d6-5b8a-4685-bdd8-1702d702178a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039171465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.4039171465
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3104317922
Short name T579
Test name
Test status
Simulation time 57013359 ps
CPU time 0.77 seconds
Started Aug 02 05:16:05 PM PDT 24
Finished Aug 02 05:16:06 PM PDT 24
Peak memory 198232 kb
Host smart-edd3721d-44a6-45f2-9bc8-0a25a45d1f52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104317922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3104317922
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2211817173
Short name T350
Test name
Test status
Simulation time 29861405 ps
CPU time 0.69 seconds
Started Aug 02 05:16:21 PM PDT 24
Finished Aug 02 05:16:22 PM PDT 24
Peak memory 199420 kb
Host smart-634dc0d5-f906-4898-8ea4-a572054a7809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211817173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2211817173
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.4097374725
Short name T415
Test name
Test status
Simulation time 107653233 ps
CPU time 0.6 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 198004 kb
Host smart-6e7ef227-f03d-4606-a2a7-24ecbec781e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097374725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.4097374725
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.4092528996
Short name T556
Test name
Test status
Simulation time 31320418 ps
CPU time 0.96 seconds
Started Aug 02 05:16:00 PM PDT 24
Finished Aug 02 05:16:01 PM PDT 24
Peak memory 200976 kb
Host smart-20de22db-d242-41ef-a938-5de752330c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092528996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.4092528996
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3935233745
Short name T585
Test name
Test status
Simulation time 96450637 ps
CPU time 0.64 seconds
Started Aug 02 05:16:11 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 198492 kb
Host smart-57de3d4f-6ffb-443a-8b4c-8d61f1e37b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935233745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3935233745
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2671948324
Short name T405
Test name
Test status
Simulation time 39066370 ps
CPU time 0.59 seconds
Started Aug 02 05:16:12 PM PDT 24
Finished Aug 02 05:16:13 PM PDT 24
Peak memory 198060 kb
Host smart-e162dcb6-f2a5-41c7-a1a1-425e13782fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671948324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2671948324
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2239647167
Short name T426
Test name
Test status
Simulation time 160188680 ps
CPU time 0.93 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:15 PM PDT 24
Peak memory 198100 kb
Host smart-7d3643e0-6c46-4e2d-acb2-6307ea1585c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239647167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2239647167
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2132260813
Short name T284
Test name
Test status
Simulation time 33456598 ps
CPU time 0.58 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 197972 kb
Host smart-612d164d-8cc6-4713-b41d-c727693cb47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132260813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2132260813
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3970231602
Short name T209
Test name
Test status
Simulation time 48020765 ps
CPU time 0.61 seconds
Started Aug 02 05:16:19 PM PDT 24
Finished Aug 02 05:16:20 PM PDT 24
Peak memory 198012 kb
Host smart-e47fdf6a-6662-404d-a8a2-1241ee575d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970231602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3970231602
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1885721632
Short name T594
Test name
Test status
Simulation time 86852225 ps
CPU time 0.74 seconds
Started Aug 02 05:16:13 PM PDT 24
Finished Aug 02 05:16:14 PM PDT 24
Peak memory 201464 kb
Host smart-4f179a69-48ad-4862-9581-5e584b8f95c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885721632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1885721632
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2167365690
Short name T10
Test name
Test status
Simulation time 69172125 ps
CPU time 0.69 seconds
Started Aug 02 05:16:24 PM PDT 24
Finished Aug 02 05:16:25 PM PDT 24
Peak memory 198388 kb
Host smart-3279629c-dc38-4c7a-af19-b94d447ccede
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167365690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2167365690
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2096158080
Short name T497
Test name
Test status
Simulation time 102414135 ps
CPU time 0.95 seconds
Started Aug 02 05:16:04 PM PDT 24
Finished Aug 02 05:16:05 PM PDT 24
Peak memory 209556 kb
Host smart-65849e34-8972-4866-af9a-03c4a9dba646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096158080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2096158080
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1277132683
Short name T263
Test name
Test status
Simulation time 86187636 ps
CPU time 0.81 seconds
Started Aug 02 05:16:06 PM PDT 24
Finished Aug 02 05:16:07 PM PDT 24
Peak memory 199240 kb
Host smart-cff77ab1-a78f-4b5a-b9d1-c4e5315958b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277132683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1277132683
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.626170128
Short name T586
Test name
Test status
Simulation time 26719070 ps
CPU time 0.68 seconds
Started Aug 02 05:16:23 PM PDT 24
Finished Aug 02 05:16:24 PM PDT 24
Peak memory 199300 kb
Host smart-3300074a-66d5-4265-a118-224fbfe39deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626170128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.626170128
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.4285160566
Short name T616
Test name
Test status
Simulation time 31207419 ps
CPU time 0.77 seconds
Started Aug 02 05:16:27 PM PDT 24
Finished Aug 02 05:16:28 PM PDT 24
Peak memory 198900 kb
Host smart-0a36818e-cfe5-4b81-be95-302514150a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285160566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.4285160566
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1663722808
Short name T521
Test name
Test status
Simulation time 49169400 ps
CPU time 0.79 seconds
Started Aug 02 05:16:11 PM PDT 24
Finished Aug 02 05:16:11 PM PDT 24
Peak memory 198600 kb
Host smart-0269cc9e-8373-4f12-8b16-84894e34cfa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663722808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1663722808
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2389580918
Short name T482
Test name
Test status
Simulation time 31551016 ps
CPU time 0.6 seconds
Started Aug 02 05:16:07 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 197328 kb
Host smart-f07dab9c-4ffd-4729-b9b2-0c5d318dbfd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389580918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.2389580918
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2404504776
Short name T554
Test name
Test status
Simulation time 637329876 ps
CPU time 0.97 seconds
Started Aug 02 05:16:24 PM PDT 24
Finished Aug 02 05:16:26 PM PDT 24
Peak memory 198448 kb
Host smart-d13f72d3-13ef-4ccd-8d6b-13cac41e32b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404504776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2404504776
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.3637120658
Short name T218
Test name
Test status
Simulation time 45795077 ps
CPU time 0.63 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198056 kb
Host smart-20fce97c-a097-4d80-9394-cafc53c32e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637120658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3637120658
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.813480283
Short name T249
Test name
Test status
Simulation time 57087709 ps
CPU time 0.63 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 198136 kb
Host smart-f71f5435-a76b-4a75-9b65-b27338283b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813480283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.813480283
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.4003255428
Short name T184
Test name
Test status
Simulation time 45221483 ps
CPU time 0.75 seconds
Started Aug 02 05:16:09 PM PDT 24
Finished Aug 02 05:16:10 PM PDT 24
Peak memory 201388 kb
Host smart-4e8ccfd9-11a5-4883-98b9-e9bedc684c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003255428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.4003255428
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3734124927
Short name T340
Test name
Test status
Simulation time 89389563 ps
CPU time 0.84 seconds
Started Aug 02 05:16:26 PM PDT 24
Finished Aug 02 05:16:27 PM PDT 24
Peak memory 199200 kb
Host smart-f02f9c14-2c9d-4c71-9981-bd287a30ca25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734124927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3734124927
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.2759384221
Short name T465
Test name
Test status
Simulation time 122648965 ps
CPU time 0.81 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:15 PM PDT 24
Peak memory 209456 kb
Host smart-aadb9d90-b9fc-4fdb-8669-c76ce11e0904
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759384221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2759384221
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2003515183
Short name T358
Test name
Test status
Simulation time 241896105 ps
CPU time 0.73 seconds
Started Aug 02 05:16:23 PM PDT 24
Finished Aug 02 05:16:24 PM PDT 24
Peak memory 198048 kb
Host smart-8000433a-e7bc-49e5-8be3-8d42458ff427
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003515183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2003515183
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1589402180
Short name T373
Test name
Test status
Simulation time 27901556 ps
CPU time 0.66 seconds
Started Aug 02 05:16:20 PM PDT 24
Finished Aug 02 05:16:21 PM PDT 24
Peak memory 199436 kb
Host smart-abae238c-366f-4589-a16d-4b7e07eeb360
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589402180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1589402180
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3109727657
Short name T562
Test name
Test status
Simulation time 95828617 ps
CPU time 0.8 seconds
Started Aug 02 05:16:14 PM PDT 24
Finished Aug 02 05:16:15 PM PDT 24
Peak memory 198772 kb
Host smart-6da6b78c-06cd-49c6-afe1-3cf7ac900d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109727657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3109727657
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1302937325
Short name T472
Test name
Test status
Simulation time 61163446 ps
CPU time 0.68 seconds
Started Aug 02 05:16:21 PM PDT 24
Finished Aug 02 05:16:22 PM PDT 24
Peak memory 199148 kb
Host smart-85c419a9-118a-4241-8371-c5d9a4c2011b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302937325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1302937325
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.2354476543
Short name T268
Test name
Test status
Simulation time 43257916 ps
CPU time 0.58 seconds
Started Aug 02 05:16:15 PM PDT 24
Finished Aug 02 05:16:16 PM PDT 24
Peak memory 197980 kb
Host smart-c7e23c70-b63a-47c8-a606-7c0ef47bee80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354476543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.2354476543
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.291201265
Short name T474
Test name
Test status
Simulation time 755399605 ps
CPU time 0.94 seconds
Started Aug 02 05:15:58 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 198044 kb
Host smart-160c77f6-c7db-4d9e-99f4-2c13ed4b5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291201265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.291201265
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3418546013
Short name T248
Test name
Test status
Simulation time 57147972 ps
CPU time 0.6 seconds
Started Aug 02 05:16:02 PM PDT 24
Finished Aug 02 05:16:03 PM PDT 24
Peak memory 198036 kb
Host smart-23e69f3d-0c3a-465d-bbfe-e43268798f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418546013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3418546013
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3018476060
Short name T398
Test name
Test status
Simulation time 65212602 ps
CPU time 0.58 seconds
Started Aug 02 05:16:08 PM PDT 24
Finished Aug 02 05:16:08 PM PDT 24
Peak memory 198028 kb
Host smart-169e6bdf-c13a-4e9f-b327-18d2f03c5061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018476060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3018476060
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3504504001
Short name T168
Test name
Test status
Simulation time 87692786 ps
CPU time 0.68 seconds
Started Aug 02 05:16:32 PM PDT 24
Finished Aug 02 05:16:33 PM PDT 24
Peak memory 201400 kb
Host smart-ae538422-ae54-4d63-b222-bdceb06a0caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504504001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3504504001
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.3164569535
Short name T459
Test name
Test status
Simulation time 26782412 ps
CPU time 0.71 seconds
Started Aug 02 05:16:26 PM PDT 24
Finished Aug 02 05:16:27 PM PDT 24
Peak memory 199220 kb
Host smart-bd0122d9-4a0b-4bcf-b810-c85c7cd936e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164569535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3164569535
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.3908111599
Short name T582
Test name
Test status
Simulation time 126071628 ps
CPU time 0.9 seconds
Started Aug 02 05:16:27 PM PDT 24
Finished Aug 02 05:16:28 PM PDT 24
Peak memory 209480 kb
Host smart-89de5f8d-b1bc-40af-ac2c-0b6e1a51a264
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908111599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3908111599
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3414937549
Short name T590
Test name
Test status
Simulation time 181727827 ps
CPU time 0.75 seconds
Started Aug 02 05:16:22 PM PDT 24
Finished Aug 02 05:16:23 PM PDT 24
Peak memory 198032 kb
Host smart-d54a6d52-6aae-4186-8a54-2b8af4f4b1c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414937549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3414937549
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.3108796790
Short name T569
Test name
Test status
Simulation time 28731497 ps
CPU time 0.66 seconds
Started Aug 02 05:16:33 PM PDT 24
Finished Aug 02 05:16:34 PM PDT 24
Peak memory 198588 kb
Host smart-8653c87a-454e-4372-9484-2e592a314e57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108796790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3108796790
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.3760301039
Short name T203
Test name
Test status
Simulation time 56169035 ps
CPU time 0.73 seconds
Started Aug 02 05:16:25 PM PDT 24
Finished Aug 02 05:16:26 PM PDT 24
Peak memory 199144 kb
Host smart-ec8a5add-a550-4d34-94bf-6298d33894f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760301039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.3760301039
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2274549134
Short name T618
Test name
Test status
Simulation time 28922431 ps
CPU time 0.63 seconds
Started Aug 02 05:16:25 PM PDT 24
Finished Aug 02 05:16:25 PM PDT 24
Peak memory 198012 kb
Host smart-ffedf39e-c109-4b0d-b99a-dc829d8c6f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274549134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2274549134
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.906572829
Short name T297
Test name
Test status
Simulation time 638745677 ps
CPU time 0.95 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 198104 kb
Host smart-c023cf2b-4aea-463b-9447-31fa10b2d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906572829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.906572829
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.2138844191
Short name T256
Test name
Test status
Simulation time 59806261 ps
CPU time 0.68 seconds
Started Aug 02 05:16:31 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 198020 kb
Host smart-31131a6a-1181-4761-bbce-78f1cf480beb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138844191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2138844191
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3996138886
Short name T222
Test name
Test status
Simulation time 43360781 ps
CPU time 0.6 seconds
Started Aug 02 05:16:16 PM PDT 24
Finished Aug 02 05:16:17 PM PDT 24
Peak memory 198452 kb
Host smart-7901e0cd-63bc-48b4-a3ae-36b0cbae8092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996138886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3996138886
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3620758355
Short name T193
Test name
Test status
Simulation time 39624589 ps
CPU time 0.72 seconds
Started Aug 02 05:16:25 PM PDT 24
Finished Aug 02 05:16:25 PM PDT 24
Peak memory 201180 kb
Host smart-1e579e2c-7891-451c-9b9e-d6f46f964441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620758355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3620758355
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.3390860173
Short name T272
Test name
Test status
Simulation time 109209359 ps
CPU time 0.68 seconds
Started Aug 02 05:16:35 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 198308 kb
Host smart-ccc7cd12-73a6-4b21-b92f-c12b50b6b04a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390860173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.3390860173
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3405556301
Short name T239
Test name
Test status
Simulation time 112024559 ps
CPU time 0.92 seconds
Started Aug 02 05:16:36 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 209456 kb
Host smart-6391a202-5618-4cc0-9e00-927e3666fa33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405556301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3405556301
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.564943137
Short name T471
Test name
Test status
Simulation time 61473709 ps
CPU time 0.83 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:38 PM PDT 24
Peak memory 198212 kb
Host smart-5242654b-b5a6-42b5-b958-ea5d5b31766d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564943137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_
mubi.564943137
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2806247893
Short name T311
Test name
Test status
Simulation time 27693907 ps
CPU time 0.67 seconds
Started Aug 02 05:16:29 PM PDT 24
Finished Aug 02 05:16:30 PM PDT 24
Peak memory 198604 kb
Host smart-37c670f6-1dbd-4d5d-9469-002f941ab4a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806247893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2806247893
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.2823328894
Short name T623
Test name
Test status
Simulation time 43001348 ps
CPU time 0.95 seconds
Started Aug 02 05:16:31 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 200968 kb
Host smart-ef3ed3de-0ab6-40f7-9254-fffe6b206ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823328894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2823328894
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.741089528
Short name T535
Test name
Test status
Simulation time 59016077 ps
CPU time 0.78 seconds
Started Aug 02 05:16:36 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 198508 kb
Host smart-890e3bfd-5665-42dc-8de2-1fdb387ae749
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741089528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.741089528
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.836191975
Short name T133
Test name
Test status
Simulation time 37518279 ps
CPU time 0.7 seconds
Started Aug 02 05:16:31 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 198016 kb
Host smart-6756597e-0003-4314-92b3-2750f69ae8cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836191975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.836191975
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.800733921
Short name T261
Test name
Test status
Simulation time 157244813 ps
CPU time 0.97 seconds
Started Aug 02 05:16:16 PM PDT 24
Finished Aug 02 05:16:17 PM PDT 24
Peak memory 198460 kb
Host smart-8e3c049a-e67b-4111-b217-984d04494d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800733921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.800733921
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3292575717
Short name T255
Test name
Test status
Simulation time 51089488 ps
CPU time 0.6 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 197440 kb
Host smart-29cea706-cea3-4523-8e4a-a792c3e20524
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292575717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3292575717
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.146375789
Short name T440
Test name
Test status
Simulation time 34052053 ps
CPU time 0.61 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 198440 kb
Host smart-54ee4ce1-50e9-40ed-9ee3-a363c2591590
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146375789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.146375789
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.2018789958
Short name T178
Test name
Test status
Simulation time 41137389 ps
CPU time 0.74 seconds
Started Aug 02 05:16:33 PM PDT 24
Finished Aug 02 05:16:34 PM PDT 24
Peak memory 201428 kb
Host smart-bde6f773-f9d6-4205-93b1-04c11444f66a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018789958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.2018789958
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2915791493
Short name T305
Test name
Test status
Simulation time 59164935 ps
CPU time 0.63 seconds
Started Aug 02 05:16:31 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 198320 kb
Host smart-c38d3cd8-79ee-4deb-8241-bc1d027c54a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915791493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2915791493
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.2694645273
Short name T262
Test name
Test status
Simulation time 103651237 ps
CPU time 0.87 seconds
Started Aug 02 05:16:25 PM PDT 24
Finished Aug 02 05:16:26 PM PDT 24
Peak memory 209488 kb
Host smart-036e52b4-6a58-4b77-b5bc-f43c5396c31c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694645273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2694645273
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3721085907
Short name T454
Test name
Test status
Simulation time 57293535 ps
CPU time 0.84 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 198080 kb
Host smart-d2cf5bf8-e7bb-4140-b9e1-83c239e0ac7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721085907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3721085907
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3950671000
Short name T504
Test name
Test status
Simulation time 54267753 ps
CPU time 0.64 seconds
Started Aug 02 05:16:32 PM PDT 24
Finished Aug 02 05:16:32 PM PDT 24
Peak memory 199408 kb
Host smart-e1ca8bc8-b3d5-4a3a-a6e1-f2e079bbd748
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950671000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3950671000
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2113746747
Short name T490
Test name
Test status
Simulation time 55015458 ps
CPU time 0.81 seconds
Started Aug 02 05:16:36 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 200084 kb
Host smart-1edd9799-6b5b-4d42-a828-a3fab0d93c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113746747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2113746747
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3351744397
Short name T448
Test name
Test status
Simulation time 62273204 ps
CPU time 0.82 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:38 PM PDT 24
Peak memory 199120 kb
Host smart-77fdec58-404f-41bf-ad55-5e7abfb3c58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351744397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3351744397
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2752575516
Short name T563
Test name
Test status
Simulation time 29133161 ps
CPU time 0.61 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 197356 kb
Host smart-1500eb25-8b32-499a-85db-40757e6a42d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752575516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.2752575516
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.2696684787
Short name T444
Test name
Test status
Simulation time 1851992981 ps
CPU time 1.02 seconds
Started Aug 02 05:16:41 PM PDT 24
Finished Aug 02 05:16:42 PM PDT 24
Peak memory 198180 kb
Host smart-885bf560-3865-470f-ba6e-c026cb5ea5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696684787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2696684787
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3598077733
Short name T389
Test name
Test status
Simulation time 37023789 ps
CPU time 0.64 seconds
Started Aug 02 05:16:35 PM PDT 24
Finished Aug 02 05:16:36 PM PDT 24
Peak memory 198072 kb
Host smart-76c3c544-9b06-4159-bef9-6ffe0a70366a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598077733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3598077733
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2741395629
Short name T246
Test name
Test status
Simulation time 45638653 ps
CPU time 0.64 seconds
Started Aug 02 05:16:24 PM PDT 24
Finished Aug 02 05:16:24 PM PDT 24
Peak memory 198112 kb
Host smart-c950be48-59f4-461d-892e-04cff9c91015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741395629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2741395629
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3921772014
Short name T194
Test name
Test status
Simulation time 73768869 ps
CPU time 0.62 seconds
Started Aug 02 05:16:36 PM PDT 24
Finished Aug 02 05:16:37 PM PDT 24
Peak memory 201412 kb
Host smart-a5d7baae-f10c-49ef-a1c1-050de04148bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921772014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3921772014
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3169325018
Short name T212
Test name
Test status
Simulation time 64767192 ps
CPU time 0.7 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:38 PM PDT 24
Peak memory 198304 kb
Host smart-74ddc75c-5dd1-446e-a911-408558b90755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169325018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3169325018
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1096181636
Short name T303
Test name
Test status
Simulation time 122588351 ps
CPU time 0.84 seconds
Started Aug 02 05:16:29 PM PDT 24
Finished Aug 02 05:16:30 PM PDT 24
Peak memory 209444 kb
Host smart-57da5c19-5e41-4be4-a0e2-c21dcd640934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096181636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1096181636
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.914770176
Short name T413
Test name
Test status
Simulation time 53918630 ps
CPU time 0.82 seconds
Started Aug 02 05:16:28 PM PDT 24
Finished Aug 02 05:16:29 PM PDT 24
Peak memory 198016 kb
Host smart-4fe382a8-83c6-4a1f-861e-5b7a0aad41ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914770176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.914770176
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.231888914
Short name T399
Test name
Test status
Simulation time 57823047 ps
CPU time 0.64 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:42 PM PDT 24
Peak memory 199360 kb
Host smart-41141c31-aab1-4b02-80ac-7cd1876c717f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231888914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.231888914
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.2480841268
Short name T615
Test name
Test status
Simulation time 29899681 ps
CPU time 0.64 seconds
Started Aug 02 05:16:35 PM PDT 24
Finished Aug 02 05:16:36 PM PDT 24
Peak memory 198228 kb
Host smart-4c67726d-268e-4927-bbe3-11d48670230d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480841268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.2480841268
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.642644834
Short name T96
Test name
Test status
Simulation time 80843895 ps
CPU time 0.72 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:45 PM PDT 24
Peak memory 199004 kb
Host smart-73c6ac8a-0a6f-4fa3-8781-a5a6e27cc4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642644834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.642644834
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.253615238
Short name T519
Test name
Test status
Simulation time 71848627 ps
CPU time 0.66 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:45 PM PDT 24
Peak memory 198524 kb
Host smart-f0066cef-89f5-48f1-abc5-df6b636faca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253615238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disa
ble_rom_integrity_check.253615238
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3094522761
Short name T525
Test name
Test status
Simulation time 28444615 ps
CPU time 0.66 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 198076 kb
Host smart-5e860359-ba86-427b-adee-985450b72626
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094522761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3094522761
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3984585362
Short name T540
Test name
Test status
Simulation time 168001400 ps
CPU time 1 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:50 PM PDT 24
Peak memory 198460 kb
Host smart-7823d97c-b703-422d-8f2c-12b751fdbca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984585362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3984585362
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3028891186
Short name T217
Test name
Test status
Simulation time 53254270 ps
CPU time 0.61 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 197440 kb
Host smart-6918c166-6010-454b-9534-2e30c20a4eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028891186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3028891186
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.478378010
Short name T266
Test name
Test status
Simulation time 33634291 ps
CPU time 0.59 seconds
Started Aug 02 05:16:30 PM PDT 24
Finished Aug 02 05:16:30 PM PDT 24
Peak memory 198160 kb
Host smart-7cb7b2ab-6c64-4cec-98f6-8d223a5b8c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478378010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.478378010
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.4116639585
Short name T536
Test name
Test status
Simulation time 44332145 ps
CPU time 0.73 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 201416 kb
Host smart-b59eefe8-f8cb-4032-a2bb-3b60cfa8f46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116639585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.4116639585
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1519623133
Short name T233
Test name
Test status
Simulation time 64341160 ps
CPU time 0.83 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 199268 kb
Host smart-bd10731a-553f-4040-9569-48ce93691aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519623133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1519623133
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.71350828
Short name T207
Test name
Test status
Simulation time 98847508 ps
CPU time 0.9 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 209564 kb
Host smart-6dfe88f4-0e16-47e3-90f5-e76994661bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71350828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.71350828
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.440440278
Short name T285
Test name
Test status
Simulation time 55505775 ps
CPU time 0.76 seconds
Started Aug 02 05:16:32 PM PDT 24
Finished Aug 02 05:16:33 PM PDT 24
Peak memory 198220 kb
Host smart-d480145c-e79a-4ac0-b569-230a9fb35a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440440278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.440440278
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.464044585
Short name T319
Test name
Test status
Simulation time 36264056 ps
CPU time 0.65 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 199352 kb
Host smart-c2b01d42-0759-4bdf-a2c7-937fe79ccec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464044585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.464044585
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.4057413159
Short name T72
Test name
Test status
Simulation time 55585203 ps
CPU time 0.72 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 199220 kb
Host smart-1a774cd3-fed2-46b4-9383-f4a2b5790dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057413159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.4057413159
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.645803610
Short name T36
Test name
Test status
Simulation time 64951255 ps
CPU time 0.68 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 199144 kb
Host smart-fc82b493-b52c-4fc9-aeaa-3854b1f98e33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645803610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.645803610
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3732823329
Short name T318
Test name
Test status
Simulation time 28367490 ps
CPU time 0.63 seconds
Started Aug 02 05:15:09 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198044 kb
Host smart-7a0749c1-98d2-4503-a841-eb32b2faf149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732823329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3732823329
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1675761312
Short name T267
Test name
Test status
Simulation time 625607597 ps
CPU time 0.97 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 198092 kb
Host smart-b9eb9c0e-b2bd-4188-8e78-74fa21587316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675761312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1675761312
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.1863863609
Short name T583
Test name
Test status
Simulation time 31744940 ps
CPU time 0.66 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 197460 kb
Host smart-1373dc67-6a5b-47ab-a936-d1e9bc8d6d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863863609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.1863863609
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.547247973
Short name T320
Test name
Test status
Simulation time 302052427 ps
CPU time 0.68 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:59 PM PDT 24
Peak memory 198116 kb
Host smart-f305a6e2-f7d3-491a-90bf-5c3bc3209080
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547247973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.547247973
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.3143828462
Short name T48
Test name
Test status
Simulation time 40060199 ps
CPU time 0.75 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 199192 kb
Host smart-24d283ce-5a17-467d-b8c7-73676f0c3405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143828462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3143828462
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2579255661
Short name T227
Test name
Test status
Simulation time 119205621 ps
CPU time 0.85 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 209592 kb
Host smart-8880898d-59e5-4d8b-a8df-caf279faf442
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579255661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2579255661
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.4154647281
Short name T21
Test name
Test status
Simulation time 341406602 ps
CPU time 1.49 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:06 PM PDT 24
Peak memory 216928 kb
Host smart-9978f2d5-1c24-4f64-a91e-7669c279f04e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154647281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.4154647281
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.411797056
Short name T67
Test name
Test status
Simulation time 92543453 ps
CPU time 0.63 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 198596 kb
Host smart-d61a57bd-fe22-4eb3-a976-4c95244d2c46
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411797056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm
_ctrl_config_regwen.411797056
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2974322656
Short name T123
Test name
Test status
Simulation time 57901840 ps
CPU time 0.8 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 198200 kb
Host smart-a5c0e58f-b8bb-40a3-8e90-d16d5d8db3e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974322656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2974322656
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1951431847
Short name T88
Test name
Test status
Simulation time 119202075 ps
CPU time 0.62 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198612 kb
Host smart-f693924a-ee63-4717-81d4-d138e7487fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951431847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1951431847
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.1267692370
Short name T143
Test name
Test status
Simulation time 47976591 ps
CPU time 0.59 seconds
Started Aug 02 05:14:56 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 198224 kb
Host smart-40c6ea23-1a45-4fbb-8fc9-58853c2a616f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267692370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1267692370
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.4169864626
Short name T542
Test name
Test status
Simulation time 50998071 ps
CPU time 0.99 seconds
Started Aug 02 05:16:46 PM PDT 24
Finished Aug 02 05:16:47 PM PDT 24
Peak memory 200980 kb
Host smart-2c4acc7f-b226-4679-bbef-b508472ae143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169864626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.4169864626
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2785039621
Short name T450
Test name
Test status
Simulation time 68757104 ps
CPU time 0.72 seconds
Started Aug 02 05:16:41 PM PDT 24
Finished Aug 02 05:16:42 PM PDT 24
Peak memory 199124 kb
Host smart-e63bd5a7-5301-452f-bf43-8f7af02937ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785039621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2785039621
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3077141329
Short name T456
Test name
Test status
Simulation time 43237588 ps
CPU time 0.58 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 197376 kb
Host smart-07b3bdf6-de2d-47da-8762-ce4388de873a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077141329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3077141329
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3183850860
Short name T464
Test name
Test status
Simulation time 162786095 ps
CPU time 0.92 seconds
Started Aug 02 05:16:43 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 198144 kb
Host smart-800b9863-0c58-4862-a303-232cd1c20578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183850860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3183850860
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2612335986
Short name T463
Test name
Test status
Simulation time 274495289 ps
CPU time 0.61 seconds
Started Aug 02 05:16:35 PM PDT 24
Finished Aug 02 05:16:36 PM PDT 24
Peak memory 198164 kb
Host smart-8ac9121c-51a6-4f8e-a13a-c9505452267f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612335986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2612335986
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3144079290
Short name T13
Test name
Test status
Simulation time 91270819 ps
CPU time 0.6 seconds
Started Aug 02 05:16:43 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 198396 kb
Host smart-4e9b3dd5-6a9d-4b39-8f48-62d4af0e1051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144079290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3144079290
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2344930815
Short name T163
Test name
Test status
Simulation time 52300824 ps
CPU time 0.67 seconds
Started Aug 02 05:16:33 PM PDT 24
Finished Aug 02 05:16:34 PM PDT 24
Peak memory 201416 kb
Host smart-7d2e08e9-6da3-44cc-b0e4-ce67872a8cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344930815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2344930815
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3612186771
Short name T260
Test name
Test status
Simulation time 35376060 ps
CPU time 0.63 seconds
Started Aug 02 05:16:49 PM PDT 24
Finished Aug 02 05:16:50 PM PDT 24
Peak memory 198056 kb
Host smart-d1058323-fe23-4eda-af8e-6598cc8d1ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612186771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3612186771
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2517009799
Short name T300
Test name
Test status
Simulation time 130126976 ps
CPU time 0.83 seconds
Started Aug 02 05:16:28 PM PDT 24
Finished Aug 02 05:16:29 PM PDT 24
Peak memory 209528 kb
Host smart-882f6047-56e1-4ebb-a348-5191a8f57626
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517009799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2517009799
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2797133173
Short name T243
Test name
Test status
Simulation time 71718309 ps
CPU time 0.93 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 199492 kb
Host smart-a1a84ce8-c8e9-458e-b460-3b30a9e37463
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797133173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2797133173
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.3811896943
Short name T506
Test name
Test status
Simulation time 82029966 ps
CPU time 0.63 seconds
Started Aug 02 05:16:43 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 198560 kb
Host smart-b8ee57af-e725-49fd-82c1-89997c4a46c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811896943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3811896943
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1942356510
Short name T420
Test name
Test status
Simulation time 30659206 ps
CPU time 0.75 seconds
Started Aug 02 05:16:33 PM PDT 24
Finished Aug 02 05:16:34 PM PDT 24
Peak memory 198964 kb
Host smart-61d11714-064e-43dd-9668-92922f09e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942356510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1942356510
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.4146712307
Short name T204
Test name
Test status
Simulation time 82579280 ps
CPU time 0.68 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 199268 kb
Host smart-028aadc6-f336-4042-bb63-d23fa87fb971
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146712307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.4146712307
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3340094087
Short name T287
Test name
Test status
Simulation time 30232902 ps
CPU time 0.67 seconds
Started Aug 02 05:16:58 PM PDT 24
Finished Aug 02 05:16:59 PM PDT 24
Peak memory 198048 kb
Host smart-6c57f37d-8f26-49fd-82a0-5d8073e396dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340094087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3340094087
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2525438692
Short name T629
Test name
Test status
Simulation time 159227224 ps
CPU time 0.99 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 198440 kb
Host smart-a2723ba5-110a-4c4a-9709-4dd3c40abaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525438692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2525438692
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1306805835
Short name T613
Test name
Test status
Simulation time 57446494 ps
CPU time 0.59 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:45 PM PDT 24
Peak memory 198140 kb
Host smart-6e76e814-936e-4a62-a376-de72a6b7c81c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306805835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1306805835
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1347600117
Short name T225
Test name
Test status
Simulation time 77655758 ps
CPU time 0.6 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 198132 kb
Host smart-ecd3f33b-ee94-4dd4-a0a3-20208bfbecde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347600117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1347600117
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2983768939
Short name T449
Test name
Test status
Simulation time 85358720 ps
CPU time 0.67 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 201452 kb
Host smart-986c515e-b38a-455d-a1c1-57229ca906fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983768939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2983768939
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2772063152
Short name T349
Test name
Test status
Simulation time 61652508 ps
CPU time 0.85 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:38 PM PDT 24
Peak memory 199160 kb
Host smart-731afeab-d417-4be1-9170-f55517146be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772063152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2772063152
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1783012944
Short name T499
Test name
Test status
Simulation time 119741176 ps
CPU time 0.9 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 209448 kb
Host smart-6b6f252b-1575-4f9b-9076-ffe453557b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783012944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1783012944
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1047239544
Short name T418
Test name
Test status
Simulation time 75312078 ps
CPU time 0.74 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:45 PM PDT 24
Peak memory 198228 kb
Host smart-a554727a-0546-4fe4-bf81-f9ace75cd5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047239544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1047239544
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3671515565
Short name T385
Test name
Test status
Simulation time 64591145 ps
CPU time 0.63 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 198600 kb
Host smart-17d2b180-42e8-4d53-b9d2-356791967e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671515565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3671515565
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.2897785856
Short name T363
Test name
Test status
Simulation time 147383207 ps
CPU time 0.66 seconds
Started Aug 02 05:16:45 PM PDT 24
Finished Aug 02 05:16:45 PM PDT 24
Peak memory 198684 kb
Host smart-b3e3c464-7e04-400d-bb20-d1a3c1020780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897785856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2897785856
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3721126459
Short name T430
Test name
Test status
Simulation time 61604778 ps
CPU time 0.84 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198600 kb
Host smart-e0f8a3e3-da83-4646-9a46-c8103cccfcfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721126459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3721126459
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2649988692
Short name T351
Test name
Test status
Simulation time 38444938 ps
CPU time 0.59 seconds
Started Aug 02 05:16:41 PM PDT 24
Finished Aug 02 05:16:42 PM PDT 24
Peak memory 198060 kb
Host smart-01395dd6-061f-4dac-b956-28d351982de8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649988692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2649988692
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.2569804987
Short name T5
Test name
Test status
Simulation time 624925448 ps
CPU time 0.94 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198088 kb
Host smart-62fd0d8c-e4ed-4dfc-a23c-e2be9cf17589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569804987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2569804987
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.3968666631
Short name T503
Test name
Test status
Simulation time 48493717 ps
CPU time 0.61 seconds
Started Aug 02 05:16:29 PM PDT 24
Finished Aug 02 05:16:30 PM PDT 24
Peak memory 197456 kb
Host smart-b616f1a7-d72f-41b0-8270-a8d3d4a639fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968666631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3968666631
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.511833092
Short name T559
Test name
Test status
Simulation time 50112512 ps
CPU time 0.61 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198108 kb
Host smart-ce04869f-ad2b-4cdb-bdcb-949afd9d27b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511833092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.511833092
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3992105824
Short name T436
Test name
Test status
Simulation time 41189172 ps
CPU time 0.7 seconds
Started Aug 02 05:16:50 PM PDT 24
Finished Aug 02 05:16:51 PM PDT 24
Peak memory 199180 kb
Host smart-fefe1c56-1473-499a-a0f5-5d86536f0ad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992105824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3992105824
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1467348682
Short name T520
Test name
Test status
Simulation time 116179492 ps
CPU time 0.84 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 209536 kb
Host smart-cdc40c7b-0765-4914-a001-dc172291f324
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467348682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1467348682
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.646871389
Short name T288
Test name
Test status
Simulation time 54787891 ps
CPU time 0.82 seconds
Started Aug 02 05:16:35 PM PDT 24
Finished Aug 02 05:16:36 PM PDT 24
Peak memory 199488 kb
Host smart-d1f56cf4-6c22-4bf0-a592-cc512212d8aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646871389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.646871389
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.336467787
Short name T545
Test name
Test status
Simulation time 35470077 ps
CPU time 0.67 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 198420 kb
Host smart-d729e7a0-5786-4a85-8867-0c15327f5a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336467787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.336467787
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.2486048981
Short name T142
Test name
Test status
Simulation time 56487353 ps
CPU time 0.77 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 199148 kb
Host smart-8cbdb880-3e9c-489d-9fe1-6d81dcffe0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486048981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2486048981
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.4120872015
Short name T162
Test name
Test status
Simulation time 54219239 ps
CPU time 0.81 seconds
Started Aug 02 05:16:43 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 198520 kb
Host smart-b3e58f4b-d0a6-487a-9653-ce72ae3ce9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120872015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.4120872015
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2462227034
Short name T397
Test name
Test status
Simulation time 39738762 ps
CPU time 0.62 seconds
Started Aug 02 05:16:46 PM PDT 24
Finished Aug 02 05:16:47 PM PDT 24
Peak memory 198112 kb
Host smart-5a88477a-2d3a-43f5-8101-5962070c89b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462227034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.2462227034
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3135897167
Short name T374
Test name
Test status
Simulation time 639218864 ps
CPU time 0.95 seconds
Started Aug 02 05:16:38 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198088 kb
Host smart-09630faf-9a3d-43ac-a60c-87ad42679765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135897167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3135897167
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2941217752
Short name T47
Test name
Test status
Simulation time 56496632 ps
CPU time 0.62 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 198092 kb
Host smart-74c2261a-efea-48cb-9a28-9cf5194209fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941217752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2941217752
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.1848426553
Short name T56
Test name
Test status
Simulation time 28850235 ps
CPU time 0.6 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 198468 kb
Host smart-8729646c-6628-4b59-a37d-4fe2ffadf379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848426553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1848426553
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.262138513
Short name T407
Test name
Test status
Simulation time 42368686 ps
CPU time 0.73 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 201144 kb
Host smart-da65f577-4e13-4f1d-a246-24f628aa5968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262138513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.262138513
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.4087591447
Short name T592
Test name
Test status
Simulation time 54703406 ps
CPU time 0.7 seconds
Started Aug 02 05:16:37 PM PDT 24
Finished Aug 02 05:16:38 PM PDT 24
Peak memory 199080 kb
Host smart-3413ec9d-fed4-45ec-b6a1-f8636b990994
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087591447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.4087591447
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1050044254
Short name T309
Test name
Test status
Simulation time 109513330 ps
CPU time 0.97 seconds
Started Aug 02 05:17:00 PM PDT 24
Finished Aug 02 05:17:01 PM PDT 24
Peak memory 209532 kb
Host smart-8a2e1343-bc71-47e8-9751-5db4f8d20f99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050044254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1050044254
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2122161022
Short name T507
Test name
Test status
Simulation time 63554543 ps
CPU time 0.92 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 198964 kb
Host smart-c8edd1ed-51f6-4c17-a8ac-f44fdec80e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122161022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2122161022
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.3995074578
Short name T383
Test name
Test status
Simulation time 67428886 ps
CPU time 0.63 seconds
Started Aug 02 05:16:39 PM PDT 24
Finished Aug 02 05:16:39 PM PDT 24
Peak memory 198584 kb
Host smart-b64d6053-65ab-4a05-97b9-bbc358b75f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995074578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3995074578
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1388214975
Short name T331
Test name
Test status
Simulation time 52556746 ps
CPU time 0.74 seconds
Started Aug 02 05:16:46 PM PDT 24
Finished Aug 02 05:16:47 PM PDT 24
Peak memory 198860 kb
Host smart-362230bf-6144-46ba-8e6d-47b407cb1aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388214975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1388214975
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3420475633
Short name T457
Test name
Test status
Simulation time 57088911 ps
CPU time 0.78 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 198684 kb
Host smart-9f1130a4-db3d-4ccb-af3e-979a9ca70eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420475633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3420475633
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1132955055
Short name T524
Test name
Test status
Simulation time 32340968 ps
CPU time 0.64 seconds
Started Aug 02 05:16:42 PM PDT 24
Finished Aug 02 05:16:43 PM PDT 24
Peak memory 198028 kb
Host smart-94122fb3-f7fa-4ed4-b24d-a43c29fbed69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132955055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1132955055
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.1051154130
Short name T442
Test name
Test status
Simulation time 162689682 ps
CPU time 0.94 seconds
Started Aug 02 05:16:51 PM PDT 24
Finished Aug 02 05:16:52 PM PDT 24
Peak memory 198160 kb
Host smart-98c430d1-7ab6-4c08-97bf-63480f6d34b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051154130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1051154130
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.4054340654
Short name T534
Test name
Test status
Simulation time 44206593 ps
CPU time 0.66 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 197292 kb
Host smart-18b38dce-18f1-4da3-a7ea-9fb857c2563b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054340654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.4054340654
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1546151736
Short name T259
Test name
Test status
Simulation time 43833126 ps
CPU time 0.6 seconds
Started Aug 02 05:16:41 PM PDT 24
Finished Aug 02 05:16:41 PM PDT 24
Peak memory 198448 kb
Host smart-9e16ced0-f759-400b-9756-02ad862e14d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546151736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1546151736
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2367154218
Short name T240
Test name
Test status
Simulation time 41752244 ps
CPU time 0.68 seconds
Started Aug 02 05:16:45 PM PDT 24
Finished Aug 02 05:16:46 PM PDT 24
Peak memory 201328 kb
Host smart-5a916d73-fbbd-4fa7-ae29-940f548601e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367154218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2367154218
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2811833441
Short name T279
Test name
Test status
Simulation time 72362489 ps
CPU time 0.89 seconds
Started Aug 02 05:16:34 PM PDT 24
Finished Aug 02 05:16:35 PM PDT 24
Peak memory 198648 kb
Host smart-cf8ab291-557a-418f-a251-494d4ec08911
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811833441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2811833441
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4249929678
Short name T367
Test name
Test status
Simulation time 313219958 ps
CPU time 0.74 seconds
Started Aug 02 05:16:45 PM PDT 24
Finished Aug 02 05:16:46 PM PDT 24
Peak memory 209596 kb
Host smart-0f8f651c-8823-4e36-81f1-b63941d43d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249929678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4249929678
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3087809576
Short name T544
Test name
Test status
Simulation time 71624765 ps
CPU time 0.96 seconds
Started Aug 02 05:16:50 PM PDT 24
Finished Aug 02 05:16:51 PM PDT 24
Peak memory 199236 kb
Host smart-3ebc9a18-6858-4bef-89e5-6d3fd9450dde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087809576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3087809576
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.2294810303
Short name T513
Test name
Test status
Simulation time 27940646 ps
CPU time 0.69 seconds
Started Aug 02 05:16:41 PM PDT 24
Finished Aug 02 05:16:42 PM PDT 24
Peak memory 199416 kb
Host smart-28877c34-337b-4929-b4f2-bdbe75af8d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294810303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2294810303
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3157179316
Short name T496
Test name
Test status
Simulation time 31132016 ps
CPU time 0.66 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 198664 kb
Host smart-fb0a57f5-629e-4312-a001-21fb6992a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157179316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3157179316
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3385454539
Short name T154
Test name
Test status
Simulation time 56417742 ps
CPU time 0.69 seconds
Started Aug 02 05:16:43 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 199232 kb
Host smart-865008b4-a5b2-4e78-9c13-0214e26f5467
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385454539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3385454539
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3916195974
Short name T223
Test name
Test status
Simulation time 29415917 ps
CPU time 0.7 seconds
Started Aug 02 05:17:01 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 198028 kb
Host smart-e6c9a7f7-82e0-4188-8c7c-781232041569
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916195974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3916195974
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.2370195057
Short name T522
Test name
Test status
Simulation time 165610950 ps
CPU time 0.96 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:16:55 PM PDT 24
Peak memory 198128 kb
Host smart-8c37ed4e-0038-42e3-9901-3bd3fd96a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370195057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2370195057
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.4010893505
Short name T432
Test name
Test status
Simulation time 56015900 ps
CPU time 0.67 seconds
Started Aug 02 05:16:51 PM PDT 24
Finished Aug 02 05:16:52 PM PDT 24
Peak memory 197956 kb
Host smart-e8d2e89e-8092-4c18-9519-4ff611afcf7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010893505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.4010893505
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1351845921
Short name T215
Test name
Test status
Simulation time 44628707 ps
CPU time 0.6 seconds
Started Aug 02 05:17:01 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 198068 kb
Host smart-b8e98fe5-ad0c-4fa6-9128-5644038b95aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351845921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1351845921
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1553899795
Short name T187
Test name
Test status
Simulation time 65784746 ps
CPU time 0.68 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 201308 kb
Host smart-72f54fba-58ca-4bf7-95ec-281eb1235e40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553899795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1553899795
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.3569923825
Short name T343
Test name
Test status
Simulation time 76452287 ps
CPU time 0.74 seconds
Started Aug 02 05:17:08 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 199168 kb
Host smart-ea019d11-47e7-4072-bfd9-c357691a8c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569923825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.3569923825
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.159923564
Short name T290
Test name
Test status
Simulation time 158168082 ps
CPU time 0.84 seconds
Started Aug 02 05:16:49 PM PDT 24
Finished Aug 02 05:16:50 PM PDT 24
Peak memory 209520 kb
Host smart-c1587712-bfce-421d-bbbc-f407f07cca38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159923564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.159923564
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3267297492
Short name T299
Test name
Test status
Simulation time 64667377 ps
CPU time 0.85 seconds
Started Aug 02 05:16:53 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 199224 kb
Host smart-42290247-a4ff-4758-9553-4c715959e6ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267297492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3267297492
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1238494928
Short name T493
Test name
Test status
Simulation time 31552687 ps
CPU time 0.67 seconds
Started Aug 02 05:16:40 PM PDT 24
Finished Aug 02 05:16:40 PM PDT 24
Peak memory 198536 kb
Host smart-4c52a6a0-f8f5-4422-a8e5-6be3e341da60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238494928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1238494928
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.2008062461
Short name T199
Test name
Test status
Simulation time 182080657 ps
CPU time 1.02 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 200984 kb
Host smart-3cf99b31-991c-4bc9-9ee9-bba02c810349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008062461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.2008062461
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.661679571
Short name T527
Test name
Test status
Simulation time 68688264 ps
CPU time 0.69 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 199184 kb
Host smart-4982a1bf-0513-4d30-8270-d567d30d07f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661679571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.661679571
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1655965728
Short name T136
Test name
Test status
Simulation time 70747897 ps
CPU time 0.67 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:07 PM PDT 24
Peak memory 198364 kb
Host smart-8642ed70-05d4-45b9-99b3-4d81327b68b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655965728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1655965728
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.4136177062
Short name T264
Test name
Test status
Simulation time 107128268 ps
CPU time 0.59 seconds
Started Aug 02 05:16:51 PM PDT 24
Finished Aug 02 05:16:52 PM PDT 24
Peak memory 197964 kb
Host smart-7719759d-d182-4b3b-a841-ce3ab61aa568
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136177062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.4136177062
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.1311257975
Short name T509
Test name
Test status
Simulation time 168690485 ps
CPU time 0.93 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 198164 kb
Host smart-93594f1e-5633-4ba0-b12d-e24117084bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311257975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1311257975
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2946437069
Short name T528
Test name
Test status
Simulation time 46022111 ps
CPU time 0.68 seconds
Started Aug 02 05:16:46 PM PDT 24
Finished Aug 02 05:16:47 PM PDT 24
Peak memory 197420 kb
Host smart-67d6a068-a0ae-401f-8629-4123158482a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946437069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2946437069
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.686068701
Short name T400
Test name
Test status
Simulation time 88410188 ps
CPU time 0.62 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:07 PM PDT 24
Peak memory 198136 kb
Host smart-8fcaca8f-40d7-4c46-a32e-fe9846c1d834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686068701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.686068701
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3051986711
Short name T553
Test name
Test status
Simulation time 79315760 ps
CPU time 0.65 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 201324 kb
Host smart-0ba3a4df-3706-46fb-ae82-c36ac5336601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051986711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3051986711
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2917679007
Short name T18
Test name
Test status
Simulation time 145466762 ps
CPU time 0.75 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:08 PM PDT 24
Peak memory 199232 kb
Host smart-a73f83f7-ea00-49a2-a98f-a0dd9875903a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917679007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2917679007
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.290751467
Short name T274
Test name
Test status
Simulation time 158551526 ps
CPU time 0.8 seconds
Started Aug 02 05:16:45 PM PDT 24
Finished Aug 02 05:16:46 PM PDT 24
Peak memory 209488 kb
Host smart-31aeb4bb-544f-41a9-93af-e541573d22a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290751467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.290751467
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.843272809
Short name T257
Test name
Test status
Simulation time 74343567 ps
CPU time 0.73 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 198120 kb
Host smart-2d1abf6d-e7ce-4752-9912-d7271216d370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843272809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_
mubi.843272809
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2545214477
Short name T610
Test name
Test status
Simulation time 41178519 ps
CPU time 0.62 seconds
Started Aug 02 05:16:44 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 199256 kb
Host smart-1fbed4b6-55ae-4ba8-bce9-4376494fc018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545214477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2545214477
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1538855334
Short name T577
Test name
Test status
Simulation time 44718610 ps
CPU time 0.78 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 198524 kb
Host smart-f17f0797-892a-4109-8950-9f8d9261b288
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538855334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1538855334
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3125170153
Short name T226
Test name
Test status
Simulation time 32497831 ps
CPU time 0.58 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:53 PM PDT 24
Peak memory 197428 kb
Host smart-5b5d9c43-21a9-4ac4-b1b4-fb11aea815d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125170153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3125170153
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2526208394
Short name T292
Test name
Test status
Simulation time 836949996 ps
CPU time 0.96 seconds
Started Aug 02 05:17:01 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 198164 kb
Host smart-e548afbe-2b63-4a6a-bbc5-b0b18b359617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526208394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2526208394
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1784761845
Short name T286
Test name
Test status
Simulation time 64156239 ps
CPU time 0.62 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 197504 kb
Host smart-8adc92a9-4807-44e7-a4d5-80db94536a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784761845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1784761845
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2478121309
Short name T51
Test name
Test status
Simulation time 89905324 ps
CPU time 0.62 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 198200 kb
Host smart-60c82694-49e3-4c23-825a-b94d675a9173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478121309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2478121309
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.171722798
Short name T174
Test name
Test status
Simulation time 80193581 ps
CPU time 0.66 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 201184 kb
Host smart-40c738e6-4b89-406d-85a8-487f97804998
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171722798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invali
d.171722798
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.4214238399
Short name T328
Test name
Test status
Simulation time 94617822 ps
CPU time 0.81 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 198500 kb
Host smart-7cc679cb-fb6d-4787-ad37-22e25fdf8692
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214238399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.4214238399
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3939962693
Short name T403
Test name
Test status
Simulation time 169397443 ps
CPU time 0.81 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 209464 kb
Host smart-c3ace771-8d14-4ce3-a92c-d02a78b278aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939962693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3939962693
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.21978869
Short name T584
Test name
Test status
Simulation time 96957521 ps
CPU time 0.69 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 197976 kb
Host smart-644f0817-270d-47e0-8308-926fe412b585
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.21978869
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1994244614
Short name T360
Test name
Test status
Simulation time 51869704 ps
CPU time 0.63 seconds
Started Aug 02 05:17:08 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 198424 kb
Host smart-e8c53bd9-a193-4c6c-8036-495efb85f329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994244614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1994244614
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.906319272
Short name T125
Test name
Test status
Simulation time 33551927 ps
CPU time 0.74 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 198932 kb
Host smart-b9e5bb66-16f5-4539-aee3-0c1ef438df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906319272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.906319272
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.4001182711
Short name T33
Test name
Test status
Simulation time 49527625 ps
CPU time 0.75 seconds
Started Aug 02 05:17:01 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 199152 kb
Host smart-a5f7b2db-4fa4-448e-ad62-f4d73a7d15f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001182711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.4001182711
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.632784819
Short name T132
Test name
Test status
Simulation time 39039576 ps
CPU time 0.57 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 198080 kb
Host smart-120dc4f9-b0b6-4126-8f1a-71a04045d777
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632784819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.632784819
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2819001689
Short name T492
Test name
Test status
Simulation time 586998886 ps
CPU time 0.94 seconds
Started Aug 02 05:17:09 PM PDT 24
Finished Aug 02 05:17:10 PM PDT 24
Peak memory 198152 kb
Host smart-cc3ca43d-f7f8-4882-b440-3ea92f359805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819001689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2819001689
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.2590105148
Short name T275
Test name
Test status
Simulation time 40420388 ps
CPU time 0.65 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:03 PM PDT 24
Peak memory 198224 kb
Host smart-59661c46-a19a-4d01-a6e8-a1e502a1f8b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590105148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2590105148
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3944277169
Short name T298
Test name
Test status
Simulation time 102017412 ps
CPU time 0.58 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:05 PM PDT 24
Peak memory 198176 kb
Host smart-9e295b18-fe8e-483f-8951-f2d42e1495a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944277169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3944277169
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3265968055
Short name T179
Test name
Test status
Simulation time 47563582 ps
CPU time 0.67 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 201440 kb
Host smart-27e91484-488a-45ea-808b-fabfcafdf4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265968055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3265968055
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.2738195433
Short name T301
Test name
Test status
Simulation time 42726963 ps
CPU time 0.69 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:16:59 PM PDT 24
Peak memory 198424 kb
Host smart-bc9a1c4b-197f-4360-b2a1-944e9d58cac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738195433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2738195433
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.620015593
Short name T550
Test name
Test status
Simulation time 153149442 ps
CPU time 0.78 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:16:55 PM PDT 24
Peak memory 209504 kb
Host smart-89751005-0388-41e6-b1ca-ced5030c5e85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620015593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.620015593
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1233343492
Short name T282
Test name
Test status
Simulation time 100959325 ps
CPU time 0.71 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 198156 kb
Host smart-ff55b9a0-c95a-4c14-b233-2a348f743052
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233343492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1233343492
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.536379139
Short name T89
Test name
Test status
Simulation time 50189095 ps
CPU time 0.67 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 199356 kb
Host smart-e825ecbf-433c-4721-aa42-a614477c8d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536379139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.536379139
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.940958122
Short name T587
Test name
Test status
Simulation time 41654767 ps
CPU time 0.69 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 199384 kb
Host smart-d0deb90e-89bc-4b4f-ac68-6e899067db94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940958122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.940958122
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.3137416562
Short name T478
Test name
Test status
Simulation time 29808260 ps
CPU time 0.73 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 199160 kb
Host smart-8897a97a-495b-4129-9a31-61c98ddeb176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137416562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.3137416562
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1616596486
Short name T202
Test name
Test status
Simulation time 94260575 ps
CPU time 0.68 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:10 PM PDT 24
Peak memory 198540 kb
Host smart-1ebde422-f63e-4f54-9e2c-2bb5a6854f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616596486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1616596486
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3604037942
Short name T622
Test name
Test status
Simulation time 39341044 ps
CPU time 0.61 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:58 PM PDT 24
Peak memory 198052 kb
Host smart-6376ced0-b8c4-4fa7-839f-64285a39a22d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604037942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3604037942
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3146010815
Short name T359
Test name
Test status
Simulation time 183318426 ps
CPU time 0.93 seconds
Started Aug 02 05:16:53 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 198120 kb
Host smart-ba32c9f9-f712-4907-845c-9c50ad99d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146010815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3146010815
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.404519955
Short name T477
Test name
Test status
Simulation time 63098651 ps
CPU time 0.71 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:04 PM PDT 24
Peak memory 197320 kb
Host smart-fbf39b10-34b8-4fb3-99de-ee9d526ba7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404519955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.404519955
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.322704339
Short name T601
Test name
Test status
Simulation time 108856387 ps
CPU time 0.61 seconds
Started Aug 02 05:17:05 PM PDT 24
Finished Aug 02 05:17:06 PM PDT 24
Peak memory 198148 kb
Host smart-25b5d295-0d08-461b-a0bb-8f0c3be4375d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322704339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.322704339
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2826514597
Short name T543
Test name
Test status
Simulation time 79796402 ps
CPU time 0.62 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 199168 kb
Host smart-23f031cc-a7b0-43b6-8d2c-4037ba27a361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826514597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2826514597
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1363689483
Short name T346
Test name
Test status
Simulation time 348806829 ps
CPU time 0.78 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:03 PM PDT 24
Peak memory 209484 kb
Host smart-8c385966-5d4c-46fb-80c5-83228e9700fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363689483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1363689483
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.430830500
Short name T289
Test name
Test status
Simulation time 58306641 ps
CPU time 0.77 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 198056 kb
Host smart-dd62662e-756d-454f-be37-d6ce65119dfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430830500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.430830500
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1530131241
Short name T380
Test name
Test status
Simulation time 26616427 ps
CPU time 0.68 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:05 PM PDT 24
Peak memory 199300 kb
Host smart-367808c4-3682-4d71-a1a7-712abb7ab071
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530131241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1530131241
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2966043488
Short name T421
Test name
Test status
Simulation time 48019139 ps
CPU time 0.95 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 200316 kb
Host smart-096f40ad-1e80-491a-9692-4673ee77209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966043488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2966043488
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.133203514
Short name T485
Test name
Test status
Simulation time 62497721 ps
CPU time 0.79 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 199116 kb
Host smart-4b960558-3afe-4379-a03d-eb1b99eba230
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133203514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disab
le_rom_integrity_check.133203514
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.4275450367
Short name T127
Test name
Test status
Simulation time 39231006 ps
CPU time 0.6 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 198048 kb
Host smart-ff5af17d-5e9d-48f0-a839-c5b2b258a0fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275450367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.4275450367
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2948261525
Short name T470
Test name
Test status
Simulation time 315091806 ps
CPU time 0.96 seconds
Started Aug 02 05:15:21 PM PDT 24
Finished Aug 02 05:15:22 PM PDT 24
Peak memory 198440 kb
Host smart-865c62e9-9e1d-4f38-9259-614de16d52f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948261525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2948261525
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2382949416
Short name T39
Test name
Test status
Simulation time 54854893 ps
CPU time 0.62 seconds
Started Aug 02 05:15:11 PM PDT 24
Finished Aug 02 05:15:12 PM PDT 24
Peak memory 198068 kb
Host smart-98e6b998-46d5-4bde-8651-8abdc8b65b3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382949416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2382949416
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3209763570
Short name T283
Test name
Test status
Simulation time 52893143 ps
CPU time 0.58 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 198144 kb
Host smart-bdee1c48-9b40-4c46-b26d-d104cc4809c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209763570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3209763570
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1487932401
Short name T175
Test name
Test status
Simulation time 49154332 ps
CPU time 0.68 seconds
Started Aug 02 05:15:24 PM PDT 24
Finished Aug 02 05:15:25 PM PDT 24
Peak memory 201436 kb
Host smart-283b6a19-9a22-4e12-aeaa-09e0f693e55a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487932401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1487932401
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2980561219
Short name T355
Test name
Test status
Simulation time 69160162 ps
CPU time 0.85 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 199220 kb
Host smart-a77ddb85-56a7-4531-8b5e-52cd7e02bf1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980561219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2980561219
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.335221589
Short name T595
Test name
Test status
Simulation time 144644520 ps
CPU time 0.82 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 209500 kb
Host smart-a81b85c1-e62d-4564-a3b6-9a64264e934d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335221589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.335221589
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2782279432
Short name T231
Test name
Test status
Simulation time 57714127 ps
CPU time 0.82 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:08 PM PDT 24
Peak memory 198172 kb
Host smart-f1ad77a4-01a9-4e7c-af1a-55c973851fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782279432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2782279432
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.3085749455
Short name T92
Test name
Test status
Simulation time 38952311 ps
CPU time 0.65 seconds
Started Aug 02 05:15:17 PM PDT 24
Finished Aug 02 05:15:18 PM PDT 24
Peak memory 199448 kb
Host smart-ae2e27dd-fdc9-422a-b764-948e2db81876
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085749455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3085749455
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3152974708
Short name T322
Test name
Test status
Simulation time 21381960 ps
CPU time 0.77 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 199192 kb
Host smart-6bde3c3e-7885-4c7e-8372-d9e49db232ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152974708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3152974708
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1578854056
Short name T158
Test name
Test status
Simulation time 87772470 ps
CPU time 0.69 seconds
Started Aug 02 05:15:23 PM PDT 24
Finished Aug 02 05:15:23 PM PDT 24
Peak memory 199212 kb
Host smart-a4f9735b-a18b-4e67-8c4f-05c2a50973cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578854056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1578854056
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1637354568
Short name T245
Test name
Test status
Simulation time 30975069 ps
CPU time 0.63 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:53 PM PDT 24
Peak memory 198088 kb
Host smart-42b70217-0a03-454b-90e9-144e215ef23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637354568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1637354568
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.478144220
Short name T278
Test name
Test status
Simulation time 688515414 ps
CPU time 0.91 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198380 kb
Host smart-880b8c7d-56df-4293-928d-8368923dd413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478144220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.478144220
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.2018716844
Short name T479
Test name
Test status
Simulation time 41337875 ps
CPU time 0.64 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198100 kb
Host smart-0754f210-405e-4142-aded-30c21fdf7316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018716844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.2018716844
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2199822330
Short name T441
Test name
Test status
Simulation time 32405409 ps
CPU time 0.61 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:08 PM PDT 24
Peak memory 198456 kb
Host smart-01c7b2ca-ae3e-4168-83d0-09c3f8383130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199822330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2199822330
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.3916260942
Short name T342
Test name
Test status
Simulation time 50789487 ps
CPU time 0.74 seconds
Started Aug 02 05:15:20 PM PDT 24
Finished Aug 02 05:15:21 PM PDT 24
Peak memory 199136 kb
Host smart-539d1316-2433-40c4-82f6-7b9f69383634
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916260942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3916260942
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1585511549
Short name T213
Test name
Test status
Simulation time 102243693 ps
CPU time 0.86 seconds
Started Aug 02 05:15:15 PM PDT 24
Finished Aug 02 05:15:16 PM PDT 24
Peak memory 209508 kb
Host smart-dce14436-aa96-42ce-b8a8-124f16f07a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585511549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1585511549
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2226732941
Short name T247
Test name
Test status
Simulation time 73835684 ps
CPU time 0.91 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 199236 kb
Host smart-925db48c-71ac-4f9a-b440-8639a9ac8476
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226732941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2226732941
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.226754948
Short name T487
Test name
Test status
Simulation time 97189421 ps
CPU time 0.63 seconds
Started Aug 02 05:15:07 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 198476 kb
Host smart-b77a241a-cbb6-424b-a18b-7a9de1807e4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226754948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.226754948
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2410463174
Short name T321
Test name
Test status
Simulation time 66743142 ps
CPU time 0.9 seconds
Started Aug 02 05:15:21 PM PDT 24
Finished Aug 02 05:15:22 PM PDT 24
Peak memory 200100 kb
Host smart-aaefa6d3-beb2-4812-a136-5497aedd1e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410463174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2410463174
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.224300120
Short name T491
Test name
Test status
Simulation time 54817632 ps
CPU time 0.68 seconds
Started Aug 02 05:15:16 PM PDT 24
Finished Aug 02 05:15:17 PM PDT 24
Peak memory 198520 kb
Host smart-c54e34af-e23f-438c-8c63-d12a23769b1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224300120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.224300120
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2608314721
Short name T376
Test name
Test status
Simulation time 28831057 ps
CPU time 0.63 seconds
Started Aug 02 05:15:10 PM PDT 24
Finished Aug 02 05:15:11 PM PDT 24
Peak memory 198092 kb
Host smart-8512d171-5378-4c25-bfc9-26115dd18de8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608314721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2608314721
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.36697396
Short name T604
Test name
Test status
Simulation time 622699609 ps
CPU time 0.94 seconds
Started Aug 02 05:15:06 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 198156 kb
Host smart-399012c2-8386-4df4-8288-02ee76525051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36697396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.36697396
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3386326284
Short name T576
Test name
Test status
Simulation time 46622704 ps
CPU time 0.58 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 197432 kb
Host smart-52a5fc42-5435-4106-a579-437fb3fc9e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386326284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3386326284
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1135947761
Short name T605
Test name
Test status
Simulation time 29958319 ps
CPU time 0.59 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198392 kb
Host smart-18cbffb3-045d-414b-909f-b49aa21d7ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135947761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1135947761
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.801275898
Short name T165
Test name
Test status
Simulation time 75270413 ps
CPU time 0.63 seconds
Started Aug 02 05:15:07 PM PDT 24
Finished Aug 02 05:15:08 PM PDT 24
Peak memory 201400 kb
Host smart-9edfb432-eafa-43b1-9ba9-ff2c69a26a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801275898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid
.801275898
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.3067311564
Short name T244
Test name
Test status
Simulation time 28428892 ps
CPU time 0.66 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 199196 kb
Host smart-2861dec4-6dce-4dcf-81ee-41e8fca6e46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067311564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3067311564
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1426598751
Short name T606
Test name
Test status
Simulation time 109490184 ps
CPU time 0.92 seconds
Started Aug 02 05:15:36 PM PDT 24
Finished Aug 02 05:15:37 PM PDT 24
Peak memory 209496 kb
Host smart-f2c620cf-e3f7-4fcb-8087-a8813446ee42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426598751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1426598751
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.932007635
Short name T269
Test name
Test status
Simulation time 192737179 ps
CPU time 0.69 seconds
Started Aug 02 05:15:02 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 198112 kb
Host smart-0d3fca85-df0f-4e8e-bf32-1cfb5dfda096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932007635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.932007635
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2957076502
Short name T93
Test name
Test status
Simulation time 33228081 ps
CPU time 0.72 seconds
Started Aug 02 05:15:11 PM PDT 24
Finished Aug 02 05:15:12 PM PDT 24
Peak memory 198572 kb
Host smart-32665cbb-658b-4b17-8ab4-7cb2cea0b6a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957076502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2957076502
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.2394000422
Short name T409
Test name
Test status
Simulation time 20812521 ps
CPU time 0.63 seconds
Started Aug 02 05:15:05 PM PDT 24
Finished Aug 02 05:15:06 PM PDT 24
Peak memory 198736 kb
Host smart-4ff385e8-6e84-419b-a74d-5e5bdffa220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394000422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2394000422
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1167089288
Short name T578
Test name
Test status
Simulation time 64301449 ps
CPU time 0.75 seconds
Started Aug 02 05:15:13 PM PDT 24
Finished Aug 02 05:15:14 PM PDT 24
Peak memory 199064 kb
Host smart-bf1633c8-795b-4a1e-9e9d-b3340488d362
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167089288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1167089288
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1071306331
Short name T356
Test name
Test status
Simulation time 36661139 ps
CPU time 0.59 seconds
Started Aug 02 05:15:17 PM PDT 24
Finished Aug 02 05:15:18 PM PDT 24
Peak memory 197968 kb
Host smart-94afc93d-660c-4198-9cf9-1c50fc9c1e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071306331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1071306331
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3064263270
Short name T611
Test name
Test status
Simulation time 632001542 ps
CPU time 0.96 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198088 kb
Host smart-cdb2fec6-c694-49cf-9dc4-dce7cf548936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064263270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3064263270
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3873763095
Short name T529
Test name
Test status
Simulation time 62887733 ps
CPU time 0.59 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 197468 kb
Host smart-a1699c0b-031f-450b-8d8c-804ba08aba75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873763095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3873763095
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.2513676617
Short name T57
Test name
Test status
Simulation time 43555745 ps
CPU time 0.62 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 198144 kb
Host smart-420d9c2f-4352-4d0b-9e4d-6f55a435b0cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513676617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2513676617
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1716007832
Short name T555
Test name
Test status
Simulation time 45170729 ps
CPU time 0.72 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 201384 kb
Host smart-031d629b-110e-4129-9ee3-7bbabbad0558
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716007832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1716007832
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.2034624291
Short name T197
Test name
Test status
Simulation time 59306543 ps
CPU time 0.62 seconds
Started Aug 02 05:15:10 PM PDT 24
Finished Aug 02 05:15:10 PM PDT 24
Peak memory 199164 kb
Host smart-28943029-973d-4394-8b32-3479799702a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034624291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.2034624291
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.3859557947
Short name T621
Test name
Test status
Simulation time 80389459 ps
CPU time 0.9 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 199084 kb
Host smart-082ff9bf-a5df-4374-bd00-a2465115b9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859557947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.3859557947
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.684207300
Short name T371
Test name
Test status
Simulation time 163624553 ps
CPU time 0.77 seconds
Started Aug 02 05:15:12 PM PDT 24
Finished Aug 02 05:15:13 PM PDT 24
Peak memory 209528 kb
Host smart-d00ea67c-dfc4-4ab4-a12f-3fc3c7f2efb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684207300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.684207300
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3868692972
Short name T489
Test name
Test status
Simulation time 92150951 ps
CPU time 0.71 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 197800 kb
Host smart-316f062f-c54c-49c8-b656-b08b353cd471
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868692972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3868692972
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.488639497
Short name T361
Test name
Test status
Simulation time 41375037 ps
CPU time 0.65 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 199336 kb
Host smart-c95163f1-60e2-425f-87e2-864eedc936e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488639497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.488639497
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3442350224
Short name T121
Test name
Test status
Simulation time 85074446 ps
CPU time 0.72 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:59 PM PDT 24
Peak memory 198900 kb
Host smart-17f9f993-6ec7-4bc4-80cf-16f3e235980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442350224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3442350224
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.619773864
Short name T161
Test name
Test status
Simulation time 53344405 ps
CPU time 0.8 seconds
Started Aug 02 05:15:16 PM PDT 24
Finished Aug 02 05:15:17 PM PDT 24
Peak memory 198624 kb
Host smart-b11668aa-0f75-4daa-81a8-c6dd711a3479
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619773864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.619773864
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1684873245
Short name T395
Test name
Test status
Simulation time 36928466 ps
CPU time 0.59 seconds
Started Aug 02 05:15:13 PM PDT 24
Finished Aug 02 05:15:14 PM PDT 24
Peak memory 198064 kb
Host smart-e1adae6d-29a7-45df-a290-74e15209223b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684873245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1684873245
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.69634040
Short name T276
Test name
Test status
Simulation time 162018235 ps
CPU time 0.95 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198412 kb
Host smart-5c015db6-c584-4f29-9789-2902525281ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69634040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.69634040
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.660350152
Short name T619
Test name
Test status
Simulation time 90755878 ps
CPU time 0.6 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 198148 kb
Host smart-29462deb-3989-4705-aa68-12faf9db51a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660350152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.660350152
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2002631497
Short name T475
Test name
Test status
Simulation time 72549488 ps
CPU time 0.63 seconds
Started Aug 02 05:15:19 PM PDT 24
Finished Aug 02 05:15:20 PM PDT 24
Peak memory 198088 kb
Host smart-05169a06-70ce-4c9e-8aa2-ceafa91834ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002631497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2002631497
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.4230076231
Short name T186
Test name
Test status
Simulation time 41214094 ps
CPU time 0.73 seconds
Started Aug 02 05:15:20 PM PDT 24
Finished Aug 02 05:15:21 PM PDT 24
Peak memory 201376 kb
Host smart-e9a59571-1d5a-495c-bfbe-5ecacbeaf618
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230076231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.4230076231
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2414567000
Short name T617
Test name
Test status
Simulation time 70597837 ps
CPU time 0.65 seconds
Started Aug 02 05:15:13 PM PDT 24
Finished Aug 02 05:15:14 PM PDT 24
Peak memory 198212 kb
Host smart-1ff84f7b-e18a-4d39-8111-82be5df1f4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414567000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2414567000
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.143900886
Short name T308
Test name
Test status
Simulation time 249387260 ps
CPU time 0.77 seconds
Started Aug 02 05:15:14 PM PDT 24
Finished Aug 02 05:15:15 PM PDT 24
Peak memory 209524 kb
Host smart-c4453a14-243b-4c80-b761-a2863860b6d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143900886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.143900886
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1993549149
Short name T452
Test name
Test status
Simulation time 67679741 ps
CPU time 0.73 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:09 PM PDT 24
Peak memory 198020 kb
Host smart-5a83caa0-ce49-4de1-b321-719ab9862afc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993549149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1993549149
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.303973617
Short name T338
Test name
Test status
Simulation time 41552147 ps
CPU time 0.62 seconds
Started Aug 02 05:15:16 PM PDT 24
Finished Aug 02 05:15:17 PM PDT 24
Peak memory 198512 kb
Host smart-c76ba635-5ed8-4d8e-b4e4-27dff710bf98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303973617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.303973617
Directory /workspace/9.pwrmgr_smoke/latest
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