Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 540 1 T1 2 T2 2 T5 5
auto[1] 428 1 T5 10 T9 5 T50 2


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 541 1 T1 2 T2 2 T5 9
auto[1] 427 1 T5 6 T9 3 T50 3


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 431 1 T5 9 T9 4 T50 3
auto[1] 537 1 T1 2 T2 2 T5 6


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 772 1 T1 1 T2 1 T5 15
auto[1] 196 1 T1 1 T2 1 T6 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 416 1 T5 5 T9 3 T50 2
auto[1] 552 1 T1 2 T2 2 T5 10


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 543 1 T1 2 T2 2 T5 9
auto[1] 425 1 T5 6 T9 6 T50 3


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 19 1 T29 1 T163 1 T58 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 2 1 T163 1 T164 1 - -
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 15 1 T5 1 T58 1 T164 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 4 1 T165 1 T166 1 T143 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 19 1 T50 1 T51 1 T16 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 4 1 T167 1 T168 1 T166 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 74 1 T1 1 T2 1 T6 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 54 1 T1 1 T2 1 T6 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 35 1 T5 1 T58 1 T87 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 3 1 T169 1 T143 1 T170 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 22 1 T87 1 T90 1 T28 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T90 1 T28 1 T171 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 19 1 T9 1 T16 1 T87 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 7 1 T172 1 T27 1 T173 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 23 1 T14 1 T55 1 T174 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 5 1 T55 1 T175 1 T176 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 21 1 T5 1 T58 1 T174 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 4 1 T174 1 T177 1 T56 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 20 1 T5 1 T16 1 T55 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 7 1 T178 1 T179 2 T180 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 34 1 T5 1 T49 1 T16 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 9 1 T86 1 T90 1 T181 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 29 1 T55 1 T52 1 T58 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 4 1 T52 1 T141 2 T182 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 12 1 T87 1 T97 1 T98 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 3 1 T183 1 T184 1 T185 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 20 1 T50 1 T86 1 T88 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 4 1 T50 1 T186 1 T187 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 25 1 T16 2 T188 1 T87 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T188 1 T186 1 T189 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 27 1 T50 1 T51 1 T16 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 7 1 T55 1 T190 1 T168 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 24 1 T16 2 T29 1 T188 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 6 1 T188 1 T191 2 T192 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 29 1 T51 1 T16 1 T90 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 5 1 T51 1 T142 2 T193 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 22 1 T5 2 T50 1 T90 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 5 1 T50 1 T194 1 T195 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 28 1 T5 1 T16 2 T29 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 8 1 T164 1 T144 1 T187 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 23 1 T117 2 T96 1 T196 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 4 1 T192 1 T197 1 T198 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 20 1 T9 1 T29 1 T86 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 5 1 T9 1 T178 1 T175 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 25 1 T5 3 T49 1 T16 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 1 1 T199 1 - - - -
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 22 1 T5 1 T16 1 T200 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 4 1 T190 1 T143 1 T201 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 23 1 T174 1 T164 1 T196 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 3 1 T174 1 T202 1 T203 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 16 1 T5 1 T117 1 T173 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 3 1 T173 1 T165 1 T201 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 24 1 T5 1 T49 1 T51 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 5 1 T49 1 T51 1 T204 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 17 1 T58 1 T188 1 T172 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 6 1 T172 1 T181 1 T53 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 21 1 T9 1 T49 1 T29 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 4 1 T49 1 T205 1 T206 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 30 1 T16 1 T29 1 T58 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 4 1 T194 1 T54 1 T207 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 17 1 T9 1 T204 1 T172 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T9 1 T204 1 T28 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 17 1 T5 1 T52 1 T86 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 3 1 T52 1 T86 1 T183 1

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