Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 98.23 96.15 99.44 96.00 96.18 100.00 96.24


Total test records in report: 747
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T561 /workspace/coverage/default/27.pwrmgr_global_esc.991952025 Aug 03 05:00:00 PM PDT 24 Aug 03 05:00:01 PM PDT 24 65641167 ps
T562 /workspace/coverage/default/12.pwrmgr_smoke.1568601303 Aug 03 04:59:17 PM PDT 24 Aug 03 04:59:18 PM PDT 24 55652908 ps
T563 /workspace/coverage/default/15.pwrmgr_global_esc.2728842141 Aug 03 04:59:32 PM PDT 24 Aug 03 04:59:33 PM PDT 24 80069531 ps
T564 /workspace/coverage/default/14.pwrmgr_aborted_low_power.1231346605 Aug 03 04:59:24 PM PDT 24 Aug 03 04:59:25 PM PDT 24 28260575 ps
T33 /workspace/coverage/default/2.pwrmgr_sec_cm.2903305796 Aug 03 04:58:41 PM PDT 24 Aug 03 04:58:43 PM PDT 24 740144954 ps
T565 /workspace/coverage/default/29.pwrmgr_escalation_timeout.3873593992 Aug 03 05:00:07 PM PDT 24 Aug 03 05:00:09 PM PDT 24 632119324 ps
T566 /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.141225876 Aug 03 04:59:22 PM PDT 24 Aug 03 04:59:23 PM PDT 24 119241709 ps
T567 /workspace/coverage/default/29.pwrmgr_reset.3270600638 Aug 03 05:00:05 PM PDT 24 Aug 03 05:00:06 PM PDT 24 53081974 ps
T568 /workspace/coverage/default/48.pwrmgr_reset.4018402814 Aug 03 05:00:48 PM PDT 24 Aug 03 05:00:49 PM PDT 24 93377886 ps
T569 /workspace/coverage/default/11.pwrmgr_global_esc.602935179 Aug 03 04:59:18 PM PDT 24 Aug 03 04:59:18 PM PDT 24 39053463 ps
T570 /workspace/coverage/default/13.pwrmgr_reset_invalid.2614263511 Aug 03 04:59:22 PM PDT 24 Aug 03 04:59:23 PM PDT 24 130014173 ps
T571 /workspace/coverage/default/12.pwrmgr_escalation_timeout.3021589507 Aug 03 04:59:18 PM PDT 24 Aug 03 04:59:19 PM PDT 24 2509598221 ps
T572 /workspace/coverage/default/12.pwrmgr_reset_invalid.3081016053 Aug 03 04:59:19 PM PDT 24 Aug 03 04:59:20 PM PDT 24 89200952 ps
T573 /workspace/coverage/default/36.pwrmgr_escalation_timeout.244424594 Aug 03 05:00:31 PM PDT 24 Aug 03 05:00:32 PM PDT 24 165771603 ps
T185 /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2469841437 Aug 03 04:59:24 PM PDT 24 Aug 03 04:59:25 PM PDT 24 42596408 ps
T574 /workspace/coverage/default/32.pwrmgr_glitch.2498001623 Aug 03 05:00:24 PM PDT 24 Aug 03 05:00:25 PM PDT 24 31895870 ps
T575 /workspace/coverage/default/42.pwrmgr_escalation_timeout.2432382826 Aug 03 05:00:49 PM PDT 24 Aug 03 05:00:50 PM PDT 24 786300194 ps
T576 /workspace/coverage/default/21.pwrmgr_reset_invalid.1969017636 Aug 03 04:59:46 PM PDT 24 Aug 03 04:59:47 PM PDT 24 142676443 ps
T577 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3595703468 Aug 03 05:00:35 PM PDT 24 Aug 03 05:00:36 PM PDT 24 39002518 ps
T578 /workspace/coverage/default/38.pwrmgr_glitch.129942947 Aug 03 05:00:47 PM PDT 24 Aug 03 05:00:48 PM PDT 24 48548368 ps
T579 /workspace/coverage/default/32.pwrmgr_escalation_timeout.1890426721 Aug 03 05:00:14 PM PDT 24 Aug 03 05:00:15 PM PDT 24 312995356 ps
T580 /workspace/coverage/default/43.pwrmgr_reset.898919361 Aug 03 05:00:34 PM PDT 24 Aug 03 05:00:35 PM PDT 24 63247085 ps
T581 /workspace/coverage/default/9.pwrmgr_reset.116289524 Aug 03 04:59:16 PM PDT 24 Aug 03 04:59:17 PM PDT 24 84381147 ps
T582 /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1680458002 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:04 PM PDT 24 66163448 ps
T583 /workspace/coverage/default/35.pwrmgr_glitch.3742815804 Aug 03 05:00:18 PM PDT 24 Aug 03 05:00:19 PM PDT 24 67827997 ps
T584 /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1188063771 Aug 03 04:59:21 PM PDT 24 Aug 03 04:59:22 PM PDT 24 33730001 ps
T585 /workspace/coverage/default/45.pwrmgr_reset.2945457336 Aug 03 05:00:45 PM PDT 24 Aug 03 05:00:46 PM PDT 24 55732141 ps
T586 /workspace/coverage/default/37.pwrmgr_global_esc.3968387492 Aug 03 05:00:42 PM PDT 24 Aug 03 05:00:43 PM PDT 24 41733268 ps
T587 /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.4072779877 Aug 03 05:00:30 PM PDT 24 Aug 03 05:00:31 PM PDT 24 40241097 ps
T588 /workspace/coverage/default/41.pwrmgr_reset.4085466087 Aug 03 05:00:31 PM PDT 24 Aug 03 05:00:32 PM PDT 24 47171828 ps
T589 /workspace/coverage/default/45.pwrmgr_reset_invalid.3309543017 Aug 03 05:00:52 PM PDT 24 Aug 03 05:00:53 PM PDT 24 107790890 ps
T590 /workspace/coverage/default/4.pwrmgr_aborted_low_power.2381215080 Aug 03 04:58:54 PM PDT 24 Aug 03 04:58:55 PM PDT 24 22002589 ps
T591 /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3450042457 Aug 03 05:00:10 PM PDT 24 Aug 03 05:00:11 PM PDT 24 60983072 ps
T592 /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2455090071 Aug 03 04:59:46 PM PDT 24 Aug 03 04:59:47 PM PDT 24 62614644 ps
T593 /workspace/coverage/default/13.pwrmgr_escalation_timeout.291453584 Aug 03 04:59:28 PM PDT 24 Aug 03 04:59:29 PM PDT 24 611407110 ps
T57 /workspace/coverage/default/32.pwrmgr_wakeup_reset.1325442487 Aug 03 05:00:21 PM PDT 24 Aug 03 05:00:22 PM PDT 24 62394056 ps
T594 /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2906247496 Aug 03 04:58:28 PM PDT 24 Aug 03 04:58:29 PM PDT 24 51725381 ps
T595 /workspace/coverage/default/27.pwrmgr_reset.3057667545 Aug 03 04:59:57 PM PDT 24 Aug 03 05:00:06 PM PDT 24 75516242 ps
T596 /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3496556355 Aug 03 04:58:53 PM PDT 24 Aug 03 04:58:54 PM PDT 24 51925013 ps
T597 /workspace/coverage/default/43.pwrmgr_escalation_timeout.3794838968 Aug 03 05:00:38 PM PDT 24 Aug 03 05:00:39 PM PDT 24 751882643 ps
T598 /workspace/coverage/default/27.pwrmgr_glitch.1077437709 Aug 03 05:00:15 PM PDT 24 Aug 03 05:00:16 PM PDT 24 35027395 ps
T599 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2052586619 Aug 03 05:00:19 PM PDT 24 Aug 03 05:00:20 PM PDT 24 105384096 ps
T600 /workspace/coverage/default/19.pwrmgr_glitch.1626036750 Aug 03 04:59:41 PM PDT 24 Aug 03 04:59:42 PM PDT 24 46178417 ps
T601 /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3010341975 Aug 03 04:59:47 PM PDT 24 Aug 03 04:59:48 PM PDT 24 29383325 ps
T602 /workspace/coverage/default/18.pwrmgr_glitch.2079867024 Aug 03 04:59:40 PM PDT 24 Aug 03 04:59:41 PM PDT 24 56111159 ps
T213 /workspace/coverage/default/15.pwrmgr_wakeup.1234302459 Aug 03 04:59:30 PM PDT 24 Aug 03 04:59:31 PM PDT 24 60737311 ps
T603 /workspace/coverage/default/8.pwrmgr_smoke.3245551000 Aug 03 04:59:05 PM PDT 24 Aug 03 04:59:06 PM PDT 24 27958534 ps
T34 /workspace/coverage/default/3.pwrmgr_sec_cm.3481120872 Aug 03 04:58:46 PM PDT 24 Aug 03 04:58:48 PM PDT 24 688915003 ps
T604 /workspace/coverage/default/20.pwrmgr_escalation_timeout.2370508371 Aug 03 04:59:47 PM PDT 24 Aug 03 04:59:48 PM PDT 24 684947512 ps
T605 /workspace/coverage/default/7.pwrmgr_escalation_timeout.2658782039 Aug 03 04:59:04 PM PDT 24 Aug 03 04:59:05 PM PDT 24 310658262 ps
T606 /workspace/coverage/default/16.pwrmgr_aborted_low_power.1954674644 Aug 03 04:59:32 PM PDT 24 Aug 03 04:59:33 PM PDT 24 57416642 ps
T607 /workspace/coverage/default/24.pwrmgr_reset_invalid.4292239031 Aug 03 04:59:54 PM PDT 24 Aug 03 04:59:55 PM PDT 24 116456745 ps
T608 /workspace/coverage/default/17.pwrmgr_reset_invalid.2143709333 Aug 03 04:59:36 PM PDT 24 Aug 03 04:59:37 PM PDT 24 125474129 ps
T609 /workspace/coverage/default/33.pwrmgr_smoke.2121587543 Aug 03 05:00:18 PM PDT 24 Aug 03 05:00:18 PM PDT 24 30490558 ps
T610 /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1768691577 Aug 03 05:00:59 PM PDT 24 Aug 03 05:01:00 PM PDT 24 147031155 ps
T203 /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2046865576 Aug 03 04:59:18 PM PDT 24 Aug 03 04:59:19 PM PDT 24 64459078 ps
T611 /workspace/coverage/default/1.pwrmgr_reset.2162512241 Aug 03 04:58:26 PM PDT 24 Aug 03 04:58:27 PM PDT 24 36341462 ps
T612 /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3433471821 Aug 03 05:00:23 PM PDT 24 Aug 03 05:00:24 PM PDT 24 50277940 ps
T613 /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3138684878 Aug 03 04:59:39 PM PDT 24 Aug 03 04:59:39 PM PDT 24 59548729 ps
T614 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3220276683 Aug 03 04:59:18 PM PDT 24 Aug 03 04:59:18 PM PDT 24 38550039 ps
T615 /workspace/coverage/default/5.pwrmgr_smoke.533266479 Aug 03 04:58:54 PM PDT 24 Aug 03 04:58:54 PM PDT 24 31461371 ps
T616 /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2611058467 Aug 03 04:59:06 PM PDT 24 Aug 03 04:59:07 PM PDT 24 30896953 ps
T617 /workspace/coverage/default/21.pwrmgr_global_esc.2632143209 Aug 03 04:59:49 PM PDT 24 Aug 03 04:59:49 PM PDT 24 40602329 ps
T618 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3850057631 Aug 03 04:59:49 PM PDT 24 Aug 03 04:59:49 PM PDT 24 87734183 ps
T619 /workspace/coverage/default/14.pwrmgr_escalation_timeout.3174769122 Aug 03 04:59:24 PM PDT 24 Aug 03 04:59:25 PM PDT 24 623713077 ps
T620 /workspace/coverage/default/45.pwrmgr_glitch.10237378 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:13 PM PDT 24 56424481 ps
T621 /workspace/coverage/default/21.pwrmgr_aborted_low_power.2951970763 Aug 03 04:59:42 PM PDT 24 Aug 03 04:59:43 PM PDT 24 25230794 ps
T622 /workspace/coverage/default/16.pwrmgr_escalation_timeout.3094590774 Aug 03 04:59:33 PM PDT 24 Aug 03 04:59:34 PM PDT 24 630022134 ps
T623 /workspace/coverage/default/33.pwrmgr_global_esc.1329562676 Aug 03 05:00:21 PM PDT 24 Aug 03 05:00:22 PM PDT 24 35414767 ps
T624 /workspace/coverage/default/7.pwrmgr_glitch.3641918171 Aug 03 04:59:05 PM PDT 24 Aug 03 04:59:06 PM PDT 24 75172895 ps
T625 /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.181905011 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:04 PM PDT 24 71198744 ps
T626 /workspace/coverage/default/42.pwrmgr_smoke.239885088 Aug 03 05:00:36 PM PDT 24 Aug 03 05:00:37 PM PDT 24 35912997 ps
T627 /workspace/coverage/default/2.pwrmgr_reset.408553678 Aug 03 04:58:32 PM PDT 24 Aug 03 04:58:33 PM PDT 24 40242765 ps
T628 /workspace/coverage/default/44.pwrmgr_aborted_low_power.2929221499 Aug 03 05:00:53 PM PDT 24 Aug 03 05:00:54 PM PDT 24 50909090 ps
T629 /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.345362139 Aug 03 04:59:51 PM PDT 24 Aug 03 04:59:52 PM PDT 24 31041477 ps
T630 /workspace/coverage/default/32.pwrmgr_reset.571357319 Aug 03 05:00:22 PM PDT 24 Aug 03 05:00:23 PM PDT 24 70661064 ps
T631 /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1273622829 Aug 03 04:59:37 PM PDT 24 Aug 03 04:59:38 PM PDT 24 102732485 ps
T632 /workspace/coverage/default/4.pwrmgr_reset_invalid.3418968438 Aug 03 04:58:53 PM PDT 24 Aug 03 04:58:55 PM PDT 24 108791618 ps
T633 /workspace/coverage/default/18.pwrmgr_global_esc.1770817108 Aug 03 04:59:46 PM PDT 24 Aug 03 04:59:47 PM PDT 24 36314917 ps
T634 /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2238702138 Aug 03 04:59:51 PM PDT 24 Aug 03 04:59:52 PM PDT 24 61418273 ps
T635 /workspace/coverage/default/24.pwrmgr_glitch.503062030 Aug 03 04:59:58 PM PDT 24 Aug 03 04:59:58 PM PDT 24 87951840 ps
T636 /workspace/coverage/default/6.pwrmgr_aborted_low_power.3902230053 Aug 03 04:58:58 PM PDT 24 Aug 03 04:58:59 PM PDT 24 41632454 ps
T23 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2716802807 Aug 03 04:24:25 PM PDT 24 Aug 03 04:24:26 PM PDT 24 103804971 ps
T70 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2889723118 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:23 PM PDT 24 20458794 ps
T63 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2870925059 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:39 PM PDT 24 60347893 ps
T71 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.895556496 Aug 03 04:24:47 PM PDT 24 Aug 03 04:24:48 PM PDT 24 18868132 ps
T64 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1763368742 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:58 PM PDT 24 26989034 ps
T65 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2617734098 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:23 PM PDT 24 40778809 ps
T24 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3447374787 Aug 03 04:24:33 PM PDT 24 Aug 03 04:24:36 PM PDT 24 492470986 ps
T72 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4146119152 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:53 PM PDT 24 21455704 ps
T25 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.253498259 Aug 03 04:24:36 PM PDT 24 Aug 03 04:24:37 PM PDT 24 241661204 ps
T76 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.548317891 Aug 03 04:24:39 PM PDT 24 Aug 03 04:24:40 PM PDT 24 37882965 ps
T62 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3178085777 Aug 03 04:25:02 PM PDT 24 Aug 03 04:25:04 PM PDT 24 281799070 ps
T148 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.4224326003 Aug 03 04:24:47 PM PDT 24 Aug 03 04:24:48 PM PDT 24 24270760 ps
T60 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1132889683 Aug 03 04:24:58 PM PDT 24 Aug 03 04:25:00 PM PDT 24 138170279 ps
T107 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1852836407 Aug 03 04:24:26 PM PDT 24 Aug 03 04:24:28 PM PDT 24 161381120 ps
T61 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2347146227 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:40 PM PDT 24 64182054 ps
T99 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.800832393 Aug 03 04:24:56 PM PDT 24 Aug 03 04:24:57 PM PDT 24 95024475 ps
T100 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.326717360 Aug 03 04:24:28 PM PDT 24 Aug 03 04:24:28 PM PDT 24 33625441 ps
T91 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3134663872 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:59 PM PDT 24 114434848 ps
T149 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2258411812 Aug 03 04:24:37 PM PDT 24 Aug 03 04:24:38 PM PDT 24 45714399 ps
T637 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.267893832 Aug 03 04:25:06 PM PDT 24 Aug 03 04:25:06 PM PDT 24 49965755 ps
T69 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3447164294 Aug 03 04:24:43 PM PDT 24 Aug 03 04:24:44 PM PDT 24 71816137 ps
T123 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3745057586 Aug 03 04:24:24 PM PDT 24 Aug 03 04:24:24 PM PDT 24 22499633 ps
T111 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.832895396 Aug 03 04:25:13 PM PDT 24 Aug 03 04:25:14 PM PDT 24 40431161 ps
T150 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1181621256 Aug 03 04:24:44 PM PDT 24 Aug 03 04:24:45 PM PDT 24 51505238 ps
T151 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1742989467 Aug 03 04:24:26 PM PDT 24 Aug 03 04:24:26 PM PDT 24 43661792 ps
T638 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1664995362 Aug 03 04:24:58 PM PDT 24 Aug 03 04:24:59 PM PDT 24 57061988 ps
T73 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1673959415 Aug 03 04:24:59 PM PDT 24 Aug 03 04:25:00 PM PDT 24 109063482 ps
T639 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2567951868 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:24 PM PDT 24 449519174 ps
T101 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2940729121 Aug 03 04:24:48 PM PDT 24 Aug 03 04:24:49 PM PDT 24 20350110 ps
T92 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3954258292 Aug 03 04:24:21 PM PDT 24 Aug 03 04:24:22 PM PDT 24 58022563 ps
T640 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3494162572 Aug 03 04:25:10 PM PDT 24 Aug 03 04:25:11 PM PDT 24 40343005 ps
T67 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2960808229 Aug 03 04:24:55 PM PDT 24 Aug 03 04:24:57 PM PDT 24 503758054 ps
T641 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2232310683 Aug 03 04:24:37 PM PDT 24 Aug 03 04:24:37 PM PDT 24 43562686 ps
T642 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1103358471 Aug 03 04:24:54 PM PDT 24 Aug 03 04:24:55 PM PDT 24 18101547 ps
T643 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3624781357 Aug 03 04:25:07 PM PDT 24 Aug 03 04:25:08 PM PDT 24 81392604 ps
T93 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3794785803 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:47 PM PDT 24 58355524 ps
T644 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.563665588 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:38 PM PDT 24 49025820 ps
T645 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3568757317 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:38 PM PDT 24 23691668 ps
T78 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1778067539 Aug 03 04:25:03 PM PDT 24 Aug 03 04:25:05 PM PDT 24 51951227 ps
T646 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.674156915 Aug 03 04:24:36 PM PDT 24 Aug 03 04:24:36 PM PDT 24 20644080 ps
T647 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2458127524 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:53 PM PDT 24 51954678 ps
T648 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3522709739 Aug 03 04:25:06 PM PDT 24 Aug 03 04:25:07 PM PDT 24 74875948 ps
T68 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2342368506 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:49 PM PDT 24 251367194 ps
T121 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3505879579 Aug 03 04:24:43 PM PDT 24 Aug 03 04:24:44 PM PDT 24 54870519 ps
T649 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2661990282 Aug 03 04:24:41 PM PDT 24 Aug 03 04:24:42 PM PDT 24 52060511 ps
T650 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1348018389 Aug 03 04:24:40 PM PDT 24 Aug 03 04:24:41 PM PDT 24 51414134 ps
T651 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.851961857 Aug 03 04:24:54 PM PDT 24 Aug 03 04:24:57 PM PDT 24 862255100 ps
T102 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2678788052 Aug 03 04:24:51 PM PDT 24 Aug 03 04:24:52 PM PDT 24 18734165 ps
T122 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.597868437 Aug 03 04:24:34 PM PDT 24 Aug 03 04:24:35 PM PDT 24 284507852 ps
T74 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1837827700 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:24 PM PDT 24 192513043 ps
T652 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3637446111 Aug 03 04:24:43 PM PDT 24 Aug 03 04:24:44 PM PDT 24 31555583 ps
T77 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1218844777 Aug 03 04:24:20 PM PDT 24 Aug 03 04:24:22 PM PDT 24 359973835 ps
T103 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1630158956 Aug 03 04:24:24 PM PDT 24 Aug 03 04:24:25 PM PDT 24 104918527 ps
T653 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1056030356 Aug 03 04:24:54 PM PDT 24 Aug 03 04:24:55 PM PDT 24 16653620 ps
T145 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3558276544 Aug 03 04:24:43 PM PDT 24 Aug 03 04:24:45 PM PDT 24 339247203 ps
T146 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2041964705 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:54 PM PDT 24 123616617 ps
T654 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2758559430 Aug 03 04:24:36 PM PDT 24 Aug 03 04:24:39 PM PDT 24 72221963 ps
T112 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1049732017 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:23 PM PDT 24 136290545 ps
T655 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3223523401 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:57 PM PDT 24 20643452 ps
T113 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1781535905 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:46 PM PDT 24 90713357 ps
T656 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2724955054 Aug 03 04:24:58 PM PDT 24 Aug 03 04:24:59 PM PDT 24 33238057 ps
T657 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1891748739 Aug 03 04:25:10 PM PDT 24 Aug 03 04:25:11 PM PDT 24 41523801 ps
T658 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3712543600 Aug 03 04:24:40 PM PDT 24 Aug 03 04:24:41 PM PDT 24 56262846 ps
T114 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1389548340 Aug 03 04:24:41 PM PDT 24 Aug 03 04:24:41 PM PDT 24 27680172 ps
T659 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3195380546 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:39 PM PDT 24 45086493 ps
T660 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1785261022 Aug 03 04:24:33 PM PDT 24 Aug 03 04:24:35 PM PDT 24 97188882 ps
T661 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1198160846 Aug 03 04:24:21 PM PDT 24 Aug 03 04:24:27 PM PDT 24 49323134 ps
T662 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.882311691 Aug 03 04:24:36 PM PDT 24 Aug 03 04:24:37 PM PDT 24 61719350 ps
T147 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3952037059 Aug 03 04:24:24 PM PDT 24 Aug 03 04:24:26 PM PDT 24 292611191 ps
T663 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2314175946 Aug 03 04:24:48 PM PDT 24 Aug 03 04:24:49 PM PDT 24 17915414 ps
T664 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1245250820 Aug 03 04:24:37 PM PDT 24 Aug 03 04:24:38 PM PDT 24 202017976 ps
T665 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2734679211 Aug 03 04:24:35 PM PDT 24 Aug 03 04:24:36 PM PDT 24 19370681 ps
T666 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3261410276 Aug 03 04:24:42 PM PDT 24 Aug 03 04:24:43 PM PDT 24 61590028 ps
T667 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2197124604 Aug 03 04:25:05 PM PDT 24 Aug 03 04:25:05 PM PDT 24 46176923 ps
T668 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1067191401 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:23 PM PDT 24 26425894 ps
T79 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3539117661 Aug 03 04:24:24 PM PDT 24 Aug 03 04:24:26 PM PDT 24 414058681 ps
T669 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2549040727 Aug 03 04:24:24 PM PDT 24 Aug 03 04:24:25 PM PDT 24 61466180 ps
T670 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3743227779 Aug 03 04:25:13 PM PDT 24 Aug 03 04:25:23 PM PDT 24 24555493 ps
T671 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3498705202 Aug 03 04:24:23 PM PDT 24 Aug 03 04:24:24 PM PDT 24 50040008 ps
T672 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.672296108 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:39 PM PDT 24 23211678 ps
T673 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.911983504 Aug 03 04:24:55 PM PDT 24 Aug 03 04:24:57 PM PDT 24 427686646 ps
T674 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3650092044 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:52 PM PDT 24 32878076 ps
T675 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3748030711 Aug 03 04:24:51 PM PDT 24 Aug 03 04:24:52 PM PDT 24 46818355 ps
T676 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3845729521 Aug 03 04:24:35 PM PDT 24 Aug 03 04:24:36 PM PDT 24 409212425 ps
T677 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2620640467 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:59 PM PDT 24 291807116 ps
T678 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.970995411 Aug 03 04:24:56 PM PDT 24 Aug 03 04:24:59 PM PDT 24 109940612 ps
T115 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.665127956 Aug 03 04:25:02 PM PDT 24 Aug 03 04:25:03 PM PDT 24 29289000 ps
T679 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2937848923 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:57 PM PDT 24 25251598 ps
T680 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3488432102 Aug 03 04:24:41 PM PDT 24 Aug 03 04:24:42 PM PDT 24 315738755 ps
T104 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2895701 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:50 PM PDT 24 46618498 ps
T681 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1313644389 Aug 03 04:24:47 PM PDT 24 Aug 03 04:24:48 PM PDT 24 37449404 ps
T116 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.459632201 Aug 03 04:25:02 PM PDT 24 Aug 03 04:25:03 PM PDT 24 128230534 ps
T682 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.77876314 Aug 03 04:25:03 PM PDT 24 Aug 03 04:25:04 PM PDT 24 33999240 ps
T683 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.521032890 Aug 03 04:24:37 PM PDT 24 Aug 03 04:24:37 PM PDT 24 37868737 ps
T684 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.675440920 Aug 03 04:24:59 PM PDT 24 Aug 03 04:24:59 PM PDT 24 19186585 ps
T105 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2366400176 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:45 PM PDT 24 70369413 ps
T685 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3834982366 Aug 03 04:25:15 PM PDT 24 Aug 03 04:25:17 PM PDT 24 45798481 ps
T686 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3422986679 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:39 PM PDT 24 273209954 ps
T687 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1783433070 Aug 03 04:25:10 PM PDT 24 Aug 03 04:25:11 PM PDT 24 109429808 ps
T688 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.526728987 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:57 PM PDT 24 50853146 ps
T106 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1481180594 Aug 03 04:24:46 PM PDT 24 Aug 03 04:24:47 PM PDT 24 16670970 ps
T689 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2902354850 Aug 03 04:24:35 PM PDT 24 Aug 03 04:24:36 PM PDT 24 126969652 ps
T690 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.676123191 Aug 03 04:24:51 PM PDT 24 Aug 03 04:24:53 PM PDT 24 617336966 ps
T691 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4091365082 Aug 03 04:25:05 PM PDT 24 Aug 03 04:25:05 PM PDT 24 47777802 ps
T692 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2505112732 Aug 03 04:24:17 PM PDT 24 Aug 03 04:24:18 PM PDT 24 127150221 ps
T693 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3707988792 Aug 03 04:24:25 PM PDT 24 Aug 03 04:24:26 PM PDT 24 51036577 ps
T694 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1673121472 Aug 03 04:24:36 PM PDT 24 Aug 03 04:24:37 PM PDT 24 69885297 ps
T695 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3933849763 Aug 03 04:24:22 PM PDT 24 Aug 03 04:24:23 PM PDT 24 67598134 ps
T696 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2798582263 Aug 03 04:24:50 PM PDT 24 Aug 03 04:24:51 PM PDT 24 18291313 ps
T697 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.4057530875 Aug 03 04:25:10 PM PDT 24 Aug 03 04:25:11 PM PDT 24 22571714 ps
T698 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4066671049 Aug 03 04:24:44 PM PDT 24 Aug 03 04:24:44 PM PDT 24 17797911 ps
T699 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1085805545 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:46 PM PDT 24 92515267 ps
T700 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2147735178 Aug 03 04:24:51 PM PDT 24 Aug 03 04:24:52 PM PDT 24 229232570 ps
T701 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1021223951 Aug 03 04:24:56 PM PDT 24 Aug 03 04:24:56 PM PDT 24 18190666 ps
T702 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2461210832 Aug 03 04:25:00 PM PDT 24 Aug 03 04:25:01 PM PDT 24 124339310 ps
T703 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4019637977 Aug 03 04:24:54 PM PDT 24 Aug 03 04:24:54 PM PDT 24 83449502 ps
T80 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3094749571 Aug 03 04:24:31 PM PDT 24 Aug 03 04:24:32 PM PDT 24 671239062 ps
T704 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2046892888 Aug 03 04:24:46 PM PDT 24 Aug 03 04:24:47 PM PDT 24 140621846 ps
T108 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3686563157 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:53 PM PDT 24 25079346 ps
T109 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2058268438 Aug 03 04:24:25 PM PDT 24 Aug 03 04:24:26 PM PDT 24 150116272 ps
T705 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2236965186 Aug 03 04:24:32 PM PDT 24 Aug 03 04:24:33 PM PDT 24 73189679 ps
T706 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.154858088 Aug 03 04:24:43 PM PDT 24 Aug 03 04:24:44 PM PDT 24 819007515 ps
T707 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2040267198 Aug 03 04:24:42 PM PDT 24 Aug 03 04:24:43 PM PDT 24 39684289 ps
T708 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2977615668 Aug 03 04:24:26 PM PDT 24 Aug 03 04:24:27 PM PDT 24 285935700 ps
T709 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3105874762 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:51 PM PDT 24 529209256 ps
T710 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1781262364 Aug 03 04:25:00 PM PDT 24 Aug 03 04:25:01 PM PDT 24 25541337 ps
T711 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3648194386 Aug 03 04:24:21 PM PDT 24 Aug 03 04:24:22 PM PDT 24 54286379 ps
T712 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2899513445 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:50 PM PDT 24 66228125 ps
T713 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2333855853 Aug 03 04:24:44 PM PDT 24 Aug 03 04:24:45 PM PDT 24 21588294 ps
T714 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.871906933 Aug 03 04:25:02 PM PDT 24 Aug 03 04:25:03 PM PDT 24 37950840 ps
T715 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.294355980 Aug 03 04:24:26 PM PDT 24 Aug 03 04:24:27 PM PDT 24 102976103 ps
T716 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3229538260 Aug 03 04:25:13 PM PDT 24 Aug 03 04:25:14 PM PDT 24 45233161 ps
T717 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2817486024 Aug 03 04:24:46 PM PDT 24 Aug 03 04:24:47 PM PDT 24 99649419 ps
T718 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.771409820 Aug 03 04:24:57 PM PDT 24 Aug 03 04:24:57 PM PDT 24 19426547 ps
T719 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2345323483 Aug 03 04:24:53 PM PDT 24 Aug 03 04:24:53 PM PDT 24 22659700 ps
T720 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2240720118 Aug 03 04:25:03 PM PDT 24 Aug 03 04:25:04 PM PDT 24 30020656 ps
T721 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2121633947 Aug 03 04:24:23 PM PDT 24 Aug 03 04:24:25 PM PDT 24 173688441 ps
T722 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2695245431 Aug 03 04:24:50 PM PDT 24 Aug 03 04:24:51 PM PDT 24 42609151 ps
T723 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1959674567 Aug 03 04:24:41 PM PDT 24 Aug 03 04:24:42 PM PDT 24 112166962 ps
T724 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3387992287 Aug 03 04:24:40 PM PDT 24 Aug 03 04:24:41 PM PDT 24 128252989 ps
T725 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3992335370 Aug 03 04:24:58 PM PDT 24 Aug 03 04:24:59 PM PDT 24 18022409 ps
T726 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2973025755 Aug 03 04:24:39 PM PDT 24 Aug 03 04:24:41 PM PDT 24 78875558 ps
T75 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3514469581 Aug 03 04:24:25 PM PDT 24 Aug 03 04:24:27 PM PDT 24 197325406 ps
T727 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3825138511 Aug 03 04:24:53 PM PDT 24 Aug 03 04:24:53 PM PDT 24 58723041 ps
T728 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.755777649 Aug 03 04:24:20 PM PDT 24 Aug 03 04:24:21 PM PDT 24 44217069 ps
T729 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.850083029 Aug 03 04:24:52 PM PDT 24 Aug 03 04:24:54 PM PDT 24 59135892 ps
T730 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2160713181 Aug 03 04:24:56 PM PDT 24 Aug 03 04:24:59 PM PDT 24 242960804 ps
T731 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.4055974388 Aug 03 04:24:46 PM PDT 24 Aug 03 04:24:48 PM PDT 24 88494976 ps
T732 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3480192502 Aug 03 04:25:04 PM PDT 24 Aug 03 04:25:04 PM PDT 24 38356447 ps
T733 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1328065461 Aug 03 04:24:48 PM PDT 24 Aug 03 04:24:48 PM PDT 24 37404387 ps
T734 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.375630435 Aug 03 04:24:19 PM PDT 24 Aug 03 04:24:20 PM PDT 24 47852951 ps
T735 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3525422268 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:50 PM PDT 24 44682774 ps
T736 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4263285334 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:46 PM PDT 24 23551550 ps
T737 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2306040122 Aug 03 04:25:00 PM PDT 24 Aug 03 04:25:00 PM PDT 24 64612138 ps
T738 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3161689421 Aug 03 04:25:14 PM PDT 24 Aug 03 04:25:14 PM PDT 24 16596305 ps
T739 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.877329218 Aug 03 04:24:58 PM PDT 24 Aug 03 04:24:59 PM PDT 24 275599772 ps
T740 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.894782391 Aug 03 04:24:47 PM PDT 24 Aug 03 04:24:47 PM PDT 24 101872466 ps
T110 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.4132981438 Aug 03 04:24:59 PM PDT 24 Aug 03 04:24:59 PM PDT 24 16648706 ps
T741 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1386925407 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:46 PM PDT 24 62622446 ps
T742 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.898294759 Aug 03 04:25:08 PM PDT 24 Aug 03 04:25:10 PM PDT 24 419024811 ps
T743 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.838834705 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:51 PM PDT 24 82698911 ps
T744 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.387816537 Aug 03 04:24:45 PM PDT 24 Aug 03 04:24:46 PM PDT 24 22295090 ps
T745 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1358451801 Aug 03 04:24:49 PM PDT 24 Aug 03 04:24:50 PM PDT 24 29841483 ps
T746 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1696247795 Aug 03 04:24:51 PM PDT 24 Aug 03 04:24:52 PM PDT 24 17068949 ps
T747 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2056250122 Aug 03 04:25:05 PM PDT 24 Aug 03 04:25:06 PM PDT 24 43217163 ps

Test location /workspace/coverage/default/0.pwrmgr_smoke.523004260
Short name T6
Test name
Test status
Simulation time 43569634 ps
CPU time 0.63 seconds
Started Aug 03 04:58:20 PM PDT 24
Finished Aug 03 04:58:21 PM PDT 24
Peak memory 198560 kb
Host smart-8118837a-6497-46be-98e4-9a50fd45cf3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523004260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.523004260
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1628874935
Short name T7
Test name
Test status
Simulation time 143772091 ps
CPU time 0.92 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 209448 kb
Host smart-2d79bee6-7d8b-411a-812b-54f1787073b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628874935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1628874935
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3178085777
Short name T62
Test name
Test status
Simulation time 281799070 ps
CPU time 1.62 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:25:04 PM PDT 24
Peak memory 195260 kb
Host smart-1438a603-d578-4e44-b47b-2d0d0a34db32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178085777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3178085777
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.451208566
Short name T58
Test name
Test status
Simulation time 108191579 ps
CPU time 0.76 seconds
Started Aug 03 05:01:07 PM PDT 24
Finished Aug 03 05:01:08 PM PDT 24
Peak memory 198888 kb
Host smart-030ebb13-47e8-4139-a2d1-ec534c9c2115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451208566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.451208566
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.1119260842
Short name T19
Test name
Test status
Simulation time 310841054 ps
CPU time 1.46 seconds
Started Aug 03 04:58:35 PM PDT 24
Finished Aug 03 04:58:36 PM PDT 24
Peak memory 216932 kb
Host smart-76302b69-9cb4-42fa-b636-ec72a3a6d37b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119260842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1119260842
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1122135144
Short name T51
Test name
Test status
Simulation time 49856960 ps
CPU time 0.68 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 201060 kb
Host smart-af0137ed-3d57-4447-a10f-555930f9713d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122135144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.1122135144
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2323710111
Short name T32
Test name
Test status
Simulation time 59493902 ps
CPU time 0.75 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:36 PM PDT 24
Peak memory 199212 kb
Host smart-7e854192-51d9-4353-99af-a2e4be12b1dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323710111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2323710111
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.3533146186
Short name T164
Test name
Test status
Simulation time 148103229 ps
CPU time 1.54 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:29 PM PDT 24
Peak memory 201044 kb
Host smart-1f8a3a4d-7bf7-41ca-99d9-33e92c0b31c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533146186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3533146186
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3447374787
Short name T24
Test name
Test status
Simulation time 492470986 ps
CPU time 2.51 seconds
Started Aug 03 04:24:33 PM PDT 24
Finished Aug 03 04:24:36 PM PDT 24
Peak memory 196124 kb
Host smart-51b03810-4e82-4dba-bf9f-692ff474b2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447374787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3447374787
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1624126733
Short name T55
Test name
Test status
Simulation time 75200193 ps
CPU time 0.63 seconds
Started Aug 03 04:58:41 PM PDT 24
Finished Aug 03 04:58:42 PM PDT 24
Peak memory 198648 kb
Host smart-0bf38101-02c0-41ec-b585-3743a5e17cc8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624126733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.1624126733
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3724832247
Short name T66
Test name
Test status
Simulation time 99412820 ps
CPU time 1.06 seconds
Started Aug 03 04:59:25 PM PDT 24
Finished Aug 03 04:59:26 PM PDT 24
Peak memory 209524 kb
Host smart-0d4c2f2e-968e-4cc9-bdf9-c1261b6a6f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724832247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3724832247
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1664995362
Short name T638
Test name
Test status
Simulation time 57061988 ps
CPU time 0.63 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 194880 kb
Host smart-6c58d6ec-ff7b-4d09-be71-66fee2bef81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664995362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1664995362
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2775106375
Short name T10
Test name
Test status
Simulation time 37859129 ps
CPU time 0.63 seconds
Started Aug 03 05:01:04 PM PDT 24
Finished Aug 03 05:01:05 PM PDT 24
Peak memory 198524 kb
Host smart-90ce9d13-2afa-4e75-8169-f7a5b70f6c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775106375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2775106375
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.3827605729
Short name T13
Test name
Test status
Simulation time 660976123 ps
CPU time 1 seconds
Started Aug 03 04:59:53 PM PDT 24
Finished Aug 03 04:59:54 PM PDT 24
Peak memory 198084 kb
Host smart-7d5b57c2-c531-4973-bebd-5e2e39cd7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827605729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.3827605729
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1267738711
Short name T136
Test name
Test status
Simulation time 63281761 ps
CPU time 0.76 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 199120 kb
Host smart-5dbfde6f-5c64-49d8-a1da-d5b4b16c7006
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267738711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1267738711
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2678788052
Short name T102
Test name
Test status
Simulation time 18734165 ps
CPU time 0.69 seconds
Started Aug 03 04:24:51 PM PDT 24
Finished Aug 03 04:24:52 PM PDT 24
Peak memory 194904 kb
Host smart-55d20c27-22fe-415f-945c-24e68214bbbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678788052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2678788052
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2961802176
Short name T188
Test name
Test status
Simulation time 69818064 ps
CPU time 0.66 seconds
Started Aug 03 04:58:38 PM PDT 24
Finished Aug 03 04:58:38 PM PDT 24
Peak memory 201364 kb
Host smart-9756962d-3bb1-4f55-8534-6fbf879b18bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961802176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2961802176
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.4115921046
Short name T56
Test name
Test status
Simulation time 117932448 ps
CPU time 0.72 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 199292 kb
Host smart-42113d8e-ee55-43e6-a83b-3d533a2575b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115921046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.4115921046
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.3868569887
Short name T142
Test name
Test status
Simulation time 53113382 ps
CPU time 0.7 seconds
Started Aug 03 04:59:50 PM PDT 24
Finished Aug 03 04:59:51 PM PDT 24
Peak memory 198628 kb
Host smart-24d98a66-6a3b-4130-89a4-eba41c0a6aaf
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868569887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.3868569887
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.1049601701
Short name T39
Test name
Test status
Simulation time 75741050 ps
CPU time 0.65 seconds
Started Aug 03 05:01:07 PM PDT 24
Finished Aug 03 05:01:08 PM PDT 24
Peak memory 199128 kb
Host smart-53e3cf93-e32c-4ffd-9a3d-dec5b6beed9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049601701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.1049601701
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.387166917
Short name T52
Test name
Test status
Simulation time 59213237 ps
CPU time 0.67 seconds
Started Aug 03 05:01:17 PM PDT 24
Finished Aug 03 05:01:18 PM PDT 24
Peak memory 198320 kb
Host smart-d2565564-bb6f-4c9f-9f48-b7fd47beacb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387166917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wa
keup_race.387166917
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.3641850944
Short name T192
Test name
Test status
Simulation time 74586488 ps
CPU time 0.81 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198516 kb
Host smart-8499f656-cbbd-451a-8c82-0a8fa85db3e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641850944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3641850944
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3162168787
Short name T204
Test name
Test status
Simulation time 219862414 ps
CPU time 0.69 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:07 PM PDT 24
Peak memory 201396 kb
Host smart-e95e3564-3a52-4af3-a57a-363517ad8f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162168787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3162168787
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.866948952
Short name T87
Test name
Test status
Simulation time 96135415 ps
CPU time 0.76 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198988 kb
Host smart-db349f5a-4722-47f8-81dd-8e4fd84258c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866948952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.866948952
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4212776943
Short name T159
Test name
Test status
Simulation time 68774645 ps
CPU time 0.69 seconds
Started Aug 03 05:00:54 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 199140 kb
Host smart-77295edd-b5ac-401b-bb3b-7fb68999e719
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212776943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.4212776943
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.498808436
Short name T54
Test name
Test status
Simulation time 36342236 ps
CPU time 0.65 seconds
Started Aug 03 04:59:50 PM PDT 24
Finished Aug 03 04:59:51 PM PDT 24
Peak memory 198192 kb
Host smart-64400c71-3c88-4d40-8cf7-b27d6c790ea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498808436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wa
keup_race.498808436
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3164159332
Short name T143
Test name
Test status
Simulation time 54812381 ps
CPU time 0.75 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 198824 kb
Host smart-f54b57ad-c281-4030-b8fc-2e2bcebead69
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164159332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.3164159332
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2559229129
Short name T172
Test name
Test status
Simulation time 41709408 ps
CPU time 0.69 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 201332 kb
Host smart-9508bafc-9528-44a1-8301-0bc5539b8efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559229129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2559229129
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.326717360
Short name T100
Test name
Test status
Simulation time 33625441 ps
CPU time 0.67 seconds
Started Aug 03 04:24:28 PM PDT 24
Finished Aug 03 04:24:28 PM PDT 24
Peak memory 194972 kb
Host smart-eb7a5d0f-529a-46b1-a8b4-47f54f7c9f2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326717360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.326717360
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2960808229
Short name T67
Test name
Test status
Simulation time 503758054 ps
CPU time 1.43 seconds
Started Aug 03 04:24:55 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 200384 kb
Host smart-00e737d0-3dc8-4cee-9d5b-8bbb7b1496fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960808229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2960808229
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1175549012
Short name T202
Test name
Test status
Simulation time 44216571 ps
CPU time 0.67 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 201372 kb
Host smart-6bace89c-40f4-454e-84de-e69fdbee85ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175549012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1175549012
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1397452527
Short name T31
Test name
Test status
Simulation time 78013293 ps
CPU time 0.66 seconds
Started Aug 03 05:00:22 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 199072 kb
Host smart-0103cbcb-15a2-4b64-a128-dcbc1c501aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397452527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1397452527
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.3483741774
Short name T165
Test name
Test status
Simulation time 87065248 ps
CPU time 0.66 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 201340 kb
Host smart-96b651e9-2747-4192-b4a0-4697a869a17b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483741774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.3483741774
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.3634957638
Short name T199
Test name
Test status
Simulation time 58354643 ps
CPU time 0.7 seconds
Started Aug 03 04:58:59 PM PDT 24
Finished Aug 03 04:59:00 PM PDT 24
Peak memory 201420 kb
Host smart-8c471178-ec57-4826-be1c-4d4b54ea1382
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634957638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.3634957638
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.116881060
Short name T50
Test name
Test status
Simulation time 93786072 ps
CPU time 0.67 seconds
Started Aug 03 04:59:40 PM PDT 24
Finished Aug 03 04:59:41 PM PDT 24
Peak memory 201392 kb
Host smart-e874e1a4-a2e3-49d6-819a-3a9a50a65944
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116881060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.116881060
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2920993029
Short name T393
Test name
Test status
Simulation time 104598767 ps
CPU time 0.65 seconds
Started Aug 03 04:58:28 PM PDT 24
Finished Aug 03 04:58:29 PM PDT 24
Peak memory 198424 kb
Host smart-71621ae5-cbc5-4999-97d3-bb97a9b0f5aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920993029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2920993029
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2469841437
Short name T185
Test name
Test status
Simulation time 42596408 ps
CPU time 0.74 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 201152 kb
Host smart-fab6fe7b-683e-4795-8d23-182e532d843b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469841437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.2469841437
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.4289830164
Short name T85
Test name
Test status
Simulation time 29591651 ps
CPU time 0.66 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 198504 kb
Host smart-694b93f7-1c92-4214-b123-e074035afdd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289830164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.4289830164
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4063557688
Short name T210
Test name
Test status
Simulation time 57678137 ps
CPU time 0.81 seconds
Started Aug 03 04:58:42 PM PDT 24
Finished Aug 03 04:58:43 PM PDT 24
Peak memory 199096 kb
Host smart-e18eb3c2-29c9-43a0-b9d5-624df5b1cc28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063557688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.4063557688
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.941325755
Short name T205
Test name
Test status
Simulation time 45728250 ps
CPU time 0.72 seconds
Started Aug 03 04:59:58 PM PDT 24
Finished Aug 03 04:59:58 PM PDT 24
Peak memory 201376 kb
Host smart-d2632ebc-2ac1-4659-9183-28870a29713e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941325755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.941325755
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.1325442487
Short name T57
Test name
Test status
Simulation time 62394056 ps
CPU time 0.66 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198124 kb
Host smart-942bd39f-3e84-4144-aa8f-f003651b99c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325442487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.1325442487
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.3483458289
Short name T28
Test name
Test status
Simulation time 57460535 ps
CPU time 0.73 seconds
Started Aug 03 04:58:55 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 199248 kb
Host smart-5c64810e-8852-4e90-8276-1b77a310376d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483458289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3483458289
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3514469581
Short name T75
Test name
Test status
Simulation time 197325406 ps
CPU time 1.6 seconds
Started Aug 03 04:24:25 PM PDT 24
Finished Aug 03 04:24:27 PM PDT 24
Peak memory 200036 kb
Host smart-13f739ac-dc6e-434a-945d-4ee13511b58e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514469581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3514469581
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3094749571
Short name T80
Test name
Test status
Simulation time 671239062 ps
CPU time 1.51 seconds
Started Aug 03 04:24:31 PM PDT 24
Finished Aug 03 04:24:32 PM PDT 24
Peak memory 200440 kb
Host smart-d2f51376-c773-483d-820a-16275581c60c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094749571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.3094749571
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1664300759
Short name T17
Test name
Test status
Simulation time 59398453 ps
CPU time 0.68 seconds
Started Aug 03 04:59:21 PM PDT 24
Finished Aug 03 04:59:21 PM PDT 24
Peak memory 197972 kb
Host smart-318882e9-51e3-4616-8ab6-b27f0e4da6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664300759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1664300759
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2058268438
Short name T109
Test name
Test status
Simulation time 150116272 ps
CPU time 0.95 seconds
Started Aug 03 04:24:25 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 194888 kb
Host smart-8c46258f-2a03-4b46-8d41-1a981249526b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058268438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
058268438
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2567951868
Short name T639
Test name
Test status
Simulation time 449519174 ps
CPU time 1.91 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:24 PM PDT 24
Peak memory 195128 kb
Host smart-a7b87c92-1a7c-44fb-ae50-dfce002fe033
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567951868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.2
567951868
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2347146227
Short name T61
Test name
Test status
Simulation time 64182054 ps
CPU time 1.28 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:40 PM PDT 24
Peak memory 200472 kb
Host smart-4cdae323-1fd8-4a0f-8882-c5179baef91c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347146227 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2347146227
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1696247795
Short name T746
Test name
Test status
Simulation time 17068949 ps
CPU time 0.6 seconds
Started Aug 03 04:24:51 PM PDT 24
Finished Aug 03 04:24:52 PM PDT 24
Peak memory 194884 kb
Host smart-f0ec81db-00c3-4307-a24c-ff6c95399b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696247795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1696247795
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1781535905
Short name T113
Test name
Test status
Simulation time 90713357 ps
CPU time 0.67 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:46 PM PDT 24
Peak memory 197292 kb
Host smart-d60aef71-df91-46ed-84a6-d8ff0a918cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781535905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1781535905
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2505112732
Short name T692
Test name
Test status
Simulation time 127150221 ps
CPU time 1.12 seconds
Started Aug 03 04:24:17 PM PDT 24
Finished Aug 03 04:24:18 PM PDT 24
Peak memory 195408 kb
Host smart-a7ad5984-48b0-4295-8e86-e9a686320ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505112732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.2505112732
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2716802807
Short name T23
Test name
Test status
Simulation time 103804971 ps
CPU time 1.1 seconds
Started Aug 03 04:24:25 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 199688 kb
Host smart-03051ac1-83b4-48e9-81cc-a95cc21f34ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716802807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.2716802807
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1763368742
Short name T64
Test name
Test status
Simulation time 26989034 ps
CPU time 0.97 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:58 PM PDT 24
Peak memory 194932 kb
Host smart-f21b6f82-2fed-4ff1-a772-406c7a062378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763368742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
763368742
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2758559430
Short name T654
Test name
Test status
Simulation time 72221963 ps
CPU time 2.78 seconds
Started Aug 03 04:24:36 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 195096 kb
Host smart-939ba411-f81b-419c-8b91-b6a3ee28ab5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758559430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
758559430
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.563665588
Short name T644
Test name
Test status
Simulation time 49025820 ps
CPU time 0.62 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:38 PM PDT 24
Peak memory 197488 kb
Host smart-d42a2d90-75d1-4c40-b19b-517affaf0cff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563665588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.563665588
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.882311691
Short name T662
Test name
Test status
Simulation time 61719350 ps
CPU time 0.69 seconds
Started Aug 03 04:24:36 PM PDT 24
Finished Aug 03 04:24:37 PM PDT 24
Peak memory 195040 kb
Host smart-8bf3c7f8-41ae-4389-ae5b-28c259a27788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882311691 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.882311691
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2366400176
Short name T105
Test name
Test status
Simulation time 70369413 ps
CPU time 0.65 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:45 PM PDT 24
Peak memory 195008 kb
Host smart-7d54cd1b-7659-41eb-9c02-ecadf293f720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366400176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2366400176
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2889723118
Short name T70
Test name
Test status
Simulation time 20458794 ps
CPU time 0.59 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 194924 kb
Host smart-7de97a8d-bbf2-449a-bde0-da632665f7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889723118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2889723118
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3525422268
Short name T735
Test name
Test status
Simulation time 44682774 ps
CPU time 0.68 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:50 PM PDT 24
Peak memory 198364 kb
Host smart-ab5b277a-47a2-4997-83fb-f0131ffaaa5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525422268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3525422268
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3105874762
Short name T709
Test name
Test status
Simulation time 529209256 ps
CPU time 1.26 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:51 PM PDT 24
Peak memory 195416 kb
Host smart-4269bbc3-573c-4041-a942-968d38b9648e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105874762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3105874762
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.838834705
Short name T743
Test name
Test status
Simulation time 82698911 ps
CPU time 1 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:51 PM PDT 24
Peak memory 195132 kb
Host smart-a2071429-51ac-4bb2-8c46-d7a21de9e982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838834705 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.838834705
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2940729121
Short name T101
Test name
Test status
Simulation time 20350110 ps
CPU time 0.62 seconds
Started Aug 03 04:24:48 PM PDT 24
Finished Aug 03 04:24:49 PM PDT 24
Peak memory 195012 kb
Host smart-ee91570e-bf3a-4b9a-bbb7-e9ae75b29fdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940729121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2940729121
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.672296108
Short name T672
Test name
Test status
Simulation time 23211678 ps
CPU time 0.61 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 194908 kb
Host smart-1952df9a-75a8-4a12-9cca-94e2d455ec3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672296108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.672296108
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.4019637977
Short name T703
Test name
Test status
Simulation time 83449502 ps
CPU time 0.73 seconds
Started Aug 03 04:24:54 PM PDT 24
Finished Aug 03 04:24:54 PM PDT 24
Peak memory 194936 kb
Host smart-1af6f749-ba29-4971-97a9-b1a97404d9b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019637977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.4019637977
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.294355980
Short name T715
Test name
Test status
Simulation time 102976103 ps
CPU time 1.33 seconds
Started Aug 03 04:24:26 PM PDT 24
Finished Aug 03 04:24:27 PM PDT 24
Peak memory 200468 kb
Host smart-209a7124-d88d-498e-9593-284197c1d129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294355980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.294355980
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3229538260
Short name T716
Test name
Test status
Simulation time 45233161 ps
CPU time 0.94 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:25:14 PM PDT 24
Peak memory 195092 kb
Host smart-8762780c-7e29-44c6-9dbc-07aeec0ee237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229538260 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.3229538260
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2895701
Short name T104
Test name
Test status
Simulation time 46618498 ps
CPU time 0.65 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:50 PM PDT 24
Peak memory 194964 kb
Host smart-b2b90ab4-456f-4d86-a572-5e9a9ce66b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2895701
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1103358471
Short name T642
Test name
Test status
Simulation time 18101547 ps
CPU time 0.64 seconds
Started Aug 03 04:24:54 PM PDT 24
Finished Aug 03 04:24:55 PM PDT 24
Peak memory 194948 kb
Host smart-fcdabaaf-29c2-417f-9854-533d23a5af57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103358471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1103358471
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4263285334
Short name T736
Test name
Test status
Simulation time 23551550 ps
CPU time 0.83 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:46 PM PDT 24
Peak memory 195016 kb
Host smart-50476cc0-b7f9-4242-afe0-def4c4897811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263285334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.4263285334
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.4055974388
Short name T731
Test name
Test status
Simulation time 88494976 ps
CPU time 1.87 seconds
Started Aug 03 04:24:46 PM PDT 24
Finished Aug 03 04:24:48 PM PDT 24
Peak memory 196300 kb
Host smart-a00bd4f5-cf7f-4ef5-9931-0ae36317de86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055974388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.4055974388
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3488432102
Short name T680
Test name
Test status
Simulation time 315738755 ps
CPU time 1.03 seconds
Started Aug 03 04:24:41 PM PDT 24
Finished Aug 03 04:24:42 PM PDT 24
Peak memory 195244 kb
Host smart-9b5b2036-49e7-4c7d-9abf-7f6ccd98ea20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488432102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.3488432102
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3648194386
Short name T711
Test name
Test status
Simulation time 54286379 ps
CPU time 0.95 seconds
Started Aug 03 04:24:21 PM PDT 24
Finished Aug 03 04:24:22 PM PDT 24
Peak memory 200368 kb
Host smart-f132fc2d-b42b-4602-b495-85deb710a816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648194386 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3648194386
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2345323483
Short name T719
Test name
Test status
Simulation time 22659700 ps
CPU time 0.67 seconds
Started Aug 03 04:24:53 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 197140 kb
Host smart-8f0a2f9f-bc42-4aa2-b222-bd616d2c105b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345323483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2345323483
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1313644389
Short name T681
Test name
Test status
Simulation time 37449404 ps
CPU time 0.62 seconds
Started Aug 03 04:24:47 PM PDT 24
Finished Aug 03 04:24:48 PM PDT 24
Peak memory 194904 kb
Host smart-49a90f21-a5d8-4d69-be90-20e01046714b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313644389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1313644389
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1389548340
Short name T114
Test name
Test status
Simulation time 27680172 ps
CPU time 0.76 seconds
Started Aug 03 04:24:41 PM PDT 24
Finished Aug 03 04:24:41 PM PDT 24
Peak memory 197276 kb
Host smart-dd58f2ab-ba21-420f-9bd0-07b0ca2a1ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389548340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.1389548340
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3794785803
Short name T93
Test name
Test status
Simulation time 58355524 ps
CPU time 1.26 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:47 PM PDT 24
Peak memory 195368 kb
Host smart-78d84485-ab9d-4e0f-94ee-6b72f285c860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794785803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3794785803
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3845729521
Short name T676
Test name
Test status
Simulation time 409212425 ps
CPU time 1.64 seconds
Started Aug 03 04:24:35 PM PDT 24
Finished Aug 03 04:24:36 PM PDT 24
Peak memory 195560 kb
Host smart-b5852e9c-4088-4fef-b1c0-b43d7281d4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845729521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.3845729521
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3954258292
Short name T92
Test name
Test status
Simulation time 58022563 ps
CPU time 0.99 seconds
Started Aug 03 04:24:21 PM PDT 24
Finished Aug 03 04:24:22 PM PDT 24
Peak memory 196044 kb
Host smart-373c79fd-6304-4b34-8d2a-f09f1360fa09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954258292 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3954258292
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.4132981438
Short name T110
Test name
Test status
Simulation time 16648706 ps
CPU time 0.62 seconds
Started Aug 03 04:24:59 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 194964 kb
Host smart-79f9b8a7-dfad-4d48-985d-84a92ad791f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132981438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.4132981438
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.387816537
Short name T744
Test name
Test status
Simulation time 22295090 ps
CPU time 0.6 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:46 PM PDT 24
Peak memory 194816 kb
Host smart-4a4aa456-aac7-4ecd-90ba-bdd9adc53968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387816537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.387816537
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2977615668
Short name T708
Test name
Test status
Simulation time 285935700 ps
CPU time 0.88 seconds
Started Aug 03 04:24:26 PM PDT 24
Finished Aug 03 04:24:27 PM PDT 24
Peak memory 198316 kb
Host smart-cad442df-b2b5-479c-84ce-ead129740aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977615668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2977615668
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2147735178
Short name T700
Test name
Test status
Simulation time 229232570 ps
CPU time 1.34 seconds
Started Aug 03 04:24:51 PM PDT 24
Finished Aug 03 04:24:52 PM PDT 24
Peak memory 195380 kb
Host smart-30d14691-ee2e-4677-82a9-5284681e16a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147735178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2147735178
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2041964705
Short name T146
Test name
Test status
Simulation time 123616617 ps
CPU time 1.06 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:54 PM PDT 24
Peak memory 199740 kb
Host smart-803d5a79-0be9-464f-a214-2fc8315390cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041964705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.2041964705
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3707988792
Short name T693
Test name
Test status
Simulation time 51036577 ps
CPU time 0.78 seconds
Started Aug 03 04:24:25 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 195124 kb
Host smart-3ddeb517-96f2-43e1-9097-51c751992d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707988792 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.3707988792
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1481180594
Short name T106
Test name
Test status
Simulation time 16670970 ps
CPU time 0.63 seconds
Started Aug 03 04:24:46 PM PDT 24
Finished Aug 03 04:24:47 PM PDT 24
Peak memory 195028 kb
Host smart-c14fa00c-d05d-4d7c-8c3f-bea3d165282c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481180594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1481180594
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4066671049
Short name T698
Test name
Test status
Simulation time 17797911 ps
CPU time 0.62 seconds
Started Aug 03 04:24:44 PM PDT 24
Finished Aug 03 04:24:44 PM PDT 24
Peak memory 194908 kb
Host smart-2871cf47-346b-48b1-a939-5f5a99b69b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066671049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.4066671049
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2046892888
Short name T704
Test name
Test status
Simulation time 140621846 ps
CPU time 0.9 seconds
Started Aug 03 04:24:46 PM PDT 24
Finished Aug 03 04:24:47 PM PDT 24
Peak memory 198304 kb
Host smart-a60290e8-4772-4d61-b3e4-61af4099add1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046892888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2046892888
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3834982366
Short name T685
Test name
Test status
Simulation time 45798481 ps
CPU time 1.98 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:25:17 PM PDT 24
Peak memory 200560 kb
Host smart-7ce7fc8f-967e-415f-9120-d14d605259a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834982366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3834982366
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3422986679
Short name T686
Test name
Test status
Simulation time 273209954 ps
CPU time 0.97 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 200256 kb
Host smart-385d6967-33cf-40d8-97f0-8feea7cb0f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422986679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3422986679
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.526728987
Short name T688
Test name
Test status
Simulation time 50853146 ps
CPU time 0.79 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 195192 kb
Host smart-1ff13c09-d7e4-412c-b858-a52e5b7f8e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526728987 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.526728987
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2798582263
Short name T696
Test name
Test status
Simulation time 18291313 ps
CPU time 0.65 seconds
Started Aug 03 04:24:50 PM PDT 24
Finished Aug 03 04:24:51 PM PDT 24
Peak memory 197216 kb
Host smart-92fba11d-eb9e-4efc-98ca-9ec37c1e060c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798582263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2798582263
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1067191401
Short name T668
Test name
Test status
Simulation time 26425894 ps
CPU time 0.61 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 194940 kb
Host smart-5f0cfc5a-6462-404f-8f13-65fcbc7427ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067191401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1067191401
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1781262364
Short name T710
Test name
Test status
Simulation time 25541337 ps
CPU time 0.68 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:25:01 PM PDT 24
Peak memory 198480 kb
Host smart-660b8cf8-df2c-45d9-aba9-b17c973b5b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781262364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1781262364
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.850083029
Short name T729
Test name
Test status
Simulation time 59135892 ps
CPU time 1.37 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:54 PM PDT 24
Peak memory 195300 kb
Host smart-9d847ce6-897d-42c0-a7a0-c62ab2932795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850083029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.850083029
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.253498259
Short name T25
Test name
Test status
Simulation time 241661204 ps
CPU time 1.57 seconds
Started Aug 03 04:24:36 PM PDT 24
Finished Aug 03 04:24:37 PM PDT 24
Peak memory 200188 kb
Host smart-5bd0e1a5-8c64-4371-961a-a6fec6c177fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253498259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err
.253498259
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3522709739
Short name T648
Test name
Test status
Simulation time 74875948 ps
CPU time 0.77 seconds
Started Aug 03 04:25:06 PM PDT 24
Finished Aug 03 04:25:07 PM PDT 24
Peak memory 195076 kb
Host smart-82691eba-46ad-4048-8492-fb1452dd62dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522709739 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3522709739
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3686563157
Short name T108
Test name
Test status
Simulation time 25079346 ps
CPU time 0.65 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 197116 kb
Host smart-a3d1c12d-0b24-4ec3-a58d-95c8eb35780f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686563157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3686563157
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.755777649
Short name T728
Test name
Test status
Simulation time 44217069 ps
CPU time 0.58 seconds
Started Aug 03 04:24:20 PM PDT 24
Finished Aug 03 04:24:21 PM PDT 24
Peak memory 194924 kb
Host smart-3de0b35c-1c07-4669-8538-f8aecfaba62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755777649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.755777649
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2240720118
Short name T720
Test name
Test status
Simulation time 30020656 ps
CPU time 0.83 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:25:04 PM PDT 24
Peak memory 198384 kb
Host smart-d419c9e7-f57a-4721-9b2d-7ec65dce0532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240720118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.2240720118
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2160713181
Short name T730
Test name
Test status
Simulation time 242960804 ps
CPU time 2.47 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 196104 kb
Host smart-ba72fb87-73f8-4af4-bb8a-e87595dee4c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160713181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2160713181
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2121633947
Short name T721
Test name
Test status
Simulation time 173688441 ps
CPU time 1.57 seconds
Started Aug 03 04:24:23 PM PDT 24
Finished Aug 03 04:24:25 PM PDT 24
Peak memory 200264 kb
Host smart-92878f32-54e5-44df-ae5a-6ba0cb9264b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121633947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2121633947
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3712543600
Short name T658
Test name
Test status
Simulation time 56262846 ps
CPU time 0.77 seconds
Started Aug 03 04:24:40 PM PDT 24
Finished Aug 03 04:24:41 PM PDT 24
Peak memory 195176 kb
Host smart-704b37d5-2d21-4bf1-ab9e-2e355a97520a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712543600 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3712543600
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2314175946
Short name T663
Test name
Test status
Simulation time 17915414 ps
CPU time 0.6 seconds
Started Aug 03 04:24:48 PM PDT 24
Finished Aug 03 04:24:49 PM PDT 24
Peak memory 195048 kb
Host smart-3f4a4d8f-30c9-4b76-bd91-9b7c64ccbc85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314175946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2314175946
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2661990282
Short name T649
Test name
Test status
Simulation time 52060511 ps
CPU time 0.58 seconds
Started Aug 03 04:24:41 PM PDT 24
Finished Aug 03 04:24:42 PM PDT 24
Peak memory 194980 kb
Host smart-6c1ad91d-aa74-4cd0-99ac-47f56bdb30ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661990282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2661990282
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.832895396
Short name T111
Test name
Test status
Simulation time 40431161 ps
CPU time 0.83 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:25:14 PM PDT 24
Peak memory 198516 kb
Host smart-e16f09cb-4621-40be-b395-7a2374c3012d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832895396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.832895396
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2620640467
Short name T677
Test name
Test status
Simulation time 291807116 ps
CPU time 1.57 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 195248 kb
Host smart-3215291d-13e4-4233-ba3d-f660ab6b27ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620640467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.2620640467
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2899513445
Short name T712
Test name
Test status
Simulation time 66228125 ps
CPU time 0.85 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:50 PM PDT 24
Peak memory 195168 kb
Host smart-8e3f0394-7bf9-45c1-b9c9-3e1806577ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899513445 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2899513445
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3825138511
Short name T727
Test name
Test status
Simulation time 58723041 ps
CPU time 0.66 seconds
Started Aug 03 04:24:53 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 194952 kb
Host smart-08cd76ef-42c5-4207-9a63-28ba0b1e6d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825138511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3825138511
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3748030711
Short name T675
Test name
Test status
Simulation time 46818355 ps
CPU time 0.68 seconds
Started Aug 03 04:24:51 PM PDT 24
Finished Aug 03 04:24:52 PM PDT 24
Peak memory 194952 kb
Host smart-51a1261e-adf4-4969-8edf-1b7f0c706d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748030711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3748030711
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.665127956
Short name T115
Test name
Test status
Simulation time 29289000 ps
CPU time 0.75 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:25:03 PM PDT 24
Peak memory 197128 kb
Host smart-75a00f05-6452-4dcf-9c43-85fd3b48e12d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665127956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.665127956
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2342368506
Short name T68
Test name
Test status
Simulation time 251367194 ps
CPU time 3.13 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:49 PM PDT 24
Peak memory 197348 kb
Host smart-b5b7f7f5-8a0d-4775-b28d-d441eb759546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342368506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.2342368506
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3134663872
Short name T91
Test name
Test status
Simulation time 114434848 ps
CPU time 1.19 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 199812 kb
Host smart-52ac47b9-52b3-43d4-8a12-6db6dd99c28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134663872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3134663872
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1132889683
Short name T60
Test name
Test status
Simulation time 138170279 ps
CPU time 1.35 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:25:00 PM PDT 24
Peak memory 200276 kb
Host smart-d70bbce4-ca7f-4950-afdb-9cd3aca00fe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132889683 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1132889683
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.800832393
Short name T99
Test name
Test status
Simulation time 95024475 ps
CPU time 0.62 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 195044 kb
Host smart-5aa523bb-a034-4ccd-af3f-6ea5a657774e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800832393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.800832393
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4091365082
Short name T691
Test name
Test status
Simulation time 47777802 ps
CPU time 0.6 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:25:05 PM PDT 24
Peak memory 194888 kb
Host smart-cc3c6fd3-bbe0-497f-8733-6d8ae6192849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091365082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4091365082
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.459632201
Short name T116
Test name
Test status
Simulation time 128230534 ps
CPU time 0.87 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:25:03 PM PDT 24
Peak memory 194960 kb
Host smart-22bdd5ac-53ac-4394-8cbd-20870cf7a567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459632201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sa
me_csr_outstanding.459632201
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.911983504
Short name T673
Test name
Test status
Simulation time 427686646 ps
CPU time 2.09 seconds
Started Aug 03 04:24:55 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 196632 kb
Host smart-2e3ed4d5-582c-4635-ac14-a3abadd4f52a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911983504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.911983504
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3558276544
Short name T145
Test name
Test status
Simulation time 339247203 ps
CPU time 1.43 seconds
Started Aug 03 04:24:43 PM PDT 24
Finished Aug 03 04:24:45 PM PDT 24
Peak memory 200232 kb
Host smart-cedd6ecd-3ded-45bf-8348-0b823f65276b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558276544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3558276544
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3505879579
Short name T121
Test name
Test status
Simulation time 54870519 ps
CPU time 1.04 seconds
Started Aug 03 04:24:43 PM PDT 24
Finished Aug 03 04:24:44 PM PDT 24
Peak memory 198356 kb
Host smart-2e5d76c0-66dc-4421-b36d-d8bd122c3a4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505879579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
505879579
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.851961857
Short name T651
Test name
Test status
Simulation time 862255100 ps
CPU time 3.21 seconds
Started Aug 03 04:24:54 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 195112 kb
Host smart-844d0266-4a41-4499-be02-be6f08670188
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851961857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.851961857
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3494162572
Short name T640
Test name
Test status
Simulation time 40343005 ps
CPU time 0.64 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 198108 kb
Host smart-e793c6c7-186f-4158-8ac5-debea659b350
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494162572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
494162572
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3447164294
Short name T69
Test name
Test status
Simulation time 71816137 ps
CPU time 1.32 seconds
Started Aug 03 04:24:43 PM PDT 24
Finished Aug 03 04:24:44 PM PDT 24
Peak memory 197568 kb
Host smart-c5dec540-7b9f-43bc-87cc-d9721ac5c90e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447164294 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.3447164294
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2040267198
Short name T707
Test name
Test status
Simulation time 39684289 ps
CPU time 0.67 seconds
Started Aug 03 04:24:42 PM PDT 24
Finished Aug 03 04:24:43 PM PDT 24
Peak memory 194984 kb
Host smart-11a91611-3a53-42f7-a8a4-512edffaadd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040267198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2040267198
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.674156915
Short name T646
Test name
Test status
Simulation time 20644080 ps
CPU time 0.62 seconds
Started Aug 03 04:24:36 PM PDT 24
Finished Aug 03 04:24:36 PM PDT 24
Peak memory 194920 kb
Host smart-0906bce6-ccd3-4483-a901-4a337108153f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674156915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.674156915
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3387992287
Short name T724
Test name
Test status
Simulation time 128252989 ps
CPU time 0.86 seconds
Started Aug 03 04:24:40 PM PDT 24
Finished Aug 03 04:24:41 PM PDT 24
Peak memory 194960 kb
Host smart-4ec858eb-06ca-4dc9-9524-85c4c010e157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387992287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3387992287
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.970995411
Short name T678
Test name
Test status
Simulation time 109940612 ps
CPU time 2.22 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 196576 kb
Host smart-c386ebcb-4709-464d-8252-fb0134a96870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970995411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.970995411
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.877329218
Short name T739
Test name
Test status
Simulation time 275599772 ps
CPU time 1.05 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 200376 kb
Host smart-94a7d8e3-03d9-48be-b079-204c9f35ecc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877329218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
877329218
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.4057530875
Short name T697
Test name
Test status
Simulation time 22571714 ps
CPU time 0.58 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 194972 kb
Host smart-868dfff7-232b-44ab-ac24-64ea19db4d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057530875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.4057530875
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2724955054
Short name T656
Test name
Test status
Simulation time 33238057 ps
CPU time 0.63 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 194896 kb
Host smart-18b70a67-28ee-45a6-b6c3-4cd7198d02f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724955054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2724955054
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.771409820
Short name T718
Test name
Test status
Simulation time 19426547 ps
CPU time 0.61 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 194928 kb
Host smart-ea4e5122-d85e-4869-91d6-869fce741cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771409820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.771409820
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3650092044
Short name T674
Test name
Test status
Simulation time 32878076 ps
CPU time 0.57 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:52 PM PDT 24
Peak memory 194816 kb
Host smart-67ce5646-4143-4959-a659-5e1cb9466afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650092044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3650092044
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1021223951
Short name T701
Test name
Test status
Simulation time 18190666 ps
CPU time 0.6 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:24:56 PM PDT 24
Peak memory 194884 kb
Host smart-69380e2b-5a63-4b32-ab6f-a2861f6696a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021223951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1021223951
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1056030356
Short name T653
Test name
Test status
Simulation time 16653620 ps
CPU time 0.63 seconds
Started Aug 03 04:24:54 PM PDT 24
Finished Aug 03 04:24:55 PM PDT 24
Peak memory 194908 kb
Host smart-1a526622-d2b0-4a65-8a92-68530a726e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056030356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1056030356
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3161689421
Short name T738
Test name
Test status
Simulation time 16596305 ps
CPU time 0.57 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:25:14 PM PDT 24
Peak memory 194884 kb
Host smart-17398964-a538-4ad1-b024-b6481970fa75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161689421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3161689421
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3992335370
Short name T725
Test name
Test status
Simulation time 18022409 ps
CPU time 0.63 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 194960 kb
Host smart-f9e016d8-54e6-4639-b472-439cab07e521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992335370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3992335370
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.675440920
Short name T684
Test name
Test status
Simulation time 19186585 ps
CPU time 0.6 seconds
Started Aug 03 04:24:59 PM PDT 24
Finished Aug 03 04:24:59 PM PDT 24
Peak memory 194816 kb
Host smart-db404629-283a-4a2f-a3d5-e640557225f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675440920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.675440920
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.895556496
Short name T71
Test name
Test status
Simulation time 18868132 ps
CPU time 0.65 seconds
Started Aug 03 04:24:47 PM PDT 24
Finished Aug 03 04:24:48 PM PDT 24
Peak memory 194924 kb
Host smart-658588a0-2f8e-4f0f-a4c1-11c07beeb99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895556496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.895556496
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1959674567
Short name T723
Test name
Test status
Simulation time 112166962 ps
CPU time 0.74 seconds
Started Aug 03 04:24:41 PM PDT 24
Finished Aug 03 04:24:42 PM PDT 24
Peak memory 194804 kb
Host smart-0bcb8217-39fc-4faf-bdbf-0175a0bda77b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959674567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1
959674567
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1852836407
Short name T107
Test name
Test status
Simulation time 161381120 ps
CPU time 1.92 seconds
Started Aug 03 04:24:26 PM PDT 24
Finished Aug 03 04:24:28 PM PDT 24
Peak memory 195160 kb
Host smart-f065c730-1af0-4b6b-a267-208c74a0aaae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852836407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
852836407
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.548317891
Short name T76
Test name
Test status
Simulation time 37882965 ps
CPU time 0.68 seconds
Started Aug 03 04:24:39 PM PDT 24
Finished Aug 03 04:24:40 PM PDT 24
Peak memory 198048 kb
Host smart-9fec953f-828e-4e13-b4ac-1d4771330ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548317891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.548317891
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1778067539
Short name T78
Test name
Test status
Simulation time 51951227 ps
CPU time 1.51 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:25:05 PM PDT 24
Peak memory 199400 kb
Host smart-598c85d0-f861-4d55-b850-a4cbfe6420db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778067539 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1778067539
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2458127524
Short name T647
Test name
Test status
Simulation time 51954678 ps
CPU time 0.68 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 195004 kb
Host smart-6be53cbb-0d54-4f6e-bf70-e20f4b4e3672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458127524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2458127524
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.267893832
Short name T637
Test name
Test status
Simulation time 49965755 ps
CPU time 0.62 seconds
Started Aug 03 04:25:06 PM PDT 24
Finished Aug 03 04:25:06 PM PDT 24
Peak memory 194928 kb
Host smart-194fa15b-c959-4e87-9a72-c23f800f2e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267893832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.267893832
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1358451801
Short name T745
Test name
Test status
Simulation time 29841483 ps
CPU time 0.7 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:24:50 PM PDT 24
Peak memory 197204 kb
Host smart-cdaabca1-8f87-4ae2-8cd5-0bd8bafa6c60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358451801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.1358451801
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3261410276
Short name T666
Test name
Test status
Simulation time 61590028 ps
CPU time 1.25 seconds
Started Aug 03 04:24:42 PM PDT 24
Finished Aug 03 04:24:43 PM PDT 24
Peak memory 197172 kb
Host smart-8e4719bf-9354-4cc7-b969-3a16c78783a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261410276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3261410276
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1837827700
Short name T74
Test name
Test status
Simulation time 192513043 ps
CPU time 1.68 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:24 PM PDT 24
Peak memory 200380 kb
Host smart-299ad1cb-0ae3-45e1-bbfb-c227c76c0fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837827700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1837827700
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3195380546
Short name T659
Test name
Test status
Simulation time 45086493 ps
CPU time 0.55 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 194956 kb
Host smart-31c55a1f-0b34-4856-a8e9-d0471e7dcb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195380546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3195380546
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3624781357
Short name T643
Test name
Test status
Simulation time 81392604 ps
CPU time 0.64 seconds
Started Aug 03 04:25:07 PM PDT 24
Finished Aug 03 04:25:08 PM PDT 24
Peak memory 194908 kb
Host smart-d765b7d4-c2df-46ee-9ac5-4b991bce998c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624781357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3624781357
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2306040122
Short name T737
Test name
Test status
Simulation time 64612138 ps
CPU time 0.61 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:25:00 PM PDT 24
Peak memory 194980 kb
Host smart-add35048-2247-48ed-be33-a50baff17045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306040122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2306040122
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2258411812
Short name T149
Test name
Test status
Simulation time 45714399 ps
CPU time 0.61 seconds
Started Aug 03 04:24:37 PM PDT 24
Finished Aug 03 04:24:38 PM PDT 24
Peak memory 194880 kb
Host smart-f3e49df6-fd1f-48c7-b7ba-0d43cd54cc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258411812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2258411812
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1891748739
Short name T657
Test name
Test status
Simulation time 41523801 ps
CPU time 0.6 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 194896 kb
Host smart-f82bcc6e-c022-43a5-9000-c3e669c3cfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891748739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1891748739
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.4224326003
Short name T148
Test name
Test status
Simulation time 24270760 ps
CPU time 0.67 seconds
Started Aug 03 04:24:47 PM PDT 24
Finished Aug 03 04:24:48 PM PDT 24
Peak memory 194960 kb
Host smart-61ddcbd0-8d38-4688-b3de-41ce761debf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224326003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.4224326003
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2232310683
Short name T641
Test name
Test status
Simulation time 43562686 ps
CPU time 0.58 seconds
Started Aug 03 04:24:37 PM PDT 24
Finished Aug 03 04:24:37 PM PDT 24
Peak memory 194876 kb
Host smart-fa5c5f24-d58c-4776-9f6a-cccd5340aed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232310683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2232310683
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4146119152
Short name T72
Test name
Test status
Simulation time 21455704 ps
CPU time 0.61 seconds
Started Aug 03 04:24:52 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 194884 kb
Host smart-6f39179d-c783-4034-8d7e-0478007da8f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146119152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.4146119152
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2695245431
Short name T722
Test name
Test status
Simulation time 42609151 ps
CPU time 0.62 seconds
Started Aug 03 04:24:50 PM PDT 24
Finished Aug 03 04:24:51 PM PDT 24
Peak memory 194884 kb
Host smart-aab8b361-ffc5-48d1-ab55-96a2515b32b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695245431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2695245431
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3223523401
Short name T655
Test name
Test status
Simulation time 20643452 ps
CPU time 0.65 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 194936 kb
Host smart-be67636b-bb8f-442c-906f-614fae180507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223523401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3223523401
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3637446111
Short name T652
Test name
Test status
Simulation time 31555583 ps
CPU time 0.82 seconds
Started Aug 03 04:24:43 PM PDT 24
Finished Aug 03 04:24:44 PM PDT 24
Peak memory 197144 kb
Host smart-7258ab16-9245-46e1-8805-2fae4829d845
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637446111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3
637446111
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.676123191
Short name T690
Test name
Test status
Simulation time 617336966 ps
CPU time 1.93 seconds
Started Aug 03 04:24:51 PM PDT 24
Finished Aug 03 04:24:53 PM PDT 24
Peak memory 195100 kb
Host smart-cd457d61-401e-41cf-8ab4-58dbaf97007d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676123191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.676123191
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3568757317
Short name T645
Test name
Test status
Simulation time 23691668 ps
CPU time 0.62 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:38 PM PDT 24
Peak memory 197616 kb
Host smart-3c616375-5960-4b4e-9bc5-95ba95ad1a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568757317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
568757317
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2902354850
Short name T689
Test name
Test status
Simulation time 126969652 ps
CPU time 0.94 seconds
Started Aug 03 04:24:35 PM PDT 24
Finished Aug 03 04:24:36 PM PDT 24
Peak memory 195980 kb
Host smart-5310444e-c16f-489f-8550-c182dcf4b870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902354850 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2902354850
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3745057586
Short name T123
Test name
Test status
Simulation time 22499633 ps
CPU time 0.63 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:24 PM PDT 24
Peak memory 197028 kb
Host smart-67673b8e-85ed-48bb-bcd2-eca26930ab26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745057586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3745057586
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2734679211
Short name T665
Test name
Test status
Simulation time 19370681 ps
CPU time 0.62 seconds
Started Aug 03 04:24:35 PM PDT 24
Finished Aug 03 04:24:36 PM PDT 24
Peak memory 194928 kb
Host smart-b1bb8b58-d4e4-41d4-9efc-c15ea65ddefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734679211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2734679211
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2617734098
Short name T65
Test name
Test status
Simulation time 40778809 ps
CPU time 0.83 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 199680 kb
Host smart-b2300e50-1939-4dca-bc33-12f5ab477876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617734098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.2617734098
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1218844777
Short name T77
Test name
Test status
Simulation time 359973835 ps
CPU time 1.16 seconds
Started Aug 03 04:24:20 PM PDT 24
Finished Aug 03 04:24:22 PM PDT 24
Peak memory 197052 kb
Host smart-ac9369da-3f53-4362-a700-a8bce23b4915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218844777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1218844777
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1673959415
Short name T73
Test name
Test status
Simulation time 109063482 ps
CPU time 1.15 seconds
Started Aug 03 04:24:59 PM PDT 24
Finished Aug 03 04:25:00 PM PDT 24
Peak memory 200292 kb
Host smart-46883a1f-1066-43f4-a440-4d4c37c82e68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673959415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1673959415
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1181621256
Short name T150
Test name
Test status
Simulation time 51505238 ps
CPU time 0.63 seconds
Started Aug 03 04:24:44 PM PDT 24
Finished Aug 03 04:24:45 PM PDT 24
Peak memory 194964 kb
Host smart-83d2cf22-376a-4333-870e-36838759a214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181621256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1181621256
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.871906933
Short name T714
Test name
Test status
Simulation time 37950840 ps
CPU time 0.66 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:25:03 PM PDT 24
Peak memory 194896 kb
Host smart-1adaeee8-9b29-4537-8211-fa920b636d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871906933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.871906933
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3480192502
Short name T732
Test name
Test status
Simulation time 38356447 ps
CPU time 0.65 seconds
Started Aug 03 04:25:04 PM PDT 24
Finished Aug 03 04:25:04 PM PDT 24
Peak memory 194908 kb
Host smart-c9baf836-9db0-428a-a485-e0bf573c2ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480192502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3480192502
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2937848923
Short name T679
Test name
Test status
Simulation time 25251598 ps
CPU time 0.58 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:24:57 PM PDT 24
Peak memory 194884 kb
Host smart-3196a17b-4f07-43c9-85f4-c15c71c16858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937848923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2937848923
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1328065461
Short name T733
Test name
Test status
Simulation time 37404387 ps
CPU time 0.57 seconds
Started Aug 03 04:24:48 PM PDT 24
Finished Aug 03 04:24:48 PM PDT 24
Peak memory 194980 kb
Host smart-fb416be3-528e-49fa-a9eb-266b44396819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328065461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1328065461
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3743227779
Short name T670
Test name
Test status
Simulation time 24555493 ps
CPU time 0.61 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:25:23 PM PDT 24
Peak memory 194952 kb
Host smart-f8ecd56a-709e-4e14-9279-4b443e996a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743227779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3743227779
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1742989467
Short name T151
Test name
Test status
Simulation time 43661792 ps
CPU time 0.65 seconds
Started Aug 03 04:24:26 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 195228 kb
Host smart-77fe7b4f-a234-4e6f-8047-60ca987ce269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742989467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1742989467
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2197124604
Short name T667
Test name
Test status
Simulation time 46176923 ps
CPU time 0.61 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:25:05 PM PDT 24
Peak memory 194948 kb
Host smart-ff80b33e-3fa5-465e-8052-f997e10f319b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197124604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2197124604
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.894782391
Short name T740
Test name
Test status
Simulation time 101872466 ps
CPU time 0.59 seconds
Started Aug 03 04:24:47 PM PDT 24
Finished Aug 03 04:24:47 PM PDT 24
Peak memory 194928 kb
Host smart-ccf644c9-c454-43c0-a1ed-21d2ab4151d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894782391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.894782391
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3933849763
Short name T695
Test name
Test status
Simulation time 67598134 ps
CPU time 1.29 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 196948 kb
Host smart-d8c6f903-f079-449a-8982-8c38a758cddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933849763 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3933849763
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1630158956
Short name T103
Test name
Test status
Simulation time 104918527 ps
CPU time 0.67 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:25 PM PDT 24
Peak memory 194448 kb
Host smart-cc92791f-ff7a-46e8-a601-2855e61a3b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630158956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1630158956
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2236965186
Short name T705
Test name
Test status
Simulation time 73189679 ps
CPU time 0.58 seconds
Started Aug 03 04:24:32 PM PDT 24
Finished Aug 03 04:24:33 PM PDT 24
Peak memory 194828 kb
Host smart-3de8760e-f6be-441f-8103-e343d2f6fd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236965186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2236965186
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1049732017
Short name T112
Test name
Test status
Simulation time 136290545 ps
CPU time 0.79 seconds
Started Aug 03 04:24:22 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 199684 kb
Host smart-ed396092-588b-4b20-9510-696a5f968ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049732017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.1049732017
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.154858088
Short name T706
Test name
Test status
Simulation time 819007515 ps
CPU time 1.22 seconds
Started Aug 03 04:24:43 PM PDT 24
Finished Aug 03 04:24:44 PM PDT 24
Peak memory 195392 kb
Host smart-086ff6f1-354d-4d9f-8a53-66770297bbe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154858088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.154858088
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3539117661
Short name T79
Test name
Test status
Simulation time 414058681 ps
CPU time 1.55 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 200408 kb
Host smart-b4c0b2cb-c5d7-40a6-8a2f-be46b4b7ecd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539117661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3539117661
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1085805545
Short name T699
Test name
Test status
Simulation time 92515267 ps
CPU time 1.16 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:46 PM PDT 24
Peak memory 200628 kb
Host smart-8839a278-ea68-4fed-bef2-17c4557d11bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085805545 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1085805545
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1673121472
Short name T694
Test name
Test status
Simulation time 69885297 ps
CPU time 0.59 seconds
Started Aug 03 04:24:36 PM PDT 24
Finished Aug 03 04:24:37 PM PDT 24
Peak memory 194908 kb
Host smart-8722e852-32cf-432c-9340-6bd84aec15a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673121472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1673121472
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3498705202
Short name T671
Test name
Test status
Simulation time 50040008 ps
CPU time 0.65 seconds
Started Aug 03 04:24:23 PM PDT 24
Finished Aug 03 04:24:24 PM PDT 24
Peak memory 194960 kb
Host smart-4c4fedad-e284-4d20-905e-5ca049263abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498705202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3498705202
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1783433070
Short name T687
Test name
Test status
Simulation time 109429808 ps
CPU time 0.88 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 198580 kb
Host smart-f2161cd1-f47c-4c1f-b44a-975b0a514caf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783433070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1783433070
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2461210832
Short name T702
Test name
Test status
Simulation time 124339310 ps
CPU time 1.61 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:25:01 PM PDT 24
Peak memory 197356 kb
Host smart-19706bcb-c545-4c05-a7d6-e317d77c8dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461210832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2461210832
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2549040727
Short name T669
Test name
Test status
Simulation time 61466180 ps
CPU time 1.25 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:25 PM PDT 24
Peak memory 196568 kb
Host smart-a548595f-8b74-4ecc-9725-337408f9d4c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549040727 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2549040727
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1245250820
Short name T664
Test name
Test status
Simulation time 202017976 ps
CPU time 0.6 seconds
Started Aug 03 04:24:37 PM PDT 24
Finished Aug 03 04:24:38 PM PDT 24
Peak memory 194996 kb
Host smart-d0527a53-ca26-43b9-a7b1-e4a4488a1012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245250820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1245250820
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.77876314
Short name T682
Test name
Test status
Simulation time 33999240 ps
CPU time 0.6 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:25:04 PM PDT 24
Peak memory 194912 kb
Host smart-45be33e3-5967-4fd0-9424-2adc5ab46a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77876314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.77876314
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1386925407
Short name T741
Test name
Test status
Simulation time 62622446 ps
CPU time 0.83 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:24:46 PM PDT 24
Peak memory 198300 kb
Host smart-ba332522-047c-47c1-8f98-ecd364bafcaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386925407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1386925407
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1785261022
Short name T660
Test name
Test status
Simulation time 97188882 ps
CPU time 1.22 seconds
Started Aug 03 04:24:33 PM PDT 24
Finished Aug 03 04:24:35 PM PDT 24
Peak memory 196268 kb
Host smart-ec06309a-6b98-4f19-9ac1-8a1943c1b1af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785261022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1785261022
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2817486024
Short name T717
Test name
Test status
Simulation time 99649419 ps
CPU time 0.86 seconds
Started Aug 03 04:24:46 PM PDT 24
Finished Aug 03 04:24:47 PM PDT 24
Peak memory 195148 kb
Host smart-ec55383c-3e52-4399-99e0-0f6a5788d8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817486024 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2817486024
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1198160846
Short name T661
Test name
Test status
Simulation time 49323134 ps
CPU time 0.62 seconds
Started Aug 03 04:24:21 PM PDT 24
Finished Aug 03 04:24:27 PM PDT 24
Peak memory 197284 kb
Host smart-6bf9aba9-5369-4fea-b4fd-7ad2f207fda5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198160846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.1198160846
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.521032890
Short name T683
Test name
Test status
Simulation time 37868737 ps
CPU time 0.62 seconds
Started Aug 03 04:24:37 PM PDT 24
Finished Aug 03 04:24:37 PM PDT 24
Peak memory 194952 kb
Host smart-29dc78c8-2715-4fb4-b508-98f9890ab06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521032890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.521032890
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2870925059
Short name T63
Test name
Test status
Simulation time 60347893 ps
CPU time 0.71 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 194960 kb
Host smart-a20f5163-679e-447b-913a-b80afeb14150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870925059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2870925059
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.597868437
Short name T122
Test name
Test status
Simulation time 284507852 ps
CPU time 1.59 seconds
Started Aug 03 04:24:34 PM PDT 24
Finished Aug 03 04:24:35 PM PDT 24
Peak memory 197272 kb
Host smart-4ecb9242-ed80-40bc-97be-b730e3982ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597868437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.597868437
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.898294759
Short name T742
Test name
Test status
Simulation time 419024811 ps
CPU time 1.49 seconds
Started Aug 03 04:25:08 PM PDT 24
Finished Aug 03 04:25:10 PM PDT 24
Peak memory 195204 kb
Host smart-8293f3b0-fbb4-4fda-a24f-a1a691902998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898294759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.
898294759
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1348018389
Short name T650
Test name
Test status
Simulation time 51414134 ps
CPU time 1.15 seconds
Started Aug 03 04:24:40 PM PDT 24
Finished Aug 03 04:24:41 PM PDT 24
Peak memory 196380 kb
Host smart-efe38442-d903-448a-9d74-fd05f36d7024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348018389 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1348018389
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.375630435
Short name T734
Test name
Test status
Simulation time 47852951 ps
CPU time 0.63 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:20 PM PDT 24
Peak memory 194992 kb
Host smart-2aca6453-eac3-4bd7-b774-73e630ce2f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375630435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.375630435
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2333855853
Short name T713
Test name
Test status
Simulation time 21588294 ps
CPU time 0.63 seconds
Started Aug 03 04:24:44 PM PDT 24
Finished Aug 03 04:24:45 PM PDT 24
Peak memory 194864 kb
Host smart-3b64e4f5-4243-4b67-b76c-9cc4dba88be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333855853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2333855853
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2056250122
Short name T747
Test name
Test status
Simulation time 43217163 ps
CPU time 0.87 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:25:06 PM PDT 24
Peak memory 195020 kb
Host smart-e11e2b5a-39cc-46ac-804d-308699b2af33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056250122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2056250122
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2973025755
Short name T726
Test name
Test status
Simulation time 78875558 ps
CPU time 1.86 seconds
Started Aug 03 04:24:39 PM PDT 24
Finished Aug 03 04:24:41 PM PDT 24
Peak memory 196208 kb
Host smart-b72632c7-dbc6-489b-905f-836ec9ec8cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973025755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2973025755
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3952037059
Short name T147
Test name
Test status
Simulation time 292611191 ps
CPU time 1.62 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 200016 kb
Host smart-1ceca1b8-bbe2-4bfd-8efd-5150a0f8aa2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952037059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.3952037059
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.142880989
Short name T95
Test name
Test status
Simulation time 70081869 ps
CPU time 0.75 seconds
Started Aug 03 04:58:29 PM PDT 24
Finished Aug 03 04:58:30 PM PDT 24
Peak memory 199992 kb
Host smart-1018663b-de57-4b48-b6f2-5b0a69e9b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142880989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.142880989
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3029345555
Short name T368
Test name
Test status
Simulation time 30687378 ps
CPU time 0.64 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 197292 kb
Host smart-6763fff0-1f01-458c-8f9a-93e468ef8a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029345555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3029345555
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.2386740566
Short name T264
Test name
Test status
Simulation time 307893967 ps
CPU time 0.97 seconds
Started Aug 03 04:58:26 PM PDT 24
Finished Aug 03 04:58:27 PM PDT 24
Peak memory 198052 kb
Host smart-08e7b704-f539-4584-8173-0fddfb4b9ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386740566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.2386740566
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.562086707
Short name T400
Test name
Test status
Simulation time 61557396 ps
CPU time 0.6 seconds
Started Aug 03 04:58:30 PM PDT 24
Finished Aug 03 04:58:30 PM PDT 24
Peak memory 197356 kb
Host smart-ba325616-be30-4735-bece-360cc0200220
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562086707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.562086707
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.762791391
Short name T399
Test name
Test status
Simulation time 88563834 ps
CPU time 0.61 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:27 PM PDT 24
Peak memory 198108 kb
Host smart-1678e50e-609b-49a2-869f-d7157fbfe810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762791391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.762791391
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.3378694180
Short name T178
Test name
Test status
Simulation time 74261580 ps
CPU time 0.65 seconds
Started Aug 03 04:58:26 PM PDT 24
Finished Aug 03 04:58:26 PM PDT 24
Peak memory 201396 kb
Host smart-8963483a-b88a-4ac9-ba89-28396a15bc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378694180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.3378694180
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3860648758
Short name T256
Test name
Test status
Simulation time 122257167 ps
CPU time 0.76 seconds
Started Aug 03 04:58:21 PM PDT 24
Finished Aug 03 04:58:22 PM PDT 24
Peak memory 199188 kb
Host smart-15ff0a42-eca1-49c5-bf94-5082dda35d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860648758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3860648758
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3455932841
Short name T472
Test name
Test status
Simulation time 513194664 ps
CPU time 0.75 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 209500 kb
Host smart-31f2cd68-9804-4c72-9f4f-f9714d8e1881
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455932841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3455932841
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2578763583
Short name T20
Test name
Test status
Simulation time 384043678 ps
CPU time 1.2 seconds
Started Aug 03 04:58:30 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 217676 kb
Host smart-8bc6b0be-a63e-4b46-b115-44477f01b5b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578763583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2578763583
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2906247496
Short name T594
Test name
Test status
Simulation time 51725381 ps
CPU time 0.86 seconds
Started Aug 03 04:58:28 PM PDT 24
Finished Aug 03 04:58:29 PM PDT 24
Peak memory 199404 kb
Host smart-7a0f9809-2a42-4f5a-8eb8-09fe6bbb7a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906247496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2906247496
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.99325170
Short name T117
Test name
Test status
Simulation time 19364420 ps
CPU time 0.71 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 199212 kb
Host smart-b10de5a0-6cc6-4ec7-a808-16236bb784f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99325170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.99325170
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.187203661
Short name T329
Test name
Test status
Simulation time 53901475 ps
CPU time 0.83 seconds
Started Aug 03 04:58:35 PM PDT 24
Finished Aug 03 04:58:36 PM PDT 24
Peak memory 198560 kb
Host smart-328ee3d1-0e3a-4de1-9062-66e2619be135
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187203661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disab
le_rom_integrity_check.187203661
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1976371337
Short name T263
Test name
Test status
Simulation time 32128970 ps
CPU time 0.6 seconds
Started Aug 03 04:58:32 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 197344 kb
Host smart-70c32e3a-d9b8-4148-b1e3-d28c30cb216f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976371337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1976371337
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2970221425
Short name T550
Test name
Test status
Simulation time 636512086 ps
CPU time 0.96 seconds
Started Aug 03 04:58:33 PM PDT 24
Finished Aug 03 04:58:34 PM PDT 24
Peak memory 198020 kb
Host smart-0b111abc-166f-4c23-b7e2-94f182cada2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970221425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2970221425
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.286130444
Short name T469
Test name
Test status
Simulation time 55945222 ps
CPU time 0.63 seconds
Started Aug 03 04:58:35 PM PDT 24
Finished Aug 03 04:58:35 PM PDT 24
Peak memory 197984 kb
Host smart-ce4e7c8e-05c5-4e94-8c8b-a375f93c65dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286130444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.286130444
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1726580482
Short name T387
Test name
Test status
Simulation time 76330730 ps
CPU time 0.62 seconds
Started Aug 03 04:58:32 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 198564 kb
Host smart-84143233-c4e1-4d52-81da-ded8318a8a03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726580482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1726580482
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1320100289
Short name T201
Test name
Test status
Simulation time 62330588 ps
CPU time 0.66 seconds
Started Aug 03 04:58:34 PM PDT 24
Finished Aug 03 04:58:35 PM PDT 24
Peak memory 201384 kb
Host smart-23b1298c-aad4-49dd-87c3-83a9d9963bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320100289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1320100289
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2162512241
Short name T611
Test name
Test status
Simulation time 36341462 ps
CPU time 0.69 seconds
Started Aug 03 04:58:26 PM PDT 24
Finished Aug 03 04:58:27 PM PDT 24
Peak memory 199176 kb
Host smart-33fd0227-7d89-4916-b2a0-24f9dc2d894a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162512241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2162512241
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.3391940686
Short name T315
Test name
Test status
Simulation time 180714472 ps
CPU time 0.77 seconds
Started Aug 03 04:58:34 PM PDT 24
Finished Aug 03 04:58:35 PM PDT 24
Peak memory 209456 kb
Host smart-ebb0085c-d0b4-46f1-9184-2b3576cf8b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391940686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.3391940686
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3717759009
Short name T308
Test name
Test status
Simulation time 52477087 ps
CPU time 0.81 seconds
Started Aug 03 04:58:33 PM PDT 24
Finished Aug 03 04:58:34 PM PDT 24
Peak memory 198104 kb
Host smart-bf30a8b5-d446-4590-a60e-ca10b06ebea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717759009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3717759009
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1130246596
Short name T437
Test name
Test status
Simulation time 62948021 ps
CPU time 0.64 seconds
Started Aug 03 04:58:27 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 198560 kb
Host smart-e0b31bde-f5e0-4f13-9efb-f4291832fa7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130246596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1130246596
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3217983255
Short name T416
Test name
Test status
Simulation time 132980527 ps
CPU time 0.67 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 198640 kb
Host smart-74fa5b39-525a-4f30-ac77-a2b2083719a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217983255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3217983255
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2689860443
Short name T41
Test name
Test status
Simulation time 88912153 ps
CPU time 0.66 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 198596 kb
Host smart-ad97e82e-509f-404b-9376-06d447dab525
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689860443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2689860443
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.735578993
Short name T528
Test name
Test status
Simulation time 37519094 ps
CPU time 0.62 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 197956 kb
Host smart-f9c3c999-eb27-4aa7-895d-e356bfaf6a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735578993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_
malfunc.735578993
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3788444816
Short name T266
Test name
Test status
Simulation time 1004393647 ps
CPU time 0.99 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:20 PM PDT 24
Peak memory 197504 kb
Host smart-3798b42f-d5f7-4b7e-9e89-b264bf8f1d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788444816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3788444816
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.3495475821
Short name T306
Test name
Test status
Simulation time 59496789 ps
CPU time 0.62 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 198124 kb
Host smart-80167eb9-903a-4504-8e7a-eb857a239a77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495475821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3495475821
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.4223817561
Short name T283
Test name
Test status
Simulation time 33563412 ps
CPU time 0.63 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 198112 kb
Host smart-d69d516b-bcb1-42a3-b387-c259398a501f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223817561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.4223817561
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1990272924
Short name T186
Test name
Test status
Simulation time 44976542 ps
CPU time 0.7 seconds
Started Aug 03 04:59:13 PM PDT 24
Finished Aug 03 04:59:14 PM PDT 24
Peak memory 201304 kb
Host smart-bb224196-f1dc-4057-9480-2f6b71648e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990272924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1990272924
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2707690641
Short name T332
Test name
Test status
Simulation time 143331841 ps
CPU time 0.74 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 199060 kb
Host smart-88bf1ab7-eccb-4968-ab53-d42ce4b82da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707690641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2707690641
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.818746565
Short name T532
Test name
Test status
Simulation time 110760214 ps
CPU time 1.07 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 209464 kb
Host smart-2c67c46e-901b-4b67-9111-9099a75d15ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818746565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.818746565
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1330698400
Short name T500
Test name
Test status
Simulation time 158789383 ps
CPU time 0.88 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 199196 kb
Host smart-e6c9f27c-8a0d-48c2-a100-97d1ae13d149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330698400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1330698400
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1627711292
Short name T284
Test name
Test status
Simulation time 31831421 ps
CPU time 0.72 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 199352 kb
Host smart-5d4a060b-26b3-4f1a-9549-7a8b35af8d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627711292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1627711292
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3066776522
Short name T88
Test name
Test status
Simulation time 23776673 ps
CPU time 0.66 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:17 PM PDT 24
Peak memory 198608 kb
Host smart-5b42f43d-57a9-4d60-91bb-53aaf0704773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066776522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3066776522
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.2259203843
Short name T366
Test name
Test status
Simulation time 56386627 ps
CPU time 0.76 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 199124 kb
Host smart-47d9b00c-c8f0-4134-835c-3524976d680c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259203843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.2259203843
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1188063771
Short name T584
Test name
Test status
Simulation time 33730001 ps
CPU time 0.61 seconds
Started Aug 03 04:59:21 PM PDT 24
Finished Aug 03 04:59:22 PM PDT 24
Peak memory 197108 kb
Host smart-fc1929c9-a7b5-4353-8923-f0b2fc7997f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188063771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1188063771
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.685287536
Short name T252
Test name
Test status
Simulation time 158509259 ps
CPU time 1.07 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:19 PM PDT 24
Peak memory 198420 kb
Host smart-1e2ed291-45e3-4dc0-b1b9-7217377ba738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685287536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.685287536
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1190502752
Short name T257
Test name
Test status
Simulation time 62031711 ps
CPU time 0.68 seconds
Started Aug 03 04:59:16 PM PDT 24
Finished Aug 03 04:59:17 PM PDT 24
Peak memory 197356 kb
Host smart-fbf00d75-2651-420f-ba34-9eac8efd7a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190502752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1190502752
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.602935179
Short name T569
Test name
Test status
Simulation time 39053463 ps
CPU time 0.6 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 198288 kb
Host smart-ca317f8f-a324-40c7-b4d3-0657c51efa60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602935179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.602935179
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1102632198
Short name T181
Test name
Test status
Simulation time 213719570 ps
CPU time 0.72 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 201388 kb
Host smart-c4014a9b-dc24-4c55-8b86-a15504254144
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102632198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1102632198
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.1703159685
Short name T492
Test name
Test status
Simulation time 55719173 ps
CPU time 0.8 seconds
Started Aug 03 04:59:13 PM PDT 24
Finished Aug 03 04:59:14 PM PDT 24
Peak memory 198332 kb
Host smart-56841022-8d32-4fa6-9bc5-42fdddeda83a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703159685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1703159685
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2684113100
Short name T222
Test name
Test status
Simulation time 127252794 ps
CPU time 0.88 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 209480 kb
Host smart-8e903586-b957-4069-843e-e3182cac1113
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684113100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2684113100
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2046865576
Short name T203
Test name
Test status
Simulation time 64459078 ps
CPU time 0.59 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:19 PM PDT 24
Peak memory 198176 kb
Host smart-207f228e-8854-42bd-9a9a-af60bc091b63
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046865576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_
cm_ctrl_config_regwen.2046865576
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3009945684
Short name T493
Test name
Test status
Simulation time 72622310 ps
CPU time 0.9 seconds
Started Aug 03 04:59:15 PM PDT 24
Finished Aug 03 04:59:16 PM PDT 24
Peak memory 199400 kb
Host smart-dfeb5e2c-a10c-4e92-855f-2b849766e412
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009945684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3009945684
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2014956307
Short name T395
Test name
Test status
Simulation time 28441421 ps
CPU time 0.68 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 198500 kb
Host smart-cf2d578b-8f13-4fd5-98ac-9993c644d47f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014956307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2014956307
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.1189403448
Short name T16
Test name
Test status
Simulation time 31585809 ps
CPU time 1.09 seconds
Started Aug 03 04:59:21 PM PDT 24
Finished Aug 03 04:59:22 PM PDT 24
Peak memory 200892 kb
Host smart-fb51c4ae-4ee8-4938-8ad6-20d17d141252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189403448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1189403448
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3819381879
Short name T30
Test name
Test status
Simulation time 93284446 ps
CPU time 0.66 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 198340 kb
Host smart-c171ef1e-ce44-41be-973c-5d8d777e187d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819381879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3819381879
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3220276683
Short name T614
Test name
Test status
Simulation time 38550039 ps
CPU time 0.59 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 198044 kb
Host smart-0cf6ef42-bfcb-4537-b186-a6af887ab46c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220276683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3220276683
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3021589507
Short name T571
Test name
Test status
Simulation time 2509598221 ps
CPU time 0.93 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:19 PM PDT 24
Peak memory 198340 kb
Host smart-c8aa8116-7f8a-44f0-9168-ac614b4fb302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021589507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3021589507
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3888453289
Short name T422
Test name
Test status
Simulation time 37178155 ps
CPU time 0.6 seconds
Started Aug 03 04:59:19 PM PDT 24
Finished Aug 03 04:59:20 PM PDT 24
Peak memory 198376 kb
Host smart-56fb9531-3379-4ca6-a466-cd2d35fced10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888453289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3888453289
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.1495091915
Short name T182
Test name
Test status
Simulation time 50027135 ps
CPU time 0.73 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 201436 kb
Host smart-d11891bb-5388-4aeb-b3d0-e49842ca73c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495091915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.1495091915
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.3679543252
Short name T291
Test name
Test status
Simulation time 59245139 ps
CPU time 0.67 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 199152 kb
Host smart-023fe9e0-0f4b-4e0a-ac92-f3db27ef3d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679543252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.3679543252
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3081016053
Short name T572
Test name
Test status
Simulation time 89200952 ps
CPU time 0.86 seconds
Started Aug 03 04:59:19 PM PDT 24
Finished Aug 03 04:59:20 PM PDT 24
Peak memory 209564 kb
Host smart-943172aa-68e8-4a03-bcc0-dea492fadf33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081016053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3081016053
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3169459537
Short name T260
Test name
Test status
Simulation time 75665356 ps
CPU time 0.79 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 198036 kb
Host smart-4228187e-a5b1-491e-9a61-a4ca2f0c1578
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169459537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3169459537
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1568601303
Short name T562
Test name
Test status
Simulation time 55652908 ps
CPU time 0.68 seconds
Started Aug 03 04:59:17 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 198420 kb
Host smart-91073d5a-4828-4162-8a38-21cf795da2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568601303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1568601303
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.3038431336
Short name T513
Test name
Test status
Simulation time 30104352 ps
CPU time 0.99 seconds
Started Aug 03 04:59:25 PM PDT 24
Finished Aug 03 04:59:26 PM PDT 24
Peak memory 200916 kb
Host smart-3aee86d1-499d-4721-8dcf-486420741511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038431336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3038431336
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.353615516
Short name T22
Test name
Test status
Simulation time 28502417 ps
CPU time 0.67 seconds
Started Aug 03 04:59:26 PM PDT 24
Finished Aug 03 04:59:27 PM PDT 24
Peak memory 197308 kb
Host smart-18f9ae90-270b-43b3-ad36-dfcd93f74794
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353615516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.353615516
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.291453584
Short name T593
Test name
Test status
Simulation time 611407110 ps
CPU time 0.93 seconds
Started Aug 03 04:59:28 PM PDT 24
Finished Aug 03 04:59:29 PM PDT 24
Peak memory 198088 kb
Host smart-6ec0b558-e658-46ad-a5ff-c2cf33a4a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291453584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.291453584
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3896556051
Short name T350
Test name
Test status
Simulation time 56597392 ps
CPU time 0.67 seconds
Started Aug 03 04:59:23 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 198060 kb
Host smart-7f50a42b-2a29-43db-ba3a-6b2d6bf380c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896556051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3896556051
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.1828050773
Short name T441
Test name
Test status
Simulation time 84273228 ps
CPU time 0.58 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:22 PM PDT 24
Peak memory 198116 kb
Host smart-e079662b-717d-4ff7-90c6-1c0fa710e19b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828050773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1828050773
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2795162131
Short name T168
Test name
Test status
Simulation time 43353534 ps
CPU time 0.69 seconds
Started Aug 03 04:59:23 PM PDT 24
Finished Aug 03 04:59:24 PM PDT 24
Peak memory 201376 kb
Host smart-28931f01-e010-40a7-90cb-2860571f41fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795162131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2795162131
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2077538799
Short name T281
Test name
Test status
Simulation time 58789202 ps
CPU time 0.84 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 199156 kb
Host smart-ef77ac16-e17a-48f8-b24c-326a7440acd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077538799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2077538799
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2614263511
Short name T570
Test name
Test status
Simulation time 130014173 ps
CPU time 0.83 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 209456 kb
Host smart-cd35fce6-892e-49a9-9816-61cb1634cbd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614263511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2614263511
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.141225876
Short name T566
Test name
Test status
Simulation time 119241709 ps
CPU time 0.85 seconds
Started Aug 03 04:59:22 PM PDT 24
Finished Aug 03 04:59:23 PM PDT 24
Peak memory 199200 kb
Host smart-0a6edd6c-030b-43a7-a6e3-5cf52808c3f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141225876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.141225876
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1678395830
Short name T221
Test name
Test status
Simulation time 58558598 ps
CPU time 0.64 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198552 kb
Host smart-d2100bf7-810f-403a-8aef-82bcb78da2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678395830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1678395830
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1231346605
Short name T564
Test name
Test status
Simulation time 28260575 ps
CPU time 0.62 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198564 kb
Host smart-77401dc1-db2c-4dc2-bb13-9d9fb87ae670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231346605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1231346605
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.352176113
Short name T208
Test name
Test status
Simulation time 158412248 ps
CPU time 0.66 seconds
Started Aug 03 04:59:23 PM PDT 24
Finished Aug 03 04:59:24 PM PDT 24
Peak memory 198612 kb
Host smart-dda36040-5a2d-4818-a91d-e6f1f0f00546
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352176113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disa
ble_rom_integrity_check.352176113
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.4040587201
Short name T476
Test name
Test status
Simulation time 38801490 ps
CPU time 0.59 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198012 kb
Host smart-0b39f6e8-cfef-421d-a846-b724558adac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040587201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.4040587201
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.3174769122
Short name T619
Test name
Test status
Simulation time 623713077 ps
CPU time 0.97 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198368 kb
Host smart-f99fc7be-e008-41e7-b68f-b6f36049862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174769122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3174769122
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.938334743
Short name T4
Test name
Test status
Simulation time 32863120 ps
CPU time 0.64 seconds
Started Aug 03 04:59:24 PM PDT 24
Finished Aug 03 04:59:25 PM PDT 24
Peak memory 198152 kb
Host smart-7d6e38cf-f228-49d3-b515-94f196df4329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938334743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.938334743
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.2861650254
Short name T445
Test name
Test status
Simulation time 37916507 ps
CPU time 0.64 seconds
Started Aug 03 04:59:23 PM PDT 24
Finished Aug 03 04:59:24 PM PDT 24
Peak memory 198068 kb
Host smart-1eb16bea-8cc0-4636-b5a3-859529e9421c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861650254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2861650254
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.317910044
Short name T426
Test name
Test status
Simulation time 52345577 ps
CPU time 0.67 seconds
Started Aug 03 04:59:23 PM PDT 24
Finished Aug 03 04:59:24 PM PDT 24
Peak memory 199136 kb
Host smart-222bfc32-5dec-489e-bbdc-982e2a0c352d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317910044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.317910044
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2971965154
Short name T362
Test name
Test status
Simulation time 58661108 ps
CPU time 0.89 seconds
Started Aug 03 04:59:25 PM PDT 24
Finished Aug 03 04:59:26 PM PDT 24
Peak memory 199404 kb
Host smart-6594f5ce-98f8-45d5-8491-8578b87179a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971965154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2971965154
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3376519156
Short name T511
Test name
Test status
Simulation time 193919077 ps
CPU time 0.89 seconds
Started Aug 03 04:59:33 PM PDT 24
Finished Aug 03 04:59:34 PM PDT 24
Peak memory 200216 kb
Host smart-13db92e0-1bdd-48fc-b1e3-bf501f4f609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376519156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3376519156
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.3513084923
Short name T154
Test name
Test status
Simulation time 50049738 ps
CPU time 0.78 seconds
Started Aug 03 04:59:31 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 198528 kb
Host smart-b8757850-8ea1-4747-9ecd-02282a57cba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513084923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.3513084923
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2808667498
Short name T411
Test name
Test status
Simulation time 39546727 ps
CPU time 0.61 seconds
Started Aug 03 04:59:32 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 197976 kb
Host smart-2820e64c-9102-4c4e-b639-5d3e903408fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808667498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2808667498
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2807325546
Short name T126
Test name
Test status
Simulation time 161274480 ps
CPU time 0.94 seconds
Started Aug 03 04:59:30 PM PDT 24
Finished Aug 03 04:59:31 PM PDT 24
Peak memory 198108 kb
Host smart-305280f3-dd65-4e21-971e-e395b96b51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807325546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2807325546
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.651080198
Short name T347
Test name
Test status
Simulation time 51848898 ps
CPU time 0.61 seconds
Started Aug 03 04:59:31 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 198044 kb
Host smart-17ea04ba-cdf8-4161-9435-85ea21c3f853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651080198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.651080198
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.2728842141
Short name T563
Test name
Test status
Simulation time 80069531 ps
CPU time 0.63 seconds
Started Aug 03 04:59:32 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 198076 kb
Host smart-24f28e56-0a37-48c5-8ffa-e3ea84799df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728842141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.2728842141
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.819537956
Short name T428
Test name
Test status
Simulation time 51331502 ps
CPU time 0.67 seconds
Started Aug 03 04:59:37 PM PDT 24
Finished Aug 03 04:59:38 PM PDT 24
Peak memory 201348 kb
Host smart-96995c95-2004-4b9b-ab3a-c1c553ce466e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819537956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invali
d.819537956
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2487587882
Short name T460
Test name
Test status
Simulation time 38207661 ps
CPU time 0.64 seconds
Started Aug 03 04:59:31 PM PDT 24
Finished Aug 03 04:59:31 PM PDT 24
Peak memory 198320 kb
Host smart-92d192be-e5b6-4109-bcda-743fd1a36062
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487587882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2487587882
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.3215370196
Short name T309
Test name
Test status
Simulation time 162711260 ps
CPU time 0.82 seconds
Started Aug 03 04:59:29 PM PDT 24
Finished Aug 03 04:59:30 PM PDT 24
Peak memory 209480 kb
Host smart-c8265d1b-bf40-4eac-be0f-de29b223ca85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215370196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.3215370196
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3752865547
Short name T390
Test name
Test status
Simulation time 85566410 ps
CPU time 0.75 seconds
Started Aug 03 04:59:36 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 198096 kb
Host smart-a32a62ce-ba5d-4b41-b679-c4c08423434e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752865547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3752865547
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3936231824
Short name T82
Test name
Test status
Simulation time 56888758 ps
CPU time 0.65 seconds
Started Aug 03 04:59:32 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 198416 kb
Host smart-b59243f4-292c-4f69-bd6f-2b1c7c4f01f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936231824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3936231824
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.1234302459
Short name T213
Test name
Test status
Simulation time 60737311 ps
CPU time 0.63 seconds
Started Aug 03 04:59:30 PM PDT 24
Finished Aug 03 04:59:31 PM PDT 24
Peak memory 198004 kb
Host smart-b1e91310-3baa-44d1-a5b2-74ab97675a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234302459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1234302459
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1954674644
Short name T606
Test name
Test status
Simulation time 57416642 ps
CPU time 0.86 seconds
Started Aug 03 04:59:32 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 200216 kb
Host smart-8b9d8bac-7c2f-4b04-9d32-029789e8e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954674644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1954674644
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2479702616
Short name T435
Test name
Test status
Simulation time 32860882 ps
CPU time 0.63 seconds
Started Aug 03 04:59:33 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 198044 kb
Host smart-3b693590-4b79-4eed-aa10-db1bc0231b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479702616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2479702616
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3094590774
Short name T622
Test name
Test status
Simulation time 630022134 ps
CPU time 0.98 seconds
Started Aug 03 04:59:33 PM PDT 24
Finished Aug 03 04:59:34 PM PDT 24
Peak memory 198128 kb
Host smart-c9140a37-1d63-40b9-a269-a9bc1951c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094590774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3094590774
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.2837664372
Short name T412
Test name
Test status
Simulation time 27558984 ps
CPU time 0.61 seconds
Started Aug 03 04:59:34 PM PDT 24
Finished Aug 03 04:59:34 PM PDT 24
Peak memory 198084 kb
Host smart-52d95ea2-9670-459c-b485-9b3175506847
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837664372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2837664372
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3807887960
Short name T464
Test name
Test status
Simulation time 23078263 ps
CPU time 0.6 seconds
Started Aug 03 04:59:38 PM PDT 24
Finished Aug 03 04:59:38 PM PDT 24
Peak memory 198364 kb
Host smart-bbe135a6-a9f4-49d3-b39b-6ff2d86db51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807887960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3807887960
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.4235867017
Short name T259
Test name
Test status
Simulation time 53733099 ps
CPU time 0.65 seconds
Started Aug 03 04:59:30 PM PDT 24
Finished Aug 03 04:59:30 PM PDT 24
Peak memory 198188 kb
Host smart-bfd40d45-7f50-4aec-8243-347016dc5c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235867017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.4235867017
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.1178781189
Short name T3
Test name
Test status
Simulation time 156549287 ps
CPU time 0.77 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:43 PM PDT 24
Peak memory 209444 kb
Host smart-c68b04cf-6d00-4102-8719-45815a685d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178781189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.1178781189
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1822634043
Short name T240
Test name
Test status
Simulation time 103468177 ps
CPU time 0.81 seconds
Started Aug 03 04:59:30 PM PDT 24
Finished Aug 03 04:59:31 PM PDT 24
Peak memory 199140 kb
Host smart-2f1ce0cb-468d-46f2-a74d-5529d1c6c79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822634043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1822634043
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2484498883
Short name T83
Test name
Test status
Simulation time 34382919 ps
CPU time 0.61 seconds
Started Aug 03 04:59:27 PM PDT 24
Finished Aug 03 04:59:28 PM PDT 24
Peak memory 198528 kb
Host smart-67e1d0a3-e754-4773-bd25-ba9741e54fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484498883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2484498883
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.3450563847
Short name T360
Test name
Test status
Simulation time 25706712 ps
CPU time 0.79 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:42 PM PDT 24
Peak memory 199924 kb
Host smart-6272c1b3-4c2b-4d06-8351-88ea0483234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450563847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3450563847
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3138684878
Short name T613
Test name
Test status
Simulation time 59548729 ps
CPU time 0.8 seconds
Started Aug 03 04:59:39 PM PDT 24
Finished Aug 03 04:59:39 PM PDT 24
Peak memory 198544 kb
Host smart-c8373ba4-7aef-4784-b8ef-abaecce422b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138684878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3138684878
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.4027723496
Short name T495
Test name
Test status
Simulation time 38442123 ps
CPU time 0.6 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:35 PM PDT 24
Peak memory 198036 kb
Host smart-0ff94e1e-78ee-46f7-b426-577071e986ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027723496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.4027723496
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.2083500682
Short name T131
Test name
Test status
Simulation time 2961457527 ps
CPU time 1.02 seconds
Started Aug 03 04:59:36 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 198204 kb
Host smart-5bc214fd-7776-406e-9d6d-208c61715db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083500682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2083500682
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3263482486
Short name T396
Test name
Test status
Simulation time 68681276 ps
CPU time 0.59 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:36 PM PDT 24
Peak memory 198060 kb
Host smart-3ad53e22-a805-4678-ada4-a3f5620ace30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263482486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3263482486
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.1249690981
Short name T535
Test name
Test status
Simulation time 24816896 ps
CPU time 0.61 seconds
Started Aug 03 04:59:36 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 198372 kb
Host smart-1c8ac856-517f-4e09-9a65-a28b820e154c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249690981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1249690981
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3857443925
Short name T90
Test name
Test status
Simulation time 194274919 ps
CPU time 0.63 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 201372 kb
Host smart-287cfd3d-500c-4aca-8e1f-1cdf47fcb78a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857443925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3857443925
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.1215268629
Short name T53
Test name
Test status
Simulation time 53408347 ps
CPU time 0.69 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:36 PM PDT 24
Peak memory 198272 kb
Host smart-ecaf57c5-acf2-4d91-b558-2223401ed536
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215268629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.1215268629
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3616832408
Short name T440
Test name
Test status
Simulation time 60187132 ps
CPU time 0.66 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:35 PM PDT 24
Peak memory 198288 kb
Host smart-7ec904cd-82c9-4289-9bd8-13fd53cf60ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616832408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3616832408
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2143709333
Short name T608
Test name
Test status
Simulation time 125474129 ps
CPU time 0.81 seconds
Started Aug 03 04:59:36 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 209508 kb
Host smart-9a6c3386-9724-4bc9-8958-cebfa8ba6821
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143709333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2143709333
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1273622829
Short name T631
Test name
Test status
Simulation time 102732485 ps
CPU time 0.74 seconds
Started Aug 03 04:59:37 PM PDT 24
Finished Aug 03 04:59:38 PM PDT 24
Peak memory 199160 kb
Host smart-3724c975-fe73-4dd0-bac4-6e03db26f3af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273622829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1273622829
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.973496507
Short name T311
Test name
Test status
Simulation time 41594905 ps
CPU time 0.66 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 199396 kb
Host smart-f9f57599-82f4-45c5-9475-5db86059b6f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973496507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.973496507
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3413876450
Short name T363
Test name
Test status
Simulation time 60362448 ps
CPU time 0.66 seconds
Started Aug 03 04:59:37 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 198688 kb
Host smart-d65c6bab-460b-493b-b30c-617a6576759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413876450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3413876450
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2238702138
Short name T634
Test name
Test status
Simulation time 61418273 ps
CPU time 0.69 seconds
Started Aug 03 04:59:51 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 199228 kb
Host smart-78d3098e-8798-44aa-a40f-5b31bc9adb43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238702138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2238702138
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.394836452
Short name T253
Test name
Test status
Simulation time 30688092 ps
CPU time 0.64 seconds
Started Aug 03 04:59:37 PM PDT 24
Finished Aug 03 04:59:37 PM PDT 24
Peak memory 197948 kb
Host smart-4cf5353f-b0b5-4a7a-b90a-aea7471cb2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394836452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.394836452
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.448527969
Short name T340
Test name
Test status
Simulation time 323548675 ps
CPU time 1.02 seconds
Started Aug 03 04:59:51 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 198136 kb
Host smart-14ea9689-dd62-4b8d-a642-ac24e482a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448527969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.448527969
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2079867024
Short name T602
Test name
Test status
Simulation time 56111159 ps
CPU time 0.59 seconds
Started Aug 03 04:59:40 PM PDT 24
Finished Aug 03 04:59:41 PM PDT 24
Peak memory 197996 kb
Host smart-ebe8b36b-ae00-4518-83cd-2632127cbfc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079867024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2079867024
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1770817108
Short name T633
Test name
Test status
Simulation time 36314917 ps
CPU time 0.64 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 198448 kb
Host smart-cf772b7f-8e86-401d-9e35-dc29be6d6f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770817108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1770817108
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.1217921260
Short name T394
Test name
Test status
Simulation time 33201370 ps
CPU time 0.65 seconds
Started Aug 03 04:59:35 PM PDT 24
Finished Aug 03 04:59:36 PM PDT 24
Peak memory 199128 kb
Host smart-7bead912-f323-49b8-8f48-63f136c2e395
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217921260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1217921260
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2942763886
Short name T449
Test name
Test status
Simulation time 102338047 ps
CPU time 1.07 seconds
Started Aug 03 04:59:39 PM PDT 24
Finished Aug 03 04:59:40 PM PDT 24
Peak memory 209504 kb
Host smart-85a7d0e3-80a1-41a4-b579-fb2dc225c8bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942763886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2942763886
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1368731489
Short name T318
Test name
Test status
Simulation time 136752467 ps
CPU time 0.84 seconds
Started Aug 03 04:59:38 PM PDT 24
Finished Aug 03 04:59:39 PM PDT 24
Peak memory 199168 kb
Host smart-857ce200-91cc-4bb1-a118-f271370f3770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368731489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1368731489
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3454917799
Short name T386
Test name
Test status
Simulation time 129344561 ps
CPU time 0.63 seconds
Started Aug 03 04:59:34 PM PDT 24
Finished Aug 03 04:59:35 PM PDT 24
Peak memory 198468 kb
Host smart-02ea4e58-7a75-40f1-9ac7-c0349832e8d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454917799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3454917799
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.712396469
Short name T358
Test name
Test status
Simulation time 23052016 ps
CPU time 0.62 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198568 kb
Host smart-857c9fc7-5df4-412e-a1f7-1adeb358df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712396469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.712396469
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3938506137
Short name T161
Test name
Test status
Simulation time 60788304 ps
CPU time 0.72 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:53 PM PDT 24
Peak memory 198428 kb
Host smart-b799e354-04bd-43aa-9e06-47d7691d4ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938506137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.3938506137
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2292040035
Short name T130
Test name
Test status
Simulation time 45206223 ps
CPU time 0.58 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198060 kb
Host smart-07c1517b-b01a-431f-b761-ae5f232a6029
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292040035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2292040035
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.3700005181
Short name T540
Test name
Test status
Simulation time 584268332 ps
CPU time 0.99 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198056 kb
Host smart-7536a311-be98-4e64-a741-89b3d6a20a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700005181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3700005181
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1626036750
Short name T600
Test name
Test status
Simulation time 46178417 ps
CPU time 0.66 seconds
Started Aug 03 04:59:41 PM PDT 24
Finished Aug 03 04:59:42 PM PDT 24
Peak memory 198072 kb
Host smart-81671be3-1167-4597-a640-5f80256b8e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626036750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1626036750
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.238038954
Short name T228
Test name
Test status
Simulation time 178664534 ps
CPU time 0.64 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198396 kb
Host smart-d17b340b-75ce-488d-97a9-dffb6dc29263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238038954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.238038954
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1801457136
Short name T195
Test name
Test status
Simulation time 148229891 ps
CPU time 0.64 seconds
Started Aug 03 04:59:45 PM PDT 24
Finished Aug 03 04:59:46 PM PDT 24
Peak memory 201296 kb
Host smart-aad58749-6a81-4533-bc52-210b394780d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801457136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1801457136
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2159161788
Short name T331
Test name
Test status
Simulation time 220315989 ps
CPU time 0.75 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198440 kb
Host smart-d5b62af2-ca9b-4e88-8a5b-431fd16fd6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159161788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2159161788
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.2805190348
Short name T223
Test name
Test status
Simulation time 111440531 ps
CPU time 0.97 seconds
Started Aug 03 04:59:40 PM PDT 24
Finished Aug 03 04:59:41 PM PDT 24
Peak memory 209536 kb
Host smart-9a57d90b-4311-427e-82bb-5cf7f270c232
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805190348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2805190348
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2175865521
Short name T509
Test name
Test status
Simulation time 61430960 ps
CPU time 0.85 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198296 kb
Host smart-486ecf99-ca30-4bd2-ab79-12c72128ac30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175865521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2175865521
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3251161785
Short name T313
Test name
Test status
Simulation time 77888653 ps
CPU time 0.62 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:42 PM PDT 24
Peak memory 198488 kb
Host smart-83703a1f-81b8-49ed-8223-0f92eaf1fe09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251161785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3251161785
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.241920856
Short name T461
Test name
Test status
Simulation time 49865606 ps
CPU time 0.63 seconds
Started Aug 03 04:58:43 PM PDT 24
Finished Aug 03 04:58:44 PM PDT 24
Peak memory 198640 kb
Host smart-177da0ec-0edf-4bc4-a7e0-5cacc13acfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241920856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.241920856
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2430718398
Short name T423
Test name
Test status
Simulation time 40648662 ps
CPU time 0.58 seconds
Started Aug 03 04:58:41 PM PDT 24
Finished Aug 03 04:58:42 PM PDT 24
Peak memory 198004 kb
Host smart-03441e1c-684b-4c91-a291-95ff04c16bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430718398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.2430718398
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.1787675796
Short name T220
Test name
Test status
Simulation time 713255974 ps
CPU time 1.02 seconds
Started Aug 03 04:58:44 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 198384 kb
Host smart-285b3d78-349c-4607-a88a-336bc8bb8945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787675796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1787675796
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.2196180079
Short name T237
Test name
Test status
Simulation time 38740941 ps
CPU time 0.59 seconds
Started Aug 03 04:58:42 PM PDT 24
Finished Aug 03 04:58:43 PM PDT 24
Peak memory 197316 kb
Host smart-cc411eba-d454-4c04-bb77-fb4e5d34721b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196180079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2196180079
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1764035406
Short name T409
Test name
Test status
Simulation time 59733113 ps
CPU time 0.58 seconds
Started Aug 03 04:58:39 PM PDT 24
Finished Aug 03 04:58:40 PM PDT 24
Peak memory 198408 kb
Host smart-eda910ae-cd2c-4ddb-b573-cde3680287fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764035406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1764035406
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.408553678
Short name T627
Test name
Test status
Simulation time 40242765 ps
CPU time 0.62 seconds
Started Aug 03 04:58:32 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 198280 kb
Host smart-eda18c74-e005-476c-984b-8cd0c2378f3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408553678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.408553678
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.937741
Short name T537
Test name
Test status
Simulation time 157277874 ps
CPU time 0.8 seconds
Started Aug 03 04:58:41 PM PDT 24
Finished Aug 03 04:58:42 PM PDT 24
Peak memory 209508 kb
Host smart-d21b4782-1cdf-41ac-bf72-3c61f2f500cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.937741
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.2903305796
Short name T33
Test name
Test status
Simulation time 740144954 ps
CPU time 1.81 seconds
Started Aug 03 04:58:41 PM PDT 24
Finished Aug 03 04:58:43 PM PDT 24
Peak memory 218072 kb
Host smart-7752c0a3-a0ac-4fd5-8d8f-db22e369b0be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903305796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2903305796
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1855478579
Short name T385
Test name
Test status
Simulation time 50503666 ps
CPU time 0.76 seconds
Started Aug 03 04:58:41 PM PDT 24
Finished Aug 03 04:58:42 PM PDT 24
Peak memory 198096 kb
Host smart-fa4082e8-4ff2-4ffc-874d-5b51aea26666
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855478579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1855478579
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3155001973
Short name T2
Test name
Test status
Simulation time 66576047 ps
CPU time 0.62 seconds
Started Aug 03 04:58:32 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 198524 kb
Host smart-0a87bcd5-3a8d-4937-a207-50cf22a54fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155001973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3155001973
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.3110736834
Short name T487
Test name
Test status
Simulation time 127176609 ps
CPU time 0.8 seconds
Started Aug 03 04:58:39 PM PDT 24
Finished Aug 03 04:58:40 PM PDT 24
Peak memory 198888 kb
Host smart-aef05617-302a-462f-969d-65784fb4d707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110736834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3110736834
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.143535127
Short name T370
Test name
Test status
Simulation time 47706614 ps
CPU time 0.63 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198660 kb
Host smart-620804b8-c6c3-4c12-b6dd-f78018f4173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143535127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.143535127
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1962391470
Short name T466
Test name
Test status
Simulation time 62162154 ps
CPU time 0.81 seconds
Started Aug 03 04:59:45 PM PDT 24
Finished Aug 03 04:59:46 PM PDT 24
Peak memory 199112 kb
Host smart-cea94fa9-e409-468c-9ba6-4751b5da68f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962391470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1962391470
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3010341975
Short name T601
Test name
Test status
Simulation time 29383325 ps
CPU time 0.68 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198028 kb
Host smart-11da6b41-24f7-4306-ba9b-ea7ae67a1021
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010341975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3010341975
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2370508371
Short name T604
Test name
Test status
Simulation time 684947512 ps
CPU time 0.97 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198120 kb
Host smart-83ea08f4-8288-460d-8b9e-6377eab3f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370508371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2370508371
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.971523014
Short name T474
Test name
Test status
Simulation time 46626827 ps
CPU time 0.59 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:43 PM PDT 24
Peak memory 198064 kb
Host smart-09a4bdc6-0b35-4982-ac97-ffee748462e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971523014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.971523014
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2814760761
Short name T297
Test name
Test status
Simulation time 78455764 ps
CPU time 0.62 seconds
Started Aug 03 04:59:44 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198128 kb
Host smart-3a3843e9-6b9c-4073-9be1-3e021708b64e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814760761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2814760761
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2785261455
Short name T163
Test name
Test status
Simulation time 41346960 ps
CPU time 0.71 seconds
Started Aug 03 04:59:40 PM PDT 24
Finished Aug 03 04:59:40 PM PDT 24
Peak memory 201600 kb
Host smart-1ac727c0-a94d-40be-b415-a833e867cf8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785261455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2785261455
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.3608466166
Short name T430
Test name
Test status
Simulation time 64096993 ps
CPU time 0.64 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 198328 kb
Host smart-ed4e0998-a9f4-4e1c-b0b0-381b67624d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608466166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3608466166
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1095048909
Short name T382
Test name
Test status
Simulation time 119841538 ps
CPU time 0.95 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 209432 kb
Host smart-4713d0a7-c091-4f31-95b0-94462fd2c054
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095048909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1095048909
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.409003170
Short name T401
Test name
Test status
Simulation time 65073665 ps
CPU time 0.92 seconds
Started Aug 03 04:59:43 PM PDT 24
Finished Aug 03 04:59:44 PM PDT 24
Peak memory 199396 kb
Host smart-2721383a-b773-4abf-b7c9-0a3ba7f026a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409003170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_
mubi.409003170
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.4043257451
Short name T294
Test name
Test status
Simulation time 25935743 ps
CPU time 0.67 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:43 PM PDT 24
Peak memory 199372 kb
Host smart-5fbe82cd-6f1f-48bf-9f7d-02750ead3416
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043257451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.4043257451
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.3243716436
Short name T559
Test name
Test status
Simulation time 63313862 ps
CPU time 0.66 seconds
Started Aug 03 04:59:40 PM PDT 24
Finished Aug 03 04:59:40 PM PDT 24
Peak memory 198644 kb
Host smart-5cd1ca69-b249-4d21-ad23-029438013da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243716436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3243716436
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.2951970763
Short name T621
Test name
Test status
Simulation time 25230794 ps
CPU time 0.68 seconds
Started Aug 03 04:59:42 PM PDT 24
Finished Aug 03 04:59:43 PM PDT 24
Peak memory 198768 kb
Host smart-417744b8-d66c-4d9a-8170-185f4aab8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951970763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2951970763
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4092011467
Short name T43
Test name
Test status
Simulation time 64285937 ps
CPU time 0.64 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198176 kb
Host smart-4e1475e2-a7d8-4017-bb76-a82931212c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092011467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.4092011467
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2069194005
Short name T420
Test name
Test status
Simulation time 34484932 ps
CPU time 0.6 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 197340 kb
Host smart-464803a6-240e-4302-b766-c345f134397e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069194005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2069194005
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.54434688
Short name T235
Test name
Test status
Simulation time 43588573 ps
CPU time 0.64 seconds
Started Aug 03 04:59:50 PM PDT 24
Finished Aug 03 04:59:51 PM PDT 24
Peak memory 198004 kb
Host smart-59cbc9cd-b5c5-40be-b51e-d98df0ba5668
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54434688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.54434688
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2632143209
Short name T617
Test name
Test status
Simulation time 40602329 ps
CPU time 0.64 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198372 kb
Host smart-6d7eeb5d-3e1d-4e08-8763-3b628427f828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632143209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2632143209
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.4068095429
Short name T488
Test name
Test status
Simulation time 89871233 ps
CPU time 0.76 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 201336 kb
Host smart-d0957e50-8e9d-45d5-9b26-4d7adc3810ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068095429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.4068095429
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.1515473131
Short name T328
Test name
Test status
Simulation time 34864575 ps
CPU time 0.63 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 198592 kb
Host smart-08e3ff94-5c2c-48f4-b80b-ea8b6d55a26c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515473131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.1515473131
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1969017636
Short name T576
Test name
Test status
Simulation time 142676443 ps
CPU time 0.78 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 209500 kb
Host smart-a33b357f-e349-42c8-915f-64f461e154aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969017636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1969017636
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.4000859467
Short name T510
Test name
Test status
Simulation time 191548989 ps
CPU time 0.82 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 199120 kb
Host smart-c52294e5-139a-4e30-98a5-7e219c4a4850
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000859467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4000859467
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.656808394
Short name T413
Test name
Test status
Simulation time 100548528 ps
CPU time 0.64 seconds
Started Aug 03 04:59:41 PM PDT 24
Finished Aug 03 04:59:41 PM PDT 24
Peak memory 199360 kb
Host smart-6af7ce2e-5578-4001-a8b0-fe857e15aa3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656808394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.656808394
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.2615325366
Short name T15
Test name
Test status
Simulation time 42822326 ps
CPU time 0.7 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 198616 kb
Host smart-acc96dc1-efab-49dc-96c9-988283e127cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615325366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.2615325366
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3400763813
Short name T14
Test name
Test status
Simulation time 49860028 ps
CPU time 0.61 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198536 kb
Host smart-834a0727-15ab-4fa6-b795-259cdfd13a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400763813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3400763813
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3850057631
Short name T618
Test name
Test status
Simulation time 87734183 ps
CPU time 0.67 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 199492 kb
Host smart-b4050d9c-3357-4dda-8089-a48657702bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850057631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.3850057631
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.791524046
Short name T124
Test name
Test status
Simulation time 28106826 ps
CPU time 0.63 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 197972 kb
Host smart-b0a2e918-a817-4739-ad6f-a6cf3a7b84b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791524046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_
malfunc.791524046
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2195362222
Short name T380
Test name
Test status
Simulation time 518673155 ps
CPU time 0.98 seconds
Started Aug 03 04:59:51 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 198420 kb
Host smart-908c03d4-ca61-4aac-8987-65500354615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195362222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2195362222
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.264875414
Short name T247
Test name
Test status
Simulation time 40640458 ps
CPU time 0.58 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 198072 kb
Host smart-270fab3a-f5f2-40b8-a973-f6ebec491c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264875414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.264875414
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.2304667717
Short name T507
Test name
Test status
Simulation time 23349131 ps
CPU time 0.61 seconds
Started Aug 03 04:59:45 PM PDT 24
Finished Aug 03 04:59:46 PM PDT 24
Peak memory 198324 kb
Host smart-ba1f682f-8207-4ad5-8e0c-8eaabdc7d7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304667717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.2304667717
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3123232395
Short name T184
Test name
Test status
Simulation time 110098184 ps
CPU time 0.66 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 201364 kb
Host smart-a4280264-6cdc-4cc1-9eb2-1df3072a6080
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123232395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3123232395
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3211309748
Short name T8
Test name
Test status
Simulation time 74086123 ps
CPU time 0.7 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198392 kb
Host smart-4663405c-5377-41bf-9ef4-67b5a1e05b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211309748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3211309748
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.1628101481
Short name T398
Test name
Test status
Simulation time 98586720 ps
CPU time 0.94 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 209504 kb
Host smart-dbfe51d7-5b9a-49b3-96d5-f5ffaa1df98b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628101481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1628101481
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2455090071
Short name T592
Test name
Test status
Simulation time 62614644 ps
CPU time 0.81 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 198112 kb
Host smart-33360ceb-5881-40e5-82c4-6f46e84f9b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455090071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2455090071
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1757222374
Short name T524
Test name
Test status
Simulation time 30840857 ps
CPU time 0.66 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198520 kb
Host smart-b7b05384-49a6-4542-ab1e-53487dfc85f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757222374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1757222374
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2234773959
Short name T97
Test name
Test status
Simulation time 21395263 ps
CPU time 0.81 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 199824 kb
Host smart-985e24e3-271c-4813-a701-51e25ff0285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234773959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2234773959
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2862500327
Short name T544
Test name
Test status
Simulation time 91896201 ps
CPU time 0.61 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198464 kb
Host smart-dca7b5fc-1265-4fa2-a763-2b4d12fb4a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862500327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2862500327
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.345362139
Short name T629
Test name
Test status
Simulation time 31041477 ps
CPU time 0.69 seconds
Started Aug 03 04:59:51 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 197272 kb
Host smart-84f5c603-29cf-4efe-8d10-60c9d8efc582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345362139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.345362139
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1385927955
Short name T249
Test name
Test status
Simulation time 160866825 ps
CPU time 0.96 seconds
Started Aug 03 04:59:47 PM PDT 24
Finished Aug 03 04:59:48 PM PDT 24
Peak memory 198100 kb
Host smart-9a737a01-d1de-4be7-b5a2-e7607969162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385927955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1385927955
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.535849001
Short name T312
Test name
Test status
Simulation time 43807466 ps
CPU time 0.66 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 197436 kb
Host smart-d32c5c5d-4d3c-492b-a0c0-c9ad7e9881fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535849001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.535849001
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.2749308542
Short name T499
Test name
Test status
Simulation time 48158448 ps
CPU time 0.65 seconds
Started Aug 03 04:59:46 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 198408 kb
Host smart-2d5308a3-a071-4153-aefe-08a66c461618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749308542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2749308542
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1462079476
Short name T9
Test name
Test status
Simulation time 40950700 ps
CPU time 0.66 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 201336 kb
Host smart-f4eb2da2-f3e7-41e1-bf6f-99627f810f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462079476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1462079476
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.170185102
Short name T37
Test name
Test status
Simulation time 74514428 ps
CPU time 0.7 seconds
Started Aug 03 04:59:51 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 199124 kb
Host smart-b0ee7468-565b-46c6-bb61-afc3c98ea57d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170185102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.170185102
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3201994404
Short name T343
Test name
Test status
Simulation time 339652575 ps
CPU time 0.79 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 209476 kb
Host smart-c5a05c7b-366b-427a-aaa5-45d075266c6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201994404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3201994404
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2317118549
Short name T40
Test name
Test status
Simulation time 83409203 ps
CPU time 0.71 seconds
Started Aug 03 04:59:48 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 198064 kb
Host smart-d62a8faf-de1f-4871-b4f7-9dc6eda60ad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317118549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2317118549
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.3206571085
Short name T322
Test name
Test status
Simulation time 64441145 ps
CPU time 0.68 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:52 PM PDT 24
Peak memory 198472 kb
Host smart-5da19c75-266e-4beb-adda-59e61622b766
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206571085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3206571085
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.2716757328
Short name T198
Test name
Test status
Simulation time 55840386 ps
CPU time 0.72 seconds
Started Aug 03 04:59:49 PM PDT 24
Finished Aug 03 04:59:50 PM PDT 24
Peak memory 198056 kb
Host smart-d12473ec-2c80-4061-bcdd-11cfdca3bc8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716757328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.2716757328
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.1928094567
Short name T348
Test name
Test status
Simulation time 84761894 ps
CPU time 0.67 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:53 PM PDT 24
Peak memory 198572 kb
Host smart-573b4f5e-1875-4b7a-8810-e9a4c134d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928094567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1928094567
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.584869453
Short name T155
Test name
Test status
Simulation time 69576602 ps
CPU time 0.68 seconds
Started Aug 03 05:00:05 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199116 kb
Host smart-0e0e0d5d-1965-4d07-adf7-c4927d1fe410
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584869453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disa
ble_rom_integrity_check.584869453
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3431200071
Short name T553
Test name
Test status
Simulation time 64025934 ps
CPU time 0.58 seconds
Started Aug 03 04:59:56 PM PDT 24
Finished Aug 03 04:59:57 PM PDT 24
Peak memory 198020 kb
Host smart-f10c373e-b644-4465-9593-a3789bd38b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431200071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3431200071
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.1330922619
Short name T125
Test name
Test status
Simulation time 163348583 ps
CPU time 1 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 198396 kb
Host smart-2ce046b7-e7c4-4642-999e-e5160b331d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330922619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1330922619
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.503062030
Short name T635
Test name
Test status
Simulation time 87951840 ps
CPU time 0.6 seconds
Started Aug 03 04:59:58 PM PDT 24
Finished Aug 03 04:59:58 PM PDT 24
Peak memory 198108 kb
Host smart-ee880bc2-cfd3-4fff-8b77-1110797c2b96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503062030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.503062030
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3617751562
Short name T388
Test name
Test status
Simulation time 58116900 ps
CPU time 0.64 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198092 kb
Host smart-bcaf9a0a-f8f1-4827-a002-75d3ee90b552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617751562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3617751562
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3355816228
Short name T191
Test name
Test status
Simulation time 69788002 ps
CPU time 0.69 seconds
Started Aug 03 05:00:02 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 201220 kb
Host smart-ea59fbdc-0b16-4bc9-86b1-1b4f2906f582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355816228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3355816228
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2684106287
Short name T397
Test name
Test status
Simulation time 109249176 ps
CPU time 0.73 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:53 PM PDT 24
Peak memory 198616 kb
Host smart-f433137d-27be-4ad0-8341-5d2ee48e8797
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684106287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2684106287
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.4292239031
Short name T607
Test name
Test status
Simulation time 116456745 ps
CPU time 0.93 seconds
Started Aug 03 04:59:54 PM PDT 24
Finished Aug 03 04:59:55 PM PDT 24
Peak memory 209432 kb
Host smart-44649fe1-df83-453c-be59-aa2e58301315
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292239031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.4292239031
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4200570775
Short name T229
Test name
Test status
Simulation time 91779661 ps
CPU time 0.75 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:10 PM PDT 24
Peak memory 199328 kb
Host smart-3ece0799-23b9-4a1c-8929-cdd5797c0a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200570775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4200570775
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.4031060019
Short name T212
Test name
Test status
Simulation time 25700489 ps
CPU time 0.66 seconds
Started Aug 03 04:59:53 PM PDT 24
Finished Aug 03 04:59:54 PM PDT 24
Peak memory 198552 kb
Host smart-4783cb01-0334-4165-9825-a8730bedfed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031060019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.4031060019
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3907872687
Short name T448
Test name
Test status
Simulation time 103235004 ps
CPU time 0.76 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 198768 kb
Host smart-e12aa993-2eb0-4e30-b623-c666f1270a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907872687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3907872687
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2346056023
Short name T135
Test name
Test status
Simulation time 60836282 ps
CPU time 0.69 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 198336 kb
Host smart-cc77b969-5210-4959-a676-ecf350860525
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346056023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2346056023
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3369953782
Short name T310
Test name
Test status
Simulation time 30023618 ps
CPU time 0.66 seconds
Started Aug 03 05:00:04 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198028 kb
Host smart-2643a53a-0d9e-4074-a3ce-0a82e31c4961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369953782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3369953782
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.750161387
Short name T354
Test name
Test status
Simulation time 605764263 ps
CPU time 0.98 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 198432 kb
Host smart-d71d103a-4e7b-480a-8bbc-7868414d95f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750161387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.750161387
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3268772262
Short name T254
Test name
Test status
Simulation time 48183452 ps
CPU time 0.64 seconds
Started Aug 03 05:00:05 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198208 kb
Host smart-1800df3f-651d-4e5e-bf37-02b49c49ccb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268772262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3268772262
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1505242264
Short name T250
Test name
Test status
Simulation time 57270316 ps
CPU time 0.61 seconds
Started Aug 03 04:59:56 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 198124 kb
Host smart-3bbec371-ba33-47a0-ab83-0d6f6b0c9e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505242264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1505242264
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1458396669
Short name T534
Test name
Test status
Simulation time 46856099 ps
CPU time 0.78 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 198424 kb
Host smart-e366db99-649e-4acb-a519-e8464e657d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458396669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1458396669
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1236968816
Short name T432
Test name
Test status
Simulation time 152772155 ps
CPU time 0.84 seconds
Started Aug 03 04:59:56 PM PDT 24
Finished Aug 03 04:59:57 PM PDT 24
Peak memory 209480 kb
Host smart-cecda136-7a5b-4712-9ef6-dd191fd57dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236968816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1236968816
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.836898422
Short name T375
Test name
Test status
Simulation time 55302891 ps
CPU time 0.83 seconds
Started Aug 03 05:00:13 PM PDT 24
Finished Aug 03 05:00:14 PM PDT 24
Peak memory 198148 kb
Host smart-1a8cab07-73de-4235-bcee-e05a4485b9e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836898422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_
mubi.836898422
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.4172366956
Short name T470
Test name
Test status
Simulation time 33462748 ps
CPU time 0.68 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199416 kb
Host smart-7c01165c-3a06-4991-8488-4f7404b164e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172366956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.4172366956
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3270338995
Short name T516
Test name
Test status
Simulation time 64159687 ps
CPU time 0.69 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198636 kb
Host smart-0214200b-42cc-4558-b792-2996a9887ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270338995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3270338995
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1495086099
Short name T489
Test name
Test status
Simulation time 38336762 ps
CPU time 0.6 seconds
Started Aug 03 04:59:52 PM PDT 24
Finished Aug 03 04:59:53 PM PDT 24
Peak memory 197956 kb
Host smart-20e9158e-4e0d-4512-9750-9a771fd0b371
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495086099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1495086099
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2699638131
Short name T417
Test name
Test status
Simulation time 307910214 ps
CPU time 0.99 seconds
Started Aug 03 05:00:13 PM PDT 24
Finished Aug 03 05:00:14 PM PDT 24
Peak memory 198108 kb
Host smart-2570aa6b-c83d-483a-81ad-47a933c8980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699638131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2699638131
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.234668423
Short name T536
Test name
Test status
Simulation time 41486954 ps
CPU time 0.61 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:55 PM PDT 24
Peak memory 198116 kb
Host smart-171324c5-a215-4a92-b60e-5294e3a5a3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234668423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.234668423
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3976240803
Short name T295
Test name
Test status
Simulation time 79503062 ps
CPU time 0.63 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198368 kb
Host smart-ef78efda-85bb-40f7-97d5-d80295294e8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976240803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3976240803
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3980793117
Short name T190
Test name
Test status
Simulation time 55504693 ps
CPU time 0.68 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 201356 kb
Host smart-9b710b01-c972-451b-8dac-c28951d719d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980793117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3980793117
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3981638059
Short name T451
Test name
Test status
Simulation time 60869519 ps
CPU time 0.72 seconds
Started Aug 03 04:59:58 PM PDT 24
Finished Aug 03 04:59:59 PM PDT 24
Peak memory 199100 kb
Host smart-2f8e568c-6da3-4715-9ee4-a09bb431274f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981638059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3981638059
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.2758691975
Short name T473
Test name
Test status
Simulation time 168145824 ps
CPU time 0.74 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:10 PM PDT 24
Peak memory 209468 kb
Host smart-98f5da53-e496-40dd-a25f-785ca9250b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758691975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2758691975
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.361068451
Short name T316
Test name
Test status
Simulation time 58330866 ps
CPU time 0.84 seconds
Started Aug 03 05:00:04 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198044 kb
Host smart-bcbe5b46-9786-462e-a582-307cad1815e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361068451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.361068451
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.105235127
Short name T531
Test name
Test status
Simulation time 65903399 ps
CPU time 0.62 seconds
Started Aug 03 04:59:55 PM PDT 24
Finished Aug 03 04:59:55 PM PDT 24
Peak memory 198532 kb
Host smart-cd10458a-cc71-409a-a991-6d0e35519c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105235127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.105235127
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.100315516
Short name T180
Test name
Test status
Simulation time 56580210 ps
CPU time 0.6 seconds
Started Aug 03 04:59:54 PM PDT 24
Finished Aug 03 04:59:55 PM PDT 24
Peak memory 198192 kb
Host smart-f894771c-e517-4a64-a690-ddd2ddc1d074
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100315516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.100315516
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.118055161
Short name T429
Test name
Test status
Simulation time 35013343 ps
CPU time 0.69 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198768 kb
Host smart-f6a69c25-cb9d-4b4e-a016-66853a044d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118055161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.118055161
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.919587378
Short name T162
Test name
Test status
Simulation time 74365609 ps
CPU time 0.67 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 199032 kb
Host smart-b0aabee2-a5af-4b8f-aa85-a9efcb505c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919587378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.919587378
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1669481038
Short name T302
Test name
Test status
Simulation time 33050090 ps
CPU time 0.61 seconds
Started Aug 03 04:59:59 PM PDT 24
Finished Aug 03 05:00:00 PM PDT 24
Peak memory 198044 kb
Host smart-2452a263-f640-48c9-8d16-f525d9703944
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669481038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1669481038
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2493151265
Short name T518
Test name
Test status
Simulation time 633636682 ps
CPU time 1.04 seconds
Started Aug 03 05:00:00 PM PDT 24
Finished Aug 03 05:00:01 PM PDT 24
Peak memory 198056 kb
Host smart-22bfe12b-78e6-4ff7-a4c9-9cafe6b800f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493151265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2493151265
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.1077437709
Short name T598
Test name
Test status
Simulation time 35027395 ps
CPU time 0.65 seconds
Started Aug 03 05:00:15 PM PDT 24
Finished Aug 03 05:00:16 PM PDT 24
Peak memory 197424 kb
Host smart-becda2c5-5768-4f9e-a5fa-636b6656b31c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077437709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1077437709
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.991952025
Short name T561
Test name
Test status
Simulation time 65641167 ps
CPU time 0.62 seconds
Started Aug 03 05:00:00 PM PDT 24
Finished Aug 03 05:00:01 PM PDT 24
Peak memory 198108 kb
Host smart-5e763ebf-356e-41b6-b2e8-199e6ebb55b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991952025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.991952025
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3767157807
Short name T166
Test name
Test status
Simulation time 55499786 ps
CPU time 0.7 seconds
Started Aug 03 05:00:08 PM PDT 24
Finished Aug 03 05:00:09 PM PDT 24
Peak memory 201452 kb
Host smart-86590cb3-4870-4941-be79-bc02f9f7d682
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767157807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3767157807
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.3057667545
Short name T595
Test name
Test status
Simulation time 75516242 ps
CPU time 0.62 seconds
Started Aug 03 04:59:57 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198032 kb
Host smart-d0ed2378-04b5-4332-9ddc-79d875479e60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057667545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.3057667545
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3975745694
Short name T365
Test name
Test status
Simulation time 165916567 ps
CPU time 0.78 seconds
Started Aug 03 05:00:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 209344 kb
Host smart-a084bc45-cd1c-4037-9e73-cba343ca6dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975745694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3975745694
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.304988895
Short name T271
Test name
Test status
Simulation time 130788117 ps
CPU time 0.85 seconds
Started Aug 03 05:00:02 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199240 kb
Host smart-06beb928-3597-408c-bdeb-1ce2e3041487
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304988895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.304988895
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2050794544
Short name T456
Test name
Test status
Simulation time 37490441 ps
CPU time 0.66 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 198552 kb
Host smart-93a96893-444a-4145-b107-4021f245d8b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050794544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2050794544
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3533480825
Short name T545
Test name
Test status
Simulation time 110417925 ps
CPU time 0.89 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 200148 kb
Host smart-01f3a8c7-0f0c-4891-b602-730b9999b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533480825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3533480825
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1670909715
Short name T153
Test name
Test status
Simulation time 54684343 ps
CPU time 0.85 seconds
Started Aug 03 05:00:12 PM PDT 24
Finished Aug 03 05:00:13 PM PDT 24
Peak memory 199088 kb
Host smart-d11f4bc3-3d90-4804-8da2-4a29435cdeb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670909715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.1670909715
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3919403181
Short name T327
Test name
Test status
Simulation time 33091294 ps
CPU time 0.61 seconds
Started Aug 03 05:00:08 PM PDT 24
Finished Aug 03 05:00:09 PM PDT 24
Peak memory 198000 kb
Host smart-f97e2c4b-2c0c-4c98-819f-4f0812a014b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919403181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3919403181
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1013802967
Short name T127
Test name
Test status
Simulation time 311186878 ps
CPU time 0.92 seconds
Started Aug 03 05:00:09 PM PDT 24
Finished Aug 03 05:00:10 PM PDT 24
Peak memory 198404 kb
Host smart-f77c48cb-e8d0-4b66-9607-c55fe660fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013802967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1013802967
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3066866232
Short name T270
Test name
Test status
Simulation time 32090883 ps
CPU time 0.65 seconds
Started Aug 03 05:00:06 PM PDT 24
Finished Aug 03 05:00:07 PM PDT 24
Peak memory 198052 kb
Host smart-41cc7909-9b30-4ccd-9f3b-d99fe4b81abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066866232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3066866232
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3097031086
Short name T94
Test name
Test status
Simulation time 49323888 ps
CPU time 0.61 seconds
Started Aug 03 05:00:16 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198404 kb
Host smart-c29967e0-d854-4853-9cf0-d4b314d98b48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097031086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3097031086
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2920242411
Short name T206
Test name
Test status
Simulation time 43428877 ps
CPU time 0.68 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 201300 kb
Host smart-2bc381ad-46c5-48d0-97d9-96c9d0e7a718
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920242411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2920242411
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1164006721
Short name T224
Test name
Test status
Simulation time 106891595 ps
CPU time 0.76 seconds
Started Aug 03 05:00:15 PM PDT 24
Finished Aug 03 05:00:16 PM PDT 24
Peak memory 199092 kb
Host smart-1a65c5be-051d-452a-93d5-96548d242dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164006721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1164006721
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3109977801
Short name T458
Test name
Test status
Simulation time 119716993 ps
CPU time 0.83 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 209536 kb
Host smart-05d676af-1ba7-460e-97db-678d4965719d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109977801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3109977801
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3450042457
Short name T591
Test name
Test status
Simulation time 60983072 ps
CPU time 0.77 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 197972 kb
Host smart-3a166943-0c88-46e6-a599-7aa41f00e368
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450042457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3450042457
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2631892732
Short name T330
Test name
Test status
Simulation time 29857252 ps
CPU time 0.69 seconds
Started Aug 03 05:00:05 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199380 kb
Host smart-25a278f3-68a9-496c-a186-b904145b79d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631892732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2631892732
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.1716072916
Short name T119
Test name
Test status
Simulation time 31937909 ps
CPU time 0.68 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:07 PM PDT 24
Peak memory 198644 kb
Host smart-ee205e8e-b429-41b8-b7b3-8f9da234b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716072916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1716072916
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3079855572
Short name T158
Test name
Test status
Simulation time 62207985 ps
CPU time 0.82 seconds
Started Aug 03 05:00:05 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199156 kb
Host smart-5d291aba-ad6a-4caf-bf7e-b7fad3ee545f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079855572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3079855572
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3231004254
Short name T419
Test name
Test status
Simulation time 35450430 ps
CPU time 0.6 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 197948 kb
Host smart-701ca2a9-17ca-4220-90e8-f8967f87ed20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231004254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3231004254
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3873593992
Short name T565
Test name
Test status
Simulation time 632119324 ps
CPU time 0.96 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:09 PM PDT 24
Peak memory 198020 kb
Host smart-3a874b89-5e0e-4af5-a2bf-47b4ddd2561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873593992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3873593992
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1671106460
Short name T342
Test name
Test status
Simulation time 47083796 ps
CPU time 0.68 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 198004 kb
Host smart-a9501e3a-2da2-4c8a-b397-0974bd3e8db9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671106460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1671106460
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3238834966
Short name T519
Test name
Test status
Simulation time 50771822 ps
CPU time 0.61 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 198076 kb
Host smart-033aa11d-afc9-4b41-a30c-45242067c706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238834966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3238834966
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3270600638
Short name T567
Test name
Test status
Simulation time 53081974 ps
CPU time 0.78 seconds
Started Aug 03 05:00:05 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198292 kb
Host smart-40248672-dfce-451d-84b1-850986b817b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270600638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3270600638
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2694943975
Short name T267
Test name
Test status
Simulation time 155293286 ps
CPU time 0.89 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 209540 kb
Host smart-ece932f4-0265-40f9-99d7-a1c8804a3c93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694943975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2694943975
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1562688714
Short name T262
Test name
Test status
Simulation time 83830001 ps
CPU time 0.74 seconds
Started Aug 03 05:00:01 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198172 kb
Host smart-4d5dc022-9fcb-46e6-b3e1-c2e6bca1db64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562688714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1562688714
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.3300345628
Short name T236
Test name
Test status
Simulation time 35846974 ps
CPU time 0.65 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 198460 kb
Host smart-bb0a7450-9922-4fd9-a07a-9faa993d9751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300345628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.3300345628
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1402362470
Short name T356
Test name
Test status
Simulation time 72457574 ps
CPU time 0.7 seconds
Started Aug 03 04:58:44 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 198828 kb
Host smart-7dd6ab8c-e80b-4750-88bf-51b75c601004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402362470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1402362470
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.4053161401
Short name T389
Test name
Test status
Simulation time 73111224 ps
CPU time 0.64 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 199176 kb
Host smart-85d032e7-3a16-43c5-8b87-f94602896a08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053161401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.4053161401
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.420575655
Short name T450
Test name
Test status
Simulation time 38510317 ps
CPU time 0.59 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 198076 kb
Host smart-b800501d-4a2b-4b7a-b792-6bc093fd01b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420575655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_m
alfunc.420575655
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2271530855
Short name T404
Test name
Test status
Simulation time 630366645 ps
CPU time 1 seconds
Started Aug 03 04:58:46 PM PDT 24
Finished Aug 03 04:58:47 PM PDT 24
Peak memory 198048 kb
Host smart-6c9a9067-c4ab-4baf-9b33-4fa633f568f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271530855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2271530855
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1361108748
Short name T239
Test name
Test status
Simulation time 45594861 ps
CPU time 0.68 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 198060 kb
Host smart-45f67b55-bd34-40a7-924a-18e4cbe5ca1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361108748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1361108748
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.213952031
Short name T526
Test name
Test status
Simulation time 35501560 ps
CPU time 0.66 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 198124 kb
Host smart-ac4ba3a7-84b3-413b-bcb1-e43ab5a47010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213952031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.213952031
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1450857758
Short name T171
Test name
Test status
Simulation time 46316460 ps
CPU time 0.71 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 201368 kb
Host smart-cb760f32-d9ac-42c1-ad21-78dd850de87f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450857758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1450857758
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.3114016745
Short name T433
Test name
Test status
Simulation time 80295501 ps
CPU time 0.9 seconds
Started Aug 03 04:58:40 PM PDT 24
Finished Aug 03 04:58:41 PM PDT 24
Peak memory 199040 kb
Host smart-4bf4e6e2-8810-4cfe-8f09-f3459cae8fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114016745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3114016745
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3486302418
Short name T45
Test name
Test status
Simulation time 159405379 ps
CPU time 0.78 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 209508 kb
Host smart-35e00a81-870f-4bea-9dac-02a9a809bb9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486302418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3486302418
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3481120872
Short name T34
Test name
Test status
Simulation time 688915003 ps
CPU time 2.11 seconds
Started Aug 03 04:58:46 PM PDT 24
Finished Aug 03 04:58:48 PM PDT 24
Peak memory 217984 kb
Host smart-a0f29d97-5643-4367-85c6-0c88fec72df5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481120872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3481120872
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2661754395
Short name T272
Test name
Test status
Simulation time 130816573 ps
CPU time 0.71 seconds
Started Aug 03 04:58:46 PM PDT 24
Finished Aug 03 04:58:47 PM PDT 24
Peak memory 198144 kb
Host smart-f4b82b7e-2824-4b11-a782-78ffe58a23ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661754395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2661754395
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.1598543119
Short name T512
Test name
Test status
Simulation time 29459158 ps
CPU time 0.68 seconds
Started Aug 03 04:58:44 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 199356 kb
Host smart-996bc52a-aba4-415b-8627-53a79dc583f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598543119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1598543119
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.2034547348
Short name T514
Test name
Test status
Simulation time 81710882 ps
CPU time 0.72 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198632 kb
Host smart-666cc7af-a406-4abf-bd40-df4427660526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034547348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2034547348
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1474840956
Short name T160
Test name
Test status
Simulation time 56162075 ps
CPU time 0.78 seconds
Started Aug 03 05:00:16 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198540 kb
Host smart-d9363bb1-f60c-4f2a-895c-2f7bb9d375f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474840956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1474840956
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.487866304
Short name T405
Test name
Test status
Simulation time 37408847 ps
CPU time 0.59 seconds
Started Aug 03 05:00:13 PM PDT 24
Finished Aug 03 05:00:14 PM PDT 24
Peak memory 198000 kb
Host smart-60a9c420-9999-4897-83fe-a8204b80e029
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487866304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_
malfunc.487866304
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3739321528
Short name T304
Test name
Test status
Simulation time 2462243186 ps
CPU time 0.92 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198464 kb
Host smart-d51ae377-d486-4603-b0cc-407e27c42492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739321528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3739321528
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2904761873
Short name T288
Test name
Test status
Simulation time 64215744 ps
CPU time 0.65 seconds
Started Aug 03 05:00:15 PM PDT 24
Finished Aug 03 05:00:16 PM PDT 24
Peak memory 198044 kb
Host smart-8d62464f-0491-4e61-ad74-8cc4c3c8824a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904761873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2904761873
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2193533107
Short name T341
Test name
Test status
Simulation time 64381073 ps
CPU time 0.62 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198108 kb
Host smart-9ac3b0fc-ea3d-41a4-b9e8-ba374a80edb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193533107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2193533107
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.1204133140
Short name T517
Test name
Test status
Simulation time 57236363 ps
CPU time 0.69 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 201348 kb
Host smart-63f63c6c-cc34-460d-b936-7c086d66dfec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204133140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.1204133140
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2056488923
Short name T319
Test name
Test status
Simulation time 53569697 ps
CPU time 0.77 seconds
Started Aug 03 05:00:09 PM PDT 24
Finished Aug 03 05:00:09 PM PDT 24
Peak memory 198276 kb
Host smart-e3a36215-b3fd-4cf8-8894-0a3122774fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056488923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2056488923
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1944427135
Short name T527
Test name
Test status
Simulation time 114001850 ps
CPU time 0.86 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 209504 kb
Host smart-cd1483e3-6c4a-4134-9a7e-20d9b48244dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944427135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1944427135
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.15396035
Short name T541
Test name
Test status
Simulation time 63250807 ps
CPU time 0.97 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 199312 kb
Host smart-13364034-c626-4aae-8aab-16a76b450567
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15396035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.15396035
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2759591092
Short name T234
Test name
Test status
Simulation time 29010506 ps
CPU time 0.68 seconds
Started Aug 03 05:00:06 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 198476 kb
Host smart-841b6321-d05a-4bcd-a919-45133c7eee56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759591092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2759591092
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.1547888296
Short name T200
Test name
Test status
Simulation time 54767842 ps
CPU time 0.67 seconds
Started Aug 03 05:00:10 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 198544 kb
Host smart-8a612877-ef54-4d7c-bc2c-103a5ef0007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547888296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1547888296
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1295003943
Short name T209
Test name
Test status
Simulation time 49433403 ps
CPU time 0.79 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198580 kb
Host smart-01a26a05-fed6-436e-a0f8-521ae04c3633
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295003943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1295003943
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1074927729
Short name T438
Test name
Test status
Simulation time 72575659 ps
CPU time 0.6 seconds
Started Aug 03 05:00:11 PM PDT 24
Finished Aug 03 05:00:12 PM PDT 24
Peak memory 198176 kb
Host smart-edd67d2b-a786-4d25-983e-41182cd5e975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074927729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1074927729
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.3036011093
Short name T273
Test name
Test status
Simulation time 160517292 ps
CPU time 0.98 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 198100 kb
Host smart-bd6ea946-4556-4930-b0c0-878cf8c0ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036011093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3036011093
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3490358550
Short name T486
Test name
Test status
Simulation time 86092829 ps
CPU time 0.67 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 198028 kb
Host smart-30e54f9f-c93f-4e37-9918-6280fd0bac9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490358550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3490358550
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.3462450635
Short name T227
Test name
Test status
Simulation time 177263475 ps
CPU time 0.6 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198096 kb
Host smart-3e815973-fcf2-41aa-bfab-33c82c876af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462450635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3462450635
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.4106834518
Short name T167
Test name
Test status
Simulation time 63505195 ps
CPU time 0.71 seconds
Started Aug 03 05:00:09 PM PDT 24
Finished Aug 03 05:00:09 PM PDT 24
Peak memory 201372 kb
Host smart-c13937b8-d3f4-4756-a4ba-77d0ba81f1e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106834518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.4106834518
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3983684666
Short name T269
Test name
Test status
Simulation time 60648471 ps
CPU time 0.65 seconds
Started Aug 03 05:00:07 PM PDT 24
Finished Aug 03 05:00:08 PM PDT 24
Peak memory 198240 kb
Host smart-fac65c9c-9943-4dd5-820a-efd1a317fe6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983684666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3983684666
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.53141947
Short name T334
Test name
Test status
Simulation time 96133393 ps
CPU time 1.06 seconds
Started Aug 03 05:00:04 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 209580 kb
Host smart-7ed8c063-dced-429e-84db-87ff9dbb8b9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53141947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.53141947
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2151548056
Short name T285
Test name
Test status
Simulation time 53825691 ps
CPU time 0.78 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 197960 kb
Host smart-8b857717-ec02-453d-9c81-2161e8eba779
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151548056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2151548056
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3131671955
Short name T479
Test name
Test status
Simulation time 29378696 ps
CPU time 0.67 seconds
Started Aug 03 05:00:12 PM PDT 24
Finished Aug 03 05:00:13 PM PDT 24
Peak memory 198536 kb
Host smart-6464c1c4-60a3-46d6-b013-4e85b21da3d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131671955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3131671955
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3542911022
Short name T549
Test name
Test status
Simulation time 264202225 ps
CPU time 0.7 seconds
Started Aug 03 05:00:13 PM PDT 24
Finished Aug 03 05:00:14 PM PDT 24
Peak memory 198792 kb
Host smart-ad487d35-8673-4f60-8cc8-44fcc559b129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542911022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3542911022
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3433471821
Short name T612
Test name
Test status
Simulation time 50277940 ps
CPU time 0.78 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198476 kb
Host smart-38d32160-ec2a-47c2-bc65-66b9c8f04414
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433471821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3433471821
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1188252782
Short name T132
Test name
Test status
Simulation time 38417536 ps
CPU time 0.57 seconds
Started Aug 03 05:00:11 PM PDT 24
Finished Aug 03 05:00:12 PM PDT 24
Peak memory 197348 kb
Host smart-86e9cb67-1333-4380-8d0d-e11bcc71201f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188252782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1188252782
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.1890426721
Short name T579
Test name
Test status
Simulation time 312995356 ps
CPU time 0.98 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 198344 kb
Host smart-0025b694-c5c4-4277-8731-56627644d4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890426721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1890426721
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.2498001623
Short name T574
Test name
Test status
Simulation time 31895870 ps
CPU time 0.63 seconds
Started Aug 03 05:00:24 PM PDT 24
Finished Aug 03 05:00:25 PM PDT 24
Peak memory 198072 kb
Host smart-7787a51c-f796-4138-a100-3064405dffb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498001623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2498001623
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1001562650
Short name T246
Test name
Test status
Simulation time 71435016 ps
CPU time 0.61 seconds
Started Aug 03 05:00:19 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 198028 kb
Host smart-18c859eb-7753-4b99-a90e-0182e6c10784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001562650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1001562650
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.1172502371
Short name T194
Test name
Test status
Simulation time 59124099 ps
CPU time 0.64 seconds
Started Aug 03 05:00:22 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 201364 kb
Host smart-b2b02103-04a2-4a19-8607-d3b2fe9cbb95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172502371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.1172502371
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.571357319
Short name T630
Test name
Test status
Simulation time 70661064 ps
CPU time 0.88 seconds
Started Aug 03 05:00:22 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 198420 kb
Host smart-3b0688f4-1f7e-4daf-941b-94b7328d4495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571357319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.571357319
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1256063994
Short name T275
Test name
Test status
Simulation time 102309863 ps
CPU time 0.93 seconds
Started Aug 03 05:00:19 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 209520 kb
Host smart-55823639-fbf0-440a-96a8-32725291afeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256063994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1256063994
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2283713614
Short name T282
Test name
Test status
Simulation time 57832186 ps
CPU time 0.8 seconds
Started Aug 03 05:00:11 PM PDT 24
Finished Aug 03 05:00:12 PM PDT 24
Peak memory 198088 kb
Host smart-45635f20-1b6d-40fa-89de-cad4eb13aff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283713614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2283713614
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.4152725412
Short name T503
Test name
Test status
Simulation time 53172102 ps
CPU time 0.63 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198548 kb
Host smart-62b98440-ae95-4f64-955d-ab24d9420f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152725412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.4152725412
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3117907440
Short name T27
Test name
Test status
Simulation time 50104757 ps
CPU time 0.61 seconds
Started Aug 03 05:00:11 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 198168 kb
Host smart-fe1de8a2-70cb-4478-8b7b-38203d5df7e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117907440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3117907440
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.1913884838
Short name T406
Test name
Test status
Simulation time 39161041 ps
CPU time 0.82 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 200212 kb
Host smart-e6896c67-ef40-4edb-8044-9399f426211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913884838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1913884838
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1740727646
Short name T137
Test name
Test status
Simulation time 69057157 ps
CPU time 0.66 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198316 kb
Host smart-633ea805-d478-4ed3-95cf-3749d26c8e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740727646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1740727646
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3539713773
Short name T424
Test name
Test status
Simulation time 45912545 ps
CPU time 0.61 seconds
Started Aug 03 05:00:11 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 197324 kb
Host smart-fb0faba0-185b-4905-9adf-f5e9d584c70a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539713773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3539713773
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2057221883
Short name T515
Test name
Test status
Simulation time 309026310 ps
CPU time 0.94 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 198044 kb
Host smart-59a2dca8-4a40-40b4-a30e-08fcbc74302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057221883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2057221883
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3163740608
Short name T233
Test name
Test status
Simulation time 54972245 ps
CPU time 0.58 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198056 kb
Host smart-baf03d34-9914-4858-8746-39c34bd22873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163740608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3163740608
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1329562676
Short name T623
Test name
Test status
Simulation time 35414767 ps
CPU time 0.62 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198104 kb
Host smart-c1b08c82-b434-4f88-8dfc-657df2449490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329562676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1329562676
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3563835794
Short name T86
Test name
Test status
Simulation time 104354134 ps
CPU time 0.68 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 201296 kb
Host smart-6b76bdcb-91ee-4735-9d00-7eeca74e3e23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563835794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3563835794
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2092659006
Short name T44
Test name
Test status
Simulation time 75087128 ps
CPU time 0.87 seconds
Started Aug 03 05:00:28 PM PDT 24
Finished Aug 03 05:00:36 PM PDT 24
Peak memory 199084 kb
Host smart-f822456d-0f88-4fcf-ba5c-facc92198b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092659006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2092659006
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2937113803
Short name T533
Test name
Test status
Simulation time 146758710 ps
CPU time 0.79 seconds
Started Aug 03 05:00:14 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 209440 kb
Host smart-c9bd400c-d288-4bb9-9cd3-467364a3da7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937113803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2937113803
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2131174859
Short name T251
Test name
Test status
Simulation time 97900399 ps
CPU time 0.73 seconds
Started Aug 03 05:00:17 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 198192 kb
Host smart-e0a402d0-e9f0-4414-ab25-5b02953ba751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131174859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2131174859
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2121587543
Short name T609
Test name
Test status
Simulation time 30490558 ps
CPU time 0.67 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 198568 kb
Host smart-9dd4d3ec-bd30-42d4-b24a-75c31939a153
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121587543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2121587543
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.271134398
Short name T478
Test name
Test status
Simulation time 32946199 ps
CPU time 0.75 seconds
Started Aug 03 05:00:09 PM PDT 24
Finished Aug 03 05:00:10 PM PDT 24
Peak memory 198832 kb
Host smart-a8ac1b6e-e8fa-4d44-8c2b-dc469d5c151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271134398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.271134398
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3233901255
Short name T314
Test name
Test status
Simulation time 65818575 ps
CPU time 0.78 seconds
Started Aug 03 05:00:20 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 198552 kb
Host smart-b9b0171e-3095-4e00-8c78-17cb008558a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233901255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3233901255
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1049011087
Short name T298
Test name
Test status
Simulation time 30561243 ps
CPU time 0.62 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 197288 kb
Host smart-ddcfd08a-d1fb-4b6b-97a0-adb16ced8fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049011087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1049011087
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3590886899
Short name T129
Test name
Test status
Simulation time 604894462 ps
CPU time 0.97 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198100 kb
Host smart-5ac1d5bf-69bf-4340-8aad-13051854c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590886899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3590886899
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.30600264
Short name T381
Test name
Test status
Simulation time 41319819 ps
CPU time 0.61 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 197376 kb
Host smart-fee1ebad-1fda-44e5-9c4f-e5ccbfe2898d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30600264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.30600264
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1688360153
Short name T344
Test name
Test status
Simulation time 44907865 ps
CPU time 0.63 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198060 kb
Host smart-727dca62-ab82-47ee-94f9-c2a25eeef65b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688360153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1688360153
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3819237441
Short name T425
Test name
Test status
Simulation time 105152057 ps
CPU time 0.74 seconds
Started Aug 03 05:00:16 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198368 kb
Host smart-606948fa-514b-4a08-9775-117229026d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819237441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3819237441
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.507682054
Short name T410
Test name
Test status
Simulation time 99188980 ps
CPU time 1.01 seconds
Started Aug 03 05:00:20 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 209448 kb
Host smart-22269a96-0f1f-4c63-8d49-f2ba8fd2f0b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507682054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.507682054
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2052586619
Short name T599
Test name
Test status
Simulation time 105384096 ps
CPU time 0.66 seconds
Started Aug 03 05:00:19 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 197740 kb
Host smart-1c359976-253f-40a5-9098-43a3b1a63a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052586619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2052586619
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2132818375
Short name T289
Test name
Test status
Simulation time 58269048 ps
CPU time 0.63 seconds
Started Aug 03 05:00:16 PM PDT 24
Finished Aug 03 05:00:17 PM PDT 24
Peak memory 198536 kb
Host smart-177065c6-0543-4599-8721-f34d5c94926c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132818375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2132818375
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3031741128
Short name T542
Test name
Test status
Simulation time 26702286 ps
CPU time 0.7 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198732 kb
Host smart-d9f73fa2-07c6-4a2c-8b42-f93d77df55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031741128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3031741128
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.384298819
Short name T506
Test name
Test status
Simulation time 39936864 ps
CPU time 0.58 seconds
Started Aug 03 05:00:26 PM PDT 24
Finished Aug 03 05:00:27 PM PDT 24
Peak memory 197328 kb
Host smart-3279afe6-3c38-48a1-827f-fcccd74d9cc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384298819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.384298819
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.240703853
Short name T349
Test name
Test status
Simulation time 159915509 ps
CPU time 0.94 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 198104 kb
Host smart-a4a2fd58-0664-4db6-adb2-b9cf1b73bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240703853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.240703853
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3742815804
Short name T583
Test name
Test status
Simulation time 67827997 ps
CPU time 0.64 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 197320 kb
Host smart-8c3495a8-a206-4148-a2f3-89637756cac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742815804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3742815804
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3633780727
Short name T225
Test name
Test status
Simulation time 89318105 ps
CPU time 0.59 seconds
Started Aug 03 05:00:20 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 198124 kb
Host smart-8f6b103c-e3ba-4399-b84d-2e4c18a64a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633780727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3633780727
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2141627475
Short name T177
Test name
Test status
Simulation time 134485712 ps
CPU time 0.69 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 201332 kb
Host smart-80f5a70d-e410-4d7c-a61e-c9f6560c92fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141627475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.2141627475
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.725803660
Short name T505
Test name
Test status
Simulation time 62918822 ps
CPU time 0.81 seconds
Started Aug 03 05:00:22 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 198368 kb
Host smart-d17f9618-da68-4fe9-995f-e529a3e3278b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725803660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.725803660
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.2402886537
Short name T483
Test name
Test status
Simulation time 188730601 ps
CPU time 0.83 seconds
Started Aug 03 05:00:21 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 201308 kb
Host smart-2b7b8851-574f-48c7-9f51-49be092f09bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402886537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2402886537
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2532356281
Short name T371
Test name
Test status
Simulation time 102295160 ps
CPU time 0.75 seconds
Started Aug 03 05:00:19 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198080 kb
Host smart-b546dd15-9ff0-4821-ad81-2bc99c8002aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532356281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2532356281
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2292707249
Short name T238
Test name
Test status
Simulation time 38865563 ps
CPU time 0.72 seconds
Started Aug 03 05:00:20 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 199308 kb
Host smart-ca7cd8c4-8fd9-44ce-a581-1b13a6ab0168
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292707249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2292707249
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.1776847149
Short name T543
Test name
Test status
Simulation time 48518716 ps
CPU time 0.76 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:18 PM PDT 24
Peak memory 199108 kb
Host smart-d1ace111-018a-4c2e-9b7c-9f4388381fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776847149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.1776847149
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.3313611809
Short name T138
Test name
Test status
Simulation time 63519769 ps
CPU time 0.64 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 198316 kb
Host smart-d2f0fc8e-e004-40d7-a4c0-9cc1bd22f04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313611809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.3313611809
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3431500139
Short name T556
Test name
Test status
Simulation time 32172170 ps
CPU time 0.6 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198036 kb
Host smart-02441544-1c30-4ef5-9e2d-ac25edb98c1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431500139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3431500139
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.244424594
Short name T573
Test name
Test status
Simulation time 165771603 ps
CPU time 0.94 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198112 kb
Host smart-c995fcdd-eee8-43c8-9fe4-467d84092d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244424594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.244424594
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.981155756
Short name T248
Test name
Test status
Simulation time 48935910 ps
CPU time 0.67 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 198088 kb
Host smart-8a63e82c-ebfa-46f7-803e-b8df79a8c844
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981155756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.981155756
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3180908267
Short name T255
Test name
Test status
Simulation time 23647442 ps
CPU time 0.6 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 198068 kb
Host smart-f9f097e9-2e7f-4d31-9e9f-501812f970cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180908267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3180908267
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.840171188
Short name T179
Test name
Test status
Simulation time 78441747 ps
CPU time 0.66 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:45 PM PDT 24
Peak memory 201380 kb
Host smart-726babf5-63f1-4c87-a00a-ce6196799f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840171188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invali
d.840171188
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.3346393625
Short name T211
Test name
Test status
Simulation time 59456452 ps
CPU time 0.64 seconds
Started Aug 03 05:00:19 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 198496 kb
Host smart-7899a406-a6db-4704-8c85-911ad39ca2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346393625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.3346393625
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1357113456
Short name T226
Test name
Test status
Simulation time 45918322 ps
CPU time 0.8 seconds
Started Aug 03 05:00:22 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 199144 kb
Host smart-3a0c9de2-f892-42a7-a364-2e512ca4a5eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357113456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1357113456
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1112800504
Short name T243
Test name
Test status
Simulation time 151795372 ps
CPU time 0.82 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 209504 kb
Host smart-3e5b48fb-f42a-4de6-9779-309a3fdb0a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112800504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1112800504
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1651946375
Short name T36
Test name
Test status
Simulation time 56966497 ps
CPU time 0.77 seconds
Started Aug 03 05:00:18 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 198292 kb
Host smart-ec6ba4f8-1e2a-4010-9a4a-bbbf69f44eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651946375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1651946375
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3532083141
Short name T351
Test name
Test status
Simulation time 30247123 ps
CPU time 0.65 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198488 kb
Host smart-4318d9ca-882d-46f3-8f62-ce187f6bbf91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532083141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3532083141
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3675471002
Short name T196
Test name
Test status
Simulation time 45846720 ps
CPU time 0.86 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 200224 kb
Host smart-36c307b4-85bc-4fbf-beed-6d70cac70f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675471002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3675471002
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3096400238
Short name T555
Test name
Test status
Simulation time 62078360 ps
CPU time 0.77 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 199096 kb
Host smart-1071c090-e475-4160-ace0-7a1ce41e6cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096400238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3096400238
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1555100146
Short name T301
Test name
Test status
Simulation time 37834765 ps
CPU time 0.59 seconds
Started Aug 03 05:00:33 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 198040 kb
Host smart-6e686e5a-6341-4980-a341-62c2fb58743a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555100146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1555100146
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.434838022
Short name T364
Test name
Test status
Simulation time 471766733 ps
CPU time 0.96 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198124 kb
Host smart-e78d2aef-bfe7-4676-982b-68facdfba15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434838022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.434838022
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2975012705
Short name T558
Test name
Test status
Simulation time 41884799 ps
CPU time 0.64 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198108 kb
Host smart-be4ec342-f9d4-413a-8cc0-b96b8af5384b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975012705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2975012705
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.3968387492
Short name T586
Test name
Test status
Simulation time 41733268 ps
CPU time 0.62 seconds
Started Aug 03 05:00:42 PM PDT 24
Finished Aug 03 05:00:43 PM PDT 24
Peak memory 197912 kb
Host smart-1b15cb7a-6ffa-474c-9c78-605be845b84e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968387492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3968387492
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.44097551
Short name T175
Test name
Test status
Simulation time 43028970 ps
CPU time 0.76 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 201216 kb
Host smart-171e4e37-8b9e-4d23-b97f-66df1ab1de76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44097551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid
.44097551
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1586122941
Short name T321
Test name
Test status
Simulation time 66479444 ps
CPU time 0.83 seconds
Started Aug 03 05:00:48 PM PDT 24
Finished Aug 03 05:00:49 PM PDT 24
Peak memory 198988 kb
Host smart-70fb615f-9e14-409f-82f9-f0240c37ccc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586122941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1586122941
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1007286722
Short name T530
Test name
Test status
Simulation time 108998719 ps
CPU time 0.86 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 209444 kb
Host smart-dc13c5c5-69f1-4788-bdc6-ef7a508b7481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007286722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1007286722
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.4127657215
Short name T353
Test name
Test status
Simulation time 58508165 ps
CPU time 0.81 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 197864 kb
Host smart-0b717714-e6fc-4ed8-ac46-285c72de9c39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127657215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4127657215
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.916597479
Short name T522
Test name
Test status
Simulation time 58026549 ps
CPU time 0.63 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198560 kb
Host smart-cc3e7199-df27-47fd-b14b-862bb7e81538
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916597479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.916597479
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2406109791
Short name T96
Test name
Test status
Simulation time 83510684 ps
CPU time 0.68 seconds
Started Aug 03 05:00:42 PM PDT 24
Finished Aug 03 05:00:42 PM PDT 24
Peak memory 198784 kb
Host smart-b21c1e0b-c052-4d80-85f0-abb0a62116e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406109791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2406109791
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3398077126
Short name T134
Test name
Test status
Simulation time 75024532 ps
CPU time 0.67 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198300 kb
Host smart-7b1bf97b-cc8d-4dfa-a73f-b0752a8355d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398077126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3398077126
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2837272468
Short name T442
Test name
Test status
Simulation time 40093978 ps
CPU time 0.59 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 197312 kb
Host smart-6fc5eccb-0c4e-4b51-9ced-20c18db1923b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837272468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.2837272468
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.155110510
Short name T446
Test name
Test status
Simulation time 2999048186 ps
CPU time 0.94 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 197984 kb
Host smart-31f461fd-933d-4d8a-8881-95ea1d10cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155110510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.155110510
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.129942947
Short name T578
Test name
Test status
Simulation time 48548368 ps
CPU time 0.61 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198080 kb
Host smart-4f935f57-73f0-4747-9763-d20ed62b5c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129942947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.129942947
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.452145324
Short name T336
Test name
Test status
Simulation time 38567004 ps
CPU time 0.6 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198080 kb
Host smart-8644f6ea-5774-477d-b72f-38db6704f769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452145324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.452145324
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.668743963
Short name T554
Test name
Test status
Simulation time 85654786 ps
CPU time 0.67 seconds
Started Aug 03 05:00:44 PM PDT 24
Finished Aug 03 05:00:45 PM PDT 24
Peak memory 201340 kb
Host smart-aaad8691-c824-48d9-ab78-8b9332705b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668743963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.668743963
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.540071641
Short name T215
Test name
Test status
Simulation time 44858870 ps
CPU time 0.72 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 198936 kb
Host smart-6860be72-d710-4277-a254-fad1a5bdfa20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540071641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.540071641
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.733678425
Short name T361
Test name
Test status
Simulation time 111167990 ps
CPU time 1.05 seconds
Started Aug 03 05:00:33 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 209256 kb
Host smart-b0af6a4e-041d-4e63-b521-6cd1b3d55ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733678425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.733678425
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1896647884
Short name T35
Test name
Test status
Simulation time 54885655 ps
CPU time 0.74 seconds
Started Aug 03 05:00:23 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 198168 kb
Host smart-f5aaf2e0-30be-4ccd-af74-8aa24fd6bf02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896647884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1896647884
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.4188538839
Short name T415
Test name
Test status
Simulation time 45270238 ps
CPU time 0.64 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198492 kb
Host smart-64a2ef05-5e9b-47c0-a74d-5fb510ed40f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188538839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.4188538839
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.1674708213
Short name T459
Test name
Test status
Simulation time 60131920 ps
CPU time 0.91 seconds
Started Aug 03 05:00:46 PM PDT 24
Finished Aug 03 05:00:47 PM PDT 24
Peak memory 200340 kb
Host smart-ad19b1cd-97f5-44c3-9c84-02149262d328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674708213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.1674708213
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.2138152403
Short name T352
Test name
Test status
Simulation time 96031282 ps
CPU time 0.65 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 198616 kb
Host smart-cc9a08b1-ef62-4a39-a419-5fe06f390eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138152403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2138152403
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.264710703
Short name T157
Test name
Test status
Simulation time 72353341 ps
CPU time 0.68 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198280 kb
Host smart-a9aa3a61-ff24-4844-b73b-ce3cf004ba43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264710703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disa
ble_rom_integrity_check.264710703
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.2412208205
Short name T265
Test name
Test status
Simulation time 27568181 ps
CPU time 0.67 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198036 kb
Host smart-f2656c61-18c3-4c83-b825-d28991794e54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412208205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.2412208205
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2436321486
Short name T245
Test name
Test status
Simulation time 495857100 ps
CPU time 1 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198104 kb
Host smart-34344955-925d-4935-bd0e-e1484e71aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436321486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2436321486
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3175116894
Short name T258
Test name
Test status
Simulation time 41600383 ps
CPU time 0.69 seconds
Started Aug 03 05:00:32 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 197356 kb
Host smart-220a78bf-27fa-4ab7-bc0d-a55862c91735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175116894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3175116894
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1221670924
Short name T407
Test name
Test status
Simulation time 50950573 ps
CPU time 0.62 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 198104 kb
Host smart-4a7bc578-6f32-4cba-ba51-3c5d0138c975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221670924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1221670924
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.927650972
Short name T170
Test name
Test status
Simulation time 42605393 ps
CPU time 0.75 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 201380 kb
Host smart-945ca9dd-0eef-4cf0-9af5-d3d59698cfd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927650972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invali
d.927650972
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.4186840654
Short name T359
Test name
Test status
Simulation time 82105646 ps
CPU time 0.71 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 199096 kb
Host smart-8fde8e84-580d-4898-a2e7-feb2468a23a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186840654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.4186840654
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.3609645799
Short name T498
Test name
Test status
Simulation time 103460802 ps
CPU time 0.83 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 209508 kb
Host smart-04309fc2-d116-4b01-81be-6eaeed4aa2f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609645799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3609645799
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2131364660
Short name T355
Test name
Test status
Simulation time 50556521 ps
CPU time 0.83 seconds
Started Aug 03 05:00:32 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 198080 kb
Host smart-d42b4a06-b064-4ba1-906f-1b49513eec7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131364660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2131364660
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1097597152
Short name T457
Test name
Test status
Simulation time 52303177 ps
CPU time 0.64 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 198456 kb
Host smart-5b18258a-ea4c-49f5-a8ec-f67075952baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097597152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1097597152
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2381215080
Short name T590
Test name
Test status
Simulation time 22002589 ps
CPU time 0.63 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 198492 kb
Host smart-b9c5a93b-2d55-47c8-8d3e-6d9b1b4dc022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381215080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2381215080
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3496556355
Short name T596
Test name
Test status
Simulation time 51925013 ps
CPU time 0.8 seconds
Started Aug 03 04:58:53 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 199212 kb
Host smart-d5639975-c704-4a4a-82bd-c42acdeffebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496556355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3496556355
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1298581770
Short name T454
Test name
Test status
Simulation time 37807672 ps
CPU time 0.59 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 198056 kb
Host smart-d57a031c-cec2-4f98-be13-1f2de05230dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298581770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1298581770
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.494275624
Short name T475
Test name
Test status
Simulation time 626255477 ps
CPU time 0.98 seconds
Started Aug 03 04:58:56 PM PDT 24
Finished Aug 03 04:58:57 PM PDT 24
Peak memory 198092 kb
Host smart-c199eb88-56ad-428e-ae54-a4e68e2c73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494275624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.494275624
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2992817382
Short name T42
Test name
Test status
Simulation time 59754165 ps
CPU time 0.72 seconds
Started Aug 03 04:58:53 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 197296 kb
Host smart-c87e29af-176e-4681-8f56-c596241349af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992817382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2992817382
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2940951085
Short name T324
Test name
Test status
Simulation time 23924710 ps
CPU time 0.63 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 198384 kb
Host smart-85226578-4470-41cd-a50e-50554cee2d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940951085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2940951085
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.3261418280
Short name T47
Test name
Test status
Simulation time 94788318 ps
CPU time 0.87 seconds
Started Aug 03 04:58:47 PM PDT 24
Finished Aug 03 04:58:48 PM PDT 24
Peak memory 199136 kb
Host smart-422eebf4-90ef-406a-bf87-bb0937b1c284
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261418280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3261418280
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.3418968438
Short name T632
Test name
Test status
Simulation time 108791618 ps
CPU time 1.13 seconds
Started Aug 03 04:58:53 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 209496 kb
Host smart-bfd58240-61ba-4421-9bdf-e3cfbfac84cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418968438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.3418968438
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2893055679
Short name T21
Test name
Test status
Simulation time 1324868869 ps
CPU time 1.46 seconds
Started Aug 03 04:58:56 PM PDT 24
Finished Aug 03 04:58:57 PM PDT 24
Peak memory 219508 kb
Host smart-311c2435-61c4-4fab-9a00-04457d60436a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893055679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2893055679
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1008046857
Short name T299
Test name
Test status
Simulation time 58871723 ps
CPU time 0.85 seconds
Started Aug 03 04:58:53 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 199144 kb
Host smart-70cb59e7-9410-441a-ae98-787935155b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008046857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1008046857
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1700255895
Short name T391
Test name
Test status
Simulation time 33214872 ps
CPU time 0.66 seconds
Started Aug 03 04:58:45 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 198584 kb
Host smart-b1719cbb-f241-4a9f-9d2a-41c3e63ff302
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700255895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1700255895
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.3804743603
Short name T89
Test name
Test status
Simulation time 53922079 ps
CPU time 0.71 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 198776 kb
Host smart-49b88c23-21ef-46c9-a477-2511ff061aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804743603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.3804743603
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3662411196
Short name T133
Test name
Test status
Simulation time 67372192 ps
CPU time 0.71 seconds
Started Aug 03 05:00:33 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 198252 kb
Host smart-7e3370ab-5cd8-4197-a7d0-c4d2d6fe228c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662411196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3662411196
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1203627579
Short name T280
Test name
Test status
Simulation time 84556554 ps
CPU time 0.59 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 197296 kb
Host smart-c752b3c0-fa26-4ce5-8e6b-35b8ebede4b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203627579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1203627579
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.209885417
Short name T491
Test name
Test status
Simulation time 166174302 ps
CPU time 0.95 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 198328 kb
Host smart-1f7e38f5-7264-4407-84a2-e72149877ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209885417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.209885417
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1106809599
Short name T392
Test name
Test status
Simulation time 40738669 ps
CPU time 0.65 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 198080 kb
Host smart-2e885a60-3f36-47e4-98a5-8a5b38c4bcd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106809599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1106809599
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.279395709
Short name T232
Test name
Test status
Simulation time 115687669 ps
CPU time 0.59 seconds
Started Aug 03 05:00:33 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 198348 kb
Host smart-d1291175-de3f-4901-985e-5dbfa0b6c84c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279395709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.279395709
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.4204622207
Short name T523
Test name
Test status
Simulation time 120493259 ps
CPU time 0.68 seconds
Started Aug 03 05:00:41 PM PDT 24
Finished Aug 03 05:00:42 PM PDT 24
Peak memory 201348 kb
Host smart-4436009a-b4b1-45cb-bd9b-5257a4eaeaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204622207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.4204622207
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.4072779877
Short name T587
Test name
Test status
Simulation time 40241097 ps
CPU time 0.62 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 198268 kb
Host smart-fc8fc932-be0a-40bf-a552-9be3e37e4716
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072779877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.4072779877
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.1629514732
Short name T367
Test name
Test status
Simulation time 62628494 ps
CPU time 0.9 seconds
Started Aug 03 05:00:32 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 199188 kb
Host smart-d6941e51-c03a-4d7e-b2ad-5fc4719a5bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629514732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1629514732
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.4144436164
Short name T403
Test name
Test status
Simulation time 115104636 ps
CPU time 0.88 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 209484 kb
Host smart-d0a8e427-83e5-4298-a44b-085bc84eafa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144436164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.4144436164
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.832283884
Short name T477
Test name
Test status
Simulation time 63979328 ps
CPU time 0.95 seconds
Started Aug 03 05:00:34 PM PDT 24
Finished Aug 03 05:00:35 PM PDT 24
Peak memory 199236 kb
Host smart-e126070f-be92-4e5b-a21c-0b37cc928002
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832283884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_
mubi.832283884
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1779855606
Short name T557
Test name
Test status
Simulation time 61255720 ps
CPU time 0.64 seconds
Started Aug 03 05:00:38 PM PDT 24
Finished Aug 03 05:00:39 PM PDT 24
Peak memory 198540 kb
Host smart-f985cfa1-0220-4383-a3ca-b7dd49974554
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779855606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1779855606
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1686640026
Short name T5
Test name
Test status
Simulation time 88670548 ps
CPU time 0.83 seconds
Started Aug 03 05:00:32 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 200028 kb
Host smart-783efbc0-4954-4e8d-a818-9241d866b394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686640026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1686640026
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2739047984
Short name T333
Test name
Test status
Simulation time 65899579 ps
CPU time 0.65 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 199184 kb
Host smart-cdf13af7-d9fe-414a-9996-77baf6b44449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739047984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2739047984
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.937177933
Short name T244
Test name
Test status
Simulation time 30044635 ps
CPU time 0.65 seconds
Started Aug 03 05:00:29 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 198064 kb
Host smart-b7a2a799-5df5-4f10-bfc7-e16f51433a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937177933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_
malfunc.937177933
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.888414338
Short name T546
Test name
Test status
Simulation time 168047246 ps
CPU time 0.91 seconds
Started Aug 03 05:00:32 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 198388 kb
Host smart-b7e4f3f4-0263-43b5-8b62-b3161768ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888414338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.888414338
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3635511818
Short name T465
Test name
Test status
Simulation time 62808384 ps
CPU time 0.61 seconds
Started Aug 03 05:00:33 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 198108 kb
Host smart-b1680630-1d26-435d-b13e-ca753898fc1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635511818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3635511818
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1936592593
Short name T462
Test name
Test status
Simulation time 81166212 ps
CPU time 0.62 seconds
Started Aug 03 05:00:37 PM PDT 24
Finished Aug 03 05:00:38 PM PDT 24
Peak memory 198084 kb
Host smart-1ad2fa1c-1aa8-43de-8b3d-7f9f004138da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936592593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1936592593
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1588910602
Short name T552
Test name
Test status
Simulation time 190290458 ps
CPU time 0.69 seconds
Started Aug 03 05:00:51 PM PDT 24
Finished Aug 03 05:00:56 PM PDT 24
Peak memory 201336 kb
Host smart-3418fc2c-9253-4a15-aac6-a0d1a95b5e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588910602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1588910602
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.4085466087
Short name T588
Test name
Test status
Simulation time 47171828 ps
CPU time 0.78 seconds
Started Aug 03 05:00:31 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 199116 kb
Host smart-2ff1a508-a0d7-4e0f-aaa6-c9c45d849594
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085466087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.4085466087
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.4018137495
Short name T452
Test name
Test status
Simulation time 466927086 ps
CPU time 0.81 seconds
Started Aug 03 05:00:37 PM PDT 24
Finished Aug 03 05:00:38 PM PDT 24
Peak memory 209424 kb
Host smart-48ef051f-6c34-4548-9837-5a761cb520fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018137495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.4018137495
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.4259758834
Short name T490
Test name
Test status
Simulation time 56222793 ps
CPU time 0.78 seconds
Started Aug 03 05:00:38 PM PDT 24
Finished Aug 03 05:00:39 PM PDT 24
Peak memory 198132 kb
Host smart-0d2f4b7b-2d65-42bf-96e7-a66b22a677d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259758834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4259758834
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.167844323
Short name T120
Test name
Test status
Simulation time 41255751 ps
CPU time 0.69 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 198500 kb
Host smart-c97bd125-0d8e-49a4-a51a-78427c8fbec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167844323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.167844323
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.257192137
Short name T144
Test name
Test status
Simulation time 63093565 ps
CPU time 0.72 seconds
Started Aug 03 05:00:30 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 198280 kb
Host smart-8f45a2a4-ede3-4733-9432-99f44974e025
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257192137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.257192137
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.2496869565
Short name T453
Test name
Test status
Simulation time 89117455 ps
CPU time 0.69 seconds
Started Aug 03 05:00:37 PM PDT 24
Finished Aug 03 05:00:38 PM PDT 24
Peak memory 198652 kb
Host smart-e43c4704-5088-4bd7-b304-478f9f66a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496869565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2496869565
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.232848006
Short name T408
Test name
Test status
Simulation time 61244420 ps
CPU time 0.8 seconds
Started Aug 03 05:00:50 PM PDT 24
Finished Aug 03 05:00:51 PM PDT 24
Peak memory 198424 kb
Host smart-374ea869-68f7-4dbf-be78-9eaa2820ee71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232848006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.232848006
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3595703468
Short name T577
Test name
Test status
Simulation time 39002518 ps
CPU time 0.6 seconds
Started Aug 03 05:00:35 PM PDT 24
Finished Aug 03 05:00:36 PM PDT 24
Peak memory 198008 kb
Host smart-4f9c1b68-1cb5-4580-a088-d34f91cc21ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595703468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3595703468
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.2432382826
Short name T575
Test name
Test status
Simulation time 786300194 ps
CPU time 0.98 seconds
Started Aug 03 05:00:49 PM PDT 24
Finished Aug 03 05:00:50 PM PDT 24
Peak memory 198004 kb
Host smart-873a4082-bdf2-4258-9e8f-a55c65fdef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432382826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2432382826
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.1185135514
Short name T241
Test name
Test status
Simulation time 78627440 ps
CPU time 0.64 seconds
Started Aug 03 05:00:39 PM PDT 24
Finished Aug 03 05:00:39 PM PDT 24
Peak memory 197308 kb
Host smart-19afaf65-0e25-401f-a8c5-7ef7c460cae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185135514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1185135514
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1651666986
Short name T374
Test name
Test status
Simulation time 36337427 ps
CPU time 0.64 seconds
Started Aug 03 05:00:37 PM PDT 24
Finished Aug 03 05:00:38 PM PDT 24
Peak memory 198104 kb
Host smart-b618a601-6219-43c6-bff0-5ac5c52b257a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651666986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1651666986
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3931281604
Short name T539
Test name
Test status
Simulation time 53348198 ps
CPU time 0.77 seconds
Started Aug 03 05:00:49 PM PDT 24
Finished Aug 03 05:00:50 PM PDT 24
Peak memory 201380 kb
Host smart-bf6d4e40-8487-473a-8044-e52266f230f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931281604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3931281604
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2979621019
Short name T373
Test name
Test status
Simulation time 50707145 ps
CPU time 0.67 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 199152 kb
Host smart-96a43d0e-879a-46c4-8289-17e69ceb40e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979621019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2979621019
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2226602161
Short name T444
Test name
Test status
Simulation time 129423940 ps
CPU time 0.86 seconds
Started Aug 03 05:00:51 PM PDT 24
Finished Aug 03 05:00:52 PM PDT 24
Peak memory 209476 kb
Host smart-bc487e79-5356-4157-8997-19bef76f0089
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226602161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2226602161
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1622243172
Short name T547
Test name
Test status
Simulation time 211582404 ps
CPU time 0.83 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 199352 kb
Host smart-ea165792-995c-451c-850c-b790dbf94bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622243172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1622243172
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.239885088
Short name T626
Test name
Test status
Simulation time 35912997 ps
CPU time 0.69 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 199344 kb
Host smart-c6d86984-2013-403a-a9dd-a09b44006bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239885088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.239885088
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2541249584
Short name T29
Test name
Test status
Simulation time 31602176 ps
CPU time 0.73 seconds
Started Aug 03 05:00:59 PM PDT 24
Finished Aug 03 05:01:00 PM PDT 24
Peak memory 199112 kb
Host smart-9f1d098e-662f-44f6-b637-54e281fb6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541249584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2541249584
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3250653487
Short name T346
Test name
Test status
Simulation time 31071719 ps
CPU time 0.62 seconds
Started Aug 03 05:00:37 PM PDT 24
Finished Aug 03 05:00:38 PM PDT 24
Peak memory 197324 kb
Host smart-9290a21c-50bb-4de2-aa48-fce7a505eec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250653487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3250653487
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3794838968
Short name T597
Test name
Test status
Simulation time 751882643 ps
CPU time 0.96 seconds
Started Aug 03 05:00:38 PM PDT 24
Finished Aug 03 05:00:39 PM PDT 24
Peak memory 198080 kb
Host smart-60e22dc3-9dd8-4934-9b9f-2d730cd2b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794838968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3794838968
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.1787383752
Short name T443
Test name
Test status
Simulation time 57836213 ps
CPU time 0.69 seconds
Started Aug 03 05:00:39 PM PDT 24
Finished Aug 03 05:00:40 PM PDT 24
Peak memory 197352 kb
Host smart-804ca430-0737-43bd-a4ef-4f88bf90d886
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787383752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1787383752
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.92431922
Short name T520
Test name
Test status
Simulation time 45357062 ps
CPU time 0.65 seconds
Started Aug 03 05:00:36 PM PDT 24
Finished Aug 03 05:00:37 PM PDT 24
Peak memory 198084 kb
Host smart-211c3f8b-1a61-4680-b9e5-66ff5df998aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92431922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.92431922
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.104852124
Short name T174
Test name
Test status
Simulation time 40158735 ps
CPU time 0.75 seconds
Started Aug 03 05:00:59 PM PDT 24
Finished Aug 03 05:01:00 PM PDT 24
Peak memory 201412 kb
Host smart-d4d7e508-2a6e-49bf-9435-70f3452afaf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104852124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.104852124
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.898919361
Short name T580
Test name
Test status
Simulation time 63247085 ps
CPU time 0.71 seconds
Started Aug 03 05:00:34 PM PDT 24
Finished Aug 03 05:00:35 PM PDT 24
Peak memory 198276 kb
Host smart-273c76b9-cbf3-4cbd-b5be-52fde31ebeed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898919361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.898919361
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2972049544
Short name T46
Test name
Test status
Simulation time 151818610 ps
CPU time 0.81 seconds
Started Aug 03 05:00:57 PM PDT 24
Finished Aug 03 05:00:58 PM PDT 24
Peak memory 209560 kb
Host smart-1eb41eba-2ea6-4d2f-b03c-7516261343d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972049544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2972049544
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3081306268
Short name T118
Test name
Test status
Simulation time 62165403 ps
CPU time 0.87 seconds
Started Aug 03 05:00:41 PM PDT 24
Finished Aug 03 05:00:42 PM PDT 24
Peak memory 198044 kb
Host smart-11fe683d-303e-4657-9836-a025d9b963a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081306268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3081306268
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.936642998
Short name T296
Test name
Test status
Simulation time 28105269 ps
CPU time 0.64 seconds
Started Aug 03 05:00:39 PM PDT 24
Finished Aug 03 05:00:40 PM PDT 24
Peak memory 198488 kb
Host smart-9f370083-ac62-4918-ad65-02421f5f2f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936642998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.936642998
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2929221499
Short name T628
Test name
Test status
Simulation time 50909090 ps
CPU time 0.7 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 199188 kb
Host smart-8178e53d-65bf-4906-8077-717fb44be3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929221499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2929221499
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.525483254
Short name T139
Test name
Test status
Simulation time 55078012 ps
CPU time 0.81 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198516 kb
Host smart-0b591364-b2ca-4fcc-8442-1e24c9b0d9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525483254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa
ble_rom_integrity_check.525483254
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.719416317
Short name T290
Test name
Test status
Simulation time 29609536 ps
CPU time 0.63 seconds
Started Aug 03 05:00:42 PM PDT 24
Finished Aug 03 05:00:42 PM PDT 24
Peak memory 198016 kb
Host smart-c3e448f7-6bca-4dc9-ade2-f22e3813afb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719416317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_
malfunc.719416317
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2619064179
Short name T508
Test name
Test status
Simulation time 994719393 ps
CPU time 1 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:47 PM PDT 24
Peak memory 198084 kb
Host smart-42f6ec37-fa9a-4e17-a841-bcdf653593f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619064179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2619064179
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1096050275
Short name T300
Test name
Test status
Simulation time 34710361 ps
CPU time 0.65 seconds
Started Aug 03 05:01:02 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 198000 kb
Host smart-024faa56-8d17-434f-837a-619dd0a8f17f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096050275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1096050275
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2808393785
Short name T303
Test name
Test status
Simulation time 42267541 ps
CPU time 0.6 seconds
Started Aug 03 05:01:06 PM PDT 24
Finished Aug 03 05:01:07 PM PDT 24
Peak memory 198116 kb
Host smart-f7cb6568-e054-4a91-905a-71ac3f69513d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808393785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2808393785
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.458892347
Short name T193
Test name
Test status
Simulation time 45762321 ps
CPU time 0.7 seconds
Started Aug 03 05:00:48 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 201400 kb
Host smart-13642a4e-6697-4c66-8fba-97479ff1bb43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458892347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali
d.458892347
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2615938866
Short name T548
Test name
Test status
Simulation time 30798524 ps
CPU time 0.68 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198288 kb
Host smart-eabf5691-97cc-4664-9bfa-62638299877b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615938866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2615938866
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.175188731
Short name T323
Test name
Test status
Simulation time 90396025 ps
CPU time 1.01 seconds
Started Aug 03 05:00:44 PM PDT 24
Finished Aug 03 05:00:45 PM PDT 24
Peak memory 209496 kb
Host smart-5e3ab126-5a75-470c-a92b-b9e78fa59782
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175188731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.175188731
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1104662904
Short name T261
Test name
Test status
Simulation time 77277947 ps
CPU time 0.65 seconds
Started Aug 03 05:00:42 PM PDT 24
Finished Aug 03 05:00:43 PM PDT 24
Peak memory 198136 kb
Host smart-3341f371-ee8f-4f32-ba66-c9112e780892
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104662904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1104662904
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1877035537
Short name T345
Test name
Test status
Simulation time 161794476 ps
CPU time 0.61 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198516 kb
Host smart-ebc9b9e8-af25-44d2-962d-457d42960951
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877035537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1877035537
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.111757775
Short name T377
Test name
Test status
Simulation time 29278432 ps
CPU time 0.87 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 200328 kb
Host smart-23407d73-3c40-48b6-a722-0e97dbafaf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111757775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.111757775
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.663179307
Short name T11
Test name
Test status
Simulation time 31078670 ps
CPU time 0.62 seconds
Started Aug 03 05:00:47 PM PDT 24
Finished Aug 03 05:00:48 PM PDT 24
Peak memory 198056 kb
Host smart-65059522-3426-4607-9c48-48a7d419d942
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663179307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_
malfunc.663179307
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3626167811
Short name T335
Test name
Test status
Simulation time 629553048 ps
CPU time 0.95 seconds
Started Aug 03 05:00:51 PM PDT 24
Finished Aug 03 05:00:52 PM PDT 24
Peak memory 198072 kb
Host smart-a6f6589e-98ee-4a46-be7b-d29d5edf53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626167811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3626167811
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.10237378
Short name T620
Test name
Test status
Simulation time 56424481 ps
CPU time 0.63 seconds
Started Aug 03 05:01:12 PM PDT 24
Finished Aug 03 05:01:13 PM PDT 24
Peak memory 197276 kb
Host smart-b71e9e3b-3024-4360-9a32-1915c1429f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10237378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.10237378
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.4089827217
Short name T376
Test name
Test status
Simulation time 103297906 ps
CPU time 0.59 seconds
Started Aug 03 05:00:54 PM PDT 24
Finished Aug 03 05:00:55 PM PDT 24
Peak memory 198108 kb
Host smart-999cb3bc-8c45-4598-b6a2-5050bf8d3afb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089827217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.4089827217
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1502553274
Short name T207
Test name
Test status
Simulation time 58239544 ps
CPU time 0.71 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 201396 kb
Host smart-ad2355e1-c277-4e38-bb0a-c60b8b2871a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502553274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1502553274
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2945457336
Short name T585
Test name
Test status
Simulation time 55732141 ps
CPU time 0.68 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 198372 kb
Host smart-e6557192-c8d7-4b43-90c1-b2d6c0fe67a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945457336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2945457336
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3309543017
Short name T589
Test name
Test status
Simulation time 107790890 ps
CPU time 0.9 seconds
Started Aug 03 05:00:52 PM PDT 24
Finished Aug 03 05:00:53 PM PDT 24
Peak memory 209460 kb
Host smart-57466b69-fa63-428c-adc1-50528a542ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309543017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3309543017
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1421856210
Short name T81
Test name
Test status
Simulation time 88795587 ps
CPU time 0.72 seconds
Started Aug 03 05:00:45 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 198184 kb
Host smart-b3aa8515-7306-4adc-8450-311c5ca2320d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421856210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1421856210
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1864505602
Short name T1
Test name
Test status
Simulation time 54034894 ps
CPU time 0.64 seconds
Started Aug 03 05:00:58 PM PDT 24
Finished Aug 03 05:00:58 PM PDT 24
Peak memory 198480 kb
Host smart-44fda750-2afe-4a03-a44e-51e8cce29726
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864505602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1864505602
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.1346021723
Short name T434
Test name
Test status
Simulation time 62236015 ps
CPU time 0.64 seconds
Started Aug 03 05:01:05 PM PDT 24
Finished Aug 03 05:01:06 PM PDT 24
Peak memory 198624 kb
Host smart-dc5d28b5-b898-43d9-95cf-b64552e7f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346021723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1346021723
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.181905011
Short name T625
Test name
Test status
Simulation time 71198744 ps
CPU time 0.66 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 198424 kb
Host smart-1b2aea61-7fa8-44e0-a1a6-da6728c1b14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181905011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.181905011
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.898982707
Short name T485
Test name
Test status
Simulation time 28481162 ps
CPU time 0.63 seconds
Started Aug 03 05:01:00 PM PDT 24
Finished Aug 03 05:01:01 PM PDT 24
Peak memory 197948 kb
Host smart-a1e5e5b6-3fc0-4050-90b3-5850ea86e780
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898982707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.898982707
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3757911732
Short name T481
Test name
Test status
Simulation time 599236006 ps
CPU time 1.03 seconds
Started Aug 03 05:01:02 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 198360 kb
Host smart-7de345b1-4675-48eb-a705-9c186cabd495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757911732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3757911732
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2511492039
Short name T496
Test name
Test status
Simulation time 57970591 ps
CPU time 0.6 seconds
Started Aug 03 05:00:52 PM PDT 24
Finished Aug 03 05:00:53 PM PDT 24
Peak memory 197356 kb
Host smart-5144a3e3-7c98-4c00-93d6-3c28f59eaa8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511492039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2511492039
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1668370460
Short name T338
Test name
Test status
Simulation time 32492661 ps
CPU time 0.61 seconds
Started Aug 03 05:01:09 PM PDT 24
Finished Aug 03 05:01:10 PM PDT 24
Peak memory 198104 kb
Host smart-4de816d1-3798-4daf-9df9-fd27807aef52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668370460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1668370460
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.508845093
Short name T187
Test name
Test status
Simulation time 41915064 ps
CPU time 0.69 seconds
Started Aug 03 05:00:48 PM PDT 24
Finished Aug 03 05:00:49 PM PDT 24
Peak memory 201416 kb
Host smart-73c83f37-7110-4749-a505-4a734964bc53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508845093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.508845093
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2387220074
Short name T463
Test name
Test status
Simulation time 38391979 ps
CPU time 0.71 seconds
Started Aug 03 05:01:02 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 199076 kb
Host smart-d966a20a-bd85-4d02-a3ec-b4ebc66c8df3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387220074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2387220074
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1182766327
Short name T494
Test name
Test status
Simulation time 102443607 ps
CPU time 0.94 seconds
Started Aug 03 05:01:05 PM PDT 24
Finished Aug 03 05:01:06 PM PDT 24
Peak memory 209500 kb
Host smart-22764809-2429-4aef-8d04-136513534aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182766327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1182766327
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.418910268
Short name T504
Test name
Test status
Simulation time 319379182 ps
CPU time 0.75 seconds
Started Aug 03 05:01:04 PM PDT 24
Finished Aug 03 05:01:05 PM PDT 24
Peak memory 198132 kb
Host smart-4f1cd42f-6feb-4ecc-9c78-34b533c0c04b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418910268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_
mubi.418910268
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.3188919929
Short name T84
Test name
Test status
Simulation time 58684949 ps
CPU time 0.76 seconds
Started Aug 03 05:01:02 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 199348 kb
Host smart-d5499b83-a292-483c-8e19-3251d3f73df9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188919929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.3188919929
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.3781705116
Short name T169
Test name
Test status
Simulation time 56966567 ps
CPU time 0.65 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 198092 kb
Host smart-877953de-8a4a-4505-a88f-6ee7ca1aa032
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781705116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.3781705116
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2125734916
Short name T98
Test name
Test status
Simulation time 49943513 ps
CPU time 0.64 seconds
Started Aug 03 05:00:51 PM PDT 24
Finished Aug 03 05:00:52 PM PDT 24
Peak memory 199116 kb
Host smart-b3b26436-8f15-4a06-b086-62a9c65a2de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125734916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2125734916
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1387605626
Short name T339
Test name
Test status
Simulation time 75761469 ps
CPU time 0.66 seconds
Started Aug 03 05:00:51 PM PDT 24
Finished Aug 03 05:00:52 PM PDT 24
Peak memory 198304 kb
Host smart-4750cf1c-2425-4375-9845-79b260d7ec7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387605626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1387605626
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2144091892
Short name T551
Test name
Test status
Simulation time 29424862 ps
CPU time 0.64 seconds
Started Aug 03 05:00:55 PM PDT 24
Finished Aug 03 05:00:55 PM PDT 24
Peak memory 198056 kb
Host smart-649bb16c-a13a-44d1-b867-03506e28a47f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144091892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.2144091892
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.3434098291
Short name T560
Test name
Test status
Simulation time 1095551429 ps
CPU time 0.94 seconds
Started Aug 03 05:00:52 PM PDT 24
Finished Aug 03 05:00:53 PM PDT 24
Peak memory 198084 kb
Host smart-a48388d8-6df3-4d52-afbd-bad3ae64fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434098291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.3434098291
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1890742389
Short name T497
Test name
Test status
Simulation time 41851084 ps
CPU time 0.63 seconds
Started Aug 03 05:00:58 PM PDT 24
Finished Aug 03 05:00:59 PM PDT 24
Peak memory 197564 kb
Host smart-3b9aed5e-da40-4a12-b6bb-1af7828c2cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890742389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1890742389
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.1683894376
Short name T471
Test name
Test status
Simulation time 29749952 ps
CPU time 0.57 seconds
Started Aug 03 05:00:48 PM PDT 24
Finished Aug 03 05:00:49 PM PDT 24
Peak memory 198124 kb
Host smart-bd00f887-fc1b-4e16-8d7f-7e2f3e238d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683894376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1683894376
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1768691577
Short name T610
Test name
Test status
Simulation time 147031155 ps
CPU time 0.68 seconds
Started Aug 03 05:00:59 PM PDT 24
Finished Aug 03 05:01:00 PM PDT 24
Peak memory 201376 kb
Host smart-83e37783-e1ae-48cd-a5fd-1c4df427e63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768691577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1768691577
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.59884218
Short name T292
Test name
Test status
Simulation time 36716610 ps
CPU time 0.64 seconds
Started Aug 03 05:00:50 PM PDT 24
Finished Aug 03 05:00:51 PM PDT 24
Peak memory 198108 kb
Host smart-59958d6e-48b9-4af3-8d74-a2ec9eb1399c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59884218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.59884218
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1760871245
Short name T320
Test name
Test status
Simulation time 153122988 ps
CPU time 0.86 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 201364 kb
Host smart-6bde7961-b3d3-4b82-8d18-32c4a37afcba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760871245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1760871245
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3886700570
Short name T176
Test name
Test status
Simulation time 37183375 ps
CPU time 0.62 seconds
Started Aug 03 05:00:59 PM PDT 24
Finished Aug 03 05:01:00 PM PDT 24
Peak memory 198480 kb
Host smart-3123be39-4935-4039-b870-1bf98b457829
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886700570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.3886700570
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.4047978984
Short name T279
Test name
Test status
Simulation time 88772231 ps
CPU time 0.68 seconds
Started Aug 03 05:01:06 PM PDT 24
Finished Aug 03 05:01:07 PM PDT 24
Peak memory 197720 kb
Host smart-d53898dc-be9b-4903-a86b-22106fa98434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047978984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4047978984
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1073834294
Short name T230
Test name
Test status
Simulation time 61868895 ps
CPU time 0.63 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 198500 kb
Host smart-2bc65861-7208-4bf9-aa6f-8aa0d500ed6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073834294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1073834294
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.823115748
Short name T484
Test name
Test status
Simulation time 61970191 ps
CPU time 0.75 seconds
Started Aug 03 05:00:58 PM PDT 24
Finished Aug 03 05:00:59 PM PDT 24
Peak memory 198836 kb
Host smart-05dfd149-c65e-4338-a221-cfaca72fd961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823115748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.823115748
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1680458002
Short name T582
Test name
Test status
Simulation time 66163448 ps
CPU time 0.81 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 198452 kb
Host smart-b1772430-291a-47b5-a993-a9fc843e2468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680458002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1680458002
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2297762114
Short name T379
Test name
Test status
Simulation time 28564901 ps
CPU time 0.61 seconds
Started Aug 03 05:01:14 PM PDT 24
Finished Aug 03 05:01:15 PM PDT 24
Peak memory 197244 kb
Host smart-623c0cc5-7859-419e-8da1-6f2d7dad7f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297762114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2297762114
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2364770815
Short name T277
Test name
Test status
Simulation time 160051609 ps
CPU time 0.94 seconds
Started Aug 03 05:01:07 PM PDT 24
Finished Aug 03 05:01:08 PM PDT 24
Peak memory 198104 kb
Host smart-95b14d69-8125-40f7-822a-5aa1da65b5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364770815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2364770815
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.4173777922
Short name T26
Test name
Test status
Simulation time 34724055 ps
CPU time 0.66 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:54 PM PDT 24
Peak memory 197912 kb
Host smart-8e809ed6-f3f5-4f76-9eb1-4980125ee9d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173777922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.4173777922
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3434977940
Short name T218
Test name
Test status
Simulation time 229665910 ps
CPU time 0.6 seconds
Started Aug 03 05:00:53 PM PDT 24
Finished Aug 03 05:00:53 PM PDT 24
Peak memory 197972 kb
Host smart-219f729b-9e18-409a-baa2-1da24e678d6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434977940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3434977940
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.721191343
Short name T197
Test name
Test status
Simulation time 137337419 ps
CPU time 0.67 seconds
Started Aug 03 05:01:09 PM PDT 24
Finished Aug 03 05:01:10 PM PDT 24
Peak memory 201432 kb
Host smart-cd9cf47a-a857-4d6d-aac2-a8f897fb8590
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721191343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invali
d.721191343
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.4018402814
Short name T568
Test name
Test status
Simulation time 93377886 ps
CPU time 0.78 seconds
Started Aug 03 05:00:48 PM PDT 24
Finished Aug 03 05:00:49 PM PDT 24
Peak memory 199120 kb
Host smart-9df70f1c-8823-40eb-ab33-c764da098e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018402814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.4018402814
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1463124635
Short name T467
Test name
Test status
Simulation time 100270872 ps
CPU time 0.89 seconds
Started Aug 03 05:01:15 PM PDT 24
Finished Aug 03 05:01:16 PM PDT 24
Peak memory 209464 kb
Host smart-709634f8-4059-41c4-8635-fd46cec10e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463124635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1463124635
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3826104829
Short name T287
Test name
Test status
Simulation time 107428521 ps
CPU time 0.76 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 198048 kb
Host smart-0765892e-e656-4219-87c3-5031eb7ddc1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826104829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3826104829
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3568518264
Short name T538
Test name
Test status
Simulation time 69011992 ps
CPU time 0.63 seconds
Started Aug 03 05:01:05 PM PDT 24
Finished Aug 03 05:01:06 PM PDT 24
Peak memory 199396 kb
Host smart-4a0ab0d7-49e3-4e34-a1ce-d50b349b131d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568518264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3568518264
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3203272333
Short name T59
Test name
Test status
Simulation time 112015984 ps
CPU time 0.66 seconds
Started Aug 03 05:01:12 PM PDT 24
Finished Aug 03 05:01:12 PM PDT 24
Peak memory 199180 kb
Host smart-b56f2773-4bc1-484e-a0be-3b8351e0087d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203272333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3203272333
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.556805907
Short name T219
Test name
Test status
Simulation time 38776496 ps
CPU time 0.59 seconds
Started Aug 03 05:01:05 PM PDT 24
Finished Aug 03 05:01:06 PM PDT 24
Peak memory 198008 kb
Host smart-875fead2-ecb2-4d96-919b-7374e4786096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556805907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.556805907
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3677641543
Short name T274
Test name
Test status
Simulation time 161809116 ps
CPU time 0.97 seconds
Started Aug 03 05:01:00 PM PDT 24
Finished Aug 03 05:01:02 PM PDT 24
Peak memory 198116 kb
Host smart-37306d20-5cff-4a46-816f-240b04034974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677641543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3677641543
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.98859365
Short name T18
Test name
Test status
Simulation time 43723563 ps
CPU time 0.61 seconds
Started Aug 03 05:00:56 PM PDT 24
Finished Aug 03 05:00:57 PM PDT 24
Peak memory 198156 kb
Host smart-8d357bbc-d453-4627-aa8b-a94babaf2422
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98859365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.98859365
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3032434935
Short name T480
Test name
Test status
Simulation time 24223453 ps
CPU time 0.61 seconds
Started Aug 03 05:01:11 PM PDT 24
Finished Aug 03 05:01:12 PM PDT 24
Peak memory 198088 kb
Host smart-8055d196-b127-4186-b6d7-af08a399548c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032434935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3032434935
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2902723116
Short name T183
Test name
Test status
Simulation time 55035599 ps
CPU time 0.68 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 201460 kb
Host smart-26d11672-4275-417c-a695-35589a87ce1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902723116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2902723116
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.232049851
Short name T216
Test name
Test status
Simulation time 54500393 ps
CPU time 0.61 seconds
Started Aug 03 05:01:00 PM PDT 24
Finished Aug 03 05:01:00 PM PDT 24
Peak memory 198188 kb
Host smart-c98f9944-e01b-439b-b87a-5be4b1b22884
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232049851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.232049851
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3740381196
Short name T482
Test name
Test status
Simulation time 107902661 ps
CPU time 0.92 seconds
Started Aug 03 05:01:05 PM PDT 24
Finished Aug 03 05:01:06 PM PDT 24
Peak memory 209472 kb
Host smart-1167a7fe-e125-44aa-9077-33d805747753
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740381196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3740381196
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1005821000
Short name T293
Test name
Test status
Simulation time 61549964 ps
CPU time 0.74 seconds
Started Aug 03 05:01:03 PM PDT 24
Finished Aug 03 05:01:04 PM PDT 24
Peak memory 198208 kb
Host smart-e4e70cd7-36e7-47e0-ba6f-98c6468f4975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005821000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1005821000
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1942937032
Short name T383
Test name
Test status
Simulation time 65231987 ps
CPU time 0.9 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 200148 kb
Host smart-aac81180-8c6a-44f2-83a1-1ed637a636a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942937032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1942937032
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2321178717
Short name T502
Test name
Test status
Simulation time 61198654 ps
CPU time 0.69 seconds
Started Aug 03 04:59:00 PM PDT 24
Finished Aug 03 04:59:01 PM PDT 24
Peak memory 198232 kb
Host smart-f0569091-318b-4e38-9e90-6afbe72d435c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321178717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2321178717
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.750515933
Short name T12
Test name
Test status
Simulation time 37660934 ps
CPU time 0.56 seconds
Started Aug 03 04:58:59 PM PDT 24
Finished Aug 03 04:59:00 PM PDT 24
Peak memory 198088 kb
Host smart-e5cfa24c-c871-4e0f-aa65-91f1e8d2b89d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750515933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.750515933
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2438349452
Short name T128
Test name
Test status
Simulation time 158184479 ps
CPU time 0.98 seconds
Started Aug 03 04:59:01 PM PDT 24
Finished Aug 03 04:59:02 PM PDT 24
Peak memory 198084 kb
Host smart-122edf38-f6a8-49ec-81bb-42d1bdf6a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438349452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2438349452
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.1131734924
Short name T307
Test name
Test status
Simulation time 57455269 ps
CPU time 0.72 seconds
Started Aug 03 04:59:00 PM PDT 24
Finished Aug 03 04:59:01 PM PDT 24
Peak memory 198044 kb
Host smart-f2a80ede-2495-49ac-8a7b-fa683da5fb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131734924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1131734924
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3905224453
Short name T418
Test name
Test status
Simulation time 65921563 ps
CPU time 0.63 seconds
Started Aug 03 04:58:59 PM PDT 24
Finished Aug 03 04:59:00 PM PDT 24
Peak memory 198124 kb
Host smart-6d05d06e-214c-45ed-8841-de02a751ab42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905224453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3905224453
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3472368021
Short name T436
Test name
Test status
Simulation time 85970137 ps
CPU time 0.71 seconds
Started Aug 03 04:58:55 PM PDT 24
Finished Aug 03 04:58:56 PM PDT 24
Peak memory 198116 kb
Host smart-9cd2dbbf-c7e4-4c0e-925d-3eb5579aa80d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472368021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3472368021
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.654724175
Short name T48
Test name
Test status
Simulation time 98954949 ps
CPU time 1.02 seconds
Started Aug 03 04:59:01 PM PDT 24
Finished Aug 03 04:59:02 PM PDT 24
Peak memory 209432 kb
Host smart-19a1c660-f6fd-4e48-8501-5ec390cbce96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654724175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.654724175
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2497350448
Short name T421
Test name
Test status
Simulation time 64432798 ps
CPU time 0.92 seconds
Started Aug 03 04:59:00 PM PDT 24
Finished Aug 03 04:59:01 PM PDT 24
Peak memory 199212 kb
Host smart-df376bdc-90e9-4d9d-8165-ba5a53a50a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497350448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2497350448
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.533266479
Short name T615
Test name
Test status
Simulation time 31461371 ps
CPU time 0.67 seconds
Started Aug 03 04:58:54 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 198544 kb
Host smart-bf0f7ede-b820-45f9-9df1-21cf73c53319
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533266479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.533266479
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.2192350899
Short name T141
Test name
Test status
Simulation time 55477056 ps
CPU time 0.8 seconds
Started Aug 03 04:58:53 PM PDT 24
Finished Aug 03 04:58:54 PM PDT 24
Peak memory 198284 kb
Host smart-5d4e814d-3095-45bd-a355-748d54bfd4cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192350899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.2192350899
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3902230053
Short name T636
Test name
Test status
Simulation time 41632454 ps
CPU time 0.86 seconds
Started Aug 03 04:58:58 PM PDT 24
Finished Aug 03 04:58:59 PM PDT 24
Peak memory 200172 kb
Host smart-49483067-be90-4e7f-a6fb-4cce8a192909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902230053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3902230053
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1046940737
Short name T337
Test name
Test status
Simulation time 59875452 ps
CPU time 0.7 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 198564 kb
Host smart-fac67f48-1d9f-480c-8dc3-d2aa84e95516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046940737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1046940737
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2611058467
Short name T616
Test name
Test status
Simulation time 30896953 ps
CPU time 0.6 seconds
Started Aug 03 04:59:06 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 197960 kb
Host smart-34f588a2-2a3a-4e72-b5d9-d5d02da0b210
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611058467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2611058467
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.4167861745
Short name T501
Test name
Test status
Simulation time 165722786 ps
CPU time 0.99 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 198140 kb
Host smart-844db8c2-4c2c-42c1-b5ed-97c68382381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167861745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4167861745
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3294804570
Short name T439
Test name
Test status
Simulation time 71134293 ps
CPU time 0.64 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 198068 kb
Host smart-6acd4286-3a14-47f5-97fc-facc3a6fe793
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294804570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3294804570
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.3510338907
Short name T278
Test name
Test status
Simulation time 48325947 ps
CPU time 0.63 seconds
Started Aug 03 04:59:06 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 198044 kb
Host smart-6d34f7f1-ee54-453d-bf9f-3cdab9d39355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510338907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3510338907
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2002985519
Short name T173
Test name
Test status
Simulation time 42370745 ps
CPU time 0.77 seconds
Started Aug 03 04:59:08 PM PDT 24
Finished Aug 03 04:59:09 PM PDT 24
Peak memory 201388 kb
Host smart-b43dea9a-0935-4134-a162-8ae8c283f468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002985519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2002985519
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.3229349369
Short name T276
Test name
Test status
Simulation time 50133457 ps
CPU time 0.67 seconds
Started Aug 03 04:59:00 PM PDT 24
Finished Aug 03 04:59:01 PM PDT 24
Peak memory 198332 kb
Host smart-ecaf685d-6eea-45cb-a08b-8536b7b6d110
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229349369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3229349369
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2998092416
Short name T525
Test name
Test status
Simulation time 61271834 ps
CPU time 0.81 seconds
Started Aug 03 04:59:02 PM PDT 24
Finished Aug 03 04:59:03 PM PDT 24
Peak memory 198080 kb
Host smart-deab2177-ab93-47cd-8273-6012d696aeb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998092416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2998092416
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.4266449845
Short name T242
Test name
Test status
Simulation time 32236612 ps
CPU time 0.68 seconds
Started Aug 03 04:58:58 PM PDT 24
Finished Aug 03 04:58:58 PM PDT 24
Peak memory 199272 kb
Host smart-85be71a1-7294-422f-8cee-84f23b2bf1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266449845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.4266449845
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.763965943
Short name T384
Test name
Test status
Simulation time 48036170 ps
CPU time 0.89 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 200040 kb
Host smart-ce058eaf-36e2-4d8d-bb5c-f314ae3c0427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763965943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.763965943
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3206958002
Short name T156
Test name
Test status
Simulation time 51526994 ps
CPU time 0.8 seconds
Started Aug 03 04:59:03 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 199164 kb
Host smart-d6ffb05c-8aae-47d5-97e3-45c1dc54c316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206958002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.3206958002
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.24461618
Short name T521
Test name
Test status
Simulation time 39425342 ps
CPU time 0.61 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 197300 kb
Host smart-9ae3047c-9767-4bda-ad1e-d9d3cf8fd1d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_ma
lfunc.24461618
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2658782039
Short name T605
Test name
Test status
Simulation time 310658262 ps
CPU time 0.99 seconds
Started Aug 03 04:59:04 PM PDT 24
Finished Aug 03 04:59:05 PM PDT 24
Peak memory 198440 kb
Host smart-c29cb47f-05fb-42ae-9472-226bd011e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658782039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2658782039
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3641918171
Short name T624
Test name
Test status
Simulation time 75172895 ps
CPU time 0.62 seconds
Started Aug 03 04:59:05 PM PDT 24
Finished Aug 03 04:59:06 PM PDT 24
Peak memory 197412 kb
Host smart-3c98f8ff-b407-42ef-8282-6c1a92a368ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641918171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3641918171
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.623564246
Short name T369
Test name
Test status
Simulation time 44317105 ps
CPU time 0.71 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 198112 kb
Host smart-5a14f399-cdbe-4e61-9ec0-dd8401c8d612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623564246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.623564246
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2670665426
Short name T189
Test name
Test status
Simulation time 45732641 ps
CPU time 0.74 seconds
Started Aug 03 04:59:03 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 201400 kb
Host smart-f0db894b-d44b-46b7-9566-13bddb062001
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670665426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2670665426
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.759766735
Short name T214
Test name
Test status
Simulation time 86868718 ps
CPU time 0.66 seconds
Started Aug 03 04:59:04 PM PDT 24
Finished Aug 03 04:59:05 PM PDT 24
Peak memory 199124 kb
Host smart-aba83458-f723-4208-ae8a-91a4d14d0172
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759766735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.759766735
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.4292621842
Short name T529
Test name
Test status
Simulation time 100897819 ps
CPU time 0.96 seconds
Started Aug 03 04:59:08 PM PDT 24
Finished Aug 03 04:59:09 PM PDT 24
Peak memory 209584 kb
Host smart-f8862b57-2bd2-4d3a-8c98-8dfe838e9628
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292621842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.4292621842
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.317675697
Short name T402
Test name
Test status
Simulation time 55115992 ps
CPU time 0.8 seconds
Started Aug 03 04:59:05 PM PDT 24
Finished Aug 03 04:59:06 PM PDT 24
Peak memory 198128 kb
Host smart-06a5ec46-5382-4f70-98eb-873534b5a225
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317675697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.317675697
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2812949377
Short name T38
Test name
Test status
Simulation time 56119849 ps
CPU time 0.72 seconds
Started Aug 03 04:59:06 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 198536 kb
Host smart-6ec3b763-cfbf-43bc-a5fa-a76a233c7c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812949377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2812949377
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.2510556664
Short name T427
Test name
Test status
Simulation time 44468698 ps
CPU time 0.85 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 200124 kb
Host smart-19b1815e-d0d4-4b31-8c29-ad054a41e507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510556664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2510556664
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1355139776
Short name T286
Test name
Test status
Simulation time 81158142 ps
CPU time 0.64 seconds
Started Aug 03 04:59:08 PM PDT 24
Finished Aug 03 04:59:09 PM PDT 24
Peak memory 199036 kb
Host smart-fd7fa5af-6589-498c-90b2-5382c585cb86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355139776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1355139776
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.120196743
Short name T357
Test name
Test status
Simulation time 32592952 ps
CPU time 0.61 seconds
Started Aug 03 04:59:05 PM PDT 24
Finished Aug 03 04:59:06 PM PDT 24
Peak memory 198016 kb
Host smart-05e8d70c-ff36-4e85-ab63-6de65f2baf6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120196743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m
alfunc.120196743
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.35364260
Short name T455
Test name
Test status
Simulation time 607008299 ps
CPU time 0.97 seconds
Started Aug 03 04:59:06 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 198444 kb
Host smart-648f91fa-8f15-43d2-a4aa-66b7a5e15a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35364260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.35364260
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.239470111
Short name T231
Test name
Test status
Simulation time 42548322 ps
CPU time 0.71 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 197400 kb
Host smart-9b3c9370-ab82-48e0-b1f3-64d56ce6b01e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239470111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.239470111
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.601198381
Short name T325
Test name
Test status
Simulation time 53336532 ps
CPU time 0.58 seconds
Started Aug 03 04:59:04 PM PDT 24
Finished Aug 03 04:59:05 PM PDT 24
Peak memory 198440 kb
Host smart-a4b394c5-e7aa-4693-8b09-191ad14ab549
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601198381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.601198381
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.4020546556
Short name T49
Test name
Test status
Simulation time 39953760 ps
CPU time 0.76 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 201048 kb
Host smart-aa0efa2c-6565-4fba-bd16-3e803d1e6d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020546556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.4020546556
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2080358194
Short name T468
Test name
Test status
Simulation time 61238417 ps
CPU time 0.69 seconds
Started Aug 03 04:59:09 PM PDT 24
Finished Aug 03 04:59:10 PM PDT 24
Peak memory 198244 kb
Host smart-70e7a663-bfb4-47a6-a2fd-9136cf3e1882
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080358194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2080358194
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.4173295341
Short name T217
Test name
Test status
Simulation time 188128057 ps
CPU time 0.81 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 209476 kb
Host smart-68ae428d-1f7a-43e6-b5c5-faca51ad63be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173295341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.4173295341
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.510608004
Short name T447
Test name
Test status
Simulation time 58152999 ps
CPU time 0.82 seconds
Started Aug 03 04:59:07 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 198276 kb
Host smart-541c8e3d-cdda-428c-ad55-0e0927827b41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510608004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.510608004
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.3245551000
Short name T603
Test name
Test status
Simulation time 27958534 ps
CPU time 0.66 seconds
Started Aug 03 04:59:05 PM PDT 24
Finished Aug 03 04:59:06 PM PDT 24
Peak memory 199344 kb
Host smart-dc8aa052-aabe-4313-b49a-eb93b34f16ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245551000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.3245551000
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2529241907
Short name T326
Test name
Test status
Simulation time 32127510 ps
CPU time 0.76 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 198744 kb
Host smart-8aa19af0-216a-43cc-abf1-6779e608d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529241907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2529241907
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.463418703
Short name T152
Test name
Test status
Simulation time 52311057 ps
CPU time 0.82 seconds
Started Aug 03 04:59:18 PM PDT 24
Finished Aug 03 04:59:19 PM PDT 24
Peak memory 198500 kb
Host smart-878c3531-60d6-4238-8053-f581ca146d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463418703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.463418703
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3429389912
Short name T305
Test name
Test status
Simulation time 27699961 ps
CPU time 0.64 seconds
Started Aug 03 04:59:15 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 196992 kb
Host smart-5e652a94-0989-4810-ab3a-914434752df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429389912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3429389912
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1335680761
Short name T414
Test name
Test status
Simulation time 503633424 ps
CPU time 0.97 seconds
Started Aug 03 04:59:10 PM PDT 24
Finished Aug 03 04:59:11 PM PDT 24
Peak memory 198100 kb
Host smart-84abd9ff-e2c3-4592-b866-157819c438fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335680761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1335680761
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2270830813
Short name T268
Test name
Test status
Simulation time 105094510 ps
CPU time 0.63 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 197416 kb
Host smart-e3dbcd73-3b99-4c2f-8b8d-6829e998f46c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270830813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2270830813
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.30400554
Short name T431
Test name
Test status
Simulation time 50607556 ps
CPU time 0.64 seconds
Started Aug 03 04:59:12 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 198064 kb
Host smart-f221d4d9-8c23-4799-acb4-96316accbc91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.30400554
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.116289524
Short name T581
Test name
Test status
Simulation time 84381147 ps
CPU time 0.9 seconds
Started Aug 03 04:59:16 PM PDT 24
Finished Aug 03 04:59:17 PM PDT 24
Peak memory 198500 kb
Host smart-a2a976e2-c4d1-408a-887c-4890322149d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116289524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.116289524
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.496468903
Short name T372
Test name
Test status
Simulation time 154009656 ps
CPU time 0.79 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:12 PM PDT 24
Peak memory 209500 kb
Host smart-f2d10925-76c9-42d7-b8fc-ea2c46728d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496468903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.496468903
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2019936701
Short name T378
Test name
Test status
Simulation time 163705542 ps
CPU time 0.86 seconds
Started Aug 03 04:59:11 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 199012 kb
Host smart-22984e55-05ed-4d7b-ba9b-59bca2627bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019936701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2019936701
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2881159717
Short name T317
Test name
Test status
Simulation time 45448242 ps
CPU time 0.64 seconds
Started Aug 03 04:59:13 PM PDT 24
Finished Aug 03 04:59:14 PM PDT 24
Peak memory 198660 kb
Host smart-897d306e-e978-45c5-bf73-4d835e9d3af0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881159717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2881159717
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.1196313579
Short name T140
Test name
Test status
Simulation time 66707814 ps
CPU time 0.66 seconds
Started Aug 03 04:59:14 PM PDT 24
Finished Aug 03 04:59:15 PM PDT 24
Peak memory 198308 kb
Host smart-ec490a22-f478-4bc5-b459-555368969f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196313579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1196313579
Directory /workspace/9.pwrmgr_wakeup/latest
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