Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591

1

T10

4

T13

2

T16

2

auto[1]

445

1

T10

3

T16

4

T29

5

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

554

1

T10

2

T13

2

T16

5

auto[1]

482

1

T10

5

T16

1

T29

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

464

1

T10

3

T16

3

T29

2

auto[1]

572

1

T10

4

T13

2

T16

3

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848

1

T10

7

T13

1

T16

4

auto[1]

188

1

T13

1

T16

2

T29

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

453

1

T10

5

T16

1

T29

6

auto[1]

583

1

T10

2

T13

2

T16

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

568

1

T10

4

T13

2

T16

1

auto[1]

468

1

T10

3

T16

5

T29

5

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

23

1

T17

1

T162

1

T163

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T162

1

T163

1

T164

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30

1

T10

1

T27

1

T82

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T27

1

T141

1

T165

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T15

1

T162

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T166

1

T167

1

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

76

1

T13

1

T51

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

58

1

T13

1

T51

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T10

1

T16

1

T82

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T169

1

T170

1

T171

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T55

1

T172

2

T173

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T174

1

T143

1

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T15

1

T54

1

T175

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T175

2

T176

1

T177

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T55

1

T111

1

T178

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T55

1

T49

1

T179

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

22

1

T111

1

T173

1

T180

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T181

1

T182

1

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T10

1

T29

1

T163

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T163

1

T28

1

T50

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25

1

T15

1

T53

1

T163

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T183

1

T184

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T16

1

T176

1

T173

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T170

1

T186

1

T165

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T10

1

T187

1

T112

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T172

1

T188

1

T189

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T27

1

T53

1

T36

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T27

1

T50

1

T190

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T175

1

T86

1

T111

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T191

1

T50

1

T192

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

34

1

T17

1

T53

2

T54

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T50

1

T193

1

T140

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

29

1

T15

1

T194

2

T162

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T171

1

T195

2

T196

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20

1

T15

1

T53

1

T112

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T167

1

T197

1

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

21

1

T54

2

T112

1

T169

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T169

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T14

1

T17

3

T173

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T14

1

T198

1

T50

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

16

1

T29

1

T54

2

T173

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T29

1

T199

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T15

1

T53

3

T176

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T176

1

T142

1

T200

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T16

1

T162

1

T170

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T16

1

T162

1

T28

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T16

1

T54

1

T82

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T16

1

T49

1

T184

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

27

1

T15

1

T55

1

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T27

1

T164

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T10

1

T14

1

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T14

1

T188

1

T190

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T10

1

T15

1

T53

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T194

1

T201

1

T193

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T55

1

T112

1

T36

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T55

1

T202

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

22

1

T54

1

T187

1

T183

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T187

1

T183

1

T191

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T29

2

T36

1

T173

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T29

1

T50

1

T168

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T17

2

T54

1

T183

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T203

1

T204

1

T205

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T10

1

T14

1

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T14

1

T187

1

T172

1