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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 98.23 96.15 99.44 96.00 96.18 100.00 96.24


Total test records in report: 736
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T564 /workspace/coverage/default/4.pwrmgr_glitch.2939064737 Aug 04 05:15:36 PM PDT 24 Aug 04 05:15:37 PM PDT 24 102679994 ps
T565 /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.355880539 Aug 04 05:17:15 PM PDT 24 Aug 04 05:17:16 PM PDT 24 55369673 ps
T566 /workspace/coverage/default/18.pwrmgr_escalation_timeout.2275163690 Aug 04 05:16:21 PM PDT 24 Aug 04 05:16:22 PM PDT 24 166292425 ps
T567 /workspace/coverage/default/12.pwrmgr_glitch.2595206381 Aug 04 05:16:00 PM PDT 24 Aug 04 05:16:01 PM PDT 24 34706159 ps
T568 /workspace/coverage/default/24.pwrmgr_aborted_low_power.805683909 Aug 04 05:16:22 PM PDT 24 Aug 04 05:16:23 PM PDT 24 43855581 ps
T569 /workspace/coverage/default/32.pwrmgr_global_esc.2873299473 Aug 04 05:17:12 PM PDT 24 Aug 04 05:17:13 PM PDT 24 39707289 ps
T570 /workspace/coverage/default/38.pwrmgr_smoke.3699980539 Aug 04 05:17:08 PM PDT 24 Aug 04 05:17:09 PM PDT 24 28913012 ps
T571 /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3045720853 Aug 04 05:17:17 PM PDT 24 Aug 04 05:17:18 PM PDT 24 67096340 ps
T572 /workspace/coverage/default/9.pwrmgr_aborted_low_power.3132384450 Aug 04 05:15:52 PM PDT 24 Aug 04 05:15:53 PM PDT 24 135416059 ps
T573 /workspace/coverage/default/13.pwrmgr_smoke.1897719050 Aug 04 05:16:09 PM PDT 24 Aug 04 05:16:10 PM PDT 24 125946373 ps
T574 /workspace/coverage/default/30.pwrmgr_reset.1648295788 Aug 04 05:16:58 PM PDT 24 Aug 04 05:16:59 PM PDT 24 26586594 ps
T575 /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4255661479 Aug 04 05:16:22 PM PDT 24 Aug 04 05:16:23 PM PDT 24 48879332 ps
T576 /workspace/coverage/default/17.pwrmgr_escalation_timeout.174926449 Aug 04 05:16:23 PM PDT 24 Aug 04 05:16:24 PM PDT 24 624342433 ps
T577 /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1164147962 Aug 04 05:16:22 PM PDT 24 Aug 04 05:16:23 PM PDT 24 41977388 ps
T578 /workspace/coverage/default/21.pwrmgr_glitch.3000826557 Aug 04 05:16:18 PM PDT 24 Aug 04 05:16:19 PM PDT 24 39644431 ps
T579 /workspace/coverage/default/0.pwrmgr_global_esc.3636620402 Aug 04 05:15:33 PM PDT 24 Aug 04 05:15:34 PM PDT 24 74234229 ps
T580 /workspace/coverage/default/3.pwrmgr_aborted_low_power.4027171704 Aug 04 05:15:40 PM PDT 24 Aug 04 05:15:41 PM PDT 24 73723432 ps
T581 /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.729525341 Aug 04 05:16:45 PM PDT 24 Aug 04 05:16:46 PM PDT 24 37012413 ps
T582 /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2109937631 Aug 04 05:17:22 PM PDT 24 Aug 04 05:17:23 PM PDT 24 60157811 ps
T583 /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.630918646 Aug 04 05:15:59 PM PDT 24 Aug 04 05:16:00 PM PDT 24 48936617 ps
T214 /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.983610859 Aug 04 05:15:59 PM PDT 24 Aug 04 05:16:00 PM PDT 24 53526881 ps
T584 /workspace/coverage/default/37.pwrmgr_reset_invalid.3548838458 Aug 04 05:17:11 PM PDT 24 Aug 04 05:17:12 PM PDT 24 163503823 ps
T585 /workspace/coverage/default/25.pwrmgr_stress_all.1343373576 Aug 04 05:16:29 PM PDT 24 Aug 04 05:16:30 PM PDT 24 99457746 ps
T586 /workspace/coverage/default/15.pwrmgr_glitch.4180760788 Aug 04 05:16:18 PM PDT 24 Aug 04 05:16:19 PM PDT 24 47594811 ps
T587 /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.474567743 Aug 04 05:17:02 PM PDT 24 Aug 04 05:17:03 PM PDT 24 29362192 ps
T588 /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3698844878 Aug 04 05:17:15 PM PDT 24 Aug 04 05:17:16 PM PDT 24 32540131 ps
T589 /workspace/coverage/default/22.pwrmgr_smoke.3019217365 Aug 04 05:16:26 PM PDT 24 Aug 04 05:16:27 PM PDT 24 44425400 ps
T590 /workspace/coverage/default/22.pwrmgr_global_esc.1532659950 Aug 04 05:16:58 PM PDT 24 Aug 04 05:16:59 PM PDT 24 37939627 ps
T591 /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.4188644761 Aug 04 05:16:55 PM PDT 24 Aug 04 05:16:56 PM PDT 24 59503570 ps
T592 /workspace/coverage/default/32.pwrmgr_smoke.3196316152 Aug 04 05:16:52 PM PDT 24 Aug 04 05:16:53 PM PDT 24 58177528 ps
T593 /workspace/coverage/default/48.pwrmgr_reset_invalid.1776439901 Aug 04 05:17:16 PM PDT 24 Aug 04 05:17:17 PM PDT 24 148466122 ps
T594 /workspace/coverage/default/30.pwrmgr_aborted_low_power.399313130 Aug 04 05:16:37 PM PDT 24 Aug 04 05:16:38 PM PDT 24 60841995 ps
T189 /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1841698310 Aug 04 05:16:06 PM PDT 24 Aug 04 05:16:07 PM PDT 24 42388806 ps
T595 /workspace/coverage/default/8.pwrmgr_reset.1686740460 Aug 04 05:15:47 PM PDT 24 Aug 04 05:15:48 PM PDT 24 38080729 ps
T596 /workspace/coverage/default/13.pwrmgr_aborted_low_power.993359368 Aug 04 05:16:05 PM PDT 24 Aug 04 05:16:06 PM PDT 24 131659067 ps
T185 /workspace/coverage/default/30.pwrmgr_lowpower_invalid.232050564 Aug 04 05:17:02 PM PDT 24 Aug 04 05:17:03 PM PDT 24 49124854 ps
T597 /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1814508452 Aug 04 05:16:57 PM PDT 24 Aug 04 05:16:58 PM PDT 24 38030965 ps
T598 /workspace/coverage/default/9.pwrmgr_lowpower_invalid.4239623669 Aug 04 05:16:01 PM PDT 24 Aug 04 05:16:02 PM PDT 24 138573324 ps
T599 /workspace/coverage/default/27.pwrmgr_aborted_low_power.2702428877 Aug 04 05:16:36 PM PDT 24 Aug 04 05:16:36 PM PDT 24 21462865 ps
T600 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2756036533 Aug 04 05:16:28 PM PDT 24 Aug 04 05:16:30 PM PDT 24 83552811 ps
T601 /workspace/coverage/default/42.pwrmgr_global_esc.2129748771 Aug 04 05:17:14 PM PDT 24 Aug 04 05:17:15 PM PDT 24 42097535 ps
T602 /workspace/coverage/default/40.pwrmgr_reset_invalid.1379706422 Aug 04 05:17:11 PM PDT 24 Aug 04 05:17:12 PM PDT 24 161827815 ps
T603 /workspace/coverage/default/11.pwrmgr_aborted_low_power.386530450 Aug 04 05:16:15 PM PDT 24 Aug 04 05:16:15 PM PDT 24 24229779 ps
T604 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1680473975 Aug 04 05:15:56 PM PDT 24 Aug 04 05:15:57 PM PDT 24 47748972 ps
T197 /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1687314903 Aug 04 05:17:14 PM PDT 24 Aug 04 05:17:15 PM PDT 24 49513784 ps
T605 /workspace/coverage/default/17.pwrmgr_smoke.1490383982 Aug 04 05:16:16 PM PDT 24 Aug 04 05:16:17 PM PDT 24 37619077 ps
T606 /workspace/coverage/default/38.pwrmgr_escalation_timeout.295078138 Aug 04 05:17:07 PM PDT 24 Aug 04 05:17:08 PM PDT 24 305250599 ps
T607 /workspace/coverage/default/6.pwrmgr_reset_invalid.483916268 Aug 04 05:15:45 PM PDT 24 Aug 04 05:15:46 PM PDT 24 172304577 ps
T608 /workspace/coverage/default/47.pwrmgr_smoke.593922660 Aug 04 05:17:11 PM PDT 24 Aug 04 05:17:12 PM PDT 24 67594672 ps
T609 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3583080191 Aug 04 05:16:29 PM PDT 24 Aug 04 05:16:30 PM PDT 24 82499051 ps
T610 /workspace/coverage/default/2.pwrmgr_aborted_low_power.3954927972 Aug 04 05:15:40 PM PDT 24 Aug 04 05:15:41 PM PDT 24 47519228 ps
T31 /workspace/coverage/default/4.pwrmgr_sec_cm.2612095669 Aug 04 05:15:37 PM PDT 24 Aug 04 05:15:38 PM PDT 24 622069251 ps
T611 /workspace/coverage/default/47.pwrmgr_lowpower_invalid.444878603 Aug 04 05:17:17 PM PDT 24 Aug 04 05:17:18 PM PDT 24 55699379 ps
T143 /workspace/coverage/default/11.pwrmgr_stress_all.3216436029 Aug 04 05:16:04 PM PDT 24 Aug 04 05:16:04 PM PDT 24 208091333 ps
T612 /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.353865864 Aug 04 05:17:25 PM PDT 24 Aug 04 05:17:26 PM PDT 24 62097295 ps
T613 /workspace/coverage/default/44.pwrmgr_aborted_low_power.1837573029 Aug 04 05:17:20 PM PDT 24 Aug 04 05:17:21 PM PDT 24 53020015 ps
T614 /workspace/coverage/default/13.pwrmgr_reset_invalid.560153954 Aug 04 05:16:00 PM PDT 24 Aug 04 05:16:02 PM PDT 24 93811387 ps
T615 /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.686332696 Aug 04 05:17:19 PM PDT 24 Aug 04 05:17:20 PM PDT 24 50048889 ps
T616 /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.438184234 Aug 04 05:15:54 PM PDT 24 Aug 04 05:15:55 PM PDT 24 124020255 ps
T617 /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.4215215878 Aug 04 05:15:50 PM PDT 24 Aug 04 05:15:51 PM PDT 24 49905642 ps
T618 /workspace/coverage/default/11.pwrmgr_global_esc.1866492094 Aug 04 05:16:03 PM PDT 24 Aug 04 05:16:03 PM PDT 24 55556557 ps
T619 /workspace/coverage/default/36.pwrmgr_aborted_low_power.3417239998 Aug 04 05:17:15 PM PDT 24 Aug 04 05:17:16 PM PDT 24 89024053 ps
T620 /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.596203318 Aug 04 05:17:05 PM PDT 24 Aug 04 05:17:05 PM PDT 24 34813227 ps
T621 /workspace/coverage/default/27.pwrmgr_global_esc.3135513917 Aug 04 05:16:28 PM PDT 24 Aug 04 05:16:30 PM PDT 24 34607247 ps
T622 /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1547705611 Aug 04 05:17:20 PM PDT 24 Aug 04 05:17:21 PM PDT 24 33001242 ps
T623 /workspace/coverage/default/43.pwrmgr_escalation_timeout.3637394630 Aug 04 05:17:22 PM PDT 24 Aug 04 05:17:23 PM PDT 24 844571530 ps
T624 /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1480201364 Aug 04 05:17:24 PM PDT 24 Aug 04 05:17:25 PM PDT 24 31453192 ps
T625 /workspace/coverage/default/24.pwrmgr_escalation_timeout.3500611990 Aug 04 05:16:28 PM PDT 24 Aug 04 05:16:30 PM PDT 24 162566903 ps
T626 /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2033343820 Aug 04 05:15:59 PM PDT 24 Aug 04 05:16:00 PM PDT 24 55033082 ps
T192 /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2267008063 Aug 04 05:16:12 PM PDT 24 Aug 04 05:16:13 PM PDT 24 35800193 ps
T627 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2096796018 Aug 04 05:17:11 PM PDT 24 Aug 04 05:17:13 PM PDT 24 54150687 ps
T70 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2719004418 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:04 PM PDT 24 35955551 ps
T71 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3080775261 Aug 04 04:27:12 PM PDT 24 Aug 04 04:27:12 PM PDT 24 93615587 ps
T66 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2736195414 Aug 04 04:27:11 PM PDT 24 Aug 04 04:27:12 PM PDT 24 18769632 ps
T24 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4209574483 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 181081691 ps
T61 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3388895068 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:04 PM PDT 24 168538054 ps
T25 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1822196634 Aug 04 04:27:28 PM PDT 24 Aug 04 04:27:29 PM PDT 24 71112147 ps
T26 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.655077349 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:09 PM PDT 24 189369069 ps
T67 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3634318453 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 54013613 ps
T68 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3684928551 Aug 04 04:27:53 PM PDT 24 Aug 04 04:27:54 PM PDT 24 42480027 ps
T56 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3969808158 Aug 04 04:27:41 PM PDT 24 Aug 04 04:27:44 PM PDT 24 485535651 ps
T153 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3747526755 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:58 PM PDT 24 216189378 ps
T146 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1251865215 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 16879375 ps
T628 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3089769090 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 35219912 ps
T73 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1377182053 Aug 04 04:27:09 PM PDT 24 Aug 04 04:27:10 PM PDT 24 35454322 ps
T57 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2727552443 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:01 PM PDT 24 157773587 ps
T147 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.278240735 Aug 04 04:27:12 PM PDT 24 Aug 04 04:27:12 PM PDT 24 94938132 ps
T148 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3552898034 Aug 04 04:27:07 PM PDT 24 Aug 04 04:27:08 PM PDT 24 128964626 ps
T91 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3349321162 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 21952767 ps
T105 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.796488044 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:03 PM PDT 24 74807877 ps
T149 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2669607681 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:04 PM PDT 24 19355257 ps
T100 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1191204310 Aug 04 04:27:13 PM PDT 24 Aug 04 04:27:14 PM PDT 24 42218778 ps
T74 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2630248622 Aug 04 04:27:15 PM PDT 24 Aug 04 04:27:16 PM PDT 24 41198977 ps
T150 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.897403159 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 29177074 ps
T58 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.197819172 Aug 04 04:27:07 PM PDT 24 Aug 04 04:27:08 PM PDT 24 80416605 ps
T629 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1267593876 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 35439777 ps
T630 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1718434088 Aug 04 04:27:27 PM PDT 24 Aug 04 04:27:27 PM PDT 24 21541002 ps
T631 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4154385037 Aug 04 04:27:37 PM PDT 24 Aug 04 04:27:38 PM PDT 24 42515165 ps
T92 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.179794484 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 46789290 ps
T93 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3136954328 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:01 PM PDT 24 23546799 ps
T106 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1831598689 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:02 PM PDT 24 46933023 ps
T59 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.138558610 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 361136399 ps
T69 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.419083312 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:58 PM PDT 24 220805929 ps
T94 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.266898023 Aug 04 04:27:29 PM PDT 24 Aug 04 04:27:30 PM PDT 24 33433032 ps
T151 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3696854593 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 179449537 ps
T632 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2523979480 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 18574938 ps
T60 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3901024470 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 766426308 ps
T107 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1331322897 Aug 04 04:27:13 PM PDT 24 Aug 04 04:27:14 PM PDT 24 22577691 ps
T633 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.1007734760 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 51967624 ps
T634 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.673911587 Aug 04 04:27:07 PM PDT 24 Aug 04 04:27:08 PM PDT 24 31744181 ps
T635 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2042690345 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 20046802 ps
T636 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3146181441 Aug 04 04:27:34 PM PDT 24 Aug 04 04:27:35 PM PDT 24 21829326 ps
T637 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2139402707 Aug 04 04:26:46 PM PDT 24 Aug 04 04:26:47 PM PDT 24 43165318 ps
T108 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.940520367 Aug 04 04:26:52 PM PDT 24 Aug 04 04:26:53 PM PDT 24 73715039 ps
T638 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3060977646 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:54 PM PDT 24 41769125 ps
T152 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3881596379 Aug 04 04:26:58 PM PDT 24 Aug 04 04:27:09 PM PDT 24 45893667 ps
T84 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1140371640 Aug 04 04:27:19 PM PDT 24 Aug 04 04:27:20 PM PDT 24 41354342 ps
T109 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3325011178 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 21591300 ps
T85 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2190290538 Aug 04 04:27:06 PM PDT 24 Aug 04 04:27:07 PM PDT 24 33397779 ps
T77 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3886215378 Aug 04 04:27:58 PM PDT 24 Aug 04 04:27:59 PM PDT 24 146421154 ps
T65 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.209806139 Aug 04 04:27:00 PM PDT 24 Aug 04 04:27:01 PM PDT 24 146651995 ps
T639 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.438151822 Aug 04 04:27:19 PM PDT 24 Aug 04 04:27:20 PM PDT 24 27834450 ps
T95 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3994915906 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 18639091 ps
T640 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2739732510 Aug 04 04:27:22 PM PDT 24 Aug 04 04:27:23 PM PDT 24 18632015 ps
T110 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2864949805 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:54 PM PDT 24 147781527 ps
T641 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1681138909 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 175473445 ps
T72 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1927638363 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:05 PM PDT 24 343544951 ps
T642 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3647346880 Aug 04 04:27:22 PM PDT 24 Aug 04 04:27:23 PM PDT 24 40214592 ps
T643 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1551668655 Aug 04 04:26:59 PM PDT 24 Aug 04 04:26:59 PM PDT 24 26360622 ps
T75 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2378066210 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:03 PM PDT 24 469118138 ps
T118 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3620985987 Aug 04 04:27:44 PM PDT 24 Aug 04 04:27:46 PM PDT 24 627372688 ps
T644 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1692846785 Aug 04 04:27:17 PM PDT 24 Aug 04 04:27:17 PM PDT 24 109041692 ps
T119 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3062026209 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 137119469 ps
T645 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1565856605 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:02 PM PDT 24 28558899 ps
T96 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1521879733 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 27056156 ps
T144 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1060050641 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 399945309 ps
T120 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.142816289 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:03 PM PDT 24 163832433 ps
T646 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1401012312 Aug 04 04:27:07 PM PDT 24 Aug 04 04:27:08 PM PDT 24 24712774 ps
T647 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1962139811 Aug 04 04:26:56 PM PDT 24 Aug 04 04:27:03 PM PDT 24 112426487 ps
T648 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3330734111 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:56 PM PDT 24 58623712 ps
T649 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1189072943 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 29469026 ps
T650 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.350146330 Aug 04 04:27:06 PM PDT 24 Aug 04 04:27:06 PM PDT 24 18852514 ps
T145 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1987083347 Aug 04 04:27:31 PM PDT 24 Aug 04 04:27:32 PM PDT 24 355292836 ps
T651 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2188961487 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 20070502 ps
T652 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3301590247 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:05 PM PDT 24 19393880 ps
T653 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3826166546 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:05 PM PDT 24 54600243 ps
T101 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.472831861 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:58 PM PDT 24 606170244 ps
T654 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.649373867 Aug 04 04:26:57 PM PDT 24 Aug 04 04:27:03 PM PDT 24 61617850 ps
T655 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1680237434 Aug 04 04:27:11 PM PDT 24 Aug 04 04:27:12 PM PDT 24 28337885 ps
T97 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3121646266 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 22892348 ps
T656 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2504985691 Aug 04 04:27:29 PM PDT 24 Aug 04 04:27:31 PM PDT 24 132906617 ps
T657 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4079400883 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:59 PM PDT 24 290257104 ps
T658 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1606395716 Aug 04 04:27:00 PM PDT 24 Aug 04 04:27:01 PM PDT 24 222879004 ps
T659 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1756690631 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 449481497 ps
T660 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2174284218 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 42299021 ps
T661 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4047735003 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 54773360 ps
T662 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.645496329 Aug 04 04:27:04 PM PDT 24 Aug 04 04:27:06 PM PDT 24 259492256 ps
T663 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1868318384 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 30128281 ps
T664 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4278333960 Aug 04 04:27:54 PM PDT 24 Aug 04 04:27:55 PM PDT 24 50511279 ps
T665 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2116084504 Aug 04 04:26:52 PM PDT 24 Aug 04 04:26:53 PM PDT 24 58846413 ps
T666 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.977500039 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 33162460 ps
T667 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3783413040 Aug 04 04:27:10 PM PDT 24 Aug 04 04:27:10 PM PDT 24 19233074 ps
T668 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.4063837903 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:02 PM PDT 24 42348815 ps
T669 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1223402915 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:56 PM PDT 24 186924090 ps
T670 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3208565648 Aug 04 04:27:24 PM PDT 24 Aug 04 04:27:24 PM PDT 24 19738052 ps
T98 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.923885427 Aug 04 04:26:52 PM PDT 24 Aug 04 04:26:53 PM PDT 24 53660482 ps
T99 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.265778492 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 88996746 ps
T671 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2091044933 Aug 04 04:27:05 PM PDT 24 Aug 04 04:27:06 PM PDT 24 78944322 ps
T672 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.834850895 Aug 04 04:27:17 PM PDT 24 Aug 04 04:27:18 PM PDT 24 49721125 ps
T673 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1159823009 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:57 PM PDT 24 279713536 ps
T674 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.772955679 Aug 04 04:27:00 PM PDT 24 Aug 04 04:27:02 PM PDT 24 80027423 ps
T675 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.582104882 Aug 04 04:27:08 PM PDT 24 Aug 04 04:27:09 PM PDT 24 21237445 ps
T102 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.586841611 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 24736069 ps
T676 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1037982430 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:10 PM PDT 24 75186641 ps
T677 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.520547599 Aug 04 04:27:28 PM PDT 24 Aug 04 04:27:30 PM PDT 24 112646826 ps
T678 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1523465270 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:02 PM PDT 24 91549927 ps
T679 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.551199537 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 20319244 ps
T680 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3661751572 Aug 04 04:27:33 PM PDT 24 Aug 04 04:27:34 PM PDT 24 48841875 ps
T681 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2679067811 Aug 04 04:27:20 PM PDT 24 Aug 04 04:27:22 PM PDT 24 131762694 ps
T682 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3381175850 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 347061956 ps
T683 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3841765184 Aug 04 04:27:15 PM PDT 24 Aug 04 04:27:16 PM PDT 24 51551162 ps
T684 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2706241081 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:56 PM PDT 24 53185517 ps
T685 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3060832738 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 41303460 ps
T686 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3315896517 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 58325069 ps
T687 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2171792776 Aug 04 04:26:54 PM PDT 24 Aug 04 04:27:00 PM PDT 24 28393772 ps
T688 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1242628177 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 52689408 ps
T689 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.356834301 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:57 PM PDT 24 21474936 ps
T690 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1420112553 Aug 04 04:26:56 PM PDT 24 Aug 04 04:27:02 PM PDT 24 29004328 ps
T691 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1940076226 Aug 04 04:27:28 PM PDT 24 Aug 04 04:27:29 PM PDT 24 130885410 ps
T692 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2768116279 Aug 04 04:27:00 PM PDT 24 Aug 04 04:27:02 PM PDT 24 194666162 ps
T693 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.429234510 Aug 04 04:26:58 PM PDT 24 Aug 04 04:27:00 PM PDT 24 341214073 ps
T694 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.930020497 Aug 04 04:27:20 PM PDT 24 Aug 04 04:27:21 PM PDT 24 144327297 ps
T695 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1341992115 Aug 04 04:27:07 PM PDT 24 Aug 04 04:27:07 PM PDT 24 47972862 ps
T696 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3154298237 Aug 04 04:27:25 PM PDT 24 Aug 04 04:27:26 PM PDT 24 20106129 ps
T697 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3582417986 Aug 04 04:26:58 PM PDT 24 Aug 04 04:27:05 PM PDT 24 106403931 ps
T698 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2966681293 Aug 04 04:27:08 PM PDT 24 Aug 04 04:27:10 PM PDT 24 121462811 ps
T699 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2196032470 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:03 PM PDT 24 41203028 ps
T700 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1718423198 Aug 04 04:26:54 PM PDT 24 Aug 04 04:26:55 PM PDT 24 40308211 ps
T701 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.414905704 Aug 04 04:27:06 PM PDT 24 Aug 04 04:27:08 PM PDT 24 261547096 ps
T702 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1399602372 Aug 04 04:27:30 PM PDT 24 Aug 04 04:27:31 PM PDT 24 114039924 ps
T703 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3623383988 Aug 04 04:27:15 PM PDT 24 Aug 04 04:27:16 PM PDT 24 61606298 ps
T704 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3250987292 Aug 04 04:27:18 PM PDT 24 Aug 04 04:27:19 PM PDT 24 33761643 ps
T705 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4099588675 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:01 PM PDT 24 198399709 ps
T706 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1307751556 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:07 PM PDT 24 131916124 ps
T707 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1994250242 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 214136615 ps
T708 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.62948179 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 48942843 ps
T709 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.222460251 Aug 04 04:27:52 PM PDT 24 Aug 04 04:27:53 PM PDT 24 23873124 ps
T710 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2314145387 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:03 PM PDT 24 394789016 ps
T711 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3432866564 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 58138932 ps
T712 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1650843529 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 105980070 ps
T713 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2522888226 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 48192654 ps
T714 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1174583146 Aug 04 04:27:23 PM PDT 24 Aug 04 04:27:24 PM PDT 24 18682457 ps
T715 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.894466460 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:54 PM PDT 24 30100829 ps
T716 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1682649561 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:03 PM PDT 24 152733954 ps
T717 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1394609332 Aug 04 04:26:58 PM PDT 24 Aug 04 04:26:59 PM PDT 24 19507056 ps
T718 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2257733374 Aug 04 04:26:49 PM PDT 24 Aug 04 04:26:49 PM PDT 24 100184237 ps
T719 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1036023140 Aug 04 04:27:02 PM PDT 24 Aug 04 04:27:03 PM PDT 24 60406639 ps
T720 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1061005580 Aug 04 04:27:23 PM PDT 24 Aug 04 04:27:24 PM PDT 24 21174603 ps
T721 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1242897524 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 20116181 ps
T103 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1051417781 Aug 04 04:26:57 PM PDT 24 Aug 04 04:26:58 PM PDT 24 26327724 ps
T722 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.178561414 Aug 04 04:26:59 PM PDT 24 Aug 04 04:27:00 PM PDT 24 78889262 ps
T723 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.907439788 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:04 PM PDT 24 62992146 ps
T724 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2668296555 Aug 04 04:27:38 PM PDT 24 Aug 04 04:27:39 PM PDT 24 26946448 ps
T725 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3802179754 Aug 04 04:27:46 PM PDT 24 Aug 04 04:27:47 PM PDT 24 45922680 ps
T726 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.4082216968 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:53 PM PDT 24 16378582 ps
T727 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1080348409 Aug 04 04:27:37 PM PDT 24 Aug 04 04:27:38 PM PDT 24 39431936 ps
T728 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1785411154 Aug 04 04:27:31 PM PDT 24 Aug 04 04:27:33 PM PDT 24 79246316 ps
T729 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2883671388 Aug 04 04:27:25 PM PDT 24 Aug 04 04:27:25 PM PDT 24 20197817 ps
T104 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.40949357 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:57 PM PDT 24 565241409 ps
T730 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2930784809 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:57 PM PDT 24 21075815 ps
T731 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3707164742 Aug 04 04:27:04 PM PDT 24 Aug 04 04:27:06 PM PDT 24 519176189 ps
T732 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.766677828 Aug 04 04:26:58 PM PDT 24 Aug 04 04:27:00 PM PDT 24 147521275 ps
T733 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3003096336 Aug 04 04:27:33 PM PDT 24 Aug 04 04:27:35 PM PDT 24 115957544 ps
T734 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3315548405 Aug 04 04:27:24 PM PDT 24 Aug 04 04:27:25 PM PDT 24 44696332 ps
T735 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1686954735 Aug 04 04:26:56 PM PDT 24 Aug 04 04:26:58 PM PDT 24 450497612 ps
T736 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2304166958 Aug 04 04:27:08 PM PDT 24 Aug 04 04:27:09 PM PDT 24 20485102 ps

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1752045293
Short name T9
Test name
Test status
Simulation time 64206167 ps
CPU time 0.68 seconds
Started Aug 04 05:15:38 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 198208 kb
Host smart-e72501da-1edc-462b-809e-88b18a562fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752045293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1752045293
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.1300103896
Short name T14
Test name
Test status
Simulation time 42044584 ps
CPU time 0.76 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 198432 kb
Host smart-18ca40e6-91d0-4c78-a700-875890d242dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300103896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.1300103896
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3339819480
Short name T45
Test name
Test status
Simulation time 95170295 ps
CPU time 1.12 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 209476 kb
Host smart-0265dfca-b394-4759-98f9-7de47a7a540b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339819480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3339819480
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4209574483
Short name T24
Test name
Test status
Simulation time 181081691 ps
CPU time 0.81 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 195124 kb
Host smart-da978712-05da-4060-802c-755f856c7cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209574483 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4209574483
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2077718276
Short name T30
Test name
Test status
Simulation time 667271049 ps
CPU time 2.12 seconds
Started Aug 04 05:15:34 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 218268 kb
Host smart-574a1d7d-d31e-4930-8dc4-fe43d54685a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077718276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2077718276
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2825635929
Short name T16
Test name
Test status
Simulation time 41512198 ps
CPU time 0.71 seconds
Started Aug 04 05:16:44 PM PDT 24
Finished Aug 04 05:16:45 PM PDT 24
Peak memory 201340 kb
Host smart-a9025017-e0e1-43d9-99bd-20a598aca70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825635929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2825635929
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2411808982
Short name T54
Test name
Test status
Simulation time 93433787 ps
CPU time 0.81 seconds
Started Aug 04 05:17:00 PM PDT 24
Finished Aug 04 05:17:01 PM PDT 24
Peak memory 200192 kb
Host smart-2ab1f9d4-6824-40c4-9b51-ae32a7aeeeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411808982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2411808982
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.1441419145
Short name T50
Test name
Test status
Simulation time 106597271 ps
CPU time 0.99 seconds
Started Aug 04 05:15:39 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 199240 kb
Host smart-3c765b2c-342b-4173-b792-a52100c61341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441419145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.1441419145
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.138558610
Short name T59
Test name
Test status
Simulation time 361136399 ps
CPU time 1.41 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 200440 kb
Host smart-83a8b282-a410-4a6f-985c-7f127512d56f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138558610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.
138558610
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.2781654845
Short name T27
Test name
Test status
Simulation time 109236093 ps
CPU time 0.68 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 198372 kb
Host smart-7b22c1c9-0102-42d1-8424-b8dc25cba15a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781654845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2781654845
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3370748069
Short name T11
Test name
Test status
Simulation time 32733764 ps
CPU time 0.6 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 197960 kb
Host smart-dda07c6c-e2b6-46c4-a94a-50fda6ef6633
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370748069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3370748069
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2378127452
Short name T111
Test name
Test status
Simulation time 125867979 ps
CPU time 0.79 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 199988 kb
Host smart-7cce1ff9-f443-4278-9f3b-a30a8de52900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378127452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2378127452
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2669607681
Short name T149
Test name
Test status
Simulation time 19355257 ps
CPU time 0.62 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 194860 kb
Host smart-817e4f10-9be9-4f09-a490-a927b43d91b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669607681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2669607681
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.179794484
Short name T92
Test name
Test status
Simulation time 46789290 ps
CPU time 0.62 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 194980 kb
Host smart-276f2f59-6ddf-44d6-b1a7-7fb2d8d38568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179794484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.179794484
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2504985691
Short name T656
Test name
Test status
Simulation time 132906617 ps
CPU time 1.95 seconds
Started Aug 04 04:27:29 PM PDT 24
Finished Aug 04 04:27:31 PM PDT 24
Peak memory 197240 kb
Host smart-b029d808-7169-43b8-a6e7-23aaba0a1b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504985691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2504985691
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.2263338316
Short name T3
Test name
Test status
Simulation time 64249785 ps
CPU time 0.85 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 198596 kb
Host smart-434fc4b1-a884-468c-9f5c-d4665e0eec0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263338316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.2263338316
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.511893183
Short name T53
Test name
Test status
Simulation time 34508383 ps
CPU time 0.76 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 198896 kb
Host smart-ed8c3437-195c-4841-bca0-be404ad9be57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511893183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.511893183
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2880732079
Short name T49
Test name
Test status
Simulation time 55666225 ps
CPU time 0.66 seconds
Started Aug 04 05:15:59 PM PDT 24
Finished Aug 04 05:15:59 PM PDT 24
Peak memory 199388 kb
Host smart-13e08beb-ccf8-43a7-a067-e851be26d04a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880732079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2880732079
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3030884204
Short name T198
Test name
Test status
Simulation time 201795962 ps
CPU time 0.72 seconds
Started Aug 04 05:16:00 PM PDT 24
Finished Aug 04 05:16:06 PM PDT 24
Peak memory 201240 kb
Host smart-a37036f4-2517-475d-bf96-c648b01b2419
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030884204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.3030884204
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1447486556
Short name T132
Test name
Test status
Simulation time 56607181 ps
CPU time 0.67 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 198104 kb
Host smart-4df9552c-8f51-4b09-9453-8454691db2c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447486556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1447486556
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.3216436029
Short name T143
Test name
Test status
Simulation time 208091333 ps
CPU time 0.65 seconds
Started Aug 04 05:16:04 PM PDT 24
Finished Aug 04 05:16:04 PM PDT 24
Peak memory 198640 kb
Host smart-5dcb01c6-3044-4395-a3a7-5d091fab26aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216436029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3216436029
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1954504440
Short name T492
Test name
Test status
Simulation time 74593690 ps
CPU time 0.68 seconds
Started Aug 04 05:16:35 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 199076 kb
Host smart-1ad6feec-9755-4747-a53d-d78571092b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954504440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.1954504440
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.3395498111
Short name T55
Test name
Test status
Simulation time 71459466 ps
CPU time 0.68 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 201240 kb
Host smart-5ddf0085-fbd4-4954-a525-f6ad30d20706
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395498111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.3395498111
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1476034653
Short name T171
Test name
Test status
Simulation time 42327314 ps
CPU time 0.72 seconds
Started Aug 04 05:15:57 PM PDT 24
Finished Aug 04 05:15:57 PM PDT 24
Peak memory 201184 kb
Host smart-60ce90b9-7e2b-4dad-af10-8f5fc9e30cd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476034653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1476034653
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1137417269
Short name T375
Test name
Test status
Simulation time 69043299 ps
CPU time 0.66 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 198136 kb
Host smart-86f9d362-2f57-4511-a285-9f469c251f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137417269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.1137417269
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1278844346
Short name T215
Test name
Test status
Simulation time 38634584 ps
CPU time 0.68 seconds
Started Aug 04 05:17:26 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 201400 kb
Host smart-a6d7246c-c418-4583-8c60-1344de01a99d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278844346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1278844346
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.578851798
Short name T81
Test name
Test status
Simulation time 32097943 ps
CPU time 0.69 seconds
Started Aug 04 05:16:50 PM PDT 24
Finished Aug 04 05:16:51 PM PDT 24
Peak memory 199300 kb
Host smart-7fb5d352-e703-4853-8858-183ae48e570f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578851798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.578851798
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.983610859
Short name T214
Test name
Test status
Simulation time 53526881 ps
CPU time 0.68 seconds
Started Aug 04 05:15:59 PM PDT 24
Finished Aug 04 05:16:00 PM PDT 24
Peak memory 198240 kb
Host smart-59e813a5-a270-49e3-9aeb-166dec70849a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983610859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wa
keup_race.983610859
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3738601303
Short name T176
Test name
Test status
Simulation time 78784640 ps
CPU time 0.67 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 201472 kb
Host smart-4c4b3323-bd13-49aa-9d4a-7f936ff90db5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738601303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3738601303
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2267008063
Short name T192
Test name
Test status
Simulation time 35800193 ps
CPU time 0.68 seconds
Started Aug 04 05:16:12 PM PDT 24
Finished Aug 04 05:16:13 PM PDT 24
Peak memory 198452 kb
Host smart-179c9e41-0ae2-4873-b13f-6567418a8d25
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267008063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.2267008063
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3466667416
Short name T183
Test name
Test status
Simulation time 47842166 ps
CPU time 0.76 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 201348 kb
Host smart-e0577c5e-642e-45bc-833a-ea98f75245b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466667416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3466667416
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1625789221
Short name T155
Test name
Test status
Simulation time 216435247 ps
CPU time 0.67 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198452 kb
Host smart-e0da8e50-5b7e-4fd8-93e3-2c46ea7278c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625789221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.1625789221
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3592758604
Short name T169
Test name
Test status
Simulation time 73896492 ps
CPU time 0.7 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 201080 kb
Host smart-5074a2c0-5349-450b-87d0-c57fc90343ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592758604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3592758604
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3969808158
Short name T56
Test name
Test status
Simulation time 485535651 ps
CPU time 2.96 seconds
Started Aug 04 04:27:41 PM PDT 24
Finished Aug 04 04:27:44 PM PDT 24
Peak memory 197432 kb
Host smart-5dc8c330-53c6-463b-a715-0be3e7f6d3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969808158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3969808158
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1868318384
Short name T663
Test name
Test status
Simulation time 30128281 ps
CPU time 0.6 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 194856 kb
Host smart-e91f724a-2ee2-490b-a1c1-432b99669634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868318384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1868318384
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.4048040448
Short name T210
Test name
Test status
Simulation time 55248919 ps
CPU time 0.8 seconds
Started Aug 04 05:15:55 PM PDT 24
Finished Aug 04 05:15:56 PM PDT 24
Peak memory 198544 kb
Host smart-0daa0e92-3a85-4603-b62c-9cc0bd878c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048040448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.4048040448
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.519521322
Short name T188
Test name
Test status
Simulation time 83714449 ps
CPU time 0.72 seconds
Started Aug 04 05:16:06 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 201416 kb
Host smart-18e42ff2-a4eb-4613-aea3-43d5820ccb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519521322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.519521322
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.1348353336
Short name T181
Test name
Test status
Simulation time 42049910 ps
CPU time 0.73 seconds
Started Aug 04 05:16:17 PM PDT 24
Finished Aug 04 05:16:18 PM PDT 24
Peak memory 201396 kb
Host smart-a35824cb-2dd4-4841-a218-43bcfaacb784
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348353336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.1348353336
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1607295690
Short name T203
Test name
Test status
Simulation time 44912646 ps
CPU time 0.77 seconds
Started Aug 04 05:16:19 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 201456 kb
Host smart-a06fbfa0-77b2-4144-a14f-6a111206f058
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607295690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1607295690
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1589279286
Short name T208
Test name
Test status
Simulation time 72500694 ps
CPU time 0.62 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:33 PM PDT 24
Peak memory 198416 kb
Host smart-78159a9d-2405-49b1-9071-207be40b1168
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589279286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.1589279286
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.601869864
Short name T207
Test name
Test status
Simulation time 80274488 ps
CPU time 0.65 seconds
Started Aug 04 05:15:39 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 198452 kb
Host smart-e915a030-8bb4-4042-82a2-7a3b8804f6e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601869864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.601869864
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.653876038
Short name T199
Test name
Test status
Simulation time 55786205 ps
CPU time 0.66 seconds
Started Aug 04 05:16:56 PM PDT 24
Finished Aug 04 05:16:57 PM PDT 24
Peak memory 201380 kb
Host smart-4d38a0c8-bff7-45f8-b007-5e32f66f92e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653876038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.653876038
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3902727140
Short name T167
Test name
Test status
Simulation time 70955652 ps
CPU time 0.65 seconds
Started Aug 04 05:17:46 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 201304 kb
Host smart-3210a6f4-4585-4e3d-880e-6b63def3f6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902727140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3902727140
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2405742382
Short name T234
Test name
Test status
Simulation time 68481805 ps
CPU time 0.63 seconds
Started Aug 04 05:16:00 PM PDT 24
Finished Aug 04 05:16:01 PM PDT 24
Peak memory 197292 kb
Host smart-96afd8cb-21dc-469a-b293-2a1d7d4fb09c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405742382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2405742382
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.977500039
Short name T666
Test name
Test status
Simulation time 33162460 ps
CPU time 0.85 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 197264 kb
Host smart-4e24be11-3490-43a5-a342-337630842416
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977500039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.977500039
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.40949357
Short name T104
Test name
Test status
Simulation time 565241409 ps
CPU time 1.91 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 195160 kb
Host smart-08c22de8-581b-456e-8b64-2b737b71171d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40949357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.40949357
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3250987292
Short name T704
Test name
Test status
Simulation time 33761643 ps
CPU time 0.61 seconds
Started Aug 04 04:27:18 PM PDT 24
Finished Aug 04 04:27:19 PM PDT 24
Peak memory 194952 kb
Host smart-07dd480a-4397-487b-9a20-e10bcf1173fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250987292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
250987292
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3062026209
Short name T119
Test name
Test status
Simulation time 137119469 ps
CPU time 0.9 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 195060 kb
Host smart-1b6c617a-759e-459c-ae3c-9c284227d759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062026209 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3062026209
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1521879733
Short name T96
Test name
Test status
Simulation time 27056156 ps
CPU time 0.61 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 197084 kb
Host smart-2ab2dab0-aafd-4e13-aa54-0ea69559b6e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521879733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1521879733
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1606395716
Short name T658
Test name
Test status
Simulation time 222879004 ps
CPU time 0.93 seconds
Started Aug 04 04:27:00 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 195016 kb
Host smart-e724252a-d63f-45eb-b2d3-ac8ceb0c2199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606395716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1606395716
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3582417986
Short name T697
Test name
Test status
Simulation time 106403931 ps
CPU time 1.27 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:27:05 PM PDT 24
Peak memory 195408 kb
Host smart-569a1411-27ef-4575-8b27-9d7b0a902a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582417986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3582417986
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.142816289
Short name T120
Test name
Test status
Simulation time 163832433 ps
CPU time 1.14 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 200152 kb
Host smart-405006d2-6d60-4593-b36a-f04594fcf777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142816289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
142816289
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3349321162
Short name T91
Test name
Test status
Simulation time 21952767 ps
CPU time 0.77 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194900 kb
Host smart-e1426863-c4fb-4e36-ab1f-08545c30227a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349321162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
349321162
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3388895068
Short name T61
Test name
Test status
Simulation time 168538054 ps
CPU time 1.64 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 198780 kb
Host smart-274033f6-fb22-431e-858c-1f3f1efcbd6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388895068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
388895068
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3315548405
Short name T734
Test name
Test status
Simulation time 44696332 ps
CPU time 0.7 seconds
Started Aug 04 04:27:24 PM PDT 24
Finished Aug 04 04:27:25 PM PDT 24
Peak memory 194944 kb
Host smart-cc786efd-5233-4703-8126-ca1fd0f4661d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315548405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
315548405
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3432866564
Short name T711
Test name
Test status
Simulation time 58138932 ps
CPU time 0.91 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 195100 kb
Host smart-9c6193f5-7e8a-4ee9-8024-affe46decec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432866564 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3432866564
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2042690345
Short name T635
Test name
Test status
Simulation time 20046802 ps
CPU time 0.66 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 197092 kb
Host smart-5c409d1c-f63f-40ae-9318-3030fa436134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042690345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2042690345
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.278240735
Short name T147
Test name
Test status
Simulation time 94938132 ps
CPU time 0.59 seconds
Started Aug 04 04:27:12 PM PDT 24
Finished Aug 04 04:27:12 PM PDT 24
Peak memory 194892 kb
Host smart-522a9462-a28b-4d8a-946c-b16289e65dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278240735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.278240735
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.930020497
Short name T694
Test name
Test status
Simulation time 144327297 ps
CPU time 0.86 seconds
Started Aug 04 04:27:20 PM PDT 24
Finished Aug 04 04:27:21 PM PDT 24
Peak memory 194956 kb
Host smart-bdbf92bf-b10e-47a4-a4d8-cca7e313ca18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930020497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.930020497
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2190290538
Short name T85
Test name
Test status
Simulation time 33397779 ps
CPU time 1.43 seconds
Started Aug 04 04:27:06 PM PDT 24
Finished Aug 04 04:27:07 PM PDT 24
Peak memory 196220 kb
Host smart-76d68f35-bc29-4616-8da0-9560b1d699a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190290538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2190290538
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1159823009
Short name T673
Test name
Test status
Simulation time 279713536 ps
CPU time 1.03 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 195216 kb
Host smart-08556e79-e20c-40be-96e2-dcb1dce6c447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159823009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1159823009
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.197819172
Short name T58
Test name
Test status
Simulation time 80416605 ps
CPU time 0.82 seconds
Started Aug 04 04:27:07 PM PDT 24
Finished Aug 04 04:27:08 PM PDT 24
Peak memory 200284 kb
Host smart-163838ad-8213-45b5-99bf-2da6fe1e0556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197819172 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.197819172
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2091044933
Short name T671
Test name
Test status
Simulation time 78944322 ps
CPU time 0.6 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 194976 kb
Host smart-1ed335b1-05e0-452a-84e4-2a5e1e3dc3cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091044933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2091044933
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1341992115
Short name T695
Test name
Test status
Simulation time 47972862 ps
CPU time 0.6 seconds
Started Aug 04 04:27:07 PM PDT 24
Finished Aug 04 04:27:07 PM PDT 24
Peak memory 194908 kb
Host smart-7bcd7ca5-a238-4a4a-b4f3-15684b1fda66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341992115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1341992115
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3080775261
Short name T71
Test name
Test status
Simulation time 93615587 ps
CPU time 0.73 seconds
Started Aug 04 04:27:12 PM PDT 24
Finished Aug 04 04:27:12 PM PDT 24
Peak memory 197184 kb
Host smart-7a83946a-a8d5-4d19-b4ec-888708dd9054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080775261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3080775261
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3003096336
Short name T733
Test name
Test status
Simulation time 115957544 ps
CPU time 2.5 seconds
Started Aug 04 04:27:33 PM PDT 24
Finished Aug 04 04:27:35 PM PDT 24
Peak memory 200580 kb
Host smart-f80c0313-6756-44ea-9d84-4fa4e02952c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003096336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3003096336
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.645496329
Short name T662
Test name
Test status
Simulation time 259492256 ps
CPU time 1.49 seconds
Started Aug 04 04:27:04 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 195264 kb
Host smart-4e10379d-dc87-4b14-9034-4307972810f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645496329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.645496329
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1036023140
Short name T719
Test name
Test status
Simulation time 60406639 ps
CPU time 0.81 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 195112 kb
Host smart-708feb13-f004-4dd1-a4cc-eb69ca6be813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036023140 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1036023140
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2116084504
Short name T665
Test name
Test status
Simulation time 58846413 ps
CPU time 0.59 seconds
Started Aug 04 04:26:52 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 195000 kb
Host smart-578c8944-cda3-4db9-95fa-989981679153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116084504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2116084504
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1307751556
Short name T706
Test name
Test status
Simulation time 131916124 ps
CPU time 0.57 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:07 PM PDT 24
Peak memory 194900 kb
Host smart-037287b4-121d-4687-b303-ae0376863812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307751556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1307751556
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3315896517
Short name T686
Test name
Test status
Simulation time 58325069 ps
CPU time 0.83 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 198332 kb
Host smart-71220749-ba6d-43ea-b1d4-be5d3b1983cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315896517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3315896517
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4099588675
Short name T705
Test name
Test status
Simulation time 198399709 ps
CPU time 1.53 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 200496 kb
Host smart-cc0096c7-6254-413d-b147-32c32ddbee36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099588675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.4099588675
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.520547599
Short name T677
Test name
Test status
Simulation time 112646826 ps
CPU time 1.34 seconds
Started Aug 04 04:27:28 PM PDT 24
Finished Aug 04 04:27:30 PM PDT 24
Peak memory 196256 kb
Host smart-8b4efa35-1f75-405e-90c1-f628a00df9d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520547599 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.520547599
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2930784809
Short name T730
Test name
Test status
Simulation time 21075815 ps
CPU time 0.63 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 197204 kb
Host smart-d11a3381-f9bb-4eae-9bc0-e7a930494ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930784809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2930784809
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1251865215
Short name T146
Test name
Test status
Simulation time 16879375 ps
CPU time 0.61 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 194852 kb
Host smart-06f5b4fe-e01a-479d-afd0-654dfeef8b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251865215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1251865215
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3325011178
Short name T109
Test name
Test status
Simulation time 21591300 ps
CPU time 0.78 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 194988 kb
Host smart-a9e7e1d2-6001-4c0d-93ca-061d1b6ec4ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325011178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3325011178
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2727552443
Short name T57
Test name
Test status
Simulation time 157773587 ps
CPU time 2 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 196400 kb
Host smart-9ed8f920-2a07-4f13-ab38-dc91ef639be4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727552443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2727552443
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1686954735
Short name T735
Test name
Test status
Simulation time 450497612 ps
CPU time 1.48 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 195216 kb
Host smart-292660b5-6e13-4947-9cda-f4984cc48f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686954735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1686954735
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.649373867
Short name T654
Test name
Test status
Simulation time 61617850 ps
CPU time 0.82 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 195076 kb
Host smart-b364dd4c-a680-4374-9bef-662b59c5c384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649373867 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.649373867
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1650843529
Short name T712
Test name
Test status
Simulation time 105980070 ps
CPU time 0.61 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 197092 kb
Host smart-5e751285-0e4c-49a3-89b4-3a15085f9200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650843529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.1650843529
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.4082216968
Short name T726
Test name
Test status
Simulation time 16378582 ps
CPU time 0.59 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 194888 kb
Host smart-8cb9b4df-0bdd-45ee-a465-71fd6887b1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082216968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.4082216968
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1223402915
Short name T669
Test name
Test status
Simulation time 186924090 ps
CPU time 0.83 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 194952 kb
Host smart-6d93c653-a342-469a-8d80-416b17dfca13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223402915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1223402915
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1822196634
Short name T25
Test name
Test status
Simulation time 71112147 ps
CPU time 1.04 seconds
Started Aug 04 04:27:28 PM PDT 24
Finished Aug 04 04:27:29 PM PDT 24
Peak memory 195180 kb
Host smart-3ef013cf-8b35-410b-ab81-0f080f3404ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822196634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1822196634
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.429234510
Short name T693
Test name
Test status
Simulation time 341214073 ps
CPU time 1.39 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 195232 kb
Host smart-57df7c0c-6b2d-407b-b194-5b0387553ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429234510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err
.429234510
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2522888226
Short name T713
Test name
Test status
Simulation time 48192654 ps
CPU time 0.96 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 195188 kb
Host smart-d03bf571-f02e-46a9-9b6a-ec23365e6d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522888226 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.2522888226
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3060977646
Short name T638
Test name
Test status
Simulation time 41769125 ps
CPU time 0.6 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:54 PM PDT 24
Peak memory 197184 kb
Host smart-b7d95a98-9564-45da-a678-5525c42a89b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060977646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3060977646
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1080348409
Short name T727
Test name
Test status
Simulation time 39431936 ps
CPU time 0.62 seconds
Started Aug 04 04:27:37 PM PDT 24
Finished Aug 04 04:27:38 PM PDT 24
Peak memory 194892 kb
Host smart-174c1be5-2be1-4d0a-b18e-b476f413df98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080348409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1080348409
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1189072943
Short name T649
Test name
Test status
Simulation time 29469026 ps
CPU time 0.71 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 194936 kb
Host smart-0914212a-a655-464a-83fc-56abd733dff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189072943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1189072943
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2768116279
Short name T692
Test name
Test status
Simulation time 194666162 ps
CPU time 2.03 seconds
Started Aug 04 04:27:00 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 196488 kb
Host smart-c2a30263-0249-48d1-9428-c4b9c6a22590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768116279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2768116279
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1987083347
Short name T145
Test name
Test status
Simulation time 355292836 ps
CPU time 1.05 seconds
Started Aug 04 04:27:31 PM PDT 24
Finished Aug 04 04:27:32 PM PDT 24
Peak memory 200336 kb
Host smart-6ef6259d-ddbb-4cd2-a7c9-e5317261af86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987083347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1987083347
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1377182053
Short name T73
Test name
Test status
Simulation time 35454322 ps
CPU time 0.73 seconds
Started Aug 04 04:27:09 PM PDT 24
Finished Aug 04 04:27:10 PM PDT 24
Peak memory 195068 kb
Host smart-2ffb4977-7bc2-46d7-a27c-7203dbaf5553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377182053 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.1377182053
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3994915906
Short name T95
Test name
Test status
Simulation time 18639091 ps
CPU time 0.62 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194972 kb
Host smart-81f9a43d-6957-457d-9f62-77286ad9a879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994915906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3994915906
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2736195414
Short name T66
Test name
Test status
Simulation time 18769632 ps
CPU time 0.57 seconds
Started Aug 04 04:27:11 PM PDT 24
Finished Aug 04 04:27:12 PM PDT 24
Peak memory 194868 kb
Host smart-23c6148c-edb2-4653-a5fd-39d2ad228de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736195414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2736195414
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1681138909
Short name T641
Test name
Test status
Simulation time 175473445 ps
CPU time 0.83 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 198964 kb
Host smart-97b23f44-575c-4203-8036-8d535dd217e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681138909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1681138909
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.894466460
Short name T715
Test name
Test status
Simulation time 30100829 ps
CPU time 1.15 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:54 PM PDT 24
Peak memory 195300 kb
Host smart-11e9cec2-64dd-4139-b2fc-a3f6172e260b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894466460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.894466460
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3381175850
Short name T682
Test name
Test status
Simulation time 347061956 ps
CPU time 1.47 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 200496 kb
Host smart-f576b2dd-e65f-423f-9cb4-4b62515301ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381175850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3381175850
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4047735003
Short name T661
Test name
Test status
Simulation time 54773360 ps
CPU time 0.75 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 195080 kb
Host smart-d64f6005-8305-4929-82d9-3121a8685fad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047735003 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.4047735003
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1331322897
Short name T107
Test name
Test status
Simulation time 22577691 ps
CPU time 0.66 seconds
Started Aug 04 04:27:13 PM PDT 24
Finished Aug 04 04:27:14 PM PDT 24
Peak memory 197124 kb
Host smart-73dd0773-f814-4441-895e-d679b20234ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331322897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1331322897
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.907439788
Short name T723
Test name
Test status
Simulation time 62992146 ps
CPU time 0.57 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 194900 kb
Host smart-eea9802c-48ab-4342-8916-2da79cf9cd67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907439788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.907439788
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1523465270
Short name T678
Test name
Test status
Simulation time 91549927 ps
CPU time 0.73 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 197208 kb
Host smart-9782239c-f387-48be-8191-b7d30052d203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523465270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1523465270
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1994250242
Short name T707
Test name
Test status
Simulation time 214136615 ps
CPU time 1.32 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 195496 kb
Host smart-8faf7695-818a-4619-9484-57289c87b723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994250242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1994250242
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.414905704
Short name T701
Test name
Test status
Simulation time 261547096 ps
CPU time 1.65 seconds
Started Aug 04 04:27:06 PM PDT 24
Finished Aug 04 04:27:08 PM PDT 24
Peak memory 200732 kb
Host smart-21df1cc0-aed4-4c0e-964d-0c4fb9770cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414905704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.414905704
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.834850895
Short name T672
Test name
Test status
Simulation time 49721125 ps
CPU time 0.92 seconds
Started Aug 04 04:27:17 PM PDT 24
Finished Aug 04 04:27:18 PM PDT 24
Peak memory 195092 kb
Host smart-ad3ca767-d2b1-4e47-9ecb-908ba37182d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834850895 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.834850895
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3301590247
Short name T652
Test name
Test status
Simulation time 19393880 ps
CPU time 0.66 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:05 PM PDT 24
Peak memory 197096 kb
Host smart-ee6bfae8-a301-4d01-9591-c3f0cc0fff78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301590247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3301590247
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.222460251
Short name T709
Test name
Test status
Simulation time 23873124 ps
CPU time 0.81 seconds
Started Aug 04 04:27:52 PM PDT 24
Finished Aug 04 04:27:53 PM PDT 24
Peak memory 198324 kb
Host smart-436cead4-deba-4e12-b4da-2cc7b8a19b97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222460251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.222460251
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3623383988
Short name T703
Test name
Test status
Simulation time 61606298 ps
CPU time 1.33 seconds
Started Aug 04 04:27:15 PM PDT 24
Finished Aug 04 04:27:16 PM PDT 24
Peak memory 196048 kb
Host smart-4d7a631e-9a4e-4776-a8b3-2a30aa27a348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623383988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3623383988
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4079400883
Short name T657
Test name
Test status
Simulation time 290257104 ps
CPU time 1.48 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 200484 kb
Host smart-b7463ab4-787e-4688-bc03-93c324f1889a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079400883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.4079400883
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2630248622
Short name T74
Test name
Test status
Simulation time 41198977 ps
CPU time 0.71 seconds
Started Aug 04 04:27:15 PM PDT 24
Finished Aug 04 04:27:16 PM PDT 24
Peak memory 195084 kb
Host smart-a8b453f4-ca2e-4ea2-9a01-850bbb1ac995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630248622 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2630248622
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2719004418
Short name T70
Test name
Test status
Simulation time 35955551 ps
CPU time 0.58 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 197140 kb
Host smart-dc22f244-4d3b-462a-a1d3-bae72ca181fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719004418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2719004418
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2739732510
Short name T640
Test name
Test status
Simulation time 18632015 ps
CPU time 0.6 seconds
Started Aug 04 04:27:22 PM PDT 24
Finished Aug 04 04:27:23 PM PDT 24
Peak memory 194976 kb
Host smart-17530ab9-465b-4fda-a8fe-92a8157798c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739732510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2739732510
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.796488044
Short name T105
Test name
Test status
Simulation time 74807877 ps
CPU time 0.79 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 198572 kb
Host smart-f8781b2e-f3ca-46a6-b91f-a2f49c2cd231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796488044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.796488044
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1785411154
Short name T728
Test name
Test status
Simulation time 79246316 ps
CPU time 1.27 seconds
Started Aug 04 04:27:31 PM PDT 24
Finished Aug 04 04:27:33 PM PDT 24
Peak memory 200604 kb
Host smart-8d483316-e85e-4afd-a1de-6dd7f939cef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785411154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1785411154
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1927638363
Short name T72
Test name
Test status
Simulation time 343544951 ps
CPU time 1.54 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:05 PM PDT 24
Peak memory 200528 kb
Host smart-0c8690c9-5fcf-4350-b3e3-19c01ec4d1a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927638363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.1927638363
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1140371640
Short name T84
Test name
Test status
Simulation time 41354342 ps
CPU time 0.79 seconds
Started Aug 04 04:27:19 PM PDT 24
Finished Aug 04 04:27:20 PM PDT 24
Peak memory 195076 kb
Host smart-1665d3a7-2000-4dc1-b206-bd7b224369e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140371640 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1140371640
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1565856605
Short name T645
Test name
Test status
Simulation time 28558899 ps
CPU time 0.61 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 194948 kb
Host smart-137d57c3-78a8-4577-b37b-0115e7fc58cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565856605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1565856605
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3783413040
Short name T667
Test name
Test status
Simulation time 19233074 ps
CPU time 0.59 seconds
Started Aug 04 04:27:10 PM PDT 24
Finished Aug 04 04:27:10 PM PDT 24
Peak memory 194844 kb
Host smart-cf280bee-54a2-400f-9b97-4c933a5f9a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783413040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3783413040
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3826166546
Short name T653
Test name
Test status
Simulation time 54600243 ps
CPU time 0.7 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:05 PM PDT 24
Peak memory 198240 kb
Host smart-97a05371-cd27-42c5-9af4-524603e4fd64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826166546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3826166546
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3886215378
Short name T77
Test name
Test status
Simulation time 146421154 ps
CPU time 1.5 seconds
Started Aug 04 04:27:58 PM PDT 24
Finished Aug 04 04:27:59 PM PDT 24
Peak memory 196256 kb
Host smart-369396d3-138d-4c7b-a335-3788f4c7cd7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886215378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3886215378
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2378066210
Short name T75
Test name
Test status
Simulation time 469118138 ps
CPU time 1.37 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 195248 kb
Host smart-863aa7c7-d456-4406-9ba4-35e093cfc608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378066210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2378066210
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1051417781
Short name T103
Test name
Test status
Simulation time 26327724 ps
CPU time 0.93 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 194892 kb
Host smart-1729acf5-26c2-40ec-80e2-053f010d7601
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051417781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1
051417781
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3747526755
Short name T153
Test name
Test status
Simulation time 216189378 ps
CPU time 3.14 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 195124 kb
Host smart-f3065622-1352-4b4a-8f4c-f58a976356d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747526755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
747526755
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1692846785
Short name T644
Test name
Test status
Simulation time 109041692 ps
CPU time 0.62 seconds
Started Aug 04 04:27:17 PM PDT 24
Finished Aug 04 04:27:17 PM PDT 24
Peak memory 197668 kb
Host smart-8e9edb02-c794-4459-8e5a-55b4e866171f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692846785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
692846785
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.209806139
Short name T65
Test name
Test status
Simulation time 146651995 ps
CPU time 0.92 seconds
Started Aug 04 04:27:00 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 196064 kb
Host smart-4850b463-17bf-4113-8907-9041e3012a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209806139 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.209806139
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1191204310
Short name T100
Test name
Test status
Simulation time 42218778 ps
CPU time 0.65 seconds
Started Aug 04 04:27:13 PM PDT 24
Finished Aug 04 04:27:14 PM PDT 24
Peak memory 197136 kb
Host smart-6de162ca-9335-41d9-855a-a12b70105167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191204310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1191204310
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3647346880
Short name T642
Test name
Test status
Simulation time 40214592 ps
CPU time 0.64 seconds
Started Aug 04 04:27:22 PM PDT 24
Finished Aug 04 04:27:23 PM PDT 24
Peak memory 194968 kb
Host smart-9d53b1a6-b163-40a8-b6ed-eda515748f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647346880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3647346880
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.178561414
Short name T722
Test name
Test status
Simulation time 78889262 ps
CPU time 0.76 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 195004 kb
Host smart-22784bb0-ab13-4a41-9edb-abd814ffafd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178561414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sam
e_csr_outstanding.178561414
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.772955679
Short name T674
Test name
Test status
Simulation time 80027423 ps
CPU time 1.51 seconds
Started Aug 04 04:27:00 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 196228 kb
Host smart-0b7d6864-5b84-4e0a-87aa-b112ae165f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772955679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.772955679
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1756690631
Short name T659
Test name
Test status
Simulation time 449481497 ps
CPU time 1.42 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 195260 kb
Host smart-1ddb06a5-4ec9-455e-a7ef-74f07263e39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756690631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1756690631
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.4063837903
Short name T668
Test name
Test status
Simulation time 42348815 ps
CPU time 0.58 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 194884 kb
Host smart-a0d2faf6-c19a-46b1-8f96-d81dfa7660e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063837903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.4063837903
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3841765184
Short name T683
Test name
Test status
Simulation time 51551162 ps
CPU time 0.62 seconds
Started Aug 04 04:27:15 PM PDT 24
Finished Aug 04 04:27:16 PM PDT 24
Peak memory 194896 kb
Host smart-b2583cf6-426e-4d70-b460-6cfd70a9b819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841765184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3841765184
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4154385037
Short name T631
Test name
Test status
Simulation time 42515165 ps
CPU time 0.57 seconds
Started Aug 04 04:27:37 PM PDT 24
Finished Aug 04 04:27:38 PM PDT 24
Peak memory 194908 kb
Host smart-caa7b017-ae1e-45dc-856e-3663e6f81503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154385037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.4154385037
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2188961487
Short name T651
Test name
Test status
Simulation time 20070502 ps
CPU time 0.62 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194820 kb
Host smart-2dcf755a-fc71-4682-acfc-195034c1578f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188961487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2188961487
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2883671388
Short name T729
Test name
Test status
Simulation time 20197817 ps
CPU time 0.58 seconds
Started Aug 04 04:27:25 PM PDT 24
Finished Aug 04 04:27:25 PM PDT 24
Peak memory 194836 kb
Host smart-5b7e552a-50c0-40a5-a6ee-483a3d868f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883671388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2883671388
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3208565648
Short name T670
Test name
Test status
Simulation time 19738052 ps
CPU time 0.61 seconds
Started Aug 04 04:27:24 PM PDT 24
Finished Aug 04 04:27:24 PM PDT 24
Peak memory 194824 kb
Host smart-36b066cf-00cd-4aa8-aa23-7222b5fb5b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208565648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3208565648
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1242897524
Short name T721
Test name
Test status
Simulation time 20116181 ps
CPU time 0.57 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 194792 kb
Host smart-e814f7a0-d825-466e-9338-bab30a824039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242897524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1242897524
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.356834301
Short name T689
Test name
Test status
Simulation time 21474936 ps
CPU time 0.6 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 194856 kb
Host smart-aa964ff0-2197-4826-b15e-527422d46445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356834301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.356834301
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.1007734760
Short name T633
Test name
Test status
Simulation time 51967624 ps
CPU time 0.59 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194920 kb
Host smart-5506a49a-3022-48c2-9a5e-a0bfd8897626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007734760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.1007734760
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.438151822
Short name T639
Test name
Test status
Simulation time 27834450 ps
CPU time 0.61 seconds
Started Aug 04 04:27:19 PM PDT 24
Finished Aug 04 04:27:20 PM PDT 24
Peak memory 194896 kb
Host smart-00755a6e-59f0-4571-8e8d-8953d68cba59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438151822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.438151822
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3136954328
Short name T93
Test name
Test status
Simulation time 23546799 ps
CPU time 0.95 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 198400 kb
Host smart-2c9e30ec-44f0-4351-adf8-d72370b24582
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136954328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
136954328
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2966681293
Short name T698
Test name
Test status
Simulation time 121462811 ps
CPU time 1.88 seconds
Started Aug 04 04:27:08 PM PDT 24
Finished Aug 04 04:27:10 PM PDT 24
Peak memory 195056 kb
Host smart-adff1994-0667-4a0d-a9a4-d8feaedd34b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966681293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
966681293
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.586841611
Short name T102
Test name
Test status
Simulation time 24736069 ps
CPU time 0.63 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 197428 kb
Host smart-45fed172-7e38-4d14-a8ba-e557e262ebb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586841611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.586841611
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3089769090
Short name T628
Test name
Test status
Simulation time 35219912 ps
CPU time 0.63 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 194948 kb
Host smart-2b7bec49-de5f-41e8-a5a9-58bcade0c139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089769090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3089769090
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2523979480
Short name T632
Test name
Test status
Simulation time 18574938 ps
CPU time 0.59 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194900 kb
Host smart-338f5e3c-f1cb-4ec0-b22a-c3f9b9fc6bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523979480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.2523979480
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.940520367
Short name T108
Test name
Test status
Simulation time 73715039 ps
CPU time 0.74 seconds
Started Aug 04 04:26:52 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 198212 kb
Host smart-aac4236b-3b37-4e60-ab6c-b15b6535030c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940520367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.940520367
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1962139811
Short name T647
Test name
Test status
Simulation time 112426487 ps
CPU time 1.34 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 196240 kb
Host smart-21bc38e9-477a-4bd8-9587-39e9c8b3ce31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962139811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1962139811
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3707164742
Short name T731
Test name
Test status
Simulation time 519176189 ps
CPU time 1.52 seconds
Started Aug 04 04:27:04 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 200488 kb
Host smart-16d2bb67-671f-4ff8-bb78-4cfa3cb6d0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707164742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3707164742
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3146181441
Short name T636
Test name
Test status
Simulation time 21829326 ps
CPU time 0.59 seconds
Started Aug 04 04:27:34 PM PDT 24
Finished Aug 04 04:27:35 PM PDT 24
Peak memory 194860 kb
Host smart-55467b03-a5ff-43de-846a-c7d1abadd1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146181441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3146181441
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1551668655
Short name T643
Test name
Test status
Simulation time 26360622 ps
CPU time 0.57 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194912 kb
Host smart-19f1ff0f-25d7-4fab-b1a9-239d2c83d965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551668655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1551668655
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.673911587
Short name T634
Test name
Test status
Simulation time 31744181 ps
CPU time 0.58 seconds
Started Aug 04 04:27:07 PM PDT 24
Finished Aug 04 04:27:08 PM PDT 24
Peak memory 194868 kb
Host smart-e2f650fc-ecf7-4940-8add-65996ac87a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673911587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.673911587
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3060832738
Short name T685
Test name
Test status
Simulation time 41303460 ps
CPU time 0.57 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194912 kb
Host smart-7498809c-a902-45bb-9e33-52f7b4799240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060832738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3060832738
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.350146330
Short name T650
Test name
Test status
Simulation time 18852514 ps
CPU time 0.6 seconds
Started Aug 04 04:27:06 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 194916 kb
Host smart-9d1c2946-0ca5-436d-a6bc-320f777c89b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350146330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.350146330
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3154298237
Short name T696
Test name
Test status
Simulation time 20106129 ps
CPU time 0.61 seconds
Started Aug 04 04:27:25 PM PDT 24
Finished Aug 04 04:27:26 PM PDT 24
Peak memory 194976 kb
Host smart-cf520d7e-cdc0-4e82-af9e-aca2bc412a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154298237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3154298237
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3552898034
Short name T148
Test name
Test status
Simulation time 128964626 ps
CPU time 0.57 seconds
Started Aug 04 04:27:07 PM PDT 24
Finished Aug 04 04:27:08 PM PDT 24
Peak memory 194840 kb
Host smart-1ddd5e7d-af1e-4e8f-b4ee-8ed2a11f4cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552898034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3552898034
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1420112553
Short name T690
Test name
Test status
Simulation time 29004328 ps
CPU time 0.59 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 194852 kb
Host smart-31294245-51ed-47f1-9cf0-b336862802ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420112553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1420112553
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2706241081
Short name T684
Test name
Test status
Simulation time 53185517 ps
CPU time 0.59 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 194880 kb
Host smart-9436fe8e-127c-4e8e-b72d-67c1c7ab859d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706241081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2706241081
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.897403159
Short name T150
Test name
Test status
Simulation time 29177074 ps
CPU time 0.64 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194916 kb
Host smart-73e3b374-355d-4b12-a53c-b9f63ce33793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897403159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.897403159
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2139402707
Short name T637
Test name
Test status
Simulation time 43165318 ps
CPU time 0.76 seconds
Started Aug 04 04:26:46 PM PDT 24
Finished Aug 04 04:26:47 PM PDT 24
Peak memory 197180 kb
Host smart-64acd39d-7bbc-4018-ba41-9e427e5b46f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139402707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2
139402707
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.472831861
Short name T101
Test name
Test status
Simulation time 606170244 ps
CPU time 3.46 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 195160 kb
Host smart-e27c5787-5ad3-4a70-91c3-e38de7a108da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472831861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.472831861
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.923885427
Short name T98
Test name
Test status
Simulation time 53660482 ps
CPU time 0.62 seconds
Started Aug 04 04:26:52 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 194936 kb
Host smart-847077a9-2bd2-4443-a1a1-3a3fdcea06ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923885427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.923885427
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2257733374
Short name T718
Test name
Test status
Simulation time 100184237 ps
CPU time 0.76 seconds
Started Aug 04 04:26:49 PM PDT 24
Finished Aug 04 04:26:49 PM PDT 24
Peak memory 195116 kb
Host smart-e511b2de-7c2e-4fc1-96e5-7cf0fc662bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257733374 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2257733374
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.62948179
Short name T708
Test name
Test status
Simulation time 48942843 ps
CPU time 0.64 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 197052 kb
Host smart-9809cc7b-1b73-4be7-bf6c-6c8a3abef299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62948179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.62948179
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1267593876
Short name T629
Test name
Test status
Simulation time 35439777 ps
CPU time 0.58 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 194880 kb
Host smart-0c661021-47fd-443f-bc62-4bda4be2f755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267593876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1267593876
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1718423198
Short name T700
Test name
Test status
Simulation time 40308211 ps
CPU time 0.92 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 194944 kb
Host smart-6ce1146e-6e09-4508-a632-306f09372cf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718423198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1718423198
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.419083312
Short name T69
Test name
Test status
Simulation time 220805929 ps
CPU time 1.46 seconds
Started Aug 04 04:26:56 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 196204 kb
Host smart-7d13957c-ba93-4c10-8bb7-e0ec1fd7d7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419083312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.419083312
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1060050641
Short name T144
Test name
Test status
Simulation time 399945309 ps
CPU time 1.56 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 195244 kb
Host smart-9798064d-3518-4954-849f-19b94f987a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060050641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1060050641
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2668296555
Short name T724
Test name
Test status
Simulation time 26946448 ps
CPU time 0.59 seconds
Started Aug 04 04:27:38 PM PDT 24
Finished Aug 04 04:27:39 PM PDT 24
Peak memory 194888 kb
Host smart-539f6952-2e42-48cc-b783-c2952c6c044b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668296555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2668296555
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1242628177
Short name T688
Test name
Test status
Simulation time 52689408 ps
CPU time 0.68 seconds
Started Aug 04 04:26:57 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 195276 kb
Host smart-298dd00d-5412-4551-b209-bb6f157adea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242628177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1242628177
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1401012312
Short name T646
Test name
Test status
Simulation time 24712774 ps
CPU time 0.58 seconds
Started Aug 04 04:27:07 PM PDT 24
Finished Aug 04 04:27:08 PM PDT 24
Peak memory 194912 kb
Host smart-0f77db24-2b4f-4177-a67e-213f36d6ac4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401012312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1401012312
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1061005580
Short name T720
Test name
Test status
Simulation time 21174603 ps
CPU time 0.6 seconds
Started Aug 04 04:27:23 PM PDT 24
Finished Aug 04 04:27:24 PM PDT 24
Peak memory 194872 kb
Host smart-dfee5463-0ddd-4c50-94bc-b0faf6005657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061005580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1061005580
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1718434088
Short name T630
Test name
Test status
Simulation time 21541002 ps
CPU time 0.61 seconds
Started Aug 04 04:27:27 PM PDT 24
Finished Aug 04 04:27:27 PM PDT 24
Peak memory 194896 kb
Host smart-ecf6fb5c-da37-481d-bbda-b2f55aa31fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718434088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1718434088
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3881596379
Short name T152
Test name
Test status
Simulation time 45893667 ps
CPU time 0.63 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:27:09 PM PDT 24
Peak memory 195272 kb
Host smart-ad50cef4-e6ad-4e2a-ae52-eef5941ecebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881596379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3881596379
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1680237434
Short name T655
Test name
Test status
Simulation time 28337885 ps
CPU time 0.6 seconds
Started Aug 04 04:27:11 PM PDT 24
Finished Aug 04 04:27:12 PM PDT 24
Peak memory 194888 kb
Host smart-8d8ba90f-587b-4da9-b87d-569fc9316c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680237434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1680237434
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1394609332
Short name T717
Test name
Test status
Simulation time 19507056 ps
CPU time 0.59 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194908 kb
Host smart-fd3f906d-fb2b-480a-a347-39b2a80a7bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394609332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1394609332
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1174583146
Short name T714
Test name
Test status
Simulation time 18682457 ps
CPU time 0.58 seconds
Started Aug 04 04:27:23 PM PDT 24
Finished Aug 04 04:27:24 PM PDT 24
Peak memory 194888 kb
Host smart-fc9885af-972b-44d6-bd65-6f112571346f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174583146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1174583146
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2304166958
Short name T736
Test name
Test status
Simulation time 20485102 ps
CPU time 0.59 seconds
Started Aug 04 04:27:08 PM PDT 24
Finished Aug 04 04:27:09 PM PDT 24
Peak memory 194864 kb
Host smart-53840851-e01b-4890-bf90-ef73bd71be4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304166958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2304166958
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3330734111
Short name T648
Test name
Test status
Simulation time 58623712 ps
CPU time 0.91 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 200348 kb
Host smart-9e34f6b6-9a08-4142-a91c-89c73946d51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330734111 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3330734111
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.265778492
Short name T99
Test name
Test status
Simulation time 88996746 ps
CPU time 0.66 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194980 kb
Host smart-2f57fa9b-9015-451f-b738-8bd2cf636fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265778492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.265778492
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3634318453
Short name T67
Test name
Test status
Simulation time 54013613 ps
CPU time 0.59 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 194896 kb
Host smart-20f2ba77-03a1-4cb5-890d-66917fffb219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634318453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3634318453
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2864949805
Short name T110
Test name
Test status
Simulation time 147781527 ps
CPU time 0.69 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:54 PM PDT 24
Peak memory 194960 kb
Host smart-228a885d-b624-4866-8f62-c09ab2ebaf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864949805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2864949805
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.766677828
Short name T732
Test name
Test status
Simulation time 147521275 ps
CPU time 2.01 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 196216 kb
Host smart-aeb166cb-918b-48a2-86bd-fbc6f0430baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766677828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.766677828
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2174284218
Short name T660
Test name
Test status
Simulation time 42299021 ps
CPU time 0.79 seconds
Started Aug 04 04:26:59 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 195188 kb
Host smart-79b11825-2f47-4e8e-b52f-0ac47dbdc0b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174284218 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2174284218
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.582104882
Short name T675
Test name
Test status
Simulation time 21237445 ps
CPU time 0.62 seconds
Started Aug 04 04:27:08 PM PDT 24
Finished Aug 04 04:27:09 PM PDT 24
Peak memory 197144 kb
Host smart-b5eb7873-b130-4159-aefc-44e0c00f4f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582104882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.582104882
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3802179754
Short name T725
Test name
Test status
Simulation time 45922680 ps
CPU time 0.61 seconds
Started Aug 04 04:27:46 PM PDT 24
Finished Aug 04 04:27:47 PM PDT 24
Peak memory 194908 kb
Host smart-9ddddee0-7a53-4436-b96d-dd0fd3d27f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802179754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3802179754
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1831598689
Short name T106
Test name
Test status
Simulation time 46933023 ps
CPU time 0.9 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 194952 kb
Host smart-d637387e-6bfe-418e-9c28-776fd59679b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831598689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1831598689
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1037982430
Short name T676
Test name
Test status
Simulation time 75186641 ps
CPU time 1.93 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:10 PM PDT 24
Peak memory 196284 kb
Host smart-78772ee6-696c-4256-b95f-b6b029ba2c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037982430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.1037982430
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2314145387
Short name T710
Test name
Test status
Simulation time 394789016 ps
CPU time 1.48 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 200444 kb
Host smart-390e95ae-cb53-4503-bd1c-b547ca1c8545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314145387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.2314145387
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2196032470
Short name T699
Test name
Test status
Simulation time 41203028 ps
CPU time 0.79 seconds
Started Aug 04 04:27:02 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 195104 kb
Host smart-cf616b1b-0f47-4979-8c82-c6e9adae6497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196032470 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2196032470
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.266898023
Short name T94
Test name
Test status
Simulation time 33433032 ps
CPU time 0.63 seconds
Started Aug 04 04:27:29 PM PDT 24
Finished Aug 04 04:27:30 PM PDT 24
Peak memory 197160 kb
Host smart-faf666d2-1a2c-4a8b-9e8d-00ff0a3c4782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266898023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.266898023
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.551199537
Short name T679
Test name
Test status
Simulation time 20319244 ps
CPU time 0.66 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194888 kb
Host smart-8ef443c3-fecd-417f-b055-1dc4b46a8686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551199537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.551199537
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1940076226
Short name T691
Test name
Test status
Simulation time 130885410 ps
CPU time 0.76 seconds
Started Aug 04 04:27:28 PM PDT 24
Finished Aug 04 04:27:29 PM PDT 24
Peak memory 197172 kb
Host smart-18480b43-4046-4eca-988f-dc7b9dde4777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940076226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1940076226
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2679067811
Short name T681
Test name
Test status
Simulation time 131762694 ps
CPU time 1.76 seconds
Started Aug 04 04:27:20 PM PDT 24
Finished Aug 04 04:27:22 PM PDT 24
Peak memory 196248 kb
Host smart-0d3412e1-817b-4cbd-b8b0-3474085581e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679067811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2679067811
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3620985987
Short name T118
Test name
Test status
Simulation time 627372688 ps
CPU time 1.49 seconds
Started Aug 04 04:27:44 PM PDT 24
Finished Aug 04 04:27:46 PM PDT 24
Peak memory 195172 kb
Host smart-2d55e09b-0cc7-441b-9132-8987996cad46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620985987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.3620985987
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4278333960
Short name T664
Test name
Test status
Simulation time 50511279 ps
CPU time 1.22 seconds
Started Aug 04 04:27:54 PM PDT 24
Finished Aug 04 04:27:55 PM PDT 24
Peak memory 198424 kb
Host smart-0766e867-8423-4110-9a36-0cc52c9a38a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278333960 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.4278333960
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3121646266
Short name T97
Test name
Test status
Simulation time 22892348 ps
CPU time 0.68 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:26:59 PM PDT 24
Peak memory 194992 kb
Host smart-0a4f2860-e010-4104-ab24-69897238f8d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121646266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3121646266
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3696854593
Short name T151
Test name
Test status
Simulation time 179449537 ps
CPU time 0.6 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:55 PM PDT 24
Peak memory 194892 kb
Host smart-3cd488df-c4f2-49fb-807b-512e06bb80d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696854593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3696854593
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2171792776
Short name T687
Test name
Test status
Simulation time 28393772 ps
CPU time 0.86 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 198348 kb
Host smart-dcd58695-77c5-4bab-a2f1-aec210caf012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171792776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2171792776
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1682649561
Short name T716
Test name
Test status
Simulation time 152733954 ps
CPU time 1.8 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 195200 kb
Host smart-fba63a9c-afd7-43ce-9d30-8fb391a31173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682649561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1682649561
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3901024470
Short name T60
Test name
Test status
Simulation time 766426308 ps
CPU time 1.62 seconds
Started Aug 04 04:27:05 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 200464 kb
Host smart-cbb9203a-12a8-4ee6-bcf0-5942ce04ea88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901024470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.3901024470
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3661751572
Short name T680
Test name
Test status
Simulation time 48841875 ps
CPU time 1.25 seconds
Started Aug 04 04:27:33 PM PDT 24
Finished Aug 04 04:27:34 PM PDT 24
Peak memory 197260 kb
Host smart-84e53351-6519-4b1a-92a0-0f0d4d7fb509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661751572 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3661751572
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3684928551
Short name T68
Test name
Test status
Simulation time 42480027 ps
CPU time 0.6 seconds
Started Aug 04 04:27:53 PM PDT 24
Finished Aug 04 04:27:54 PM PDT 24
Peak memory 194904 kb
Host smart-76f7df98-85f3-42d8-9057-db2cdb08fa25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684928551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3684928551
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1399602372
Short name T702
Test name
Test status
Simulation time 114039924 ps
CPU time 0.89 seconds
Started Aug 04 04:27:30 PM PDT 24
Finished Aug 04 04:27:31 PM PDT 24
Peak memory 198172 kb
Host smart-1e470b03-2b54-4a6a-b16a-7c5a264b1666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399602372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.1399602372
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.655077349
Short name T26
Test name
Test status
Simulation time 189369069 ps
CPU time 1.1 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:09 PM PDT 24
Peak memory 200364 kb
Host smart-1f58c35a-8b43-4042-83f1-b52b49779826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655077349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
655077349
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.892665454
Short name T173
Test name
Test status
Simulation time 104587623 ps
CPU time 0.82 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 200164 kb
Host smart-a2bf1cc0-3437-4ce0-a344-3c323cf5e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892665454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.892665454
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2819046320
Short name T135
Test name
Test status
Simulation time 56531568 ps
CPU time 0.75 seconds
Started Aug 04 05:15:33 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 199324 kb
Host smart-2a5b0872-d636-401d-906d-aa7f829c9654
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819046320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2819046320
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2478464749
Short name T533
Test name
Test status
Simulation time 27708088 ps
CPU time 0.63 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 197880 kb
Host smart-836f0726-b524-47e3-ae56-a85efa178e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478464749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2478464749
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3551364934
Short name T352
Test name
Test status
Simulation time 163981151 ps
CPU time 1 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 198004 kb
Host smart-450a0eeb-2af5-4570-b092-a8c56297d270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551364934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3551364934
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3938667448
Short name T329
Test name
Test status
Simulation time 53966863 ps
CPU time 0.62 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 197360 kb
Host smart-1f1ff9d5-5f92-4ee9-910a-ebd226b462f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938667448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3938667448
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3636620402
Short name T579
Test name
Test status
Simulation time 74234229 ps
CPU time 0.6 seconds
Started Aug 04 05:15:33 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 197980 kb
Host smart-e77763ea-fc4e-4da7-a842-827e781f8b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636620402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3636620402
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.578504226
Short name T184
Test name
Test status
Simulation time 81167007 ps
CPU time 0.66 seconds
Started Aug 04 05:15:30 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 201356 kb
Host smart-5a84c6db-7af3-4660-be16-b17f7f4e67eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578504226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.578504226
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3391972684
Short name T504
Test name
Test status
Simulation time 49413473 ps
CPU time 0.78 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 198280 kb
Host smart-893d1a25-5643-4e1c-894f-2ee6622fb93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391972684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3391972684
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.81192854
Short name T339
Test name
Test status
Simulation time 147010150 ps
CPU time 0.82 seconds
Started Aug 04 05:15:30 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 209416 kb
Host smart-b571c9e7-b1d1-4f13-bbba-6bdd2aebfb8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81192854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.81192854
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1807227604
Short name T76
Test name
Test status
Simulation time 91807576 ps
CPU time 0.84 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 199112 kb
Host smart-81d4ba8f-2b1d-4bd3-ba90-63ef2e4326aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807227604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1807227604
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.170137655
Short name T78
Test name
Test status
Simulation time 35603600 ps
CPU time 0.68 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 199368 kb
Host smart-4d668601-b402-408f-aac4-d295f18e524f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170137655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.170137655
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1601633895
Short name T280
Test name
Test status
Simulation time 32321511 ps
CPU time 0.73 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 199184 kb
Host smart-3368ccc8-0b53-4263-84a5-e8fdf375bfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601633895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1601633895
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1403304067
Short name T503
Test name
Test status
Simulation time 52247060 ps
CPU time 0.78 seconds
Started Aug 04 05:15:33 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 198412 kb
Host smart-822bfe26-3459-48e8-a896-685fd31e3f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403304067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1403304067
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2895933920
Short name T403
Test name
Test status
Simulation time 29714789 ps
CPU time 0.64 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 197948 kb
Host smart-00778476-f0d6-4b78-9b63-6bb547dde57d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895933920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.2895933920
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.96109470
Short name T402
Test name
Test status
Simulation time 1265329515 ps
CPU time 0.99 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 198112 kb
Host smart-94964606-9b42-48c6-b422-efa1d2488d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96109470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.96109470
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3683197616
Short name T344
Test name
Test status
Simulation time 48129299 ps
CPU time 0.66 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 198028 kb
Host smart-2800b07a-ce6f-4db8-9e03-62e16f998939
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683197616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3683197616
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1053435924
Short name T421
Test name
Test status
Simulation time 22783849 ps
CPU time 0.62 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 198440 kb
Host smart-957bb76f-9a71-462d-9aba-e01b036f8a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053435924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1053435924
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2617380373
Short name T200
Test name
Test status
Simulation time 302316816 ps
CPU time 0.66 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 201300 kb
Host smart-11956b47-3b9c-4436-acad-e470f23ad0c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617380373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2617380373
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.3266494263
Short name T373
Test name
Test status
Simulation time 78234767 ps
CPU time 0.69 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 199108 kb
Host smart-935e40c7-15ec-4ff3-83c7-f391b70a5d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266494263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3266494263
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.174086608
Short name T40
Test name
Test status
Simulation time 351853045 ps
CPU time 0.78 seconds
Started Aug 04 05:15:33 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 209412 kb
Host smart-33e449c1-9936-4bbf-82a3-e5d015d52194
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174086608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.174086608
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.205754424
Short name T22
Test name
Test status
Simulation time 373797237 ps
CPU time 1.25 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 217380 kb
Host smart-a3ab2019-eab6-4413-aed2-e2f92d9aeccc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205754424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.205754424
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1802378594
Short name T246
Test name
Test status
Simulation time 59325517 ps
CPU time 0.77 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 198140 kb
Host smart-ec55f78a-dcd2-4d5f-ab09-d08a6dc57be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802378594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1802378594
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3290043226
Short name T488
Test name
Test status
Simulation time 56570057 ps
CPU time 0.65 seconds
Started Aug 04 05:15:30 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 199384 kb
Host smart-647f1180-7e81-49e7-b5d1-a72146ecd280
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290043226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3290043226
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.112875485
Short name T300
Test name
Test status
Simulation time 42003478 ps
CPU time 0.66 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 198640 kb
Host smart-4a53a209-bd55-47de-be98-4ca0b963225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112875485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.112875485
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2723038514
Short name T133
Test name
Test status
Simulation time 96009171 ps
CPU time 0.68 seconds
Started Aug 04 05:15:54 PM PDT 24
Finished Aug 04 05:15:55 PM PDT 24
Peak memory 198592 kb
Host smart-21d4b4c8-b2d8-4dd3-8597-d3b11c54a751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723038514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2723038514
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1701919916
Short name T304
Test name
Test status
Simulation time 30257430 ps
CPU time 0.63 seconds
Started Aug 04 05:15:54 PM PDT 24
Finished Aug 04 05:15:55 PM PDT 24
Peak memory 197944 kb
Host smart-1120e31c-146e-4139-9600-6b672df0f732
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701919916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1701919916
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.912392967
Short name T534
Test name
Test status
Simulation time 164042897 ps
CPU time 0.96 seconds
Started Aug 04 05:15:53 PM PDT 24
Finished Aug 04 05:15:54 PM PDT 24
Peak memory 198104 kb
Host smart-cc78edbb-6408-49ba-a86b-65423f499b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912392967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.912392967
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2549245795
Short name T425
Test name
Test status
Simulation time 33749543 ps
CPU time 0.65 seconds
Started Aug 04 05:15:55 PM PDT 24
Finished Aug 04 05:15:56 PM PDT 24
Peak memory 197952 kb
Host smart-0157dc2c-1cbc-4841-b9c5-80451b360b1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549245795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2549245795
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.892047511
Short name T222
Test name
Test status
Simulation time 31984555 ps
CPU time 0.67 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 198304 kb
Host smart-8b08e51a-92fd-404b-86e6-9516ff39ef87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892047511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.892047511
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.3173090563
Short name T404
Test name
Test status
Simulation time 76416102 ps
CPU time 0.78 seconds
Started Aug 04 05:15:57 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 199092 kb
Host smart-59bcd94a-d708-4489-afaa-b672933d30b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173090563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3173090563
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.508729095
Short name T374
Test name
Test status
Simulation time 104907278 ps
CPU time 0.96 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 209500 kb
Host smart-8bc4733c-5d50-48a6-b08d-8426dfef7ddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508729095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.508729095
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.438184234
Short name T616
Test name
Test status
Simulation time 124020255 ps
CPU time 0.87 seconds
Started Aug 04 05:15:54 PM PDT 24
Finished Aug 04 05:15:55 PM PDT 24
Peak memory 199460 kb
Host smart-2df3e3e6-bcf6-4b4f-9bb1-ccfded9128e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438184234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_
mubi.438184234
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1716701644
Short name T366
Test name
Test status
Simulation time 46744732 ps
CPU time 0.62 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:50 PM PDT 24
Peak memory 198508 kb
Host smart-d2d2c90c-ec37-4b52-9c37-3dda4c77a754
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716701644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1716701644
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.386530450
Short name T603
Test name
Test status
Simulation time 24229779 ps
CPU time 0.67 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 198512 kb
Host smart-d07f67f7-7dbc-4d3e-a14d-ed8e16771961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386530450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.386530450
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1560913613
Short name T309
Test name
Test status
Simulation time 33234849 ps
CPU time 0.6 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198064 kb
Host smart-bced7be5-f1cc-400c-823e-1fa844bf1c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560913613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1560913613
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1495967999
Short name T271
Test name
Test status
Simulation time 166498824 ps
CPU time 1 seconds
Started Aug 04 05:16:07 PM PDT 24
Finished Aug 04 05:16:08 PM PDT 24
Peak memory 198404 kb
Host smart-adfc4286-fab8-4f2a-868f-7a7dcefaea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495967999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1495967999
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.3318044324
Short name T497
Test name
Test status
Simulation time 24434653 ps
CPU time 0.63 seconds
Started Aug 04 05:15:59 PM PDT 24
Finished Aug 04 05:15:59 PM PDT 24
Peak memory 198024 kb
Host smart-8c9a04cf-0dc1-4bce-aafb-733e7978e341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318044324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3318044324
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1866492094
Short name T618
Test name
Test status
Simulation time 55556557 ps
CPU time 0.62 seconds
Started Aug 04 05:16:03 PM PDT 24
Finished Aug 04 05:16:03 PM PDT 24
Peak memory 198024 kb
Host smart-decb4170-d2c4-44c5-8b36-58fa07c40903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866492094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1866492094
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.687390798
Short name T326
Test name
Test status
Simulation time 24126975 ps
CPU time 0.68 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 199192 kb
Host smart-920b5fbc-c8c2-40b5-898f-7b058b827305
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687390798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.687390798
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3682614574
Short name T336
Test name
Test status
Simulation time 106001261 ps
CPU time 0.91 seconds
Started Aug 04 05:15:57 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 209456 kb
Host smart-48097db2-5266-4e98-8f95-d71207ba8d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682614574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3682614574
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2033343820
Short name T626
Test name
Test status
Simulation time 55033082 ps
CPU time 0.74 seconds
Started Aug 04 05:15:59 PM PDT 24
Finished Aug 04 05:16:00 PM PDT 24
Peak memory 197916 kb
Host smart-e2f6f6dd-a496-4039-b5f5-8c0b8d6e782b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033343820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2033343820
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.216946398
Short name T263
Test name
Test status
Simulation time 27759129 ps
CPU time 0.68 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 199376 kb
Host smart-19ad92b9-f774-4a88-beb7-2795914022c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216946398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.216946398
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.2641288768
Short name T241
Test name
Test status
Simulation time 30033297 ps
CPU time 0.61 seconds
Started Aug 04 05:15:56 PM PDT 24
Finished Aug 04 05:15:57 PM PDT 24
Peak memory 198500 kb
Host smart-de3ecf70-a4a4-4485-af01-d03fbc0b3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641288768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2641288768
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.630918646
Short name T583
Test name
Test status
Simulation time 48936617 ps
CPU time 0.8 seconds
Started Aug 04 05:15:59 PM PDT 24
Finished Aug 04 05:16:00 PM PDT 24
Peak memory 199212 kb
Host smart-da2ade47-073e-4bc9-b78a-90734e172a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630918646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.630918646
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1680473975
Short name T604
Test name
Test status
Simulation time 47748972 ps
CPU time 0.63 seconds
Started Aug 04 05:15:56 PM PDT 24
Finished Aug 04 05:15:57 PM PDT 24
Peak memory 197980 kb
Host smart-16cb8cd3-8032-46e3-b700-6ffd9b04cb13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680473975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1680473975
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.278165843
Short name T433
Test name
Test status
Simulation time 949993023 ps
CPU time 0.96 seconds
Started Aug 04 05:16:10 PM PDT 24
Finished Aug 04 05:16:11 PM PDT 24
Peak memory 198128 kb
Host smart-aee8eab8-9861-42d8-bfc0-940da5a50438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278165843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.278165843
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.2595206381
Short name T567
Test name
Test status
Simulation time 34706159 ps
CPU time 0.63 seconds
Started Aug 04 05:16:00 PM PDT 24
Finished Aug 04 05:16:01 PM PDT 24
Peak memory 197292 kb
Host smart-1c7532e7-62ef-41da-a29f-fe37de72184f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595206381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2595206381
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.476132326
Short name T561
Test name
Test status
Simulation time 41776418 ps
CPU time 0.65 seconds
Started Aug 04 05:16:04 PM PDT 24
Finished Aug 04 05:16:05 PM PDT 24
Peak memory 198032 kb
Host smart-5ac041ea-74f0-498a-9e57-719c05f730b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476132326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.476132326
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.494754071
Short name T217
Test name
Test status
Simulation time 43523424 ps
CPU time 0.69 seconds
Started Aug 04 05:16:05 PM PDT 24
Finished Aug 04 05:16:05 PM PDT 24
Peak memory 198296 kb
Host smart-88f10fed-3cf0-4973-b384-685be246c100
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494754071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.494754071
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.4000383573
Short name T466
Test name
Test status
Simulation time 131792956 ps
CPU time 0.78 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 209512 kb
Host smart-e63eea8b-d8b0-4e59-a68b-ec269c2008bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000383573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.4000383573
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1794324013
Short name T297
Test name
Test status
Simulation time 81764852 ps
CPU time 0.81 seconds
Started Aug 04 05:16:03 PM PDT 24
Finished Aug 04 05:16:04 PM PDT 24
Peak memory 199412 kb
Host smart-cd92e55d-2eeb-4cf6-9d44-009e8dc6ca61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794324013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1794324013
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1634798288
Short name T51
Test name
Test status
Simulation time 34326010 ps
CPU time 0.65 seconds
Started Aug 04 05:16:03 PM PDT 24
Finished Aug 04 05:16:03 PM PDT 24
Peak memory 199312 kb
Host smart-53503f83-3477-4313-8de0-bfb04d8f545d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634798288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1634798288
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.993359368
Short name T596
Test name
Test status
Simulation time 131659067 ps
CPU time 0.81 seconds
Started Aug 04 05:16:05 PM PDT 24
Finished Aug 04 05:16:06 PM PDT 24
Peak memory 200132 kb
Host smart-215bf587-f7f3-481d-ba60-04d91ca572a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993359368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.993359368
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3627173181
Short name T211
Test name
Test status
Simulation time 59296180 ps
CPU time 0.8 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 199020 kb
Host smart-fa556e0b-4ccc-471a-aaac-b2fe10c910a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627173181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3627173181
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2113112673
Short name T361
Test name
Test status
Simulation time 39406793 ps
CPU time 0.59 seconds
Started Aug 04 05:16:04 PM PDT 24
Finished Aug 04 05:16:05 PM PDT 24
Peak memory 198004 kb
Host smart-a266d940-40ae-413a-bc55-f683b0e1b537
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113112673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2113112673
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2568773543
Short name T124
Test name
Test status
Simulation time 160233847 ps
CPU time 1.05 seconds
Started Aug 04 05:16:09 PM PDT 24
Finished Aug 04 05:16:10 PM PDT 24
Peak memory 198116 kb
Host smart-807960ca-f815-4371-a15f-8b642c3e825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568773543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2568773543
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.403583518
Short name T318
Test name
Test status
Simulation time 48000046 ps
CPU time 0.68 seconds
Started Aug 04 05:16:02 PM PDT 24
Finished Aug 04 05:16:03 PM PDT 24
Peak memory 198032 kb
Host smart-322a775c-5176-456d-9dd1-d581044e451a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403583518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.403583518
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2220197260
Short name T190
Test name
Test status
Simulation time 69240543 ps
CPU time 0.7 seconds
Started Aug 04 05:16:09 PM PDT 24
Finished Aug 04 05:16:10 PM PDT 24
Peak memory 201456 kb
Host smart-74ebdf04-2a81-45a9-8047-90366b9faf12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220197260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2220197260
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.289717986
Short name T432
Test name
Test status
Simulation time 40145183 ps
CPU time 0.74 seconds
Started Aug 04 05:16:06 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 199176 kb
Host smart-77f40a45-87fa-4796-a7df-52b032ae38e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289717986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.289717986
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.560153954
Short name T614
Test name
Test status
Simulation time 93811387 ps
CPU time 1.03 seconds
Started Aug 04 05:16:00 PM PDT 24
Finished Aug 04 05:16:02 PM PDT 24
Peak memory 209484 kb
Host smart-14bbeacd-9add-4c61-9d39-67b343074deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560153954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.560153954
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.247066130
Short name T531
Test name
Test status
Simulation time 95497866 ps
CPU time 0.73 seconds
Started Aug 04 05:16:06 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 197752 kb
Host smart-a1dc09a2-0eda-4dde-9a3c-e40c5e302a6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247066130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.247066130
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1897719050
Short name T573
Test name
Test status
Simulation time 125946373 ps
CPU time 0.63 seconds
Started Aug 04 05:16:09 PM PDT 24
Finished Aug 04 05:16:10 PM PDT 24
Peak memory 198472 kb
Host smart-1384aae5-12fa-4b66-b56a-c2637ed7979b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897719050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1897719050
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1737664837
Short name T495
Test name
Test status
Simulation time 45944803 ps
CPU time 0.64 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 198736 kb
Host smart-37db303f-84c9-4d29-b3fd-441d92efa9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737664837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1737664837
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.4034694607
Short name T157
Test name
Test status
Simulation time 51619202 ps
CPU time 0.75 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 199076 kb
Host smart-d50467bc-998d-4a0b-a733-2ad51ad5a57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034694607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.4034694607
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2899219753
Short name T229
Test name
Test status
Simulation time 40033939 ps
CPU time 0.62 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 198048 kb
Host smart-bb25dc51-9d3f-469c-9c42-294f9b7f9804
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899219753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2899219753
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.256927000
Short name T510
Test name
Test status
Simulation time 305530032 ps
CPU time 1.02 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 198024 kb
Host smart-c379f4e1-dd01-4746-9163-e1aff23bdd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256927000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.256927000
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.973119577
Short name T400
Test name
Test status
Simulation time 46762268 ps
CPU time 0.65 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 197636 kb
Host smart-c1cba6df-051a-4387-a18a-54d1c95482ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973119577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.973119577
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3055636600
Short name T532
Test name
Test status
Simulation time 94290593 ps
CPU time 0.62 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 198404 kb
Host smart-359726d3-9028-4875-a187-0b606e7ca359
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055636600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3055636600
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1841698310
Short name T189
Test name
Test status
Simulation time 42388806 ps
CPU time 0.72 seconds
Started Aug 04 05:16:06 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 201336 kb
Host smart-9cecf8f5-fad5-4a18-9d95-0909b220dc51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841698310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1841698310
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3769054347
Short name T235
Test name
Test status
Simulation time 103753242 ps
CPU time 0.8 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 199196 kb
Host smart-693ce734-6877-4152-bdac-e2c31813ef9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769054347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3769054347
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.1526460609
Short name T328
Test name
Test status
Simulation time 103681610 ps
CPU time 0.91 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 209520 kb
Host smart-f7ec04cb-7c4a-4aae-a25f-51fa76c9d33b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526460609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.1526460609
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1414069465
Short name T314
Test name
Test status
Simulation time 129968913 ps
CPU time 0.76 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 197816 kb
Host smart-3b2e7812-ee26-4a16-bf4f-632d5e1d6cf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414069465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1414069465
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.479632285
Short name T399
Test name
Test status
Simulation time 49496249 ps
CPU time 0.62 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 198728 kb
Host smart-ac8d60f3-7977-44a7-971b-938dcc6b6530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479632285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.479632285
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1730218972
Short name T87
Test name
Test status
Simulation time 35720411 ps
CPU time 0.74 seconds
Started Aug 04 05:16:19 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 199168 kb
Host smart-a69403f3-1c15-4a12-a81c-2f6c3fe3ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730218972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1730218972
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.3411781902
Short name T160
Test name
Test status
Simulation time 55619975 ps
CPU time 0.79 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 198496 kb
Host smart-bbf75e93-394d-4b8b-bfb3-a667f5d635e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411781902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.3411781902
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.4172649624
Short name T247
Test name
Test status
Simulation time 47047344 ps
CPU time 0.61 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 197308 kb
Host smart-bbf484dc-3a51-4dd5-adc1-f35141e85c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172649624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.4172649624
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.638937135
Short name T516
Test name
Test status
Simulation time 166993323 ps
CPU time 0.95 seconds
Started Aug 04 05:16:10 PM PDT 24
Finished Aug 04 05:16:11 PM PDT 24
Peak memory 198156 kb
Host smart-e079a97f-c622-49c1-a85a-d6e31f3e3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638937135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.638937135
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.4180760788
Short name T586
Test name
Test status
Simulation time 47594811 ps
CPU time 0.72 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 198124 kb
Host smart-34c00ec1-ecae-4a47-91e7-d0a7189d65df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180760788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.4180760788
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.4164721801
Short name T469
Test name
Test status
Simulation time 37009535 ps
CPU time 0.63 seconds
Started Aug 04 05:16:13 PM PDT 24
Finished Aug 04 05:16:13 PM PDT 24
Peak memory 198108 kb
Host smart-d420671b-4ae0-40ef-8b34-cc15eeb521da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164721801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.4164721801
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2314813896
Short name T179
Test name
Test status
Simulation time 74832013 ps
CPU time 0.68 seconds
Started Aug 04 05:16:19 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 201332 kb
Host smart-24b3e21c-c422-4f2b-8505-b259a42ee8fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314813896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2314813896
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.2275189488
Short name T140
Test name
Test status
Simulation time 158364180 ps
CPU time 0.78 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 198336 kb
Host smart-046a56f6-d2b9-4491-89cf-d6c84c03fde1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275189488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.2275189488
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.5436034
Short name T486
Test name
Test status
Simulation time 105464906 ps
CPU time 0.72 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 199116 kb
Host smart-50b2e408-55c2-42e4-93f8-16adbc226114
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5436034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.5436034
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1448722958
Short name T435
Test name
Test status
Simulation time 514159482 ps
CPU time 0.84 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 209544 kb
Host smart-7fccd05a-81ab-41d4-aa87-2ad434f144b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448722958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1448722958
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2136982753
Short name T224
Test name
Test status
Simulation time 81621638 ps
CPU time 0.76 seconds
Started Aug 04 05:16:13 PM PDT 24
Finished Aug 04 05:16:14 PM PDT 24
Peak memory 199088 kb
Host smart-2ca21c4c-3795-40ee-92f4-220946427dee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136982753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2136982753
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3903981662
Short name T415
Test name
Test status
Simulation time 38033437 ps
CPU time 0.63 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 198792 kb
Host smart-cecf2d18-8399-45f9-ad6b-4dc958198137
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903981662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3903981662
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2211766465
Short name T461
Test name
Test status
Simulation time 81350162 ps
CPU time 0.64 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 198692 kb
Host smart-912caa94-4a47-453e-a43d-84d70672c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211766465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2211766465
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3569419621
Short name T131
Test name
Test status
Simulation time 86901795 ps
CPU time 0.65 seconds
Started Aug 04 05:16:17 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 198976 kb
Host smart-81a18fd9-11e5-4196-95d0-dd12d199bc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569419621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3569419621
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3950749747
Short name T293
Test name
Test status
Simulation time 38736482 ps
CPU time 0.6 seconds
Started Aug 04 05:16:14 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 197356 kb
Host smart-5937aa5b-ad1d-4e7a-b170-c1ce9b0f9a20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950749747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.3950749747
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.1635684764
Short name T47
Test name
Test status
Simulation time 317586001 ps
CPU time 0.96 seconds
Started Aug 04 05:16:14 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 198112 kb
Host smart-08f3743a-08ee-46ea-b42d-88c403d025d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635684764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1635684764
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3876746911
Short name T490
Test name
Test status
Simulation time 127275515 ps
CPU time 0.61 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 198092 kb
Host smart-64ad15a4-1bb0-4fae-bb7e-0f9fc191437f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876746911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3876746911
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.1295242493
Short name T551
Test name
Test status
Simulation time 46495879 ps
CPU time 0.63 seconds
Started Aug 04 05:16:17 PM PDT 24
Finished Aug 04 05:16:18 PM PDT 24
Peak memory 198120 kb
Host smart-e070b9b0-b77c-4704-a2c3-2824e5f29ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295242493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.1295242493
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.282832994
Short name T505
Test name
Test status
Simulation time 40287927 ps
CPU time 0.62 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 199116 kb
Host smart-9cc5ad0e-73fd-4e9f-873f-04324890eef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282832994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.282832994
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2549924971
Short name T467
Test name
Test status
Simulation time 87487351 ps
CPU time 1.05 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 209492 kb
Host smart-9ee870a1-69ee-42ff-afde-ab14f25da070
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549924971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2549924971
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.575543124
Short name T113
Test name
Test status
Simulation time 158346071 ps
CPU time 0.74 seconds
Started Aug 04 05:16:08 PM PDT 24
Finished Aug 04 05:16:09 PM PDT 24
Peak memory 198100 kb
Host smart-f8722d36-afe7-4e17-8d99-13ef6e02d3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575543124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.575543124
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3288953275
Short name T365
Test name
Test status
Simulation time 51790682 ps
CPU time 0.64 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 199280 kb
Host smart-9d48829b-5990-4b8a-ae1a-73df5eb947ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288953275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3288953275
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1997932274
Short name T82
Test name
Test status
Simulation time 87710648 ps
CPU time 0.7 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 198604 kb
Host smart-f1f2783e-c099-4e3f-be06-4221e27ada55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997932274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1997932274
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3607341010
Short name T418
Test name
Test status
Simulation time 52612506 ps
CPU time 0.77 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 199064 kb
Host smart-c455db0c-ad2c-4502-810e-4ae56aec2099
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607341010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3607341010
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.997784426
Short name T285
Test name
Test status
Simulation time 41242388 ps
CPU time 0.62 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 197228 kb
Host smart-79a37ac9-7f14-4b76-89be-fe7d9eab038c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997784426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.997784426
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.174926449
Short name T576
Test name
Test status
Simulation time 624342433 ps
CPU time 1 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 198048 kb
Host smart-88a54d5a-228b-4713-8695-187e9a841e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174926449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.174926449
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.4130807844
Short name T284
Test name
Test status
Simulation time 101939349 ps
CPU time 0.61 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 198100 kb
Host smart-c091b2d7-2f9c-4a31-a873-a661b4026f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130807844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.4130807844
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3316811854
Short name T410
Test name
Test status
Simulation time 61537086 ps
CPU time 0.6 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 198116 kb
Host smart-8e03747b-a02c-412e-9393-b4489786c0a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316811854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3316811854
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3401391065
Short name T2
Test name
Test status
Simulation time 31261260 ps
CPU time 0.7 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:18 PM PDT 24
Peak memory 198252 kb
Host smart-3f63df18-3f15-4abb-9329-05670425952c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401391065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3401391065
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.215784374
Short name T362
Test name
Test status
Simulation time 156259944 ps
CPU time 0.83 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 209536 kb
Host smart-1e47c225-b0b1-4d4a-8105-12af4861cfaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215784374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.215784374
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2639983053
Short name T414
Test name
Test status
Simulation time 65792613 ps
CPU time 0.76 seconds
Started Aug 04 05:16:10 PM PDT 24
Finished Aug 04 05:16:10 PM PDT 24
Peak memory 198384 kb
Host smart-78f65d27-0142-42ba-93c6-312348786c9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639983053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2639983053
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.1490383982
Short name T605
Test name
Test status
Simulation time 37619077 ps
CPU time 0.68 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 199280 kb
Host smart-a03d1a0f-5392-4d73-b519-45a7703a292e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490383982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.1490383982
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3468901919
Short name T83
Test name
Test status
Simulation time 36724203 ps
CPU time 0.65 seconds
Started Aug 04 05:16:16 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 198504 kb
Host smart-4657d757-a49b-41d6-86bb-ccb4c1df1930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468901919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3468901919
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1964786112
Short name T514
Test name
Test status
Simulation time 72749651 ps
CPU time 0.62 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198980 kb
Host smart-a8915a53-7cc6-4213-8475-2938d3a9bc9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964786112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1964786112
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1996474022
Short name T12
Test name
Test status
Simulation time 31435184 ps
CPU time 0.64 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 197964 kb
Host smart-5e170c4b-e984-4581-ba2a-2aa856f2c76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996474022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1996474022
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2275163690
Short name T566
Test name
Test status
Simulation time 166292425 ps
CPU time 0.92 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 198312 kb
Host smart-024b8701-bd00-462d-906b-2992f0e6e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275163690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2275163690
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.178433573
Short name T18
Test name
Test status
Simulation time 79806437 ps
CPU time 0.61 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198032 kb
Host smart-e770c55c-3b2e-4a4d-8e49-4dc5b12f1cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178433573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.178433573
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.966060561
Short name T223
Test name
Test status
Simulation time 29290115 ps
CPU time 0.62 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198024 kb
Host smart-341e06e4-2960-4963-a7a9-35f9a3741aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966060561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.966060561
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.4210659580
Short name T553
Test name
Test status
Simulation time 124651562 ps
CPU time 0.67 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 201280 kb
Host smart-9b231f2e-f3c6-439d-ac92-5c83cf2eb12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210659580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.4210659580
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3767736823
Short name T411
Test name
Test status
Simulation time 81138464 ps
CPU time 0.89 seconds
Started Aug 04 05:16:17 PM PDT 24
Finished Aug 04 05:16:18 PM PDT 24
Peak memory 199040 kb
Host smart-ba237e7a-82cd-4118-a96a-e821722aa5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767736823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3767736823
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2488754939
Short name T330
Test name
Test status
Simulation time 99670231 ps
CPU time 0.91 seconds
Started Aug 04 05:16:17 PM PDT 24
Finished Aug 04 05:16:18 PM PDT 24
Peak memory 209580 kb
Host smart-338ab96a-5e79-43cc-abca-255df42a8283
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488754939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2488754939
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3875786893
Short name T507
Test name
Test status
Simulation time 60896948 ps
CPU time 0.86 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 198160 kb
Host smart-5e733e70-35ef-49e1-96ad-808c12d45335
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875786893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3875786893
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2895814193
Short name T519
Test name
Test status
Simulation time 56468933 ps
CPU time 0.65 seconds
Started Aug 04 05:16:15 PM PDT 24
Finished Aug 04 05:16:16 PM PDT 24
Peak memory 198384 kb
Host smart-ac2814e4-ff5a-4b7f-85c4-2434df1229b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895814193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2895814193
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.3758866937
Short name T178
Test name
Test status
Simulation time 137474127 ps
CPU time 0.9 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 200188 kb
Host smart-cb66b87c-cb4f-4cf2-ad1b-832c2d1cf6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758866937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3758866937
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4255661479
Short name T575
Test name
Test status
Simulation time 48879332 ps
CPU time 0.7 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 198120 kb
Host smart-eaa573d9-02d3-4bd2-bb4e-057d67b8c182
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255661479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.4255661479
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.879661929
Short name T459
Test name
Test status
Simulation time 36566150 ps
CPU time 0.6 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 197304 kb
Host smart-7822becb-40c5-4fd6-83de-9806df3544f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879661929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_
malfunc.879661929
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2900160185
Short name T493
Test name
Test status
Simulation time 516474254 ps
CPU time 0.94 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198092 kb
Host smart-645a3e83-bd95-4f08-8f83-77dd56f12767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900160185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2900160185
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2876961111
Short name T463
Test name
Test status
Simulation time 42863189 ps
CPU time 0.66 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 198056 kb
Host smart-8e271e2c-a7c6-4d28-b074-1ca2e558e4b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876961111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2876961111
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1296451642
Short name T385
Test name
Test status
Simulation time 38457617 ps
CPU time 0.67 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198428 kb
Host smart-573c3b25-aa11-434f-bd78-d2120b303325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296451642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1296451642
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2458060987
Short name T491
Test name
Test status
Simulation time 100727792 ps
CPU time 0.68 seconds
Started Aug 04 05:16:34 PM PDT 24
Finished Aug 04 05:16:35 PM PDT 24
Peak memory 199048 kb
Host smart-540c2fc9-598e-4d20-90d2-e70c21e78b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458060987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2458060987
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.4225332315
Short name T228
Test name
Test status
Simulation time 149928376 ps
CPU time 0.83 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 209564 kb
Host smart-c8816618-00d2-4f49-a8c2-70c16901f6a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225332315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.4225332315
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2472261949
Short name T462
Test name
Test status
Simulation time 60778282 ps
CPU time 0.74 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 198188 kb
Host smart-c33ab66d-9159-49f7-90ad-0ea11c4450b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472261949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2472261949
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3252386250
Short name T422
Test name
Test status
Simulation time 63079168 ps
CPU time 0.64 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 198544 kb
Host smart-9ae40b9e-5b20-489d-b4d9-8e3bb3ac7034
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252386250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3252386250
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.3954927972
Short name T610
Test name
Test status
Simulation time 47519228 ps
CPU time 0.89 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 200436 kb
Host smart-83b8be55-8c5e-43b5-953b-9a9926955dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954927972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.3954927972
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4132594616
Short name T557
Test name
Test status
Simulation time 59962578 ps
CPU time 0.7 seconds
Started Aug 04 05:15:34 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 199032 kb
Host smart-fa8674be-4a65-4a7f-93f0-72176641d819
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132594616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.4132594616
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3504981159
Short name T125
Test name
Test status
Simulation time 43576708 ps
CPU time 0.59 seconds
Started Aug 04 05:15:34 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 197268 kb
Host smart-e278f725-c7ee-452d-aeae-1cf71388910e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504981159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3504981159
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.673779166
Short name T484
Test name
Test status
Simulation time 317844044 ps
CPU time 0.94 seconds
Started Aug 04 05:15:36 PM PDT 24
Finished Aug 04 05:15:37 PM PDT 24
Peak memory 198052 kb
Host smart-60893468-ca16-4f88-8bd1-99fd4846948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673779166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.673779166
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3207717637
Short name T416
Test name
Test status
Simulation time 49518711 ps
CPU time 0.62 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 197408 kb
Host smart-d9605858-0cf3-4d84-bf6e-b827233925a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207717637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3207717637
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.3002143269
Short name T8
Test name
Test status
Simulation time 202183748 ps
CPU time 0.59 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 198076 kb
Host smart-eaa5c8e9-3459-4ecf-92c9-5b4e4ce23a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002143269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3002143269
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.3240309484
Short name T193
Test name
Test status
Simulation time 72621747 ps
CPU time 0.68 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 201108 kb
Host smart-626d8067-9a6c-4a6d-a567-59c2df0df361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240309484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.3240309484
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2203412888
Short name T248
Test name
Test status
Simulation time 70065907 ps
CPU time 0.76 seconds
Started Aug 04 05:15:33 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 199016 kb
Host smart-57ac3153-8f82-4a8d-976c-8e589552b913
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203412888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2203412888
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3264195908
Short name T312
Test name
Test status
Simulation time 98423117 ps
CPU time 1.07 seconds
Started Aug 04 05:15:37 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 209484 kb
Host smart-8a24d0bf-db6f-4a2d-a624-ec47a8a73b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264195908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3264195908
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.3301497468
Short name T23
Test name
Test status
Simulation time 451378768 ps
CPU time 1.09 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 217208 kb
Host smart-1191a050-cefc-4519-889f-e5f9099f1419
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301497468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3301497468
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1317004439
Short name T423
Test name
Test status
Simulation time 57833833 ps
CPU time 0.88 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 197872 kb
Host smart-0c347b1f-2590-4528-bc09-d2afbecc1b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317004439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1317004439
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.941244661
Short name T562
Test name
Test status
Simulation time 33916570 ps
CPU time 0.69 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 198280 kb
Host smart-1bc6ec7b-1cd5-4ec9-a0c1-45d150528f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941244661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.941244661
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1891817638
Short name T518
Test name
Test status
Simulation time 85928549 ps
CPU time 0.75 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 198920 kb
Host smart-5e63b83c-7f09-48f5-97f4-34c7d768f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891817638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1891817638
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.359876064
Short name T158
Test name
Test status
Simulation time 64717344 ps
CPU time 0.81 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198408 kb
Host smart-172d30a6-13ac-48c9-b58b-a0a28f5798da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359876064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.359876064
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2718537908
Short name T317
Test name
Test status
Simulation time 31207923 ps
CPU time 0.6 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 197192 kb
Host smart-96592cca-115e-4eeb-ab76-83ba077f5eb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718537908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2718537908
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.1912473467
Short name T545
Test name
Test status
Simulation time 628602473 ps
CPU time 0.94 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198136 kb
Host smart-6716c876-51ba-44f5-9077-5a443d13ffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912473467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1912473467
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2200490842
Short name T447
Test name
Test status
Simulation time 50474031 ps
CPU time 0.67 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198052 kb
Host smart-0b39ed8b-9806-469d-b9bf-81fb7ea51565
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200490842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2200490842
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.4055223526
Short name T307
Test name
Test status
Simulation time 30772628 ps
CPU time 0.6 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198140 kb
Host smart-58e62419-a2ef-4529-ba19-50ab76e5048a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055223526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.4055223526
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1800120926
Short name T175
Test name
Test status
Simulation time 51962161 ps
CPU time 0.68 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 201188 kb
Host smart-be88b0bc-fad8-4649-9564-0c2ea26adc8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800120926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1800120926
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1496559450
Short name T405
Test name
Test status
Simulation time 24885212 ps
CPU time 0.69 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 199168 kb
Host smart-4ddfe577-4bbf-433b-ab18-e5bf07c5631b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496559450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1496559450
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3738175050
Short name T267
Test name
Test status
Simulation time 104996830 ps
CPU time 0.84 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 209432 kb
Host smart-bf59cd17-8c72-4b12-b937-e6a73caffdfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738175050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3738175050
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.4270908321
Short name T114
Test name
Test status
Simulation time 85308408 ps
CPU time 0.74 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198044 kb
Host smart-275c13e9-9480-4b70-b748-8fab37bc1731
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270908321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4270908321
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.204535601
Short name T52
Test name
Test status
Simulation time 50628604 ps
CPU time 0.63 seconds
Started Aug 04 05:16:19 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 198548 kb
Host smart-5cdb22ce-4801-423c-8665-5d8fec5ee643
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204535601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.204535601
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.2249390836
Short name T88
Test name
Test status
Simulation time 50319355 ps
CPU time 0.88 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 200380 kb
Host smart-1784be43-bcbe-4e1e-af11-42f82bfe68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249390836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2249390836
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2983581
Short name T420
Test name
Test status
Simulation time 58287733 ps
CPU time 0.74 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 199388 kb
Host smart-f80850c6-dca3-41a2-a152-fc462a408533
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_inte
grity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disabl
e_rom_integrity_check.2983581
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2292577450
Short name T409
Test name
Test status
Simulation time 31078815 ps
CPU time 0.64 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 197264 kb
Host smart-7dfd40e5-417f-4c13-bc7e-803499e76403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292577450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2292577450
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.4122000775
Short name T377
Test name
Test status
Simulation time 344051447 ps
CPU time 0.92 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 198088 kb
Host smart-844454f5-bbc4-4d7a-ad4e-49d884ffe319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122000775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.4122000775
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.3000826557
Short name T578
Test name
Test status
Simulation time 39644431 ps
CPU time 0.63 seconds
Started Aug 04 05:16:18 PM PDT 24
Finished Aug 04 05:16:19 PM PDT 24
Peak memory 197356 kb
Host smart-362ac32d-b5cb-4d01-a140-d98798d693f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000826557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3000826557
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.715483459
Short name T483
Test name
Test status
Simulation time 65984303 ps
CPU time 0.58 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 198412 kb
Host smart-e0fde028-51a3-43d8-9042-3f0db7834a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715483459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.715483459
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1164147962
Short name T577
Test name
Test status
Simulation time 41977388 ps
CPU time 0.79 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 201364 kb
Host smart-16634b01-ae4e-4b42-af4f-b72cb461fbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164147962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1164147962
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.765651758
Short name T355
Test name
Test status
Simulation time 72141624 ps
CPU time 0.74 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198996 kb
Host smart-a816b751-ac73-456e-9c5b-8876c69ebcc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765651758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.765651758
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1831062325
Short name T305
Test name
Test status
Simulation time 152657570 ps
CPU time 0.86 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 209584 kb
Host smart-523cc655-5549-4a40-b305-31a96e060411
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831062325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1831062325
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2257065127
Short name T449
Test name
Test status
Simulation time 94411144 ps
CPU time 0.9 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 199216 kb
Host smart-59940f68-c293-43c5-8ecb-a9a064ab0bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257065127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2257065127
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1694926197
Short name T542
Test name
Test status
Simulation time 30506604 ps
CPU time 0.71 seconds
Started Aug 04 05:16:26 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 199328 kb
Host smart-2125b60e-78eb-4f59-8796-d0d18944d4c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694926197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1694926197
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.125081506
Short name T502
Test name
Test status
Simulation time 72018257 ps
CPU time 0.69 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198872 kb
Host smart-a85cc044-283f-4710-8465-ba6e087885d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125081506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.125081506
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2756036533
Short name T600
Test name
Test status
Simulation time 83552811 ps
CPU time 0.68 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 199196 kb
Host smart-3bd87da2-c42c-47f4-930f-fd09a31a3b14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756036533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2756036533
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.4212365748
Short name T126
Test name
Test status
Simulation time 29637697 ps
CPU time 0.7 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 197224 kb
Host smart-36253e6c-429c-4acb-a257-10e8e4c08701
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212365748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.4212365748
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.653097261
Short name T353
Test name
Test status
Simulation time 165525476 ps
CPU time 0.99 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 198392 kb
Host smart-18fe7822-8a48-454a-adfc-ddd70f6a4c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653097261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.653097261
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.684900356
Short name T236
Test name
Test status
Simulation time 46014572 ps
CPU time 0.61 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 198120 kb
Host smart-18c7dacc-00a1-412d-957d-9974a88e3557
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684900356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.684900356
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1532659950
Short name T590
Test name
Test status
Simulation time 37939627 ps
CPU time 0.65 seconds
Started Aug 04 05:16:58 PM PDT 24
Finished Aug 04 05:16:59 PM PDT 24
Peak memory 198312 kb
Host smart-5bd45c8a-26cf-460b-b0d4-99f77abefee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532659950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1532659950
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3651217978
Short name T194
Test name
Test status
Simulation time 43853375 ps
CPU time 0.72 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 201644 kb
Host smart-6e9f378a-78a8-49f0-935a-790553f2daa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651217978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3651217978
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1217120738
Short name T43
Test name
Test status
Simulation time 69803946 ps
CPU time 0.73 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 198312 kb
Host smart-c6cdf4e9-8a86-4b39-9639-8c4505c52713
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217120738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1217120738
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.378084910
Short name T41
Test name
Test status
Simulation time 108793026 ps
CPU time 0.89 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 209456 kb
Host smart-18130efc-58e6-4d01-8445-91df13ee20a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378084910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.378084910
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1190469095
Short name T370
Test name
Test status
Simulation time 54485367 ps
CPU time 0.77 seconds
Started Aug 04 05:16:26 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 198316 kb
Host smart-fa883ca3-d2cf-460e-b423-ec546bfce0e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190469095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1190469095
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3019217365
Short name T589
Test name
Test status
Simulation time 44425400 ps
CPU time 0.64 seconds
Started Aug 04 05:16:26 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 198536 kb
Host smart-e4da4186-8f76-4a62-9c26-1f1d17899b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019217365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3019217365
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.1488138112
Short name T89
Test name
Test status
Simulation time 80790981 ps
CPU time 0.89 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 200140 kb
Host smart-59e51940-3c15-49d4-9b49-a4202b8a6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488138112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1488138112
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2815028074
Short name T428
Test name
Test status
Simulation time 75248628 ps
CPU time 0.66 seconds
Started Aug 04 05:16:33 PM PDT 24
Finished Aug 04 05:16:34 PM PDT 24
Peak memory 198200 kb
Host smart-df262548-01a0-4c2e-90ce-06e00a1a185e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815028074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2815028074
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2974952502
Short name T316
Test name
Test status
Simulation time 29639585 ps
CPU time 0.63 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 197904 kb
Host smart-6344fd0b-8d63-448c-a014-05e63ab8c59d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974952502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2974952502
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1387302178
Short name T549
Test name
Test status
Simulation time 298272623 ps
CPU time 0.94 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198116 kb
Host smart-6434b1e4-c89c-4a00-a76a-5582be63d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387302178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1387302178
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1076731637
Short name T539
Test name
Test status
Simulation time 41405626 ps
CPU time 0.65 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198120 kb
Host smart-a12775d0-bab0-4e5f-8eb2-dcf2168f60b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076731637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1076731637
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.407883689
Short name T537
Test name
Test status
Simulation time 122405850 ps
CPU time 0.59 seconds
Started Aug 04 05:16:30 PM PDT 24
Finished Aug 04 05:16:31 PM PDT 24
Peak memory 198080 kb
Host smart-0e33ccdd-07c5-41bb-be32-907ba2dc2bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407883689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.407883689
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.972682727
Short name T163
Test name
Test status
Simulation time 163231802 ps
CPU time 0.7 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:28 PM PDT 24
Peak memory 201644 kb
Host smart-a815d283-af02-4901-8a24-5595c7e6d2bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972682727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invali
d.972682727
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.2367302623
Short name T296
Test name
Test status
Simulation time 107207404 ps
CPU time 0.73 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 199100 kb
Host smart-976f246a-7415-4a25-829d-e18f680e9c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367302623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2367302623
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2138755824
Short name T245
Test name
Test status
Simulation time 150221452 ps
CPU time 0.86 seconds
Started Aug 04 05:16:19 PM PDT 24
Finished Aug 04 05:16:20 PM PDT 24
Peak memory 199052 kb
Host smart-09e54494-6eab-4741-9770-98e699614e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138755824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2138755824
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1559589344
Short name T13
Test name
Test status
Simulation time 64615242 ps
CPU time 0.63 seconds
Started Aug 04 05:16:21 PM PDT 24
Finished Aug 04 05:16:22 PM PDT 24
Peak memory 198520 kb
Host smart-d5db5c68-2cd0-468d-8ca0-3d656bf14d4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559589344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1559589344
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.805683909
Short name T568
Test name
Test status
Simulation time 43855581 ps
CPU time 0.65 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 199208 kb
Host smart-da6533d8-84ef-47a4-9db3-70bf3532b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805683909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.805683909
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.3610044721
Short name T156
Test name
Test status
Simulation time 58050705 ps
CPU time 0.82 seconds
Started Aug 04 05:16:35 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 199132 kb
Host smart-195074cd-427e-4f2b-9d05-dfa7aeabd3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610044721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.3610044721
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2094920210
Short name T130
Test name
Test status
Simulation time 28417624 ps
CPU time 0.64 seconds
Started Aug 04 05:16:24 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 198048 kb
Host smart-8a98aaa2-0aa4-484f-b756-8c6750d197b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094920210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.2094920210
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3500611990
Short name T625
Test name
Test status
Simulation time 162566903 ps
CPU time 0.96 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 197992 kb
Host smart-8f86f549-fcdc-4273-b02c-fe6743d6b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500611990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3500611990
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.2876845247
Short name T354
Test name
Test status
Simulation time 22905616 ps
CPU time 0.65 seconds
Started Aug 04 05:16:34 PM PDT 24
Finished Aug 04 05:16:35 PM PDT 24
Peak memory 197316 kb
Host smart-035c625c-9b57-4c7a-8b83-70bc5160687c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876845247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.2876845247
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2664900124
Short name T346
Test name
Test status
Simulation time 46747666 ps
CPU time 0.73 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198028 kb
Host smart-81c8f7bc-6bce-4237-a11a-fbb2f09d8522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664900124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2664900124
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1705381608
Short name T202
Test name
Test status
Simulation time 81430081 ps
CPU time 0.64 seconds
Started Aug 04 05:16:35 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 201284 kb
Host smart-5ab76e86-e852-4496-a596-b1923a36ea69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705381608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1705381608
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2037014979
Short name T218
Test name
Test status
Simulation time 53939148 ps
CPU time 0.84 seconds
Started Aug 04 05:16:25 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 199080 kb
Host smart-3bc53131-e813-47b5-9ad7-5c983d342f4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037014979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2037014979
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3717548089
Short name T242
Test name
Test status
Simulation time 172799695 ps
CPU time 0.76 seconds
Started Aug 04 05:16:27 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 209440 kb
Host smart-c2c1ebdf-78b2-4d93-aafd-d72a5aa43e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717548089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3717548089
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3815435981
Short name T543
Test name
Test status
Simulation time 72376114 ps
CPU time 0.74 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 197980 kb
Host smart-df483970-d8d9-4f02-a965-5e0d6d2770ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815435981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3815435981
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.1956021687
Short name T448
Test name
Test status
Simulation time 55244265 ps
CPU time 0.62 seconds
Started Aug 04 05:16:20 PM PDT 24
Finished Aug 04 05:16:21 PM PDT 24
Peak memory 199396 kb
Host smart-694891c6-65b0-4e42-a3bc-bf0be29e055e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956021687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.1956021687
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3233291144
Short name T364
Test name
Test status
Simulation time 45170452 ps
CPU time 0.6 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 198440 kb
Host smart-04fcc271-5e59-42d4-9cf6-56b4b955345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233291144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3233291144
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2172190888
Short name T134
Test name
Test status
Simulation time 55627270 ps
CPU time 0.74 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198600 kb
Host smart-5ae04c30-7304-4c5b-baf4-a3022e19334e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172190888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2172190888
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3706465182
Short name T286
Test name
Test status
Simulation time 38751596 ps
CPU time 0.62 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:33 PM PDT 24
Peak memory 197352 kb
Host smart-b2d66bc3-e066-4c82-9299-62273193e734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706465182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3706465182
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2963572789
Short name T455
Test name
Test status
Simulation time 161040825 ps
CPU time 0.98 seconds
Started Aug 04 05:16:47 PM PDT 24
Finished Aug 04 05:16:48 PM PDT 24
Peak memory 198112 kb
Host smart-f1cf7d1f-e780-4375-a45d-47519959ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963572789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2963572789
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.662722388
Short name T544
Test name
Test status
Simulation time 32832611 ps
CPU time 0.63 seconds
Started Aug 04 05:16:30 PM PDT 24
Finished Aug 04 05:16:31 PM PDT 24
Peak memory 198012 kb
Host smart-0ccfa8d9-6874-4f80-b4e3-20f5fceefc02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662722388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.662722388
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.981821996
Short name T520
Test name
Test status
Simulation time 25017997 ps
CPU time 0.63 seconds
Started Aug 04 05:16:26 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198028 kb
Host smart-28dc2b60-f816-45b6-a5dd-9f48cf4690f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981821996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.981821996
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3583080191
Short name T609
Test name
Test status
Simulation time 82499051 ps
CPU time 0.65 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 201360 kb
Host smart-796462ca-8da2-4e30-b11a-081efadc8f2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583080191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3583080191
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.1485140859
Short name T139
Test name
Test status
Simulation time 48430461 ps
CPU time 0.75 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198372 kb
Host smart-e9da32d9-699e-4e0b-b3a7-9d338e76cc48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485140859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.1485140859
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1941115903
Short name T46
Test name
Test status
Simulation time 41195988 ps
CPU time 0.71 seconds
Started Aug 04 05:16:22 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 199048 kb
Host smart-d708445e-fac8-42d2-973f-da9bc27dfd77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941115903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1941115903
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.86631369
Short name T327
Test name
Test status
Simulation time 161313058 ps
CPU time 0.84 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 209436 kb
Host smart-aca18ee0-04a0-49b9-a71d-de62d5eb063b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86631369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.86631369
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3403313131
Short name T342
Test name
Test status
Simulation time 65435992 ps
CPU time 0.72 seconds
Started Aug 04 05:16:30 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 199172 kb
Host smart-436cef45-afcd-4b4b-a5e3-25d492c43fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403313131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3403313131
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2507043060
Short name T436
Test name
Test status
Simulation time 56788106 ps
CPU time 0.63 seconds
Started Aug 04 05:16:26 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 198380 kb
Host smart-56d4f4b9-085a-48b6-8ef9-ec6c20632809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507043060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2507043060
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1343373576
Short name T585
Test name
Test status
Simulation time 99457746 ps
CPU time 0.81 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 200072 kb
Host smart-97b8ff1b-b1e7-48af-8cee-5f9e5406fe85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343373576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1343373576
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3817508504
Short name T180
Test name
Test status
Simulation time 38063963 ps
CPU time 0.66 seconds
Started Aug 04 05:16:50 PM PDT 24
Finished Aug 04 05:16:50 PM PDT 24
Peak memory 198636 kb
Host smart-c0def9cf-da65-4e2f-bce4-755d526c11d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817508504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3817508504
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.4198020243
Short name T277
Test name
Test status
Simulation time 29535219 ps
CPU time 0.62 seconds
Started Aug 04 05:16:30 PM PDT 24
Finished Aug 04 05:16:31 PM PDT 24
Peak memory 197956 kb
Host smart-6997e3b0-8f81-4bbe-9c91-486c89fb8037
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198020243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.4198020243
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3885904572
Short name T250
Test name
Test status
Simulation time 278413273 ps
CPU time 0.94 seconds
Started Aug 04 05:16:30 PM PDT 24
Finished Aug 04 05:16:31 PM PDT 24
Peak memory 198000 kb
Host smart-ef8248fd-c4da-44bd-afe8-66171e6a39d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885904572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3885904572
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.476177660
Short name T19
Test name
Test status
Simulation time 67164704 ps
CPU time 0.63 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198068 kb
Host smart-16000085-a860-42df-8f07-7a39be94343f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476177660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.476177660
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.2679886581
Short name T276
Test name
Test status
Simulation time 56388515 ps
CPU time 0.58 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198108 kb
Host smart-c887daa7-a3f4-4117-bdb5-80e6ad8257b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679886581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2679886581
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.1050290620
Short name T187
Test name
Test status
Simulation time 48282399 ps
CPU time 0.72 seconds
Started Aug 04 05:16:38 PM PDT 24
Finished Aug 04 05:16:39 PM PDT 24
Peak memory 201348 kb
Host smart-c994c35c-2456-489c-a45a-5b41f527ec55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050290620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.1050290620
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.4103600703
Short name T226
Test name
Test status
Simulation time 129025853 ps
CPU time 0.75 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 199104 kb
Host smart-3b6db92f-86d2-46ad-ab2b-894a564f6afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103600703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.4103600703
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1273582320
Short name T379
Test name
Test status
Simulation time 105624197 ps
CPU time 1.04 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:31 PM PDT 24
Peak memory 209412 kb
Host smart-703f0c00-7c92-49d9-a840-dcf11b0e17ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273582320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1273582320
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3043605596
Short name T387
Test name
Test status
Simulation time 133667686 ps
CPU time 0.78 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 199036 kb
Host smart-14fb6b36-6000-4579-9529-20115f5599d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043605596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3043605596
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3587163835
Short name T392
Test name
Test status
Simulation time 40019565 ps
CPU time 0.65 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 199312 kb
Host smart-0aa55860-2bdf-4457-918d-b10c73bf47ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587163835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3587163835
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2702428877
Short name T599
Test name
Test status
Simulation time 21462865 ps
CPU time 0.69 seconds
Started Aug 04 05:16:36 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 198560 kb
Host smart-32637e26-0955-4395-b8fe-b1561bb97b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702428877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2702428877
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2678455154
Short name T282
Test name
Test status
Simulation time 30268973 ps
CPU time 0.63 seconds
Started Aug 04 05:16:48 PM PDT 24
Finished Aug 04 05:16:49 PM PDT 24
Peak memory 197956 kb
Host smart-d5174ad4-c99e-4c49-a3ae-6bd36aef1bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678455154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2678455154
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3556644365
Short name T394
Test name
Test status
Simulation time 160091518 ps
CPU time 1 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 197996 kb
Host smart-7b3bbb2a-05fc-4b3a-9bef-95b2a069157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556644365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3556644365
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.2937768918
Short name T278
Test name
Test status
Simulation time 103213697 ps
CPU time 0.61 seconds
Started Aug 04 05:16:42 PM PDT 24
Finished Aug 04 05:16:42 PM PDT 24
Peak memory 198000 kb
Host smart-38bde943-bba4-441e-b785-94a8b3278f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937768918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2937768918
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3135513917
Short name T621
Test name
Test status
Simulation time 34607247 ps
CPU time 0.61 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 198148 kb
Host smart-df20285f-9ed7-4170-965d-3d455ad91923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135513917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3135513917
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3942930744
Short name T204
Test name
Test status
Simulation time 43194148 ps
CPU time 0.72 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:33 PM PDT 24
Peak memory 201344 kb
Host smart-25158a53-26b2-454d-a56f-d435a481c577
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942930744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3942930744
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1229476046
Short name T494
Test name
Test status
Simulation time 69337416 ps
CPU time 0.66 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 199092 kb
Host smart-bb8f7341-ae83-42e5-9782-a71f2fef7c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229476046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1229476046
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2912210333
Short name T393
Test name
Test status
Simulation time 447586406 ps
CPU time 0.78 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:33 PM PDT 24
Peak memory 209408 kb
Host smart-681bc52e-73c4-46c9-ba65-ef2643a316cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912210333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2912210333
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3356403228
Short name T429
Test name
Test status
Simulation time 175202277 ps
CPU time 0.71 seconds
Started Aug 04 05:16:37 PM PDT 24
Finished Aug 04 05:16:38 PM PDT 24
Peak memory 197908 kb
Host smart-778af6d7-4fd3-49e4-a60f-e7ed4fcf9ce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356403228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3356403228
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.3507448456
Short name T243
Test name
Test status
Simulation time 41151624 ps
CPU time 0.64 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 198544 kb
Host smart-6b44c53e-ea6f-44f6-8aef-7c3314705278
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507448456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3507448456
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3196901379
Short name T528
Test name
Test status
Simulation time 93785251 ps
CPU time 0.89 seconds
Started Aug 04 05:16:29 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 200212 kb
Host smart-0997ae5d-51ac-4124-ba2c-630a45f66d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196901379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3196901379
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.4166628087
Short name T559
Test name
Test status
Simulation time 29447559 ps
CPU time 0.64 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198008 kb
Host smart-70e79c1f-af4c-4eba-8b79-adb653ab8b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166628087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.4166628087
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1938008690
Short name T472
Test name
Test status
Simulation time 687230422 ps
CPU time 0.98 seconds
Started Aug 04 05:16:52 PM PDT 24
Finished Aug 04 05:16:53 PM PDT 24
Peak memory 198024 kb
Host smart-72bc4440-5475-4f4e-819f-594867d1583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938008690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1938008690
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2836767990
Short name T272
Test name
Test status
Simulation time 86895050 ps
CPU time 0.64 seconds
Started Aug 04 05:16:50 PM PDT 24
Finished Aug 04 05:16:51 PM PDT 24
Peak memory 197940 kb
Host smart-01cb62c7-53cf-44e9-8c9e-e76e13057675
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836767990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2836767990
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.2642967075
Short name T478
Test name
Test status
Simulation time 44772593 ps
CPU time 0.68 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198092 kb
Host smart-d0b7c496-7c8b-489a-ab2f-c44edaff77f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642967075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2642967075
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2433505452
Short name T522
Test name
Test status
Simulation time 69506721 ps
CPU time 0.91 seconds
Started Aug 04 05:16:32 PM PDT 24
Finished Aug 04 05:16:33 PM PDT 24
Peak memory 199092 kb
Host smart-442a48a1-53cc-4b93-987a-57c529a2acb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433505452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2433505452
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3167003606
Short name T230
Test name
Test status
Simulation time 123062434 ps
CPU time 0.94 seconds
Started Aug 04 05:16:33 PM PDT 24
Finished Aug 04 05:16:34 PM PDT 24
Peak memory 209580 kb
Host smart-fb741274-f5f2-41bf-96ce-cfaf3766a096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167003606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3167003606
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1795494485
Short name T464
Test name
Test status
Simulation time 59030247 ps
CPU time 0.72 seconds
Started Aug 04 05:16:28 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 198156 kb
Host smart-76320a7b-f787-41d6-b503-9160590e2ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795494485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1795494485
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2143888008
Short name T115
Test name
Test status
Simulation time 53278722 ps
CPU time 0.62 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198440 kb
Host smart-3e7cf0b1-3c37-46c7-b05b-d96d42b80c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143888008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2143888008
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3540083081
Short name T513
Test name
Test status
Simulation time 207309482 ps
CPU time 0.8 seconds
Started Aug 04 05:16:34 PM PDT 24
Finished Aug 04 05:16:35 PM PDT 24
Peak memory 199936 kb
Host smart-39242638-b704-451f-93bf-39a423217649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540083081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3540083081
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.4171917295
Short name T138
Test name
Test status
Simulation time 68109492 ps
CPU time 0.66 seconds
Started Aug 04 05:16:37 PM PDT 24
Finished Aug 04 05:16:37 PM PDT 24
Peak memory 198272 kb
Host smart-1f38430e-fb02-43fd-a237-db2eb9f9de95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171917295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.4171917295
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2176040973
Short name T496
Test name
Test status
Simulation time 32381556 ps
CPU time 0.57 seconds
Started Aug 04 05:16:42 PM PDT 24
Finished Aug 04 05:16:43 PM PDT 24
Peak memory 197980 kb
Host smart-251ccf56-7c27-4fb6-bf1e-659bb6097029
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176040973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2176040973
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.2422073104
Short name T412
Test name
Test status
Simulation time 159680218 ps
CPU time 0.98 seconds
Started Aug 04 05:16:50 PM PDT 24
Finished Aug 04 05:16:51 PM PDT 24
Peak memory 198160 kb
Host smart-b66f4756-c4d0-4988-a90e-543c1bedad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422073104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2422073104
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2809676637
Short name T406
Test name
Test status
Simulation time 75265814 ps
CPU time 0.61 seconds
Started Aug 04 05:16:45 PM PDT 24
Finished Aug 04 05:16:45 PM PDT 24
Peak memory 197336 kb
Host smart-3cd186d3-cda8-4d5c-84a4-e68cc44650b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809676637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2809676637
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1291649853
Short name T350
Test name
Test status
Simulation time 50988877 ps
CPU time 0.62 seconds
Started Aug 04 05:16:42 PM PDT 24
Finished Aug 04 05:16:43 PM PDT 24
Peak memory 198048 kb
Host smart-60e5c9d7-865c-4dc1-9c4d-856d48792114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291649853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1291649853
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1814508452
Short name T597
Test name
Test status
Simulation time 38030965 ps
CPU time 0.71 seconds
Started Aug 04 05:16:57 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 201636 kb
Host smart-ef71b1bd-31bb-432b-b9d7-bb804ef9be68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814508452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1814508452
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2691247770
Short name T294
Test name
Test status
Simulation time 63337998 ps
CPU time 0.69 seconds
Started Aug 04 05:16:31 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 199328 kb
Host smart-47c02f87-7ee6-4d44-b9ab-521749b7cfd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691247770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2691247770
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.812163747
Short name T333
Test name
Test status
Simulation time 130323218 ps
CPU time 0.84 seconds
Started Aug 04 05:16:56 PM PDT 24
Finished Aug 04 05:16:57 PM PDT 24
Peak memory 201244 kb
Host smart-4a726f85-acda-428d-bf7f-b210e22e5da4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812163747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.812163747
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3837978157
Short name T244
Test name
Test status
Simulation time 50568563 ps
CPU time 0.84 seconds
Started Aug 04 05:16:35 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 199368 kb
Host smart-2ecc914b-4ca3-4277-b23d-96ff7b234f08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837978157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3837978157
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2520844086
Short name T308
Test name
Test status
Simulation time 70370911 ps
CPU time 0.64 seconds
Started Aug 04 05:16:37 PM PDT 24
Finished Aug 04 05:16:38 PM PDT 24
Peak memory 198452 kb
Host smart-ca6c6c4a-4fc4-450f-9ab6-7b9109982c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520844086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2520844086
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.4027171704
Short name T580
Test name
Test status
Simulation time 73723432 ps
CPU time 0.77 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 198868 kb
Host smart-05904b46-d973-425c-9159-f6536e627be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027171704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4027171704
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.695267768
Short name T324
Test name
Test status
Simulation time 31032282 ps
CPU time 0.62 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 197260 kb
Host smart-5044a079-6015-48e2-bf82-13e23b1c45fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695267768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_m
alfunc.695267768
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2982251913
Short name T256
Test name
Test status
Simulation time 564224801 ps
CPU time 0.9 seconds
Started Aug 04 05:15:38 PM PDT 24
Finished Aug 04 05:15:39 PM PDT 24
Peak memory 198004 kb
Host smart-140cbd45-ff20-45eb-9ca2-91275f6f699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982251913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2982251913
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.945393455
Short name T306
Test name
Test status
Simulation time 31027821 ps
CPU time 0.65 seconds
Started Aug 04 05:15:38 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 197976 kb
Host smart-d08183ce-e0da-4e78-9776-384c67023192
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945393455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.945393455
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.257305085
Short name T508
Test name
Test status
Simulation time 289135270 ps
CPU time 0.65 seconds
Started Aug 04 05:15:37 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 198112 kb
Host smart-7b2f5509-dc84-4318-bed6-5e8031aa0609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257305085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.257305085
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.4279485806
Short name T195
Test name
Test status
Simulation time 46064992 ps
CPU time 0.73 seconds
Started Aug 04 05:15:39 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 201160 kb
Host smart-bb8a2af2-045e-410a-9164-69c60fa2710e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279485806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.4279485806
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.3140815190
Short name T220
Test name
Test status
Simulation time 80781750 ps
CPU time 0.79 seconds
Started Aug 04 05:15:36 PM PDT 24
Finished Aug 04 05:15:37 PM PDT 24
Peak memory 198624 kb
Host smart-cb67f139-4dd0-42c2-ba8d-30316f32b4f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140815190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3140815190
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1490484904
Short name T482
Test name
Test status
Simulation time 115656907 ps
CPU time 0.91 seconds
Started Aug 04 05:15:37 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 209516 kb
Host smart-48ed3c75-30f9-4caf-8551-118be4788997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490484904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1490484904
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.4132337309
Short name T21
Test name
Test status
Simulation time 473108920 ps
CPU time 1.1 seconds
Started Aug 04 05:15:38 PM PDT 24
Finished Aug 04 05:15:39 PM PDT 24
Peak memory 216812 kb
Host smart-84cf9bb7-faf7-4dc7-abd7-82e31433ca30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132337309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4132337309
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1468211783
Short name T499
Test name
Test status
Simulation time 53283985 ps
CPU time 0.81 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 198104 kb
Host smart-634fe8d0-2e54-4af9-93b1-9b3ccafbd30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468211783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1468211783
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.300349614
Short name T521
Test name
Test status
Simulation time 58238939 ps
CPU time 0.64 seconds
Started Aug 04 05:15:35 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 198540 kb
Host smart-df346e84-c95a-4bf4-8ba5-0e3cf420c054
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300349614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.300349614
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.399313130
Short name T594
Test name
Test status
Simulation time 60841995 ps
CPU time 0.86 seconds
Started Aug 04 05:16:37 PM PDT 24
Finished Aug 04 05:16:38 PM PDT 24
Peak memory 200100 kb
Host smart-a597bcaa-ec88-4aee-88cd-28c2b3f6d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399313130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.399313130
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.4188644761
Short name T591
Test name
Test status
Simulation time 59503570 ps
CPU time 0.79 seconds
Started Aug 04 05:16:55 PM PDT 24
Finished Aug 04 05:16:56 PM PDT 24
Peak memory 198400 kb
Host smart-9b547ee4-7e37-4d04-82b7-3f8f25272800
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188644761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.4188644761
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.729525341
Short name T581
Test name
Test status
Simulation time 37012413 ps
CPU time 0.61 seconds
Started Aug 04 05:16:45 PM PDT 24
Finished Aug 04 05:16:46 PM PDT 24
Peak memory 198000 kb
Host smart-fa27b4d6-96c1-4d8c-9dcc-ac49b6b61093
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729525341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_
malfunc.729525341
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.4054108988
Short name T368
Test name
Test status
Simulation time 627677535 ps
CPU time 0.95 seconds
Started Aug 04 05:16:54 PM PDT 24
Finished Aug 04 05:16:55 PM PDT 24
Peak memory 198084 kb
Host smart-be86ed0d-1c61-4736-aa2e-ba96717e3d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054108988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.4054108988
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.4003204714
Short name T481
Test name
Test status
Simulation time 48036342 ps
CPU time 0.68 seconds
Started Aug 04 05:16:58 PM PDT 24
Finished Aug 04 05:16:59 PM PDT 24
Peak memory 197956 kb
Host smart-0f133e28-f543-4505-a1c3-f43acffc96fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003204714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.4003204714
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.462604922
Short name T434
Test name
Test status
Simulation time 65820280 ps
CPU time 0.59 seconds
Started Aug 04 05:17:03 PM PDT 24
Finished Aug 04 05:17:04 PM PDT 24
Peak memory 198024 kb
Host smart-f5ea648a-a412-4bfd-9926-256717f564f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462604922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.462604922
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.232050564
Short name T185
Test name
Test status
Simulation time 49124854 ps
CPU time 0.68 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 201372 kb
Host smart-b9cfd1fa-cb74-4adf-8c2a-d93433388a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232050564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali
d.232050564
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.1648295788
Short name T574
Test name
Test status
Simulation time 26586594 ps
CPU time 0.66 seconds
Started Aug 04 05:16:58 PM PDT 24
Finished Aug 04 05:16:59 PM PDT 24
Peak memory 198208 kb
Host smart-d63f9b42-3751-4a1a-a1b0-917c741f7a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648295788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.1648295788
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2958865369
Short name T480
Test name
Test status
Simulation time 148419505 ps
CPU time 0.84 seconds
Started Aug 04 05:17:00 PM PDT 24
Finished Aug 04 05:17:01 PM PDT 24
Peak memory 209372 kb
Host smart-33e9ebd4-6004-4ae6-b023-50c3264d86fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958865369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2958865369
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2640096162
Short name T554
Test name
Test status
Simulation time 133133389 ps
CPU time 0.86 seconds
Started Aug 04 05:16:57 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 199280 kb
Host smart-8b4ecbb7-9246-468b-a46d-2f8d67ebcc9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640096162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2640096162
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3759505669
Short name T442
Test name
Test status
Simulation time 44680651 ps
CPU time 0.63 seconds
Started Aug 04 05:16:53 PM PDT 24
Finished Aug 04 05:16:54 PM PDT 24
Peak memory 198140 kb
Host smart-b5721f0b-042a-483f-b44c-26d2e8a12739
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759505669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3759505669
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2245569764
Short name T450
Test name
Test status
Simulation time 71236168 ps
CPU time 0.99 seconds
Started Aug 04 05:17:00 PM PDT 24
Finished Aug 04 05:17:02 PM PDT 24
Peak memory 200068 kb
Host smart-2dd7552e-cedc-4a1b-99bb-1d4b878f0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245569764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2245569764
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.4289606126
Short name T536
Test name
Test status
Simulation time 48945625 ps
CPU time 0.75 seconds
Started Aug 04 05:16:53 PM PDT 24
Finished Aug 04 05:16:54 PM PDT 24
Peak memory 198584 kb
Host smart-21cfc18f-4a1c-4f35-8851-0a506c4150ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289606126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.4289606126
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3611621912
Short name T451
Test name
Test status
Simulation time 40184373 ps
CPU time 0.6 seconds
Started Aug 04 05:17:01 PM PDT 24
Finished Aug 04 05:17:02 PM PDT 24
Peak memory 197964 kb
Host smart-063478c7-756b-401e-9bd0-63f220254c72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611621912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.3611621912
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.330020013
Short name T265
Test name
Test status
Simulation time 307758402 ps
CPU time 0.95 seconds
Started Aug 04 05:16:50 PM PDT 24
Finished Aug 04 05:16:52 PM PDT 24
Peak memory 198104 kb
Host smart-5547d4d7-ff30-4912-bf13-055b06f81e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330020013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.330020013
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.2077608953
Short name T6
Test name
Test status
Simulation time 110864011 ps
CPU time 0.6 seconds
Started Aug 04 05:16:51 PM PDT 24
Finished Aug 04 05:16:51 PM PDT 24
Peak memory 197976 kb
Host smart-45deb8bb-2d31-41f9-9766-72a19bdbfb22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077608953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2077608953
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.604727617
Short name T48
Test name
Test status
Simulation time 122263811 ps
CPU time 0.6 seconds
Started Aug 04 05:16:54 PM PDT 24
Finished Aug 04 05:16:55 PM PDT 24
Peak memory 198332 kb
Host smart-d0af5abd-db90-43b8-8c40-1e5267058e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604727617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.604727617
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.755412180
Short name T164
Test name
Test status
Simulation time 88721027 ps
CPU time 0.67 seconds
Started Aug 04 05:17:01 PM PDT 24
Finished Aug 04 05:17:02 PM PDT 24
Peak memory 201316 kb
Host smart-1c935685-9b2a-4554-804b-dd3378419ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755412180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.755412180
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.2056359398
Short name T372
Test name
Test status
Simulation time 36018477 ps
CPU time 0.65 seconds
Started Aug 04 05:16:53 PM PDT 24
Finished Aug 04 05:16:54 PM PDT 24
Peak memory 198268 kb
Host smart-4b52d118-830e-46f3-b04c-0d1362b5f84b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056359398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2056359398
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.969879751
Short name T446
Test name
Test status
Simulation time 99532083 ps
CPU time 0.87 seconds
Started Aug 04 05:17:01 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 209540 kb
Host smart-b74349d6-974a-4f50-bfdc-19da9e6a5fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969879751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.969879751
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1950375813
Short name T443
Test name
Test status
Simulation time 58336577 ps
CPU time 0.79 seconds
Started Aug 04 05:16:58 PM PDT 24
Finished Aug 04 05:16:59 PM PDT 24
Peak memory 197840 kb
Host smart-527fcc69-0655-4e22-b2f3-51d5766567ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950375813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1950375813
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.2849071836
Short name T212
Test name
Test status
Simulation time 104087209 ps
CPU time 0.62 seconds
Started Aug 04 05:16:49 PM PDT 24
Finished Aug 04 05:16:50 PM PDT 24
Peak memory 198212 kb
Host smart-b3ec58fc-30fd-41b8-8cc8-b4a069353ead
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849071836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2849071836
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2340491823
Short name T509
Test name
Test status
Simulation time 58214548 ps
CPU time 0.73 seconds
Started Aug 04 05:16:56 PM PDT 24
Finished Aug 04 05:16:57 PM PDT 24
Peak memory 199108 kb
Host smart-5d9948a5-f893-4bbb-9641-ad2d60725166
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340491823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.2340491823
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1578705772
Short name T476
Test name
Test status
Simulation time 33395780 ps
CPU time 0.73 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 197232 kb
Host smart-8110e376-d853-4163-a81f-31c8822af089
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578705772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1578705772
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.583367616
Short name T283
Test name
Test status
Simulation time 517397803 ps
CPU time 0.94 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:04 PM PDT 24
Peak memory 198144 kb
Host smart-16776e9c-dafd-462b-aaca-cd9bbfebb6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583367616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.583367616
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1040414701
Short name T20
Test name
Test status
Simulation time 46962478 ps
CPU time 0.63 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 197972 kb
Host smart-468ca6d8-fb9d-42e4-960f-98ca375dafda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040414701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1040414701
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2873299473
Short name T569
Test name
Test status
Simulation time 39707289 ps
CPU time 0.65 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 198032 kb
Host smart-6227db9c-2eae-40f4-a854-6061fc371913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873299473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2873299473
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.3541488041
Short name T216
Test name
Test status
Simulation time 117293501 ps
CPU time 0.78 seconds
Started Aug 04 05:16:51 PM PDT 24
Finished Aug 04 05:16:52 PM PDT 24
Peak memory 198344 kb
Host smart-4b82fc86-a473-4bba-926d-2c5b12a06eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541488041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3541488041
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2426206127
Short name T465
Test name
Test status
Simulation time 181586317 ps
CPU time 0.77 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 209416 kb
Host smart-25980760-54f1-488e-b04b-4c00d1111c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426206127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2426206127
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2609269738
Short name T419
Test name
Test status
Simulation time 106461458 ps
CPU time 0.92 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:04 PM PDT 24
Peak memory 199344 kb
Host smart-df183a95-04b2-4818-99ae-7575f17f38d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609269738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2609269738
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3196316152
Short name T592
Test name
Test status
Simulation time 58177528 ps
CPU time 0.62 seconds
Started Aug 04 05:16:52 PM PDT 24
Finished Aug 04 05:16:53 PM PDT 24
Peak memory 199388 kb
Host smart-65e651ed-691d-413e-8da4-99bc1c9f6487
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196316152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3196316152
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.4245616556
Short name T28
Test name
Test status
Simulation time 57151720 ps
CPU time 0.69 seconds
Started Aug 04 05:16:53 PM PDT 24
Finished Aug 04 05:16:54 PM PDT 24
Peak memory 198024 kb
Host smart-e3e5d394-ed36-4c68-9e8a-e53c64b9d423
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245616556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.4245616556
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.993529962
Short name T253
Test name
Test status
Simulation time 147584820 ps
CPU time 0.88 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 200156 kb
Host smart-e62ef810-38e5-4b59-a8c9-2ce8896c8169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993529962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.993529962
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3619361361
Short name T381
Test name
Test status
Simulation time 64586326 ps
CPU time 0.66 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 199192 kb
Host smart-b57f98fd-fb2e-4bf1-8a1d-3f7f31aeaad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619361361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3619361361
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.474567743
Short name T587
Test name
Test status
Simulation time 29362192 ps
CPU time 0.61 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 198000 kb
Host smart-7391d1f7-f680-4e52-87ee-41b8bb4093aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474567743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_
malfunc.474567743
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.141893957
Short name T485
Test name
Test status
Simulation time 456450549 ps
CPU time 0.95 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198336 kb
Host smart-d0916bd9-0127-4e9f-816e-2a0d7238e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141893957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.141893957
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.1268471072
Short name T501
Test name
Test status
Simulation time 105273539 ps
CPU time 0.6 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 197940 kb
Host smart-eb919f33-6f85-42e8-b209-0847698a566e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268471072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1268471072
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.2505417093
Short name T281
Test name
Test status
Simulation time 23949590 ps
CPU time 0.61 seconds
Started Aug 04 05:16:55 PM PDT 24
Finished Aug 04 05:16:56 PM PDT 24
Peak memory 198372 kb
Host smart-0c201a39-cabf-4c42-a62a-ea6411856b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505417093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2505417093
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.70453596
Short name T177
Test name
Test status
Simulation time 42658652 ps
CPU time 0.76 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 201188 kb
Host smart-0d67ff6d-bde5-4b6e-924d-1fbe51d6c477
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70453596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid
.70453596
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2442496582
Short name T323
Test name
Test status
Simulation time 98140944 ps
CPU time 0.73 seconds
Started Aug 04 05:16:57 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 199128 kb
Host smart-b912fa76-86f4-409e-9c88-41a8d1cf85ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442496582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2442496582
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2626875361
Short name T44
Test name
Test status
Simulation time 104558229 ps
CPU time 1.04 seconds
Started Aug 04 05:16:57 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 209468 kb
Host smart-55efe0dd-615b-47ae-bd72-5bba15bc3ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626875361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2626875361
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3824263112
Short name T249
Test name
Test status
Simulation time 50307423 ps
CPU time 0.87 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 199200 kb
Host smart-710bbdd8-0638-4fc9-ad87-0c59af61c610
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824263112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3824263112
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3334422233
Short name T437
Test name
Test status
Simulation time 55732439 ps
CPU time 0.64 seconds
Started Aug 04 05:16:57 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 198476 kb
Host smart-4a73edff-2444-4c6c-b981-b16cc8937349
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334422233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3334422233
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2553199724
Short name T86
Test name
Test status
Simulation time 52527728 ps
CPU time 0.68 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 199200 kb
Host smart-c2702c6f-77f5-407f-8dd2-b2b9fa4c6d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553199724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2553199724
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2612183137
Short name T206
Test name
Test status
Simulation time 62502706 ps
CPU time 0.72 seconds
Started Aug 04 05:17:05 PM PDT 24
Finished Aug 04 05:17:05 PM PDT 24
Peak memory 198516 kb
Host smart-a182c7da-20d6-4edf-b589-1b8c2d26d2e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612183137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2612183137
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3766733153
Short name T395
Test name
Test status
Simulation time 29004009 ps
CPU time 0.62 seconds
Started Aug 04 05:17:00 PM PDT 24
Finished Aug 04 05:17:01 PM PDT 24
Peak memory 198020 kb
Host smart-8639a43a-29ff-460d-81f7-fd2d3ee46b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766733153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3766733153
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.1734503662
Short name T525
Test name
Test status
Simulation time 602919185 ps
CPU time 0.94 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198340 kb
Host smart-634dd98f-b9d8-47de-aa65-c0f933fdd01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734503662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1734503662
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.31427505
Short name T239
Test name
Test status
Simulation time 39341428 ps
CPU time 0.57 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:06 PM PDT 24
Peak memory 197988 kb
Host smart-168badf9-f6ee-40d5-9128-6c9dd495b458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31427505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.31427505
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2933734949
Short name T32
Test name
Test status
Simulation time 140388724 ps
CPU time 0.61 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 198348 kb
Host smart-04d0b826-f8aa-4d7a-b440-0f0cd6ff6c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933734949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2933734949
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3826260303
Short name T376
Test name
Test status
Simulation time 66972310 ps
CPU time 0.8 seconds
Started Aug 04 05:16:58 PM PDT 24
Finished Aug 04 05:16:59 PM PDT 24
Peak memory 199112 kb
Host smart-76a73936-6ab9-4a02-b1d1-f0a38c460b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826260303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3826260303
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.3747694081
Short name T225
Test name
Test status
Simulation time 169032515 ps
CPU time 0.77 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 209500 kb
Host smart-a04a0dc0-7843-4f7d-81eb-04c3d90504a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747694081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3747694081
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2096796018
Short name T627
Test name
Test status
Simulation time 54150687 ps
CPU time 0.82 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 198156 kb
Host smart-e4502eaa-3267-4d9b-a049-58fcef77dfe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096796018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2096796018
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1942342886
Short name T546
Test name
Test status
Simulation time 45468346 ps
CPU time 0.65 seconds
Started Aug 04 05:17:05 PM PDT 24
Finished Aug 04 05:17:06 PM PDT 24
Peak memory 198440 kb
Host smart-fbc5d6a0-6acd-4370-9ab3-e76b95071e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942342886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1942342886
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.416825493
Short name T302
Test name
Test status
Simulation time 33027383 ps
CPU time 0.77 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 198636 kb
Host smart-b62ddca4-6712-4c32-a6f6-f812583fa491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416825493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.416825493
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.3333358169
Short name T137
Test name
Test status
Simulation time 82146815 ps
CPU time 0.65 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:06 PM PDT 24
Peak memory 198492 kb
Host smart-9e00870d-3970-4a5a-afa0-21b7dea5b9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333358169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.3333358169
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.596203318
Short name T620
Test name
Test status
Simulation time 34813227 ps
CPU time 0.61 seconds
Started Aug 04 05:17:05 PM PDT 24
Finished Aug 04 05:17:05 PM PDT 24
Peak memory 197960 kb
Host smart-472dae00-8728-4419-b78f-a7d20f96cf04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596203318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.596203318
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3626410606
Short name T258
Test name
Test status
Simulation time 718103260 ps
CPU time 1 seconds
Started Aug 04 05:16:54 PM PDT 24
Finished Aug 04 05:16:55 PM PDT 24
Peak memory 198108 kb
Host smart-04ed65e9-3ad5-405e-9697-62f902c4d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626410606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3626410606
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1052114637
Short name T33
Test name
Test status
Simulation time 57672977 ps
CPU time 0.68 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 197916 kb
Host smart-d04fa85f-2589-4e82-9fbd-63f387f27bc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052114637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1052114637
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1736565119
Short name T292
Test name
Test status
Simulation time 58450537 ps
CPU time 0.59 seconds
Started Aug 04 05:17:07 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 197740 kb
Host smart-4254f766-96d1-455a-b30d-99c89f22139b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736565119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1736565119
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.923926569
Short name T417
Test name
Test status
Simulation time 42410284 ps
CPU time 0.75 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 199048 kb
Host smart-fb0cdc23-0d8d-42d1-9cc7-9534e87c6849
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923926569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.923926569
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1579070234
Short name T347
Test name
Test status
Simulation time 115606871 ps
CPU time 0.82 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 209580 kb
Host smart-06393b07-b026-4751-98c9-b2992bad3cc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579070234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1579070234
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1803248615
Short name T63
Test name
Test status
Simulation time 79712443 ps
CPU time 0.88 seconds
Started Aug 04 05:17:04 PM PDT 24
Finished Aug 04 05:17:05 PM PDT 24
Peak memory 199064 kb
Host smart-448080d1-135b-4c25-893b-4e596fe7d522
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803248615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1803248615
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.4218162026
Short name T470
Test name
Test status
Simulation time 47595263 ps
CPU time 0.63 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 199368 kb
Host smart-2bdbc5ac-5042-4300-adcc-257025672ebb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218162026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.4218162026
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3417239998
Short name T619
Test name
Test status
Simulation time 89024053 ps
CPU time 0.8 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 200292 kb
Host smart-c7b6ab9b-db50-4af5-a7ca-9cfe63082686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417239998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3417239998
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.3912665414
Short name T7
Test name
Test status
Simulation time 56538983 ps
CPU time 0.7 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 199136 kb
Host smart-220012b7-3dc1-4a5c-bf89-9d502fe79cfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912665414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.3912665414
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1547705611
Short name T622
Test name
Test status
Simulation time 33001242 ps
CPU time 0.6 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 197340 kb
Host smart-9a756aff-656c-4c8c-bbd2-898c460b9f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547705611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.1547705611
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.497329978
Short name T560
Test name
Test status
Simulation time 161202228 ps
CPU time 0.98 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 198344 kb
Host smart-1ecaddfb-99d9-4b2e-be83-b2979f65aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497329978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.497329978
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.2762632641
Short name T371
Test name
Test status
Simulation time 55056120 ps
CPU time 0.67 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 197352 kb
Host smart-7b51773a-c8f2-40de-b373-6b36898ff775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762632641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2762632641
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3266940921
Short name T117
Test name
Test status
Simulation time 87822525 ps
CPU time 0.59 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 198012 kb
Host smart-2726d81b-d896-4748-bb86-6868a7d1d2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266940921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3266940921
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2509984791
Short name T186
Test name
Test status
Simulation time 42134171 ps
CPU time 0.7 seconds
Started Aug 04 05:17:00 PM PDT 24
Finished Aug 04 05:17:01 PM PDT 24
Peak memory 201412 kb
Host smart-d789d34e-7713-44b3-be0c-3592a248b362
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509984791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.2509984791
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.3231275801
Short name T232
Test name
Test status
Simulation time 67169428 ps
CPU time 0.66 seconds
Started Aug 04 05:17:02 PM PDT 24
Finished Aug 04 05:17:03 PM PDT 24
Peak memory 199044 kb
Host smart-1d893068-665e-434a-8e88-775c4b609cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231275801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.3231275801
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.952991487
Short name T475
Test name
Test status
Simulation time 107237297 ps
CPU time 0.98 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 209388 kb
Host smart-529431ee-c29d-4a00-8e97-ebcde872c7e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952991487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.952991487
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3883356001
Short name T273
Test name
Test status
Simulation time 219990540 ps
CPU time 0.75 seconds
Started Aug 04 05:17:07 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 198140 kb
Host smart-d9931d2c-ae43-4e95-a14a-32c226918569
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883356001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3883356001
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3419632259
Short name T80
Test name
Test status
Simulation time 98781225 ps
CPU time 0.63 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 198456 kb
Host smart-49596c90-3de1-4975-af62-d4d2dfe186db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419632259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3419632259
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.4104342153
Short name T363
Test name
Test status
Simulation time 26919056 ps
CPU time 0.61 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:06 PM PDT 24
Peak memory 199104 kb
Host smart-c692810e-e627-44f2-bc32-d48b2e452fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104342153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.4104342153
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.372146626
Short name T458
Test name
Test status
Simulation time 39093678 ps
CPU time 0.58 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198000 kb
Host smart-3a9c2cdc-e8a1-4c3c-a1f5-92625fa94866
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372146626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.372146626
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.2140766745
Short name T315
Test name
Test status
Simulation time 163817792 ps
CPU time 0.96 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 198040 kb
Host smart-d15e7b0b-1abb-4a91-a8bd-fe75f2544012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140766745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2140766745
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2973810115
Short name T498
Test name
Test status
Simulation time 48904237 ps
CPU time 0.65 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198092 kb
Host smart-4cb62b27-4cca-425e-909d-38856e44e81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973810115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2973810115
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1072405736
Short name T341
Test name
Test status
Simulation time 87634789 ps
CPU time 0.61 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 198084 kb
Host smart-da7fcaad-cb74-4290-a4e4-6f41a781a500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072405736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1072405736
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.636212145
Short name T191
Test name
Test status
Simulation time 41569759 ps
CPU time 0.68 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 201276 kb
Host smart-bb64bb86-de2b-4ab5-abdd-29ef706d8c4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636212145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.636212145
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2891510722
Short name T279
Test name
Test status
Simulation time 21044316 ps
CPU time 0.65 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 198056 kb
Host smart-571dde60-fefa-469d-a789-248c146f575e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891510722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2891510722
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.3548838458
Short name T584
Test name
Test status
Simulation time 163503823 ps
CPU time 0.82 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 209484 kb
Host smart-9d9ce2a6-6da3-4a34-80dd-75f9e63e53ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548838458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3548838458
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2319216962
Short name T266
Test name
Test status
Simulation time 52903359 ps
CPU time 0.74 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 198008 kb
Host smart-86863af2-41c6-4975-8c9f-9bdbbd442959
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319216962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2319216962
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.832245073
Short name T473
Test name
Test status
Simulation time 53370960 ps
CPU time 0.64 seconds
Started Aug 04 05:17:26 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 198556 kb
Host smart-f492a031-965c-433b-bc2a-d6f3606be024
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832245073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.832245073
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2948987979
Short name T388
Test name
Test status
Simulation time 125518482 ps
CPU time 0.9 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 200256 kb
Host smart-31185855-8966-4f23-a0d8-cc8047cb0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948987979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2948987979
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.959764708
Short name T386
Test name
Test status
Simulation time 140582012 ps
CPU time 0.72 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:22 PM PDT 24
Peak memory 198392 kb
Host smart-2e0a8c90-3a2e-44eb-bdf7-369ffe92018e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959764708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa
ble_rom_integrity_check.959764708
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3698844878
Short name T588
Test name
Test status
Simulation time 32540131 ps
CPU time 0.65 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 197996 kb
Host smart-49276871-229c-433b-93b2-7304e450099e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698844878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3698844878
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.295078138
Short name T606
Test name
Test status
Simulation time 305250599 ps
CPU time 0.95 seconds
Started Aug 04 05:17:07 PM PDT 24
Finished Aug 04 05:17:08 PM PDT 24
Peak memory 198036 kb
Host smart-8a8ef4b2-fa2c-4c61-a962-ea15b80b7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295078138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.295078138
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3037864738
Short name T438
Test name
Test status
Simulation time 66683507 ps
CPU time 0.63 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 197988 kb
Host smart-fad67dd9-c786-4e02-bb81-d1c732912288
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037864738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3037864738
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2573735333
Short name T340
Test name
Test status
Simulation time 43656136 ps
CPU time 0.59 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 198328 kb
Host smart-28f97625-9b5b-44ac-91c6-dd1f4c5ab828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573735333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2573735333
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3754078896
Short name T166
Test name
Test status
Simulation time 55462829 ps
CPU time 0.65 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 201276 kb
Host smart-41c22a90-7bd2-432e-b08e-84222385762d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754078896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3754078896
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3488739748
Short name T426
Test name
Test status
Simulation time 45310320 ps
CPU time 0.67 seconds
Started Aug 04 05:17:06 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 198240 kb
Host smart-056c2b19-c941-4421-a810-dfe523e0591b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488739748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3488739748
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.805166836
Short name T287
Test name
Test status
Simulation time 144695534 ps
CPU time 0.81 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 209120 kb
Host smart-f3b5d4b2-1d17-4b6b-9837-83af0a964ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805166836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.805166836
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3939282694
Short name T238
Test name
Test status
Simulation time 69433754 ps
CPU time 0.85 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 199104 kb
Host smart-07be8656-b787-4282-a5b9-83e5fafb046e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939282694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3939282694
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3699980539
Short name T570
Test name
Test status
Simulation time 28913012 ps
CPU time 0.7 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 199308 kb
Host smart-f9a63e50-b264-41b0-88e0-1137f1cade76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699980539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3699980539
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1562228804
Short name T17
Test name
Test status
Simulation time 25789438 ps
CPU time 0.85 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 199856 kb
Host smart-5ecf0159-1b1d-4fa4-9778-cd01e3861d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562228804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1562228804
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.334532733
Short name T550
Test name
Test status
Simulation time 32147800 ps
CPU time 0.61 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 197340 kb
Host smart-7eebc138-15d2-4464-870c-e193fb0838ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334532733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.334532733
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3160705137
Short name T34
Test name
Test status
Simulation time 934002380 ps
CPU time 0.94 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 198132 kb
Host smart-2b974a07-4114-4218-affb-0da7db88a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160705137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3160705137
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3757069444
Short name T221
Test name
Test status
Simulation time 79227573 ps
CPU time 0.63 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198140 kb
Host smart-67d2b811-9119-46c2-9de8-d82eb0c23e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757069444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3757069444
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.241062626
Short name T4
Test name
Test status
Simulation time 151777687 ps
CPU time 0.63 seconds
Started Aug 04 05:17:10 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 198460 kb
Host smart-0433ace8-a834-4125-b9f8-e6b1d02b290a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241062626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.241062626
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.124257213
Short name T529
Test name
Test status
Simulation time 65659827 ps
CPU time 0.69 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 199028 kb
Host smart-c12a899f-b9fd-43bd-b80e-3e72b313d9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124257213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.124257213
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.139658617
Short name T460
Test name
Test status
Simulation time 166449716 ps
CPU time 0.78 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 209432 kb
Host smart-5b7b5676-8e88-4215-933e-0ac0460e6439
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139658617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.139658617
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3410279569
Short name T384
Test name
Test status
Simulation time 51413386 ps
CPU time 0.87 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 199348 kb
Host smart-ec334468-8526-42f7-9970-3704ed7e95c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410279569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3410279569
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.3496125847
Short name T254
Test name
Test status
Simulation time 58115530 ps
CPU time 0.65 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 198428 kb
Host smart-1145a554-30f1-42d3-be58-e5d02fab8200
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496125847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3496125847
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.4108379992
Short name T427
Test name
Test status
Simulation time 63173617 ps
CPU time 0.78 seconds
Started Aug 04 05:15:39 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 200052 kb
Host smart-f92aab0f-d3b1-4586-82db-46f6604d1791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108379992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.4108379992
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1387122937
Short name T252
Test name
Test status
Simulation time 47835191 ps
CPU time 0.59 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 197280 kb
Host smart-ff12f824-5b7c-46fb-84ed-dea9ecc287b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387122937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1387122937
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.3088016918
Short name T35
Test name
Test status
Simulation time 2470071179 ps
CPU time 1.02 seconds
Started Aug 04 05:15:38 PM PDT 24
Finished Aug 04 05:15:39 PM PDT 24
Peak memory 198164 kb
Host smart-a969f42e-613a-4c57-a218-9301f6d0f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088016918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3088016918
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2939064737
Short name T564
Test name
Test status
Simulation time 102679994 ps
CPU time 0.59 seconds
Started Aug 04 05:15:36 PM PDT 24
Finished Aug 04 05:15:37 PM PDT 24
Peak memory 197324 kb
Host smart-49c9f450-de93-4234-af65-cebcb8a9813b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939064737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2939064737
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2248422655
Short name T311
Test name
Test status
Simulation time 60071356 ps
CPU time 0.68 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 198080 kb
Host smart-d1562ae6-3966-43c2-b120-55588a9c7741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248422655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2248422655
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2602646190
Short name T174
Test name
Test status
Simulation time 53821806 ps
CPU time 0.69 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 201328 kb
Host smart-e7b8ade5-b8c4-464d-9629-a58fe4221752
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602646190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2602646190
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.3999355847
Short name T257
Test name
Test status
Simulation time 104662908 ps
CPU time 0.73 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 199108 kb
Host smart-f879e308-8968-41bd-a504-59717af07257
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999355847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3999355847
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2177381582
Short name T474
Test name
Test status
Simulation time 244996427 ps
CPU time 0.75 seconds
Started Aug 04 05:15:39 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 209380 kb
Host smart-f4b67226-ed1a-4862-9537-a0c80ed5debb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177381582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2177381582
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2612095669
Short name T31
Test name
Test status
Simulation time 622069251 ps
CPU time 1.11 seconds
Started Aug 04 05:15:37 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 216952 kb
Host smart-37f968ee-5b60-4c0d-b517-7caadc1f20bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612095669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2612095669
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2961809666
Short name T275
Test name
Test status
Simulation time 60677124 ps
CPU time 0.87 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 198112 kb
Host smart-01f0839f-ea6f-48ae-b579-956f22b79257
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961809666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2961809666
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2355697000
Short name T378
Test name
Test status
Simulation time 31184955 ps
CPU time 0.66 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 199268 kb
Host smart-e686c9ea-2730-4282-a95a-3e975917f469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355697000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2355697000
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1039088539
Short name T555
Test name
Test status
Simulation time 61078466 ps
CPU time 0.64 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 198836 kb
Host smart-8534c790-df91-4bad-92bd-ce82e3d4151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039088539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1039088539
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.58885554
Short name T359
Test name
Test status
Simulation time 46704511 ps
CPU time 0.76 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198580 kb
Host smart-d3d1fe60-d175-4a45-b239-d639f46bbf78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58885554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disab
le_rom_integrity_check.58885554
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3589035471
Short name T116
Test name
Test status
Simulation time 31318355 ps
CPU time 0.64 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 198068 kb
Host smart-d633851e-afd7-4147-acbd-a815b9b0f764
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589035471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3589035471
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.121133740
Short name T556
Test name
Test status
Simulation time 555206266 ps
CPU time 0.92 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198140 kb
Host smart-5ed1d8a7-6a3e-4321-a64b-7a262f636bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121133740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.121133740
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.885009804
Short name T367
Test name
Test status
Simulation time 59110613 ps
CPU time 0.7 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 197964 kb
Host smart-f4775b0d-a857-4801-9e5d-58b08fb23cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885009804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.885009804
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.4228784364
Short name T523
Test name
Test status
Simulation time 87781093 ps
CPU time 0.63 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 197968 kb
Host smart-519ac283-ae8a-4b5e-80cd-f706633ad775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228784364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.4228784364
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.370542768
Short name T182
Test name
Test status
Simulation time 48058620 ps
CPU time 0.71 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 201320 kb
Host smart-220f994a-9896-4e7a-84e2-5f064c6f47ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370542768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invali
d.370542768
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.889472904
Short name T343
Test name
Test status
Simulation time 24745611 ps
CPU time 0.7 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 199208 kb
Host smart-48b0a1b7-3cf1-4f4d-912c-206e291daa72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889472904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.889472904
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1379706422
Short name T602
Test name
Test status
Simulation time 161827815 ps
CPU time 0.83 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 209580 kb
Host smart-4f5d667e-5827-44a1-b30f-ed96418f6744
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379706422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1379706422
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1157523353
Short name T319
Test name
Test status
Simulation time 97998782 ps
CPU time 0.68 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198020 kb
Host smart-15ce9cfc-fa7b-4ae2-aad5-9639e84c9564
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157523353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1157523353
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2875200841
Short name T310
Test name
Test status
Simulation time 111964011 ps
CPU time 0.68 seconds
Started Aug 04 05:17:08 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 198400 kb
Host smart-26468607-41c0-41dd-9177-0be7a7df2d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875200841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2875200841
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2042218517
Short name T468
Test name
Test status
Simulation time 53672202 ps
CPU time 0.86 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 198532 kb
Host smart-10a4b1bb-b5f2-45f3-a73a-cbaa6d973a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042218517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2042218517
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2471062862
Short name T456
Test name
Test status
Simulation time 38935002 ps
CPU time 0.6 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 197336 kb
Host smart-08950776-2983-415d-8d7a-7c3d848b8cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471062862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2471062862
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2633957107
Short name T369
Test name
Test status
Simulation time 306821166 ps
CPU time 0.96 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 198648 kb
Host smart-a175695f-30d1-485f-96a6-4ea8020eb3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633957107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2633957107
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.661614818
Short name T334
Test name
Test status
Simulation time 45719451 ps
CPU time 0.58 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 197340 kb
Host smart-2adaf975-387c-4239-b177-193a4db487bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661614818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.661614818
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1227806691
Short name T227
Test name
Test status
Simulation time 43997936 ps
CPU time 0.58 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 197992 kb
Host smart-becb3a3b-0383-42aa-84d9-537f13a4fcc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227806691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1227806691
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2585858158
Short name T170
Test name
Test status
Simulation time 42829832 ps
CPU time 0.75 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 201460 kb
Host smart-1cb39bbc-04d5-4b09-9f9b-6c5e94d939a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585858158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2585858158
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.811180034
Short name T398
Test name
Test status
Simulation time 97183181 ps
CPU time 0.7 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 199204 kb
Host smart-052d9c75-505d-4f65-a59a-9f14425b191d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811180034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.811180034
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1575482779
Short name T269
Test name
Test status
Simulation time 172673901 ps
CPU time 0.81 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 209580 kb
Host smart-57323c31-1586-4a54-8db8-f4e17608444c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575482779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1575482779
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3409327323
Short name T500
Test name
Test status
Simulation time 59268208 ps
CPU time 0.81 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 198060 kb
Host smart-dfe10e2c-2547-4e91-9e02-047017d85c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409327323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3409327323
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.2741868939
Short name T541
Test name
Test status
Simulation time 35088869 ps
CPU time 0.64 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 198528 kb
Host smart-0c448d70-1cc6-40d2-882c-84ffef472303
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741868939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2741868939
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1602258127
Short name T36
Test name
Test status
Simulation time 502704225 ps
CPU time 0.81 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 200128 kb
Host smart-3b81dcf0-a859-42b7-b39d-d2191f2a29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602258127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1602258127
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3492652655
Short name T159
Test name
Test status
Simulation time 61246957 ps
CPU time 0.69 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 199096 kb
Host smart-94e94b12-5382-4b8f-9347-e84fe6d4c40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492652655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3492652655
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.544962787
Short name T345
Test name
Test status
Simulation time 37586752 ps
CPU time 0.6 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 197232 kb
Host smart-86ecc191-ebb1-4e83-aae3-f2e48f2cf7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544962787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_
malfunc.544962787
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.4188534643
Short name T121
Test name
Test status
Simulation time 1493151550 ps
CPU time 0.95 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 197988 kb
Host smart-13db9acd-0b9a-4d04-97a9-61fa4569a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188534643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.4188534643
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.4235658930
Short name T321
Test name
Test status
Simulation time 34246296 ps
CPU time 0.6 seconds
Started Aug 04 05:17:36 PM PDT 24
Finished Aug 04 05:17:36 PM PDT 24
Peak memory 197320 kb
Host smart-df5d6b24-0eab-4740-b33e-17deed9efc92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235658930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.4235658930
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2129748771
Short name T601
Test name
Test status
Simulation time 42097535 ps
CPU time 0.7 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198056 kb
Host smart-3959183b-7c77-498b-ac40-dee167c39aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129748771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2129748771
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.634858868
Short name T162
Test name
Test status
Simulation time 72588046 ps
CPU time 0.67 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 201224 kb
Host smart-cca0a024-c025-43cb-9f20-5e4e8416ef8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634858868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.634858868
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.1359155153
Short name T231
Test name
Test status
Simulation time 20266593 ps
CPU time 0.62 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 198172 kb
Host smart-7f46c473-956c-41de-9089-837a0b0efe9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359155153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1359155153
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.849389252
Short name T563
Test name
Test status
Simulation time 164511172 ps
CPU time 0.77 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 209508 kb
Host smart-c359cb7c-67c8-4dc3-a350-6ffda6d871b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849389252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.849389252
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.3342443431
Short name T517
Test name
Test status
Simulation time 81431626 ps
CPU time 0.77 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:22 PM PDT 24
Peak memory 198164 kb
Host smart-9e71fa58-c2a5-405e-a92c-68fefe4f97f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342443431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3342443431
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.96631540
Short name T357
Test name
Test status
Simulation time 93912698 ps
CPU time 0.61 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198444 kb
Host smart-6ad0d494-9fd3-43b4-b183-a84f07f99202
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96631540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.96631540
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1144798032
Short name T303
Test name
Test status
Simulation time 68706475 ps
CPU time 0.73 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 199108 kb
Host smart-9db3ca62-cc3e-40a6-a838-0b5f8035fa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144798032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1144798032
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3739482355
Short name T161
Test name
Test status
Simulation time 71503252 ps
CPU time 0.65 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 198264 kb
Host smart-6a8bc659-431b-4b1a-b6b1-a0b84267a705
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739482355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.3739482355
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1480201364
Short name T624
Test name
Test status
Simulation time 31453192 ps
CPU time 0.61 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 198008 kb
Host smart-f7b409c0-4cd8-48da-8ee6-a4b7e820a528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480201364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.1480201364
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3637394630
Short name T623
Test name
Test status
Simulation time 844571530 ps
CPU time 0.99 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 198336 kb
Host smart-005be4eb-e91b-4f4c-be88-4e25b78d9c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637394630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3637394630
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.930931794
Short name T251
Test name
Test status
Simulation time 60145630 ps
CPU time 0.66 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 197940 kb
Host smart-b0df85d6-8106-4058-a238-94ad80c36b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930931794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.930931794
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.2800169325
Short name T440
Test name
Test status
Simulation time 39997427 ps
CPU time 0.62 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:30 PM PDT 24
Peak memory 198392 kb
Host smart-151a0a8c-3ded-4772-a940-87e30da60df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800169325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2800169325
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.977409077
Short name T141
Test name
Test status
Simulation time 29847792 ps
CPU time 0.66 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 198428 kb
Host smart-c11334e8-edf9-4c41-a8fd-9b9000ad8cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977409077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wa
keup_race.977409077
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1980560645
Short name T290
Test name
Test status
Simulation time 79560638 ps
CPU time 0.77 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 199080 kb
Host smart-037b7300-997e-4bb9-ad11-d1953c81d208
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980560645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1980560645
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1172397751
Short name T39
Test name
Test status
Simulation time 124260980 ps
CPU time 0.82 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 209604 kb
Host smart-f66f4f83-fe07-4203-b88c-979f4af9549d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172397751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1172397751
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2109937631
Short name T582
Test name
Test status
Simulation time 60157811 ps
CPU time 0.8 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 198048 kb
Host smart-0223cfe3-1d4b-4fd5-ab84-bc5982d68e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109937631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2109937631
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.4235662077
Short name T439
Test name
Test status
Simulation time 28858194 ps
CPU time 0.67 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 198540 kb
Host smart-a5d9b9ff-32d7-4366-842f-c09f86ec45e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235662077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.4235662077
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1837573029
Short name T613
Test name
Test status
Simulation time 53020015 ps
CPU time 0.95 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 200172 kb
Host smart-34d4d32f-6645-40d3-8e4e-abe5c81c08d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837573029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1837573029
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.355880539
Short name T565
Test name
Test status
Simulation time 55369673 ps
CPU time 0.78 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 198612 kb
Host smart-89d99c4d-f120-40ff-a58c-7b77f8db8575
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355880539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa
ble_rom_integrity_check.355880539
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.649388070
Short name T383
Test name
Test status
Simulation time 30087867 ps
CPU time 0.63 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198032 kb
Host smart-0aadde40-b258-4d64-a777-a821e4135063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649388070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_
malfunc.649388070
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.718092234
Short name T430
Test name
Test status
Simulation time 891808896 ps
CPU time 0.93 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 198328 kb
Host smart-1281fe9f-b520-4713-8f33-485c2323b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718092234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.718092234
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.2991269064
Short name T268
Test name
Test status
Simulation time 64827753 ps
CPU time 0.61 seconds
Started Aug 04 05:17:09 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 198016 kb
Host smart-d660d2a8-831c-4cba-8053-b1e93f31a1a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991269064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2991269064
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.853188757
Short name T298
Test name
Test status
Simulation time 68354047 ps
CPU time 0.6 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198000 kb
Host smart-41a35e75-08f3-4c52-b80b-6893c6d1be81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853188757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.853188757
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1649525494
Short name T205
Test name
Test status
Simulation time 42550668 ps
CPU time 0.73 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 201324 kb
Host smart-67d36941-93eb-4168-b77d-5b0a895ba2aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649525494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1649525494
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1490130234
Short name T295
Test name
Test status
Simulation time 114245428 ps
CPU time 0.74 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:29 PM PDT 24
Peak memory 199096 kb
Host smart-1551a36e-683d-4ae5-9523-ba1a213ae17d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490130234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1490130234
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1907686840
Short name T335
Test name
Test status
Simulation time 176195553 ps
CPU time 0.78 seconds
Started Aug 04 05:17:29 PM PDT 24
Finished Aug 04 05:17:30 PM PDT 24
Peak memory 209464 kb
Host smart-2441c1b1-78be-4703-b6d0-a27d2acafff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907686840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1907686840
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.986717898
Short name T487
Test name
Test status
Simulation time 123443301 ps
CPU time 0.71 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 197996 kb
Host smart-bd95dc2e-3d9d-4d03-bdb7-6de34f457e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986717898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.986717898
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1857100267
Short name T233
Test name
Test status
Simulation time 31661711 ps
CPU time 0.65 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 199356 kb
Host smart-68856314-4cca-4dcc-b280-029c812db27a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857100267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1857100267
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2266906570
Short name T90
Test name
Test status
Simulation time 27597514 ps
CPU time 0.69 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 199100 kb
Host smart-b4d08140-368a-4c81-943a-80de15089fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266906570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2266906570
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.429132648
Short name T154
Test name
Test status
Simulation time 52146485 ps
CPU time 0.72 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198384 kb
Host smart-142b4d5b-5bec-412b-97c6-4bb6bfc9b5b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429132648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disa
ble_rom_integrity_check.429132648
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.4148078997
Short name T129
Test name
Test status
Simulation time 39893277 ps
CPU time 0.58 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 197284 kb
Host smart-cbdbfd16-baee-478a-8b49-b4cbb3cdb30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148078997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.4148078997
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.2160011236
Short name T382
Test name
Test status
Simulation time 160808256 ps
CPU time 0.98 seconds
Started Aug 04 05:17:18 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 197968 kb
Host smart-fb18c7ca-bb90-4d10-ba16-5336dccef2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160011236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2160011236
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2834893539
Short name T445
Test name
Test status
Simulation time 48492556 ps
CPU time 0.6 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 198056 kb
Host smart-02822663-b247-4c56-a548-46923d664588
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834893539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2834893539
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2214473281
Short name T397
Test name
Test status
Simulation time 35555573 ps
CPU time 0.62 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198296 kb
Host smart-7beee5a6-41bb-4586-87ad-ca4bded2ad1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214473281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2214473281
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2195445615
Short name T168
Test name
Test status
Simulation time 68718404 ps
CPU time 0.7 seconds
Started Aug 04 05:17:25 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 201292 kb
Host smart-48414483-da3f-4b48-a6c1-9d047307cee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195445615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2195445615
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2378473269
Short name T540
Test name
Test status
Simulation time 51735635 ps
CPU time 0.71 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 199084 kb
Host smart-b60b9cdc-b320-457f-9d00-adc751d45017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378473269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2378473269
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.4169447274
Short name T320
Test name
Test status
Simulation time 103125567 ps
CPU time 1.12 seconds
Started Aug 04 05:17:12 PM PDT 24
Finished Aug 04 05:17:13 PM PDT 24
Peak memory 209528 kb
Host smart-e658a3e8-e041-42e0-8d2d-39778eb1252f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169447274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.4169447274
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2526994563
Short name T511
Test name
Test status
Simulation time 51996124 ps
CPU time 0.76 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 198196 kb
Host smart-7855302b-7f7a-4346-8b13-4f4e05699047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526994563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2526994563
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.3848456600
Short name T558
Test name
Test status
Simulation time 31166659 ps
CPU time 0.69 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 199328 kb
Host smart-bd75e8cd-b107-4bfc-bd04-af59cb7bed49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848456600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3848456600
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.3450833625
Short name T360
Test name
Test status
Simulation time 46672099 ps
CPU time 0.91 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:22 PM PDT 24
Peak memory 199968 kb
Host smart-709a6e2e-0c97-4a09-814d-d5c272e41bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450833625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3450833625
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.686332696
Short name T615
Test name
Test status
Simulation time 50048889 ps
CPU time 0.72 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 199048 kb
Host smart-84d7ad5b-21e5-4974-b6fa-0d0d180dea42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686332696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.686332696
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2115656791
Short name T259
Test name
Test status
Simulation time 30482428 ps
CPU time 0.63 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 197968 kb
Host smart-3586ac61-265a-4a18-84ca-a15cc1820672
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115656791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.2115656791
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2696346097
Short name T515
Test name
Test status
Simulation time 162506065 ps
CPU time 0.93 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:20 PM PDT 24
Peak memory 198000 kb
Host smart-5cd626b7-0ce2-424c-8aa7-a7b3b29cbde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696346097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2696346097
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.3687904002
Short name T453
Test name
Test status
Simulation time 50355921 ps
CPU time 0.64 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 198116 kb
Host smart-c9076735-c1e1-4bad-9a50-5444f35cd10b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687904002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3687904002
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1434907062
Short name T62
Test name
Test status
Simulation time 95964066 ps
CPU time 0.6 seconds
Started Aug 04 05:17:34 PM PDT 24
Finished Aug 04 05:17:35 PM PDT 24
Peak memory 198304 kb
Host smart-975408c8-9c49-4fe1-9d24-e8585441d086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434907062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1434907062
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1408921271
Short name T201
Test name
Test status
Simulation time 66767454 ps
CPU time 0.67 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 201272 kb
Host smart-b87ae866-2c71-4519-af27-79c5d5be3cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408921271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1408921271
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.290054526
Short name T380
Test name
Test status
Simulation time 40837748 ps
CPU time 0.68 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 198200 kb
Host smart-0fd84ab4-be03-459c-b778-5d91536391d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290054526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.290054526
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2629485748
Short name T535
Test name
Test status
Simulation time 115247076 ps
CPU time 0.84 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 209536 kb
Host smart-2f45d9ab-718f-41d8-a9ab-ba01f67d606b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629485748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2629485748
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1441853430
Short name T389
Test name
Test status
Simulation time 240856929 ps
CPU time 0.7 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 198224 kb
Host smart-3e3f6fda-7292-434c-bd75-ffb93a57e937
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441853430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1441853430
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.4117283313
Short name T332
Test name
Test status
Simulation time 27680188 ps
CPU time 0.65 seconds
Started Aug 04 05:17:18 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 199288 kb
Host smart-925b0897-ed2c-4ae7-8a0a-6bdba83a6187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117283313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.4117283313
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2554248046
Short name T396
Test name
Test status
Simulation time 110190721 ps
CPU time 0.78 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 199940 kb
Host smart-a90907f9-21e2-4f04-b4cc-bba1c7414e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554248046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2554248046
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3045720853
Short name T571
Test name
Test status
Simulation time 67096340 ps
CPU time 0.65 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 198536 kb
Host smart-5e41e415-13d1-4d4e-a7f4-33d664523583
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045720853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3045720853
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4207398272
Short name T5
Test name
Test status
Simulation time 31656973 ps
CPU time 0.65 seconds
Started Aug 04 05:17:29 PM PDT 24
Finished Aug 04 05:17:30 PM PDT 24
Peak memory 197304 kb
Host smart-5f1f6492-6522-4620-91d9-b6640715ccf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207398272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.4207398272
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.836234489
Short name T408
Test name
Test status
Simulation time 605692943 ps
CPU time 0.92 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198324 kb
Host smart-acb4d96d-4c21-4143-8259-78088adbe1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836234489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.836234489
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.82550354
Short name T264
Test name
Test status
Simulation time 53292051 ps
CPU time 0.67 seconds
Started Aug 04 05:17:25 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 197336 kb
Host smart-e0b8bb0b-1f4f-4c68-a252-7b455adebd8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82550354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.82550354
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2030749232
Short name T289
Test name
Test status
Simulation time 25264447 ps
CPU time 0.61 seconds
Started Aug 04 05:17:15 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 198352 kb
Host smart-23315e84-80f5-480d-90e7-fac9733f51ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030749232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2030749232
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.444878603
Short name T611
Test name
Test status
Simulation time 55699379 ps
CPU time 0.68 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 201332 kb
Host smart-c35d084e-7f75-4e46-9e62-df0af309b392
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444878603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invali
d.444878603
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.997846307
Short name T255
Test name
Test status
Simulation time 46746574 ps
CPU time 0.73 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 199020 kb
Host smart-d76e5141-adbd-4049-92f6-99723707371c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997846307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.997846307
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3695748029
Short name T413
Test name
Test status
Simulation time 391072493 ps
CPU time 0.73 seconds
Started Aug 04 05:17:18 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 209392 kb
Host smart-2cfcca2a-abe4-4304-8bbf-570f30db438d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695748029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3695748029
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.2669134039
Short name T274
Test name
Test status
Simulation time 60413361 ps
CPU time 0.81 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 197976 kb
Host smart-b3497ee3-e0db-42e0-bed3-841dce530dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669134039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2669134039
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.593922660
Short name T608
Test name
Test status
Simulation time 67594672 ps
CPU time 0.63 seconds
Started Aug 04 05:17:11 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 198548 kb
Host smart-db1017cf-0cf6-4de3-b2a6-3e4f58d10aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593922660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.593922660
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1443356708
Short name T552
Test name
Test status
Simulation time 35396252 ps
CPU time 0.85 seconds
Started Aug 04 05:17:27 PM PDT 24
Finished Aug 04 05:17:28 PM PDT 24
Peak memory 200340 kb
Host smart-7fbfda4f-f727-4d6e-823f-748ec4fbbe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443356708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1443356708
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.353865864
Short name T612
Test name
Test status
Simulation time 62097295 ps
CPU time 0.81 seconds
Started Aug 04 05:17:25 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 199020 kb
Host smart-882be5c7-48f3-46da-9e96-2dc36a168126
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353865864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disa
ble_rom_integrity_check.353865864
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.320666074
Short name T123
Test name
Test status
Simulation time 31365401 ps
CPU time 0.65 seconds
Started Aug 04 05:17:25 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 197952 kb
Host smart-70280ab4-50b8-48cd-a398-209f28bb99fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320666074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.320666074
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1643726713
Short name T471
Test name
Test status
Simulation time 720270733 ps
CPU time 0.94 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 197996 kb
Host smart-9b2ed18e-1592-42cc-a1bd-a9995652f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643726713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1643726713
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1609837263
Short name T444
Test name
Test status
Simulation time 42713439 ps
CPU time 0.59 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:18 PM PDT 24
Peak memory 198064 kb
Host smart-bb00d4cb-64de-49bf-ad9f-e998a7f67416
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609837263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1609837263
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.1438874897
Short name T240
Test name
Test status
Simulation time 46123296 ps
CPU time 0.59 seconds
Started Aug 04 05:17:36 PM PDT 24
Finished Aug 04 05:17:36 PM PDT 24
Peak memory 198012 kb
Host smart-27c5d8be-b57b-46ae-962f-ae279b5a8822
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438874897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1438874897
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1687314903
Short name T197
Test name
Test status
Simulation time 49513784 ps
CPU time 0.67 seconds
Started Aug 04 05:17:14 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 201264 kb
Host smart-be9ccd64-a9c1-44cc-b369-d682d0640149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687314903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1687314903
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.1167993732
Short name T213
Test name
Test status
Simulation time 57256285 ps
CPU time 0.62 seconds
Started Aug 04 05:17:38 PM PDT 24
Finished Aug 04 05:17:38 PM PDT 24
Peak memory 199056 kb
Host smart-3f17dc49-2728-466c-ba38-bc81a739f8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167993732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.1167993732
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.377677385
Short name T42
Test name
Test status
Simulation time 41138569 ps
CPU time 0.65 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 199424 kb
Host smart-73f05b35-c3a9-4aed-8017-157368115726
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377677385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.377677385
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1776439901
Short name T593
Test name
Test status
Simulation time 148466122 ps
CPU time 0.78 seconds
Started Aug 04 05:17:16 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 209428 kb
Host smart-2b640d25-0919-412b-b193-a3d4bb5a41dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776439901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1776439901
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3135865105
Short name T548
Test name
Test status
Simulation time 72334538 ps
CPU time 0.86 seconds
Started Aug 04 05:17:13 PM PDT 24
Finished Aug 04 05:17:15 PM PDT 24
Peak memory 199104 kb
Host smart-4ae4bb8b-4036-4901-8626-5645651f8cba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135865105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3135865105
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.475015993
Short name T64
Test name
Test status
Simulation time 48442034 ps
CPU time 0.59 seconds
Started Aug 04 05:17:18 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 199244 kb
Host smart-d47b98d4-c813-466d-bd44-469f1cd3adb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475015993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.475015993
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1404002123
Short name T489
Test name
Test status
Simulation time 71607605 ps
CPU time 0.65 seconds
Started Aug 04 05:17:21 PM PDT 24
Finished Aug 04 05:17:22 PM PDT 24
Peak memory 198468 kb
Host smart-ecf4fadd-f338-4b8d-9b77-1148d8ccf4ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404002123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1404002123
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.210851305
Short name T407
Test name
Test status
Simulation time 37739676 ps
CPU time 0.56 seconds
Started Aug 04 05:17:18 PM PDT 24
Finished Aug 04 05:17:19 PM PDT 24
Peak memory 198044 kb
Host smart-09289f1d-4690-41fa-854a-a4263c349d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210851305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.210851305
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.795980729
Short name T325
Test name
Test status
Simulation time 160963772 ps
CPU time 0.96 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 198136 kb
Host smart-b503330a-6adf-4881-8dfc-502a0aaa62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795980729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.795980729
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2167399355
Short name T291
Test name
Test status
Simulation time 29234050 ps
CPU time 0.61 seconds
Started Aug 04 05:17:20 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198052 kb
Host smart-dcb87f17-f354-41fe-9ba6-d57b45aede48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167399355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2167399355
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.620017399
Short name T358
Test name
Test status
Simulation time 63021165 ps
CPU time 0.6 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 198124 kb
Host smart-997899ba-cacb-446c-ac4c-676fab1ff1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620017399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.620017399
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.3454268573
Short name T219
Test name
Test status
Simulation time 69592030 ps
CPU time 0.84 seconds
Started Aug 04 05:17:19 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 198688 kb
Host smart-fb55a2bf-03a0-4b1b-a1b4-6ede57566abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454268573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.3454268573
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.461809412
Short name T299
Test name
Test status
Simulation time 153838259 ps
CPU time 0.83 seconds
Started Aug 04 05:17:25 PM PDT 24
Finished Aug 04 05:17:26 PM PDT 24
Peak memory 209512 kb
Host smart-1be921ff-65c6-443e-bcd9-c31ed83f316f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461809412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.461809412
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.4089158506
Short name T142
Test name
Test status
Simulation time 68259142 ps
CPU time 0.63 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 198836 kb
Host smart-e5b36aba-9f3c-4fb1-81bc-f7fd50b82d2b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089158506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.4089158506
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.886540881
Short name T454
Test name
Test status
Simulation time 61581101 ps
CPU time 0.81 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 199232 kb
Host smart-88dccb3f-35f9-445e-9d75-baaa9ad492d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886540881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.886540881
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2676826675
Short name T260
Test name
Test status
Simulation time 42602062 ps
CPU time 0.66 seconds
Started Aug 04 05:17:17 PM PDT 24
Finished Aug 04 05:17:17 PM PDT 24
Peak memory 198408 kb
Host smart-5edf80ff-bb63-4b24-aa51-8f879ab43df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676826675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2676826675
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.862394276
Short name T10
Test name
Test status
Simulation time 48203956 ps
CPU time 0.7 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 199136 kb
Host smart-e04bf047-42ab-41d2-bebd-c213192daead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862394276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.862394276
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2013799910
Short name T457
Test name
Test status
Simulation time 97871692 ps
CPU time 0.66 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:44 PM PDT 24
Peak memory 198508 kb
Host smart-7744975f-ed9a-4351-8aef-73dea3ecbe01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013799910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2013799910
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.4292500886
Short name T237
Test name
Test status
Simulation time 41028316 ps
CPU time 0.61 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 197348 kb
Host smart-860ad2d0-a2fe-4600-9008-6d94beab72b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292500886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.4292500886
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.3495023428
Short name T391
Test name
Test status
Simulation time 1062042274 ps
CPU time 0.97 seconds
Started Aug 04 05:16:23 PM PDT 24
Finished Aug 04 05:16:24 PM PDT 24
Peak memory 198072 kb
Host smart-f6e09b3a-15b4-4468-a8f4-91090543a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495023428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3495023428
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3087795671
Short name T301
Test name
Test status
Simulation time 53838476 ps
CPU time 0.61 seconds
Started Aug 04 05:15:45 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 197372 kb
Host smart-a8bad0e0-0302-4b02-a948-4f53b3038d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087795671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3087795671
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1193090765
Short name T322
Test name
Test status
Simulation time 33772336 ps
CPU time 0.59 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 198460 kb
Host smart-9edd0128-b2c8-426f-8ff8-9dfa83eecc4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193090765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1193090765
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.3381748820
Short name T165
Test name
Test status
Simulation time 41271476 ps
CPU time 0.73 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:44 PM PDT 24
Peak memory 201348 kb
Host smart-5a74c199-fa5e-4720-a030-ba08374cb620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381748820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.3381748820
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2684198759
Short name T270
Test name
Test status
Simulation time 71470076 ps
CPU time 0.89 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 199148 kb
Host smart-0c7cd5c5-ff8e-4066-b416-5c632b1785c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684198759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2684198759
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2220411012
Short name T349
Test name
Test status
Simulation time 110161631 ps
CPU time 0.82 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 209492 kb
Host smart-c64f9156-49cf-4dfc-b354-419fdd8fef43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220411012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2220411012
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3996078877
Short name T337
Test name
Test status
Simulation time 173408158 ps
CPU time 0.95 seconds
Started Aug 04 05:15:43 PM PDT 24
Finished Aug 04 05:15:44 PM PDT 24
Peak memory 199304 kb
Host smart-f9189f40-1e16-4b3d-946b-10ddf8ec3ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996078877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3996078877
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.3682138417
Short name T452
Test name
Test status
Simulation time 33679943 ps
CPU time 0.66 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 198416 kb
Host smart-1201c3da-3e02-4f41-8498-a9c2eaf92ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682138417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3682138417
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.4294171148
Short name T313
Test name
Test status
Simulation time 79068029 ps
CPU time 0.9 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 200364 kb
Host smart-aaba4d6b-2b62-4abf-9125-db98780e8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294171148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.4294171148
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1225327195
Short name T136
Test name
Test status
Simulation time 60110168 ps
CPU time 0.77 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 198548 kb
Host smart-4881b2c6-3524-4d2e-9904-0dfd44c33308
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225327195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1225327195
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1023818544
Short name T547
Test name
Test status
Simulation time 39218949 ps
CPU time 0.56 seconds
Started Aug 04 05:15:40 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 198044 kb
Host smart-4f819f97-ae9c-4f1b-990d-465f72051c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023818544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1023818544
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.2877700308
Short name T526
Test name
Test status
Simulation time 605224720 ps
CPU time 0.93 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 198436 kb
Host smart-8deaed9f-e67c-457f-b087-9f2b1cb1ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877700308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2877700308
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.1589707501
Short name T424
Test name
Test status
Simulation time 47995860 ps
CPU time 0.7 seconds
Started Aug 04 05:15:42 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 198104 kb
Host smart-a4b370ab-afa0-4ab7-8c42-40be655740ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589707501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.1589707501
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1083676879
Short name T390
Test name
Test status
Simulation time 24753529 ps
CPU time 0.6 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 198432 kb
Host smart-ecdd6e99-77f8-4433-b5d8-ae89be677ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083676879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1083676879
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1017785079
Short name T196
Test name
Test status
Simulation time 41947932 ps
CPU time 0.74 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 201428 kb
Host smart-eaf0fd75-c488-4ece-bfef-bd6674ed2373
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017785079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1017785079
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1230525272
Short name T538
Test name
Test status
Simulation time 36236761 ps
CPU time 0.67 seconds
Started Aug 04 05:15:41 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 199116 kb
Host smart-038c92fd-f5f8-4d75-9cf9-4fb3368f23c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230525272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1230525272
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.483916268
Short name T607
Test name
Test status
Simulation time 172304577 ps
CPU time 0.83 seconds
Started Aug 04 05:15:45 PM PDT 24
Finished Aug 04 05:15:46 PM PDT 24
Peak memory 209456 kb
Host smart-15dfe63e-45f9-4688-a647-12638fccab18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483916268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.483916268
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.916817526
Short name T479
Test name
Test status
Simulation time 54267735 ps
CPU time 0.75 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 198008 kb
Host smart-e7b0ae56-523f-43ce-a0fe-c78fa6d252f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916817526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.916817526
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1808069647
Short name T512
Test name
Test status
Simulation time 28936086 ps
CPU time 0.7 seconds
Started Aug 04 05:15:45 PM PDT 24
Finished Aug 04 05:15:46 PM PDT 24
Peak memory 199380 kb
Host smart-413e15bc-b835-4fcb-9e5a-a9126dbd57a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808069647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1808069647
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.3527110201
Short name T524
Test name
Test status
Simulation time 25544429 ps
CPU time 0.68 seconds
Started Aug 04 05:15:45 PM PDT 24
Finished Aug 04 05:15:46 PM PDT 24
Peak memory 198700 kb
Host smart-9e9d2963-75e2-4efb-badf-6f5c67c04abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527110201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3527110201
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1125092898
Short name T209
Test name
Test status
Simulation time 56680252 ps
CPU time 0.79 seconds
Started Aug 04 05:15:48 PM PDT 24
Finished Aug 04 05:15:49 PM PDT 24
Peak memory 199040 kb
Host smart-18b483a7-1d6e-43a4-bd03-aaf984a1aced
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125092898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1125092898
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.97820903
Short name T128
Test name
Test status
Simulation time 47880452 ps
CPU time 0.63 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 197260 kb
Host smart-74af14ba-4131-4f53-abb7-4753acaa7a8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97820903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_ma
lfunc.97820903
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2070309785
Short name T401
Test name
Test status
Simulation time 627470989 ps
CPU time 0.91 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 198400 kb
Host smart-a54664ad-6e89-4e8f-8126-baefb33af0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070309785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2070309785
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.2916771309
Short name T431
Test name
Test status
Simulation time 48716809 ps
CPU time 0.63 seconds
Started Aug 04 05:15:49 PM PDT 24
Finished Aug 04 05:15:49 PM PDT 24
Peak memory 198104 kb
Host smart-73791323-2377-4801-9e66-c79e26e86ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916771309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2916771309
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1031603061
Short name T530
Test name
Test status
Simulation time 79105626 ps
CPU time 0.62 seconds
Started Aug 04 05:15:57 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 198116 kb
Host smart-b9a3d859-c816-4e9e-9085-65d29fe6e1af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031603061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1031603061
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3283388753
Short name T172
Test name
Test status
Simulation time 44529354 ps
CPU time 0.69 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 201428 kb
Host smart-d303ae7f-acd3-4e05-8468-ef7d34c2bb33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283388753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3283388753
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.3136561746
Short name T37
Test name
Test status
Simulation time 36216252 ps
CPU time 0.73 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 199108 kb
Host smart-876cd5a3-a605-4420-ac1e-5f24cf50b149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136561746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3136561746
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1096251884
Short name T261
Test name
Test status
Simulation time 114886660 ps
CPU time 0.82 seconds
Started Aug 04 05:15:48 PM PDT 24
Finished Aug 04 05:15:49 PM PDT 24
Peak memory 209492 kb
Host smart-9248b773-b69e-4db3-b04a-937e66941be5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096251884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1096251884
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.905139108
Short name T477
Test name
Test status
Simulation time 72648256 ps
CPU time 0.91 seconds
Started Aug 04 05:15:45 PM PDT 24
Finished Aug 04 05:15:46 PM PDT 24
Peak memory 199124 kb
Host smart-0f5fab51-17da-448a-8075-3ce089131baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905139108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.905139108
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2506986999
Short name T356
Test name
Test status
Simulation time 153762381 ps
CPU time 0.64 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 198508 kb
Host smart-446bf1c0-1539-44d0-8373-de1d912fb4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506986999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2506986999
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.3957812862
Short name T15
Test name
Test status
Simulation time 51205602 ps
CPU time 0.81 seconds
Started Aug 04 05:15:46 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 200000 kb
Host smart-0a2ed323-4fc2-4a3c-a5a2-a45dfdc3566a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957812862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3957812862
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3612276280
Short name T112
Test name
Test status
Simulation time 138648338 ps
CPU time 0.81 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:51 PM PDT 24
Peak memory 200032 kb
Host smart-bc074431-b5cb-4979-b9af-676805993cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612276280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3612276280
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2048705180
Short name T122
Test name
Test status
Simulation time 334377326 ps
CPU time 1.01 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:51 PM PDT 24
Peak memory 198428 kb
Host smart-d57c34cc-412c-40ac-baa0-3fc77781bb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048705180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2048705180
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2613626580
Short name T351
Test name
Test status
Simulation time 35948184 ps
CPU time 0.65 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:50 PM PDT 24
Peak memory 198052 kb
Host smart-dad19a08-aaed-47cd-8c9b-5acbd69629df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613626580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2613626580
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.11764249
Short name T127
Test name
Test status
Simulation time 42644084 ps
CPU time 0.65 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 198020 kb
Host smart-ab4265c2-0499-4f69-bdac-f5c70ec2e4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.11764249
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1950617346
Short name T29
Test name
Test status
Simulation time 73096370 ps
CPU time 0.68 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 201420 kb
Host smart-e64b1793-8926-4647-be50-e93812926ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950617346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1950617346
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1686740460
Short name T595
Test name
Test status
Simulation time 38080729 ps
CPU time 0.62 seconds
Started Aug 04 05:15:47 PM PDT 24
Finished Aug 04 05:15:48 PM PDT 24
Peak memory 198296 kb
Host smart-0248cce7-c15a-412f-adb3-23eccf2587ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686740460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1686740460
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.246719175
Short name T441
Test name
Test status
Simulation time 99936870 ps
CPU time 0.9 seconds
Started Aug 04 05:15:49 PM PDT 24
Finished Aug 04 05:15:50 PM PDT 24
Peak memory 209448 kb
Host smart-6ba53c14-5013-4ee2-b77f-fef10c18c0d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246719175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.246719175
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.781748012
Short name T38
Test name
Test status
Simulation time 109191622 ps
CPU time 0.73 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:51 PM PDT 24
Peak memory 198044 kb
Host smart-40df9a4e-1d90-48af-bc4e-6eced09f090c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781748012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.781748012
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.3973226811
Short name T288
Test name
Test status
Simulation time 96428290 ps
CPU time 0.62 seconds
Started Aug 04 05:15:44 PM PDT 24
Finished Aug 04 05:15:45 PM PDT 24
Peak memory 198532 kb
Host smart-88581ebd-5c00-4b6a-bd0a-2942e884f478
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973226811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.3973226811
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3132384450
Short name T572
Test name
Test status
Simulation time 135416059 ps
CPU time 0.9 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 200352 kb
Host smart-7f247619-396f-472a-bcdc-7423dc7ec982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132384450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3132384450
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.4215215878
Short name T617
Test name
Test status
Simulation time 49905642 ps
CPU time 0.79 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:51 PM PDT 24
Peak memory 199124 kb
Host smart-cc56108d-eaa6-4266-b992-b61767986c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215215878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.4215215878
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.31652813
Short name T338
Test name
Test status
Simulation time 40345993 ps
CPU time 0.58 seconds
Started Aug 04 05:15:48 PM PDT 24
Finished Aug 04 05:15:49 PM PDT 24
Peak memory 198008 kb
Host smart-ad07f800-50ee-4c0d-b8ef-0f5257d165ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31652813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_ma
lfunc.31652813
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1732746839
Short name T527
Test name
Test status
Simulation time 825260580 ps
CPU time 0.99 seconds
Started Aug 04 05:15:56 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 198344 kb
Host smart-9b666bfb-e74e-4364-9e92-d8baf371c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732746839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1732746839
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.721243054
Short name T506
Test name
Test status
Simulation time 56120418 ps
CPU time 0.6 seconds
Started Aug 04 05:15:57 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 197332 kb
Host smart-45ef96fa-aa5a-40ff-9502-8b9b9d365b7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721243054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.721243054
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.1776693275
Short name T348
Test name
Test status
Simulation time 52390945 ps
CPU time 0.61 seconds
Started Aug 04 05:15:50 PM PDT 24
Finished Aug 04 05:15:51 PM PDT 24
Peak memory 197968 kb
Host smart-7ac6f637-1793-4da6-a347-f14fca63fbb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776693275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1776693275
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.4239623669
Short name T598
Test name
Test status
Simulation time 138573324 ps
CPU time 0.69 seconds
Started Aug 04 05:16:01 PM PDT 24
Finished Aug 04 05:16:02 PM PDT 24
Peak memory 201332 kb
Host smart-52be76c2-12a4-48b6-b624-4a91c9d1e66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239623669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.4239623669
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1125792038
Short name T262
Test name
Test status
Simulation time 27485381 ps
CPU time 0.67 seconds
Started Aug 04 05:15:51 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 199056 kb
Host smart-e27faa7c-ab6a-4a96-82b3-3391a6864556
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125792038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1125792038
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.4243658039
Short name T1
Test name
Test status
Simulation time 98713239 ps
CPU time 0.99 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 209500 kb
Host smart-8ee16c2f-7e65-4a15-ac3e-569eb4d73f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243658039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.4243658039
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2948308362
Short name T331
Test name
Test status
Simulation time 172166811 ps
CPU time 0.81 seconds
Started Aug 04 05:15:56 PM PDT 24
Finished Aug 04 05:15:57 PM PDT 24
Peak memory 199184 kb
Host smart-eb5525d8-3e81-4ae2-8926-f8a316bdad80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948308362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2948308362
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.51440493
Short name T79
Test name
Test status
Simulation time 71444381 ps
CPU time 0.65 seconds
Started Aug 04 05:15:52 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 198392 kb
Host smart-f469c66c-5452-420f-904b-f2800fe1268a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51440493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.51440493
Directory /workspace/9.pwrmgr_smoke/latest
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