Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

500

1

T5

1

T10

2

T13

2

auto[1]

441

1

T5

5

T9

2

T42

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524

1

T5

3

T9

2

T10

2

auto[1]

417

1

T5

3

T42

2

T15

6

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

433

1

T42

5

T15

5

T47

1

auto[1]

508

1

T5

6

T9

2

T10

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

774

1

T5

4

T9

1

T10

1

auto[1]

167

1

T5

2

T9

1

T10

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

419

1

T5

5

T9

2

T42

4

auto[1]

522

1

T5

1

T10

2

T13

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

491

1

T5

1

T9

2

T10

2

auto[1]

450

1

T5

5

T42

3

T15

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

21

1

T42

1

T16

1

T29

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T42

1

T164

1

T165

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

13

1

T16

1

T81

1

T88

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T81

1

T166

1

-

-

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

26

1

T29

3

T86

1

T167

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T168

1

T169

1

T170

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

71

1

T10

1

T13

1

T21

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

54

1

T10

1

T13

1

T21

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T29

1

T85

1

T51

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T171

1

T172

1

-

-

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T29

1

T92

2

T93

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T49

1

T168

1

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T52

2

T51

1

T167

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T51

1

T164

1

T173

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T5

1

T15

1

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T171

1

T174

2

T175

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T15

1

T85

1

T88

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T176

1

T170

1

T177

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18

1

T86

1

T87

1

T178

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T178

1

T179

2

T180

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

11

1

T87

1

T181

2

T182

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T183

1

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T15

1

T16

1

T62

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T62

1

T184

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

20

1

T16

2

T29

1

T86

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T48

1

T175

1

T186

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T15

1

T81

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T27

1

T187

1

T188

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T29

1

T86

2

T88

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T189

1

T186

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

22

1

T15

1

T29

1

T81

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T190

1

T191

1

T192

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

19

1

T42

1

T51

1

T26

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T51

1

T26

1

T193

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20

1

T9

1

T15

1

T29

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T9

1

T140

1

T194

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

17

1

T16

1

T29

1

T195

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T195

1

T196

1

T166

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T14

1

T15

1

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T197

1

T198

1

T142

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T15

1

T47

1

T16

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T197

1

T191

1

T199

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T5

1

T42

1

T15

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T5

1

T81

1

T141

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T15

1

T16

1

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T187

1

T200

1

T201

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T47

1

T52

1

T48

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T47

1

T48

1

T196

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

19

1

T52

2

T167

1

T202

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T189

1

T203

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

24

1

T5

1

T52

2

T86

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T176

1

T203

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T29

1

T86

2

T164

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T204

1

T188

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

19

1

T16

1

T29

1

T62

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T62

1

T178

1

T173

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T15

1

T16

1

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T190

1

T184

1

T205

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T5

1

T52

1

T27

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T5

1

T27

1

T165

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T42

1

T15

1

T86

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T42

1

T27

1

T185

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T47

1

T62

1

T52

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T47

1

T195

1

T205

1