Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.23 96.15 99.44 96.00 96.18 100.00 95.74


Total test records in report: 730
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T567 /workspace/coverage/default/40.pwrmgr_reset_invalid.1246607309 Aug 05 05:47:03 PM PDT 24 Aug 05 05:47:04 PM PDT 24 163162981 ps
T568 /workspace/coverage/default/44.pwrmgr_lowpower_invalid.3711735257 Aug 05 05:47:31 PM PDT 24 Aug 05 05:47:32 PM PDT 24 44526062 ps
T569 /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.336008158 Aug 05 05:47:02 PM PDT 24 Aug 05 05:47:03 PM PDT 24 73520567 ps
T570 /workspace/coverage/default/1.pwrmgr_global_esc.802320114 Aug 05 05:45:25 PM PDT 24 Aug 05 05:45:26 PM PDT 24 44259355 ps
T571 /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3150948375 Aug 05 05:47:36 PM PDT 24 Aug 05 05:47:37 PM PDT 24 559749983 ps
T572 /workspace/coverage/default/7.pwrmgr_reset.1614004130 Aug 05 05:45:45 PM PDT 24 Aug 05 05:45:46 PM PDT 24 51036522 ps
T573 /workspace/coverage/default/44.pwrmgr_glitch.1100656408 Aug 05 05:47:26 PM PDT 24 Aug 05 05:47:27 PM PDT 24 38871959 ps
T188 /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2109425718 Aug 05 05:46:53 PM PDT 24 Aug 05 05:46:54 PM PDT 24 44016099 ps
T574 /workspace/coverage/default/46.pwrmgr_aborted_low_power.4247375086 Aug 05 05:47:27 PM PDT 24 Aug 05 05:47:27 PM PDT 24 100839504 ps
T575 /workspace/coverage/default/16.pwrmgr_reset_invalid.4196124401 Aug 05 05:46:08 PM PDT 24 Aug 05 05:46:09 PM PDT 24 102526957 ps
T576 /workspace/coverage/default/16.pwrmgr_glitch.3747867139 Aug 05 05:46:08 PM PDT 24 Aug 05 05:46:09 PM PDT 24 70806594 ps
T577 /workspace/coverage/default/14.pwrmgr_reset_invalid.3932922146 Aug 05 05:46:08 PM PDT 24 Aug 05 05:46:09 PM PDT 24 147551991 ps
T578 /workspace/coverage/default/49.pwrmgr_aborted_low_power.3697149521 Aug 05 05:47:39 PM PDT 24 Aug 05 05:47:40 PM PDT 24 84113259 ps
T579 /workspace/coverage/default/48.pwrmgr_reset.3742970831 Aug 05 05:48:02 PM PDT 24 Aug 05 05:48:03 PM PDT 24 61898590 ps
T580 /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2715183622 Aug 05 05:46:28 PM PDT 24 Aug 05 05:46:29 PM PDT 24 90359106 ps
T581 /workspace/coverage/default/9.pwrmgr_global_esc.2670806101 Aug 05 05:45:58 PM PDT 24 Aug 05 05:45:59 PM PDT 24 105739249 ps
T209 /workspace/coverage/default/0.pwrmgr_stress_all.428975688 Aug 05 05:45:25 PM PDT 24 Aug 05 05:45:26 PM PDT 24 116939446 ps
T582 /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2056236849 Aug 05 05:47:02 PM PDT 24 Aug 05 05:47:03 PM PDT 24 59586989 ps
T583 /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1885794794 Aug 05 05:47:13 PM PDT 24 Aug 05 05:47:14 PM PDT 24 30675447 ps
T584 /workspace/coverage/default/41.pwrmgr_glitch.825764263 Aug 05 05:47:14 PM PDT 24 Aug 05 05:47:15 PM PDT 24 28508533 ps
T585 /workspace/coverage/default/17.pwrmgr_reset.3034951437 Aug 05 05:46:16 PM PDT 24 Aug 05 05:46:17 PM PDT 24 69787185 ps
T586 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2814977522 Aug 05 05:47:14 PM PDT 24 Aug 05 05:47:14 PM PDT 24 31076605 ps
T587 /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1205890626 Aug 05 05:47:12 PM PDT 24 Aug 05 05:47:13 PM PDT 24 39124947 ps
T588 /workspace/coverage/default/27.pwrmgr_escalation_timeout.338838623 Aug 05 05:47:19 PM PDT 24 Aug 05 05:47:20 PM PDT 24 308028020 ps
T589 /workspace/coverage/default/47.pwrmgr_reset.1898202554 Aug 05 05:47:48 PM PDT 24 Aug 05 05:47:49 PM PDT 24 108530478 ps
T590 /workspace/coverage/default/36.pwrmgr_glitch.784882011 Aug 05 05:47:03 PM PDT 24 Aug 05 05:47:04 PM PDT 24 44939738 ps
T591 /workspace/coverage/default/23.pwrmgr_smoke.1890098352 Aug 05 05:46:32 PM PDT 24 Aug 05 05:46:33 PM PDT 24 30942799 ps
T592 /workspace/coverage/default/0.pwrmgr_glitch.3451055999 Aug 05 05:45:25 PM PDT 24 Aug 05 05:45:25 PM PDT 24 24203724 ps
T593 /workspace/coverage/default/5.pwrmgr_escalation_timeout.593045686 Aug 05 05:45:40 PM PDT 24 Aug 05 05:45:41 PM PDT 24 163547188 ps
T594 /workspace/coverage/default/30.pwrmgr_global_esc.2755693085 Aug 05 05:47:11 PM PDT 24 Aug 05 05:47:12 PM PDT 24 72297190 ps
T595 /workspace/coverage/default/3.pwrmgr_smoke.4162615503 Aug 05 05:45:30 PM PDT 24 Aug 05 05:45:31 PM PDT 24 100301995 ps
T596 /workspace/coverage/default/37.pwrmgr_escalation_timeout.2615864208 Aug 05 05:46:58 PM PDT 24 Aug 05 05:47:00 PM PDT 24 160716751 ps
T597 /workspace/coverage/default/39.pwrmgr_reset.4005940764 Aug 05 05:47:35 PM PDT 24 Aug 05 05:47:36 PM PDT 24 37211533 ps
T598 /workspace/coverage/default/43.pwrmgr_reset.1255681011 Aug 05 05:47:22 PM PDT 24 Aug 05 05:47:22 PM PDT 24 38848264 ps
T599 /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3913111351 Aug 05 05:45:58 PM PDT 24 Aug 05 05:45:59 PM PDT 24 80144270 ps
T600 /workspace/coverage/default/29.pwrmgr_reset.3959595366 Aug 05 05:46:43 PM PDT 24 Aug 05 05:46:43 PM PDT 24 43792052 ps
T601 /workspace/coverage/default/3.pwrmgr_reset_invalid.3081822226 Aug 05 05:45:34 PM PDT 24 Aug 05 05:45:35 PM PDT 24 158119857 ps
T602 /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2971322696 Aug 05 05:47:05 PM PDT 24 Aug 05 05:47:06 PM PDT 24 38054298 ps
T603 /workspace/coverage/default/41.pwrmgr_reset.2246990412 Aug 05 05:47:11 PM PDT 24 Aug 05 05:47:12 PM PDT 24 47623566 ps
T604 /workspace/coverage/default/24.pwrmgr_global_esc.1344122972 Aug 05 05:47:24 PM PDT 24 Aug 05 05:47:35 PM PDT 24 42466746 ps
T605 /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3487733340 Aug 05 05:46:34 PM PDT 24 Aug 05 05:46:35 PM PDT 24 31140648 ps
T177 /workspace/coverage/default/18.pwrmgr_lowpower_invalid.356380596 Aug 05 05:46:15 PM PDT 24 Aug 05 05:46:16 PM PDT 24 53886254 ps
T606 /workspace/coverage/default/22.pwrmgr_reset.3003190119 Aug 05 05:47:00 PM PDT 24 Aug 05 05:47:01 PM PDT 24 60204705 ps
T607 /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2870772708 Aug 05 05:47:33 PM PDT 24 Aug 05 05:47:33 PM PDT 24 54591773 ps
T186 /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1200461288 Aug 05 05:46:13 PM PDT 24 Aug 05 05:46:14 PM PDT 24 40656960 ps
T608 /workspace/coverage/default/10.pwrmgr_aborted_low_power.1878789170 Aug 05 05:45:56 PM PDT 24 Aug 05 05:45:57 PM PDT 24 20344837 ps
T609 /workspace/coverage/default/27.pwrmgr_aborted_low_power.2916953335 Aug 05 05:47:21 PM PDT 24 Aug 05 05:47:22 PM PDT 24 26197700 ps
T610 /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2498655805 Aug 05 05:46:42 PM PDT 24 Aug 05 05:46:43 PM PDT 24 37920383 ps
T611 /workspace/coverage/default/12.pwrmgr_escalation_timeout.2603495893 Aug 05 05:46:05 PM PDT 24 Aug 05 05:46:06 PM PDT 24 609179295 ps
T158 /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3148982017 Aug 05 05:47:24 PM PDT 24 Aug 05 05:47:25 PM PDT 24 50047949 ps
T612 /workspace/coverage/default/38.pwrmgr_aborted_low_power.1257457696 Aug 05 05:47:02 PM PDT 24 Aug 05 05:47:03 PM PDT 24 35147842 ps
T613 /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3504665313 Aug 05 05:46:05 PM PDT 24 Aug 05 05:46:06 PM PDT 24 40731414 ps
T614 /workspace/coverage/default/32.pwrmgr_escalation_timeout.311427486 Aug 05 05:46:49 PM PDT 24 Aug 05 05:46:50 PM PDT 24 1008668008 ps
T615 /workspace/coverage/default/13.pwrmgr_glitch.3328580201 Aug 05 05:46:07 PM PDT 24 Aug 05 05:46:08 PM PDT 24 55227417 ps
T616 /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1832445249 Aug 05 05:46:44 PM PDT 24 Aug 05 05:46:45 PM PDT 24 51679455 ps
T617 /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.632331736 Aug 05 05:46:17 PM PDT 24 Aug 05 05:46:18 PM PDT 24 98570379 ps
T618 /workspace/coverage/default/14.pwrmgr_global_esc.2815800936 Aug 05 05:46:10 PM PDT 24 Aug 05 05:46:10 PM PDT 24 29607888 ps
T619 /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.814582147 Aug 05 05:46:55 PM PDT 24 Aug 05 05:46:56 PM PDT 24 52267660 ps
T620 /workspace/coverage/default/22.pwrmgr_smoke.4093294411 Aug 05 05:47:12 PM PDT 24 Aug 05 05:47:13 PM PDT 24 138822878 ps
T621 /workspace/coverage/default/41.pwrmgr_reset_invalid.1584000158 Aug 05 05:47:04 PM PDT 24 Aug 05 05:47:05 PM PDT 24 121484286 ps
T622 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2858412983 Aug 05 05:46:30 PM PDT 24 Aug 05 05:46:31 PM PDT 24 59700656 ps
T623 /workspace/coverage/default/33.pwrmgr_escalation_timeout.1680319194 Aug 05 05:46:50 PM PDT 24 Aug 05 05:46:51 PM PDT 24 159111949 ps
T624 /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.845260673 Aug 05 05:45:35 PM PDT 24 Aug 05 05:45:36 PM PDT 24 30009341 ps
T625 /workspace/coverage/default/21.pwrmgr_reset.2042240324 Aug 05 05:46:21 PM PDT 24 Aug 05 05:46:22 PM PDT 24 152256404 ps
T159 /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3640217654 Aug 05 05:46:20 PM PDT 24 Aug 05 05:46:21 PM PDT 24 77139124 ps
T23 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3121214620 Aug 05 05:43:17 PM PDT 24 Aug 05 05:43:19 PM PDT 24 527762943 ps
T60 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2258374089 Aug 05 05:43:26 PM PDT 24 Aug 05 05:43:27 PM PDT 24 81452529 ps
T67 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2844963615 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 38122497 ps
T24 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2447661161 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:25 PM PDT 24 497013561 ps
T61 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.4208881650 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 26885670 ps
T68 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.42474366 Aug 05 05:43:17 PM PDT 24 Aug 05 05:43:18 PM PDT 24 61363471 ps
T149 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1970635421 Aug 05 05:42:52 PM PDT 24 Aug 05 05:42:56 PM PDT 24 221414172 ps
T122 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1813477479 Aug 05 05:42:56 PM PDT 24 Aug 05 05:42:57 PM PDT 24 96185910 ps
T150 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4066867834 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:57 PM PDT 24 76899375 ps
T69 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3292332458 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 124200678 ps
T25 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3230008480 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 48353067 ps
T99 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2065966758 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 22659738 ps
T53 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4177027263 Aug 05 05:43:08 PM PDT 24 Aug 05 05:43:09 PM PDT 24 38331474 ps
T54 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2643089843 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 38561405 ps
T145 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1342960696 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 25212159 ps
T56 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3224698967 Aug 05 05:43:13 PM PDT 24 Aug 05 05:43:14 PM PDT 24 71687853 ps
T75 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2310282401 Aug 05 05:43:02 PM PDT 24 Aug 05 05:43:03 PM PDT 24 96440833 ps
T147 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3026570774 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 20400743 ps
T626 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.287966948 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 27628636 ps
T100 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3746869128 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 30315944 ps
T148 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1768285273 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 46553267 ps
T58 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.879381235 Aug 05 05:43:12 PM PDT 24 Aug 05 05:43:13 PM PDT 24 43071503 ps
T57 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3943970155 Aug 05 05:43:15 PM PDT 24 Aug 05 05:43:17 PM PDT 24 461481398 ps
T89 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.229153066 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 53886025 ps
T59 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3726590650 Aug 05 05:42:56 PM PDT 24 Aug 05 05:42:58 PM PDT 24 122467652 ps
T113 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.410042557 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 16622117 ps
T76 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1933281041 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 46141162 ps
T114 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3790764583 Aug 05 05:43:18 PM PDT 24 Aug 05 05:43:19 PM PDT 24 19584998 ps
T115 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3842758070 Aug 05 05:42:57 PM PDT 24 Aug 05 05:42:58 PM PDT 24 28489840 ps
T90 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1132736789 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 264217410 ps
T101 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2077764690 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 17883141 ps
T123 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.529946852 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 131412865 ps
T102 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.346341565 Aug 05 05:43:03 PM PDT 24 Aug 05 05:43:04 PM PDT 24 18116291 ps
T103 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2454503046 Aug 05 05:43:08 PM PDT 24 Aug 05 05:43:09 PM PDT 24 62049486 ps
T146 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2082935500 Aug 05 05:43:30 PM PDT 24 Aug 05 05:43:31 PM PDT 24 43760285 ps
T627 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3307773332 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 16738758 ps
T116 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3908949456 Aug 05 05:43:12 PM PDT 24 Aug 05 05:43:13 PM PDT 24 24377294 ps
T628 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1023943756 Aug 05 05:43:32 PM PDT 24 Aug 05 05:43:33 PM PDT 24 42984970 ps
T104 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3052604673 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 27657248 ps
T74 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3584484503 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:56 PM PDT 24 194666762 ps
T629 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2374726265 Aug 05 05:43:09 PM PDT 24 Aug 05 05:43:10 PM PDT 24 16550985 ps
T630 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.93314943 Aug 05 05:43:37 PM PDT 24 Aug 05 05:43:38 PM PDT 24 22031195 ps
T72 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1083059432 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 85810427 ps
T631 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.872625462 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 17071717 ps
T632 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.4243545989 Aug 05 05:43:42 PM PDT 24 Aug 05 05:43:43 PM PDT 24 17484898 ps
T73 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3690368944 Aug 05 05:43:15 PM PDT 24 Aug 05 05:43:17 PM PDT 24 183571223 ps
T633 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1756345625 Aug 05 05:42:50 PM PDT 24 Aug 05 05:42:51 PM PDT 24 68875250 ps
T64 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1993903568 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 61346084 ps
T105 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3965020663 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 22334744 ps
T634 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.68120389 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 47239734 ps
T117 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.617984044 Aug 05 05:43:17 PM PDT 24 Aug 05 05:43:18 PM PDT 24 58377253 ps
T118 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.106572329 Aug 05 05:42:52 PM PDT 24 Aug 05 05:42:53 PM PDT 24 49734410 ps
T635 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2048180642 Aug 05 05:43:12 PM PDT 24 Aug 05 05:43:13 PM PDT 24 23830394 ps
T636 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.736095304 Aug 05 05:43:08 PM PDT 24 Aug 05 05:43:10 PM PDT 24 119983357 ps
T637 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2894347797 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 42004090 ps
T65 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1095481952 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:09 PM PDT 24 114996123 ps
T638 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1232706937 Aug 05 05:43:12 PM PDT 24 Aug 05 05:43:13 PM PDT 24 35747609 ps
T66 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3846733226 Aug 05 05:42:52 PM PDT 24 Aug 05 05:42:54 PM PDT 24 150448160 ps
T639 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2963029746 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 17476739 ps
T640 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2652189016 Aug 05 05:43:10 PM PDT 24 Aug 05 05:43:12 PM PDT 24 146316232 ps
T641 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1630810096 Aug 05 05:43:01 PM PDT 24 Aug 05 05:43:02 PM PDT 24 178023488 ps
T124 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2985995443 Aug 05 05:43:21 PM PDT 24 Aug 05 05:43:22 PM PDT 24 246935943 ps
T642 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.534039733 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:07 PM PDT 24 37453678 ps
T70 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.705673898 Aug 05 05:43:18 PM PDT 24 Aug 05 05:43:19 PM PDT 24 41210102 ps
T643 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3890887378 Aug 05 05:43:32 PM PDT 24 Aug 05 05:43:33 PM PDT 24 22881145 ps
T644 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1903533967 Aug 05 05:43:08 PM PDT 24 Aug 05 05:43:10 PM PDT 24 873064685 ps
T645 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2766771303 Aug 05 05:43:20 PM PDT 24 Aug 05 05:43:21 PM PDT 24 103819273 ps
T646 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1723752115 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:56 PM PDT 24 131568432 ps
T647 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3571385445 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 68046805 ps
T648 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1116051398 Aug 05 05:43:16 PM PDT 24 Aug 05 05:43:19 PM PDT 24 157642659 ps
T649 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.16769968 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:00 PM PDT 24 47734556 ps
T650 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1383712835 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 92553257 ps
T651 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.751166683 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:57 PM PDT 24 299202586 ps
T652 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2008646219 Aug 05 05:43:02 PM PDT 24 Aug 05 05:43:03 PM PDT 24 32985688 ps
T653 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1920245080 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:08 PM PDT 24 107562520 ps
T106 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2433346184 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:56 PM PDT 24 42703548 ps
T654 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2865935706 Aug 05 05:43:20 PM PDT 24 Aug 05 05:43:20 PM PDT 24 39149993 ps
T655 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.521615083 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 22950953 ps
T656 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.216848385 Aug 05 05:43:38 PM PDT 24 Aug 05 05:43:39 PM PDT 24 81516097 ps
T143 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.6343778 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:09 PM PDT 24 172886374 ps
T657 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.220636834 Aug 05 05:43:18 PM PDT 24 Aug 05 05:43:19 PM PDT 24 48665544 ps
T658 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3445190775 Aug 05 05:43:02 PM PDT 24 Aug 05 05:43:03 PM PDT 24 36163833 ps
T659 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3861780629 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 27239816 ps
T660 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2296376010 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:30 PM PDT 24 16073959 ps
T661 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1725818672 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 105169232 ps
T662 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.65855994 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 18887016 ps
T663 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1990596312 Aug 05 05:43:15 PM PDT 24 Aug 05 05:43:16 PM PDT 24 40466753 ps
T664 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3192234622 Aug 05 05:43:12 PM PDT 24 Aug 05 05:43:13 PM PDT 24 261334083 ps
T665 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1762575248 Aug 05 05:43:24 PM PDT 24 Aug 05 05:43:25 PM PDT 24 71500119 ps
T108 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.4023374732 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:03 PM PDT 24 136782893 ps
T107 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.350085411 Aug 05 05:43:24 PM PDT 24 Aug 05 05:43:24 PM PDT 24 28521467 ps
T666 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4187635024 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:56 PM PDT 24 212133289 ps
T667 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.566441128 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 51084507 ps
T668 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2388976515 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 20274622 ps
T669 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.979267283 Aug 05 05:43:13 PM PDT 24 Aug 05 05:43:13 PM PDT 24 53510922 ps
T109 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2028183534 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:01 PM PDT 24 196054022 ps
T670 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.756004469 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:07 PM PDT 24 17940494 ps
T671 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1447457865 Aug 05 05:42:49 PM PDT 24 Aug 05 05:42:49 PM PDT 24 26886047 ps
T672 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3811714964 Aug 05 05:43:09 PM PDT 24 Aug 05 05:43:10 PM PDT 24 35817762 ps
T673 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1747839491 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:23 PM PDT 24 25180714 ps
T674 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1557334086 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:09 PM PDT 24 226262895 ps
T675 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2744216428 Aug 05 05:43:10 PM PDT 24 Aug 05 05:43:13 PM PDT 24 140533202 ps
T676 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.356454927 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 112166850 ps
T77 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3032728902 Aug 05 05:42:51 PM PDT 24 Aug 05 05:42:53 PM PDT 24 196082563 ps
T677 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3861377095 Aug 05 05:43:01 PM PDT 24 Aug 05 05:43:03 PM PDT 24 103417479 ps
T678 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3714343590 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:24 PM PDT 24 28446719 ps
T679 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2196267189 Aug 05 05:43:18 PM PDT 24 Aug 05 05:43:19 PM PDT 24 21548512 ps
T680 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3483307416 Aug 05 05:43:20 PM PDT 24 Aug 05 05:43:21 PM PDT 24 125564635 ps
T681 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.730557626 Aug 05 05:42:57 PM PDT 24 Aug 05 05:42:58 PM PDT 24 43853242 ps
T682 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3867583969 Aug 05 05:43:02 PM PDT 24 Aug 05 05:43:03 PM PDT 24 63850868 ps
T71 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3179341627 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:24 PM PDT 24 307751628 ps
T683 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3291103388 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 27511018 ps
T684 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3179969438 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:23 PM PDT 24 36780157 ps
T685 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3630562542 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:56 PM PDT 24 60048736 ps
T686 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1983907770 Aug 05 05:43:10 PM PDT 24 Aug 05 05:43:11 PM PDT 24 38323574 ps
T687 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2974966244 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:29 PM PDT 24 27284851 ps
T144 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4080166551 Aug 05 05:42:52 PM PDT 24 Aug 05 05:42:53 PM PDT 24 533071870 ps
T688 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2520107381 Aug 05 05:43:27 PM PDT 24 Aug 05 05:43:27 PM PDT 24 40021528 ps
T689 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3035720562 Aug 05 05:42:50 PM PDT 24 Aug 05 05:42:54 PM PDT 24 272010009 ps
T690 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.104229572 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:22 PM PDT 24 23291771 ps
T691 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2781654390 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:24 PM PDT 24 91339927 ps
T692 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1950626825 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:30 PM PDT 24 57200783 ps
T693 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3407797687 Aug 05 05:42:55 PM PDT 24 Aug 05 05:42:56 PM PDT 24 66898813 ps
T694 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1843835033 Aug 05 05:43:27 PM PDT 24 Aug 05 05:43:28 PM PDT 24 20650630 ps
T695 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3035642000 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:00 PM PDT 24 17146691 ps
T696 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.599767717 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 48645610 ps
T697 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1711405754 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:01 PM PDT 24 26969738 ps
T698 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2012083384 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:08 PM PDT 24 187383438 ps
T699 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1488996489 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 20785935 ps
T700 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2679051269 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 36081858 ps
T701 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3847841659 Aug 05 05:43:23 PM PDT 24 Aug 05 05:43:25 PM PDT 24 208280365 ps
T702 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1127783009 Aug 05 05:43:16 PM PDT 24 Aug 05 05:43:17 PM PDT 24 19294113 ps
T703 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.243112867 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:30 PM PDT 24 34250103 ps
T704 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.165361435 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:08 PM PDT 24 22240284 ps
T705 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1313172962 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:30 PM PDT 24 28241645 ps
T706 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3391414800 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:56 PM PDT 24 81138046 ps
T707 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2563876442 Aug 05 05:43:37 PM PDT 24 Aug 05 05:43:37 PM PDT 24 36012848 ps
T708 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2072547049 Aug 05 05:42:54 PM PDT 24 Aug 05 05:42:55 PM PDT 24 45330544 ps
T709 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2770119664 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 40635444 ps
T710 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.835782617 Aug 05 05:43:16 PM PDT 24 Aug 05 05:43:18 PM PDT 24 227591078 ps
T711 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3780076608 Aug 05 05:43:32 PM PDT 24 Aug 05 05:43:33 PM PDT 24 51208790 ps
T712 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3981174559 Aug 05 05:43:18 PM PDT 24 Aug 05 05:43:20 PM PDT 24 121682508 ps
T112 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1008102617 Aug 05 05:43:22 PM PDT 24 Aug 05 05:43:23 PM PDT 24 17111086 ps
T78 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.38166635 Aug 05 05:43:01 PM PDT 24 Aug 05 05:43:03 PM PDT 24 196214349 ps
T110 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1454783553 Aug 05 05:42:50 PM PDT 24 Aug 05 05:42:51 PM PDT 24 24543511 ps
T111 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1281213819 Aug 05 05:43:05 PM PDT 24 Aug 05 05:43:06 PM PDT 24 16671160 ps
T713 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3088256683 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 47719595 ps
T714 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3712879830 Aug 05 05:42:56 PM PDT 24 Aug 05 05:42:57 PM PDT 24 30688628 ps
T715 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3893356964 Aug 05 05:42:56 PM PDT 24 Aug 05 05:42:57 PM PDT 24 26414734 ps
T716 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.984956095 Aug 05 05:43:17 PM PDT 24 Aug 05 05:43:18 PM PDT 24 358993856 ps
T717 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3549910213 Aug 05 05:43:00 PM PDT 24 Aug 05 05:43:01 PM PDT 24 46413051 ps
T718 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2761565174 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 18985266 ps
T719 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3819268731 Aug 05 05:43:11 PM PDT 24 Aug 05 05:43:12 PM PDT 24 82747441 ps
T720 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.622110657 Aug 05 05:43:06 PM PDT 24 Aug 05 05:43:07 PM PDT 24 21767148 ps
T721 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.480272827 Aug 05 05:43:31 PM PDT 24 Aug 05 05:43:32 PM PDT 24 73302272 ps
T722 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2771643783 Aug 05 05:43:13 PM PDT 24 Aug 05 05:43:13 PM PDT 24 32354659 ps
T723 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.580709779 Aug 05 05:43:16 PM PDT 24 Aug 05 05:43:17 PM PDT 24 42746008 ps
T724 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1816130492 Aug 05 05:43:32 PM PDT 24 Aug 05 05:43:33 PM PDT 24 19787265 ps
T725 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3465794737 Aug 05 05:43:02 PM PDT 24 Aug 05 05:43:03 PM PDT 24 143357530 ps
T726 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.882593577 Aug 05 05:42:53 PM PDT 24 Aug 05 05:42:54 PM PDT 24 201680768 ps
T727 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.487691226 Aug 05 05:43:07 PM PDT 24 Aug 05 05:43:09 PM PDT 24 95417022 ps
T728 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2725721768 Aug 05 05:43:29 PM PDT 24 Aug 05 05:43:30 PM PDT 24 16479449 ps
T729 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2555929213 Aug 05 05:43:37 PM PDT 24 Aug 05 05:43:38 PM PDT 24 28445109 ps
T79 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3158482722 Aug 05 05:43:14 PM PDT 24 Aug 05 05:43:15 PM PDT 24 236308153 ps
T730 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3276980650 Aug 05 05:43:28 PM PDT 24 Aug 05 05:43:29 PM PDT 24 20419776 ps

Test location /workspace/coverage/default/11.pwrmgr_smoke.1754483778
Short name T10
Test name
Test status
Simulation time 32133453 ps
CPU time 0.69 seconds
Started Aug 05 05:46:00 PM PDT 24
Finished Aug 05 05:46:01 PM PDT 24
Peak memory 199380 kb
Host smart-28704788-95d6-40bd-a033-4444a752abd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754483778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1754483778
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2207926880
Short name T30
Test name
Test status
Simulation time 58068209 ps
CPU time 0.79 seconds
Started Aug 05 05:47:32 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 198548 kb
Host smart-09f3ad1a-6523-4c9b-aa92-b55d4eb2f2da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207926880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2207926880
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.644590242
Short name T218
Test name
Test status
Simulation time 98650087 ps
CPU time 1.17 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:46:00 PM PDT 24
Peak memory 209544 kb
Host smart-956ff69f-a00a-437b-9896-c25656535745
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644590242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.644590242
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.836119244
Short name T2
Test name
Test status
Simulation time 1287303532 ps
CPU time 1.39 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 217576 kb
Host smart-baa97aac-efe0-4a23-9153-869151ccc730
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836119244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.836119244
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2297536576
Short name T29
Test name
Test status
Simulation time 213968134 ps
CPU time 0.84 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 200216 kb
Host smart-1ffd4ea2-26ae-463d-b88e-c25f71240d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297536576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2297536576
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2447661161
Short name T24
Test name
Test status
Simulation time 497013561 ps
CPU time 1.48 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:25 PM PDT 24
Peak memory 200692 kb
Host smart-f5fd9c4e-eee8-4940-8808-767798e9503a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447661161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2447661161
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2019527761
Short name T5
Test name
Test status
Simulation time 67203568 ps
CPU time 0.67 seconds
Started Aug 05 05:45:44 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 201436 kb
Host smart-5f2d4aa5-be1d-48f5-ba19-377cf77bc7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019527761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2019527761
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.4014449087
Short name T27
Test name
Test status
Simulation time 76651691 ps
CPU time 0.73 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:28 PM PDT 24
Peak memory 198768 kb
Host smart-f040ee9a-5429-448e-aeff-5b49a359966d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014449087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.4014449087
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1933281041
Short name T76
Test name
Test status
Simulation time 46141162 ps
CPU time 0.83 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195212 kb
Host smart-e6197f99-1a6f-4ba2-8f99-c78f02cd61de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933281041 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1933281041
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.1956492565
Short name T141
Test name
Test status
Simulation time 61785529 ps
CPU time 0.7 seconds
Started Aug 05 05:47:17 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 198324 kb
Host smart-a8199c40-4609-4a00-bbac-d74e5a982da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956492565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.1956492565
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3561744721
Short name T210
Test name
Test status
Simulation time 57474127 ps
CPU time 0.87 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 199384 kb
Host smart-e1c8a3ab-3a42-43de-8bcd-7795ec8b5429
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561744721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3561744721
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.42474366
Short name T68
Test name
Test status
Simulation time 61363471 ps
CPU time 0.61 seconds
Started Aug 05 05:43:17 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 195076 kb
Host smart-0b113044-61e8-4fc9-99e8-4a60c5e9584b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.42474366
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3689219634
Short name T12
Test name
Test status
Simulation time 37444342 ps
CPU time 0.74 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 198068 kb
Host smart-a17cec52-9ab6-4089-b55f-428af8dfde2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689219634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3689219634
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2454503046
Short name T103
Test name
Test status
Simulation time 62049486 ps
CPU time 0.68 seconds
Started Aug 05 05:43:08 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 195048 kb
Host smart-3369e972-703e-479b-b6bd-29d953feb34a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454503046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2454503046
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.2915665069
Short name T92
Test name
Test status
Simulation time 75685345 ps
CPU time 0.76 seconds
Started Aug 05 05:45:50 PM PDT 24
Finished Aug 05 05:45:51 PM PDT 24
Peak memory 198876 kb
Host smart-2e30bac2-02ee-4aec-b995-e274878fb445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915665069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2915665069
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2448920550
Short name T49
Test name
Test status
Simulation time 112685072 ps
CPU time 0.68 seconds
Started Aug 05 05:46:01 PM PDT 24
Finished Aug 05 05:46:02 PM PDT 24
Peak memory 198596 kb
Host smart-7acab19f-b2f1-460a-96b6-6076c71c7d02
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448920550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.2448920550
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1095481952
Short name T65
Test name
Test status
Simulation time 114996123 ps
CPU time 2.11 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 196312 kb
Host smart-f1a959b2-4dbd-4d8c-a899-e0ca33416c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095481952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1095481952
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.354972401
Short name T32
Test name
Test status
Simulation time 71203654 ps
CPU time 0.67 seconds
Started Aug 05 05:46:57 PM PDT 24
Finished Aug 05 05:46:57 PM PDT 24
Peak memory 198340 kb
Host smart-ce651784-9a11-4108-9b3d-2f9cad468dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354972401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disa
ble_rom_integrity_check.354972401
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.763197768
Short name T202
Test name
Test status
Simulation time 28771370 ps
CPU time 1.08 seconds
Started Aug 05 05:46:28 PM PDT 24
Finished Aug 05 05:46:30 PM PDT 24
Peak memory 200808 kb
Host smart-8d799a3f-d08d-47c9-9b73-9b875ad659b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763197768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.763197768
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1723072373
Short name T164
Test name
Test status
Simulation time 105214190 ps
CPU time 0.69 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 201408 kb
Host smart-65499ed7-3294-417d-8c83-9f2d5f668e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723072373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1723072373
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3002065462
Short name T153
Test name
Test status
Simulation time 69187725 ps
CPU time 0.71 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 198000 kb
Host smart-d41facae-1f0b-41b1-9c12-4045538218e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002065462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3002065462
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.3959267914
Short name T142
Test name
Test status
Simulation time 64671423 ps
CPU time 0.61 seconds
Started Aug 05 05:45:56 PM PDT 24
Finished Aug 05 05:45:57 PM PDT 24
Peak memory 198500 kb
Host smart-be3504d8-2d57-4d90-8dd5-9aeae780af67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959267914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.3959267914
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.39375280
Short name T21
Test name
Test status
Simulation time 43178738 ps
CPU time 0.69 seconds
Started Aug 05 05:47:26 PM PDT 24
Finished Aug 05 05:47:27 PM PDT 24
Peak memory 198488 kb
Host smart-01a2c862-279f-4c3d-b5a3-c563b5f0bf09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.39375280
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.2528019771
Short name T40
Test name
Test status
Simulation time 65212753 ps
CPU time 0.84 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:32 PM PDT 24
Peak memory 198484 kb
Host smart-bb874b9f-d352-40af-9c1a-b86a0e3487b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528019771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.2528019771
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3547720827
Short name T178
Test name
Test status
Simulation time 90857925 ps
CPU time 0.68 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 201412 kb
Host smart-a6d8e39c-bb48-4503-b4ac-4562e4d466b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547720827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3547720827
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3640217654
Short name T159
Test name
Test status
Simulation time 77139124 ps
CPU time 0.67 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:21 PM PDT 24
Peak memory 198432 kb
Host smart-5d2db379-f567-46c9-83d8-a5a203394c44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640217654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.3640217654
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3668289185
Short name T47
Test name
Test status
Simulation time 79310858 ps
CPU time 0.68 seconds
Started Aug 05 05:46:57 PM PDT 24
Finished Aug 05 05:46:58 PM PDT 24
Peak memory 201416 kb
Host smart-62a4c037-dbfe-44d8-8668-d0965bac90be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668289185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.3668289185
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3819736858
Short name T203
Test name
Test status
Simulation time 45514807 ps
CPU time 0.77 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 201436 kb
Host smart-265bb0e7-25da-4a97-add5-0bc2e67faabd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819736858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3819736858
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.492434126
Short name T127
Test name
Test status
Simulation time 323313872 ps
CPU time 0.95 seconds
Started Aug 05 05:47:13 PM PDT 24
Finished Aug 05 05:47:14 PM PDT 24
Peak memory 198640 kb
Host smart-dbad22d3-de05-4fee-bf40-0928baf776e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492434126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.492434126
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2160806389
Short name T140
Test name
Test status
Simulation time 38363824 ps
CPU time 0.69 seconds
Started Aug 05 05:45:24 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 199204 kb
Host smart-24ac2a11-b675-4ec2-b487-0c04a689bd6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160806389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2160806389
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.2543617466
Short name T169
Test name
Test status
Simulation time 159328543 ps
CPU time 0.71 seconds
Started Aug 05 05:46:01 PM PDT 24
Finished Aug 05 05:46:02 PM PDT 24
Peak memory 201180 kb
Host smart-ceb43ddf-7762-4ee0-ac1e-7f6431e03a37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543617466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.2543617466
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.371007359
Short name T166
Test name
Test status
Simulation time 42393272 ps
CPU time 0.72 seconds
Started Aug 05 05:46:04 PM PDT 24
Finished Aug 05 05:46:05 PM PDT 24
Peak memory 201488 kb
Host smart-b470d313-9e05-4e67-aa80-7309890418cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371007359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.371007359
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.1159641475
Short name T175
Test name
Test status
Simulation time 45307702 ps
CPU time 0.75 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 201440 kb
Host smart-bd73539e-bff9-4bdb-be86-a837e256c40e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159641475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.1159641475
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2858412983
Short name T622
Test name
Test status
Simulation time 59700656 ps
CPU time 0.71 seconds
Started Aug 05 05:46:30 PM PDT 24
Finished Aug 05 05:46:31 PM PDT 24
Peak memory 198348 kb
Host smart-a9fc9699-6206-4119-830e-2f44907df26c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858412983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2858412983
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.4060642211
Short name T190
Test name
Test status
Simulation time 89807271 ps
CPU time 0.68 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 201352 kb
Host smart-6f0e1700-17fc-44df-b545-70167ae7efe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060642211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.4060642211
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.38166635
Short name T78
Test name
Test status
Simulation time 196214349 ps
CPU time 1.75 seconds
Started Aug 05 05:43:01 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 195440 kb
Host smart-6522684b-d55c-4ddc-ac24-5433d983dfd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38166635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.38166635
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.6343778
Short name T143
Test name
Test status
Simulation time 172886374 ps
CPU time 1.61 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 195412 kb
Host smart-6954d901-1a03-4788-ba5e-8415f4ad70e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6343778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.6343778
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3026570774
Short name T147
Test name
Test status
Simulation time 20400743 ps
CPU time 0.61 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 195044 kb
Host smart-f36c901b-277e-49e3-9021-6d3ac09f9ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026570774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3026570774
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2142982076
Short name T494
Test name
Test status
Simulation time 66613293 ps
CPU time 0.76 seconds
Started Aug 05 05:45:24 PM PDT 24
Finished Aug 05 05:45:25 PM PDT 24
Peak memory 198576 kb
Host smart-50c667be-6317-40a2-8726-9a86ea416187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142982076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2142982076
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3371405952
Short name T466
Test name
Test status
Simulation time 83385158 ps
CPU time 0.72 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 201412 kb
Host smart-6175c7a3-549b-4d5e-84ab-1a77810f5932
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371405952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3371405952
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1200461288
Short name T186
Test name
Test status
Simulation time 40656960 ps
CPU time 0.66 seconds
Started Aug 05 05:46:13 PM PDT 24
Finished Aug 05 05:46:14 PM PDT 24
Peak memory 201352 kb
Host smart-84e21077-d350-4336-ac31-0e6faf4bcd67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200461288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1200461288
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.356380596
Short name T177
Test name
Test status
Simulation time 53886254 ps
CPU time 0.77 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 201396 kb
Host smart-d0067f61-3046-4f7b-b79b-9024f576a8f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356380596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.356380596
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3819221966
Short name T183
Test name
Test status
Simulation time 48484826 ps
CPU time 0.68 seconds
Started Aug 05 05:46:23 PM PDT 24
Finished Aug 05 05:46:24 PM PDT 24
Peak memory 201408 kb
Host smart-b8aa6550-31e6-45ec-8901-8969e90b6eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819221966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3819221966
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.3751470907
Short name T50
Test name
Test status
Simulation time 49715330 ps
CPU time 0.61 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:25 PM PDT 24
Peak memory 199188 kb
Host smart-688f017b-c74b-4013-a2ba-f9df412c7124
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751470907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.3751470907
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.2605564659
Short name T200
Test name
Test status
Simulation time 43202614 ps
CPU time 0.72 seconds
Started Aug 05 05:46:23 PM PDT 24
Finished Aug 05 05:46:24 PM PDT 24
Peak memory 201328 kb
Host smart-44b5f62a-caed-454b-bb04-262275233794
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605564659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.2605564659
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2109425718
Short name T188
Test name
Test status
Simulation time 44016099 ps
CPU time 0.72 seconds
Started Aug 05 05:46:53 PM PDT 24
Finished Aug 05 05:46:54 PM PDT 24
Peak memory 201420 kb
Host smart-2e3b5cb0-8f71-47a0-92df-22cbd76c1f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109425718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2109425718
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.1498741804
Short name T172
Test name
Test status
Simulation time 83580636 ps
CPU time 0.68 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:57 PM PDT 24
Peak memory 201388 kb
Host smart-de074582-80e1-4440-bcce-c10a2d7d3aa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498741804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.1498741804
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1238623677
Short name T9
Test name
Test status
Simulation time 56371914 ps
CPU time 0.62 seconds
Started Aug 05 05:47:10 PM PDT 24
Finished Aug 05 05:47:11 PM PDT 24
Peak memory 198568 kb
Host smart-4d7b8377-1fb7-4801-a291-dfa38b819e82
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238623677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.1238623677
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1243754195
Short name T206
Test name
Test status
Simulation time 51591515 ps
CPU time 0.77 seconds
Started Aug 05 05:47:41 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 199128 kb
Host smart-15af025a-1ac5-42a5-ba5f-ba1c23ab45b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243754195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1243754195
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3330167666
Short name T48
Test name
Test status
Simulation time 63140073 ps
CPU time 0.65 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 198244 kb
Host smart-0cd43bb5-af43-4c5d-9f0b-f7429efa73ba
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330167666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.3330167666
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2629786142
Short name T6
Test name
Test status
Simulation time 34253795 ps
CPU time 0.65 seconds
Started Aug 05 05:45:59 PM PDT 24
Finished Aug 05 05:46:00 PM PDT 24
Peak memory 198096 kb
Host smart-291f136e-d829-4240-b073-b90ec058b36c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629786142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2629786142
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.287966948
Short name T626
Test name
Test status
Simulation time 27628636 ps
CPU time 1.01 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 195084 kb
Host smart-c2e16fc8-4562-4f6c-af93-1158930be2b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287966948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.287966948
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3035720562
Short name T689
Test name
Test status
Simulation time 272010009 ps
CPU time 3.39 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 200428 kb
Host smart-0e76c44e-b780-49e5-8d10-232e84b89b56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035720562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
035720562
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1756345625
Short name T633
Test name
Test status
Simulation time 68875250 ps
CPU time 0.7 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:42:51 PM PDT 24
Peak memory 198308 kb
Host smart-8ca0928c-d62d-4d1d-b414-aa5d5024d3f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756345625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1
756345625
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2643089843
Short name T54
Test name
Test status
Simulation time 38561405 ps
CPU time 0.8 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 195284 kb
Host smart-16ff079d-bd4e-4c0d-bbad-141769b11828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643089843 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2643089843
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1454783553
Short name T110
Test name
Test status
Simulation time 24543511 ps
CPU time 0.71 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:42:51 PM PDT 24
Peak memory 197296 kb
Host smart-e6c79813-dd67-4d5a-828f-a54c55829716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454783553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1454783553
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.1447457865
Short name T671
Test name
Test status
Simulation time 26886047 ps
CPU time 0.63 seconds
Started Aug 05 05:42:49 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 195072 kb
Host smart-0c045598-208f-414f-bcef-53ef04194117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447457865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1447457865
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3842758070
Short name T115
Test name
Test status
Simulation time 28489840 ps
CPU time 0.87 seconds
Started Aug 05 05:42:57 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 195188 kb
Host smart-85d80ff8-5000-455f-9756-eec2c1d6e3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842758070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.3842758070
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.566441128
Short name T667
Test name
Test status
Simulation time 51084507 ps
CPU time 1.31 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 195560 kb
Host smart-187a23fd-f06d-429a-9a05-c0e941aa7491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566441128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.566441128
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.882593577
Short name T726
Test name
Test status
Simulation time 201680768 ps
CPU time 1.07 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 200552 kb
Host smart-16f959f7-65d8-4b66-8a58-611cc25406c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882593577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
882593577
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.730557626
Short name T681
Test name
Test status
Simulation time 43853242 ps
CPU time 0.97 seconds
Started Aug 05 05:42:57 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 198948 kb
Host smart-0c356924-810c-4091-bc4f-792be693b0dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730557626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.730557626
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1970635421
Short name T149
Test name
Test status
Simulation time 221414172 ps
CPU time 3.29 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 195288 kb
Host smart-6df1099d-92e3-4d8b-a649-612c61b5631b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970635421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.1
970635421
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3861780629
Short name T659
Test name
Test status
Simulation time 27239816 ps
CPU time 0.66 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 195208 kb
Host smart-4b572844-9917-45b6-9a21-36f4c5ff0c02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861780629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
861780629
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1083059432
Short name T72
Test name
Test status
Simulation time 85810427 ps
CPU time 1.2 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 197448 kb
Host smart-6b697580-39cc-4c62-91dc-f92519b34ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083059432 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1083059432
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3965020663
Short name T105
Test name
Test status
Simulation time 22334744 ps
CPU time 0.66 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 195140 kb
Host smart-972eddfc-da28-4235-90be-3e1d63b864b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965020663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3965020663
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.106572329
Short name T118
Test name
Test status
Simulation time 49734410 ps
CPU time 0.85 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 195164 kb
Host smart-42181445-176e-4c54-a90e-d7b1b5ac6b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106572329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.106572329
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3846733226
Short name T66
Test name
Test status
Simulation time 150448160 ps
CPU time 1.87 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 197656 kb
Host smart-c41853be-93b1-4c1a-b29c-3cddddd273f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846733226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3846733226
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3032728902
Short name T77
Test name
Test status
Simulation time 196082563 ps
CPU time 1.7 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 200644 kb
Host smart-507d6913-5f23-4032-84ab-a4764cc30027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032728902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.3032728902
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4177027263
Short name T53
Test name
Test status
Simulation time 38331474 ps
CPU time 0.77 seconds
Started Aug 05 05:43:08 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 195280 kb
Host smart-cca7442a-9754-489c-9f2a-c1744079f248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177027263 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.4177027263
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.410042557
Short name T113
Test name
Test status
Simulation time 16622117 ps
CPU time 0.63 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195164 kb
Host smart-3b6e4b08-1a7f-42b8-bacb-4833b90a61b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410042557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.410042557
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.165361435
Short name T704
Test name
Test status
Simulation time 22240284 ps
CPU time 0.65 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 195068 kb
Host smart-452cc9e3-d59d-4785-a7be-78973683652f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165361435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.165361435
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3811714964
Short name T672
Test name
Test status
Simulation time 35817762 ps
CPU time 0.86 seconds
Started Aug 05 05:43:09 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 195140 kb
Host smart-5b4a2824-ce6d-4312-a543-55ff61aa821b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811714964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3811714964
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3230008480
Short name T25
Test name
Test status
Simulation time 48353067 ps
CPU time 1.09 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 196184 kb
Host smart-16d75975-c38f-4859-8239-4df9f7d963e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230008480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3230008480
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.736095304
Short name T636
Test name
Test status
Simulation time 119983357 ps
CPU time 1.11 seconds
Started Aug 05 05:43:08 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 200392 kb
Host smart-c3b8557b-e1b2-4aff-8278-255a1108bb95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736095304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.736095304
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.879381235
Short name T58
Test name
Test status
Simulation time 43071503 ps
CPU time 1.04 seconds
Started Aug 05 05:43:12 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 200584 kb
Host smart-16f92ad5-9250-4139-aa72-df52362751ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879381235 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.879381235
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3908949456
Short name T116
Test name
Test status
Simulation time 24377294 ps
CPU time 0.71 seconds
Started Aug 05 05:43:12 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 195188 kb
Host smart-235b9635-ac61-4b82-ba19-4563ad4cb108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908949456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3908949456
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2374726265
Short name T629
Test name
Test status
Simulation time 16550985 ps
CPU time 0.6 seconds
Started Aug 05 05:43:09 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 195072 kb
Host smart-3664fc98-8d41-4971-b884-e135666859b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374726265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2374726265
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1232706937
Short name T638
Test name
Test status
Simulation time 35747609 ps
CPU time 0.88 seconds
Started Aug 05 05:43:12 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 199932 kb
Host smart-e8df9284-9399-442e-ad3f-71d41fafa674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232706937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1232706937
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3192234622
Short name T664
Test name
Test status
Simulation time 261334083 ps
CPU time 1.52 seconds
Started Aug 05 05:43:12 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 195580 kb
Host smart-67ce5db0-35dc-4a68-bc8b-e52a0b6377d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192234622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3192234622
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3158482722
Short name T79
Test name
Test status
Simulation time 236308153 ps
CPU time 1.59 seconds
Started Aug 05 05:43:14 PM PDT 24
Finished Aug 05 05:43:15 PM PDT 24
Peak memory 195412 kb
Host smart-d5726be0-0d23-4d6b-a1b8-de71f931f834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158482722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.3158482722
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3224698967
Short name T56
Test name
Test status
Simulation time 71687853 ps
CPU time 0.99 seconds
Started Aug 05 05:43:13 PM PDT 24
Finished Aug 05 05:43:14 PM PDT 24
Peak memory 195280 kb
Host smart-abceda1a-a0a7-41bc-b5a8-1242c375b9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224698967 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3224698967
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2771643783
Short name T722
Test name
Test status
Simulation time 32354659 ps
CPU time 0.66 seconds
Started Aug 05 05:43:13 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 195136 kb
Host smart-5bd6ef0b-4ad2-4aa7-b261-ba86004efb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771643783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2771643783
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.979267283
Short name T669
Test name
Test status
Simulation time 53510922 ps
CPU time 0.64 seconds
Started Aug 05 05:43:13 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 195108 kb
Host smart-000b722d-6427-4cb1-95de-5a5069d8275c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979267283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.979267283
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3819268731
Short name T719
Test name
Test status
Simulation time 82747441 ps
CPU time 0.75 seconds
Started Aug 05 05:43:11 PM PDT 24
Finished Aug 05 05:43:12 PM PDT 24
Peak memory 195204 kb
Host smart-20cac700-f44a-4c56-9de5-a4d4e1955fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819268731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3819268731
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2652189016
Short name T640
Test name
Test status
Simulation time 146316232 ps
CPU time 1.8 seconds
Started Aug 05 05:43:10 PM PDT 24
Finished Aug 05 05:43:12 PM PDT 24
Peak memory 197568 kb
Host smart-1338f55f-addf-4461-bacb-b2fe91034b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652189016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2652189016
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3690368944
Short name T73
Test name
Test status
Simulation time 183571223 ps
CPU time 1.72 seconds
Started Aug 05 05:43:15 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 195380 kb
Host smart-85ede330-b511-4556-a072-5f0d5c930579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690368944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.3690368944
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.220636834
Short name T657
Test name
Test status
Simulation time 48665544 ps
CPU time 1.36 seconds
Started Aug 05 05:43:18 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 197552 kb
Host smart-7d565557-1122-457c-aef9-7187c5b4a8f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220636834 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.220636834
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3790764583
Short name T114
Test name
Test status
Simulation time 19584998 ps
CPU time 0.71 seconds
Started Aug 05 05:43:18 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 197284 kb
Host smart-8816cdae-5fd9-4c83-8362-6889077bc573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790764583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3790764583
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2048180642
Short name T635
Test name
Test status
Simulation time 23830394 ps
CPU time 0.62 seconds
Started Aug 05 05:43:12 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 195076 kb
Host smart-40b28990-6e6e-4c35-a7a1-5f74fa9c6d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048180642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2048180642
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3483307416
Short name T680
Test name
Test status
Simulation time 125564635 ps
CPU time 0.75 seconds
Started Aug 05 05:43:20 PM PDT 24
Finished Aug 05 05:43:21 PM PDT 24
Peak memory 195204 kb
Host smart-98678684-b783-4265-8c64-0018bff1440c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483307416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3483307416
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2744216428
Short name T675
Test name
Test status
Simulation time 140533202 ps
CPU time 2.68 seconds
Started Aug 05 05:43:10 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 197568 kb
Host smart-06d15e21-3b73-4304-87ea-36ab045ae329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744216428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2744216428
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3943970155
Short name T57
Test name
Test status
Simulation time 461481398 ps
CPU time 1.81 seconds
Started Aug 05 05:43:15 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 195416 kb
Host smart-e9abc059-3c7c-43e2-a634-a2328f0012b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943970155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3943970155
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.705673898
Short name T70
Test name
Test status
Simulation time 41210102 ps
CPU time 1.18 seconds
Started Aug 05 05:43:18 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 200584 kb
Host smart-6bb95b06-938d-4627-b3a7-7fc067b2cff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705673898 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.705673898
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2196267189
Short name T679
Test name
Test status
Simulation time 21548512 ps
CPU time 0.68 seconds
Started Aug 05 05:43:18 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 196400 kb
Host smart-c98b3dc3-f878-446b-b434-433f33a8d939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196267189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.2196267189
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.104229572
Short name T690
Test name
Test status
Simulation time 23291771 ps
CPU time 0.64 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:22 PM PDT 24
Peak memory 195076 kb
Host smart-6bf532f5-bb3f-40db-b7a6-9d6dfe0292d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104229572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.104229572
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.617984044
Short name T117
Test name
Test status
Simulation time 58377253 ps
CPU time 0.76 seconds
Started Aug 05 05:43:17 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 195140 kb
Host smart-8809f286-dcfa-4092-b70b-6e3ed3aef1ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617984044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.617984044
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1990596312
Short name T663
Test name
Test status
Simulation time 40466753 ps
CPU time 1.07 seconds
Started Aug 05 05:43:15 PM PDT 24
Finished Aug 05 05:43:16 PM PDT 24
Peak memory 195576 kb
Host smart-a6b03f01-d758-4756-9213-eb253fd663a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990596312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1990596312
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.984956095
Short name T716
Test name
Test status
Simulation time 358993856 ps
CPU time 1.2 seconds
Started Aug 05 05:43:17 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 200676 kb
Host smart-b40a5a63-8191-4eb5-89bb-bfeedfd99dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984956095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.984956095
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2865935706
Short name T654
Test name
Test status
Simulation time 39149993 ps
CPU time 0.81 seconds
Started Aug 05 05:43:20 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 195300 kb
Host smart-5f32c146-9921-44a8-952f-cbd915653ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865935706 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2865935706
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1127783009
Short name T702
Test name
Test status
Simulation time 19294113 ps
CPU time 0.64 seconds
Started Aug 05 05:43:16 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 195180 kb
Host smart-6371ddd5-c54c-4e58-95f4-cf8ce342e76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127783009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1127783009
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.580709779
Short name T723
Test name
Test status
Simulation time 42746008 ps
CPU time 0.75 seconds
Started Aug 05 05:43:16 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 197396 kb
Host smart-09a31c69-d648-4271-8758-2dd437c0e3b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580709779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.580709779
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3981174559
Short name T712
Test name
Test status
Simulation time 121682508 ps
CPU time 2.41 seconds
Started Aug 05 05:43:18 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 197376 kb
Host smart-c2c289c2-f5a1-45ef-9ec4-6f2e84d5f4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981174559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3981174559
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3121214620
Short name T23
Test name
Test status
Simulation time 527762943 ps
CPU time 1.13 seconds
Started Aug 05 05:43:17 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 195208 kb
Host smart-f2505c21-795a-4d06-a9c2-3fc27a412622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121214620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3121214620
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.229153066
Short name T89
Test name
Test status
Simulation time 53886025 ps
CPU time 0.8 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195292 kb
Host smart-0911d9c8-6cff-40b6-b32e-99c9f56c0bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229153066 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.229153066
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1008102617
Short name T112
Test name
Test status
Simulation time 17111086 ps
CPU time 0.69 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:23 PM PDT 24
Peak memory 195152 kb
Host smart-27bbe2e4-2db8-40de-ad0f-b14ffa5a010f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008102617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1008102617
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1342960696
Short name T145
Test name
Test status
Simulation time 25212159 ps
CPU time 0.64 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195092 kb
Host smart-297aaaf7-d215-4a54-a916-1ab0db41a123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342960696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1342960696
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1747839491
Short name T673
Test name
Test status
Simulation time 25180714 ps
CPU time 0.78 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:23 PM PDT 24
Peak memory 195184 kb
Host smart-feed6b07-de0a-4ede-8db7-75bf4ddcddcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747839491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1747839491
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1116051398
Short name T648
Test name
Test status
Simulation time 157642659 ps
CPU time 2.42 seconds
Started Aug 05 05:43:16 PM PDT 24
Finished Aug 05 05:43:19 PM PDT 24
Peak memory 197464 kb
Host smart-a49f2fa8-5670-4ad1-9ee0-ee41910a05c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116051398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1116051398
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.835782617
Short name T710
Test name
Test status
Simulation time 227591078 ps
CPU time 1.57 seconds
Started Aug 05 05:43:16 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 200432 kb
Host smart-d705e759-9893-4eb7-bcc8-707331a69ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835782617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.835782617
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1132736789
Short name T90
Test name
Test status
Simulation time 264217410 ps
CPU time 0.92 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195224 kb
Host smart-ecad25dc-78d5-4288-821f-d43f8d12a4d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132736789 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1132736789
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2077764690
Short name T101
Test name
Test status
Simulation time 17883141 ps
CPU time 0.65 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195156 kb
Host smart-faf262ea-9cde-433d-bc15-dc8efb11d46f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077764690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2077764690
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3179969438
Short name T684
Test name
Test status
Simulation time 36780157 ps
CPU time 0.63 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:23 PM PDT 24
Peak memory 195012 kb
Host smart-ce45794a-018a-468e-89ac-cc0414454a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179969438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3179969438
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2985995443
Short name T124
Test name
Test status
Simulation time 246935943 ps
CPU time 0.89 seconds
Started Aug 05 05:43:21 PM PDT 24
Finished Aug 05 05:43:22 PM PDT 24
Peak memory 198440 kb
Host smart-83832be6-a7c0-44dc-b806-239d90e81c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985995443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2985995443
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2781654390
Short name T691
Test name
Test status
Simulation time 91339927 ps
CPU time 1.99 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 196484 kb
Host smart-eb5ee0eb-cc8c-4d5b-97e7-165efb37d9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781654390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2781654390
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3179341627
Short name T71
Test name
Test status
Simulation time 307751628 ps
CPU time 1.53 seconds
Started Aug 05 05:43:22 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195428 kb
Host smart-b82f506b-d9a3-42e6-950b-9e9d17832096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179341627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3179341627
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.480272827
Short name T721
Test name
Test status
Simulation time 73302272 ps
CPU time 1.02 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 195348 kb
Host smart-a19e07e2-ef8f-44b8-9d85-82598d05a211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480272827 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.480272827
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.350085411
Short name T107
Test name
Test status
Simulation time 28521467 ps
CPU time 0.64 seconds
Started Aug 05 05:43:24 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 197248 kb
Host smart-124720ac-a85d-47db-95a2-2d8fca05f4df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350085411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.350085411
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2388976515
Short name T668
Test name
Test status
Simulation time 20274622 ps
CPU time 0.63 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 195072 kb
Host smart-a88bad89-1211-45aa-b857-5ba37a1e02ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388976515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2388976515
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2766771303
Short name T645
Test name
Test status
Simulation time 103819273 ps
CPU time 0.81 seconds
Started Aug 05 05:43:20 PM PDT 24
Finished Aug 05 05:43:21 PM PDT 24
Peak memory 195140 kb
Host smart-2ed83806-8522-48c9-8d12-4d9ffd37e3dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766771303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2766771303
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3714343590
Short name T678
Test name
Test status
Simulation time 28446719 ps
CPU time 1.13 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 196636 kb
Host smart-e1cce690-73a7-47ce-97d6-d57bdc4af33c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714343590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.3714343590
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3847841659
Short name T701
Test name
Test status
Simulation time 208280365 ps
CPU time 1.69 seconds
Started Aug 05 05:43:23 PM PDT 24
Finished Aug 05 05:43:25 PM PDT 24
Peak memory 200584 kb
Host smart-0e4214c1-d0e5-48df-8294-31cd1920b038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847841659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3847841659
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.216848385
Short name T656
Test name
Test status
Simulation time 81516097 ps
CPU time 0.98 seconds
Started Aug 05 05:43:38 PM PDT 24
Finished Aug 05 05:43:39 PM PDT 24
Peak memory 200616 kb
Host smart-4a5f32d9-ea71-4c86-bc1e-c4eea457707f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216848385 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.216848385
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3746869128
Short name T100
Test name
Test status
Simulation time 30315944 ps
CPU time 0.65 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 197676 kb
Host smart-68ebbeb3-6cf6-4b96-8dc7-7432c8904576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746869128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3746869128
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2563876442
Short name T707
Test name
Test status
Simulation time 36012848 ps
CPU time 0.65 seconds
Started Aug 05 05:43:37 PM PDT 24
Finished Aug 05 05:43:37 PM PDT 24
Peak memory 195120 kb
Host smart-08657cde-bf89-4f57-ab9d-5a5097130a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563876442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.2563876442
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2258374089
Short name T60
Test name
Test status
Simulation time 81452529 ps
CPU time 0.84 seconds
Started Aug 05 05:43:26 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 198412 kb
Host smart-38acdf1b-83c2-4469-af36-849e03522b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258374089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.2258374089
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1762575248
Short name T665
Test name
Test status
Simulation time 71500119 ps
CPU time 1.53 seconds
Started Aug 05 05:43:24 PM PDT 24
Finished Aug 05 05:43:25 PM PDT 24
Peak memory 197464 kb
Host smart-764c1ec3-19bc-4931-921d-838dcd025a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762575248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1762575248
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1813477479
Short name T122
Test name
Test status
Simulation time 96185910 ps
CPU time 1.06 seconds
Started Aug 05 05:42:56 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 198996 kb
Host smart-653752a5-cbfb-472c-947b-33cea0bea7c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813477479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1
813477479
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3391414800
Short name T706
Test name
Test status
Simulation time 81138046 ps
CPU time 1.74 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 195260 kb
Host smart-994f5dcd-48cd-41dc-acb3-cc8f2d60ec88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391414800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
391414800
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3893356964
Short name T715
Test name
Test status
Simulation time 26414734 ps
CPU time 0.66 seconds
Started Aug 05 05:42:56 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 197648 kb
Host smart-77c8a485-a245-4f19-89b1-f86ce6f3000c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893356964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
893356964
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3571385445
Short name T647
Test name
Test status
Simulation time 68046805 ps
CPU time 0.86 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 195268 kb
Host smart-c7bfb47b-b6a6-4783-af63-2cc389463c5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571385445 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.3571385445
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2433346184
Short name T106
Test name
Test status
Simulation time 42703548 ps
CPU time 0.67 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 197488 kb
Host smart-c0b7f869-4f72-4dd0-ab69-595c8465c92b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433346184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2433346184
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1383712835
Short name T650
Test name
Test status
Simulation time 92553257 ps
CPU time 0.63 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 195088 kb
Host smart-a810916b-f106-447d-ba0a-0a22befe734c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383712835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1383712835
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3712879830
Short name T714
Test name
Test status
Simulation time 30688628 ps
CPU time 0.8 seconds
Started Aug 05 05:42:56 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 195064 kb
Host smart-2f34c2dc-de37-4ee0-924f-2ea8d4b8651c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712879830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.3712879830
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1723752115
Short name T646
Test name
Test status
Simulation time 131568432 ps
CPU time 1.68 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 196488 kb
Host smart-d2435a13-1283-4679-944f-18eb27e025a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723752115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1723752115
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4080166551
Short name T144
Test name
Test status
Simulation time 533071870 ps
CPU time 1.43 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 195416 kb
Host smart-2c28bdcc-7406-4daf-b20d-54217a2c674d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080166551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.4080166551
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1023943756
Short name T628
Test name
Test status
Simulation time 42984970 ps
CPU time 0.63 seconds
Started Aug 05 05:43:32 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 195016 kb
Host smart-3c576fbe-050e-46e4-ab43-1c41377bf67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023943756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1023943756
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.65855994
Short name T662
Test name
Test status
Simulation time 18887016 ps
CPU time 0.62 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195092 kb
Host smart-37345a66-5ca0-49d8-83c2-b03567f2690c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65855994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.65855994
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2679051269
Short name T700
Test name
Test status
Simulation time 36081858 ps
CPU time 0.59 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 194696 kb
Host smart-d60215ba-6d28-475f-91f4-3981a7e9ca59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679051269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2679051269
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1816130492
Short name T724
Test name
Test status
Simulation time 19787265 ps
CPU time 0.63 seconds
Started Aug 05 05:43:32 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 195072 kb
Host smart-a556b184-f476-4b8b-97d3-1e10b7760468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816130492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1816130492
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2963029746
Short name T639
Test name
Test status
Simulation time 17476739 ps
CPU time 0.64 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195068 kb
Host smart-b87b4532-1966-4e9f-839b-cf90d4ff9f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963029746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2963029746
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3890887378
Short name T643
Test name
Test status
Simulation time 22881145 ps
CPU time 0.64 seconds
Started Aug 05 05:43:32 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 195088 kb
Host smart-6437461b-b65a-4992-8d66-628750b8dd33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890887378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3890887378
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.4243545989
Short name T632
Test name
Test status
Simulation time 17484898 ps
CPU time 0.59 seconds
Started Aug 05 05:43:42 PM PDT 24
Finished Aug 05 05:43:43 PM PDT 24
Peak memory 195120 kb
Host smart-469a9e15-d0a3-4a81-873b-93d4e5ef1cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243545989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.4243545989
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1843835033
Short name T694
Test name
Test status
Simulation time 20650630 ps
CPU time 0.61 seconds
Started Aug 05 05:43:27 PM PDT 24
Finished Aug 05 05:43:28 PM PDT 24
Peak memory 195292 kb
Host smart-95f04908-35fe-4b1c-9a16-36a1394605fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843835033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.1843835033
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3291103388
Short name T683
Test name
Test status
Simulation time 27511018 ps
CPU time 0.65 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 195072 kb
Host smart-45485aeb-03e0-42d8-9c38-60cc10162fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291103388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3291103388
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1950626825
Short name T692
Test name
Test status
Simulation time 57200783 ps
CPU time 0.6 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 195060 kb
Host smart-f8734a33-4fec-4776-a022-f50fad933d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950626825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1950626825
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4187635024
Short name T666
Test name
Test status
Simulation time 212133289 ps
CPU time 0.97 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 198772 kb
Host smart-5bbefcfd-1ca9-47b0-b131-617fd53aa464
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187635024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.4
187635024
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4066867834
Short name T150
Test name
Test status
Simulation time 76899375 ps
CPU time 1.71 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 198944 kb
Host smart-30184ea0-c997-452e-9c83-8a5b1c85e35e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066867834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.4
066867834
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3052604673
Short name T104
Test name
Test status
Simulation time 27657248 ps
CPU time 0.72 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 197336 kb
Host smart-70e5360b-799d-4864-899c-cf49b5e4b1f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052604673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
052604673
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2072547049
Short name T708
Test name
Test status
Simulation time 45330544 ps
CPU time 0.89 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 200592 kb
Host smart-74e21d4b-6bca-4924-984c-5f808b207fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072547049 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2072547049
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3407797687
Short name T693
Test name
Test status
Simulation time 66898813 ps
CPU time 0.66 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 197216 kb
Host smart-bc1daff6-360c-41e9-826e-0c0b5e2c7cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407797687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3407797687
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3630562542
Short name T685
Test name
Test status
Simulation time 60048736 ps
CPU time 0.64 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 195072 kb
Host smart-bd4e3900-dd98-48f3-b2ef-b3a70e35a8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630562542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3630562542
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2894347797
Short name T637
Test name
Test status
Simulation time 42004090 ps
CPU time 0.95 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 195316 kb
Host smart-c48cd61f-d957-49eb-95fb-2979f74477ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894347797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.2894347797
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3726590650
Short name T59
Test name
Test status
Simulation time 122467652 ps
CPU time 2.43 seconds
Started Aug 05 05:42:56 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 196564 kb
Host smart-57fb4de9-0711-4999-8bd0-83f926a4d464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726590650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3726590650
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3584484503
Short name T74
Test name
Test status
Simulation time 194666762 ps
CPU time 1.79 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 200536 kb
Host smart-a6ad3336-bcd1-47b3-9106-4ea65df4dc2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584484503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3584484503
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2770119664
Short name T709
Test name
Test status
Simulation time 40635444 ps
CPU time 0.6 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195088 kb
Host smart-da2f513f-adf6-4802-b3bf-4985d5660d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770119664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.2770119664
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2296376010
Short name T660
Test name
Test status
Simulation time 16073959 ps
CPU time 0.61 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 195076 kb
Host smart-667f6cc1-d3e0-44c7-996e-168fa7057a90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296376010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2296376010
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2520107381
Short name T688
Test name
Test status
Simulation time 40021528 ps
CPU time 0.58 seconds
Started Aug 05 05:43:27 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 195092 kb
Host smart-5f3675ca-4f65-49ad-84ed-6a16063d5bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520107381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2520107381
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2844963615
Short name T67
Test name
Test status
Simulation time 38122497 ps
CPU time 0.58 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 194696 kb
Host smart-2bde5b1d-1578-4725-8048-17e379546a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844963615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2844963615
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1313172962
Short name T705
Test name
Test status
Simulation time 28241645 ps
CPU time 0.64 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 195160 kb
Host smart-5a7182f7-99b8-4ffa-9b04-472cc8221e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313172962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1313172962
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2974966244
Short name T687
Test name
Test status
Simulation time 27284851 ps
CPU time 0.62 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195076 kb
Host smart-d29c5444-398f-4aa8-97a9-0f9d6d3955a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974966244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2974966244
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3088256683
Short name T713
Test name
Test status
Simulation time 47719595 ps
CPU time 0.64 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 195076 kb
Host smart-0bcbf544-91e4-401a-ac57-55a778ddb2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088256683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3088256683
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1768285273
Short name T148
Test name
Test status
Simulation time 46553267 ps
CPU time 0.59 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195064 kb
Host smart-a9983427-85b3-4f19-be28-58de53e0bfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768285273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1768285273
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3276980650
Short name T730
Test name
Test status
Simulation time 20419776 ps
CPU time 0.61 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195072 kb
Host smart-54ecd009-daed-4c82-98bb-9ca42a2f019f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276980650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3276980650
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2082935500
Short name T146
Test name
Test status
Simulation time 43760285 ps
CPU time 0.62 seconds
Started Aug 05 05:43:30 PM PDT 24
Finished Aug 05 05:43:31 PM PDT 24
Peak memory 195092 kb
Host smart-a797191d-c500-413b-bcf6-5b3079253ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082935500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2082935500
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2028183534
Short name T109
Test name
Test status
Simulation time 196054022 ps
CPU time 0.96 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 199076 kb
Host smart-d0256c94-7434-49b7-99d8-d48690f0008d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028183534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2
028183534
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.4023374732
Short name T108
Test name
Test status
Simulation time 136782893 ps
CPU time 2.67 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 195260 kb
Host smart-ac1ea923-77b8-4c98-a690-8976071d8576
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023374732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.4
023374732
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3549910213
Short name T717
Test name
Test status
Simulation time 46413051 ps
CPU time 0.65 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 195148 kb
Host smart-9d4620f8-cfad-46a4-b745-cc931e137816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549910213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
549910213
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2310282401
Short name T75
Test name
Test status
Simulation time 96440833 ps
CPU time 0.88 seconds
Started Aug 05 05:43:02 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 195284 kb
Host smart-f16ccee1-6faa-4aae-a28d-a343d20eff1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310282401 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2310282401
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.4208881650
Short name T61
Test name
Test status
Simulation time 26885670 ps
CPU time 0.61 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 195140 kb
Host smart-2a93abed-a315-4742-972c-1694f68bcb47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208881650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4208881650
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1711405754
Short name T697
Test name
Test status
Simulation time 26969738 ps
CPU time 0.63 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 195004 kb
Host smart-03aecc24-0603-4b81-b75c-3603d5aa646e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711405754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1711405754
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2008646219
Short name T652
Test name
Test status
Simulation time 32985688 ps
CPU time 0.73 seconds
Started Aug 05 05:43:02 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 197376 kb
Host smart-c0414a30-be2e-405d-9131-fcade2b0c808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008646219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.2008646219
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.751166683
Short name T651
Test name
Test status
Simulation time 299202586 ps
CPU time 1.72 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 196384 kb
Host smart-70566d3e-942a-4133-b05d-35ff83582cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751166683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.751166683
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.356454927
Short name T676
Test name
Test status
Simulation time 112166850 ps
CPU time 1.13 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 199888 kb
Host smart-f1b9a600-c5e2-4b58-a5ee-387e3662d503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356454927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
356454927
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.93314943
Short name T630
Test name
Test status
Simulation time 22031195 ps
CPU time 0.64 seconds
Started Aug 05 05:43:37 PM PDT 24
Finished Aug 05 05:43:38 PM PDT 24
Peak memory 195104 kb
Host smart-b51ae105-a721-411f-8d7d-c2cafdf533ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93314943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.93314943
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.872625462
Short name T631
Test name
Test status
Simulation time 17071717 ps
CPU time 0.63 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195072 kb
Host smart-5e150f3a-5f74-47d3-b53a-e6c73f003eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872625462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.872625462
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.68120389
Short name T634
Test name
Test status
Simulation time 47239734 ps
CPU time 0.63 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 195072 kb
Host smart-fc23f19f-b3f5-4e08-ac6a-b1dc2293ebdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68120389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.68120389
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2555929213
Short name T729
Test name
Test status
Simulation time 28445109 ps
CPU time 0.63 seconds
Started Aug 05 05:43:37 PM PDT 24
Finished Aug 05 05:43:38 PM PDT 24
Peak memory 195124 kb
Host smart-769d7b2b-04aa-4288-bba9-e47ed5b38a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555929213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2555929213
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2761565174
Short name T718
Test name
Test status
Simulation time 18985266 ps
CPU time 0.62 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195068 kb
Host smart-15509f7d-4909-4ee3-949b-6b78d25da1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761565174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2761565174
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3780076608
Short name T711
Test name
Test status
Simulation time 51208790 ps
CPU time 0.67 seconds
Started Aug 05 05:43:32 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 195016 kb
Host smart-9876131b-91d5-4844-961d-0b8143d6d7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780076608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3780076608
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.521615083
Short name T655
Test name
Test status
Simulation time 22950953 ps
CPU time 0.61 seconds
Started Aug 05 05:43:28 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 195044 kb
Host smart-32740331-a1bf-4566-8f1c-7ae94964d9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521615083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.521615083
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.243112867
Short name T703
Test name
Test status
Simulation time 34250103 ps
CPU time 0.62 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 195072 kb
Host smart-73151c8e-38aa-46c2-8e5d-d4316827cbb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243112867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.243112867
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.2725721768
Short name T728
Test name
Test status
Simulation time 16479449 ps
CPU time 0.66 seconds
Started Aug 05 05:43:29 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 195092 kb
Host smart-b9593546-65e5-4794-be75-6a26b9c92627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725721768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2725721768
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3292332458
Short name T69
Test name
Test status
Simulation time 124200678 ps
CPU time 0.64 seconds
Started Aug 05 05:43:31 PM PDT 24
Finished Aug 05 05:43:32 PM PDT 24
Peak memory 195088 kb
Host smart-0abb5874-939d-488a-84e9-13496215f769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292332458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3292332458
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3445190775
Short name T658
Test name
Test status
Simulation time 36163833 ps
CPU time 0.81 seconds
Started Aug 05 05:43:02 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 195296 kb
Host smart-4421b006-9b27-4092-aba0-a79a08215fec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445190775 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3445190775
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.346341565
Short name T102
Test name
Test status
Simulation time 18116291 ps
CPU time 0.68 seconds
Started Aug 05 05:43:03 PM PDT 24
Finished Aug 05 05:43:04 PM PDT 24
Peak memory 195156 kb
Host smart-b26fadce-d865-4c8d-be53-fc9c1878c6b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346341565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.346341565
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3035642000
Short name T695
Test name
Test status
Simulation time 17146691 ps
CPU time 0.62 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:00 PM PDT 24
Peak memory 195088 kb
Host smart-3c4ebdae-ec31-48fb-bdd8-4e8e9c2ddfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035642000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3035642000
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.599767717
Short name T696
Test name
Test status
Simulation time 48645610 ps
CPU time 0.7 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 197364 kb
Host smart-f250df1f-82f6-41d3-8714-434dc696c08e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599767717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sam
e_csr_outstanding.599767717
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3861377095
Short name T677
Test name
Test status
Simulation time 103417479 ps
CPU time 1.81 seconds
Started Aug 05 05:43:01 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 200748 kb
Host smart-97717009-2bab-46ab-a464-c3f77fa7bf60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861377095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3861377095
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1993903568
Short name T64
Test name
Test status
Simulation time 61346084 ps
CPU time 0.93 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 200572 kb
Host smart-2e649c0c-9e66-49b4-850a-8226a101c538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993903568 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1993903568
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.534039733
Short name T642
Test name
Test status
Simulation time 37453678 ps
CPU time 0.68 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 197216 kb
Host smart-f77f8c1a-6a5b-4e01-a0d9-1de9c9c817f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534039733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.534039733
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3867583969
Short name T682
Test name
Test status
Simulation time 63850868 ps
CPU time 0.62 seconds
Started Aug 05 05:43:02 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 195072 kb
Host smart-0cc1a63c-1227-4916-84cb-a5d0c8c322f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867583969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3867583969
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.16769968
Short name T649
Test name
Test status
Simulation time 47734556 ps
CPU time 0.71 seconds
Started Aug 05 05:43:00 PM PDT 24
Finished Aug 05 05:43:00 PM PDT 24
Peak memory 195156 kb
Host smart-5bcce097-017a-48ae-b57c-5c234c7d3095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same
_csr_outstanding.16769968
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3465794737
Short name T725
Test name
Test status
Simulation time 143357530 ps
CPU time 1.16 seconds
Started Aug 05 05:43:02 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 197260 kb
Host smart-d2333266-7c92-4936-826d-ec3ea06a81fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465794737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3465794737
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1630810096
Short name T641
Test name
Test status
Simulation time 178023488 ps
CPU time 1.06 seconds
Started Aug 05 05:43:01 PM PDT 24
Finished Aug 05 05:43:02 PM PDT 24
Peak memory 195160 kb
Host smart-653d6c14-a461-4c26-a0cd-f3ff9bec682c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630810096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1630810096
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1920245080
Short name T653
Test name
Test status
Simulation time 107562520 ps
CPU time 1.33 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 197996 kb
Host smart-4f93b533-3777-408a-ada0-8fee65f0af23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920245080 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1920245080
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2065966758
Short name T99
Test name
Test status
Simulation time 22659738 ps
CPU time 0.77 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 197308 kb
Host smart-9b7cdf15-f754-456a-9ffd-1b408dd16cb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065966758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2065966758
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.622110657
Short name T720
Test name
Test status
Simulation time 21767148 ps
CPU time 0.65 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195064 kb
Host smart-7da08e28-268c-4c16-bef9-09ae120cbd85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622110657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.622110657
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1488996489
Short name T699
Test name
Test status
Simulation time 20785935 ps
CPU time 0.75 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195140 kb
Host smart-d4745e8c-27bb-4b82-a42d-49e28e63c429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488996489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1488996489
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1725818672
Short name T661
Test name
Test status
Simulation time 105169232 ps
CPU time 1.27 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 196292 kb
Host smart-699c132c-da52-488b-8a66-09999d01a3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725818672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1725818672
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.529946852
Short name T123
Test name
Test status
Simulation time 131412865 ps
CPU time 0.82 seconds
Started Aug 05 05:43:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195300 kb
Host smart-01aa15e1-6e38-4fd8-9be4-b0c8cf6a12c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529946852 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.529946852
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.756004469
Short name T670
Test name
Test status
Simulation time 17940494 ps
CPU time 0.61 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 195064 kb
Host smart-9593bb2a-70d2-4afc-aba5-ef37a8f36304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756004469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.756004469
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2012083384
Short name T698
Test name
Test status
Simulation time 187383438 ps
CPU time 0.91 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 198580 kb
Host smart-d567a5cf-25ac-4433-8554-1939177ce43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012083384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2012083384
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.487691226
Short name T727
Test name
Test status
Simulation time 95417022 ps
CPU time 1.97 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 197520 kb
Host smart-45d0ce51-18e6-423d-b009-9160b85e8c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487691226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.487691226
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1557334086
Short name T674
Test name
Test status
Simulation time 226262895 ps
CPU time 1.12 seconds
Started Aug 05 05:43:07 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 195360 kb
Host smart-75fd4233-f334-47f6-a3b8-ad9659314fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557334086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.1557334086
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1281213819
Short name T111
Test name
Test status
Simulation time 16671160 ps
CPU time 0.63 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 197320 kb
Host smart-49c7ea3b-eed7-4957-af66-1b6b5e9ff454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281213819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1281213819
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3307773332
Short name T627
Test name
Test status
Simulation time 16738758 ps
CPU time 0.65 seconds
Started Aug 05 05:43:05 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 195092 kb
Host smart-0e7be4d1-ce70-48ee-b27d-3948727a4a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307773332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3307773332
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1983907770
Short name T686
Test name
Test status
Simulation time 38323574 ps
CPU time 0.93 seconds
Started Aug 05 05:43:10 PM PDT 24
Finished Aug 05 05:43:11 PM PDT 24
Peak memory 198716 kb
Host smart-a6977b45-5f43-4ab8-abb9-b91f5c9911ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983907770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.1983907770
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1903533967
Short name T644
Test name
Test status
Simulation time 873064685 ps
CPU time 1.53 seconds
Started Aug 05 05:43:08 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 195408 kb
Host smart-327199d7-985e-46a6-9ef2-fb6c45f95186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903533967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1903533967
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3583933577
Short name T85
Test name
Test status
Simulation time 57803852 ps
CPU time 0.67 seconds
Started Aug 05 05:45:19 PM PDT 24
Finished Aug 05 05:45:20 PM PDT 24
Peak memory 198616 kb
Host smart-38b2f079-64f7-467a-959d-c39e45ea3d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583933577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3583933577
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.621558670
Short name T151
Test name
Test status
Simulation time 60069515 ps
CPU time 0.74 seconds
Started Aug 05 05:45:22 PM PDT 24
Finished Aug 05 05:45:23 PM PDT 24
Peak memory 199240 kb
Host smart-f3c5dcae-9bb8-4cfe-aa43-7e888ecd0e75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621558670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.621558670
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2985359332
Short name T507
Test name
Test status
Simulation time 29897657 ps
CPU time 0.62 seconds
Started Aug 05 05:45:24 PM PDT 24
Finished Aug 05 05:45:25 PM PDT 24
Peak memory 198052 kb
Host smart-23e2401b-2ed7-42b6-89f9-d83c004a7720
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985359332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2985359332
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.4062862630
Short name T437
Test name
Test status
Simulation time 158665112 ps
CPU time 1.04 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198416 kb
Host smart-e75f7366-d3bf-4556-b1ca-1c38eaac8fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062862630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.4062862630
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3451055999
Short name T592
Test name
Test status
Simulation time 24203724 ps
CPU time 0.63 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:25 PM PDT 24
Peak memory 198100 kb
Host smart-6125555d-ec9e-4262-a18a-5cbeca34ee8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451055999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3451055999
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.430461942
Short name T463
Test name
Test status
Simulation time 45014027 ps
CPU time 0.63 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 198112 kb
Host smart-2e09b1c3-6f27-4d22-acf1-576da2eedd40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430461942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.430461942
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2481038942
Short name T179
Test name
Test status
Simulation time 87003379 ps
CPU time 0.78 seconds
Started Aug 05 05:45:22 PM PDT 24
Finished Aug 05 05:45:23 PM PDT 24
Peak memory 201416 kb
Host smart-b3afb8ad-1133-4add-98ec-88a436a33edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481038942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2481038942
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.2083635660
Short name T215
Test name
Test status
Simulation time 95804715 ps
CPU time 0.73 seconds
Started Aug 05 05:45:18 PM PDT 24
Finished Aug 05 05:45:19 PM PDT 24
Peak memory 199188 kb
Host smart-9b7ccc84-d90b-4179-ba2a-e3dda4136953
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083635660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2083635660
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.208085907
Short name T468
Test name
Test status
Simulation time 159881949 ps
CPU time 0.8 seconds
Started Aug 05 05:45:26 PM PDT 24
Finished Aug 05 05:45:27 PM PDT 24
Peak memory 209548 kb
Host smart-75bb0f01-42e7-4e6b-aa88-2982da561165
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208085907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.208085907
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.4203685168
Short name T34
Test name
Test status
Simulation time 709023502 ps
CPU time 1.06 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 217648 kb
Host smart-0401c53c-8af2-4e62-a49f-18093f9b8439
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203685168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.4203685168
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1240287821
Short name T299
Test name
Test status
Simulation time 183945998 ps
CPU time 0.73 seconds
Started Aug 05 05:45:23 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 198376 kb
Host smart-eda8c469-f105-4de3-ae64-3ae173a71a66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240287821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1240287821
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.1055745159
Short name T335
Test name
Test status
Simulation time 36144209 ps
CPU time 0.66 seconds
Started Aug 05 05:45:17 PM PDT 24
Finished Aug 05 05:45:18 PM PDT 24
Peak memory 198524 kb
Host smart-4ba640be-e6b8-4213-87c9-f70eeb0d1785
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055745159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1055745159
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.428975688
Short name T209
Test name
Test status
Simulation time 116939446 ps
CPU time 0.7 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 199156 kb
Host smart-f54d7500-0fbc-486c-bf12-f6d14615de51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428975688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.428975688
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.624297138
Short name T306
Test name
Test status
Simulation time 30554515 ps
CPU time 0.79 seconds
Started Aug 05 05:45:24 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198980 kb
Host smart-a78a6e2a-a98c-4a29-aeb8-73e39c453b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624297138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.624297138
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3638251748
Short name T382
Test name
Test status
Simulation time 38946203 ps
CPU time 0.59 seconds
Started Aug 05 05:45:23 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 198028 kb
Host smart-b289b881-0609-4e41-9d59-1ad11fba3cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638251748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.3638251748
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2466226402
Short name T279
Test name
Test status
Simulation time 162036607 ps
CPU time 1 seconds
Started Aug 05 05:45:23 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 198360 kb
Host smart-8df069c0-f506-4c81-9cc8-3ad55892c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466226402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2466226402
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.2409745356
Short name T313
Test name
Test status
Simulation time 44078014 ps
CPU time 0.67 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198088 kb
Host smart-4df449e5-fa3d-43d0-a5fb-d3f562192cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409745356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2409745356
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.802320114
Short name T570
Test name
Test status
Simulation time 44259355 ps
CPU time 0.68 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198008 kb
Host smart-dab2dce8-e110-4afa-8a53-c3b1d2313804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802320114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.802320114
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.3594543209
Short name T36
Test name
Test status
Simulation time 57225221 ps
CPU time 0.79 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 198456 kb
Host smart-fbbaf7f1-72ea-4122-ad00-0a09d2750628
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594543209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3594543209
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.1435030350
Short name T338
Test name
Test status
Simulation time 124788478 ps
CPU time 0.86 seconds
Started Aug 05 05:45:23 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 209460 kb
Host smart-6c7a9be8-5468-4d08-b17a-e898badd1adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435030350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1435030350
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3675719663
Short name T35
Test name
Test status
Simulation time 1969139937 ps
CPU time 1.38 seconds
Started Aug 05 05:45:31 PM PDT 24
Finished Aug 05 05:45:32 PM PDT 24
Peak memory 217904 kb
Host smart-01a7edc7-8d3b-4b12-b66d-e3a9bbd138ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675719663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3675719663
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1010781575
Short name T496
Test name
Test status
Simulation time 168803911 ps
CPU time 0.7 seconds
Started Aug 05 05:45:27 PM PDT 24
Finished Aug 05 05:45:28 PM PDT 24
Peak memory 197764 kb
Host smart-ca063dde-60a0-45b1-b891-51e939f75472
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010781575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1010781575
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1406702281
Short name T352
Test name
Test status
Simulation time 45834879 ps
CPU time 0.65 seconds
Started Aug 05 05:45:25 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198552 kb
Host smart-5deae905-feed-4686-ba4f-1c8233e76fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406702281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1406702281
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1878789170
Short name T608
Test name
Test status
Simulation time 20344837 ps
CPU time 0.66 seconds
Started Aug 05 05:45:56 PM PDT 24
Finished Aug 05 05:45:57 PM PDT 24
Peak memory 198616 kb
Host smart-5336f8a1-7078-4233-bffb-9ed0bad6ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878789170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1878789170
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.837887091
Short name T161
Test name
Test status
Simulation time 94389119 ps
CPU time 0.71 seconds
Started Aug 05 05:46:01 PM PDT 24
Finished Aug 05 05:46:02 PM PDT 24
Peak memory 198568 kb
Host smart-c8c1e186-dad0-4fc5-a2bd-e994905ff35e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837887091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disa
ble_rom_integrity_check.837887091
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1124536848
Short name T547
Test name
Test status
Simulation time 29339497 ps
CPU time 0.62 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 198024 kb
Host smart-fec56e53-1328-44b0-a938-d4048f009d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124536848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1124536848
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.885479147
Short name T245
Test name
Test status
Simulation time 576062767 ps
CPU time 0.94 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 198428 kb
Host smart-57fdd91b-c4f8-419a-a6af-27ba929a0d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885479147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.885479147
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.387933765
Short name T451
Test name
Test status
Simulation time 44940154 ps
CPU time 0.68 seconds
Started Aug 05 05:45:59 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 197436 kb
Host smart-a3104a1e-1c1a-49fe-aef1-85770dfbcb28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387933765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.387933765
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.1809322691
Short name T311
Test name
Test status
Simulation time 50031275 ps
CPU time 0.68 seconds
Started Aug 05 05:45:56 PM PDT 24
Finished Aug 05 05:45:57 PM PDT 24
Peak memory 198112 kb
Host smart-020838d5-4f3d-4f54-8ef4-84b9cc872cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809322691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1809322691
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.3272102662
Short name T443
Test name
Test status
Simulation time 74205179 ps
CPU time 0.83 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 198480 kb
Host smart-3f8b7793-65b9-4b22-b7d0-9e1deee997cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272102662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3272102662
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3913111351
Short name T599
Test name
Test status
Simulation time 80144270 ps
CPU time 0.68 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 197740 kb
Host smart-9488dc08-7cbd-4455-b7cf-c6711332b90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913111351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3913111351
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1767912918
Short name T482
Test name
Test status
Simulation time 48643198 ps
CPU time 0.65 seconds
Started Aug 05 05:45:59 PM PDT 24
Finished Aug 05 05:46:00 PM PDT 24
Peak memory 199408 kb
Host smart-11e74fdc-0e68-49d2-a34f-eab32cda6c02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767912918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1767912918
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.120536108
Short name T155
Test name
Test status
Simulation time 62742636 ps
CPU time 0.86 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 199096 kb
Host smart-2b537823-8147-48f4-89b1-773cc7ef559c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120536108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.120536108
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3103052157
Short name T536
Test name
Test status
Simulation time 31006506 ps
CPU time 0.63 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 198048 kb
Host smart-02e1f0c2-6183-4116-978a-1863ce3e20ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103052157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3103052157
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3514036054
Short name T308
Test name
Test status
Simulation time 163111471 ps
CPU time 1.03 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 198060 kb
Host smart-98df5677-5d2c-45ab-83a1-b246919fcfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514036054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3514036054
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.3423576229
Short name T558
Test name
Test status
Simulation time 37114771 ps
CPU time 0.65 seconds
Started Aug 05 05:46:06 PM PDT 24
Finished Aug 05 05:46:07 PM PDT 24
Peak memory 198400 kb
Host smart-7b05a856-4d50-434e-b1b9-112bf33f3994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423576229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.3423576229
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.479794577
Short name T377
Test name
Test status
Simulation time 60621204 ps
CPU time 0.67 seconds
Started Aug 05 05:46:11 PM PDT 24
Finished Aug 05 05:46:11 PM PDT 24
Peak memory 198332 kb
Host smart-39aeb429-a948-4e9f-9f92-6f5f04ef82db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479794577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.479794577
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3947058686
Short name T251
Test name
Test status
Simulation time 188250220 ps
CPU time 0.8 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 209496 kb
Host smart-6480babf-22d4-4d92-bdea-b446b44f18bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947058686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3947058686
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.61371950
Short name T16
Test name
Test status
Simulation time 368937646 ps
CPU time 0.78 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 198784 kb
Host smart-49a5808a-6859-4751-b222-fdbbe89e3ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61371950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.61371950
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3251799514
Short name T162
Test name
Test status
Simulation time 56843365 ps
CPU time 0.85 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 198484 kb
Host smart-3fb0a718-b1b6-4089-a17a-dac9df3607e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251799514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3251799514
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1518265365
Short name T307
Test name
Test status
Simulation time 29362024 ps
CPU time 0.65 seconds
Started Aug 05 05:46:02 PM PDT 24
Finished Aug 05 05:46:03 PM PDT 24
Peak memory 198056 kb
Host smart-a86928dd-e251-4730-9a78-080af4584ca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518265365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1518265365
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2603495893
Short name T611
Test name
Test status
Simulation time 609179295 ps
CPU time 1.05 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 198420 kb
Host smart-d93dc6f8-b32b-43a4-a7e8-365e52282035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603495893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2603495893
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.681755158
Short name T267
Test name
Test status
Simulation time 44624785 ps
CPU time 0.74 seconds
Started Aug 05 05:46:04 PM PDT 24
Finished Aug 05 05:46:05 PM PDT 24
Peak memory 197356 kb
Host smart-3eebba11-3b99-4ff4-8f04-5c7973200ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681755158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.681755158
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.2101619263
Short name T459
Test name
Test status
Simulation time 60888709 ps
CPU time 0.59 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198436 kb
Host smart-deb986ff-0954-48b5-94a9-2d45fadec0cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101619263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2101619263
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.1316987366
Short name T553
Test name
Test status
Simulation time 60230704 ps
CPU time 0.84 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 199180 kb
Host smart-db9e6152-46a7-4bd6-bb4f-42ef69cb0c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316987366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1316987366
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3916741416
Short name T390
Test name
Test status
Simulation time 158587348 ps
CPU time 0.88 seconds
Started Aug 05 05:46:04 PM PDT 24
Finished Aug 05 05:46:05 PM PDT 24
Peak memory 209536 kb
Host smart-8bb5fb7c-76c5-4e5f-b61a-16c9de0d72eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916741416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3916741416
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3522893178
Short name T566
Test name
Test status
Simulation time 68213210 ps
CPU time 0.87 seconds
Started Aug 05 05:46:04 PM PDT 24
Finished Aug 05 05:46:05 PM PDT 24
Peak memory 199260 kb
Host smart-439cfb27-565b-4a6d-b10e-7d46d65e659a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522893178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3522893178
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3893021626
Short name T447
Test name
Test status
Simulation time 55464488 ps
CPU time 0.65 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 198524 kb
Host smart-486378cd-755c-4fb8-a9b5-fba321f7eb99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893021626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3893021626
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1409108155
Short name T542
Test name
Test status
Simulation time 40300628 ps
CPU time 0.85 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 199876 kb
Host smart-8b872eaa-a617-4018-a249-fed9dcaaf74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409108155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1409108155
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2178327327
Short name T392
Test name
Test status
Simulation time 68881841 ps
CPU time 0.67 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 198272 kb
Host smart-8fd98b8c-9249-4914-80c4-7dd41b491a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178327327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2178327327
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3504665313
Short name T613
Test name
Test status
Simulation time 40731414 ps
CPU time 0.62 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 197332 kb
Host smart-3154c65f-b482-4f17-a3a0-a6b7c2346ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504665313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3504665313
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.118727513
Short name T289
Test name
Test status
Simulation time 312009477 ps
CPU time 0.94 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:11 PM PDT 24
Peak memory 198124 kb
Host smart-8ad38866-aa36-4303-a2db-dfee5850274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118727513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.118727513
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3328580201
Short name T615
Test name
Test status
Simulation time 55227417 ps
CPU time 0.61 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 198060 kb
Host smart-0adc31b9-a69d-497d-b3f2-edb1c704910a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328580201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3328580201
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2327597358
Short name T262
Test name
Test status
Simulation time 33378820 ps
CPU time 0.68 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:03 PM PDT 24
Peak memory 198364 kb
Host smart-3a5714e3-6549-402c-9062-a646242f6b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327597358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2327597358
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.999599030
Short name T173
Test name
Test status
Simulation time 71224097 ps
CPU time 0.68 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 201412 kb
Host smart-1580f04e-5c1a-4819-9ad3-31bf0bb10830
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999599030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invali
d.999599030
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2716640578
Short name T229
Test name
Test status
Simulation time 45070101 ps
CPU time 0.63 seconds
Started Aug 05 05:46:06 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 198172 kb
Host smart-6d7ef314-1141-427c-b243-d6710d027b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716640578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2716640578
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1297554306
Short name T357
Test name
Test status
Simulation time 94012526 ps
CPU time 1.01 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 209568 kb
Host smart-17b1f786-4bc8-4401-9f21-f2eb6b20b9f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297554306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1297554306
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1189406056
Short name T255
Test name
Test status
Simulation time 490360185 ps
CPU time 0.85 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 199648 kb
Host smart-d8ba7ae1-d484-42cc-90a0-2a9f9cf26b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189406056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1189406056
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1349683587
Short name T356
Test name
Test status
Simulation time 29614930 ps
CPU time 0.7 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 199380 kb
Host smart-6b820f30-0f1e-418d-99fb-b075d0f75470
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349683587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1349683587
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1072458420
Short name T96
Test name
Test status
Simulation time 36227584 ps
CPU time 0.85 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198824 kb
Host smart-ed59f72a-8d92-4220-a955-2526054a13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072458420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1072458420
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.966737276
Short name T488
Test name
Test status
Simulation time 63835138 ps
CPU time 0.76 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 199096 kb
Host smart-bf5fe05b-c4f1-4825-8788-5aa4b337c32c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966737276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disa
ble_rom_integrity_check.966737276
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2397493905
Short name T316
Test name
Test status
Simulation time 38895160 ps
CPU time 0.59 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 197356 kb
Host smart-74c44951-71bd-44e8-8786-5fa325c9f1d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397493905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2397493905
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.300012680
Short name T557
Test name
Test status
Simulation time 158142484 ps
CPU time 1.01 seconds
Started Aug 05 05:46:12 PM PDT 24
Finished Aug 05 05:46:13 PM PDT 24
Peak memory 198116 kb
Host smart-e6295312-688d-4f26-8995-b872bb6a8763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300012680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.300012680
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.3426712012
Short name T290
Test name
Test status
Simulation time 43760528 ps
CPU time 0.62 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 197360 kb
Host smart-561b67cf-1e27-48da-88ab-0b0f65ebbde9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426712012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3426712012
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.2815800936
Short name T618
Test name
Test status
Simulation time 29607888 ps
CPU time 0.63 seconds
Started Aug 05 05:46:10 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198076 kb
Host smart-80f829e1-1634-4194-99e5-83d14d92283f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815800936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2815800936
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1258423643
Short name T51
Test name
Test status
Simulation time 45281985 ps
CPU time 0.74 seconds
Started Aug 05 05:46:11 PM PDT 24
Finished Aug 05 05:46:12 PM PDT 24
Peak memory 201264 kb
Host smart-a6c2411b-8960-4ce8-b712-bd4f32fd8094
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258423643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1258423643
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2025349270
Short name T440
Test name
Test status
Simulation time 100017303 ps
CPU time 0.7 seconds
Started Aug 05 05:46:05 PM PDT 24
Finished Aug 05 05:46:06 PM PDT 24
Peak memory 199180 kb
Host smart-f2d45a7b-28a3-488a-a766-e4f554596e98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025349270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2025349270
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3932922146
Short name T577
Test name
Test status
Simulation time 147551991 ps
CPU time 0.84 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 209560 kb
Host smart-8c9759ba-fadf-47f2-bf83-bb226b6b111a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932922146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3932922146
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4041059638
Short name T404
Test name
Test status
Simulation time 66142800 ps
CPU time 0.76 seconds
Started Aug 05 05:46:13 PM PDT 24
Finished Aug 05 05:46:14 PM PDT 24
Peak memory 197976 kb
Host smart-f61d7dd3-f21a-456a-b5d1-cc7dce5137ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041059638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4041059638
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.39505725
Short name T433
Test name
Test status
Simulation time 31074665 ps
CPU time 0.69 seconds
Started Aug 05 05:46:02 PM PDT 24
Finished Aug 05 05:46:03 PM PDT 24
Peak memory 199396 kb
Host smart-41795876-1ef6-4630-a618-79d4cc73240f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39505725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.39505725
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1434428541
Short name T346
Test name
Test status
Simulation time 31661670 ps
CPU time 1.09 seconds
Started Aug 05 05:46:10 PM PDT 24
Finished Aug 05 05:46:11 PM PDT 24
Peak memory 200952 kb
Host smart-add2fdc7-45bf-4a90-8d25-b4471a36bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434428541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1434428541
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2000141223
Short name T461
Test name
Test status
Simulation time 65020869 ps
CPU time 0.71 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 199116 kb
Host smart-db142050-bf47-4b00-b876-b329b19cef8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000141223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2000141223
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2679831173
Short name T355
Test name
Test status
Simulation time 64265226 ps
CPU time 0.59 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 197956 kb
Host smart-3056190e-7897-44c5-98a2-4aa9c9b7c70f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679831173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2679831173
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2637704633
Short name T337
Test name
Test status
Simulation time 160968499 ps
CPU time 0.96 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198432 kb
Host smart-e7507694-bcfe-4a77-ba2e-c1a2faad025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637704633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2637704633
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2760352934
Short name T342
Test name
Test status
Simulation time 67860257 ps
CPU time 0.65 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 197964 kb
Host smart-16299232-4389-4d63-90db-046ab8e6bea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760352934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2760352934
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3454725477
Short name T281
Test name
Test status
Simulation time 84826183 ps
CPU time 0.6 seconds
Started Aug 05 05:46:10 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198116 kb
Host smart-0758afee-8f78-40f2-9ed1-42d31c9c7193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454725477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3454725477
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.176859620
Short name T230
Test name
Test status
Simulation time 287360116 ps
CPU time 0.81 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 199180 kb
Host smart-8e309372-92a1-46a5-ae73-3463bbfd3679
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176859620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.176859620
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1060552423
Short name T379
Test name
Test status
Simulation time 111012720 ps
CPU time 1.16 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 209452 kb
Host smart-8fcdda7a-2fcb-4d1b-970f-0b35210199c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060552423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1060552423
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.675806606
Short name T349
Test name
Test status
Simulation time 52286524 ps
CPU time 0.78 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 198224 kb
Host smart-d301ef46-ac5b-4f7d-9285-6fff973b08e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675806606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.675806606
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1564261400
Short name T28
Test name
Test status
Simulation time 82990581 ps
CPU time 0.62 seconds
Started Aug 05 05:46:06 PM PDT 24
Finished Aug 05 05:46:07 PM PDT 24
Peak memory 198540 kb
Host smart-6286a765-ac4f-4b09-aeae-58eb8b87c75d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564261400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1564261400
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1607587436
Short name T413
Test name
Test status
Simulation time 64107844 ps
CPU time 0.93 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 200184 kb
Host smart-0b687d05-47a2-49b8-8c6b-d30601d3a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607587436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1607587436
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.347882493
Short name T458
Test name
Test status
Simulation time 65482790 ps
CPU time 0.9 seconds
Started Aug 05 05:46:12 PM PDT 24
Finished Aug 05 05:46:13 PM PDT 24
Peak memory 199148 kb
Host smart-a96e1ffb-ce47-4d38-94df-395b967ca349
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347882493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.347882493
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.1458560670
Short name T257
Test name
Test status
Simulation time 29143820 ps
CPU time 0.69 seconds
Started Aug 05 05:46:10 PM PDT 24
Finished Aug 05 05:46:11 PM PDT 24
Peak memory 197352 kb
Host smart-8be4672c-ee30-4449-b8c3-2c726305409d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458560670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.1458560670
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3617957308
Short name T562
Test name
Test status
Simulation time 938301809 ps
CPU time 1.01 seconds
Started Aug 05 05:46:10 PM PDT 24
Finished Aug 05 05:46:11 PM PDT 24
Peak memory 198408 kb
Host smart-2196a321-c986-4014-9d9c-48215a2d41d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617957308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3617957308
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3747867139
Short name T576
Test name
Test status
Simulation time 70806594 ps
CPU time 0.62 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 198108 kb
Host smart-8d7149cc-204a-42de-a475-ff41dc6d6283
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747867139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3747867139
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3575571408
Short name T520
Test name
Test status
Simulation time 158101846 ps
CPU time 0.64 seconds
Started Aug 05 05:46:09 PM PDT 24
Finished Aug 05 05:46:10 PM PDT 24
Peak memory 198428 kb
Host smart-e0d98779-a321-45f8-8e5b-8263d9bfb633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575571408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3575571408
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1437187340
Short name T350
Test name
Test status
Simulation time 47481207 ps
CPU time 0.82 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 199280 kb
Host smart-0ec650cf-421b-472a-af86-4de018a0c7b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437187340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1437187340
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.4196124401
Short name T575
Test name
Test status
Simulation time 102526957 ps
CPU time 1.03 seconds
Started Aug 05 05:46:08 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 209648 kb
Host smart-1c2272e8-4889-4187-a567-8506b7abb4ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196124401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.4196124401
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2895414776
Short name T319
Test name
Test status
Simulation time 123872194 ps
CPU time 0.82 seconds
Started Aug 05 05:46:07 PM PDT 24
Finished Aug 05 05:46:08 PM PDT 24
Peak memory 199244 kb
Host smart-9af86319-3f46-4c39-816b-c2a64339eed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895414776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2895414776
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.918136932
Short name T551
Test name
Test status
Simulation time 35591185 ps
CPU time 0.67 seconds
Started Aug 05 05:46:12 PM PDT 24
Finished Aug 05 05:46:13 PM PDT 24
Peak memory 199312 kb
Host smart-afb0092b-83e2-4565-a975-bef15d6d363a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918136932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.918136932
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1390008586
Short name T52
Test name
Test status
Simulation time 124148599 ps
CPU time 0.8 seconds
Started Aug 05 05:46:16 PM PDT 24
Finished Aug 05 05:46:17 PM PDT 24
Peak memory 200192 kb
Host smart-6493e6b5-90e5-4389-94de-b4418383a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390008586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1390008586
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.632331736
Short name T617
Test name
Test status
Simulation time 98570379 ps
CPU time 0.65 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 198280 kb
Host smart-eef04da3-4731-4cac-aac1-1e47d51ec10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632331736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disa
ble_rom_integrity_check.632331736
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.498057614
Short name T556
Test name
Test status
Simulation time 37912556 ps
CPU time 0.6 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:15 PM PDT 24
Peak memory 198068 kb
Host smart-09c60482-fdd6-4447-8437-27db29848f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498057614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.498057614
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3246239114
Short name T411
Test name
Test status
Simulation time 600714718 ps
CPU time 0.94 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 198128 kb
Host smart-edc92d69-4731-4bf8-88c2-1138f4c13910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246239114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3246239114
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.1275732024
Short name T239
Test name
Test status
Simulation time 81426510 ps
CPU time 0.65 seconds
Started Aug 05 05:46:18 PM PDT 24
Finished Aug 05 05:46:19 PM PDT 24
Peak memory 198136 kb
Host smart-e96214a5-e735-417d-8bec-01bb566e63ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275732024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1275732024
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2378885248
Short name T273
Test name
Test status
Simulation time 58450648 ps
CPU time 0.61 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 198112 kb
Host smart-c81f8b64-9886-4b34-8bdf-5f3ba7497091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378885248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2378885248
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3520849839
Short name T193
Test name
Test status
Simulation time 73882538 ps
CPU time 0.69 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 201352 kb
Host smart-f2e1603f-9173-4ff2-833f-b6806e9ff3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520849839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3520849839
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3034951437
Short name T585
Test name
Test status
Simulation time 69787185 ps
CPU time 0.93 seconds
Started Aug 05 05:46:16 PM PDT 24
Finished Aug 05 05:46:17 PM PDT 24
Peak memory 199024 kb
Host smart-fd01fb3e-5f2b-427c-a34d-569b190e43a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034951437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3034951437
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1656598477
Short name T477
Test name
Test status
Simulation time 233368089 ps
CPU time 0.78 seconds
Started Aug 05 05:46:16 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 209580 kb
Host smart-5c0f0d1e-a4a0-4a0c-bc49-0f0490dc8ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656598477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1656598477
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1722338756
Short name T464
Test name
Test status
Simulation time 63397281 ps
CPU time 1.01 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 199244 kb
Host smart-9480e3f0-ccef-42dc-aca4-d629907ca53c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722338756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1722338756
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.1784619788
Short name T537
Test name
Test status
Simulation time 39413745 ps
CPU time 0.65 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 198528 kb
Host smart-0ed29ec3-ecbc-40f2-960a-2e3816aaf508
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784619788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.1784619788
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.4076740715
Short name T442
Test name
Test status
Simulation time 45546164 ps
CPU time 0.96 seconds
Started Aug 05 05:46:14 PM PDT 24
Finished Aug 05 05:46:15 PM PDT 24
Peak memory 200772 kb
Host smart-6528aebb-e6a9-4a1d-8d10-8dfdd4b952e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076740715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.4076740715
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.555740885
Short name T134
Test name
Test status
Simulation time 75114869 ps
CPU time 0.71 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 199184 kb
Host smart-83402163-24e1-4036-a2f9-72206d90d916
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555740885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.555740885
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1383104319
Short name T505
Test name
Test status
Simulation time 29834615 ps
CPU time 0.65 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:15 PM PDT 24
Peak memory 198020 kb
Host smart-aaccb5ee-f17e-4a2c-a843-7d7889586406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383104319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1383104319
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.3014660315
Short name T11
Test name
Test status
Simulation time 289997610 ps
CPU time 0.92 seconds
Started Aug 05 05:46:15 PM PDT 24
Finished Aug 05 05:46:16 PM PDT 24
Peak memory 198116 kb
Host smart-0d16ced4-ef60-44b9-a7a7-112a3962f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014660315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3014660315
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2312784818
Short name T479
Test name
Test status
Simulation time 73739660 ps
CPU time 0.63 seconds
Started Aug 05 05:46:18 PM PDT 24
Finished Aug 05 05:46:19 PM PDT 24
Peak memory 198064 kb
Host smart-0ee453eb-9d86-44a5-b7e9-1de2367a69e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312784818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2312784818
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.942472881
Short name T510
Test name
Test status
Simulation time 42701116 ps
CPU time 0.63 seconds
Started Aug 05 05:46:19 PM PDT 24
Finished Aug 05 05:46:20 PM PDT 24
Peak memory 198008 kb
Host smart-ef2a3df1-3c27-40dc-8dfe-6ea31bc4ca0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942472881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.942472881
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3773839061
Short name T244
Test name
Test status
Simulation time 21767397 ps
CPU time 0.65 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 198424 kb
Host smart-c5bce282-d636-4e10-887d-3dda272d9543
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773839061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3773839061
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.3366319103
Short name T511
Test name
Test status
Simulation time 103396849 ps
CPU time 0.97 seconds
Started Aug 05 05:46:18 PM PDT 24
Finished Aug 05 05:46:19 PM PDT 24
Peak memory 209536 kb
Host smart-a8613186-006e-4db6-8935-57f94c490c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366319103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3366319103
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.4102069383
Short name T211
Test name
Test status
Simulation time 59604707 ps
CPU time 0.83 seconds
Started Aug 05 05:46:22 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 198032 kb
Host smart-fa7ac637-e6a0-49fa-bda1-a95ecb662a6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102069383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4102069383
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.484762556
Short name T83
Test name
Test status
Simulation time 86413172 ps
CPU time 0.64 seconds
Started Aug 05 05:46:14 PM PDT 24
Finished Aug 05 05:46:15 PM PDT 24
Peak memory 198524 kb
Host smart-3cef7bdd-efe3-41c5-99d3-6abd60dc3155
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484762556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.484762556
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.2279427725
Short name T94
Test name
Test status
Simulation time 38203042 ps
CPU time 0.89 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 200152 kb
Host smart-2c175778-856b-49ee-8d50-c7942883c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279427725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.2279427725
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.363008144
Short name T478
Test name
Test status
Simulation time 30768957 ps
CPU time 0.64 seconds
Started Aug 05 05:46:18 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 198052 kb
Host smart-a89d3865-496e-4f6c-9795-3182d79040e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363008144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_
malfunc.363008144
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.3350778188
Short name T481
Test name
Test status
Simulation time 725787382 ps
CPU time 0.99 seconds
Started Aug 05 05:47:06 PM PDT 24
Finished Aug 05 05:47:07 PM PDT 24
Peak memory 198424 kb
Host smart-7f6cffe6-9c5d-40b3-8f01-8e36bf7fad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350778188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3350778188
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2717179810
Short name T236
Test name
Test status
Simulation time 48618858 ps
CPU time 0.61 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:25 PM PDT 24
Peak memory 197976 kb
Host smart-7f5db868-e856-4f9c-b04a-4d356bc003ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717179810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2717179810
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1079714997
Short name T325
Test name
Test status
Simulation time 45917872 ps
CPU time 0.69 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:20 PM PDT 24
Peak memory 197996 kb
Host smart-e1fe539f-8adf-42a5-bded-a3c5d8797bd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079714997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1079714997
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.832725036
Short name T168
Test name
Test status
Simulation time 65882223 ps
CPU time 0.7 seconds
Started Aug 05 05:46:27 PM PDT 24
Finished Aug 05 05:46:28 PM PDT 24
Peak memory 201332 kb
Host smart-c4ccbaf5-7ba5-4973-a273-03607a843ce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832725036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invali
d.832725036
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.3601534039
Short name T389
Test name
Test status
Simulation time 40835624 ps
CPU time 0.74 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 199120 kb
Host smart-2eb5cfbd-4104-42bf-9afc-849c72020255
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601534039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3601534039
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.190083913
Short name T332
Test name
Test status
Simulation time 177743262 ps
CPU time 0.79 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 209472 kb
Host smart-c2199113-1114-423a-9370-1bb80fc8cc11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190083913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.190083913
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.24987833
Short name T120
Test name
Test status
Simulation time 71741690 ps
CPU time 0.98 seconds
Started Aug 05 05:46:17 PM PDT 24
Finished Aug 05 05:46:18 PM PDT 24
Peak memory 199248 kb
Host smart-95a193a9-1c4e-47b5-a302-9f8140fdbe74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.24987833
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1096637725
Short name T217
Test name
Test status
Simulation time 41194519 ps
CPU time 0.71 seconds
Started Aug 05 05:46:18 PM PDT 24
Finished Aug 05 05:46:19 PM PDT 24
Peak memory 198452 kb
Host smart-3d677427-d236-4e7d-93a4-acfd45de4379
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096637725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1096637725
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2892523319
Short name T119
Test name
Test status
Simulation time 23457298 ps
CPU time 0.59 seconds
Started Aug 05 05:45:26 PM PDT 24
Finished Aug 05 05:45:26 PM PDT 24
Peak memory 198640 kb
Host smart-15d4bab2-ecf7-4501-a503-0c0e8a4d08ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892523319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2892523319
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1000573175
Short name T154
Test name
Test status
Simulation time 78750259 ps
CPU time 0.67 seconds
Started Aug 05 05:45:27 PM PDT 24
Finished Aug 05 05:45:28 PM PDT 24
Peak memory 198420 kb
Host smart-5b7a44e7-2715-4314-808d-9789f0f8864d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000573175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1000573175
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.24663326
Short name T427
Test name
Test status
Simulation time 32982436 ps
CPU time 0.63 seconds
Started Aug 05 05:45:27 PM PDT 24
Finished Aug 05 05:45:28 PM PDT 24
Peak memory 198060 kb
Host smart-a1448fd0-e724-45b6-8f7c-002a5f21d38d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24663326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_ma
lfunc.24663326
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2307710554
Short name T253
Test name
Test status
Simulation time 3002996358 ps
CPU time 1 seconds
Started Aug 05 05:45:30 PM PDT 24
Finished Aug 05 05:45:31 PM PDT 24
Peak memory 198192 kb
Host smart-024f6368-b804-4aed-8bf5-d01a1328d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307710554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2307710554
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.2728659546
Short name T376
Test name
Test status
Simulation time 47720720 ps
CPU time 0.61 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 197356 kb
Host smart-8a6a1b8d-af17-4253-9e6b-2975c046d1e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728659546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2728659546
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.157161390
Short name T301
Test name
Test status
Simulation time 29885156 ps
CPU time 0.61 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 198412 kb
Host smart-bbdaa710-7765-4aaa-abb7-2f906be68001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157161390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.157161390
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2517596223
Short name T176
Test name
Test status
Simulation time 44010966 ps
CPU time 0.73 seconds
Started Aug 05 05:45:30 PM PDT 24
Finished Aug 05 05:45:31 PM PDT 24
Peak memory 201392 kb
Host smart-a5e11a18-f0c5-4ed4-9e9b-474900b867dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517596223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2517596223
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2952923879
Short name T485
Test name
Test status
Simulation time 71779673 ps
CPU time 0.92 seconds
Started Aug 05 05:45:29 PM PDT 24
Finished Aug 05 05:45:30 PM PDT 24
Peak memory 199096 kb
Host smart-632cebe8-3da2-46d5-b57c-de21d47df25f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952923879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2952923879
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.627800411
Short name T424
Test name
Test status
Simulation time 110599808 ps
CPU time 0.95 seconds
Started Aug 05 05:45:30 PM PDT 24
Finished Aug 05 05:45:32 PM PDT 24
Peak memory 209468 kb
Host smart-88d54027-06ce-43dc-92f1-df00a0ca637a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627800411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.627800411
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.3259598113
Short name T19
Test name
Test status
Simulation time 802635605 ps
CPU time 1.4 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 217584 kb
Host smart-4c06bf40-6a3a-4ae5-9e20-3c8d88ffb253
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259598113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3259598113
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2121715159
Short name T1
Test name
Test status
Simulation time 59688962 ps
CPU time 0.74 seconds
Started Aug 05 05:45:28 PM PDT 24
Finished Aug 05 05:45:29 PM PDT 24
Peak memory 198120 kb
Host smart-94642fd3-39e0-4b7f-b73f-de5e1d36bd5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121715159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2121715159
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3322125300
Short name T516
Test name
Test status
Simulation time 29402881 ps
CPU time 0.68 seconds
Started Aug 05 05:45:33 PM PDT 24
Finished Aug 05 05:45:34 PM PDT 24
Peak memory 199376 kb
Host smart-b8269aee-176c-4a1c-8035-63c03805f86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322125300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3322125300
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.2099180058
Short name T26
Test name
Test status
Simulation time 35562742 ps
CPU time 0.68 seconds
Started Aug 05 05:45:29 PM PDT 24
Finished Aug 05 05:45:30 PM PDT 24
Peak memory 198212 kb
Host smart-c275ae02-6e9b-4b3c-84e5-92888a5062bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099180058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.2099180058
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1142175970
Short name T88
Test name
Test status
Simulation time 30686356 ps
CPU time 0.78 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:21 PM PDT 24
Peak memory 198892 kb
Host smart-f46be503-b699-4ea5-9052-dd539fb6e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142175970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1142175970
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3440789609
Short name T137
Test name
Test status
Simulation time 55290757 ps
CPU time 0.81 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:25 PM PDT 24
Peak memory 198484 kb
Host smart-14b108c7-1a60-4264-b3f3-12e643f216f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440789609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3440789609
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.102026706
Short name T132
Test name
Test status
Simulation time 42973994 ps
CPU time 0.6 seconds
Started Aug 05 05:46:58 PM PDT 24
Finished Aug 05 05:46:58 PM PDT 24
Peak memory 198072 kb
Host smart-c98f9451-19ea-4a0c-8b66-06c7fc18212c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102026706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_
malfunc.102026706
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.676569202
Short name T296
Test name
Test status
Simulation time 370461939 ps
CPU time 0.99 seconds
Started Aug 05 05:46:31 PM PDT 24
Finished Aug 05 05:46:32 PM PDT 24
Peak memory 198100 kb
Host smart-32d7cfd2-36d3-4b82-9010-569b2b20fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676569202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.676569202
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2181776500
Short name T530
Test name
Test status
Simulation time 57780363 ps
CPU time 0.63 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 198064 kb
Host smart-b7927576-de55-4769-b0f3-6e8a58c7b1a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181776500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2181776500
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.3392488493
Short name T224
Test name
Test status
Simulation time 27558343 ps
CPU time 0.64 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:24 PM PDT 24
Peak memory 198336 kb
Host smart-d0e745eb-2769-4585-afd2-7b3692bba028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392488493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3392488493
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1838939063
Short name T383
Test name
Test status
Simulation time 61448437 ps
CPU time 0.65 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:25 PM PDT 24
Peak memory 198264 kb
Host smart-2bedcb60-1f56-4a30-bb39-238e1d356851
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838939063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1838939063
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3435047105
Short name T414
Test name
Test status
Simulation time 97018623 ps
CPU time 1.06 seconds
Started Aug 05 05:46:24 PM PDT 24
Finished Aug 05 05:46:26 PM PDT 24
Peak memory 209468 kb
Host smart-c456c43f-4d4b-418c-9349-127f2e06da1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435047105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3435047105
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1832445249
Short name T616
Test name
Test status
Simulation time 51679455 ps
CPU time 0.89 seconds
Started Aug 05 05:46:44 PM PDT 24
Finished Aug 05 05:46:45 PM PDT 24
Peak memory 199428 kb
Host smart-9bf31e7b-ca25-4cd4-9f87-17527c5f9e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832445249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1832445249
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1952686939
Short name T336
Test name
Test status
Simulation time 30508441 ps
CPU time 0.7 seconds
Started Aug 05 05:47:07 PM PDT 24
Finished Aug 05 05:47:08 PM PDT 24
Peak memory 199304 kb
Host smart-a7559909-ff50-400b-b1d6-c0552a8ded66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952686939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1952686939
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3795184881
Short name T14
Test name
Test status
Simulation time 23250057 ps
CPU time 0.62 seconds
Started Aug 05 05:46:22 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 199188 kb
Host smart-51679ee4-39cd-4495-81c0-b0e9a7f9651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795184881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3795184881
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2518631592
Short name T156
Test name
Test status
Simulation time 61827371 ps
CPU time 0.88 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:21 PM PDT 24
Peak memory 199092 kb
Host smart-5751bf8e-f201-4869-a77d-6430feffb569
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518631592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.2518631592
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.476047011
Short name T419
Test name
Test status
Simulation time 29507462 ps
CPU time 0.67 seconds
Started Aug 05 05:46:25 PM PDT 24
Finished Aug 05 05:46:26 PM PDT 24
Peak memory 198036 kb
Host smart-cc5e5c81-960b-472b-831f-a02d8d499413
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476047011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.476047011
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.3732417585
Short name T4
Test name
Test status
Simulation time 161168549 ps
CPU time 0.99 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:21 PM PDT 24
Peak memory 198192 kb
Host smart-9dcc1444-1b6b-4a22-a3d5-c3f9458f9486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732417585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.3732417585
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.3068544248
Short name T491
Test name
Test status
Simulation time 44106558 ps
CPU time 0.67 seconds
Started Aug 05 05:46:29 PM PDT 24
Finished Aug 05 05:46:30 PM PDT 24
Peak memory 198164 kb
Host smart-1f8332a6-2543-4321-b34b-ca4be171b03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068544248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3068544248
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3754626060
Short name T340
Test name
Test status
Simulation time 37133557 ps
CPU time 0.67 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 198104 kb
Host smart-2318485e-e32c-4808-bc18-2014332fc441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754626060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3754626060
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2042240324
Short name T625
Test name
Test status
Simulation time 152256404 ps
CPU time 0.78 seconds
Started Aug 05 05:46:21 PM PDT 24
Finished Aug 05 05:46:22 PM PDT 24
Peak memory 199184 kb
Host smart-afe842a4-0d54-4342-8ae1-b096a7960762
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042240324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2042240324
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2438834221
Short name T476
Test name
Test status
Simulation time 98174464 ps
CPU time 1.09 seconds
Started Aug 05 05:46:22 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 209504 kb
Host smart-65e29fa0-5b7d-45e2-9692-b36b6ca9c564
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438834221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2438834221
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1171541611
Short name T213
Test name
Test status
Simulation time 132228342 ps
CPU time 0.87 seconds
Started Aug 05 05:47:07 PM PDT 24
Finished Aug 05 05:47:08 PM PDT 24
Peak memory 199228 kb
Host smart-0f590019-daf5-413b-a586-e87e2f9b9295
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171541611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1171541611
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2471828681
Short name T381
Test name
Test status
Simulation time 31901158 ps
CPU time 0.7 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:56 PM PDT 24
Peak memory 199312 kb
Host smart-8a38c3b0-e3fc-438d-87eb-90c55628eebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471828681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2471828681
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3555739802
Short name T95
Test name
Test status
Simulation time 54813666 ps
CPU time 0.78 seconds
Started Aug 05 05:47:15 PM PDT 24
Finished Aug 05 05:47:16 PM PDT 24
Peak memory 199172 kb
Host smart-8c2a6073-08f3-4ff7-bcc1-bc349c51a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555739802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3555739802
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2047365244
Short name T493
Test name
Test status
Simulation time 28157289 ps
CPU time 0.63 seconds
Started Aug 05 05:46:22 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 198044 kb
Host smart-43e965fa-b3ce-4e43-ab21-f3026d294c00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047365244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2047365244
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.516688329
Short name T261
Test name
Test status
Simulation time 683289467 ps
CPU time 1.06 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 198436 kb
Host smart-86660a15-f003-432a-aca4-30fe0ee73a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516688329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.516688329
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.4121028127
Short name T412
Test name
Test status
Simulation time 59538920 ps
CPU time 0.71 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 198144 kb
Host smart-fab221c4-a7aa-4e70-93db-9493ac1e8836
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121028127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.4121028127
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1029195750
Short name T519
Test name
Test status
Simulation time 33022043 ps
CPU time 0.66 seconds
Started Aug 05 05:46:28 PM PDT 24
Finished Aug 05 05:46:29 PM PDT 24
Peak memory 198128 kb
Host smart-907f9082-2aa8-4822-8b84-79168a2ed1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029195750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1029195750
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.691849353
Short name T187
Test name
Test status
Simulation time 36556794 ps
CPU time 0.73 seconds
Started Aug 05 05:47:15 PM PDT 24
Finished Aug 05 05:47:16 PM PDT 24
Peak memory 201480 kb
Host smart-f3c9e0c3-a44c-4479-8c3c-2e12e5cfbd33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691849353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.691849353
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3003190119
Short name T606
Test name
Test status
Simulation time 60204705 ps
CPU time 0.86 seconds
Started Aug 05 05:47:00 PM PDT 24
Finished Aug 05 05:47:01 PM PDT 24
Peak memory 199184 kb
Host smart-e29d504c-48b1-4b78-8a48-ba134aeba18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003190119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3003190119
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3859446610
Short name T524
Test name
Test status
Simulation time 124318360 ps
CPU time 0.88 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 209440 kb
Host smart-02227082-21e2-4d94-9b0f-ad66f653df4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859446610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3859446610
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.87686340
Short name T550
Test name
Test status
Simulation time 59332182 ps
CPU time 0.88 seconds
Started Aug 05 05:46:20 PM PDT 24
Finished Aug 05 05:46:21 PM PDT 24
Peak memory 198044 kb
Host smart-3c7a8990-81bd-4180-917d-08c2e40a36e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87686340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.87686340
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.4093294411
Short name T620
Test name
Test status
Simulation time 138822878 ps
CPU time 0.61 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 198524 kb
Host smart-fbadcc08-8dfd-4699-acce-5fa0024e94a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093294411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.4093294411
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.165761667
Short name T533
Test name
Test status
Simulation time 81126667 ps
CPU time 0.76 seconds
Started Aug 05 05:46:32 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 198868 kb
Host smart-36e87144-ec9e-46bd-b825-725c49daa405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165761667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.165761667
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2032100331
Short name T138
Test name
Test status
Simulation time 78579095 ps
CPU time 0.69 seconds
Started Aug 05 05:46:35 PM PDT 24
Finished Aug 05 05:46:36 PM PDT 24
Peak memory 198520 kb
Host smart-cac22bf8-aef5-4dfb-ac72-4afe330663a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032100331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2032100331
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1893550859
Short name T497
Test name
Test status
Simulation time 32109276 ps
CPU time 0.59 seconds
Started Aug 05 05:46:27 PM PDT 24
Finished Aug 05 05:46:28 PM PDT 24
Peak memory 197368 kb
Host smart-366fc918-23a8-4b9e-b926-96b09e25b90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893550859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1893550859
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1597793927
Short name T532
Test name
Test status
Simulation time 164740858 ps
CPU time 0.96 seconds
Started Aug 05 05:46:29 PM PDT 24
Finished Aug 05 05:46:30 PM PDT 24
Peak memory 198144 kb
Host smart-6a722eec-bc86-4a07-a297-809a2974a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597793927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1597793927
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1523009016
Short name T429
Test name
Test status
Simulation time 69556291 ps
CPU time 0.63 seconds
Started Aug 05 05:46:43 PM PDT 24
Finished Aug 05 05:46:44 PM PDT 24
Peak memory 198072 kb
Host smart-9cd6941a-d177-4bf5-a181-34fbd326f0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523009016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1523009016
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.666140331
Short name T322
Test name
Test status
Simulation time 45257752 ps
CPU time 0.7 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 198020 kb
Host smart-66880298-7207-4e11-80d3-77312d175352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666140331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.666140331
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2955864518
Short name T180
Test name
Test status
Simulation time 71626439 ps
CPU time 0.72 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 201460 kb
Host smart-fae4bdf5-f367-4556-8e79-e94e4b14dd20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955864518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2955864518
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.1391813726
Short name T435
Test name
Test status
Simulation time 49759177 ps
CPU time 0.79 seconds
Started Aug 05 05:46:30 PM PDT 24
Finished Aug 05 05:46:31 PM PDT 24
Peak memory 199200 kb
Host smart-5839b399-bd23-48b4-ae7c-866efa2339dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391813726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1391813726
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3359244599
Short name T286
Test name
Test status
Simulation time 147431397 ps
CPU time 0.85 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 209500 kb
Host smart-48803a38-5b62-456f-9aee-5cb6d5e8d792
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359244599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3359244599
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3150948375
Short name T571
Test name
Test status
Simulation time 559749983 ps
CPU time 0.84 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:47:37 PM PDT 24
Peak memory 199384 kb
Host smart-1853dfff-cc7a-42a2-990e-aa3c34917a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150948375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3150948375
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1890098352
Short name T591
Test name
Test status
Simulation time 30942799 ps
CPU time 0.67 seconds
Started Aug 05 05:46:32 PM PDT 24
Finished Aug 05 05:46:33 PM PDT 24
Peak memory 198532 kb
Host smart-2c1c6286-6b3e-4714-b040-fff6c222b135
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890098352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1890098352
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.466332949
Short name T367
Test name
Test status
Simulation time 179430170 ps
CPU time 0.73 seconds
Started Aug 05 05:46:27 PM PDT 24
Finished Aug 05 05:46:28 PM PDT 24
Peak memory 198668 kb
Host smart-c79bd524-ca86-46f3-bdde-c3b2e8e904b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466332949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.466332949
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1969674868
Short name T309
Test name
Test status
Simulation time 87086358 ps
CPU time 0.66 seconds
Started Aug 05 05:46:30 PM PDT 24
Finished Aug 05 05:46:31 PM PDT 24
Peak memory 199128 kb
Host smart-f07d3fcc-49d7-4f49-9cec-6ba8d95caf98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969674868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1969674868
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3487733340
Short name T605
Test name
Test status
Simulation time 31140648 ps
CPU time 0.64 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 198036 kb
Host smart-34d63e3c-09e6-4a32-9d9c-187663ad96b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487733340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3487733340
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.607944988
Short name T552
Test name
Test status
Simulation time 165333915 ps
CPU time 1 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 198144 kb
Host smart-8f27c1b5-63a2-4f20-953c-7398a36db759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607944988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.607944988
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.356832717
Short name T227
Test name
Test status
Simulation time 57836577 ps
CPU time 0.67 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 198060 kb
Host smart-ec59937d-e047-479a-8884-2a42d86b2a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356832717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.356832717
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.1344122972
Short name T604
Test name
Test status
Simulation time 42466746 ps
CPU time 0.62 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:35 PM PDT 24
Peak memory 198224 kb
Host smart-16c5fb21-7c7e-40a2-80ea-ff5a1cf374c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344122972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1344122972
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.4103130610
Short name T191
Test name
Test status
Simulation time 53313694 ps
CPU time 0.68 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:47:37 PM PDT 24
Peak memory 201424 kb
Host smart-3e0eac0e-a360-4967-8463-76d268039eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103130610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.4103130610
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1380661103
Short name T378
Test name
Test status
Simulation time 59708688 ps
CPU time 0.82 seconds
Started Aug 05 05:46:28 PM PDT 24
Finished Aug 05 05:46:29 PM PDT 24
Peak memory 199120 kb
Host smart-f031a902-4264-4309-ba60-b6324ae8073d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380661103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1380661103
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.843932559
Short name T347
Test name
Test status
Simulation time 101699977 ps
CPU time 1.06 seconds
Started Aug 05 05:46:51 PM PDT 24
Finished Aug 05 05:46:52 PM PDT 24
Peak memory 209524 kb
Host smart-5ab5aaaa-1586-4b01-af2e-1b79c05e4bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843932559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.843932559
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2715183622
Short name T580
Test name
Test status
Simulation time 90359106 ps
CPU time 0.79 seconds
Started Aug 05 05:46:28 PM PDT 24
Finished Aug 05 05:46:29 PM PDT 24
Peak memory 199308 kb
Host smart-1eec4b17-cc73-456f-b837-bdcc11a773a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715183622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2715183622
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2175532355
Short name T549
Test name
Test status
Simulation time 28273614 ps
CPU time 0.68 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 199380 kb
Host smart-57ba9289-047b-4092-8fbb-6812c806a71c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175532355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2175532355
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.914339242
Short name T344
Test name
Test status
Simulation time 64828811 ps
CPU time 0.67 seconds
Started Aug 05 05:46:57 PM PDT 24
Finished Aug 05 05:46:58 PM PDT 24
Peak memory 199116 kb
Host smart-b37b9b39-a90b-434f-8134-c8437f5869a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914339242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disa
ble_rom_integrity_check.914339242
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1102849928
Short name T327
Test name
Test status
Simulation time 30564938 ps
CPU time 0.65 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:25 PM PDT 24
Peak memory 198020 kb
Host smart-f03fd1b6-6548-44b5-aa69-5347ae09dfb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102849928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1102849928
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2301468435
Short name T490
Test name
Test status
Simulation time 161574004 ps
CPU time 0.98 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 198092 kb
Host smart-8625880b-674a-453a-914c-27681780eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301468435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2301468435
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2077798808
Short name T254
Test name
Test status
Simulation time 64056461 ps
CPU time 0.68 seconds
Started Aug 05 05:46:38 PM PDT 24
Finished Aug 05 05:46:39 PM PDT 24
Peak memory 198096 kb
Host smart-e9463da3-d820-4338-9f71-09e9c8f0b0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077798808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2077798808
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2130790787
Short name T326
Test name
Test status
Simulation time 57036070 ps
CPU time 0.63 seconds
Started Aug 05 05:46:31 PM PDT 24
Finished Aug 05 05:46:32 PM PDT 24
Peak memory 198116 kb
Host smart-a432c627-1469-460f-968d-740321c7131f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130790787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2130790787
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.428064361
Short name T264
Test name
Test status
Simulation time 119820119 ps
CPU time 0.83 seconds
Started Aug 05 05:46:26 PM PDT 24
Finished Aug 05 05:46:27 PM PDT 24
Peak memory 198392 kb
Host smart-ddbd8075-9cf0-467c-b265-357cb2a5c7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428064361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.428064361
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3956212599
Short name T391
Test name
Test status
Simulation time 100243318 ps
CPU time 0.89 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 209536 kb
Host smart-fca3eb9a-8395-470b-b575-16cba491c4e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956212599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3956212599
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.77590062
Short name T385
Test name
Test status
Simulation time 60496105 ps
CPU time 0.71 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:33 PM PDT 24
Peak memory 198212 kb
Host smart-5898a916-5302-4888-b523-c07e982730a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77590062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.77590062
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.255793761
Short name T295
Test name
Test status
Simulation time 82365300 ps
CPU time 0.66 seconds
Started Aug 05 05:46:25 PM PDT 24
Finished Aug 05 05:46:26 PM PDT 24
Peak memory 198548 kb
Host smart-451308e5-d507-4c2c-8e01-06b35f9fdef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255793761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.255793761
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.769670550
Short name T181
Test name
Test status
Simulation time 60170545 ps
CPU time 0.96 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 200348 kb
Host smart-295ab40f-5a1c-46ee-87d5-98e04494bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769670550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.769670550
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2126392853
Short name T368
Test name
Test status
Simulation time 47331913 ps
CPU time 0.75 seconds
Started Aug 05 05:46:47 PM PDT 24
Finished Aug 05 05:46:48 PM PDT 24
Peak memory 198484 kb
Host smart-db6f57d3-3b97-43f7-9aa1-3da9d5e1ac11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126392853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2126392853
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.4294050355
Short name T128
Test name
Test status
Simulation time 30967231 ps
CPU time 0.64 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 198056 kb
Host smart-28456e75-2cfd-4d2c-a4ce-d0431e919196
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294050355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.4294050355
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2804221654
Short name T405
Test name
Test status
Simulation time 598797526 ps
CPU time 1.02 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 198120 kb
Host smart-132bbadf-6c9e-43f7-b681-ff7e31106b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804221654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2804221654
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2476685745
Short name T310
Test name
Test status
Simulation time 64894097 ps
CPU time 0.61 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:36 PM PDT 24
Peak memory 198080 kb
Host smart-3deb99b1-aa12-4c64-ab38-6616deded0fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476685745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2476685745
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3631666763
Short name T17
Test name
Test status
Simulation time 53598938 ps
CPU time 0.59 seconds
Started Aug 05 05:46:41 PM PDT 24
Finished Aug 05 05:46:42 PM PDT 24
Peak memory 198408 kb
Host smart-adeefb1c-aee9-4c1b-a61f-a2b3ee8160f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631666763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3631666763
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.1789472587
Short name T197
Test name
Test status
Simulation time 45868718 ps
CPU time 0.74 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 201396 kb
Host smart-03e8bd19-3dde-4cae-bcc4-40709ec5230b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789472587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.1789472587
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.2494121229
Short name T527
Test name
Test status
Simulation time 102314056 ps
CPU time 0.8 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 199184 kb
Host smart-1e9193f7-45fe-480b-a12a-8b62136e5083
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494121229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2494121229
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3329493144
Short name T541
Test name
Test status
Simulation time 118910148 ps
CPU time 0.94 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:25 PM PDT 24
Peak memory 209456 kb
Host smart-ba0dbf1e-d1c1-41c6-8bad-0d71540e1872
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329493144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3329493144
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.118743911
Short name T314
Test name
Test status
Simulation time 54182070 ps
CPU time 0.89 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 199304 kb
Host smart-e9a20793-9f1d-4d2e-b232-8ebe86b4ba57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118743911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.118743911
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.736367860
Short name T13
Test name
Test status
Simulation time 56159242 ps
CPU time 0.6 seconds
Started Aug 05 05:47:19 PM PDT 24
Finished Aug 05 05:47:20 PM PDT 24
Peak memory 198528 kb
Host smart-4310d852-7171-4c9c-b2cf-6279e8083ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736367860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.736367860
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2916953335
Short name T609
Test name
Test status
Simulation time 26197700 ps
CPU time 0.72 seconds
Started Aug 05 05:47:21 PM PDT 24
Finished Aug 05 05:47:22 PM PDT 24
Peak memory 198744 kb
Host smart-c3800585-bcb8-40c0-b03d-98c1f974e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916953335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2916953335
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.3693898991
Short name T321
Test name
Test status
Simulation time 59527114 ps
CPU time 0.72 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 199196 kb
Host smart-19663c58-18b6-41c5-ad49-b46b4924901a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693898991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.3693898991
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1253497006
Short name T44
Test name
Test status
Simulation time 37680168 ps
CPU time 0.58 seconds
Started Aug 05 05:46:44 PM PDT 24
Finished Aug 05 05:46:45 PM PDT 24
Peak memory 197244 kb
Host smart-c80459f8-692d-4460-a918-9dff7b73be16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253497006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1253497006
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.338838623
Short name T588
Test name
Test status
Simulation time 308028020 ps
CPU time 0.94 seconds
Started Aug 05 05:47:19 PM PDT 24
Finished Aug 05 05:47:20 PM PDT 24
Peak memory 198448 kb
Host smart-fe95bca3-83de-43b6-89ae-a4a8d94f3f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338838623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.338838623
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.821471581
Short name T252
Test name
Test status
Simulation time 50044054 ps
CPU time 0.7 seconds
Started Aug 05 05:47:19 PM PDT 24
Finished Aug 05 05:47:20 PM PDT 24
Peak memory 198152 kb
Host smart-9d58159b-4bcf-408d-ba72-55fda05179a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821471581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.821471581
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3263442331
Short name T465
Test name
Test status
Simulation time 44164522 ps
CPU time 0.68 seconds
Started Aug 05 05:46:34 PM PDT 24
Finished Aug 05 05:46:35 PM PDT 24
Peak memory 198120 kb
Host smart-34ffe3b1-1fe5-4004-a422-0d0e2cb437f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263442331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3263442331
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2710296187
Short name T42
Test name
Test status
Simulation time 144704814 ps
CPU time 0.73 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 201396 kb
Host smart-d1701438-43a6-4b19-a7ce-6c7c4bef280d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710296187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2710296187
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1912236748
Short name T480
Test name
Test status
Simulation time 46806657 ps
CPU time 0.64 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 198316 kb
Host smart-5a76c605-7750-437d-8b77-941e37ff8477
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912236748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1912236748
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.1835776916
Short name T219
Test name
Test status
Simulation time 132481021 ps
CPU time 0.83 seconds
Started Aug 05 05:46:33 PM PDT 24
Finished Aug 05 05:46:34 PM PDT 24
Peak memory 201212 kb
Host smart-e59c7c45-a2df-4647-861e-b0e5663feb93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835776916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1835776916
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.63361443
Short name T446
Test name
Test status
Simulation time 57446033 ps
CPU time 0.8 seconds
Started Aug 05 05:46:36 PM PDT 24
Finished Aug 05 05:46:37 PM PDT 24
Peak memory 198212 kb
Host smart-32147400-297f-4939-9d97-b652174c0250
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63361443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.63361443
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.1404559294
Short name T436
Test name
Test status
Simulation time 28218962 ps
CPU time 0.65 seconds
Started Aug 05 05:46:37 PM PDT 24
Finished Aug 05 05:46:38 PM PDT 24
Peak memory 198532 kb
Host smart-51896b23-7359-400b-958e-6ee0029738ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404559294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1404559294
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2535069559
Short name T388
Test name
Test status
Simulation time 28504845 ps
CPU time 0.66 seconds
Started Aug 05 05:46:52 PM PDT 24
Finished Aug 05 05:46:53 PM PDT 24
Peak memory 198644 kb
Host smart-4974a714-a189-4299-9e07-33963e695b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535069559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2535069559
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3442148227
Short name T434
Test name
Test status
Simulation time 66296664 ps
CPU time 0.72 seconds
Started Aug 05 05:47:26 PM PDT 24
Finished Aug 05 05:47:27 PM PDT 24
Peak memory 198468 kb
Host smart-548461e8-b34e-4a5b-8e1d-7c7ccf85dc7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442148227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3442148227
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2971322696
Short name T602
Test name
Test status
Simulation time 38054298 ps
CPU time 0.59 seconds
Started Aug 05 05:47:05 PM PDT 24
Finished Aug 05 05:47:06 PM PDT 24
Peak memory 197308 kb
Host smart-20aad71d-9af3-4df1-84e9-12e0ce64f823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971322696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.2971322696
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1382811558
Short name T247
Test name
Test status
Simulation time 1664036027 ps
CPU time 0.97 seconds
Started Aug 05 05:46:41 PM PDT 24
Finished Aug 05 05:46:42 PM PDT 24
Peak memory 198412 kb
Host smart-b2855682-2476-4088-9300-99ed6cec0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382811558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1382811558
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3319460887
Short name T285
Test name
Test status
Simulation time 45851071 ps
CPU time 0.61 seconds
Started Aug 05 05:47:00 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 197360 kb
Host smart-ebfb27dc-8b68-46e1-99a8-9ce80f8f00de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319460887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3319460887
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.1969211333
Short name T473
Test name
Test status
Simulation time 46027454 ps
CPU time 0.65 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 198428 kb
Host smart-0782d016-e42b-4f21-a380-c8cf9a24466e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969211333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1969211333
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2498655805
Short name T610
Test name
Test status
Simulation time 37920383 ps
CPU time 0.62 seconds
Started Aug 05 05:46:42 PM PDT 24
Finished Aug 05 05:46:43 PM PDT 24
Peak memory 198036 kb
Host smart-93b1ff76-1455-40bd-b1cd-794336dca471
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498655805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2498655805
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1247538705
Short name T453
Test name
Test status
Simulation time 97885835 ps
CPU time 0.72 seconds
Started Aug 05 05:46:54 PM PDT 24
Finished Aug 05 05:46:55 PM PDT 24
Peak memory 199128 kb
Host smart-791bef4b-2a22-4c86-8927-a003a6c8b50c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247538705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1247538705
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.502066836
Short name T358
Test name
Test status
Simulation time 95986880 ps
CPU time 1.12 seconds
Started Aug 05 05:46:53 PM PDT 24
Finished Aug 05 05:46:54 PM PDT 24
Peak memory 209468 kb
Host smart-252d759d-c98d-49ab-915e-501f4f74c1dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502066836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.502066836
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.898632674
Short name T444
Test name
Test status
Simulation time 53969878 ps
CPU time 0.86 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:56 PM PDT 24
Peak memory 199228 kb
Host smart-b9dca82e-1d2d-4c3a-9030-5ad24ca2d50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898632674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_
mubi.898632674
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3654967319
Short name T121
Test name
Test status
Simulation time 28647442 ps
CPU time 0.71 seconds
Started Aug 05 05:46:39 PM PDT 24
Finished Aug 05 05:46:40 PM PDT 24
Peak memory 198552 kb
Host smart-9eb0875e-f6ed-45d9-9694-072be7136653
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654967319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3654967319
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.532289012
Short name T93
Test name
Test status
Simulation time 52845926 ps
CPU time 0.78 seconds
Started Aug 05 05:46:45 PM PDT 24
Finished Aug 05 05:46:46 PM PDT 24
Peak memory 200120 kb
Host smart-f456cbc6-383d-4b0c-b65a-84fb90efb64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532289012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.532289012
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1462331317
Short name T163
Test name
Test status
Simulation time 51741707 ps
CPU time 0.83 seconds
Started Aug 05 05:46:45 PM PDT 24
Finished Aug 05 05:46:45 PM PDT 24
Peak memory 199204 kb
Host smart-6ca8472e-1dc3-4c3d-bfbd-1fb4b1ccafe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462331317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.1462331317
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3250830935
Short name T400
Test name
Test status
Simulation time 91375134 ps
CPU time 0.6 seconds
Started Aug 05 05:46:38 PM PDT 24
Finished Aug 05 05:46:39 PM PDT 24
Peak memory 197348 kb
Host smart-541bc4a8-b241-4f81-b892-24dda680c8c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250830935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3250830935
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3115802523
Short name T395
Test name
Test status
Simulation time 937111813 ps
CPU time 1 seconds
Started Aug 05 05:47:16 PM PDT 24
Finished Aug 05 05:47:17 PM PDT 24
Peak memory 198068 kb
Host smart-b85dc0f4-3951-4725-b356-08d6c5a9198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115802523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3115802523
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1432220674
Short name T139
Test name
Test status
Simulation time 219599677 ps
CPU time 0.62 seconds
Started Aug 05 05:47:26 PM PDT 24
Finished Aug 05 05:47:26 PM PDT 24
Peak memory 198128 kb
Host smart-6801d969-b232-4b51-bf34-60a84e5b5f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432220674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1432220674
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1369824041
Short name T456
Test name
Test status
Simulation time 88081024 ps
CPU time 0.6 seconds
Started Aug 05 05:46:41 PM PDT 24
Finished Aug 05 05:46:42 PM PDT 24
Peak memory 198136 kb
Host smart-0811926f-42ab-4360-b2ba-fe49eb3261bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369824041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1369824041
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3917738097
Short name T62
Test name
Test status
Simulation time 75304493 ps
CPU time 0.68 seconds
Started Aug 05 05:46:53 PM PDT 24
Finished Aug 05 05:46:54 PM PDT 24
Peak memory 201556 kb
Host smart-43be93a0-b9a5-431f-8337-d98602346a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917738097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3917738097
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3959595366
Short name T600
Test name
Test status
Simulation time 43792052 ps
CPU time 0.69 seconds
Started Aug 05 05:46:43 PM PDT 24
Finished Aug 05 05:46:43 PM PDT 24
Peak memory 198340 kb
Host smart-59377970-644c-4e26-87c9-16d8056081f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959595366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3959595366
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3726508392
Short name T249
Test name
Test status
Simulation time 100384233 ps
CPU time 0.95 seconds
Started Aug 05 05:46:42 PM PDT 24
Finished Aug 05 05:46:43 PM PDT 24
Peak memory 209520 kb
Host smart-c4bb1396-60dd-4d36-8596-0ca02ee0eb56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726508392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3726508392
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3473830144
Short name T393
Test name
Test status
Simulation time 54340586 ps
CPU time 0.83 seconds
Started Aug 05 05:46:39 PM PDT 24
Finished Aug 05 05:46:40 PM PDT 24
Peak memory 197892 kb
Host smart-73a2c4d6-aa63-4fc0-b105-ca9458078308
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473830144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3473830144
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1548613184
Short name T341
Test name
Test status
Simulation time 114143916 ps
CPU time 0.63 seconds
Started Aug 05 05:46:50 PM PDT 24
Finished Aug 05 05:46:51 PM PDT 24
Peak memory 198532 kb
Host smart-5aad1254-0278-487c-8c9f-9a1c959c17ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548613184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1548613184
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1880685846
Short name T500
Test name
Test status
Simulation time 33045606 ps
CPU time 0.83 seconds
Started Aug 05 05:45:26 PM PDT 24
Finished Aug 05 05:45:27 PM PDT 24
Peak memory 200032 kb
Host smart-da005ced-5996-4ec7-81f7-d1e48f31d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880685846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1880685846
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1587015130
Short name T157
Test name
Test status
Simulation time 50788621 ps
CPU time 0.79 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 199204 kb
Host smart-d39c1dc5-8c58-43c7-a7bc-f3e135ad559e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587015130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1587015130
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3238168859
Short name T426
Test name
Test status
Simulation time 35782985 ps
CPU time 0.64 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 197324 kb
Host smart-8657caac-1af3-4e6c-92b3-2e6a60d837d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238168859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3238168859
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2554556035
Short name T399
Test name
Test status
Simulation time 631126517 ps
CPU time 0.97 seconds
Started Aug 05 05:45:33 PM PDT 24
Finished Aug 05 05:45:34 PM PDT 24
Peak memory 198120 kb
Host smart-8abeb3f3-b77b-4606-9c46-8b7bf366ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554556035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2554556035
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.3568385688
Short name T275
Test name
Test status
Simulation time 48414752 ps
CPU time 0.63 seconds
Started Aug 05 05:45:34 PM PDT 24
Finished Aug 05 05:45:34 PM PDT 24
Peak memory 198048 kb
Host smart-9bade99b-a663-4c6c-b1bf-00367567a620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568385688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3568385688
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.538619745
Short name T402
Test name
Test status
Simulation time 139842095 ps
CPU time 0.6 seconds
Started Aug 05 05:45:35 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 198304 kb
Host smart-8cbd2f39-b575-40b6-9e85-ca917accbcd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538619745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.538619745
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1244815141
Short name T555
Test name
Test status
Simulation time 68204358 ps
CPU time 0.67 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 201396 kb
Host smart-f99af16b-dae0-4dab-94f0-203b039d5bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244815141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1244815141
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1313112793
Short name T470
Test name
Test status
Simulation time 76797682 ps
CPU time 0.94 seconds
Started Aug 05 05:45:29 PM PDT 24
Finished Aug 05 05:45:30 PM PDT 24
Peak memory 198556 kb
Host smart-b2cf21e1-7a68-4f02-8d17-4453dae51a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313112793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1313112793
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3081822226
Short name T601
Test name
Test status
Simulation time 158119857 ps
CPU time 0.89 seconds
Started Aug 05 05:45:34 PM PDT 24
Finished Aug 05 05:45:35 PM PDT 24
Peak memory 209512 kb
Host smart-54c66c35-7278-4f19-9b14-855cb7e93587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081822226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3081822226
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1924351487
Short name T546
Test name
Test status
Simulation time 54549294 ps
CPU time 0.79 seconds
Started Aug 05 05:45:33 PM PDT 24
Finished Aug 05 05:45:33 PM PDT 24
Peak memory 198188 kb
Host smart-a9b2ac6a-d6fe-4966-bb6f-a35878da29cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924351487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1924351487
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.4162615503
Short name T595
Test name
Test status
Simulation time 100301995 ps
CPU time 0.64 seconds
Started Aug 05 05:45:30 PM PDT 24
Finished Aug 05 05:45:31 PM PDT 24
Peak memory 198420 kb
Host smart-ff915596-4912-4a53-948a-c08c661f890c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162615503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.4162615503
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1554846506
Short name T430
Test name
Test status
Simulation time 125928342 ps
CPU time 0.95 seconds
Started Aug 05 05:47:16 PM PDT 24
Finished Aug 05 05:47:17 PM PDT 24
Peak memory 200276 kb
Host smart-f0dd50b8-59d1-49d0-ac5d-52dcc8c03e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554846506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1554846506
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3450381486
Short name T135
Test name
Test status
Simulation time 52888389 ps
CPU time 0.77 seconds
Started Aug 05 05:46:48 PM PDT 24
Finished Aug 05 05:46:49 PM PDT 24
Peak memory 198472 kb
Host smart-3317240a-d151-4a6f-8199-58f237e82eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450381486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3450381486
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1685116198
Short name T228
Test name
Test status
Simulation time 30411320 ps
CPU time 0.61 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 197964 kb
Host smart-2a694719-2ad5-4df1-8399-c8c3a7cd3b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685116198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1685116198
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.2273107335
Short name T323
Test name
Test status
Simulation time 160484033 ps
CPU time 0.95 seconds
Started Aug 05 05:46:44 PM PDT 24
Finished Aug 05 05:46:45 PM PDT 24
Peak memory 198124 kb
Host smart-611aa1b6-8848-42ce-bd22-ddf49c69e3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273107335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.2273107335
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.3346198686
Short name T242
Test name
Test status
Simulation time 61971328 ps
CPU time 0.72 seconds
Started Aug 05 05:46:41 PM PDT 24
Finished Aug 05 05:46:42 PM PDT 24
Peak memory 197292 kb
Host smart-81dfc8d6-8477-4959-890a-b4dc9c6115c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346198686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3346198686
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2755693085
Short name T594
Test name
Test status
Simulation time 72297190 ps
CPU time 0.62 seconds
Started Aug 05 05:47:11 PM PDT 24
Finished Aug 05 05:47:12 PM PDT 24
Peak memory 198404 kb
Host smart-ce2aeec4-dd88-460e-93bd-9c27bb683818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755693085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2755693085
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3422576162
Short name T185
Test name
Test status
Simulation time 43228539 ps
CPU time 0.74 seconds
Started Aug 05 05:47:00 PM PDT 24
Finished Aug 05 05:47:01 PM PDT 24
Peak memory 201444 kb
Host smart-f14aaec0-6296-4a6b-8602-07aaf13110c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422576162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.3422576162
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.3568424426
Short name T258
Test name
Test status
Simulation time 120371590 ps
CPU time 0.75 seconds
Started Aug 05 05:46:40 PM PDT 24
Finished Aug 05 05:46:41 PM PDT 24
Peak memory 198412 kb
Host smart-93c61929-f922-4988-b302-ec49e9fe0c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568424426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3568424426
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1899462262
Short name T268
Test name
Test status
Simulation time 110696106 ps
CPU time 0.98 seconds
Started Aug 05 05:46:41 PM PDT 24
Finished Aug 05 05:46:42 PM PDT 24
Peak memory 209544 kb
Host smart-c884de69-e081-41a1-b3b9-e723079870e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899462262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1899462262
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3380710653
Short name T529
Test name
Test status
Simulation time 60450459 ps
CPU time 0.8 seconds
Started Aug 05 05:46:52 PM PDT 24
Finished Aug 05 05:46:53 PM PDT 24
Peak memory 197892 kb
Host smart-c06a8b89-c54a-415c-9b95-3367d64f8fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380710653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3380710653
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2913695070
Short name T506
Test name
Test status
Simulation time 83740942 ps
CPU time 0.64 seconds
Started Aug 05 05:46:43 PM PDT 24
Finished Aug 05 05:46:44 PM PDT 24
Peak memory 198448 kb
Host smart-36fc98ea-c2ce-4ecf-8643-343ab37f98b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913695070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2913695070
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2379206029
Short name T87
Test name
Test status
Simulation time 74451340 ps
CPU time 0.73 seconds
Started Aug 05 05:46:44 PM PDT 24
Finished Aug 05 05:46:45 PM PDT 24
Peak memory 198788 kb
Host smart-4b30052e-4ac2-445e-86ad-7d877f6de4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379206029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2379206029
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.336008158
Short name T569
Test name
Test status
Simulation time 73520567 ps
CPU time 0.75 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 198584 kb
Host smart-5f0a89ce-366c-47ec-ab75-bfd2b5159bfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336008158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.336008158
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2107118251
Short name T291
Test name
Test status
Simulation time 30474722 ps
CPU time 0.65 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:32 PM PDT 24
Peak memory 197376 kb
Host smart-a326cb6d-33a4-4f63-9692-218aedd81fad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107118251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2107118251
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.2059844050
Short name T256
Test name
Test status
Simulation time 164598947 ps
CPU time 0.96 seconds
Started Aug 05 05:46:58 PM PDT 24
Finished Aug 05 05:46:59 PM PDT 24
Peak memory 198112 kb
Host smart-468f3ffa-e194-43c8-85f1-aaaf7103d34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059844050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.2059844050
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.4235894431
Short name T515
Test name
Test status
Simulation time 52294417 ps
CPU time 0.7 seconds
Started Aug 05 05:46:53 PM PDT 24
Finished Aug 05 05:46:54 PM PDT 24
Peak memory 198020 kb
Host smart-f47cae75-2f8f-4149-80ff-927aed93d9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235894431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.4235894431
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1779299060
Short name T467
Test name
Test status
Simulation time 241893119 ps
CPU time 0.62 seconds
Started Aug 05 05:46:46 PM PDT 24
Finished Aug 05 05:46:47 PM PDT 24
Peak memory 198428 kb
Host smart-6fe622e3-c8bc-469f-a920-ca9d190c899c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779299060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1779299060
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.1166416724
Short name T504
Test name
Test status
Simulation time 123915428 ps
CPU time 0.8 seconds
Started Aug 05 05:46:48 PM PDT 24
Finished Aug 05 05:46:49 PM PDT 24
Peak memory 198324 kb
Host smart-2754f234-f911-4495-87d4-667b48103823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166416724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1166416724
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.3935422419
Short name T441
Test name
Test status
Simulation time 116922991 ps
CPU time 0.82 seconds
Started Aug 05 05:46:50 PM PDT 24
Finished Aug 05 05:46:50 PM PDT 24
Peak memory 209488 kb
Host smart-cdd4ce7a-6ff1-4dc3-958b-adf0262aa369
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935422419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3935422419
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.609223859
Short name T531
Test name
Test status
Simulation time 58075709 ps
CPU time 0.78 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 198144 kb
Host smart-db3be653-c7ef-437d-9c5f-78640cd0a4b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609223859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_
mubi.609223859
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.128851475
Short name T363
Test name
Test status
Simulation time 36825201 ps
CPU time 0.76 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:56 PM PDT 24
Peak memory 199368 kb
Host smart-74bcd1c1-10ff-4391-ba7d-f036ebc5fb08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128851475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.128851475
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3681272224
Short name T455
Test name
Test status
Simulation time 40241357 ps
CPU time 0.62 seconds
Started Aug 05 05:46:46 PM PDT 24
Finished Aug 05 05:46:46 PM PDT 24
Peak memory 198576 kb
Host smart-3c7a6a55-bc16-47f5-9cc4-5f043f509622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681272224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3681272224
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1923447844
Short name T152
Test name
Test status
Simulation time 48285722 ps
CPU time 0.76 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 199184 kb
Host smart-388e7ac0-718b-440c-b242-c0e6c63fbc6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923447844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1923447844
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1468553285
Short name T232
Test name
Test status
Simulation time 39125455 ps
CPU time 0.59 seconds
Started Aug 05 05:46:51 PM PDT 24
Finished Aug 05 05:46:52 PM PDT 24
Peak memory 198056 kb
Host smart-3757a30f-98bb-45e3-b6fe-f7132213a6a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468553285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1468553285
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.311427486
Short name T614
Test name
Test status
Simulation time 1008668008 ps
CPU time 1.02 seconds
Started Aug 05 05:46:49 PM PDT 24
Finished Aug 05 05:46:50 PM PDT 24
Peak memory 198124 kb
Host smart-8c364fc9-01ef-401c-97cb-4f673596db22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311427486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.311427486
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.701587755
Short name T18
Test name
Test status
Simulation time 37290146 ps
CPU time 0.66 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 198136 kb
Host smart-ee19beca-afba-42f3-812c-e53232b53371
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701587755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.701587755
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2557251952
Short name T409
Test name
Test status
Simulation time 55551851 ps
CPU time 0.63 seconds
Started Aug 05 05:47:15 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 198100 kb
Host smart-ddcc9594-9e42-4a62-946c-305707a63974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557251952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2557251952
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2776692766
Short name T280
Test name
Test status
Simulation time 51510929 ps
CPU time 0.68 seconds
Started Aug 05 05:46:57 PM PDT 24
Finished Aug 05 05:46:58 PM PDT 24
Peak memory 198172 kb
Host smart-1426c30b-ccc6-40c9-87f1-0b9487ac06c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776692766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2776692766
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.3933239739
Short name T241
Test name
Test status
Simulation time 130621597 ps
CPU time 0.92 seconds
Started Aug 05 05:46:47 PM PDT 24
Finished Aug 05 05:46:48 PM PDT 24
Peak memory 209392 kb
Host smart-a24f94b1-f334-4b2e-9b65-1f4fd089054c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933239739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.3933239739
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.4496549
Short name T43
Test name
Test status
Simulation time 72950437 ps
CPU time 0.73 seconds
Started Aug 05 05:46:48 PM PDT 24
Finished Aug 05 05:46:49 PM PDT 24
Peak memory 198144 kb
Host smart-1280d0d2-85f8-4a48-9c5a-7b288e6b194e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4496549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mu
bi.4496549
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3673393192
Short name T417
Test name
Test status
Simulation time 43866346 ps
CPU time 0.64 seconds
Started Aug 05 05:46:47 PM PDT 24
Finished Aug 05 05:46:48 PM PDT 24
Peak memory 198528 kb
Host smart-1d16eede-c3fe-4245-9ade-113b8c87155f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673393192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3673393192
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.2100397261
Short name T448
Test name
Test status
Simulation time 29050667 ps
CPU time 0.65 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:31 PM PDT 24
Peak memory 199208 kb
Host smart-1ec1387b-0f6d-437f-8fe4-e131e780a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100397261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2100397261
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.509614053
Short name T534
Test name
Test status
Simulation time 76327084 ps
CPU time 0.67 seconds
Started Aug 05 05:46:51 PM PDT 24
Finished Aug 05 05:46:52 PM PDT 24
Peak memory 199032 kb
Host smart-1aeab373-b1a3-4fac-87c6-6e0b56fb2f43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509614053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disa
ble_rom_integrity_check.509614053
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3386168730
Short name T525
Test name
Test status
Simulation time 31680524 ps
CPU time 0.63 seconds
Started Aug 05 05:47:06 PM PDT 24
Finished Aug 05 05:47:06 PM PDT 24
Peak memory 197328 kb
Host smart-5975545d-f2f2-4565-81ac-3c19b55bb381
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386168730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3386168730
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.1680319194
Short name T623
Test name
Test status
Simulation time 159111949 ps
CPU time 0.97 seconds
Started Aug 05 05:46:50 PM PDT 24
Finished Aug 05 05:46:51 PM PDT 24
Peak memory 198120 kb
Host smart-d45d8901-09ed-47dd-b01e-f00b910542fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680319194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1680319194
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2767379910
Short name T394
Test name
Test status
Simulation time 88591746 ps
CPU time 0.66 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 197416 kb
Host smart-c90e9816-85c3-4191-b328-d3ff788b07fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767379910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2767379910
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1163060825
Short name T234
Test name
Test status
Simulation time 35862766 ps
CPU time 0.64 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 198324 kb
Host smart-6cbac181-85c1-4d6b-923f-d21cb000278a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163060825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1163060825
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3188624245
Short name T204
Test name
Test status
Simulation time 57770605 ps
CPU time 0.71 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:14 PM PDT 24
Peak memory 201380 kb
Host smart-76cdce6e-232a-4ff8-bac4-d99245e6049a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188624245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3188624245
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.3567469364
Short name T523
Test name
Test status
Simulation time 58138792 ps
CPU time 0.73 seconds
Started Aug 05 05:47:08 PM PDT 24
Finished Aug 05 05:47:09 PM PDT 24
Peak memory 199184 kb
Host smart-4361f3bd-4165-49b5-8de9-08cc8a4ce181
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567469364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.3567469364
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1435224815
Short name T486
Test name
Test status
Simulation time 125606016 ps
CPU time 0.9 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 209516 kb
Host smart-ba6add92-1ab6-4269-bbe8-cf5d88835b57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435224815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1435224815
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3085924450
Short name T484
Test name
Test status
Simulation time 103416410 ps
CPU time 0.89 seconds
Started Aug 05 05:46:59 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 199412 kb
Host smart-e120fe2d-8b5a-4ced-8fde-b88147b3329c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085924450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3085924450
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.4183212396
Short name T320
Test name
Test status
Simulation time 29361914 ps
CPU time 0.67 seconds
Started Aug 05 05:47:16 PM PDT 24
Finished Aug 05 05:47:17 PM PDT 24
Peak memory 199388 kb
Host smart-e7357c1a-d46c-4402-9c33-eb2b9038c99a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183212396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.4183212396
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.201217573
Short name T503
Test name
Test status
Simulation time 27947419 ps
CPU time 0.85 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 200236 kb
Host smart-7dd36252-fc57-4efa-ae0c-cae4b42ae5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201217573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.201217573
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3525897466
Short name T207
Test name
Test status
Simulation time 58580079 ps
CPU time 0.84 seconds
Started Aug 05 05:46:52 PM PDT 24
Finished Aug 05 05:46:53 PM PDT 24
Peak memory 199148 kb
Host smart-45fb46be-7c60-4a07-b2a8-c3694cf1a557
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525897466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3525897466
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1205890626
Short name T587
Test name
Test status
Simulation time 39124947 ps
CPU time 0.59 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 198048 kb
Host smart-92ed0f4d-af4c-4957-a9f5-c723d4e49509
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205890626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1205890626
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2587815962
Short name T538
Test name
Test status
Simulation time 410074856 ps
CPU time 0.92 seconds
Started Aug 05 05:47:07 PM PDT 24
Finished Aug 05 05:47:08 PM PDT 24
Peak memory 198100 kb
Host smart-d4f33a16-ed81-4a9d-98ad-1dbba67cf959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587815962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2587815962
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.2388545220
Short name T474
Test name
Test status
Simulation time 81367735 ps
CPU time 0.57 seconds
Started Aug 05 05:46:47 PM PDT 24
Finished Aug 05 05:46:48 PM PDT 24
Peak memory 197368 kb
Host smart-693c9eed-fcb6-4927-9d7c-ac7578ffe579
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388545220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.2388545220
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1182473847
Short name T222
Test name
Test status
Simulation time 59206348 ps
CPU time 0.6 seconds
Started Aug 05 05:47:15 PM PDT 24
Finished Aug 05 05:47:16 PM PDT 24
Peak memory 198128 kb
Host smart-feb0c192-eafb-437e-95a8-3962ce05755e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182473847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1182473847
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2670807261
Short name T194
Test name
Test status
Simulation time 49468362 ps
CPU time 0.67 seconds
Started Aug 05 05:47:10 PM PDT 24
Finished Aug 05 05:47:11 PM PDT 24
Peak memory 201356 kb
Host smart-ddb87ebe-3ed6-4c1c-aeda-b85d9bb89213
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670807261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2670807261
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3094286983
Short name T512
Test name
Test status
Simulation time 82176270 ps
CPU time 0.73 seconds
Started Aug 05 05:46:51 PM PDT 24
Finished Aug 05 05:46:52 PM PDT 24
Peak memory 198340 kb
Host smart-f90c23aa-deff-4d3f-a005-77a16523e73b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094286983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3094286983
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.3963744778
Short name T328
Test name
Test status
Simulation time 150832488 ps
CPU time 0.79 seconds
Started Aug 05 05:46:49 PM PDT 24
Finished Aug 05 05:46:50 PM PDT 24
Peak memory 209548 kb
Host smart-b13109fd-79dd-4bae-a835-3feacc1104d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963744778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3963744778
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1873656687
Short name T373
Test name
Test status
Simulation time 62663702 ps
CPU time 0.79 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 198108 kb
Host smart-c938b9b7-37b3-4305-94c0-af5407811a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873656687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1873656687
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.312496187
Short name T495
Test name
Test status
Simulation time 61586849 ps
CPU time 0.64 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 198500 kb
Host smart-1b44371c-4061-416e-aa4b-6a51fc5d1ab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312496187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.312496187
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.2871385510
Short name T182
Test name
Test status
Simulation time 48602628 ps
CPU time 0.71 seconds
Started Aug 05 05:46:59 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 198684 kb
Host smart-f832f113-ab4c-4432-b0f9-13d617b880bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871385510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.2871385510
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.3160345312
Short name T472
Test name
Test status
Simulation time 67648170 ps
CPU time 0.65 seconds
Started Aug 05 05:47:17 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 198584 kb
Host smart-cb63acd0-a629-4669-bd39-f6fe4e95777e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160345312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.3160345312
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1800235020
Short name T397
Test name
Test status
Simulation time 30050593 ps
CPU time 0.64 seconds
Started Aug 05 05:46:57 PM PDT 24
Finished Aug 05 05:46:58 PM PDT 24
Peak memory 197336 kb
Host smart-fd0c95e1-22d2-49ec-ac0e-8660a671b8da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800235020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.1800235020
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.1422356264
Short name T522
Test name
Test status
Simulation time 164929173 ps
CPU time 1.02 seconds
Started Aug 05 05:46:50 PM PDT 24
Finished Aug 05 05:46:52 PM PDT 24
Peak memory 198116 kb
Host smart-44cf2f15-5099-4d55-b7bf-c7a977e71bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422356264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1422356264
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.4117257342
Short name T432
Test name
Test status
Simulation time 32230303 ps
CPU time 0.65 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:47:48 PM PDT 24
Peak memory 198136 kb
Host smart-2c7acc65-c660-4b46-86ce-5359c52eff0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117257342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.4117257342
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1964667119
Short name T270
Test name
Test status
Simulation time 61548329 ps
CPU time 0.59 seconds
Started Aug 05 05:47:06 PM PDT 24
Finished Aug 05 05:47:07 PM PDT 24
Peak memory 198428 kb
Host smart-cf9f9c37-92f0-4b03-b674-664921de8133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964667119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1964667119
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.739757479
Short name T170
Test name
Test status
Simulation time 116611764 ps
CPU time 0.67 seconds
Started Aug 05 05:47:10 PM PDT 24
Finished Aug 05 05:47:11 PM PDT 24
Peak memory 201400 kb
Host smart-a08d0469-5fdb-4b39-9259-a3702eed889a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739757479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.739757479
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1380710436
Short name T41
Test name
Test status
Simulation time 111748962 ps
CPU time 0.8 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:57 PM PDT 24
Peak memory 198420 kb
Host smart-927dd942-0e4d-47bd-9219-222cb79c869e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380710436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1380710436
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.4214885372
Short name T7
Test name
Test status
Simulation time 240266665 ps
CPU time 0.75 seconds
Started Aug 05 05:47:17 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 209564 kb
Host smart-67cb2304-a11e-4f41-a4c0-0054f7c16b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214885372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.4214885372
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.126375964
Short name T403
Test name
Test status
Simulation time 71975289 ps
CPU time 0.67 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 198120 kb
Host smart-10be2742-3591-458f-b4f6-12f0d9942ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126375964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.126375964
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1901812792
Short name T526
Test name
Test status
Simulation time 31955175 ps
CPU time 0.74 seconds
Started Aug 05 05:46:49 PM PDT 24
Finished Aug 05 05:46:50 PM PDT 24
Peak memory 199304 kb
Host smart-d4ca3fce-c39c-4fc0-9a89-662c629ab0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901812792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1901812792
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2041453490
Short name T450
Test name
Test status
Simulation time 59124243 ps
CPU time 0.72 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 199200 kb
Host smart-a8f8c8f8-503b-40cf-a43b-da6c826cca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041453490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2041453490
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2968762822
Short name T498
Test name
Test status
Simulation time 37131096 ps
CPU time 0.61 seconds
Started Aug 05 05:47:16 PM PDT 24
Finished Aug 05 05:47:17 PM PDT 24
Peak memory 198260 kb
Host smart-6850e56b-d59e-42bb-8d7b-a8b1d8d2243d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968762822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2968762822
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.784882011
Short name T590
Test name
Test status
Simulation time 44939738 ps
CPU time 0.65 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 197396 kb
Host smart-64e1cd72-c583-406b-8243-8d87eaf4ae35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784882011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.784882011
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2168359647
Short name T263
Test name
Test status
Simulation time 39902057 ps
CPU time 0.66 seconds
Started Aug 05 05:46:59 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 198120 kb
Host smart-defef1fa-1470-41da-8959-ddcca8d1a39d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168359647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2168359647
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2188666080
Short name T38
Test name
Test status
Simulation time 60074909 ps
CPU time 0.79 seconds
Started Aug 05 05:46:59 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 199180 kb
Host smart-dad3bd57-b048-4fc9-a362-afc4136a5ba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188666080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2188666080
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.822984437
Short name T517
Test name
Test status
Simulation time 106277378 ps
CPU time 0.86 seconds
Started Aug 05 05:46:53 PM PDT 24
Finished Aug 05 05:46:54 PM PDT 24
Peak memory 209500 kb
Host smart-eb9277bf-b560-480a-b67b-eb628206ca75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822984437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.822984437
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.4201645569
Short name T55
Test name
Test status
Simulation time 75600550 ps
CPU time 0.81 seconds
Started Aug 05 05:47:17 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 199316 kb
Host smart-60036750-4e49-41ea-a34b-4476b69e9494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201645569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4201645569
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.89207149
Short name T501
Test name
Test status
Simulation time 35124171 ps
CPU time 0.7 seconds
Started Aug 05 05:46:59 PM PDT 24
Finished Aug 05 05:46:59 PM PDT 24
Peak memory 199276 kb
Host smart-c9fcbc15-a159-477f-809a-14b2f330f45b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89207149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.89207149
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3219252943
Short name T554
Test name
Test status
Simulation time 48142049 ps
CPU time 0.94 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 200776 kb
Host smart-142e84bf-960c-4424-aa4c-36ab11dc75df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219252943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3219252943
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2056236849
Short name T582
Test name
Test status
Simulation time 59586989 ps
CPU time 0.73 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 199140 kb
Host smart-e2936965-c95e-4e50-ab85-2d4d546241c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056236849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2056236849
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.4120371194
Short name T374
Test name
Test status
Simulation time 30923637 ps
CPU time 0.65 seconds
Started Aug 05 05:46:56 PM PDT 24
Finished Aug 05 05:46:57 PM PDT 24
Peak memory 198036 kb
Host smart-c2fba8f8-20ce-4a90-98f9-82b14727d306
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120371194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.4120371194
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.2615864208
Short name T596
Test name
Test status
Simulation time 160716751 ps
CPU time 1.03 seconds
Started Aug 05 05:46:58 PM PDT 24
Finished Aug 05 05:47:00 PM PDT 24
Peak memory 198048 kb
Host smart-a0e07a41-b00d-4680-b667-5f19bc42cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615864208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2615864208
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3661946088
Short name T513
Test name
Test status
Simulation time 34283605 ps
CPU time 0.71 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 197984 kb
Host smart-1d80dbe4-a4d4-43a1-832e-bebbaf13645b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661946088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3661946088
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.4184356673
Short name T445
Test name
Test status
Simulation time 47834707 ps
CPU time 0.6 seconds
Started Aug 05 05:47:07 PM PDT 24
Finished Aug 05 05:47:07 PM PDT 24
Peak memory 198408 kb
Host smart-8f530cb2-9cee-496e-b3c6-8448146c2f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184356673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.4184356673
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.3044427115
Short name T317
Test name
Test status
Simulation time 63499992 ps
CPU time 0.65 seconds
Started Aug 05 05:47:00 PM PDT 24
Finished Aug 05 05:47:01 PM PDT 24
Peak memory 199120 kb
Host smart-c72b63ac-8b21-4440-b94d-409434f6b7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044427115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3044427115
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.490564338
Short name T274
Test name
Test status
Simulation time 101140535 ps
CPU time 1.11 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 209472 kb
Host smart-c80562b5-49f7-40dd-a4a6-af9bce4d74ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490564338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.490564338
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.814582147
Short name T619
Test name
Test status
Simulation time 52267660 ps
CPU time 0.95 seconds
Started Aug 05 05:46:55 PM PDT 24
Finished Aug 05 05:46:56 PM PDT 24
Peak memory 199308 kb
Host smart-af2400bc-de65-42a8-b858-312f78367f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814582147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.814582147
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3101557881
Short name T226
Test name
Test status
Simulation time 29630457 ps
CPU time 0.68 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 199380 kb
Host smart-955041e0-bb85-4a82-94bc-17e3fc84fcd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101557881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3101557881
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1257457696
Short name T612
Test name
Test status
Simulation time 35147842 ps
CPU time 0.78 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 199972 kb
Host smart-e526b26b-9a0b-46d7-8ab0-436c21974384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257457696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1257457696
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3044717172
Short name T561
Test name
Test status
Simulation time 72332582 ps
CPU time 0.67 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:14 PM PDT 24
Peak memory 198440 kb
Host smart-1d674150-3455-4519-ae9d-08c017eb1f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044717172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3044717172
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1597029848
Short name T126
Test name
Test status
Simulation time 32644831 ps
CPU time 0.61 seconds
Started Aug 05 05:47:09 PM PDT 24
Finished Aug 05 05:47:10 PM PDT 24
Peak memory 198028 kb
Host smart-7c8faeee-3ed5-4bd7-9d45-858c2628d0e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597029848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1597029848
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.1222317060
Short name T545
Test name
Test status
Simulation time 612075272 ps
CPU time 0.98 seconds
Started Aug 05 05:47:06 PM PDT 24
Finished Aug 05 05:47:07 PM PDT 24
Peak memory 198128 kb
Host smart-e8bc7ebf-9bdc-4d3e-906a-8b54cf51f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222317060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1222317060
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.378645187
Short name T282
Test name
Test status
Simulation time 61978811 ps
CPU time 0.65 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 197968 kb
Host smart-779d5a83-1fa8-4f29-a607-15c60120b5bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378645187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.378645187
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2162438425
Short name T362
Test name
Test status
Simulation time 69715487 ps
CPU time 0.59 seconds
Started Aug 05 05:47:00 PM PDT 24
Finished Aug 05 05:47:01 PM PDT 24
Peak memory 198124 kb
Host smart-6277a694-32a6-44d2-ac8d-4ecc89bb38e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162438425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2162438425
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.1438794614
Short name T198
Test name
Test status
Simulation time 44355724 ps
CPU time 0.7 seconds
Started Aug 05 05:46:58 PM PDT 24
Finished Aug 05 05:46:59 PM PDT 24
Peak memory 201424 kb
Host smart-bf18cefa-f425-46da-b17b-0da7461e0e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438794614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.1438794614
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3531708370
Short name T237
Test name
Test status
Simulation time 55540480 ps
CPU time 0.78 seconds
Started Aug 05 05:47:11 PM PDT 24
Finished Aug 05 05:47:12 PM PDT 24
Peak memory 199112 kb
Host smart-cd062ee4-fd18-4b1c-b115-24fdd38a2786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531708370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3531708370
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3757234637
Short name T502
Test name
Test status
Simulation time 106519487 ps
CPU time 1.07 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 209540 kb
Host smart-524f8cac-34a7-431b-8672-c6e3fbaa2fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757234637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3757234637
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.470261869
Short name T63
Test name
Test status
Simulation time 53319733 ps
CPU time 0.75 seconds
Started Aug 05 05:47:09 PM PDT 24
Finished Aug 05 05:47:10 PM PDT 24
Peak memory 197872 kb
Host smart-c87c68eb-0f9a-4b2c-b448-65e499449139
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470261869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.470261869
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.2404059095
Short name T343
Test name
Test status
Simulation time 53565032 ps
CPU time 0.69 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 199396 kb
Host smart-599f70ad-cd52-4103-a4fa-16194f95d2c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404059095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2404059095
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1017809719
Short name T351
Test name
Test status
Simulation time 25789396 ps
CPU time 0.6 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:20 PM PDT 24
Peak memory 199112 kb
Host smart-d46b7d13-d4c5-45c5-ad8f-5b1f6abbb78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017809719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1017809719
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1123495523
Short name T133
Test name
Test status
Simulation time 52452168 ps
CPU time 0.84 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 199208 kb
Host smart-6dc4c43f-d3d4-4b8c-a648-208e68d02f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123495523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.1123495523
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1168526748
Short name T212
Test name
Test status
Simulation time 166897222 ps
CPU time 0.98 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 198128 kb
Host smart-497bf147-e791-486e-adfd-a39aa735cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168526748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1168526748
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.4054255707
Short name T331
Test name
Test status
Simulation time 43114143 ps
CPU time 0.65 seconds
Started Aug 05 05:47:10 PM PDT 24
Finished Aug 05 05:47:10 PM PDT 24
Peak memory 198052 kb
Host smart-5c82ac3e-aacb-40ee-aeb7-826e8d48ba0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054255707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.4054255707
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1606536873
Short name T221
Test name
Test status
Simulation time 21320423 ps
CPU time 0.6 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 198312 kb
Host smart-25a4cf5f-af1c-4f0e-ad1c-8346aba09d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606536873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1606536873
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.1608712360
Short name T165
Test name
Test status
Simulation time 45277223 ps
CPU time 0.74 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 201396 kb
Host smart-f1401215-ef78-480b-80d1-6f2361026c65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608712360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.1608712360
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.4005940764
Short name T597
Test name
Test status
Simulation time 37211533 ps
CPU time 0.71 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:36 PM PDT 24
Peak memory 199188 kb
Host smart-156f7ed3-4afd-443b-b29e-35c7f6a15d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005940764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.4005940764
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.1590277046
Short name T521
Test name
Test status
Simulation time 117450246 ps
CPU time 0.94 seconds
Started Aug 05 05:47:21 PM PDT 24
Finished Aug 05 05:47:22 PM PDT 24
Peak memory 209516 kb
Host smart-48d3b8f1-3966-4e32-a3d9-3608bb2cd758
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590277046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1590277046
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3492765638
Short name T439
Test name
Test status
Simulation time 61453902 ps
CPU time 0.74 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 197976 kb
Host smart-5c7f0ba8-8f26-4ef2-8908-ed758825a9a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492765638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3492765638
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2418419429
Short name T271
Test name
Test status
Simulation time 56875841 ps
CPU time 0.64 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 198508 kb
Host smart-53b09d5f-2e6f-4dd1-92a9-703d6981a8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418419429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2418419429
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.1348267181
Short name T508
Test name
Test status
Simulation time 24959918 ps
CPU time 0.75 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 198720 kb
Host smart-a8dbfe15-8af3-447c-a7a0-88903613872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348267181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1348267181
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.342354695
Short name T487
Test name
Test status
Simulation time 58046130 ps
CPU time 0.85 seconds
Started Aug 05 05:45:34 PM PDT 24
Finished Aug 05 05:45:34 PM PDT 24
Peak memory 199172 kb
Host smart-72e43f7b-303d-4df2-b02d-1520e6d36795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342354695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.342354695
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.845260673
Short name T624
Test name
Test status
Simulation time 30009341 ps
CPU time 0.66 seconds
Started Aug 05 05:45:35 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 198056 kb
Host smart-a3e87b47-b579-483b-b5e4-5690861f7134
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845260673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_m
alfunc.845260673
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.3345542554
Short name T46
Test name
Test status
Simulation time 165256003 ps
CPU time 1.02 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 198104 kb
Host smart-21ec0f75-8e1f-4917-a1bb-6a776938218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345542554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3345542554
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3289890574
Short name T416
Test name
Test status
Simulation time 54984839 ps
CPU time 0.76 seconds
Started Aug 05 05:45:38 PM PDT 24
Finished Aug 05 05:45:39 PM PDT 24
Peak memory 198080 kb
Host smart-7943606e-29f0-4efd-b51d-59a7865f99a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289890574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3289890574
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.799953568
Short name T449
Test name
Test status
Simulation time 23042926 ps
CPU time 0.62 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 198096 kb
Host smart-41680eed-cf05-434a-909d-3873fba389c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799953568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.799953568
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.948261517
Short name T205
Test name
Test status
Simulation time 53165640 ps
CPU time 0.68 seconds
Started Aug 05 05:45:36 PM PDT 24
Finished Aug 05 05:45:37 PM PDT 24
Peak memory 201020 kb
Host smart-db2af37c-d824-4180-b4e6-d7df6e22f06c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948261517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid
.948261517
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.55562743
Short name T294
Test name
Test status
Simulation time 68070915 ps
CPU time 0.88 seconds
Started Aug 05 05:45:35 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 199056 kb
Host smart-8311dfdb-10ed-4725-b488-c34214adca00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55562743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.55562743
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1695632878
Short name T278
Test name
Test status
Simulation time 169225610 ps
CPU time 0.77 seconds
Started Aug 05 05:45:34 PM PDT 24
Finished Aug 05 05:45:35 PM PDT 24
Peak memory 209500 kb
Host smart-fba99c3a-e5e6-4fe3-8298-aa358ee640bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695632878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1695632878
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2598999618
Short name T20
Test name
Test status
Simulation time 337609259 ps
CPU time 1.21 seconds
Started Aug 05 05:45:33 PM PDT 24
Finished Aug 05 05:45:35 PM PDT 24
Peak memory 216868 kb
Host smart-5fec1e6a-58d5-477a-be93-038b6dc8a5c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598999618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2598999618
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3917902552
Short name T3
Test name
Test status
Simulation time 79410027 ps
CPU time 0.73 seconds
Started Aug 05 05:45:33 PM PDT 24
Finished Aug 05 05:45:34 PM PDT 24
Peak memory 198228 kb
Host smart-d2385bd2-2354-467b-837b-450279597c34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917902552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3917902552
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1328888245
Short name T250
Test name
Test status
Simulation time 30008318 ps
CPU time 0.66 seconds
Started Aug 05 05:45:35 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 198460 kb
Host smart-f296ab80-4dd1-4011-8e3c-94f9801dfee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328888245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1328888245
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2190001584
Short name T167
Test name
Test status
Simulation time 114266042 ps
CPU time 0.67 seconds
Started Aug 05 05:47:09 PM PDT 24
Finished Aug 05 05:47:10 PM PDT 24
Peak memory 198676 kb
Host smart-a1d80d3d-9971-4016-831d-d7e7602d7593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190001584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2190001584
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1885794794
Short name T583
Test name
Test status
Simulation time 30675447 ps
CPU time 0.67 seconds
Started Aug 05 05:47:13 PM PDT 24
Finished Aug 05 05:47:14 PM PDT 24
Peak memory 198080 kb
Host smart-ea9f51c7-40cf-4e48-9884-5822431cb1ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885794794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1885794794
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1706093467
Short name T8
Test name
Test status
Simulation time 69183787 ps
CPU time 0.61 seconds
Started Aug 05 05:47:11 PM PDT 24
Finished Aug 05 05:47:12 PM PDT 24
Peak memory 197940 kb
Host smart-63499ed5-8e5f-4a26-ae8f-6cdcc3272f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706093467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1706093467
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3994010946
Short name T489
Test name
Test status
Simulation time 49924101 ps
CPU time 0.65 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 198120 kb
Host smart-cd464717-f184-4902-9fc8-5b59b95ef200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994010946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3994010946
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1080402716
Short name T174
Test name
Test status
Simulation time 43429779 ps
CPU time 0.74 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:28 PM PDT 24
Peak memory 201400 kb
Host smart-b663c282-9034-4d8d-b608-cdcb6f2c44bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080402716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1080402716
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.2801486364
Short name T330
Test name
Test status
Simulation time 76483087 ps
CPU time 0.68 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 198448 kb
Host smart-c9b0d8a2-122f-45da-80d6-67d73e47cf20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801486364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.2801486364
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1246607309
Short name T567
Test name
Test status
Simulation time 163162981 ps
CPU time 0.8 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 209392 kb
Host smart-44dbe2fe-4d15-4d74-8647-98ced1ea0a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246607309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1246607309
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.3244893252
Short name T514
Test name
Test status
Simulation time 50494747 ps
CPU time 0.75 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 198108 kb
Host smart-641c4a7c-53d2-47d3-ae49-336dc40f1367
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244893252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3244893252
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.3220053991
Short name T423
Test name
Test status
Simulation time 36985944 ps
CPU time 0.67 seconds
Started Aug 05 05:47:03 PM PDT 24
Finished Aug 05 05:47:04 PM PDT 24
Peak memory 199304 kb
Host smart-9957b5a1-f62a-4814-8015-613059152fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220053991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3220053991
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2476777315
Short name T298
Test name
Test status
Simulation time 74876780 ps
CPU time 0.68 seconds
Started Aug 05 05:47:19 PM PDT 24
Finished Aug 05 05:47:20 PM PDT 24
Peak memory 198848 kb
Host smart-29440fd6-cb13-45d4-8849-ae748df4dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476777315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2476777315
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.3015946782
Short name T136
Test name
Test status
Simulation time 127799785 ps
CPU time 0.67 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 199024 kb
Host smart-ae489dd2-88cd-4042-a035-4cb2542c7e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015946782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.3015946782
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2971899598
Short name T563
Test name
Test status
Simulation time 30249708 ps
CPU time 0.64 seconds
Started Aug 05 05:47:06 PM PDT 24
Finished Aug 05 05:47:07 PM PDT 24
Peak memory 197988 kb
Host smart-4ef97765-e703-4973-9336-dbd170c1b514
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971899598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2971899598
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1809626772
Short name T475
Test name
Test status
Simulation time 234915694 ps
CPU time 1.01 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 198440 kb
Host smart-1d9cc660-5a37-462b-a48a-34874d29eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809626772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1809626772
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.825764263
Short name T584
Test name
Test status
Simulation time 28508533 ps
CPU time 0.66 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:15 PM PDT 24
Peak memory 198148 kb
Host smart-e099b8a4-d542-43a8-b921-ed287bc4dbca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825764263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.825764263
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.790785359
Short name T452
Test name
Test status
Simulation time 206876727 ps
CPU time 0.57 seconds
Started Aug 05 05:47:19 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 198112 kb
Host smart-728e6f9c-3e48-43a6-9c10-d6bc2011143d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790785359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.790785359
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2147698772
Short name T184
Test name
Test status
Simulation time 41187948 ps
CPU time 0.74 seconds
Started Aug 05 05:47:01 PM PDT 24
Finished Aug 05 05:47:02 PM PDT 24
Peak memory 201476 kb
Host smart-93fc5a18-eca8-4cfc-aad6-45678df54dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147698772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2147698772
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2246990412
Short name T603
Test name
Test status
Simulation time 47623566 ps
CPU time 0.75 seconds
Started Aug 05 05:47:11 PM PDT 24
Finished Aug 05 05:47:12 PM PDT 24
Peak memory 198396 kb
Host smart-fe8db75e-d90f-4575-a8bd-b56a29011408
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246990412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2246990412
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1584000158
Short name T621
Test name
Test status
Simulation time 121484286 ps
CPU time 0.84 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 209564 kb
Host smart-3802984f-daa0-4aa5-9750-036f7019bc57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584000158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1584000158
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2536571469
Short name T415
Test name
Test status
Simulation time 50939972 ps
CPU time 0.78 seconds
Started Aug 05 05:47:11 PM PDT 24
Finished Aug 05 05:47:12 PM PDT 24
Peak memory 198136 kb
Host smart-5379fbac-497b-4bb8-a5f6-85d466105f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536571469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2536571469
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3808307444
Short name T370
Test name
Test status
Simulation time 78598250 ps
CPU time 0.62 seconds
Started Aug 05 05:47:05 PM PDT 24
Finished Aug 05 05:47:11 PM PDT 24
Peak memory 198540 kb
Host smart-58186574-6aea-4aa9-87d7-11cbb7a52556
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808307444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3808307444
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.2718280621
Short name T499
Test name
Test status
Simulation time 32643677 ps
CPU time 0.79 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 200136 kb
Host smart-29538e61-e25c-41c7-aa6c-1714c19d27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718280621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2718280621
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.545972774
Short name T292
Test name
Test status
Simulation time 72152687 ps
CPU time 0.67 seconds
Started Aug 05 05:47:18 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 198428 kb
Host smart-704098b3-029b-4898-a093-76ee1be1f231
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545972774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.545972774
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2814977522
Short name T586
Test name
Test status
Simulation time 31076605 ps
CPU time 0.67 seconds
Started Aug 05 05:47:14 PM PDT 24
Finished Aug 05 05:47:14 PM PDT 24
Peak memory 198080 kb
Host smart-235e878d-d9f2-4634-8e23-f78331aca932
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814977522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2814977522
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.87511852
Short name T518
Test name
Test status
Simulation time 800815526 ps
CPU time 1.01 seconds
Started Aug 05 05:47:05 PM PDT 24
Finished Aug 05 05:47:06 PM PDT 24
Peak memory 198172 kb
Host smart-cc6e2ac5-9c98-444d-ab61-512d151a981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87511852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.87511852
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.3805391563
Short name T418
Test name
Test status
Simulation time 39311863 ps
CPU time 0.61 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 197360 kb
Host smart-f9fbf6d5-1262-40e6-a1a3-4c83b5ea2d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805391563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3805391563
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.644895973
Short name T371
Test name
Test status
Simulation time 103098077 ps
CPU time 0.63 seconds
Started Aug 05 05:47:08 PM PDT 24
Finished Aug 05 05:47:09 PM PDT 24
Peak memory 198056 kb
Host smart-e5c6726b-2b56-4831-8f8b-771f076de3b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644895973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.644895973
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.1382038301
Short name T196
Test name
Test status
Simulation time 38826592 ps
CPU time 0.71 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 201424 kb
Host smart-cb353b1b-18f1-4ac3-9e2f-aa9d4c0171d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382038301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.1382038301
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.1986172404
Short name T559
Test name
Test status
Simulation time 43341018 ps
CPU time 0.66 seconds
Started Aug 05 05:47:32 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 199188 kb
Host smart-d93ad57d-69a3-42b9-bd03-291e22ccc0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986172404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1986172404
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2944598238
Short name T214
Test name
Test status
Simulation time 108872625 ps
CPU time 1.08 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 209460 kb
Host smart-c8798ceb-29f8-4309-87e3-7b49d9b2167e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944598238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2944598238
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.632209064
Short name T288
Test name
Test status
Simulation time 165829428 ps
CPU time 0.85 seconds
Started Aug 05 05:47:04 PM PDT 24
Finished Aug 05 05:47:05 PM PDT 24
Peak memory 199132 kb
Host smart-4eb555d4-5959-4e0e-814c-125f8aa621c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632209064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.632209064
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.450193007
Short name T287
Test name
Test status
Simulation time 54820267 ps
CPU time 0.63 seconds
Started Aug 05 05:47:02 PM PDT 24
Finished Aug 05 05:47:03 PM PDT 24
Peak memory 198524 kb
Host smart-cc4b679e-bc12-431a-8b1e-bfaba7bc3935
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450193007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.450193007
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.261401320
Short name T266
Test name
Test status
Simulation time 38320490 ps
CPU time 0.67 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 199104 kb
Host smart-14ba88f7-4aa4-4ee0-b960-fb1841c1d05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261401320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.261401320
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3117648934
Short name T300
Test name
Test status
Simulation time 37362427 ps
CPU time 0.59 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:28 PM PDT 24
Peak memory 198048 kb
Host smart-a2631bdb-59e8-4f65-a103-f33bddf77e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117648934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3117648934
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.2290809847
Short name T45
Test name
Test status
Simulation time 161125631 ps
CPU time 1.03 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 198064 kb
Host smart-42463f39-7a96-496c-8cb5-ea298053680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290809847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2290809847
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.93642668
Short name T284
Test name
Test status
Simulation time 63550559 ps
CPU time 0.68 seconds
Started Aug 05 05:47:25 PM PDT 24
Finished Aug 05 05:47:25 PM PDT 24
Peak memory 197256 kb
Host smart-f6e754f4-aab2-4f6e-9de9-99d31b2447fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93642668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.93642668
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.536045111
Short name T303
Test name
Test status
Simulation time 71026082 ps
CPU time 0.59 seconds
Started Aug 05 05:47:26 PM PDT 24
Finished Aug 05 05:47:26 PM PDT 24
Peak memory 198116 kb
Host smart-e2e23add-8a75-447e-be23-2ead81f6d5b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536045111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.536045111
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3974295699
Short name T201
Test name
Test status
Simulation time 39624068 ps
CPU time 0.74 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 201424 kb
Host smart-a0e69e0c-3018-4e78-8a9c-8e5ee4064b35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974295699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3974295699
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1255681011
Short name T598
Test name
Test status
Simulation time 38848264 ps
CPU time 0.76 seconds
Started Aug 05 05:47:22 PM PDT 24
Finished Aug 05 05:47:22 PM PDT 24
Peak memory 198352 kb
Host smart-bd452063-be6a-4218-9d79-fab07839a49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255681011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1255681011
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2386187804
Short name T384
Test name
Test status
Simulation time 147271292 ps
CPU time 0.86 seconds
Started Aug 05 05:47:45 PM PDT 24
Finished Aug 05 05:47:46 PM PDT 24
Peak memory 209404 kb
Host smart-a43a5655-d20f-4fe0-b8a8-ac25afd37b2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386187804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2386187804
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1789416665
Short name T334
Test name
Test status
Simulation time 135802421 ps
CPU time 0.75 seconds
Started Aug 05 05:47:23 PM PDT 24
Finished Aug 05 05:47:26 PM PDT 24
Peak memory 198020 kb
Host smart-9ae04917-9500-471d-a439-746ecb3f5d36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789416665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1789416665
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1532475730
Short name T509
Test name
Test status
Simulation time 30835333 ps
CPU time 0.69 seconds
Started Aug 05 05:47:05 PM PDT 24
Finished Aug 05 05:47:06 PM PDT 24
Peak memory 198540 kb
Host smart-8253184e-be7d-4881-9298-6f56faea425e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532475730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1532475730
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.4133374002
Short name T98
Test name
Test status
Simulation time 44293849 ps
CPU time 0.93 seconds
Started Aug 05 05:47:22 PM PDT 24
Finished Aug 05 05:47:23 PM PDT 24
Peak memory 200768 kb
Host smart-e5dccfd5-f804-4d50-8921-4f5068110de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133374002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4133374002
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2515054521
Short name T372
Test name
Test status
Simulation time 49229237 ps
CPU time 0.87 seconds
Started Aug 05 05:47:22 PM PDT 24
Finished Aug 05 05:47:23 PM PDT 24
Peak memory 198580 kb
Host smart-0cdd166d-88c1-46d3-93bd-1b595c1fb74b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515054521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2515054521
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1760971990
Short name T129
Test name
Test status
Simulation time 40887894 ps
CPU time 0.57 seconds
Started Aug 05 05:47:32 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 197936 kb
Host smart-8818b524-8f03-4d77-9994-e048900e00a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760971990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1760971990
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3383948584
Short name T125
Test name
Test status
Simulation time 315856066 ps
CPU time 0.99 seconds
Started Aug 05 05:47:22 PM PDT 24
Finished Aug 05 05:47:23 PM PDT 24
Peak memory 198092 kb
Host smart-d62bb3e2-be77-40da-b9be-9a413de6895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383948584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3383948584
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1100656408
Short name T573
Test name
Test status
Simulation time 38871959 ps
CPU time 0.64 seconds
Started Aug 05 05:47:26 PM PDT 24
Finished Aug 05 05:47:27 PM PDT 24
Peak memory 198136 kb
Host smart-4cc989c7-e5b1-45d5-bdf1-14c32bea77e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100656408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1100656408
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2040934317
Short name T305
Test name
Test status
Simulation time 73832949 ps
CPU time 0.63 seconds
Started Aug 05 05:47:44 PM PDT 24
Finished Aug 05 05:47:45 PM PDT 24
Peak memory 198076 kb
Host smart-3aa5480a-76fc-4d6f-86b5-3e088483d96a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040934317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2040934317
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.3711735257
Short name T568
Test name
Test status
Simulation time 44526062 ps
CPU time 0.74 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:32 PM PDT 24
Peak memory 201372 kb
Host smart-dbd556e2-4c38-4e3c-b03a-5c60aaef29a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711735257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.3711735257
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.765854774
Short name T543
Test name
Test status
Simulation time 44231625 ps
CPU time 0.74 seconds
Started Aug 05 05:47:12 PM PDT 24
Finished Aug 05 05:47:13 PM PDT 24
Peak memory 198652 kb
Host smart-78b6c20e-2018-4092-a4c1-d0c0340819ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765854774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.765854774
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4188381578
Short name T339
Test name
Test status
Simulation time 173235626 ps
CPU time 0.82 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:47:43 PM PDT 24
Peak memory 209552 kb
Host smart-0c3707e4-d5e1-4f61-9222-834e50397e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188381578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4188381578
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3711838118
Short name T353
Test name
Test status
Simulation time 58978945 ps
CPU time 0.7 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 198040 kb
Host smart-78858d89-1bde-43fe-a5d3-040b3f2be41e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711838118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3711838118
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.3035638589
Short name T216
Test name
Test status
Simulation time 27709963 ps
CPU time 0.65 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:47:43 PM PDT 24
Peak memory 199288 kb
Host smart-4b57b5f5-e245-430f-b667-8d2542b33e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035638589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3035638589
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.50972314
Short name T380
Test name
Test status
Simulation time 24321834 ps
CPU time 0.8 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:28 PM PDT 24
Peak memory 199180 kb
Host smart-d0b00f7a-cca2-4367-86fc-0f36e394acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50972314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.50972314
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3148982017
Short name T158
Test name
Test status
Simulation time 50047949 ps
CPU time 0.8 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:25 PM PDT 24
Peak memory 199140 kb
Host smart-05cf2d24-74fd-4ca3-aa06-8376f396b8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148982017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3148982017
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3068904928
Short name T540
Test name
Test status
Simulation time 32898875 ps
CPU time 0.62 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:27 PM PDT 24
Peak memory 198060 kb
Host smart-eaabc61e-0da0-493e-aa1f-ec21811dd18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068904928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3068904928
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1457138164
Short name T407
Test name
Test status
Simulation time 634953905 ps
CPU time 0.96 seconds
Started Aug 05 05:47:46 PM PDT 24
Finished Aug 05 05:47:47 PM PDT 24
Peak memory 198116 kb
Host smart-27bcd15c-700f-4060-84fe-84c6e71fcb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457138164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1457138164
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.4120051298
Short name T428
Test name
Test status
Simulation time 34921852 ps
CPU time 0.59 seconds
Started Aug 05 05:47:30 PM PDT 24
Finished Aug 05 05:47:31 PM PDT 24
Peak memory 197420 kb
Host smart-cb359a3c-0f1f-4ec0-933b-0bc13bbc67bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120051298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.4120051298
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.956501835
Short name T408
Test name
Test status
Simulation time 31932141 ps
CPU time 0.57 seconds
Started Aug 05 05:47:18 PM PDT 24
Finished Aug 05 05:47:19 PM PDT 24
Peak memory 198044 kb
Host smart-14bb96d0-558f-4066-9819-94039757cdb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956501835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.956501835
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2870772708
Short name T607
Test name
Test status
Simulation time 54591773 ps
CPU time 0.65 seconds
Started Aug 05 05:47:33 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 201380 kb
Host smart-18cc31c8-b964-4d58-8fcf-51889a2434a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870772708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2870772708
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.1505967794
Short name T535
Test name
Test status
Simulation time 76978403 ps
CPU time 0.85 seconds
Started Aug 05 05:47:33 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 199116 kb
Host smart-892d9233-68ed-41fc-8af4-292272607cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505967794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.1505967794
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2212270479
Short name T37
Test name
Test status
Simulation time 109703100 ps
CPU time 1.1 seconds
Started Aug 05 05:47:38 PM PDT 24
Finished Aug 05 05:47:39 PM PDT 24
Peak memory 209500 kb
Host smart-487fa7dd-e932-4d03-b1f7-109827021402
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212270479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2212270479
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.4245808918
Short name T565
Test name
Test status
Simulation time 51499476 ps
CPU time 0.83 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 198100 kb
Host smart-fe312ff2-f6b3-47e2-b4c7-e53d1f033a65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245808918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4245808918
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2153218181
Short name T84
Test name
Test status
Simulation time 40609103 ps
CPU time 0.68 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 199372 kb
Host smart-c3e18ed0-d386-4ea7-99b6-93929816cc0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153218181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2153218181
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.4247375086
Short name T574
Test name
Test status
Simulation time 100839504 ps
CPU time 0.73 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:27 PM PDT 24
Peak memory 198764 kb
Host smart-97bf029a-6c5c-4a33-9d23-23b27a3d37e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247375086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.4247375086
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.845269480
Short name T386
Test name
Test status
Simulation time 69107844 ps
CPU time 0.68 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:48:01 PM PDT 24
Peak memory 198480 kb
Host smart-fd94723e-6691-4204-9e34-88ddd545ddf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845269480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.845269480
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3472854405
Short name T345
Test name
Test status
Simulation time 34782926 ps
CPU time 0.59 seconds
Started Aug 05 05:47:32 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 198024 kb
Host smart-d17287ec-3980-4a4c-8ebe-82bda488cd7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472854405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.3472854405
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3411139929
Short name T272
Test name
Test status
Simulation time 159123802 ps
CPU time 0.96 seconds
Started Aug 05 05:47:30 PM PDT 24
Finished Aug 05 05:47:31 PM PDT 24
Peak memory 198424 kb
Host smart-6f6915d3-1e3e-4de4-82e8-631d7761db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411139929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3411139929
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.4143466804
Short name T457
Test name
Test status
Simulation time 65375681 ps
CPU time 0.66 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 198064 kb
Host smart-8e8e0f9f-281a-49a9-95a7-4073989fada3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143466804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.4143466804
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1014346461
Short name T329
Test name
Test status
Simulation time 29763140 ps
CPU time 0.62 seconds
Started Aug 05 05:47:25 PM PDT 24
Finished Aug 05 05:47:26 PM PDT 24
Peak memory 198108 kb
Host smart-3e90b4ef-5d61-4d5b-81e5-b92e9a585785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014346461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1014346461
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.885087136
Short name T192
Test name
Test status
Simulation time 76806347 ps
CPU time 0.68 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:28 PM PDT 24
Peak memory 201432 kb
Host smart-818289bb-8304-442c-96a4-c56a617e92c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885087136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.885087136
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3172243134
Short name T360
Test name
Test status
Simulation time 81490845 ps
CPU time 0.8 seconds
Started Aug 05 05:47:21 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 198364 kb
Host smart-dd4244e6-86ce-49ec-b15f-c15a23c8dc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172243134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3172243134
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2908889500
Short name T231
Test name
Test status
Simulation time 152280368 ps
CPU time 0.81 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:25 PM PDT 24
Peak memory 209624 kb
Host smart-512bf44d-5583-49c8-b277-4e719dc09a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908889500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2908889500
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1017583460
Short name T469
Test name
Test status
Simulation time 53488887 ps
CPU time 0.78 seconds
Started Aug 05 05:47:20 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 198116 kb
Host smart-2e26ac8d-487e-4b4e-b3a7-5414b211c6d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017583460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1017583460
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.1389262887
Short name T420
Test name
Test status
Simulation time 50898325 ps
CPU time 0.75 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:36 PM PDT 24
Peak memory 198808 kb
Host smart-59579960-27a4-40b4-be7d-74f59a4b1732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389262887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.1389262887
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.911353697
Short name T238
Test name
Test status
Simulation time 28178401 ps
CPU time 0.65 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:47:40 PM PDT 24
Peak memory 198024 kb
Host smart-a1eb26dc-b9e2-4bdd-aa63-ddc09e698ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911353697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.911353697
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2756183113
Short name T283
Test name
Test status
Simulation time 166356090 ps
CPU time 0.95 seconds
Started Aug 05 05:47:29 PM PDT 24
Finished Aug 05 05:47:30 PM PDT 24
Peak memory 198124 kb
Host smart-d5968224-0c79-4e45-b6f4-8f9b28e4c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756183113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2756183113
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.3703127900
Short name T248
Test name
Test status
Simulation time 78285119 ps
CPU time 0.59 seconds
Started Aug 05 05:47:43 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 198056 kb
Host smart-e385c205-2e84-4b18-96db-98c7ac50afb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703127900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3703127900
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2486019775
Short name T366
Test name
Test status
Simulation time 66021756 ps
CPU time 0.56 seconds
Started Aug 05 05:47:46 PM PDT 24
Finished Aug 05 05:47:47 PM PDT 24
Peak memory 198128 kb
Host smart-59ac711a-6638-4f20-bd1c-495468761b2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486019775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2486019775
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.1898202554
Short name T589
Test name
Test status
Simulation time 108530478 ps
CPU time 0.76 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 198448 kb
Host smart-6ff6acce-e6c1-4b89-a63d-b906439f0c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898202554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1898202554
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3194143697
Short name T462
Test name
Test status
Simulation time 165916623 ps
CPU time 0.79 seconds
Started Aug 05 05:47:27 PM PDT 24
Finished Aug 05 05:47:28 PM PDT 24
Peak memory 209560 kb
Host smart-031f762d-4975-4293-95aa-ae51f2bee588
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194143697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3194143697
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1066993302
Short name T369
Test name
Test status
Simulation time 58735513 ps
CPU time 0.79 seconds
Started Aug 05 05:47:38 PM PDT 24
Finished Aug 05 05:47:39 PM PDT 24
Peak memory 198096 kb
Host smart-eb7e1eba-953d-4298-9b02-6a4846655183
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066993302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1066993302
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1430718067
Short name T312
Test name
Test status
Simulation time 33314358 ps
CPU time 0.69 seconds
Started Aug 05 05:47:24 PM PDT 24
Finished Aug 05 05:47:24 PM PDT 24
Peak memory 199400 kb
Host smart-37a1a583-bd66-4e71-8212-0d23ba5eff23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430718067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1430718067
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2079471726
Short name T365
Test name
Test status
Simulation time 50664333 ps
CPU time 0.82 seconds
Started Aug 05 05:47:41 PM PDT 24
Finished Aug 05 05:47:42 PM PDT 24
Peak memory 200120 kb
Host smart-bbd509f3-e5c3-474d-9709-418221c0983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079471726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2079471726
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.2386266110
Short name T348
Test name
Test status
Simulation time 66038031 ps
CPU time 0.78 seconds
Started Aug 05 05:47:30 PM PDT 24
Finished Aug 05 05:47:31 PM PDT 24
Peak memory 199068 kb
Host smart-e7e8bab5-42be-4229-b021-5427be119aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386266110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.2386266110
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2271784672
Short name T131
Test name
Test status
Simulation time 42433680 ps
CPU time 0.59 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 198024 kb
Host smart-45145629-b5ff-4c09-914b-727e3ca5489d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271784672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2271784672
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2336601080
Short name T421
Test name
Test status
Simulation time 689885447 ps
CPU time 0.9 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:47:40 PM PDT 24
Peak memory 198328 kb
Host smart-32d43637-4780-4b5a-bca8-fc291cc68178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336601080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2336601080
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1786815939
Short name T269
Test name
Test status
Simulation time 70062314 ps
CPU time 0.62 seconds
Started Aug 05 05:47:41 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 198036 kb
Host smart-d6786ea3-4dfb-49e8-987b-63b729880e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786815939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1786815939
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.2627405951
Short name T315
Test name
Test status
Simulation time 34956546 ps
CPU time 0.62 seconds
Started Aug 05 05:47:33 PM PDT 24
Finished Aug 05 05:47:34 PM PDT 24
Peak memory 198412 kb
Host smart-37b2991e-b642-495d-8848-a9b66a16aecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627405951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2627405951
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3962484102
Short name T171
Test name
Test status
Simulation time 52410894 ps
CPU time 0.68 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:47:52 PM PDT 24
Peak memory 201372 kb
Host smart-a3d53485-7a66-4577-82d4-9d0740fe8385
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962484102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3962484102
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3742970831
Short name T579
Test name
Test status
Simulation time 61898590 ps
CPU time 0.85 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 199180 kb
Host smart-548e5255-f901-44c2-a771-e44302d4abff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742970831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3742970831
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.3069578249
Short name T364
Test name
Test status
Simulation time 174297575 ps
CPU time 0.84 seconds
Started Aug 05 05:47:33 PM PDT 24
Finished Aug 05 05:47:44 PM PDT 24
Peak memory 209516 kb
Host smart-83b62a94-cc72-4d39-bd54-b7247e15c3b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069578249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3069578249
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3919325726
Short name T410
Test name
Test status
Simulation time 54704807 ps
CPU time 0.8 seconds
Started Aug 05 05:47:30 PM PDT 24
Finished Aug 05 05:47:31 PM PDT 24
Peak memory 199584 kb
Host smart-7e836220-55d1-4eed-8899-cc0f2103fd37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919325726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3919325726
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.2833792069
Short name T398
Test name
Test status
Simulation time 49532975 ps
CPU time 0.69 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 199420 kb
Host smart-cf36eee0-3b14-4e00-9e68-507c4cd174e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833792069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.2833792069
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.3697149521
Short name T578
Test name
Test status
Simulation time 84113259 ps
CPU time 0.93 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:47:40 PM PDT 24
Peak memory 200768 kb
Host smart-bebd9863-c709-457a-84b7-6ad3c7699c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697149521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.3697149521
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3211772671
Short name T560
Test name
Test status
Simulation time 29720723 ps
CPU time 0.66 seconds
Started Aug 05 05:47:43 PM PDT 24
Finished Aug 05 05:47:44 PM PDT 24
Peak memory 198048 kb
Host smart-54f2bf81-bd19-4b5d-ac86-5fdf846cab65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211772671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3211772671
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1558551439
Short name T425
Test name
Test status
Simulation time 310731890 ps
CPU time 1.12 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 198100 kb
Host smart-4eaf3abc-93bf-457b-a2ab-b73d2f24a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558551439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1558551439
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.460112227
Short name T492
Test name
Test status
Simulation time 62431742 ps
CPU time 0.68 seconds
Started Aug 05 05:47:32 PM PDT 24
Finished Aug 05 05:47:33 PM PDT 24
Peak memory 197976 kb
Host smart-552bdd6e-7f77-4e43-98c6-93ba4921a5cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460112227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.460112227
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3170271091
Short name T544
Test name
Test status
Simulation time 47462505 ps
CPU time 0.67 seconds
Started Aug 05 05:47:34 PM PDT 24
Finished Aug 05 05:47:35 PM PDT 24
Peak memory 198088 kb
Host smart-703229c5-89e0-4038-8c73-3a8e84317cad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170271091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3170271091
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2195523698
Short name T81
Test name
Test status
Simulation time 103930850 ps
CPU time 0.65 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:32 PM PDT 24
Peak memory 201388 kb
Host smart-bdd48b3c-da8d-4647-84a6-d7079a033d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195523698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2195523698
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2373471741
Short name T539
Test name
Test status
Simulation time 106453425 ps
CPU time 0.7 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 199168 kb
Host smart-7c323be4-af0a-470c-80cb-759df33f740d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373471741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2373471741
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2819741962
Short name T293
Test name
Test status
Simulation time 104114410 ps
CPU time 1.07 seconds
Started Aug 05 05:47:28 PM PDT 24
Finished Aug 05 05:47:29 PM PDT 24
Peak memory 209524 kb
Host smart-ec55823f-78e5-4786-85c4-b607f79fdef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819741962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2819741962
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1064699000
Short name T528
Test name
Test status
Simulation time 141584142 ps
CPU time 0.68 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:36 PM PDT 24
Peak memory 198104 kb
Host smart-882c3ebc-401e-4f6c-81ea-916d08513bee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064699000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1064699000
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1152997737
Short name T396
Test name
Test status
Simulation time 29650029 ps
CPU time 0.73 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:36 PM PDT 24
Peak memory 199312 kb
Host smart-bedf60e6-24fb-4f46-b87d-57bf804e3cd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152997737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1152997737
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2143583850
Short name T15
Test name
Test status
Simulation time 42191576 ps
CPU time 0.81 seconds
Started Aug 05 05:45:38 PM PDT 24
Finished Aug 05 05:45:39 PM PDT 24
Peak memory 200020 kb
Host smart-c6dcafb6-27bf-4a9f-9464-e6b02423cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143583850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2143583850
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3224063998
Short name T564
Test name
Test status
Simulation time 74773990 ps
CPU time 0.69 seconds
Started Aug 05 05:45:39 PM PDT 24
Finished Aug 05 05:45:40 PM PDT 24
Peak memory 199104 kb
Host smart-bfb8b02e-0a12-4a69-8426-901abaed81be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224063998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.3224063998
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2823845751
Short name T438
Test name
Test status
Simulation time 32072691 ps
CPU time 0.64 seconds
Started Aug 05 05:45:41 PM PDT 24
Finished Aug 05 05:45:42 PM PDT 24
Peak memory 198020 kb
Host smart-8f54a7bd-7bbc-46bd-9ba9-79a0b17675a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823845751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.2823845751
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.593045686
Short name T593
Test name
Test status
Simulation time 163547188 ps
CPU time 0.96 seconds
Started Aug 05 05:45:40 PM PDT 24
Finished Aug 05 05:45:41 PM PDT 24
Peak memory 198144 kb
Host smart-2f99ddff-d28a-417b-a835-3e12fd18ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593045686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.593045686
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.96779793
Short name T324
Test name
Test status
Simulation time 41672214 ps
CPU time 0.62 seconds
Started Aug 05 05:45:43 PM PDT 24
Finished Aug 05 05:45:44 PM PDT 24
Peak memory 198056 kb
Host smart-b89a774a-375c-4f19-87d6-99061bbbcee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96779793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.96779793
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1569030762
Short name T260
Test name
Test status
Simulation time 61266606 ps
CPU time 0.64 seconds
Started Aug 05 05:45:40 PM PDT 24
Finished Aug 05 05:45:41 PM PDT 24
Peak memory 198116 kb
Host smart-1f148964-8c5f-4b1e-b826-efb1cc960510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569030762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1569030762
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.3825899338
Short name T375
Test name
Test status
Simulation time 82545918 ps
CPU time 0.71 seconds
Started Aug 05 05:45:39 PM PDT 24
Finished Aug 05 05:45:40 PM PDT 24
Peak memory 201416 kb
Host smart-2f7858e1-2274-42b9-ae1b-bfb8891b2597
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825899338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.3825899338
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.345227117
Short name T33
Test name
Test status
Simulation time 43315617 ps
CPU time 0.78 seconds
Started Aug 05 05:45:41 PM PDT 24
Finished Aug 05 05:45:42 PM PDT 24
Peak memory 199196 kb
Host smart-fdb002fb-03af-4e60-a21f-e3769a23a05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345227117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.345227117
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1090241280
Short name T39
Test name
Test status
Simulation time 106090975 ps
CPU time 0.96 seconds
Started Aug 05 05:45:43 PM PDT 24
Finished Aug 05 05:45:44 PM PDT 24
Peak memory 209588 kb
Host smart-f17bcd08-cb4d-40da-9c0e-9344837c8918
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090241280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1090241280
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3677948229
Short name T318
Test name
Test status
Simulation time 79533610 ps
CPU time 0.71 seconds
Started Aug 05 05:45:46 PM PDT 24
Finished Aug 05 05:45:47 PM PDT 24
Peak memory 198332 kb
Host smart-5e4def12-aa40-4736-bb28-3e4f76466b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677948229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3677948229
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1975206529
Short name T483
Test name
Test status
Simulation time 58176714 ps
CPU time 0.63 seconds
Started Aug 05 05:45:40 PM PDT 24
Finished Aug 05 05:45:41 PM PDT 24
Peak memory 198500 kb
Host smart-9672a3a7-ec5b-4aba-91b4-0d9bc63636d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975206529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1975206529
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.4263439364
Short name T86
Test name
Test status
Simulation time 123730154 ps
CPU time 0.87 seconds
Started Aug 05 05:45:42 PM PDT 24
Finished Aug 05 05:45:43 PM PDT 24
Peak memory 200084 kb
Host smart-9421c359-2165-4866-a977-77b117be06c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263439364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.4263439364
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2231472966
Short name T31
Test name
Test status
Simulation time 73518339 ps
CPU time 0.66 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:46 PM PDT 24
Peak memory 198488 kb
Host smart-1b8947c9-7bc6-4eb0-96ab-f90d9e9ca078
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231472966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2231472966
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1553831168
Short name T297
Test name
Test status
Simulation time 30780064 ps
CPU time 0.68 seconds
Started Aug 05 05:45:47 PM PDT 24
Finished Aug 05 05:45:48 PM PDT 24
Peak memory 197328 kb
Host smart-dc0388e3-adea-49f7-92db-c7c8e5b9ef0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553831168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1553831168
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.4615561
Short name T277
Test name
Test status
Simulation time 161608705 ps
CPU time 0.97 seconds
Started Aug 05 05:45:46 PM PDT 24
Finished Aug 05 05:45:47 PM PDT 24
Peak memory 198156 kb
Host smart-799352f9-ef33-4eb9-b457-c2012dbb151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4615561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4615561
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.775793452
Short name T401
Test name
Test status
Simulation time 101209609 ps
CPU time 0.63 seconds
Started Aug 05 05:45:48 PM PDT 24
Finished Aug 05 05:45:49 PM PDT 24
Peak memory 198076 kb
Host smart-8e9aefa7-d7e3-42a9-9d2d-0d4d8832094a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775793452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.775793452
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.784068417
Short name T333
Test name
Test status
Simulation time 65638549 ps
CPU time 0.59 seconds
Started Aug 05 05:46:25 PM PDT 24
Finished Aug 05 05:46:25 PM PDT 24
Peak memory 198224 kb
Host smart-30bca01e-ca3c-4cc9-ab8f-5ec81c59ec9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784068417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.784068417
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.155278896
Short name T422
Test name
Test status
Simulation time 115940754 ps
CPU time 0.76 seconds
Started Aug 05 05:45:39 PM PDT 24
Finished Aug 05 05:45:40 PM PDT 24
Peak memory 199112 kb
Host smart-44a0b2fa-b818-4cef-9674-3f8b18176c3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155278896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.155278896
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.4108201524
Short name T354
Test name
Test status
Simulation time 166084776 ps
CPU time 0.76 seconds
Started Aug 05 05:45:44 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 209580 kb
Host smart-8cf8e802-e592-44d8-968a-a474cb27b4e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108201524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.4108201524
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.178721236
Short name T91
Test name
Test status
Simulation time 61691637 ps
CPU time 0.84 seconds
Started Aug 05 05:45:49 PM PDT 24
Finished Aug 05 05:45:50 PM PDT 24
Peak memory 198196 kb
Host smart-63a66822-462b-42a2-8c32-6889751729c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178721236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.178721236
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3442775450
Short name T304
Test name
Test status
Simulation time 31506335 ps
CPU time 0.68 seconds
Started Aug 05 05:45:41 PM PDT 24
Finished Aug 05 05:45:42 PM PDT 24
Peak memory 199416 kb
Host smart-8d21231d-d681-4ede-a1d6-b1330a125d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442775450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3442775450
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2856685715
Short name T548
Test name
Test status
Simulation time 53251426 ps
CPU time 0.77 seconds
Started Aug 05 05:45:44 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 198912 kb
Host smart-690f4030-cbea-4274-9ff9-09cc5eda74d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856685715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2856685715
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.643742592
Short name T160
Test name
Test status
Simulation time 68933030 ps
CPU time 0.71 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:46 PM PDT 24
Peak memory 198340 kb
Host smart-3520ee7a-eccb-49f0-abc8-b7c155cf14df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643742592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.643742592
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2507950787
Short name T225
Test name
Test status
Simulation time 30846040 ps
CPU time 0.61 seconds
Started Aug 05 05:45:49 PM PDT 24
Finished Aug 05 05:45:50 PM PDT 24
Peak memory 198044 kb
Host smart-fcc2e9e5-0d34-43e7-bd67-75aeb08b99e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507950787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2507950787
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.449145451
Short name T387
Test name
Test status
Simulation time 1895963978 ps
CPU time 0.98 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:46 PM PDT 24
Peak memory 198136 kb
Host smart-531d8acb-237c-458f-9ad1-ac25e065319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449145451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.449145451
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3661249680
Short name T302
Test name
Test status
Simulation time 65852791 ps
CPU time 0.68 seconds
Started Aug 05 05:45:46 PM PDT 24
Finished Aug 05 05:45:47 PM PDT 24
Peak memory 198144 kb
Host smart-ace32d1a-a72b-42a2-a8c2-8cbdd4679366
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661249680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3661249680
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.2228555166
Short name T431
Test name
Test status
Simulation time 81202262 ps
CPU time 0.64 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:46 PM PDT 24
Peak memory 198408 kb
Host smart-7a011dfd-45e8-4932-a7bd-e59582c8a081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228555166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2228555166
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1155721465
Short name T199
Test name
Test status
Simulation time 41156712 ps
CPU time 0.75 seconds
Started Aug 05 05:45:53 PM PDT 24
Finished Aug 05 05:45:54 PM PDT 24
Peak memory 201444 kb
Host smart-e1129026-90c2-46b2-818b-5ba2bda4e667
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155721465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1155721465
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.1614004130
Short name T572
Test name
Test status
Simulation time 51036522 ps
CPU time 0.94 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:46 PM PDT 24
Peak memory 199076 kb
Host smart-1d31f094-a371-405c-9a48-916898a53837
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614004130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.1614004130
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2563063720
Short name T259
Test name
Test status
Simulation time 113973391 ps
CPU time 0.87 seconds
Started Aug 05 05:45:44 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 209512 kb
Host smart-c4b95c0d-470f-4e90-9988-969b0b07c245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563063720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2563063720
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.885741173
Short name T471
Test name
Test status
Simulation time 84198195 ps
CPU time 0.87 seconds
Started Aug 05 05:45:48 PM PDT 24
Finished Aug 05 05:45:50 PM PDT 24
Peak memory 199152 kb
Host smart-20a3db99-7479-41bb-a675-cb7f6a23bdf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885741173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.885741173
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3712994478
Short name T82
Test name
Test status
Simulation time 40000014 ps
CPU time 0.65 seconds
Started Aug 05 05:45:45 PM PDT 24
Finished Aug 05 05:45:45 PM PDT 24
Peak memory 198560 kb
Host smart-48f5bfee-54a8-441f-a120-72fe56bc0142
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712994478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3712994478
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3216775219
Short name T361
Test name
Test status
Simulation time 58298963 ps
CPU time 0.71 seconds
Started Aug 05 05:45:55 PM PDT 24
Finished Aug 05 05:45:56 PM PDT 24
Peak memory 198488 kb
Host smart-3775ff29-5a7f-47b4-b8fa-0f5c37366a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216775219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3216775219
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3078198004
Short name T359
Test name
Test status
Simulation time 37830254 ps
CPU time 0.59 seconds
Started Aug 05 05:45:51 PM PDT 24
Finished Aug 05 05:45:52 PM PDT 24
Peak memory 198008 kb
Host smart-6aac3141-5f8b-488e-8981-e0bac85dd52d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078198004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3078198004
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3340369030
Short name T235
Test name
Test status
Simulation time 167801903 ps
CPU time 0.94 seconds
Started Aug 05 05:46:03 PM PDT 24
Finished Aug 05 05:46:04 PM PDT 24
Peak memory 198132 kb
Host smart-43c6a439-2c0a-465f-81ce-5c09b045e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340369030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3340369030
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.809788178
Short name T233
Test name
Test status
Simulation time 95577974 ps
CPU time 0.61 seconds
Started Aug 05 05:45:50 PM PDT 24
Finished Aug 05 05:45:51 PM PDT 24
Peak memory 197332 kb
Host smart-39eec695-0474-49cc-bf16-75deaf220bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809788178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.809788178
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.502179739
Short name T246
Test name
Test status
Simulation time 41170085 ps
CPU time 0.64 seconds
Started Aug 05 05:45:52 PM PDT 24
Finished Aug 05 05:45:53 PM PDT 24
Peak memory 198096 kb
Host smart-1e722392-a28c-4428-85e1-742cc796d551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502179739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.502179739
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2810742916
Short name T189
Test name
Test status
Simulation time 74765653 ps
CPU time 0.65 seconds
Started Aug 05 05:45:54 PM PDT 24
Finished Aug 05 05:45:55 PM PDT 24
Peak memory 201420 kb
Host smart-52570b3e-cf49-4f36-ad6f-3a8053433dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810742916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2810742916
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2828883367
Short name T220
Test name
Test status
Simulation time 71692014 ps
CPU time 0.9 seconds
Started Aug 05 05:45:52 PM PDT 24
Finished Aug 05 05:45:53 PM PDT 24
Peak memory 199116 kb
Host smart-41756c69-ec67-4ab3-832c-61873c54853e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828883367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2828883367
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.558057581
Short name T454
Test name
Test status
Simulation time 109353911 ps
CPU time 0.99 seconds
Started Aug 05 05:45:52 PM PDT 24
Finished Aug 05 05:45:53 PM PDT 24
Peak memory 209532 kb
Host smart-554c70e0-3751-48c3-a559-0618122e8ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558057581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.558057581
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2546428696
Short name T276
Test name
Test status
Simulation time 57746668 ps
CPU time 0.84 seconds
Started Aug 05 05:45:50 PM PDT 24
Finished Aug 05 05:45:51 PM PDT 24
Peak memory 198216 kb
Host smart-b29826f4-daeb-41ff-bd4f-17ffcfa27307
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546428696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2546428696
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.716483166
Short name T80
Test name
Test status
Simulation time 58120862 ps
CPU time 0.65 seconds
Started Aug 05 05:45:49 PM PDT 24
Finished Aug 05 05:45:50 PM PDT 24
Peak memory 199380 kb
Host smart-896d5294-60d9-494a-86dd-ec5546f0b108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716483166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.716483166
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2409545305
Short name T97
Test name
Test status
Simulation time 39971675 ps
CPU time 0.9 seconds
Started Aug 05 05:45:57 PM PDT 24
Finished Aug 05 05:45:58 PM PDT 24
Peak memory 200100 kb
Host smart-4cc77b6c-23d1-4c5f-88c5-08e90faf9b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409545305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2409545305
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2290163869
Short name T208
Test name
Test status
Simulation time 251310189 ps
CPU time 0.69 seconds
Started Aug 05 05:45:57 PM PDT 24
Finished Aug 05 05:45:58 PM PDT 24
Peak memory 199116 kb
Host smart-a7477518-40bb-4ca9-80ab-048fabc6fab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290163869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2290163869
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2413373157
Short name T240
Test name
Test status
Simulation time 30304030 ps
CPU time 0.65 seconds
Started Aug 05 05:45:56 PM PDT 24
Finished Aug 05 05:45:57 PM PDT 24
Peak memory 198052 kb
Host smart-161dd91e-e689-4b69-8827-7b4517d83a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413373157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2413373157
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1610238390
Short name T130
Test name
Test status
Simulation time 164283292 ps
CPU time 0.99 seconds
Started Aug 05 05:45:57 PM PDT 24
Finished Aug 05 05:45:58 PM PDT 24
Peak memory 198208 kb
Host smart-40698e7b-f522-4576-bf10-0a33182ed5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610238390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1610238390
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.3407959733
Short name T22
Test name
Test status
Simulation time 35204457 ps
CPU time 0.61 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:58 PM PDT 24
Peak memory 197272 kb
Host smart-5195e569-73e9-4acb-93e0-ee5e2a942fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407959733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3407959733
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2670806101
Short name T581
Test name
Test status
Simulation time 105739249 ps
CPU time 0.62 seconds
Started Aug 05 05:45:58 PM PDT 24
Finished Aug 05 05:45:59 PM PDT 24
Peak memory 198112 kb
Host smart-3a0be309-5b2f-4602-80bf-2591efca7aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670806101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2670806101
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.2330294519
Short name T195
Test name
Test status
Simulation time 44071647 ps
CPU time 0.71 seconds
Started Aug 05 05:45:55 PM PDT 24
Finished Aug 05 05:45:56 PM PDT 24
Peak memory 201444 kb
Host smart-dd94dd09-1b64-46f7-9d04-a4c4ba55a06c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330294519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.2330294519
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.779988433
Short name T406
Test name
Test status
Simulation time 61266619 ps
CPU time 0.93 seconds
Started Aug 05 05:45:53 PM PDT 24
Finished Aug 05 05:45:54 PM PDT 24
Peak memory 199204 kb
Host smart-e2cd37fc-efeb-4db4-a098-7fc7d6324b57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779988433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.779988433
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2313140082
Short name T460
Test name
Test status
Simulation time 342348859 ps
CPU time 0.81 seconds
Started Aug 05 05:45:57 PM PDT 24
Finished Aug 05 05:45:58 PM PDT 24
Peak memory 209648 kb
Host smart-ac2e5b60-b8f6-4365-b925-d1c7e84015ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313140082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2313140082
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1851204740
Short name T265
Test name
Test status
Simulation time 165803229 ps
CPU time 0.74 seconds
Started Aug 05 05:45:59 PM PDT 24
Finished Aug 05 05:46:00 PM PDT 24
Peak memory 198116 kb
Host smart-9fd4b67e-8205-4849-8708-676fa427c052
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851204740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1851204740
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.1698375806
Short name T243
Test name
Test status
Simulation time 30976367 ps
CPU time 0.68 seconds
Started Aug 05 05:45:53 PM PDT 24
Finished Aug 05 05:45:54 PM PDT 24
Peak memory 198596 kb
Host smart-f7301998-8987-4827-adbe-82a6e791dba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698375806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1698375806
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.191479873
Short name T223
Test name
Test status
Simulation time 117822014 ps
CPU time 0.78 seconds
Started Aug 05 05:45:59 PM PDT 24
Finished Aug 05 05:46:00 PM PDT 24
Peak memory 198600 kb
Host smart-ce3200bf-0370-4c01-a785-1ce6cb4d84e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191479873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.191479873
Directory /workspace/9.pwrmgr_stress_all/latest
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