Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 584 1 T1 9 T2 3 T3 2
auto[1] 500 1 T1 9 T2 3 T3 4


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 583 1 T1 3 T2 3 T3 1
auto[1] 501 1 T1 15 T2 3 T3 5


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 462 1 T1 8 T2 4 T3 4
auto[1] 622 1 T1 10 T2 2 T3 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 912 1 T1 18 T2 4 T3 4
auto[1] 172 1 T2 2 T3 2 T5 2


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 521 1 T1 14 T2 4 T3 4
auto[1] 563 1 T1 4 T2 2 T3 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 603 1 T1 10 T2 4 T3 4
auto[1] 481 1 T1 8 T2 2 T3 2


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 33 1 T2 1 T30 1 T77 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 4 1 T30 1 T165 1 T166 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 33 1 T1 1 T16 1 T38 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 6 1 T48 1 T167 1 T168 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 24 1 T1 1 T30 1 T13 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 3 1 T30 1 T169 1 T50 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 75 1 T14 1 T49 1 T51 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 55 1 T14 1 T49 1 T51 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 18 1 T29 1 T13 1 T61 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 3 1 T61 1 T40 1 T170 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 25 1 T84 1 T92 1 T85 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 6 1 T171 1 T48 1 T172 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 19 1 T16 1 T173 1 T174 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 2 1 T173 1 T175 1 - -
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 31 1 T13 1 T38 1 T41 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 5 1 T41 1 T48 2 T176 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 29 1 T1 2 T3 1 T58 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T3 1 T58 1 - -
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 28 1 T1 2 T15 1 T16 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 3 1 T15 1 T41 1 T177 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 21 1 T1 1 T38 1 T96 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 3 1 T178 1 T179 1 T180 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 36 1 T2 1 T77 1 T16 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 6 1 T2 1 T77 1 T175 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 24 1 T1 1 T30 1 T13 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T181 1 - - - -
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 27 1 T1 1 T13 1 T84 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 6 1 T48 1 T182 1 T183 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 34 1 T5 2 T61 1 T16 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 5 1 T5 1 T61 1 T184 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 16 1 T77 1 T185 1 T171 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 1 1 T77 1 - - - -
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 26 1 T58 1 T84 1 T95 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 3 1 T171 1 T186 1 T187 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 32 1 T1 1 T5 1 T13 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 2 1 T188 1 T142 1 - -
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 20 1 T3 1 T13 1 T16 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 2 1 T189 1 T190 1 - -
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 27 1 T13 1 T85 2 T184 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 5 1 T48 2 T191 1 T192 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 30 1 T2 1 T29 1 T13 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 4 1 T2 1 T29 1 T189 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 21 1 T84 3 T85 1 T86 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 2 1 T188 1 T141 1 - -
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 27 1 T58 1 T40 1 T84 3
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 5 1 T58 1 T40 1 T190 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 28 1 T61 1 T95 1 T189 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 7 1 T173 1 T191 1 T193 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 29 1 T1 1 T2 1 T16 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T194 1 T50 1 - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 34 1 T16 1 T38 2 T84 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 6 1 T48 1 T183 1 T172 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 23 1 T1 1 T3 1 T29 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 3 1 T29 1 T167 1 T181 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 22 1 T5 1 T13 1 T41 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 6 1 T5 1 T41 1 T48 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 34 1 T1 1 T13 1 T92 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 6 1 T184 1 T182 1 T195 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 37 1 T1 4 T3 1 T16 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 5 1 T3 1 T170 1 T165 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 22 1 T95 1 T171 1 T165 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 1 1 T196 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 27 1 T1 1 T58 1 T15 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 2 1 T15 1 T197 1 - -

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