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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 98.23 95.86 99.44 96.00 95.99 100.00 94.60


Total test records in report: 728
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T558 /workspace/coverage/default/41.pwrmgr_reset.2123483368 Aug 07 04:54:08 PM PDT 24 Aug 07 04:54:09 PM PDT 24 28486494 ps
T559 /workspace/coverage/default/44.pwrmgr_global_esc.3147651286 Aug 07 04:54:35 PM PDT 24 Aug 07 04:54:36 PM PDT 24 35053103 ps
T560 /workspace/coverage/default/48.pwrmgr_global_esc.1132560514 Aug 07 04:54:27 PM PDT 24 Aug 07 04:54:28 PM PDT 24 79772301 ps
T561 /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.699197084 Aug 07 04:53:59 PM PDT 24 Aug 07 04:54:00 PM PDT 24 30455314 ps
T153 /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1195577986 Aug 07 04:54:16 PM PDT 24 Aug 07 04:54:17 PM PDT 24 243090615 ps
T562 /workspace/coverage/default/21.pwrmgr_glitch.2080397104 Aug 07 04:53:34 PM PDT 24 Aug 07 04:53:35 PM PDT 24 101683063 ps
T563 /workspace/coverage/default/23.pwrmgr_glitch.1782807802 Aug 07 04:53:56 PM PDT 24 Aug 07 04:53:57 PM PDT 24 48108968 ps
T564 /workspace/coverage/default/46.pwrmgr_lowpower_invalid.2935234946 Aug 07 04:54:20 PM PDT 24 Aug 07 04:54:21 PM PDT 24 44935835 ps
T565 /workspace/coverage/default/48.pwrmgr_aborted_low_power.3706651134 Aug 07 04:54:41 PM PDT 24 Aug 07 04:54:42 PM PDT 24 33081168 ps
T566 /workspace/coverage/default/29.pwrmgr_reset_invalid.3393219197 Aug 07 04:54:04 PM PDT 24 Aug 07 04:54:11 PM PDT 24 168809262 ps
T567 /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1250956088 Aug 07 04:53:05 PM PDT 24 Aug 07 04:53:05 PM PDT 24 28810761 ps
T568 /workspace/coverage/default/11.pwrmgr_aborted_low_power.3421018637 Aug 07 04:53:08 PM PDT 24 Aug 07 04:53:08 PM PDT 24 63910754 ps
T569 /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1334132640 Aug 07 04:54:36 PM PDT 24 Aug 07 04:54:37 PM PDT 24 59936350 ps
T570 /workspace/coverage/default/34.pwrmgr_reset.4175548014 Aug 07 04:53:55 PM PDT 24 Aug 07 04:53:56 PM PDT 24 89628340 ps
T571 /workspace/coverage/default/35.pwrmgr_aborted_low_power.137398088 Aug 07 04:54:10 PM PDT 24 Aug 07 04:54:11 PM PDT 24 28803710 ps
T572 /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2487930071 Aug 07 04:53:00 PM PDT 24 Aug 07 04:53:01 PM PDT 24 67987606 ps
T573 /workspace/coverage/default/25.pwrmgr_glitch.827192398 Aug 07 04:53:48 PM PDT 24 Aug 07 04:53:48 PM PDT 24 63950885 ps
T574 /workspace/coverage/default/6.pwrmgr_aborted_low_power.1400464180 Aug 07 04:53:01 PM PDT 24 Aug 07 04:53:02 PM PDT 24 34809096 ps
T575 /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.925788203 Aug 07 04:54:31 PM PDT 24 Aug 07 04:54:32 PM PDT 24 58403139 ps
T576 /workspace/coverage/default/26.pwrmgr_reset_invalid.1998393375 Aug 07 04:53:58 PM PDT 24 Aug 07 04:53:59 PM PDT 24 145576386 ps
T577 /workspace/coverage/default/14.pwrmgr_escalation_timeout.2176952857 Aug 07 04:53:16 PM PDT 24 Aug 07 04:53:17 PM PDT 24 1074567350 ps
T578 /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3238920644 Aug 07 04:53:09 PM PDT 24 Aug 07 04:53:10 PM PDT 24 28937303 ps
T579 /workspace/coverage/default/21.pwrmgr_global_esc.1230733444 Aug 07 04:53:33 PM PDT 24 Aug 07 04:53:34 PM PDT 24 48943790 ps
T580 /workspace/coverage/default/10.pwrmgr_global_esc.2540103767 Aug 07 04:53:11 PM PDT 24 Aug 07 04:53:12 PM PDT 24 48929370 ps
T581 /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3850566783 Aug 07 04:53:54 PM PDT 24 Aug 07 04:53:55 PM PDT 24 68022590 ps
T582 /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3345599638 Aug 07 04:53:03 PM PDT 24 Aug 07 04:53:04 PM PDT 24 119743089 ps
T583 /workspace/coverage/default/38.pwrmgr_aborted_low_power.672138383 Aug 07 04:54:17 PM PDT 24 Aug 07 04:54:18 PM PDT 24 53847324 ps
T50 /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.185394478 Aug 07 04:54:30 PM PDT 24 Aug 07 04:54:30 PM PDT 24 98782228 ps
T584 /workspace/coverage/default/43.pwrmgr_reset.1374147900 Aug 07 04:54:10 PM PDT 24 Aug 07 04:54:11 PM PDT 24 26967830 ps
T585 /workspace/coverage/default/27.pwrmgr_aborted_low_power.3665961510 Aug 07 04:54:06 PM PDT 24 Aug 07 04:54:07 PM PDT 24 181609495 ps
T586 /workspace/coverage/default/41.pwrmgr_glitch.3728942844 Aug 07 04:54:09 PM PDT 24 Aug 07 04:54:11 PM PDT 24 172019023 ps
T587 /workspace/coverage/default/4.pwrmgr_smoke.1430725857 Aug 07 04:52:57 PM PDT 24 Aug 07 04:52:58 PM PDT 24 28385465 ps
T588 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4117301498 Aug 07 04:54:36 PM PDT 24 Aug 07 04:54:36 PM PDT 24 32239456 ps
T589 /workspace/coverage/default/49.pwrmgr_aborted_low_power.1104028784 Aug 07 04:54:54 PM PDT 24 Aug 07 04:54:55 PM PDT 24 118716010 ps
T590 /workspace/coverage/default/46.pwrmgr_reset.1707393748 Aug 07 04:54:37 PM PDT 24 Aug 07 04:54:37 PM PDT 24 108076134 ps
T591 /workspace/coverage/default/4.pwrmgr_global_esc.3797267291 Aug 07 04:53:00 PM PDT 24 Aug 07 04:53:01 PM PDT 24 44394209 ps
T592 /workspace/coverage/default/23.pwrmgr_aborted_low_power.861904107 Aug 07 04:53:45 PM PDT 24 Aug 07 04:53:45 PM PDT 24 48795854 ps
T593 /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1328235921 Aug 07 04:54:26 PM PDT 24 Aug 07 04:54:27 PM PDT 24 139128843 ps
T594 /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3118937230 Aug 07 04:54:06 PM PDT 24 Aug 07 04:54:07 PM PDT 24 104951456 ps
T595 /workspace/coverage/default/0.pwrmgr_global_esc.3818994356 Aug 07 04:52:55 PM PDT 24 Aug 07 04:52:56 PM PDT 24 49032643 ps
T596 /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.4201850228 Aug 07 04:52:50 PM PDT 24 Aug 07 04:52:51 PM PDT 24 46246991 ps
T597 /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3662661313 Aug 07 04:53:21 PM PDT 24 Aug 07 04:53:22 PM PDT 24 50097378 ps
T598 /workspace/coverage/default/25.pwrmgr_reset_invalid.3837815977 Aug 07 04:53:54 PM PDT 24 Aug 07 04:53:55 PM PDT 24 152911908 ps
T599 /workspace/coverage/default/20.pwrmgr_escalation_timeout.891708067 Aug 07 04:53:43 PM PDT 24 Aug 07 04:53:44 PM PDT 24 304452498 ps
T600 /workspace/coverage/default/40.pwrmgr_glitch.1551797389 Aug 07 04:54:15 PM PDT 24 Aug 07 04:54:16 PM PDT 24 39801074 ps
T601 /workspace/coverage/default/18.pwrmgr_smoke.2098830764 Aug 07 04:53:32 PM PDT 24 Aug 07 04:53:33 PM PDT 24 53336919 ps
T602 /workspace/coverage/default/10.pwrmgr_glitch.1640250235 Aug 07 04:53:13 PM PDT 24 Aug 07 04:53:14 PM PDT 24 93477334 ps
T603 /workspace/coverage/default/17.pwrmgr_glitch.4062902927 Aug 07 04:53:13 PM PDT 24 Aug 07 04:53:13 PM PDT 24 50276690 ps
T196 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2589044150 Aug 07 04:53:43 PM PDT 24 Aug 07 04:53:44 PM PDT 24 38156858 ps
T604 /workspace/coverage/default/46.pwrmgr_glitch.940056903 Aug 07 04:54:37 PM PDT 24 Aug 07 04:54:38 PM PDT 24 55349622 ps
T605 /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.53791576 Aug 07 04:54:14 PM PDT 24 Aug 07 04:54:15 PM PDT 24 32450118 ps
T606 /workspace/coverage/default/15.pwrmgr_glitch.2367869252 Aug 07 04:53:40 PM PDT 24 Aug 07 04:53:41 PM PDT 24 54588133 ps
T607 /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3087371507 Aug 07 04:53:51 PM PDT 24 Aug 07 04:53:51 PM PDT 24 31470738 ps
T608 /workspace/coverage/default/47.pwrmgr_aborted_low_power.3654962791 Aug 07 04:54:43 PM PDT 24 Aug 07 04:54:44 PM PDT 24 35759345 ps
T609 /workspace/coverage/default/24.pwrmgr_aborted_low_power.4123347221 Aug 07 04:53:43 PM PDT 24 Aug 07 04:53:44 PM PDT 24 40448025 ps
T610 /workspace/coverage/default/22.pwrmgr_smoke.1720179993 Aug 07 04:53:16 PM PDT 24 Aug 07 04:53:17 PM PDT 24 70204453 ps
T611 /workspace/coverage/default/2.pwrmgr_smoke.280188167 Aug 07 04:52:53 PM PDT 24 Aug 07 04:52:54 PM PDT 24 29513385 ps
T612 /workspace/coverage/default/14.pwrmgr_reset_invalid.2038924985 Aug 07 04:53:09 PM PDT 24 Aug 07 04:53:10 PM PDT 24 102187311 ps
T613 /workspace/coverage/default/44.pwrmgr_reset.2311384785 Aug 07 04:54:39 PM PDT 24 Aug 07 04:54:40 PM PDT 24 67971355 ps
T614 /workspace/coverage/default/1.pwrmgr_global_esc.1859346821 Aug 07 04:52:39 PM PDT 24 Aug 07 04:52:40 PM PDT 24 113188772 ps
T615 /workspace/coverage/default/17.pwrmgr_reset.2494832297 Aug 07 04:53:11 PM PDT 24 Aug 07 04:53:12 PM PDT 24 63430613 ps
T616 /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1531683614 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:03 PM PDT 24 36853968 ps
T617 /workspace/coverage/default/5.pwrmgr_aborted_low_power.1203817799 Aug 07 04:52:48 PM PDT 24 Aug 07 04:52:49 PM PDT 24 36562701 ps
T24 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.410096416 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:14 PM PDT 24 106676230 ps
T65 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.875157465 Aug 07 04:49:49 PM PDT 24 Aug 07 04:49:50 PM PDT 24 169833362 ps
T57 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3040239264 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:14 PM PDT 24 67465437 ps
T25 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.645027931 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:18 PM PDT 24 450703460 ps
T26 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2906309959 Aug 07 04:48:42 PM PDT 24 Aug 07 04:48:44 PM PDT 24 489205910 ps
T54 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1779204879 Aug 07 04:48:17 PM PDT 24 Aug 07 04:48:19 PM PDT 24 187436392 ps
T53 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.880667834 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 174420447 ps
T115 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1045791312 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:37 PM PDT 24 31525255 ps
T116 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4250727467 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:33 PM PDT 24 29166137 ps
T66 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1898316981 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:46 PM PDT 24 52539774 ps
T67 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2479138052 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:15 PM PDT 24 35812492 ps
T129 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.752211526 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:15 PM PDT 24 21372759 ps
T155 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.2773729194 Aug 07 04:48:26 PM PDT 24 Aug 07 04:48:27 PM PDT 24 22488416 ps
T117 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1678245067 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:15 PM PDT 24 27805765 ps
T102 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2303100134 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:36 PM PDT 24 19220320 ps
T118 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2634802217 Aug 07 04:48:16 PM PDT 24 Aug 07 04:48:17 PM PDT 24 122849812 ps
T156 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1293180639 Aug 07 04:49:52 PM PDT 24 Aug 07 04:49:53 PM PDT 24 15972760 ps
T119 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1408828708 Aug 07 04:48:42 PM PDT 24 Aug 07 04:48:43 PM PDT 24 79845843 ps
T157 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.311026080 Aug 07 04:48:31 PM PDT 24 Aug 07 04:48:32 PM PDT 24 31421742 ps
T618 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.906198014 Aug 07 04:48:38 PM PDT 24 Aug 07 04:48:39 PM PDT 24 21639893 ps
T55 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1818049495 Aug 07 04:48:12 PM PDT 24 Aug 07 04:48:14 PM PDT 24 1193197990 ps
T120 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3398083738 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 67216117 ps
T121 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3763534338 Aug 07 04:48:27 PM PDT 24 Aug 07 04:48:28 PM PDT 24 61133653 ps
T56 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.4174944455 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:36 PM PDT 24 128202891 ps
T619 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3809646952 Aug 07 04:48:10 PM PDT 24 Aug 07 04:48:11 PM PDT 24 38970818 ps
T62 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3968899029 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:38 PM PDT 24 129241640 ps
T158 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.921170330 Aug 07 04:48:21 PM PDT 24 Aug 07 04:48:22 PM PDT 24 38388146 ps
T63 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4017571827 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:33 PM PDT 24 149886639 ps
T620 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.249473607 Aug 07 04:48:29 PM PDT 24 Aug 07 04:48:30 PM PDT 24 22739811 ps
T159 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3840218548 Aug 07 04:48:12 PM PDT 24 Aug 07 04:48:12 PM PDT 24 35101007 ps
T621 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.4037803873 Aug 07 04:48:22 PM PDT 24 Aug 07 04:48:23 PM PDT 24 115500769 ps
T103 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.4077448436 Aug 07 04:48:16 PM PDT 24 Aug 07 04:48:17 PM PDT 24 33294745 ps
T122 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.773127378 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 28429605 ps
T64 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1724281033 Aug 07 04:48:11 PM PDT 24 Aug 07 04:48:12 PM PDT 24 59908513 ps
T622 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.921211502 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:47 PM PDT 24 45696046 ps
T146 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.987496120 Aug 07 04:48:12 PM PDT 24 Aug 07 04:48:13 PM PDT 24 442128186 ps
T70 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2604349155 Aug 07 04:48:12 PM PDT 24 Aug 07 04:48:14 PM PDT 24 422611211 ps
T123 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1859970295 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:46 PM PDT 24 38582299 ps
T623 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1343954236 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 45304534 ps
T624 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.4167880627 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:46 PM PDT 24 45539335 ps
T625 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.778710930 Aug 07 04:48:25 PM PDT 24 Aug 07 04:48:26 PM PDT 24 19105929 ps
T71 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2879975815 Aug 07 04:48:29 PM PDT 24 Aug 07 04:48:30 PM PDT 24 492206180 ps
T104 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.846513815 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:13 PM PDT 24 56423379 ps
T105 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1410372248 Aug 07 04:48:33 PM PDT 24 Aug 07 04:48:33 PM PDT 24 24693808 ps
T106 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1136761705 Aug 07 04:48:25 PM PDT 24 Aug 07 04:48:26 PM PDT 24 30159199 ps
T626 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2251852532 Aug 07 04:48:03 PM PDT 24 Aug 07 04:48:04 PM PDT 24 33832147 ps
T627 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2938167702 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:47 PM PDT 24 77726104 ps
T147 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2242743987 Aug 07 04:48:37 PM PDT 24 Aug 07 04:48:39 PM PDT 24 301368249 ps
T628 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2595975364 Aug 07 04:48:25 PM PDT 24 Aug 07 04:48:25 PM PDT 24 19063852 ps
T629 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3217792277 Aug 07 04:48:49 PM PDT 24 Aug 07 04:48:50 PM PDT 24 20425155 ps
T630 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.249744388 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:17 PM PDT 24 50629078 ps
T631 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3679283217 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:37 PM PDT 24 20980601 ps
T632 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1923943385 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:32 PM PDT 24 17707623 ps
T130 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2570905698 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:46 PM PDT 24 67226217 ps
T633 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.351917609 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 451528586 ps
T634 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.792363321 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:32 PM PDT 24 45792044 ps
T635 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.108083597 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 111839243 ps
T636 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.90104911 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:41 PM PDT 24 48684433 ps
T637 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4055042282 Aug 07 04:48:08 PM PDT 24 Aug 07 04:48:09 PM PDT 24 42872911 ps
T638 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2241684661 Aug 07 04:48:11 PM PDT 24 Aug 07 04:48:12 PM PDT 24 41696296 ps
T639 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3299467762 Aug 07 04:48:38 PM PDT 24 Aug 07 04:48:40 PM PDT 24 56783454 ps
T640 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2736340364 Aug 07 04:48:18 PM PDT 24 Aug 07 04:48:20 PM PDT 24 52426848 ps
T131 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2561601587 Aug 07 04:48:27 PM PDT 24 Aug 07 04:48:29 PM PDT 24 511996710 ps
T641 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2149183536 Aug 07 04:48:22 PM PDT 24 Aug 07 04:48:22 PM PDT 24 41080312 ps
T132 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2391088447 Aug 07 04:48:26 PM PDT 24 Aug 07 04:48:27 PM PDT 24 38319713 ps
T642 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3261825170 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:14 PM PDT 24 51603827 ps
T643 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3466292938 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:14 PM PDT 24 28358216 ps
T644 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3502670645 Aug 07 04:48:18 PM PDT 24 Aug 07 04:48:19 PM PDT 24 29315080 ps
T645 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.506911094 Aug 07 04:48:35 PM PDT 24 Aug 07 04:48:35 PM PDT 24 116950815 ps
T145 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2315105594 Aug 07 04:48:41 PM PDT 24 Aug 07 04:48:43 PM PDT 24 316773396 ps
T72 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3671699042 Aug 07 04:48:26 PM PDT 24 Aug 07 04:48:27 PM PDT 24 242688920 ps
T646 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2247615235 Aug 07 04:48:17 PM PDT 24 Aug 07 04:48:18 PM PDT 24 413553060 ps
T647 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3239576947 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:41 PM PDT 24 19927992 ps
T648 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3500441874 Aug 07 04:48:43 PM PDT 24 Aug 07 04:48:44 PM PDT 24 166794156 ps
T649 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2689330882 Aug 07 04:48:37 PM PDT 24 Aug 07 04:48:39 PM PDT 24 129455983 ps
T650 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.460420229 Aug 07 04:48:31 PM PDT 24 Aug 07 04:48:34 PM PDT 24 222947241 ps
T651 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4073743186 Aug 07 04:48:27 PM PDT 24 Aug 07 04:48:28 PM PDT 24 88680207 ps
T652 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1189528181 Aug 07 04:48:42 PM PDT 24 Aug 07 04:48:44 PM PDT 24 79171745 ps
T653 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3169978679 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:33 PM PDT 24 221346006 ps
T654 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3647149747 Aug 07 04:48:04 PM PDT 24 Aug 07 04:48:06 PM PDT 24 758053779 ps
T68 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1149776379 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:16 PM PDT 24 443735744 ps
T107 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1323760651 Aug 07 04:48:28 PM PDT 24 Aug 07 04:48:29 PM PDT 24 33586811 ps
T655 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.855102672 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:31 PM PDT 24 118597384 ps
T656 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1794289548 Aug 07 04:48:31 PM PDT 24 Aug 07 04:48:32 PM PDT 24 128028431 ps
T657 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2341149654 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 26526553 ps
T658 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.737507678 Aug 07 04:48:09 PM PDT 24 Aug 07 04:48:10 PM PDT 24 224708885 ps
T659 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.968314731 Aug 07 04:48:10 PM PDT 24 Aug 07 04:48:11 PM PDT 24 43516839 ps
T108 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1192463921 Aug 07 04:48:16 PM PDT 24 Aug 07 04:48:17 PM PDT 24 19743836 ps
T660 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2011756225 Aug 07 04:48:31 PM PDT 24 Aug 07 04:48:32 PM PDT 24 18178760 ps
T661 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2384869182 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:45 PM PDT 24 19618117 ps
T662 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1905096871 Aug 07 04:48:51 PM PDT 24 Aug 07 04:48:52 PM PDT 24 50919314 ps
T663 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.88718173 Aug 07 04:48:44 PM PDT 24 Aug 07 04:48:45 PM PDT 24 63152782 ps
T664 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.122458012 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:48 PM PDT 24 44376170 ps
T665 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.980348063 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 59952882 ps
T666 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.339429082 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:41 PM PDT 24 18612995 ps
T667 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3905232394 Aug 07 04:48:27 PM PDT 24 Aug 07 04:48:29 PM PDT 24 365910928 ps
T668 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.319516992 Aug 07 04:48:15 PM PDT 24 Aug 07 04:48:16 PM PDT 24 156406745 ps
T669 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.4160416019 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:36 PM PDT 24 39190280 ps
T670 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.612612488 Aug 07 04:48:35 PM PDT 24 Aug 07 04:48:36 PM PDT 24 134382876 ps
T671 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2312229127 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:37 PM PDT 24 36747771 ps
T672 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3775905581 Aug 07 04:48:42 PM PDT 24 Aug 07 04:48:43 PM PDT 24 19676075 ps
T673 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.950375320 Aug 07 04:48:33 PM PDT 24 Aug 07 04:48:35 PM PDT 24 137360489 ps
T674 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.215789367 Aug 07 04:48:50 PM PDT 24 Aug 07 04:48:50 PM PDT 24 25089279 ps
T675 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2175231485 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:37 PM PDT 24 33356148 ps
T676 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3818498676 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:41 PM PDT 24 87220266 ps
T677 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2164637138 Aug 07 04:48:47 PM PDT 24 Aug 07 04:48:48 PM PDT 24 18788750 ps
T678 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.22225033 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:34 PM PDT 24 212647641 ps
T679 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.234549497 Aug 07 04:48:26 PM PDT 24 Aug 07 04:48:27 PM PDT 24 27044099 ps
T109 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1812191934 Aug 07 04:48:24 PM PDT 24 Aug 07 04:48:25 PM PDT 24 19253362 ps
T680 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.4135901999 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:33 PM PDT 24 38800248 ps
T681 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3871521954 Aug 07 04:48:35 PM PDT 24 Aug 07 04:48:36 PM PDT 24 35088774 ps
T682 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.25176134 Aug 07 04:48:17 PM PDT 24 Aug 07 04:48:19 PM PDT 24 204500957 ps
T683 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1917319274 Aug 07 04:48:32 PM PDT 24 Aug 07 04:48:35 PM PDT 24 572073912 ps
T110 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1458012849 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 22675552 ps
T684 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.417766634 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:41 PM PDT 24 36531572 ps
T685 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.337540243 Aug 07 04:48:27 PM PDT 24 Aug 07 04:48:27 PM PDT 24 64161820 ps
T69 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2357942912 Aug 07 04:48:22 PM PDT 24 Aug 07 04:48:23 PM PDT 24 549750186 ps
T686 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.509776151 Aug 07 04:48:49 PM PDT 24 Aug 07 04:48:50 PM PDT 24 87587985 ps
T687 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.776476780 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:31 PM PDT 24 46414433 ps
T688 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2445893718 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:15 PM PDT 24 27342700 ps
T689 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1108519028 Aug 07 04:48:24 PM PDT 24 Aug 07 04:48:25 PM PDT 24 24000358 ps
T690 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3548446793 Aug 07 04:48:37 PM PDT 24 Aug 07 04:48:38 PM PDT 24 54215760 ps
T691 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1682208645 Aug 07 04:48:38 PM PDT 24 Aug 07 04:48:39 PM PDT 24 39088505 ps
T692 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2158896620 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 17568594 ps
T693 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3390021871 Aug 07 04:48:04 PM PDT 24 Aug 07 04:48:05 PM PDT 24 31335634 ps
T694 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3242816457 Aug 07 04:48:41 PM PDT 24 Aug 07 04:48:42 PM PDT 24 140071304 ps
T695 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.725925708 Aug 07 04:48:11 PM PDT 24 Aug 07 04:48:13 PM PDT 24 52503355 ps
T696 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.136488428 Aug 07 04:48:36 PM PDT 24 Aug 07 04:48:37 PM PDT 24 20547282 ps
T697 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1396615787 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:36 PM PDT 24 452067288 ps
T698 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.411408807 Aug 07 04:48:44 PM PDT 24 Aug 07 04:48:45 PM PDT 24 89097438 ps
T699 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2324946379 Aug 07 04:48:23 PM PDT 24 Aug 07 04:48:24 PM PDT 24 467627295 ps
T700 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.533850422 Aug 07 04:48:38 PM PDT 24 Aug 07 04:48:39 PM PDT 24 26858545 ps
T701 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.4252608389 Aug 07 04:48:54 PM PDT 24 Aug 07 04:48:55 PM PDT 24 26482631 ps
T702 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2146418319 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:32 PM PDT 24 437894391 ps
T703 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2460307601 Aug 07 04:48:38 PM PDT 24 Aug 07 04:48:39 PM PDT 24 19948269 ps
T111 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3474232508 Aug 07 04:48:10 PM PDT 24 Aug 07 04:48:11 PM PDT 24 22713462 ps
T704 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4004015404 Aug 07 04:48:14 PM PDT 24 Aug 07 04:48:17 PM PDT 24 542489525 ps
T705 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.493162850 Aug 07 04:48:30 PM PDT 24 Aug 07 04:48:31 PM PDT 24 33154685 ps
T112 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3151482693 Aug 07 04:48:31 PM PDT 24 Aug 07 04:48:33 PM PDT 24 331258813 ps
T706 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.830988806 Aug 07 04:48:08 PM PDT 24 Aug 07 04:48:09 PM PDT 24 30145695 ps
T114 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3631849475 Aug 07 04:48:45 PM PDT 24 Aug 07 04:48:46 PM PDT 24 18301741 ps
T707 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2407106028 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:43 PM PDT 24 48803905 ps
T708 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1803419372 Aug 07 04:48:09 PM PDT 24 Aug 07 04:48:10 PM PDT 24 40855710 ps
T709 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2144323785 Aug 07 04:48:16 PM PDT 24 Aug 07 04:48:18 PM PDT 24 100579336 ps
T710 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3611701035 Aug 07 04:48:33 PM PDT 24 Aug 07 04:48:35 PM PDT 24 30762482 ps
T711 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.739987096 Aug 07 04:48:23 PM PDT 24 Aug 07 04:48:23 PM PDT 24 20678937 ps
T712 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2993099998 Aug 07 04:48:29 PM PDT 24 Aug 07 04:48:31 PM PDT 24 43841534 ps
T713 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2878769437 Aug 07 04:48:26 PM PDT 24 Aug 07 04:48:26 PM PDT 24 32912171 ps
T714 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1549507475 Aug 07 04:48:23 PM PDT 24 Aug 07 04:48:24 PM PDT 24 83350657 ps
T715 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2944857038 Aug 07 04:48:19 PM PDT 24 Aug 07 04:48:20 PM PDT 24 36733050 ps
T716 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2121095459 Aug 07 04:48:24 PM PDT 24 Aug 07 04:48:25 PM PDT 24 125386075 ps
T717 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1505538402 Aug 07 04:48:13 PM PDT 24 Aug 07 04:48:13 PM PDT 24 38308363 ps
T718 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.26083228 Aug 07 04:48:20 PM PDT 24 Aug 07 04:48:22 PM PDT 24 107294909 ps
T719 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1335525684 Aug 07 04:48:41 PM PDT 24 Aug 07 04:48:42 PM PDT 24 18973985 ps
T720 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.274429391 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:42 PM PDT 24 37662760 ps
T721 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.206353581 Aug 07 04:48:23 PM PDT 24 Aug 07 04:48:24 PM PDT 24 71835915 ps
T722 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2096939737 Aug 07 04:48:19 PM PDT 24 Aug 07 04:48:20 PM PDT 24 79691633 ps
T73 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.290776378 Aug 07 04:48:16 PM PDT 24 Aug 07 04:48:18 PM PDT 24 178473330 ps
T723 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1689813683 Aug 07 04:48:43 PM PDT 24 Aug 07 04:48:44 PM PDT 24 75608531 ps
T724 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1821377765 Aug 07 04:48:42 PM PDT 24 Aug 07 04:48:43 PM PDT 24 44132787 ps
T113 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.38552362 Aug 07 04:48:40 PM PDT 24 Aug 07 04:48:40 PM PDT 24 34314723 ps
T725 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3420205717 Aug 07 04:48:34 PM PDT 24 Aug 07 04:48:35 PM PDT 24 54043883 ps
T726 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3948659498 Aug 07 04:48:43 PM PDT 24 Aug 07 04:48:44 PM PDT 24 104486716 ps
T727 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1532150629 Aug 07 04:48:28 PM PDT 24 Aug 07 04:48:31 PM PDT 24 653725500 ps
T728 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.357390790 Aug 07 04:48:47 PM PDT 24 Aug 07 04:48:48 PM PDT 24 42822019 ps

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2497780596
Short name T5
Test name
Test status
Simulation time 39534717 ps
CPU time 0.74 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:55 PM PDT 24
Peak memory 201344 kb
Host smart-5699029d-8f98-4986-85fd-6aea01981473
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497780596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2497780596
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.276069429
Short name T6
Test name
Test status
Simulation time 102853626 ps
CPU time 1.11 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 209340 kb
Host smart-9ffff565-3c12-4ed8-96d0-03b9cf4bae45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276069429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.276069429
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.518638481
Short name T14
Test name
Test status
Simulation time 37469542 ps
CPU time 0.62 seconds
Started Aug 07 04:53:21 PM PDT 24
Finished Aug 07 04:53:21 PM PDT 24
Peak memory 199400 kb
Host smart-2ac76978-0a10-4be9-8990-3814d46250fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518638481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.518638481
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.4287054134
Short name T13
Test name
Test status
Simulation time 29357307 ps
CPU time 0.88 seconds
Started Aug 07 04:54:14 PM PDT 24
Finished Aug 07 04:54:15 PM PDT 24
Peak memory 200680 kb
Host smart-abbeaee7-870a-4baf-8ba8-1af670777ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287054134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.4287054134
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2906309959
Short name T26
Test name
Test status
Simulation time 489205910 ps
CPU time 1.47 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 200548 kb
Host smart-af1355db-8854-4375-bc4f-7b14dce11bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906309959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2906309959
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2919683677
Short name T22
Test name
Test status
Simulation time 378534997 ps
CPU time 1.21 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:56 PM PDT 24
Peak memory 216804 kb
Host smart-81705683-509e-45c6-8b25-b10a1360fcae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919683677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2919683677
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2186345823
Short name T23
Test name
Test status
Simulation time 55171899 ps
CPU time 0.79 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 198532 kb
Host smart-009b8d76-b2b6-42ce-a48a-86a0f97ac01d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186345823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2186345823
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.3655353444
Short name T48
Test name
Test status
Simulation time 120021437 ps
CPU time 0.96 seconds
Started Aug 07 04:53:21 PM PDT 24
Finished Aug 07 04:53:22 PM PDT 24
Peak memory 199476 kb
Host smart-e279c924-18eb-45e4-87a0-8ff1c317609d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655353444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3655353444
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.645027931
Short name T25
Test name
Test status
Simulation time 450703460 ps
CPU time 2.43 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:18 PM PDT 24
Peak memory 200632 kb
Host smart-280e63b6-dbaf-4f20-ade2-3d138fe78be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645027931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.645027931
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.3050007545
Short name T41
Test name
Test status
Simulation time 57413798 ps
CPU time 0.75 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:05 PM PDT 24
Peak memory 198320 kb
Host smart-f16802b9-9ed4-420b-915f-28ba6d43b3f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050007545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3050007545
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.4260569465
Short name T16
Test name
Test status
Simulation time 67622514 ps
CPU time 0.89 seconds
Started Aug 07 04:54:23 PM PDT 24
Finished Aug 07 04:54:24 PM PDT 24
Peak memory 200616 kb
Host smart-503a8ce1-ccbb-4826-b2f4-4425c917bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260569465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4260569465
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1293180639
Short name T156
Test name
Test status
Simulation time 15972760 ps
CPU time 0.6 seconds
Started Aug 07 04:49:52 PM PDT 24
Finished Aug 07 04:49:53 PM PDT 24
Peak memory 194864 kb
Host smart-fc5860a0-43bf-42c1-beb8-44fff93b3581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293180639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1293180639
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.47804675
Short name T140
Test name
Test status
Simulation time 64144249 ps
CPU time 0.72 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 198952 kb
Host smart-f2212116-d604-44aa-a9b2-1aa5f7a611b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47804675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disab
le_rom_integrity_check.47804675
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.173541315
Short name T87
Test name
Test status
Simulation time 34233336 ps
CPU time 0.61 seconds
Started Aug 07 04:54:16 PM PDT 24
Finished Aug 07 04:54:17 PM PDT 24
Peak memory 197216 kb
Host smart-19e89a27-de8a-4b3c-a2ed-1fe7c7a199f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173541315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.173541315
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.185394478
Short name T50
Test name
Test status
Simulation time 98782228 ps
CPU time 0.66 seconds
Started Aug 07 04:54:30 PM PDT 24
Finished Aug 07 04:54:30 PM PDT 24
Peak memory 198064 kb
Host smart-6b7b475e-59b5-4b1e-8799-7f5c749d669a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185394478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wa
keup_race.185394478
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.307929461
Short name T189
Test name
Test status
Simulation time 41012149 ps
CPU time 0.68 seconds
Started Aug 07 04:53:58 PM PDT 24
Finished Aug 07 04:53:59 PM PDT 24
Peak memory 201360 kb
Host smart-d7ff293a-68dc-4e68-904a-10c560e93540
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307929461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.307929461
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1323760651
Short name T107
Test name
Test status
Simulation time 33586811 ps
CPU time 0.65 seconds
Started Aug 07 04:48:28 PM PDT 24
Finished Aug 07 04:48:29 PM PDT 24
Peak memory 197200 kb
Host smart-fdd88ff2-e80f-4414-87d6-305677228450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323760651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1323760651
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2337727689
Short name T58
Test name
Test status
Simulation time 39954565 ps
CPU time 0.72 seconds
Started Aug 07 04:54:24 PM PDT 24
Finished Aug 07 04:54:24 PM PDT 24
Peak memory 201292 kb
Host smart-e94f324d-d764-4321-b531-b8f218ea8fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337727689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2337727689
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2579063127
Short name T77
Test name
Test status
Simulation time 244010153 ps
CPU time 0.67 seconds
Started Aug 07 04:52:41 PM PDT 24
Finished Aug 07 04:52:42 PM PDT 24
Peak memory 201232 kb
Host smart-9a325ad1-c98b-4eb5-a0f1-c09ca3aef635
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579063127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2579063127
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3979437998
Short name T128
Test name
Test status
Simulation time 79995702 ps
CPU time 0.67 seconds
Started Aug 07 04:53:11 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 198168 kb
Host smart-585af4ca-1507-4fce-8e94-014555f7b0a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979437998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.3979437998
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1069612956
Short name T160
Test name
Test status
Simulation time 57654032 ps
CPU time 0.67 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 199104 kb
Host smart-093abf7c-f037-46a4-abe1-be41c5a3f4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069612956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.1069612956
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1724281033
Short name T64
Test name
Test status
Simulation time 59908513 ps
CPU time 1.05 seconds
Started Aug 07 04:48:11 PM PDT 24
Finished Aug 07 04:48:12 PM PDT 24
Peak memory 195324 kb
Host smart-3e8e2baa-317f-4d10-8329-6502322051ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724281033 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1724281033
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1983354406
Short name T280
Test name
Test status
Simulation time 37926553 ps
CPU time 1.22 seconds
Started Aug 07 04:52:58 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 200788 kb
Host smart-a031f5fd-fcf9-499c-903b-998b6856bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983354406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1983354406
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889796149
Short name T199
Test name
Test status
Simulation time 86075411 ps
CPU time 0.78 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 199316 kb
Host smart-b4a20d21-4900-4c1d-aa3c-74ca01555241
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889796149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1889796149
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.191042441
Short name T144
Test name
Test status
Simulation time 158573752 ps
CPU time 0.88 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:19 PM PDT 24
Peak memory 200620 kb
Host smart-c3493ccc-7020-4eb4-a397-b93abd6964f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191042441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.191042441
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3226853724
Short name T170
Test name
Test status
Simulation time 82404136 ps
CPU time 0.68 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 201268 kb
Host smart-68f96da2-1a54-43b9-9784-85af055927f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226853724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3226853724
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2693247920
Short name T178
Test name
Test status
Simulation time 74310268 ps
CPU time 0.72 seconds
Started Aug 07 04:52:52 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 201080 kb
Host smart-db6bf4e9-c478-4c38-9a1a-74a229032885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693247920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2693247920
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.3341497433
Short name T149
Test name
Test status
Simulation time 66765249 ps
CPU time 0.71 seconds
Started Aug 07 04:54:00 PM PDT 24
Finished Aug 07 04:54:01 PM PDT 24
Peak memory 199048 kb
Host smart-242ab99f-bad9-46c6-838f-76de13b63552
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341497433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.3341497433
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.2650174717
Short name T188
Test name
Test status
Simulation time 40373721 ps
CPU time 0.7 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:15 PM PDT 24
Peak memory 201308 kb
Host smart-82595dbd-4b54-46e6-83ec-bd90ea714649
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650174717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.2650174717
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.4143629203
Short name T44
Test name
Test status
Simulation time 64969782 ps
CPU time 0.82 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 198436 kb
Host smart-69a3dfbe-522b-44f1-8b0e-d00cf389c770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143629203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.4143629203
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3033757264
Short name T173
Test name
Test status
Simulation time 49038842 ps
CPU time 0.67 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:09 PM PDT 24
Peak memory 201336 kb
Host smart-47143d9b-b5cc-48b7-91be-78ae95653257
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033757264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3033757264
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.2163768757
Short name T181
Test name
Test status
Simulation time 44555176 ps
CPU time 0.72 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 201104 kb
Host smart-1f7b9227-ab3f-4670-8b5f-4734910ee9c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163768757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.2163768757
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.290776378
Short name T73
Test name
Test status
Simulation time 178473330 ps
CPU time 1.66 seconds
Started Aug 07 04:48:16 PM PDT 24
Finished Aug 07 04:48:18 PM PDT 24
Peak memory 195288 kb
Host smart-b0acb613-6803-4c0e-8a86-2908f64e4df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290776378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.
290776378
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3151482693
Short name T112
Test name
Test status
Simulation time 331258813 ps
CPU time 2.09 seconds
Started Aug 07 04:48:31 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 195144 kb
Host smart-1120d251-f96a-4721-b2e5-eb7c0b8f9083
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151482693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
151482693
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3398083738
Short name T120
Test name
Test status
Simulation time 67216117 ps
CPU time 0.85 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 194992 kb
Host smart-4add5734-75ba-4640-8f5a-1263efb4369c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398083738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.3398083738
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2988870446
Short name T96
Test name
Test status
Simulation time 53394557 ps
CPU time 0.95 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 200008 kb
Host smart-ce3901ee-a772-4285-91b0-f8bf53171de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988870446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2988870446
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2480568691
Short name T17
Test name
Test status
Simulation time 63181885 ps
CPU time 0.65 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:05 PM PDT 24
Peak memory 197976 kb
Host smart-4dfa7d6d-33bc-4dbb-942c-b6065420e78d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480568691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2480568691
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3679283217
Short name T631
Test name
Test status
Simulation time 20980601 ps
CPU time 0.64 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:37 PM PDT 24
Peak memory 194940 kb
Host smart-43da92bb-7f1e-4b16-94d6-6fca4d73d169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679283217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3679283217
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3686348132
Short name T80
Test name
Test status
Simulation time 62329252 ps
CPU time 0.64 seconds
Started Aug 07 04:52:52 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 198424 kb
Host smart-8510b09b-f448-49b1-8b03-52aad6600326
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686348132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3686348132
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1937207242
Short name T166
Test name
Test status
Simulation time 72929839 ps
CPU time 0.68 seconds
Started Aug 07 04:53:20 PM PDT 24
Finished Aug 07 04:53:21 PM PDT 24
Peak memory 201252 kb
Host smart-c40581d9-5c2e-431a-b5ce-a4b1f9b0017c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937207242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1937207242
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.1075012109
Short name T15
Test name
Test status
Simulation time 38637528 ps
CPU time 0.68 seconds
Started Aug 07 04:53:20 PM PDT 24
Finished Aug 07 04:53:20 PM PDT 24
Peak memory 198440 kb
Host smart-44826b81-36a5-4444-91a0-eb9ea53324ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075012109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.1075012109
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.4167752485
Short name T171
Test name
Test status
Simulation time 49376787 ps
CPU time 0.66 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 201304 kb
Host smart-be8cd845-ce16-40e6-9dc4-45cbfef689b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167752485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.4167752485
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2589044150
Short name T196
Test name
Test status
Simulation time 38156858 ps
CPU time 0.74 seconds
Started Aug 07 04:53:43 PM PDT 24
Finished Aug 07 04:53:44 PM PDT 24
Peak memory 201356 kb
Host smart-9a2c4967-90ad-4dd7-9270-2dc083e4db35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589044150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2589044150
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.4161325586
Short name T152
Test name
Test status
Simulation time 65646067 ps
CPU time 0.72 seconds
Started Aug 07 04:54:35 PM PDT 24
Finished Aug 07 04:54:35 PM PDT 24
Peak memory 199044 kb
Host smart-b2859a1c-2624-42c8-83c9-670779876cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161325586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.4161325586
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.725925708
Short name T695
Test name
Test status
Simulation time 52503355 ps
CPU time 1.44 seconds
Started Aug 07 04:48:11 PM PDT 24
Finished Aug 07 04:48:13 PM PDT 24
Peak memory 198116 kb
Host smart-76fd81e8-b30b-485e-8559-0f0bf7b041c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725925708 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.725925708
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1149776379
Short name T68
Test name
Test status
Simulation time 443735744 ps
CPU time 1.61 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 200556 kb
Host smart-ca4d1576-b5af-4b7c-b799-f715b4835568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149776379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1149776379
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2445893718
Short name T688
Test name
Test status
Simulation time 27342700 ps
CPU time 0.87 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 194980 kb
Host smart-f2a28522-6a3f-49ba-9f69-d2f7065b296e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445893718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
445893718
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2479138052
Short name T67
Test name
Test status
Simulation time 35812492 ps
CPU time 0.64 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 195024 kb
Host smart-7fc4e5e0-1c0c-48fd-aaa0-6dd3b4f6ebaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479138052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
479138052
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1794289548
Short name T656
Test name
Test status
Simulation time 128028431 ps
CPU time 0.97 seconds
Started Aug 07 04:48:31 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 196104 kb
Host smart-b28e6635-9fb2-480a-8876-0b25148a726f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794289548 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1794289548
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.846513815
Short name T104
Test name
Test status
Simulation time 56423379 ps
CPU time 0.67 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:13 PM PDT 24
Peak memory 195008 kb
Host smart-21a9586b-4989-4a9f-8eca-2b76f85b38fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846513815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.846513815
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2944857038
Short name T715
Test name
Test status
Simulation time 36733050 ps
CPU time 1.64 seconds
Started Aug 07 04:48:19 PM PDT 24
Finished Aug 07 04:48:20 PM PDT 24
Peak memory 196540 kb
Host smart-62afdf60-6f4a-4957-9435-e7d33259b685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944857038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.2944857038
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.26083228
Short name T718
Test name
Test status
Simulation time 107294909 ps
CPU time 1.13 seconds
Started Aug 07 04:48:20 PM PDT 24
Finished Aug 07 04:48:22 PM PDT 24
Peak memory 200212 kb
Host smart-a89e6f5d-0219-4cf7-b2c8-72c7600a1b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26083228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.26083228
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.612612488
Short name T670
Test name
Test status
Simulation time 134382876 ps
CPU time 1.02 seconds
Started Aug 07 04:48:35 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 194924 kb
Host smart-6099936b-ac92-4b11-b65d-fc21b743a631
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612612488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.612612488
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1532150629
Short name T727
Test name
Test status
Simulation time 653725500 ps
CPU time 2.15 seconds
Started Aug 07 04:48:28 PM PDT 24
Finished Aug 07 04:48:31 PM PDT 24
Peak memory 195120 kb
Host smart-b4019e45-988e-441f-8a25-41e18ee955bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532150629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.1
532150629
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.830988806
Short name T706
Test name
Test status
Simulation time 30145695 ps
CPU time 0.66 seconds
Started Aug 07 04:48:08 PM PDT 24
Finished Aug 07 04:48:09 PM PDT 24
Peak memory 197532 kb
Host smart-86fbf3e1-8d45-4845-becc-ce70a667e5e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830988806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.830988806
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.950375320
Short name T673
Test name
Test status
Simulation time 137360489 ps
CPU time 1.21 seconds
Started Aug 07 04:48:33 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 200636 kb
Host smart-ada47be8-1153-4aa4-ab92-28f10715b35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950375320 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.950375320
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.739987096
Short name T711
Test name
Test status
Simulation time 20678937 ps
CPU time 0.62 seconds
Started Aug 07 04:48:23 PM PDT 24
Finished Aug 07 04:48:23 PM PDT 24
Peak memory 194968 kb
Host smart-9ccf7c19-094b-40b9-aeaa-52af6ff55be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739987096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.739987096
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3040239264
Short name T57
Test name
Test status
Simulation time 67465437 ps
CPU time 0.87 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 199908 kb
Host smart-690676aa-36a4-4bd5-993e-a5696984d868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040239264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3040239264
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2993099998
Short name T712
Test name
Test status
Simulation time 43841534 ps
CPU time 1.89 seconds
Started Aug 07 04:48:29 PM PDT 24
Finished Aug 07 04:48:31 PM PDT 24
Peak memory 196368 kb
Host smart-4cf9aeeb-458c-4580-aa52-03a433ce1a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993099998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2993099998
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2324946379
Short name T699
Test name
Test status
Simulation time 467627295 ps
CPU time 1.19 seconds
Started Aug 07 04:48:23 PM PDT 24
Finished Aug 07 04:48:24 PM PDT 24
Peak memory 195332 kb
Host smart-9ede8ed0-c1fc-47b6-9e40-62491561f4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324946379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.2324946379
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.38552362
Short name T113
Test name
Test status
Simulation time 34314723 ps
CPU time 0.65 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:40 PM PDT 24
Peak memory 194980 kb
Host smart-bbfcd847-4510-4513-8d55-fdbf8c42c67b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38552362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.38552362
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.921170330
Short name T158
Test name
Test status
Simulation time 38388146 ps
CPU time 0.6 seconds
Started Aug 07 04:48:21 PM PDT 24
Finished Aug 07 04:48:22 PM PDT 24
Peak memory 194968 kb
Host smart-ed791500-bd8e-43a7-8f79-a330729529c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921170330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.921170330
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2096939737
Short name T722
Test name
Test status
Simulation time 79691633 ps
CPU time 0.71 seconds
Started Aug 07 04:48:19 PM PDT 24
Finished Aug 07 04:48:20 PM PDT 24
Peak memory 195072 kb
Host smart-b67e1440-b622-4c6e-b1c5-57b28b823b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096939737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.2096939737
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.460420229
Short name T650
Test name
Test status
Simulation time 222947241 ps
CPU time 2.56 seconds
Started Aug 07 04:48:31 PM PDT 24
Finished Aug 07 04:48:34 PM PDT 24
Peak memory 198464 kb
Host smart-6ada80e7-0e04-4e04-902d-d8a98c91ac5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460420229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.460420229
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.737507678
Short name T658
Test name
Test status
Simulation time 224708885 ps
CPU time 1.09 seconds
Started Aug 07 04:48:09 PM PDT 24
Finished Aug 07 04:48:10 PM PDT 24
Peak memory 195280 kb
Host smart-c2d80eca-282e-48dc-84ea-2254be92a758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737507678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.737507678
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.206353581
Short name T721
Test name
Test status
Simulation time 71835915 ps
CPU time 0.83 seconds
Started Aug 07 04:48:23 PM PDT 24
Finished Aug 07 04:48:24 PM PDT 24
Peak memory 195196 kb
Host smart-f4969863-0510-403d-957b-889bc6f6d981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206353581 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.206353581
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.4160416019
Short name T669
Test name
Test status
Simulation time 39190280 ps
CPU time 0.66 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 197332 kb
Host smart-8bb0484c-7439-4295-b2c2-7cc5c30fef89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160416019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.4160416019
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2149183536
Short name T641
Test name
Test status
Simulation time 41080312 ps
CPU time 0.6 seconds
Started Aug 07 04:48:22 PM PDT 24
Finished Aug 07 04:48:22 PM PDT 24
Peak memory 195036 kb
Host smart-63db8065-3ff0-4665-8cf1-bb612492695f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149183536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2149183536
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1045791312
Short name T115
Test name
Test status
Simulation time 31525255 ps
CPU time 0.76 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:37 PM PDT 24
Peak memory 197276 kb
Host smart-68f78c0c-4bfd-4f38-b2ff-18ede305995f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045791312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1045791312
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2146418319
Short name T702
Test name
Test status
Simulation time 437894391 ps
CPU time 2.38 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 196416 kb
Host smart-c9acc01d-8d23-4986-a883-a188b8776dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146418319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2146418319
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.987496120
Short name T146
Test name
Test status
Simulation time 442128186 ps
CPU time 1.14 seconds
Started Aug 07 04:48:12 PM PDT 24
Finished Aug 07 04:48:13 PM PDT 24
Peak memory 200548 kb
Host smart-12dd398c-98c5-47a2-aac2-4ba4cc0f2da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987496120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err
.987496120
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3871521954
Short name T681
Test name
Test status
Simulation time 35088774 ps
CPU time 0.88 seconds
Started Aug 07 04:48:35 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 195152 kb
Host smart-97ca1d94-5705-4c79-8c48-8d2e51a716f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871521954 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3871521954
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2341149654
Short name T657
Test name
Test status
Simulation time 26526553 ps
CPU time 0.62 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 197260 kb
Host smart-ddc304e1-d8d0-407d-ab36-1621982726fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341149654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2341149654
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3818498676
Short name T676
Test name
Test status
Simulation time 87220266 ps
CPU time 0.6 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:41 PM PDT 24
Peak memory 195012 kb
Host smart-085313ae-d3fe-4117-8362-ed25449c74b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818498676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3818498676
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2878769437
Short name T713
Test name
Test status
Simulation time 32912171 ps
CPU time 0.76 seconds
Started Aug 07 04:48:26 PM PDT 24
Finished Aug 07 04:48:26 PM PDT 24
Peak memory 194996 kb
Host smart-4b5beb8b-8716-41f3-b0dc-060e3ccfc99d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878769437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2878769437
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1917319274
Short name T683
Test name
Test status
Simulation time 572073912 ps
CPU time 2.51 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 197572 kb
Host smart-c83b85ca-e921-41df-9b1b-be036d11071b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917319274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.1917319274
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3948659498
Short name T726
Test name
Test status
Simulation time 104486716 ps
CPU time 1.17 seconds
Started Aug 07 04:48:43 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 199940 kb
Host smart-0711619f-9afb-46ae-a58e-9edc6ffeca97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948659498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.3948659498
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.980348063
Short name T665
Test name
Test status
Simulation time 59952882 ps
CPU time 0.69 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 195208 kb
Host smart-8f8605e0-370d-4476-9ff3-58b361306791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980348063 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.980348063
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3631849475
Short name T114
Test name
Test status
Simulation time 18301741 ps
CPU time 0.65 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 195040 kb
Host smart-7cd176ed-a848-49d9-9f1e-3506eb8c84eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631849475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3631849475
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.311026080
Short name T157
Test name
Test status
Simulation time 31421742 ps
CPU time 0.65 seconds
Started Aug 07 04:48:31 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 194960 kb
Host smart-9511e7af-dd50-4df7-a2b0-dbe1272e8f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311026080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.311026080
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2689330882
Short name T649
Test name
Test status
Simulation time 129455983 ps
CPU time 0.9 seconds
Started Aug 07 04:48:37 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 198568 kb
Host smart-685e839d-a41d-4d57-9aa8-5a89c1edde84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689330882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2689330882
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.4174944455
Short name T56
Test name
Test status
Simulation time 128202891 ps
CPU time 1.94 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 196368 kb
Host smart-56016985-649b-4c3d-ad04-247b6a6c2c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174944455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.4174944455
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2242743987
Short name T147
Test name
Test status
Simulation time 301368249 ps
CPU time 1.51 seconds
Started Aug 07 04:48:37 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 195268 kb
Host smart-8eea650c-a258-4dcf-9cc8-73fc1ad40c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242743987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.2242743987
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4073743186
Short name T651
Test name
Test status
Simulation time 88680207 ps
CPU time 0.85 seconds
Started Aug 07 04:48:27 PM PDT 24
Finished Aug 07 04:48:28 PM PDT 24
Peak memory 200448 kb
Host smart-19131854-188e-4fe7-95d6-874113a75c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073743186 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.4073743186
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3239576947
Short name T647
Test name
Test status
Simulation time 19927992 ps
CPU time 0.71 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:41 PM PDT 24
Peak memory 197168 kb
Host smart-cd6acc20-0d57-42be-a1d8-00ba7d4106bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239576947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3239576947
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3242816457
Short name T694
Test name
Test status
Simulation time 140071304 ps
CPU time 0.62 seconds
Started Aug 07 04:48:41 PM PDT 24
Finished Aug 07 04:48:42 PM PDT 24
Peak memory 195016 kb
Host smart-9c753b44-4483-427e-8811-406ca1e8c2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242816457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3242816457
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3611701035
Short name T710
Test name
Test status
Simulation time 30762482 ps
CPU time 0.9 seconds
Started Aug 07 04:48:33 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 198572 kb
Host smart-f12b718f-98f4-40fe-9091-e1c2d6d60d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611701035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3611701035
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3905232394
Short name T667
Test name
Test status
Simulation time 365910928 ps
CPU time 1.88 seconds
Started Aug 07 04:48:27 PM PDT 24
Finished Aug 07 04:48:29 PM PDT 24
Peak memory 196412 kb
Host smart-05245de8-910a-4c2f-8955-a49d0c835258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905232394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3905232394
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2315105594
Short name T145
Test name
Test status
Simulation time 316773396 ps
CPU time 1.61 seconds
Started Aug 07 04:48:41 PM PDT 24
Finished Aug 07 04:48:43 PM PDT 24
Peak memory 200388 kb
Host smart-b3034ddb-2ad0-4cb2-bdb3-4c98dba0e65e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315105594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.2315105594
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.4135901999
Short name T680
Test name
Test status
Simulation time 38800248 ps
CPU time 0.99 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 195468 kb
Host smart-dac7564f-5e88-47dd-aa84-b6b07e0156b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135901999 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.4135901999
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.4037803873
Short name T621
Test name
Test status
Simulation time 115500769 ps
CPU time 0.65 seconds
Started Aug 07 04:48:22 PM PDT 24
Finished Aug 07 04:48:23 PM PDT 24
Peak memory 194968 kb
Host smart-ad53d8db-4ef2-4820-aa0e-3b55fd54d9ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037803873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.4037803873
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1343954236
Short name T623
Test name
Test status
Simulation time 45304534 ps
CPU time 0.67 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 194884 kb
Host smart-663d5319-7e44-4a5f-9278-e8f8e1f4efb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343954236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1343954236
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1859970295
Short name T123
Test name
Test status
Simulation time 38582299 ps
CPU time 0.88 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 198316 kb
Host smart-898c938c-8328-4955-8b2d-d392e01c67a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859970295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1859970295
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2561601587
Short name T131
Test name
Test status
Simulation time 511996710 ps
CPU time 2.35 seconds
Started Aug 07 04:48:27 PM PDT 24
Finished Aug 07 04:48:29 PM PDT 24
Peak memory 197300 kb
Host smart-6112ee71-4204-4ca5-9a04-9687ed1d026e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561601587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.2561601587
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3169978679
Short name T653
Test name
Test status
Simulation time 221346006 ps
CPU time 1.08 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 200668 kb
Host smart-2ae4f36c-8c74-4459-adcf-70e6c1d3ff5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169978679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3169978679
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.509776151
Short name T686
Test name
Test status
Simulation time 87587985 ps
CPU time 0.94 seconds
Started Aug 07 04:48:49 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 195176 kb
Host smart-66d30eda-3db6-44b3-9269-73531385f326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509776151 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.509776151
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2175231485
Short name T675
Test name
Test status
Simulation time 33356148 ps
CPU time 0.62 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:37 PM PDT 24
Peak memory 197156 kb
Host smart-20b7a4b1-ad05-402f-9584-bf3e72c92bfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175231485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2175231485
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.778710930
Short name T625
Test name
Test status
Simulation time 19105929 ps
CPU time 0.62 seconds
Started Aug 07 04:48:25 PM PDT 24
Finished Aug 07 04:48:26 PM PDT 24
Peak memory 194936 kb
Host smart-fc791855-e9c7-4be4-9829-ef45e8025e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778710930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.778710930
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1689813683
Short name T723
Test name
Test status
Simulation time 75608531 ps
CPU time 0.78 seconds
Started Aug 07 04:48:43 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 195008 kb
Host smart-5c9430b4-daae-48a4-9653-30c90b4d7a5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689813683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1689813683
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.274429391
Short name T720
Test name
Test status
Simulation time 37662760 ps
CPU time 1.62 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:42 PM PDT 24
Peak memory 197608 kb
Host smart-a3d2585b-f8f6-40a7-bbfe-b3d98c65272c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274429391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.274429391
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1779204879
Short name T54
Test name
Test status
Simulation time 187436392 ps
CPU time 1.62 seconds
Started Aug 07 04:48:17 PM PDT 24
Finished Aug 07 04:48:19 PM PDT 24
Peak memory 200588 kb
Host smart-df04ef9f-8794-43f8-9d5f-e81e55f583ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779204879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.1779204879
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.880667834
Short name T53
Test name
Test status
Simulation time 174420447 ps
CPU time 1.28 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 197720 kb
Host smart-5d99b960-7d26-4a46-b817-37489dc87f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880667834 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.880667834
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2303100134
Short name T102
Test name
Test status
Simulation time 19220320 ps
CPU time 0.65 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 197180 kb
Host smart-2b88d3a2-0f13-44af-95b9-b8fe58ea5d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303100134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2303100134
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.493162850
Short name T705
Test name
Test status
Simulation time 33154685 ps
CPU time 0.62 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:31 PM PDT 24
Peak memory 194948 kb
Host smart-24305b02-1abd-40f3-8984-07b9c600b2a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493162850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.493162850
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4250727467
Short name T116
Test name
Test status
Simulation time 29166137 ps
CPU time 0.75 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 195164 kb
Host smart-d6413ac0-0724-4a12-88c6-6aef9939de68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250727467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.4250727467
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.122458012
Short name T664
Test name
Test status
Simulation time 44376170 ps
CPU time 1.92 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:48 PM PDT 24
Peak memory 196312 kb
Host smart-6993e615-ff69-40fe-b8e3-c0ab60ca5b51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122458012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.122458012
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3500441874
Short name T648
Test name
Test status
Simulation time 166794156 ps
CPU time 1.53 seconds
Started Aug 07 04:48:43 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 200428 kb
Host smart-c82a5add-93ac-44b3-bff9-433ff054b45b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500441874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3500441874
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.776476780
Short name T687
Test name
Test status
Simulation time 46414433 ps
CPU time 1.18 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:31 PM PDT 24
Peak memory 196328 kb
Host smart-35a62b75-d134-4a76-96e5-efc528cafd13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776476780 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.776476780
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1408828708
Short name T119
Test name
Test status
Simulation time 79845843 ps
CPU time 0.68 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:43 PM PDT 24
Peak memory 197292 kb
Host smart-0cd270c1-9b08-459a-9ec6-37ed03acc4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408828708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1408828708
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2938167702
Short name T627
Test name
Test status
Simulation time 77726104 ps
CPU time 0.59 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:47 PM PDT 24
Peak memory 194936 kb
Host smart-5189c533-5fc4-45e9-bdac-8d6a5c5be664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938167702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2938167702
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.411408807
Short name T698
Test name
Test status
Simulation time 89097438 ps
CPU time 0.7 seconds
Started Aug 07 04:48:44 PM PDT 24
Finished Aug 07 04:48:45 PM PDT 24
Peak memory 197348 kb
Host smart-203a28bb-6500-4650-a0c9-d502d4384471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411408807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.411408807
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4017571827
Short name T63
Test name
Test status
Simulation time 149886639 ps
CPU time 2.17 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 196360 kb
Host smart-69c2c4e7-009a-4267-9db7-67f683605151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017571827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.4017571827
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1396615787
Short name T697
Test name
Test status
Simulation time 452067288 ps
CPU time 1.52 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:36 PM PDT 24
Peak memory 195264 kb
Host smart-7687f78c-3886-428f-b487-efbadd6e38e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396615787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.1396615787
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2570905698
Short name T130
Test name
Test status
Simulation time 67226217 ps
CPU time 0.86 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 195220 kb
Host smart-9211ee38-088a-4d6e-930c-3a652a5a1013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570905698 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2570905698
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1458012849
Short name T110
Test name
Test status
Simulation time 22675552 ps
CPU time 0.69 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 197272 kb
Host smart-f01f6938-2ea0-4cb5-ba2b-659847068011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458012849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1458012849
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1821377765
Short name T724
Test name
Test status
Simulation time 44132787 ps
CPU time 0.6 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:43 PM PDT 24
Peak memory 195032 kb
Host smart-f2a8831c-ed08-43c8-9010-05eebbcb984d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821377765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1821377765
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1189528181
Short name T652
Test name
Test status
Simulation time 79171745 ps
CPU time 0.93 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 198288 kb
Host smart-d555db4b-ae3b-46e5-8a95-ddb83d59f276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189528181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1189528181
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2407106028
Short name T707
Test name
Test status
Simulation time 48803905 ps
CPU time 2.21 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:43 PM PDT 24
Peak memory 197444 kb
Host smart-122ca72b-872d-4ae8-85e4-7caea673ff31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407106028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2407106028
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2251852532
Short name T626
Test name
Test status
Simulation time 33832147 ps
CPU time 0.79 seconds
Started Aug 07 04:48:03 PM PDT 24
Finished Aug 07 04:48:04 PM PDT 24
Peak memory 197384 kb
Host smart-7505ee1d-903f-4b26-9839-1f15c239dc52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251852532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
251852532
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.249744388
Short name T630
Test name
Test status
Simulation time 50629078 ps
CPU time 1.71 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 195124 kb
Host smart-33e4a386-a324-4aa9-ac76-49bf4cdf6cee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249744388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.249744388
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3261825170
Short name T642
Test name
Test status
Simulation time 51603827 ps
CPU time 0.65 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 198248 kb
Host smart-b549cdc8-3f94-44b8-ba96-83cfca875ca4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261825170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
261825170
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.410096416
Short name T24
Test name
Test status
Simulation time 106676230 ps
CPU time 0.85 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 195124 kb
Host smart-031ec8d9-11f6-4406-8434-d77d840ed641
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410096416 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.410096416
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1803419372
Short name T708
Test name
Test status
Simulation time 40855710 ps
CPU time 0.63 seconds
Started Aug 07 04:48:09 PM PDT 24
Finished Aug 07 04:48:10 PM PDT 24
Peak memory 194980 kb
Host smart-b8942cc5-0ac8-4c83-a707-51299096ac11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803419372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1803419372
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3390021871
Short name T693
Test name
Test status
Simulation time 31335634 ps
CPU time 0.64 seconds
Started Aug 07 04:48:04 PM PDT 24
Finished Aug 07 04:48:05 PM PDT 24
Peak memory 194948 kb
Host smart-728689c9-ec0e-47a0-a4dd-4c6b77e1dde0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390021871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3390021871
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1549507475
Short name T714
Test name
Test status
Simulation time 83350657 ps
CPU time 0.69 seconds
Started Aug 07 04:48:23 PM PDT 24
Finished Aug 07 04:48:24 PM PDT 24
Peak memory 195008 kb
Host smart-63c49d46-d61c-4e9a-aa8d-6169991e3e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549507475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.1549507475
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3647149747
Short name T654
Test name
Test status
Simulation time 758053779 ps
CPU time 2.17 seconds
Started Aug 07 04:48:04 PM PDT 24
Finished Aug 07 04:48:06 PM PDT 24
Peak memory 196276 kb
Host smart-f51183e3-b94f-4694-9bd0-cd9231e2c0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647149747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3647149747
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2879975815
Short name T71
Test name
Test status
Simulation time 492206180 ps
CPU time 1.63 seconds
Started Aug 07 04:48:29 PM PDT 24
Finished Aug 07 04:48:30 PM PDT 24
Peak memory 200564 kb
Host smart-63c60123-c727-411c-bbcb-97d3a7d5e543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879975815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.2879975815
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.906198014
Short name T618
Test name
Test status
Simulation time 21639893 ps
CPU time 0.61 seconds
Started Aug 07 04:48:38 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 194940 kb
Host smart-7cc27223-28b2-4e5d-8edc-ef44b1ccbc86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906198014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.906198014
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1898316981
Short name T66
Test name
Test status
Simulation time 52539774 ps
CPU time 0.58 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 194940 kb
Host smart-bb2c0b30-d3d9-4757-bf59-6c7eb299de00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898316981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.1898316981
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2158896620
Short name T692
Test name
Test status
Simulation time 17568594 ps
CPU time 0.64 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 194932 kb
Host smart-4b508893-d31a-4d9f-9729-ada047ee3974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158896620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2158896620
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.249473607
Short name T620
Test name
Test status
Simulation time 22739811 ps
CPU time 0.65 seconds
Started Aug 07 04:48:29 PM PDT 24
Finished Aug 07 04:48:30 PM PDT 24
Peak memory 194940 kb
Host smart-4c7213e5-3bfe-47f5-9eaf-fed05606f3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249473607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.249473607
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.506911094
Short name T645
Test name
Test status
Simulation time 116950815 ps
CPU time 0.61 seconds
Started Aug 07 04:48:35 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 194936 kb
Host smart-9fc271d7-18eb-42d7-b877-4c77026017c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506911094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.506911094
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.533850422
Short name T700
Test name
Test status
Simulation time 26858545 ps
CPU time 0.64 seconds
Started Aug 07 04:48:38 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 195036 kb
Host smart-78bd7e38-e035-4090-a950-ad8a51fe0e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533850422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.533850422
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.2773729194
Short name T155
Test name
Test status
Simulation time 22488416 ps
CPU time 0.59 seconds
Started Aug 07 04:48:26 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 194916 kb
Host smart-956d070f-6f38-4389-8631-a2a7e053610d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773729194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.2773729194
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3420205717
Short name T725
Test name
Test status
Simulation time 54043883 ps
CPU time 0.62 seconds
Started Aug 07 04:48:34 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 194952 kb
Host smart-87d963e7-285f-4d7a-872b-dcb3e7ef288b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420205717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3420205717
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2384869182
Short name T661
Test name
Test status
Simulation time 19618117 ps
CPU time 0.61 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:45 PM PDT 24
Peak memory 195032 kb
Host smart-d6ecd549-890e-484c-bdd5-545a53ed8eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384869182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2384869182
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.4252608389
Short name T701
Test name
Test status
Simulation time 26482631 ps
CPU time 0.59 seconds
Started Aug 07 04:48:54 PM PDT 24
Finished Aug 07 04:48:55 PM PDT 24
Peak memory 194940 kb
Host smart-3aca008d-0b7b-4ca6-8ea4-a1bfec422a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252608389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.4252608389
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.4055042282
Short name T637
Test name
Test status
Simulation time 42872911 ps
CPU time 1.02 seconds
Started Aug 07 04:48:08 PM PDT 24
Finished Aug 07 04:48:09 PM PDT 24
Peak memory 198404 kb
Host smart-a5a34229-ff70-485c-8607-0011f07dd14e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055042282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.4
055042282
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4004015404
Short name T704
Test name
Test status
Simulation time 542489525 ps
CPU time 2.88 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 200264 kb
Host smart-5ed3663b-5592-4ab0-bd66-3c88f409394a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004015404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.4
004015404
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.337540243
Short name T685
Test name
Test status
Simulation time 64161820 ps
CPU time 0.69 seconds
Started Aug 07 04:48:27 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 197720 kb
Host smart-938c72a7-f71a-4905-92c5-9227ef79abd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337540243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.337540243
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1812191934
Short name T109
Test name
Test status
Simulation time 19253362 ps
CPU time 0.7 seconds
Started Aug 07 04:48:24 PM PDT 24
Finished Aug 07 04:48:25 PM PDT 24
Peak memory 197164 kb
Host smart-6d4a61bc-284b-450b-8e41-7768052f1bd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812191934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1812191934
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3809646952
Short name T619
Test name
Test status
Simulation time 38970818 ps
CPU time 0.66 seconds
Started Aug 07 04:48:10 PM PDT 24
Finished Aug 07 04:48:11 PM PDT 24
Peak memory 194960 kb
Host smart-b1858b10-dbfa-4c3b-8932-778af306d9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809646952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3809646952
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1678245067
Short name T117
Test name
Test status
Simulation time 27805765 ps
CPU time 0.85 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 197244 kb
Host smart-fa0af1f4-7f3c-43c1-92c1-c4d26abf05ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678245067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.1678245067
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.108083597
Short name T635
Test name
Test status
Simulation time 111839243 ps
CPU time 0.96 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 195256 kb
Host smart-6aea7b3d-2197-490d-807b-fa72b7d4d711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108083597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.108083597
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.215789367
Short name T674
Test name
Test status
Simulation time 25089279 ps
CPU time 0.58 seconds
Started Aug 07 04:48:50 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 194944 kb
Host smart-0c3a4008-bf80-4e88-8275-6321b9dbc2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215789367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.215789367
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3548446793
Short name T690
Test name
Test status
Simulation time 54215760 ps
CPU time 0.59 seconds
Started Aug 07 04:48:37 PM PDT 24
Finished Aug 07 04:48:38 PM PDT 24
Peak memory 195032 kb
Host smart-766115cd-3ce3-404d-95d7-0f0e4adb42c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548446793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3548446793
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1923943385
Short name T632
Test name
Test status
Simulation time 17707623 ps
CPU time 0.62 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 194940 kb
Host smart-bcf04086-e708-4435-a6a6-521cf4c865ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923943385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1923943385
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.136488428
Short name T696
Test name
Test status
Simulation time 20547282 ps
CPU time 0.61 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:37 PM PDT 24
Peak memory 195036 kb
Host smart-ca4b41da-cea6-4e6e-8707-1df7917edeaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136488428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.136488428
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1905096871
Short name T662
Test name
Test status
Simulation time 50919314 ps
CPU time 0.61 seconds
Started Aug 07 04:48:51 PM PDT 24
Finished Aug 07 04:48:52 PM PDT 24
Peak memory 194948 kb
Host smart-a1ea7d0b-3556-4120-9a7a-6cff0d8a3c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905096871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1905096871
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3217792277
Short name T629
Test name
Test status
Simulation time 20425155 ps
CPU time 0.63 seconds
Started Aug 07 04:48:49 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 195004 kb
Host smart-772eda9d-bc6a-4622-b6ab-0815433197d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217792277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3217792277
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.88718173
Short name T663
Test name
Test status
Simulation time 63152782 ps
CPU time 0.61 seconds
Started Aug 07 04:48:44 PM PDT 24
Finished Aug 07 04:48:45 PM PDT 24
Peak memory 194952 kb
Host smart-67c82d61-b0f0-46f6-b735-6e87b777d710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88718173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.88718173
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.921211502
Short name T622
Test name
Test status
Simulation time 45696046 ps
CPU time 0.61 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:47 PM PDT 24
Peak memory 194944 kb
Host smart-af119caa-5d27-4ff7-aa60-6c71141e7d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921211502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.921211502
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2460307601
Short name T703
Test name
Test status
Simulation time 19948269 ps
CPU time 0.62 seconds
Started Aug 07 04:48:38 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 195032 kb
Host smart-bdd98271-bc1a-4171-b7f7-35ec70b67e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460307601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2460307601
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3474232508
Short name T111
Test name
Test status
Simulation time 22713462 ps
CPU time 0.81 seconds
Started Aug 07 04:48:10 PM PDT 24
Finished Aug 07 04:48:11 PM PDT 24
Peak memory 194976 kb
Host smart-8244aeb1-6846-4da0-b8aa-78ee814aa993
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474232508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3
474232508
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.792363321
Short name T634
Test name
Test status
Simulation time 45792044 ps
CPU time 1.79 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 198920 kb
Host smart-50a65372-daf7-443c-a54b-d07a51974eb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792363321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.792363321
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1136761705
Short name T106
Test name
Test status
Simulation time 30159199 ps
CPU time 0.65 seconds
Started Aug 07 04:48:25 PM PDT 24
Finished Aug 07 04:48:26 PM PDT 24
Peak memory 197464 kb
Host smart-eed2772a-7e50-49a2-94eb-e9dcbdf35be4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136761705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
136761705
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2241684661
Short name T638
Test name
Test status
Simulation time 41696296 ps
CPU time 0.79 seconds
Started Aug 07 04:48:11 PM PDT 24
Finished Aug 07 04:48:12 PM PDT 24
Peak memory 200452 kb
Host smart-8826cb72-84bb-4e1f-93eb-61f9a509206f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241684661 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2241684661
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.968314731
Short name T659
Test name
Test status
Simulation time 43516839 ps
CPU time 0.7 seconds
Started Aug 07 04:48:10 PM PDT 24
Finished Aug 07 04:48:11 PM PDT 24
Peak memory 197216 kb
Host smart-ea68d16c-ec98-4c77-b959-97f7688e19f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968314731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.968314731
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3502670645
Short name T644
Test name
Test status
Simulation time 29315080 ps
CPU time 0.62 seconds
Started Aug 07 04:48:18 PM PDT 24
Finished Aug 07 04:48:19 PM PDT 24
Peak memory 194940 kb
Host smart-444bd0dc-7751-41ba-9d45-2240b9b346b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502670645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3502670645
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3763534338
Short name T121
Test name
Test status
Simulation time 61133653 ps
CPU time 0.8 seconds
Started Aug 07 04:48:27 PM PDT 24
Finished Aug 07 04:48:28 PM PDT 24
Peak memory 198404 kb
Host smart-2104c8aa-33db-4023-9b76-4a53ff7f1b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763534338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3763534338
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3299467762
Short name T639
Test name
Test status
Simulation time 56783454 ps
CPU time 1.3 seconds
Started Aug 07 04:48:38 PM PDT 24
Finished Aug 07 04:48:40 PM PDT 24
Peak memory 195520 kb
Host smart-46229279-a354-4065-a9d9-03599db22e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299467762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3299467762
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.351917609
Short name T633
Test name
Test status
Simulation time 451528586 ps
CPU time 1.57 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 195268 kb
Host smart-a019938c-3dbf-4e51-a91a-ff0bf9a8b1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351917609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
351917609
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.417766634
Short name T684
Test name
Test status
Simulation time 36531572 ps
CPU time 0.6 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:41 PM PDT 24
Peak memory 194936 kb
Host smart-6e5c4651-355e-4c6f-b133-fa8b3851c3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417766634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.417766634
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.4167880627
Short name T624
Test name
Test status
Simulation time 45539335 ps
CPU time 0.61 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 194940 kb
Host smart-4e28ba57-c551-42e6-ab1d-da76c843183b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167880627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.4167880627
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.339429082
Short name T666
Test name
Test status
Simulation time 18612995 ps
CPU time 0.61 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:41 PM PDT 24
Peak memory 195036 kb
Host smart-1b709062-9b25-4455-a4bd-fe6b32bf96dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339429082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.339429082
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3775905581
Short name T672
Test name
Test status
Simulation time 19676075 ps
CPU time 0.63 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:43 PM PDT 24
Peak memory 194960 kb
Host smart-136d79e9-ed68-4ffd-b854-6d7021c3d0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775905581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.3775905581
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1335525684
Short name T719
Test name
Test status
Simulation time 18973985 ps
CPU time 0.69 seconds
Started Aug 07 04:48:41 PM PDT 24
Finished Aug 07 04:48:42 PM PDT 24
Peak memory 195036 kb
Host smart-8ec9fa34-8bb2-413d-bdab-4e4bbaad451b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335525684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1335525684
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.357390790
Short name T728
Test name
Test status
Simulation time 42822019 ps
CPU time 0.58 seconds
Started Aug 07 04:48:47 PM PDT 24
Finished Aug 07 04:48:48 PM PDT 24
Peak memory 194944 kb
Host smart-13b5b7ba-06bb-4d31-b199-82f3a3bd1e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357390790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.357390790
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.90104911
Short name T636
Test name
Test status
Simulation time 48684433 ps
CPU time 0.63 seconds
Started Aug 07 04:48:40 PM PDT 24
Finished Aug 07 04:48:41 PM PDT 24
Peak memory 194960 kb
Host smart-b159fcb4-273f-4a8f-8856-9a3871d4432d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90104911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.90104911
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.875157465
Short name T65
Test name
Test status
Simulation time 169833362 ps
CPU time 0.66 seconds
Started Aug 07 04:49:49 PM PDT 24
Finished Aug 07 04:49:50 PM PDT 24
Peak memory 194108 kb
Host smart-2d4fa3d1-d1cd-41ae-910e-fe6cf1b43bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875157465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.875157465
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1682208645
Short name T691
Test name
Test status
Simulation time 39088505 ps
CPU time 0.6 seconds
Started Aug 07 04:48:38 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 195036 kb
Host smart-fa2e6977-4b1e-477b-adb6-b7923ac96a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682208645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1682208645
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2164637138
Short name T677
Test name
Test status
Simulation time 18788750 ps
CPU time 0.69 seconds
Started Aug 07 04:48:47 PM PDT 24
Finished Aug 07 04:48:48 PM PDT 24
Peak memory 195044 kb
Host smart-7478e433-5cfa-471c-bf77-1442a88fa149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164637138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2164637138
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2312229127
Short name T671
Test name
Test status
Simulation time 36747771 ps
CPU time 0.75 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:37 PM PDT 24
Peak memory 195148 kb
Host smart-e9f49f54-f186-44b3-9125-0e7bb958bbb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312229127 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.2312229127
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1410372248
Short name T105
Test name
Test status
Simulation time 24693808 ps
CPU time 0.68 seconds
Started Aug 07 04:48:33 PM PDT 24
Finished Aug 07 04:48:33 PM PDT 24
Peak memory 197340 kb
Host smart-fbdf7728-ef4c-41d9-8a18-18d4e8e9964c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410372248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1410372248
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3840218548
Short name T159
Test name
Test status
Simulation time 35101007 ps
CPU time 0.62 seconds
Started Aug 07 04:48:12 PM PDT 24
Finished Aug 07 04:48:12 PM PDT 24
Peak memory 194956 kb
Host smart-748a1234-df2c-49c8-8c29-b52f172e04c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840218548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3840218548
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.855102672
Short name T655
Test name
Test status
Simulation time 118597384 ps
CPU time 0.99 seconds
Started Aug 07 04:48:30 PM PDT 24
Finished Aug 07 04:48:31 PM PDT 24
Peak memory 195080 kb
Host smart-2a0f070e-ee6d-44ec-8d69-2a4b930b8932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855102672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sam
e_csr_outstanding.855102672
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2736340364
Short name T640
Test name
Test status
Simulation time 52426848 ps
CPU time 2.41 seconds
Started Aug 07 04:48:18 PM PDT 24
Finished Aug 07 04:48:20 PM PDT 24
Peak memory 196480 kb
Host smart-f8af36c2-f87c-4062-a775-25d65ddef72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736340364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2736340364
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2357942912
Short name T69
Test name
Test status
Simulation time 549750186 ps
CPU time 1.07 seconds
Started Aug 07 04:48:22 PM PDT 24
Finished Aug 07 04:48:23 PM PDT 24
Peak memory 200348 kb
Host smart-18832d9a-2608-46cf-b2d6-045c5dea9ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357942912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2357942912
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2391088447
Short name T132
Test name
Test status
Simulation time 38319713 ps
CPU time 0.79 seconds
Started Aug 07 04:48:26 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 195456 kb
Host smart-f0cd159d-6456-40c8-b14a-b1b8c41d9be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391088447 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2391088447
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.752211526
Short name T129
Test name
Test status
Simulation time 21372759 ps
CPU time 0.64 seconds
Started Aug 07 04:48:14 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 197184 kb
Host smart-85c5a66a-9604-4aba-84b1-484cc176fc8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752211526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.752211526
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2011756225
Short name T660
Test name
Test status
Simulation time 18178760 ps
CPU time 0.62 seconds
Started Aug 07 04:48:31 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 194968 kb
Host smart-cb60cafd-a763-42a2-9617-beaf836c11f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011756225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2011756225
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2634802217
Short name T118
Test name
Test status
Simulation time 122849812 ps
CPU time 0.87 seconds
Started Aug 07 04:48:16 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 198580 kb
Host smart-2d824ac4-16a7-4530-b83f-e4ccee60ee1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634802217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2634802217
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.22225033
Short name T678
Test name
Test status
Simulation time 212647641 ps
CPU time 1.55 seconds
Started Aug 07 04:48:32 PM PDT 24
Finished Aug 07 04:48:34 PM PDT 24
Peak memory 196276 kb
Host smart-fe29c551-4329-485a-8927-fcb1338c8f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22225033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.22225033
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3671699042
Short name T72
Test name
Test status
Simulation time 242688920 ps
CPU time 1.07 seconds
Started Aug 07 04:48:26 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 200360 kb
Host smart-319645a9-e1a1-409b-ae07-d3de63d8d81b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671699042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3671699042
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2144323785
Short name T709
Test name
Test status
Simulation time 100579336 ps
CPU time 1.25 seconds
Started Aug 07 04:48:16 PM PDT 24
Finished Aug 07 04:48:18 PM PDT 24
Peak memory 200636 kb
Host smart-01bf77f1-a3bd-4f4a-89af-53f1062563e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144323785 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2144323785
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.4077448436
Short name T103
Test name
Test status
Simulation time 33294745 ps
CPU time 0.7 seconds
Started Aug 07 04:48:16 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 197160 kb
Host smart-30ac66c5-27d8-4044-ae12-c9b6558e209f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077448436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.4077448436
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1505538402
Short name T717
Test name
Test status
Simulation time 38308363 ps
CPU time 0.61 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:13 PM PDT 24
Peak memory 194936 kb
Host smart-22165905-b17e-4a9d-90ae-5710a3b0a74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505538402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1505538402
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.319516992
Short name T668
Test name
Test status
Simulation time 156406745 ps
CPU time 0.84 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 195144 kb
Host smart-a905abe6-78f8-4a88-bf54-d61e63cc590b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319516992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.319516992
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2604349155
Short name T70
Test name
Test status
Simulation time 422611211 ps
CPU time 2.21 seconds
Started Aug 07 04:48:12 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 196452 kb
Host smart-460e4aac-cddd-4ed2-8de6-c770211b9e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604349155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2604349155
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2247615235
Short name T646
Test name
Test status
Simulation time 413553060 ps
CPU time 0.85 seconds
Started Aug 07 04:48:17 PM PDT 24
Finished Aug 07 04:48:18 PM PDT 24
Peak memory 200476 kb
Host smart-eb23e4bc-0302-4caa-89e8-af0f7073582d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247615235 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2247615235
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2595975364
Short name T628
Test name
Test status
Simulation time 19063852 ps
CPU time 0.65 seconds
Started Aug 07 04:48:25 PM PDT 24
Finished Aug 07 04:48:25 PM PDT 24
Peak memory 197468 kb
Host smart-15dc8c5b-4ead-4fcf-9688-2a1bb0ca3633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595975364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2595975364
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1108519028
Short name T689
Test name
Test status
Simulation time 24000358 ps
CPU time 0.61 seconds
Started Aug 07 04:48:24 PM PDT 24
Finished Aug 07 04:48:25 PM PDT 24
Peak memory 195052 kb
Host smart-4d24ccf0-5793-4668-9c56-c2d53326f7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108519028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1108519028
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.773127378
Short name T122
Test name
Test status
Simulation time 28429605 ps
CPU time 0.75 seconds
Started Aug 07 04:48:15 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 198360 kb
Host smart-f450dd94-e51d-40b3-a604-2257c277a30a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773127378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.773127378
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1818049495
Short name T55
Test name
Test status
Simulation time 1193197990 ps
CPU time 1.53 seconds
Started Aug 07 04:48:12 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 195276 kb
Host smart-89825848-c884-48b0-a094-7b812947bd88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818049495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.1818049495
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2121095459
Short name T716
Test name
Test status
Simulation time 125386075 ps
CPU time 1.17 seconds
Started Aug 07 04:48:24 PM PDT 24
Finished Aug 07 04:48:25 PM PDT 24
Peak memory 196208 kb
Host smart-659cfc5a-4d1e-4384-bc3e-5569ff4554af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121095459 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2121095459
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1192463921
Short name T108
Test name
Test status
Simulation time 19743836 ps
CPU time 0.66 seconds
Started Aug 07 04:48:16 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 197192 kb
Host smart-db0afcf5-e6f9-4254-880c-8c8a389f0e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192463921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1192463921
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.234549497
Short name T679
Test name
Test status
Simulation time 27044099 ps
CPU time 0.65 seconds
Started Aug 07 04:48:26 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 195008 kb
Host smart-6c0f360e-e3da-4a76-900a-135317793a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234549497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.234549497
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3466292938
Short name T643
Test name
Test status
Simulation time 28358216 ps
CPU time 0.87 seconds
Started Aug 07 04:48:13 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 195048 kb
Host smart-082b1525-be58-4c50-894e-22f847772f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466292938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.3466292938
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3968899029
Short name T62
Test name
Test status
Simulation time 129241640 ps
CPU time 1.4 seconds
Started Aug 07 04:48:36 PM PDT 24
Finished Aug 07 04:48:38 PM PDT 24
Peak memory 196320 kb
Host smart-50c7d61e-9e8b-4c9e-906f-f9ea444919bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968899029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3968899029
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.25176134
Short name T682
Test name
Test status
Simulation time 204500957 ps
CPU time 1.65 seconds
Started Aug 07 04:48:17 PM PDT 24
Finished Aug 07 04:48:19 PM PDT 24
Peak memory 195296 kb
Host smart-06137a3c-9e80-405b-820b-bb33fc4b3bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.25176134
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.2371329444
Short name T506
Test name
Test status
Simulation time 49438777 ps
CPU time 0.92 seconds
Started Aug 07 04:52:27 PM PDT 24
Finished Aug 07 04:52:28 PM PDT 24
Peak memory 200168 kb
Host smart-d61aab05-6dcd-4d2c-a427-12b2c67ebe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371329444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2371329444
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.997436175
Short name T410
Test name
Test status
Simulation time 45948837 ps
CPU time 0.77 seconds
Started Aug 07 04:52:45 PM PDT 24
Finished Aug 07 04:52:46 PM PDT 24
Peak memory 198412 kb
Host smart-e4bfea63-fe10-4d0a-a9a5-2cf72875c3e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997436175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.997436175
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1573208824
Short name T293
Test name
Test status
Simulation time 32491931 ps
CPU time 0.6 seconds
Started Aug 07 04:52:58 PM PDT 24
Finished Aug 07 04:52:59 PM PDT 24
Peak memory 197180 kb
Host smart-12c4a429-5e62-44e5-9a6b-5a8ebe87b97c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573208824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1573208824
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.29122696
Short name T433
Test name
Test status
Simulation time 1678602152 ps
CPU time 0.92 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 197892 kb
Host smart-073b93a9-ba0b-400f-a184-f89ad47b4d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29122696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.29122696
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.23104674
Short name T481
Test name
Test status
Simulation time 67200240 ps
CPU time 0.63 seconds
Started Aug 07 04:52:39 PM PDT 24
Finished Aug 07 04:52:40 PM PDT 24
Peak memory 197940 kb
Host smart-75a848ad-a792-49f7-9af3-81a7952cada0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23104674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.23104674
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3818994356
Short name T595
Test name
Test status
Simulation time 49032643 ps
CPU time 0.64 seconds
Started Aug 07 04:52:55 PM PDT 24
Finished Aug 07 04:52:56 PM PDT 24
Peak memory 197972 kb
Host smart-850b6021-12e2-4ada-a7e0-f09789b9a91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818994356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3818994356
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.959237619
Short name T39
Test name
Test status
Simulation time 77649414 ps
CPU time 0.72 seconds
Started Aug 07 04:52:37 PM PDT 24
Finished Aug 07 04:52:38 PM PDT 24
Peak memory 199096 kb
Host smart-67825c29-94b9-4d87-97f3-612d9e5fac8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959237619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.959237619
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.10314918
Short name T362
Test name
Test status
Simulation time 100855578 ps
CPU time 1.11 seconds
Started Aug 07 04:52:25 PM PDT 24
Finished Aug 07 04:52:26 PM PDT 24
Peak memory 209352 kb
Host smart-15174384-eb2d-480c-b705-1446bdcd2226
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.10314918
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1146496593
Short name T20
Test name
Test status
Simulation time 339559086 ps
CPU time 1.54 seconds
Started Aug 07 04:52:58 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 216756 kb
Host smart-88d7f279-b3a2-476c-9758-da4facb2212e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146496593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1146496593
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3562309825
Short name T60
Test name
Test status
Simulation time 64791656 ps
CPU time 0.95 seconds
Started Aug 07 04:52:36 PM PDT 24
Finished Aug 07 04:52:38 PM PDT 24
Peak memory 199096 kb
Host smart-6295c542-feda-4e2f-b58e-b530de0c5d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562309825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3562309825
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2325682010
Short name T318
Test name
Test status
Simulation time 43944966 ps
CPU time 0.66 seconds
Started Aug 07 04:52:43 PM PDT 24
Finished Aug 07 04:52:43 PM PDT 24
Peak memory 198748 kb
Host smart-2683462a-2ddb-421d-8ba3-bcedd15d16c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325682010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2325682010
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.376509062
Short name T407
Test name
Test status
Simulation time 56156908 ps
CPU time 0.81 seconds
Started Aug 07 04:52:59 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 198456 kb
Host smart-73ae524e-e940-4e54-9ec0-358a9bba53df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376509062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disab
le_rom_integrity_check.376509062
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.906475951
Short name T306
Test name
Test status
Simulation time 28985969 ps
CPU time 0.64 seconds
Started Aug 07 04:52:40 PM PDT 24
Finished Aug 07 04:52:41 PM PDT 24
Peak memory 197264 kb
Host smart-75ed5735-2717-499c-97fb-3979d7ce0ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906475951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.906475951
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.527943320
Short name T416
Test name
Test status
Simulation time 167520470 ps
CPU time 0.96 seconds
Started Aug 07 04:52:58 PM PDT 24
Finished Aug 07 04:52:59 PM PDT 24
Peak memory 198244 kb
Host smart-dd483574-0ef6-4461-a798-f5ea03bb0cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527943320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.527943320
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.835129416
Short name T331
Test name
Test status
Simulation time 40399959 ps
CPU time 0.65 seconds
Started Aug 07 04:52:43 PM PDT 24
Finished Aug 07 04:52:44 PM PDT 24
Peak memory 198020 kb
Host smart-3efafa32-2b5f-4a9c-adf3-f713f4e44a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835129416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.835129416
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1859346821
Short name T614
Test name
Test status
Simulation time 113188772 ps
CPU time 0.67 seconds
Started Aug 07 04:52:39 PM PDT 24
Finished Aug 07 04:52:40 PM PDT 24
Peak memory 197956 kb
Host smart-0e358e2d-09ca-40da-b7d7-77adb19bd869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859346821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1859346821
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3700609081
Short name T442
Test name
Test status
Simulation time 53796085 ps
CPU time 0.69 seconds
Started Aug 07 04:52:56 PM PDT 24
Finished Aug 07 04:52:57 PM PDT 24
Peak memory 201308 kb
Host smart-1c224f3f-bb1a-434d-9636-e4af386e922c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700609081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3700609081
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1877104967
Short name T91
Test name
Test status
Simulation time 83393985 ps
CPU time 0.74 seconds
Started Aug 07 04:52:34 PM PDT 24
Finished Aug 07 04:52:34 PM PDT 24
Peak memory 199076 kb
Host smart-30982e1f-c9f6-48c6-8fdc-58e98a6c517b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877104967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1877104967
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2117908341
Short name T366
Test name
Test status
Simulation time 115539417 ps
CPU time 1.05 seconds
Started Aug 07 04:52:44 PM PDT 24
Finished Aug 07 04:52:45 PM PDT 24
Peak memory 209396 kb
Host smart-1eac1fef-4625-4aac-92f8-18d34274ee5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117908341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2117908341
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.4055957222
Short name T382
Test name
Test status
Simulation time 53875812 ps
CPU time 0.77 seconds
Started Aug 07 04:52:32 PM PDT 24
Finished Aug 07 04:52:33 PM PDT 24
Peak memory 198184 kb
Host smart-6dd2732f-2257-44a9-888c-6b2d83e894d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055957222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4055957222
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1848329519
Short name T550
Test name
Test status
Simulation time 45884591 ps
CPU time 0.69 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 199156 kb
Host smart-bb1eabfe-cb70-4366-b582-570edd0cb0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848329519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1848329519
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2294003093
Short name T12
Test name
Test status
Simulation time 48675159 ps
CPU time 0.59 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 197964 kb
Host smart-50235315-7dce-4d9f-89a5-0acd8aa6a21e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294003093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2294003093
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.1736094306
Short name T94
Test name
Test status
Simulation time 246610304 ps
CPU time 0.93 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 198012 kb
Host smart-00c8c506-3852-4fae-a1bb-d59b1f2685da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736094306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1736094306
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.1640250235
Short name T602
Test name
Test status
Simulation time 93477334 ps
CPU time 0.62 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 197992 kb
Host smart-ca583206-2e36-4639-9541-266451c24b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640250235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1640250235
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2540103767
Short name T580
Test name
Test status
Simulation time 48929370 ps
CPU time 0.62 seconds
Started Aug 07 04:53:11 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 198328 kb
Host smart-5bc1a02c-bf98-4371-a00b-ea921c4de8ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540103767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2540103767
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3861447155
Short name T194
Test name
Test status
Simulation time 43889546 ps
CPU time 0.7 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 201356 kb
Host smart-b97f82b3-240a-46db-be4b-b18145f6ddc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861447155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3861447155
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.772633738
Short name T413
Test name
Test status
Simulation time 75702768 ps
CPU time 0.72 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198316 kb
Host smart-789c4a1b-b351-432a-9158-f64688929f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772633738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.772633738
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.4038657109
Short name T447
Test name
Test status
Simulation time 151769581 ps
CPU time 0.82 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 209336 kb
Host smart-0f7f12b1-2f34-463c-ba1d-bce850bfd5bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038657109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.4038657109
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3076096797
Short name T76
Test name
Test status
Simulation time 52722325 ps
CPU time 0.83 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198032 kb
Host smart-4563a7d6-c8d9-4715-8807-cefeb8d81809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076096797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3076096797
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.3645137298
Short name T49
Test name
Test status
Simulation time 29455753 ps
CPU time 0.65 seconds
Started Aug 07 04:53:04 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 199236 kb
Host smart-2dead5b5-e4de-4b47-8c4b-65cffb37ce04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645137298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3645137298
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3421018637
Short name T568
Test name
Test status
Simulation time 63910754 ps
CPU time 0.71 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 198684 kb
Host smart-ae9b956d-ca90-4c07-b223-ca59b2a5062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421018637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3421018637
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.598153250
Short name T215
Test name
Test status
Simulation time 27291629 ps
CPU time 0.59 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 197912 kb
Host smart-361334e2-5d51-4044-a01d-a97d9e104186
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598153250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_
malfunc.598153250
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.110384025
Short name T297
Test name
Test status
Simulation time 637652189 ps
CPU time 0.95 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198328 kb
Host smart-f8ea19c7-1926-4339-9a78-85f4d9227a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110384025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.110384025
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2199765596
Short name T9
Test name
Test status
Simulation time 46181174 ps
CPU time 0.63 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 197976 kb
Host smart-635701b7-24fb-43cf-adda-7cdcb4d98146
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199765596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2199765596
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.2153827099
Short name T214
Test name
Test status
Simulation time 162445204 ps
CPU time 0.58 seconds
Started Aug 07 04:53:14 PM PDT 24
Finished Aug 07 04:53:15 PM PDT 24
Peak memory 198376 kb
Host smart-eb106385-4ec6-480e-9caa-2c8f32d3cee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153827099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2153827099
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.2584750669
Short name T504
Test name
Test status
Simulation time 57034661 ps
CPU time 0.68 seconds
Started Aug 07 04:53:10 PM PDT 24
Finished Aug 07 04:53:11 PM PDT 24
Peak memory 201268 kb
Host smart-f6d326fd-622c-4479-a0d1-991f4a837e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584750669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.2584750669
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2489394444
Short name T376
Test name
Test status
Simulation time 50701954 ps
CPU time 0.62 seconds
Started Aug 07 04:53:14 PM PDT 24
Finished Aug 07 04:53:15 PM PDT 24
Peak memory 198076 kb
Host smart-ebb42dd4-1094-4982-a489-0e505db87b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489394444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2489394444
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3395633423
Short name T271
Test name
Test status
Simulation time 127253015 ps
CPU time 0.86 seconds
Started Aug 07 04:53:21 PM PDT 24
Finished Aug 07 04:53:22 PM PDT 24
Peak memory 209380 kb
Host smart-83d1243f-eb36-4c2f-9c8a-df7b60b996ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395633423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3395633423
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2896284423
Short name T525
Test name
Test status
Simulation time 104093485 ps
CPU time 0.71 seconds
Started Aug 07 04:53:11 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 198176 kb
Host smart-07741492-8f34-481d-9eb0-a6df531fe72c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896284423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2896284423
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1103058183
Short name T344
Test name
Test status
Simulation time 37358759 ps
CPU time 0.63 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198380 kb
Host smart-cc367c6f-524d-4ce3-a31f-1c0e2ffde91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103058183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1103058183
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.2529599049
Short name T38
Test name
Test status
Simulation time 132612499 ps
CPU time 0.86 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 200012 kb
Host smart-f79bae2c-123f-4c2b-b6ba-5da6aadc9db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529599049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2529599049
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2301477523
Short name T28
Test name
Test status
Simulation time 61550602 ps
CPU time 0.84 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 199108 kb
Host smart-83558ade-9901-4b4a-8e15-24fcf49eb655
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301477523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2301477523
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3287363315
Short name T302
Test name
Test status
Simulation time 30094513 ps
CPU time 0.62 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 197912 kb
Host smart-5998a20d-ccd0-4dab-9fff-e6042eb126ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287363315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3287363315
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2402330311
Short name T317
Test name
Test status
Simulation time 159088118 ps
CPU time 1.01 seconds
Started Aug 07 04:53:03 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 197984 kb
Host smart-b08a36dc-7260-4eaf-b912-ec4847db8518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402330311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2402330311
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.2831565925
Short name T492
Test name
Test status
Simulation time 55977114 ps
CPU time 0.6 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198008 kb
Host smart-c9458b08-4bf3-4e43-80d8-3a2620dc492d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831565925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2831565925
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.476935914
Short name T343
Test name
Test status
Simulation time 33972020 ps
CPU time 0.6 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:15 PM PDT 24
Peak memory 198424 kb
Host smart-5c34e541-d2b8-4b17-910f-0c41ad8a468e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476935914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.476935914
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.460482238
Short name T167
Test name
Test status
Simulation time 42469230 ps
CPU time 0.71 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:09 PM PDT 24
Peak memory 201312 kb
Host smart-ff796b5e-fd43-447e-afc9-34faf35590ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460482238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invali
d.460482238
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.2939529929
Short name T42
Test name
Test status
Simulation time 41115610 ps
CPU time 0.76 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 198272 kb
Host smart-cb006f53-3f6d-450d-8500-d4d5bff09a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939529929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2939529929
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3024921341
Short name T541
Test name
Test status
Simulation time 108892486 ps
CPU time 0.97 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:19 PM PDT 24
Peak memory 209324 kb
Host smart-005a678d-4196-4b38-9e6b-69a7b0f33947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024921341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3024921341
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2307800684
Short name T253
Test name
Test status
Simulation time 49854266 ps
CPU time 0.77 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 197972 kb
Host smart-2a4387e4-b23f-413b-9441-fd49d1cce365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307800684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2307800684
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1558741890
Short name T490
Test name
Test status
Simulation time 28438519 ps
CPU time 0.71 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 199276 kb
Host smart-edc08e35-be9c-4bea-a77b-211728bca152
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558741890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1558741890
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1111490739
Short name T478
Test name
Test status
Simulation time 180295049 ps
CPU time 0.72 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198636 kb
Host smart-a0ddc465-29da-4f5b-9ffd-13302af709e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111490739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1111490739
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1681869227
Short name T154
Test name
Test status
Simulation time 64552687 ps
CPU time 0.68 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 199064 kb
Host smart-4969e46f-9ad8-4585-a60b-7047ce658b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681869227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1681869227
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.469278386
Short name T283
Test name
Test status
Simulation time 29772980 ps
CPU time 0.64 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:09 PM PDT 24
Peak memory 197328 kb
Host smart-b32b2117-a426-41e0-8ad8-5d72599c9864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469278386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.469278386
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.758332256
Short name T484
Test name
Test status
Simulation time 165474842 ps
CPU time 0.98 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:09 PM PDT 24
Peak memory 198024 kb
Host smart-8e7349ce-ffc1-4377-b8c2-8722bba13207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758332256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.758332256
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.387683487
Short name T454
Test name
Test status
Simulation time 49638885 ps
CPU time 0.67 seconds
Started Aug 07 04:53:36 PM PDT 24
Finished Aug 07 04:53:36 PM PDT 24
Peak memory 197900 kb
Host smart-25ff6314-dff3-4c39-9a46-b38ff4d9a8d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387683487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.387683487
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2676124618
Short name T202
Test name
Test status
Simulation time 93360198 ps
CPU time 0.6 seconds
Started Aug 07 04:53:11 PM PDT 24
Finished Aug 07 04:53:11 PM PDT 24
Peak memory 198112 kb
Host smart-e66d5891-5d19-406e-a882-9523ca8958e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676124618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2676124618
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2946191980
Short name T373
Test name
Test status
Simulation time 68473730 ps
CPU time 0.66 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198100 kb
Host smart-8f739e17-65df-49f5-bea5-f8d7ff21b0b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946191980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2946191980
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.3916067243
Short name T52
Test name
Test status
Simulation time 109566536 ps
CPU time 0.92 seconds
Started Aug 07 04:53:30 PM PDT 24
Finished Aug 07 04:53:31 PM PDT 24
Peak memory 209428 kb
Host smart-783530be-c3b6-4f7d-bbe7-7d7dba83b8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916067243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3916067243
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1727445602
Short name T453
Test name
Test status
Simulation time 72478120 ps
CPU time 0.72 seconds
Started Aug 07 04:53:39 PM PDT 24
Finished Aug 07 04:53:40 PM PDT 24
Peak memory 197996 kb
Host smart-fed04966-9376-4b53-ba3c-2493dc72be8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727445602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1727445602
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.4047956471
Short name T365
Test name
Test status
Simulation time 50996868 ps
CPU time 0.76 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 199016 kb
Host smart-abae2154-cdfe-43f4-99eb-74ad351d9230
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047956471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.4047956471
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2106437647
Short name T257
Test name
Test status
Simulation time 29559782 ps
CPU time 0.66 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 197944 kb
Host smart-01ea1ba5-a796-43b5-a4a0-4cb3095e1dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106437647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2106437647
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2176952857
Short name T577
Test name
Test status
Simulation time 1074567350 ps
CPU time 1.03 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 198348 kb
Host smart-4379f178-d2fb-432f-b346-07849c555e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176952857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2176952857
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2790850197
Short name T556
Test name
Test status
Simulation time 52403116 ps
CPU time 0.65 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 197328 kb
Host smart-17bdf685-5ac8-4174-963f-270447c3866a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790850197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2790850197
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.4283042900
Short name T235
Test name
Test status
Simulation time 88927011 ps
CPU time 0.63 seconds
Started Aug 07 04:53:20 PM PDT 24
Finished Aug 07 04:53:21 PM PDT 24
Peak memory 198012 kb
Host smart-921bec01-f0b8-4310-aca1-97116c7ddb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283042900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.4283042900
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.3317246671
Short name T198
Test name
Test status
Simulation time 209090378 ps
CPU time 0.66 seconds
Started Aug 07 04:53:33 PM PDT 24
Finished Aug 07 04:53:34 PM PDT 24
Peak memory 201324 kb
Host smart-9cd19f6a-ff83-444c-b5fc-c386cad779f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317246671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.3317246671
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3284717702
Short name T89
Test name
Test status
Simulation time 57189124 ps
CPU time 0.73 seconds
Started Aug 07 04:53:40 PM PDT 24
Finished Aug 07 04:53:41 PM PDT 24
Peak memory 198968 kb
Host smart-f3a3c053-311b-4e36-8f43-e36c54d7d38b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284717702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3284717702
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2038924985
Short name T612
Test name
Test status
Simulation time 102187311 ps
CPU time 1.03 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:10 PM PDT 24
Peak memory 209408 kb
Host smart-d3a93e72-db4e-4825-a190-b1192793b759
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038924985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2038924985
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2927286206
Short name T329
Test name
Test status
Simulation time 99745611 ps
CPU time 0.76 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 199148 kb
Host smart-374c4f83-2cdb-4faa-81b8-05ff576f3447
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927286206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2927286206
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1194901697
Short name T469
Test name
Test status
Simulation time 38020871 ps
CPU time 0.64 seconds
Started Aug 07 04:53:19 PM PDT 24
Finished Aug 07 04:53:20 PM PDT 24
Peak memory 198472 kb
Host smart-b1f65dab-ad2e-421a-9108-85ff10e21cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194901697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1194901697
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.4229006515
Short name T523
Test name
Test status
Simulation time 134465672 ps
CPU time 0.85 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 200096 kb
Host smart-781a7ba5-a580-4ec3-9731-c06fbee0fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229006515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.4229006515
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.4213630727
Short name T424
Test name
Test status
Simulation time 52012221 ps
CPU time 0.7 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 198176 kb
Host smart-5a3ade5d-94d0-4bf2-bb32-54b10f141eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213630727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.4213630727
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.4250884040
Short name T554
Test name
Test status
Simulation time 37829751 ps
CPU time 0.56 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 198048 kb
Host smart-0a7d60a9-9ec8-4781-a1ee-74e9141565a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250884040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.4250884040
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.277963749
Short name T423
Test name
Test status
Simulation time 637089766 ps
CPU time 1.01 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 198320 kb
Host smart-8ebbdb1b-7439-4027-9ccf-1827dd9a3535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277963749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.277963749
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2367869252
Short name T606
Test name
Test status
Simulation time 54588133 ps
CPU time 0.67 seconds
Started Aug 07 04:53:40 PM PDT 24
Finished Aug 07 04:53:41 PM PDT 24
Peak memory 197984 kb
Host smart-1ba7be45-4690-483a-add5-1a1afb83f140
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367869252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2367869252
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.4032684148
Short name T276
Test name
Test status
Simulation time 41098666 ps
CPU time 0.65 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 197328 kb
Host smart-bb50baff-6b21-4129-ba14-b10dc6c07a64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032684148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.4032684148
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3461532476
Short name T515
Test name
Test status
Simulation time 139854219 ps
CPU time 0.71 seconds
Started Aug 07 04:53:14 PM PDT 24
Finished Aug 07 04:53:15 PM PDT 24
Peak memory 199016 kb
Host smart-7473971a-805b-4368-83eb-0e6d60884800
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461532476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3461532476
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2586910447
Short name T90
Test name
Test status
Simulation time 65981224 ps
CPU time 0.78 seconds
Started Aug 07 04:53:37 PM PDT 24
Finished Aug 07 04:53:38 PM PDT 24
Peak memory 199124 kb
Host smart-530c5388-ea4d-4d27-a2a6-3584a39a4ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586910447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2586910447
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1554115206
Short name T340
Test name
Test status
Simulation time 38445766 ps
CPU time 0.65 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:48 PM PDT 24
Peak memory 199284 kb
Host smart-5ac9749f-32b8-460f-a518-639eb2fe67a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554115206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1554115206
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1273545915
Short name T98
Test name
Test status
Simulation time 66917089 ps
CPU time 0.88 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 199444 kb
Host smart-4b6dcc10-ff7c-4d24-8855-4eef8145209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273545915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1273545915
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.177261574
Short name T367
Test name
Test status
Simulation time 65046947 ps
CPU time 0.81 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 198440 kb
Host smart-6f3baebd-8c84-4340-a960-920e3a89e049
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177261574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.177261574
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.388536405
Short name T11
Test name
Test status
Simulation time 28533625 ps
CPU time 0.63 seconds
Started Aug 07 04:53:25 PM PDT 24
Finished Aug 07 04:53:26 PM PDT 24
Peak memory 197924 kb
Host smart-892e6bb3-045d-44e5-b8ec-1a40b0ef39c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388536405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.388536405
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.1561589121
Short name T251
Test name
Test status
Simulation time 49377090 ps
CPU time 0.58 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198144 kb
Host smart-cb1df9b6-e97c-4208-9111-bf1a33157658
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561589121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1561589121
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.1164986501
Short name T472
Test name
Test status
Simulation time 31821432 ps
CPU time 0.62 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:19 PM PDT 24
Peak memory 198324 kb
Host smart-46ab2041-d099-4f16-a68e-42edc55b36c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164986501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.1164986501
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.4036287063
Short name T542
Test name
Test status
Simulation time 40653569 ps
CPU time 0.71 seconds
Started Aug 07 04:53:29 PM PDT 24
Finished Aug 07 04:53:29 PM PDT 24
Peak memory 201196 kb
Host smart-f196e9b8-81aa-4444-aba3-1fffc4d8f77c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036287063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.4036287063
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2826370295
Short name T536
Test name
Test status
Simulation time 282324108 ps
CPU time 0.75 seconds
Started Aug 07 04:53:30 PM PDT 24
Finished Aug 07 04:53:31 PM PDT 24
Peak memory 199072 kb
Host smart-e55d9abc-6100-4e3d-b94e-03ed54986637
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826370295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2826370295
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.202315009
Short name T46
Test name
Test status
Simulation time 167376734 ps
CPU time 0.77 seconds
Started Aug 07 04:53:35 PM PDT 24
Finished Aug 07 04:53:36 PM PDT 24
Peak memory 209360 kb
Host smart-17e12e04-6ed6-41ce-a44b-47242ce55805
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202315009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.202315009
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1020043364
Short name T398
Test name
Test status
Simulation time 108085754 ps
CPU time 0.73 seconds
Started Aug 07 04:53:31 PM PDT 24
Finished Aug 07 04:53:32 PM PDT 24
Peak memory 198232 kb
Host smart-cbca0fb3-232a-45f6-9b58-cebb1d413a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020043364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1020043364
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3040912738
Short name T545
Test name
Test status
Simulation time 63404802 ps
CPU time 0.64 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 198440 kb
Host smart-84f4123b-f2d3-4863-8e87-ee18acb4aa80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040912738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3040912738
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1916350871
Short name T517
Test name
Test status
Simulation time 47020026 ps
CPU time 0.62 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198440 kb
Host smart-0962668c-6cce-421c-a448-739b7f50ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916350871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1916350871
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.482147121
Short name T266
Test name
Test status
Simulation time 72688694 ps
CPU time 0.67 seconds
Started Aug 07 04:53:39 PM PDT 24
Finished Aug 07 04:53:40 PM PDT 24
Peak memory 197928 kb
Host smart-2f630ade-3296-493e-b463-7434306a91cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482147121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disa
ble_rom_integrity_check.482147121
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3210694710
Short name T473
Test name
Test status
Simulation time 63680746 ps
CPU time 0.62 seconds
Started Aug 07 04:53:45 PM PDT 24
Finished Aug 07 04:53:45 PM PDT 24
Peak memory 197964 kb
Host smart-2843d202-6b46-43a2-8779-64be36c7f8be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210694710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3210694710
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.168811612
Short name T273
Test name
Test status
Simulation time 167725616 ps
CPU time 0.98 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 198012 kb
Host smart-56d67030-f0f6-4121-a5be-cc7c2f00dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168811612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.168811612
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.4062902927
Short name T603
Test name
Test status
Simulation time 50276690 ps
CPU time 0.62 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198012 kb
Host smart-7cb859a9-0d55-4a3a-a452-a7de66422839
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062902927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.4062902927
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2714133052
Short name T305
Test name
Test status
Simulation time 41815693 ps
CPU time 0.61 seconds
Started Aug 07 04:53:50 PM PDT 24
Finished Aug 07 04:53:51 PM PDT 24
Peak memory 197984 kb
Host smart-39ca43a0-b3b2-4659-a806-a1292ea5ea2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714133052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2714133052
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3605361013
Short name T458
Test name
Test status
Simulation time 78087397 ps
CPU time 0.67 seconds
Started Aug 07 04:53:41 PM PDT 24
Finished Aug 07 04:53:42 PM PDT 24
Peak memory 201372 kb
Host smart-3ebef6c6-d80a-48ca-9214-729ad7ae2b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605361013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3605361013
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2494832297
Short name T615
Test name
Test status
Simulation time 63430613 ps
CPU time 0.66 seconds
Started Aug 07 04:53:11 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 199092 kb
Host smart-046edd7f-f09d-468e-8c70-b33f275396a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494832297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2494832297
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.3380185869
Short name T497
Test name
Test status
Simulation time 118590226 ps
CPU time 0.85 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 209496 kb
Host smart-f8082257-27fe-4417-b337-c7f8457a9c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380185869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3380185869
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1623123670
Short name T391
Test name
Test status
Simulation time 57461195 ps
CPU time 0.73 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198108 kb
Host smart-a2c8717b-bdef-42fc-94c9-1ac0e2baf331
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623123670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1623123670
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2723166606
Short name T312
Test name
Test status
Simulation time 30615684 ps
CPU time 0.69 seconds
Started Aug 07 04:53:37 PM PDT 24
Finished Aug 07 04:53:38 PM PDT 24
Peak memory 198364 kb
Host smart-75afc663-ee31-4fbc-982c-3daf9581eda2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723166606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2723166606
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1142972548
Short name T99
Test name
Test status
Simulation time 47747169 ps
CPU time 0.63 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:19 PM PDT 24
Peak memory 198440 kb
Host smart-5274c962-f7ed-4a83-a973-03769b074cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142972548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1142972548
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1814571864
Short name T43
Test name
Test status
Simulation time 51550487 ps
CPU time 0.81 seconds
Started Aug 07 04:53:38 PM PDT 24
Finished Aug 07 04:53:39 PM PDT 24
Peak memory 199132 kb
Host smart-8f12ab45-e97f-41a8-b43b-6e69e0e1b6b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814571864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1814571864
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3238920644
Short name T578
Test name
Test status
Simulation time 28937303 ps
CPU time 0.63 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:10 PM PDT 24
Peak memory 197968 kb
Host smart-076eec98-2e17-45da-b282-5f18161279bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238920644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.3238920644
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2677699797
Short name T508
Test name
Test status
Simulation time 195489677 ps
CPU time 0.94 seconds
Started Aug 07 04:53:34 PM PDT 24
Finished Aug 07 04:53:35 PM PDT 24
Peak memory 198300 kb
Host smart-b5f3082b-8378-46b6-ace1-47e7e8a191e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677699797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2677699797
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.4133931569
Short name T270
Test name
Test status
Simulation time 102570548 ps
CPU time 0.62 seconds
Started Aug 07 04:53:46 PM PDT 24
Finished Aug 07 04:53:47 PM PDT 24
Peak memory 198300 kb
Host smart-a2cbf5d0-96e1-473c-9721-700167206590
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133931569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.4133931569
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1359090467
Short name T209
Test name
Test status
Simulation time 54370118 ps
CPU time 0.59 seconds
Started Aug 07 04:53:14 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 198312 kb
Host smart-de7ed350-f0ab-4d42-9eca-5755f6b37cca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359090467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1359090467
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.324566099
Short name T175
Test name
Test status
Simulation time 38635566 ps
CPU time 0.7 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 201460 kb
Host smart-cbde1b0b-c258-4cfa-9476-058d69aff635
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324566099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.324566099
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.2601031700
Short name T459
Test name
Test status
Simulation time 130318525 ps
CPU time 0.75 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 199008 kb
Host smart-c13b4dc2-8ecb-4289-9ab9-611a0eab8a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601031700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2601031700
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1292969892
Short name T392
Test name
Test status
Simulation time 186053300 ps
CPU time 0.81 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 209428 kb
Host smart-7477d592-4de2-4a18-9f57-51aa889eaa36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292969892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1292969892
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2311613648
Short name T245
Test name
Test status
Simulation time 51582718 ps
CPU time 0.86 seconds
Started Aug 07 04:53:19 PM PDT 24
Finished Aug 07 04:53:20 PM PDT 24
Peak memory 199132 kb
Host smart-812edda2-e371-4923-8edc-6ce990df00fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311613648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2311613648
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2098830764
Short name T601
Test name
Test status
Simulation time 53336919 ps
CPU time 0.61 seconds
Started Aug 07 04:53:32 PM PDT 24
Finished Aug 07 04:53:33 PM PDT 24
Peak memory 198308 kb
Host smart-c61fbd54-e526-455f-8d4c-a3bf68f4b61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098830764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2098830764
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.387330464
Short name T86
Test name
Test status
Simulation time 135081266 ps
CPU time 0.85 seconds
Started Aug 07 04:53:38 PM PDT 24
Finished Aug 07 04:53:39 PM PDT 24
Peak memory 200008 kb
Host smart-18e60c1b-3c11-4103-ad27-253ff80aede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387330464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.387330464
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2439655491
Short name T240
Test name
Test status
Simulation time 74121656 ps
CPU time 0.65 seconds
Started Aug 07 04:53:36 PM PDT 24
Finished Aug 07 04:53:37 PM PDT 24
Peak memory 198324 kb
Host smart-872e8640-4ce7-46a1-990c-ceb437f5a738
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439655491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2439655491
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1149897546
Short name T286
Test name
Test status
Simulation time 31614085 ps
CPU time 0.59 seconds
Started Aug 07 04:53:25 PM PDT 24
Finished Aug 07 04:53:26 PM PDT 24
Peak memory 197456 kb
Host smart-8acd42bf-aa6f-4932-862a-c9d2055bc595
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149897546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1149897546
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.3066484360
Short name T213
Test name
Test status
Simulation time 164221149 ps
CPU time 0.93 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 198012 kb
Host smart-42ff16a0-7b4e-49c6-8960-78c6fd8847fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066484360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3066484360
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.4100263780
Short name T464
Test name
Test status
Simulation time 32357274 ps
CPU time 0.68 seconds
Started Aug 07 04:53:39 PM PDT 24
Finished Aug 07 04:53:40 PM PDT 24
Peak memory 197920 kb
Host smart-5911724d-acdb-4944-96ee-2b1bf59691e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100263780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.4100263780
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.3864514308
Short name T399
Test name
Test status
Simulation time 66348358 ps
CPU time 0.6 seconds
Started Aug 07 04:53:38 PM PDT 24
Finished Aug 07 04:53:39 PM PDT 24
Peak memory 198004 kb
Host smart-b05b0b8b-b0f2-4bfa-874d-37771b919949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864514308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.3864514308
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.3940131460
Short name T387
Test name
Test status
Simulation time 101185968 ps
CPU time 0.71 seconds
Started Aug 07 04:53:25 PM PDT 24
Finished Aug 07 04:53:26 PM PDT 24
Peak memory 198276 kb
Host smart-f2be335c-5aaa-4aee-aeb9-63fdab8bb37a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940131460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3940131460
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.2612590203
Short name T546
Test name
Test status
Simulation time 149456205 ps
CPU time 0.86 seconds
Started Aug 07 04:53:30 PM PDT 24
Finished Aug 07 04:53:31 PM PDT 24
Peak memory 209388 kb
Host smart-66dcfd5b-5f57-4ff5-926d-934755ecb870
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612590203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2612590203
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2052285557
Short name T511
Test name
Test status
Simulation time 93074012 ps
CPU time 0.69 seconds
Started Aug 07 04:53:31 PM PDT 24
Finished Aug 07 04:53:32 PM PDT 24
Peak memory 197968 kb
Host smart-15557e2d-c0d8-4745-bc3a-367f02ae9606
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052285557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2052285557
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3730329309
Short name T422
Test name
Test status
Simulation time 52455552 ps
CPU time 0.62 seconds
Started Aug 07 04:53:37 PM PDT 24
Finished Aug 07 04:53:38 PM PDT 24
Peak memory 199316 kb
Host smart-811cda2a-f342-4d4b-b991-6f543f8330d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730329309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3730329309
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2953437611
Short name T92
Test name
Test status
Simulation time 18845682 ps
CPU time 0.7 seconds
Started Aug 07 04:52:59 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 199056 kb
Host smart-c48fd048-acc3-4df4-b358-42a3091df322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953437611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2953437611
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2487930071
Short name T572
Test name
Test status
Simulation time 67987606 ps
CPU time 0.67 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 199044 kb
Host smart-ddda86a4-b6fe-4989-8346-d77634cf59bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487930071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2487930071
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1043298070
Short name T267
Test name
Test status
Simulation time 40694104 ps
CPU time 0.62 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 197216 kb
Host smart-4317d95d-d22e-4dc8-a4c4-436b7ed061fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043298070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1043298070
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3836492046
Short name T535
Test name
Test status
Simulation time 638098787 ps
CPU time 1 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:55 PM PDT 24
Peak memory 198328 kb
Host smart-2311143d-bdc3-483e-adb7-661229287299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836492046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3836492046
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1621985718
Short name T268
Test name
Test status
Simulation time 54943612 ps
CPU time 0.62 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:55 PM PDT 24
Peak memory 198000 kb
Host smart-ea0cf3ac-91c3-4f02-b4db-ab6a7d1ba23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621985718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1621985718
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1761473833
Short name T210
Test name
Test status
Simulation time 29570685 ps
CPU time 0.63 seconds
Started Aug 07 04:52:50 PM PDT 24
Finished Aug 07 04:52:50 PM PDT 24
Peak memory 198348 kb
Host smart-6e59fe4b-0264-4560-84ab-54bb4c9df6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761473833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1761473833
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1951262184
Short name T435
Test name
Test status
Simulation time 57319539 ps
CPU time 0.69 seconds
Started Aug 07 04:52:57 PM PDT 24
Finished Aug 07 04:52:58 PM PDT 24
Peak memory 198136 kb
Host smart-caed831b-a594-4f73-9c61-cab5a0ae633c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951262184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1951262184
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1812077645
Short name T403
Test name
Test status
Simulation time 145791997 ps
CPU time 0.8 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:55 PM PDT 24
Peak memory 209396 kb
Host smart-90068485-4bcb-41cc-a3c7-1b42df23b0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812077645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1812077645
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1258907887
Short name T31
Test name
Test status
Simulation time 566882120 ps
CPU time 1.16 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 217400 kb
Host smart-4ea01ec7-e930-4b1a-9aa2-b92d23c4046f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258907887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1258907887
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2006665000
Short name T457
Test name
Test status
Simulation time 73274170 ps
CPU time 0.93 seconds
Started Aug 07 04:52:40 PM PDT 24
Finished Aug 07 04:52:41 PM PDT 24
Peak memory 199556 kb
Host smart-ecfae35a-687f-41a6-9060-f06ecae84250
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006665000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2006665000
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.280188167
Short name T611
Test name
Test status
Simulation time 29513385 ps
CPU time 0.71 seconds
Started Aug 07 04:52:53 PM PDT 24
Finished Aug 07 04:52:54 PM PDT 24
Peak memory 199280 kb
Host smart-cb6a7a02-8277-492b-ad99-7728e71a779c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280188167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.280188167
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.3791193749
Short name T512
Test name
Test status
Simulation time 52883298 ps
CPU time 1 seconds
Started Aug 07 04:52:43 PM PDT 24
Finished Aug 07 04:52:44 PM PDT 24
Peak memory 200544 kb
Host smart-f35603b4-bc67-414b-9437-1ef7e80a2959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791193749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3791193749
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2992756830
Short name T84
Test name
Test status
Simulation time 31722208 ps
CPU time 1.07 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 200948 kb
Host smart-d5753b07-5bf2-4387-ac6e-9bd31295e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992756830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2992756830
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1467467965
Short name T355
Test name
Test status
Simulation time 62413260 ps
CPU time 0.73 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 198484 kb
Host smart-84d9b280-c2af-4ba7-b60a-a9546d0aaa4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467467965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1467467965
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2499370562
Short name T207
Test name
Test status
Simulation time 39491155 ps
CPU time 0.63 seconds
Started Aug 07 04:53:33 PM PDT 24
Finished Aug 07 04:53:33 PM PDT 24
Peak memory 198020 kb
Host smart-1e2a197e-2041-457a-9a98-29d89c8af2f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499370562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2499370562
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.891708067
Short name T599
Test name
Test status
Simulation time 304452498 ps
CPU time 0.95 seconds
Started Aug 07 04:53:43 PM PDT 24
Finished Aug 07 04:53:44 PM PDT 24
Peak memory 198016 kb
Host smart-8ebf4423-b244-4ebe-b6fd-b6b4122a2cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891708067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.891708067
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1481551990
Short name T414
Test name
Test status
Simulation time 44504482 ps
CPU time 0.62 seconds
Started Aug 07 04:53:23 PM PDT 24
Finished Aug 07 04:53:24 PM PDT 24
Peak memory 197324 kb
Host smart-e0422e82-466f-45c9-bc18-c195597ab076
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481551990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1481551990
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.330387261
Short name T539
Test name
Test status
Simulation time 57232742 ps
CPU time 0.6 seconds
Started Aug 07 04:53:45 PM PDT 24
Finished Aug 07 04:53:46 PM PDT 24
Peak memory 198120 kb
Host smart-180c686d-6d73-4e0c-b28b-8d593670df40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330387261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.330387261
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.4288482738
Short name T346
Test name
Test status
Simulation time 45213128 ps
CPU time 0.68 seconds
Started Aug 07 04:53:27 PM PDT 24
Finished Aug 07 04:53:28 PM PDT 24
Peak memory 201256 kb
Host smart-933896df-2566-47fb-9d65-7d336b6a2822
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288482738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.4288482738
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1620830646
Short name T279
Test name
Test status
Simulation time 61020923 ps
CPU time 0.64 seconds
Started Aug 07 04:53:18 PM PDT 24
Finished Aug 07 04:53:19 PM PDT 24
Peak memory 199072 kb
Host smart-872800c4-3069-4858-9b05-51272321db66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620830646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1620830646
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1764120062
Short name T370
Test name
Test status
Simulation time 113515976 ps
CPU time 0.89 seconds
Started Aug 07 04:53:44 PM PDT 24
Finished Aug 07 04:53:45 PM PDT 24
Peak memory 209440 kb
Host smart-3072d9cf-989d-4da2-b2b2-272937dd95bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764120062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1764120062
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3662661313
Short name T597
Test name
Test status
Simulation time 50097378 ps
CPU time 0.89 seconds
Started Aug 07 04:53:21 PM PDT 24
Finished Aug 07 04:53:22 PM PDT 24
Peak memory 199188 kb
Host smart-98973756-de36-47e1-b9d0-fa8cd9a416c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662661313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3662661313
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.375299408
Short name T385
Test name
Test status
Simulation time 36610305 ps
CPU time 0.69 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 199244 kb
Host smart-37a92bf0-c1cb-4351-bfe5-c4bd864e2657
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375299408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.375299408
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1812934904
Short name T405
Test name
Test status
Simulation time 214184172 ps
CPU time 0.82 seconds
Started Aug 07 04:53:44 PM PDT 24
Finished Aug 07 04:53:45 PM PDT 24
Peak memory 199932 kb
Host smart-606528b4-2acd-4321-afcc-47453169350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812934904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1812934904
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3369694923
Short name T161
Test name
Test status
Simulation time 59210679 ps
CPU time 0.68 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:18 PM PDT 24
Peak memory 199116 kb
Host smart-6c61a212-0d49-4d56-8355-887e9bec3eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369694923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3369694923
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.699197084
Short name T561
Test name
Test status
Simulation time 30455314 ps
CPU time 0.62 seconds
Started Aug 07 04:53:59 PM PDT 24
Finished Aug 07 04:54:00 PM PDT 24
Peak memory 197328 kb
Host smart-b1f7fb48-5e45-4e30-867e-723d879c1001
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699197084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.699197084
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1429193735
Short name T217
Test name
Test status
Simulation time 622933181 ps
CPU time 0.97 seconds
Started Aug 07 04:53:36 PM PDT 24
Finished Aug 07 04:53:37 PM PDT 24
Peak memory 198016 kb
Host smart-0d5950fd-159f-4d0b-9c48-982003cd3998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429193735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1429193735
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2080397104
Short name T562
Test name
Test status
Simulation time 101683063 ps
CPU time 0.63 seconds
Started Aug 07 04:53:34 PM PDT 24
Finished Aug 07 04:53:35 PM PDT 24
Peak memory 198024 kb
Host smart-f7d5c50b-5be2-48bb-965b-0cd7d60cf8be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080397104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2080397104
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1230733444
Short name T579
Test name
Test status
Simulation time 48943790 ps
CPU time 0.73 seconds
Started Aug 07 04:53:33 PM PDT 24
Finished Aug 07 04:53:34 PM PDT 24
Peak memory 198276 kb
Host smart-e4b07310-0814-40e9-b8bd-d6cb4de8c89e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230733444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1230733444
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1958155475
Short name T30
Test name
Test status
Simulation time 134935878 ps
CPU time 0.68 seconds
Started Aug 07 04:53:45 PM PDT 24
Finished Aug 07 04:53:46 PM PDT 24
Peak memory 201080 kb
Host smart-1117392e-2eb9-4b4a-859e-b7d4f7082947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958155475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1958155475
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2390451941
Short name T260
Test name
Test status
Simulation time 97812623 ps
CPU time 0.81 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 198296 kb
Host smart-89d24e3a-4e49-4ecf-b29f-9b19a29f3355
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390451941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2390451941
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1499356115
Short name T244
Test name
Test status
Simulation time 116288635 ps
CPU time 0.82 seconds
Started Aug 07 04:53:48 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 209380 kb
Host smart-6b653177-4c3b-4b0a-84c5-29788d305e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499356115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1499356115
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3370667510
Short name T549
Test name
Test status
Simulation time 126848997 ps
CPU time 0.76 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198012 kb
Host smart-68c137c5-fa2b-49c3-90f3-c4f7274ec4f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370667510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3370667510
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3220066516
Short name T379
Test name
Test status
Simulation time 39298341 ps
CPU time 0.63 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198432 kb
Host smart-e058e386-9cc3-43b4-8527-5ae0bff5b400
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220066516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3220066516
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.2379039989
Short name T101
Test name
Test status
Simulation time 24386378 ps
CPU time 0.7 seconds
Started Aug 07 04:53:27 PM PDT 24
Finished Aug 07 04:53:32 PM PDT 24
Peak memory 198652 kb
Host smart-beb47ee2-b51c-4f79-874e-f479c1fd6f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379039989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2379039989
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2182217782
Short name T356
Test name
Test status
Simulation time 56652823 ps
CPU time 0.79 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 199060 kb
Host smart-32ab4d73-69cb-4bd6-8589-4bc00f91ac96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182217782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2182217782
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3087371507
Short name T607
Test name
Test status
Simulation time 31470738 ps
CPU time 0.6 seconds
Started Aug 07 04:53:51 PM PDT 24
Finished Aug 07 04:53:51 PM PDT 24
Peak memory 197928 kb
Host smart-82eba08e-d3eb-4414-a345-04eb6064dd58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087371507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3087371507
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.4089695418
Short name T307
Test name
Test status
Simulation time 610762086 ps
CPU time 0.92 seconds
Started Aug 07 04:53:51 PM PDT 24
Finished Aug 07 04:53:52 PM PDT 24
Peak memory 198016 kb
Host smart-1d963aa4-a3ed-4002-978a-84542cbb767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089695418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.4089695418
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2274300396
Short name T502
Test name
Test status
Simulation time 64009151 ps
CPU time 0.65 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:52 PM PDT 24
Peak memory 197268 kb
Host smart-d23cf683-0567-44d9-979f-940d96d7546d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274300396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2274300396
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.4253377247
Short name T316
Test name
Test status
Simulation time 71885153 ps
CPU time 0.61 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 198032 kb
Host smart-5560283e-6cea-4fa2-824b-5158d5cb1dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253377247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.4253377247
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2572348407
Short name T40
Test name
Test status
Simulation time 114961386 ps
CPU time 0.69 seconds
Started Aug 07 04:53:34 PM PDT 24
Finished Aug 07 04:53:35 PM PDT 24
Peak memory 201352 kb
Host smart-cd08c643-1779-4508-bb4f-e34b76e68f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572348407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2572348407
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.577722125
Short name T220
Test name
Test status
Simulation time 78585703 ps
CPU time 0.75 seconds
Started Aug 07 04:53:53 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 199032 kb
Host smart-5b2f0ab8-8e62-4f29-8932-9da017c7e80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577722125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.577722125
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3507319750
Short name T320
Test name
Test status
Simulation time 109751235 ps
CPU time 1.13 seconds
Started Aug 07 04:53:39 PM PDT 24
Finished Aug 07 04:53:40 PM PDT 24
Peak memory 209388 kb
Host smart-fbb50732-912e-4f24-9878-97d60b1c70ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507319750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3507319750
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.749471304
Short name T434
Test name
Test status
Simulation time 56604730 ps
CPU time 0.77 seconds
Started Aug 07 04:53:41 PM PDT 24
Finished Aug 07 04:53:42 PM PDT 24
Peak memory 197968 kb
Host smart-78ddb4f2-9c0a-4edc-81b2-05d89b673260
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749471304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.749471304
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1720179993
Short name T610
Test name
Test status
Simulation time 70204453 ps
CPU time 0.62 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 198468 kb
Host smart-97195045-d20a-4583-8fc1-754f1e602527
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720179993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1720179993
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.861904107
Short name T592
Test name
Test status
Simulation time 48795854 ps
CPU time 0.72 seconds
Started Aug 07 04:53:45 PM PDT 24
Finished Aug 07 04:53:45 PM PDT 24
Peak memory 198824 kb
Host smart-0f890eb5-bb37-42d2-a3fb-ac8b001cc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861904107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.861904107
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3850566783
Short name T581
Test name
Test status
Simulation time 68022590 ps
CPU time 0.69 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 199056 kb
Host smart-9be786bb-11c0-49dc-9aba-b257721b1028
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850566783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3850566783
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2886451954
Short name T495
Test name
Test status
Simulation time 44680403 ps
CPU time 0.61 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 197300 kb
Host smart-845e4e84-11aa-4857-825d-f95f91fc5f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886451954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2886451954
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.771417158
Short name T10
Test name
Test status
Simulation time 3017363982 ps
CPU time 0.95 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 198060 kb
Host smart-4ae21765-9de7-4bef-87c0-286731b2241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771417158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.771417158
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1782807802
Short name T563
Test name
Test status
Simulation time 48108968 ps
CPU time 0.63 seconds
Started Aug 07 04:53:56 PM PDT 24
Finished Aug 07 04:53:57 PM PDT 24
Peak memory 198052 kb
Host smart-46c8a08b-d216-4fdd-b259-e63c44982115
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782807802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1782807802
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.2051602348
Short name T417
Test name
Test status
Simulation time 39250704 ps
CPU time 0.64 seconds
Started Aug 07 04:53:30 PM PDT 24
Finished Aug 07 04:53:31 PM PDT 24
Peak memory 197996 kb
Host smart-12ee1698-824e-4899-8f83-0ae9521f36da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051602348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2051602348
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2491896647
Short name T172
Test name
Test status
Simulation time 188346412 ps
CPU time 0.65 seconds
Started Aug 07 04:53:36 PM PDT 24
Finished Aug 07 04:53:37 PM PDT 24
Peak memory 201228 kb
Host smart-346364b0-6f14-4413-8f84-68a4464b2b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491896647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2491896647
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.895903613
Short name T421
Test name
Test status
Simulation time 84985691 ps
CPU time 0.69 seconds
Started Aug 07 04:53:53 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 198964 kb
Host smart-9c0bcc8a-79e0-4651-ab58-61a0528b6254
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895903613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.895903613
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.1420477907
Short name T499
Test name
Test status
Simulation time 109855469 ps
CPU time 0.97 seconds
Started Aug 07 04:53:43 PM PDT 24
Finished Aug 07 04:53:44 PM PDT 24
Peak memory 209268 kb
Host smart-924e4988-ff8a-4388-8c5e-6fe6f1a4c9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420477907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1420477907
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.692291105
Short name T496
Test name
Test status
Simulation time 60083867 ps
CPU time 0.84 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 197988 kb
Host smart-1ddc044f-2e65-4e21-b042-17ea5cf27f5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692291105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.692291105
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.2254726208
Short name T491
Test name
Test status
Simulation time 32222765 ps
CPU time 0.69 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 199348 kb
Host smart-f488036a-a236-4d43-917b-67cbd89c30a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254726208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2254726208
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.338046377
Short name T142
Test name
Test status
Simulation time 30508468 ps
CPU time 0.69 seconds
Started Aug 07 04:53:51 PM PDT 24
Finished Aug 07 04:53:52 PM PDT 24
Peak memory 198160 kb
Host smart-58c0e343-372c-48dd-b265-9835ad3baec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338046377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.338046377
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.4123347221
Short name T609
Test name
Test status
Simulation time 40448025 ps
CPU time 0.86 seconds
Started Aug 07 04:53:43 PM PDT 24
Finished Aug 07 04:53:44 PM PDT 24
Peak memory 200188 kb
Host smart-b5046916-35e2-4818-80b8-7e91d2d48ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123347221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.4123347221
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1476261536
Short name T401
Test name
Test status
Simulation time 77364431 ps
CPU time 0.66 seconds
Started Aug 07 04:54:12 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 198952 kb
Host smart-89be57a5-78d0-4f34-9e68-15f60c08b2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476261536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1476261536
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.885537542
Short name T538
Test name
Test status
Simulation time 29301375 ps
CPU time 0.64 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 197948 kb
Host smart-31e5741c-e55a-4020-a3c9-cca4f5280d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885537542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_
malfunc.885537542
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2265757713
Short name T93
Test name
Test status
Simulation time 313012686 ps
CPU time 0.97 seconds
Started Aug 07 04:53:53 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 198332 kb
Host smart-8a46d2d0-57cd-460a-ad93-bd8bfd9226e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265757713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2265757713
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.287317730
Short name T338
Test name
Test status
Simulation time 37613396 ps
CPU time 0.64 seconds
Started Aug 07 04:53:45 PM PDT 24
Finished Aug 07 04:53:46 PM PDT 24
Peak memory 197964 kb
Host smart-fd9a1a44-dffb-4848-8ec3-93b363548e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287317730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.287317730
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.237192799
Short name T494
Test name
Test status
Simulation time 46053136 ps
CPU time 0.68 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 198084 kb
Host smart-b684d8e6-1e70-42e5-8f98-2ba78d65295d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237192799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.237192799
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3118937230
Short name T594
Test name
Test status
Simulation time 104951456 ps
CPU time 0.69 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 201304 kb
Host smart-332f222b-b8b8-43cb-8609-5056ac20ec1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118937230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3118937230
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1818482405
Short name T258
Test name
Test status
Simulation time 188977012 ps
CPU time 0.66 seconds
Started Aug 07 04:53:40 PM PDT 24
Finished Aug 07 04:53:41 PM PDT 24
Peak memory 198256 kb
Host smart-fffaabe4-b71f-4bb8-be4c-b3da60278bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818482405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1818482405
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2669865295
Short name T396
Test name
Test status
Simulation time 106008754 ps
CPU time 1.02 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 209504 kb
Host smart-4250aaa6-ccb4-4541-86e2-2b4ab9c69b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669865295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2669865295
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2318388346
Short name T477
Test name
Test status
Simulation time 62816175 ps
CPU time 0.82 seconds
Started Aug 07 04:53:44 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 198140 kb
Host smart-afc3c66e-36bf-4f15-a54f-787a36831057
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318388346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2318388346
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.1763663257
Short name T465
Test name
Test status
Simulation time 34413889 ps
CPU time 0.64 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 199244 kb
Host smart-6d91c7e6-1599-4cb8-adc7-48d953b26425
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763663257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.1763663257
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1598718128
Short name T471
Test name
Test status
Simulation time 42261629 ps
CPU time 0.86 seconds
Started Aug 07 04:53:43 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 200120 kb
Host smart-a5d1fd19-8cf3-4dd9-b6d3-528903490e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598718128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1598718128
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3787772640
Short name T543
Test name
Test status
Simulation time 70264648 ps
CPU time 0.67 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 198444 kb
Host smart-23510200-d387-4952-b5a5-38259c38f3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787772640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3787772640
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.605622356
Short name T438
Test name
Test status
Simulation time 30581763 ps
CPU time 0.63 seconds
Started Aug 07 04:53:37 PM PDT 24
Finished Aug 07 04:53:37 PM PDT 24
Peak memory 197924 kb
Host smart-a4a17e6d-aee2-4e18-bf62-df3170eae1c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605622356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.605622356
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3802303649
Short name T374
Test name
Test status
Simulation time 157947831 ps
CPU time 1.03 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 197972 kb
Host smart-a4190a70-db57-40f5-977a-b0f7ea813914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802303649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3802303649
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.827192398
Short name T573
Test name
Test status
Simulation time 63950885 ps
CPU time 0.69 seconds
Started Aug 07 04:53:48 PM PDT 24
Finished Aug 07 04:53:48 PM PDT 24
Peak memory 197900 kb
Host smart-40e2e66d-27d3-4119-a6bb-c81ba8a6aa1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827192398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.827192398
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1557110502
Short name T205
Test name
Test status
Simulation time 44949053 ps
CPU time 0.61 seconds
Started Aug 07 04:53:50 PM PDT 24
Finished Aug 07 04:53:51 PM PDT 24
Peak memory 198084 kb
Host smart-e3262771-65ed-446d-b79c-2e9aa1fbaf03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557110502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1557110502
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.423868338
Short name T37
Test name
Test status
Simulation time 44071856 ps
CPU time 0.61 seconds
Started Aug 07 04:53:50 PM PDT 24
Finished Aug 07 04:53:51 PM PDT 24
Peak memory 198032 kb
Host smart-1a0f047c-3d35-4f48-9525-2df3165efaf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423868338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.423868338
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3837815977
Short name T598
Test name
Test status
Simulation time 152911908 ps
CPU time 0.81 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 209380 kb
Host smart-2f6d4118-6d05-4686-bc5f-a5e1abf2131d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837815977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3837815977
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2616460442
Short name T229
Test name
Test status
Simulation time 134317937 ps
CPU time 0.6 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:53 PM PDT 24
Peak memory 198408 kb
Host smart-e8963fba-8a6c-4364-b3c4-e673eb76e3c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616460442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2616460442
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.4015968878
Short name T537
Test name
Test status
Simulation time 33813762 ps
CPU time 0.66 seconds
Started Aug 07 04:53:53 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 199068 kb
Host smart-a6ffb847-4acd-4a0e-9270-de82d1f87218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015968878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.4015968878
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.4182849980
Short name T45
Test name
Test status
Simulation time 48541689 ps
CPU time 0.8 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 198564 kb
Host smart-457f43a9-8e55-4956-a8d3-7228e2c2b16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182849980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.4182849980
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3741021948
Short name T323
Test name
Test status
Simulation time 29268320 ps
CPU time 0.66 seconds
Started Aug 07 04:53:51 PM PDT 24
Finished Aug 07 04:53:52 PM PDT 24
Peak memory 197244 kb
Host smart-253cb0ef-bc4b-4a04-9c00-70abbf95158c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741021948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3741021948
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.383930773
Short name T429
Test name
Test status
Simulation time 297081417 ps
CPU time 0.99 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:53 PM PDT 24
Peak memory 198088 kb
Host smart-a0622485-f662-4be0-b42d-141c4535acee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383930773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.383930773
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.3707666913
Short name T351
Test name
Test status
Simulation time 33675568 ps
CPU time 0.6 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 197972 kb
Host smart-f2925e4f-cac2-4bc5-8ffa-5cc9cb69944f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707666913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3707666913
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.2751795434
Short name T468
Test name
Test status
Simulation time 49451025 ps
CPU time 0.6 seconds
Started Aug 07 04:53:47 PM PDT 24
Finished Aug 07 04:53:48 PM PDT 24
Peak memory 197968 kb
Host smart-f844bb75-05f4-4f60-9f68-d0bb9c540be4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751795434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2751795434
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2186230499
Short name T184
Test name
Test status
Simulation time 77585617 ps
CPU time 0.68 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 201268 kb
Host smart-f4e43543-8575-4662-a4e9-022f3314e3df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186230499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2186230499
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.1901013733
Short name T200
Test name
Test status
Simulation time 113106488 ps
CPU time 0.78 seconds
Started Aug 07 04:53:47 PM PDT 24
Finished Aug 07 04:53:48 PM PDT 24
Peak memory 198472 kb
Host smart-fa7bac54-99fb-4815-9ace-3b4c10fc246a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901013733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1901013733
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1998393375
Short name T576
Test name
Test status
Simulation time 145576386 ps
CPU time 0.82 seconds
Started Aug 07 04:53:58 PM PDT 24
Finished Aug 07 04:53:59 PM PDT 24
Peak memory 209340 kb
Host smart-a7a5feef-4fba-4cc2-a637-6e4da4c575d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998393375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1998393375
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3888069429
Short name T461
Test name
Test status
Simulation time 76838998 ps
CPU time 0.81 seconds
Started Aug 07 04:53:50 PM PDT 24
Finished Aug 07 04:53:51 PM PDT 24
Peak memory 198008 kb
Host smart-68b30c3f-df27-4db6-bc92-f5fa39b94321
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888069429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3888069429
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1900043707
Short name T375
Test name
Test status
Simulation time 58930004 ps
CPU time 0.61 seconds
Started Aug 07 04:53:48 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 198380 kb
Host smart-5bb6adf0-fe9a-4dc4-b19c-451f9146a107
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900043707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1900043707
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3665961510
Short name T585
Test name
Test status
Simulation time 181609495 ps
CPU time 0.76 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 199808 kb
Host smart-88728e2e-1c99-4b44-a5f5-89f3a2126da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665961510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3665961510
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1515944121
Short name T540
Test name
Test status
Simulation time 31443871 ps
CPU time 0.61 seconds
Started Aug 07 04:53:56 PM PDT 24
Finished Aug 07 04:53:57 PM PDT 24
Peak memory 197916 kb
Host smart-a90274b7-c9b1-4e8d-b245-5729580f611a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515944121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1515944121
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2044303951
Short name T225
Test name
Test status
Simulation time 679004188 ps
CPU time 0.98 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198408 kb
Host smart-ff01b3f6-39cb-4a71-a241-5803736e21ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044303951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2044303951
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3644603
Short name T27
Test name
Test status
Simulation time 37673363 ps
CPU time 0.62 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 197964 kb
Host smart-2f3164d9-1b6e-47c6-aec3-269d36dd4d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3644603
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2280428164
Short name T354
Test name
Test status
Simulation time 53145041 ps
CPU time 0.61 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 197988 kb
Host smart-587ef979-a500-4b3c-8ef5-5c0b2ad04a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280428164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2280428164
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.146539424
Short name T197
Test name
Test status
Simulation time 75671723 ps
CPU time 0.66 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 201356 kb
Host smart-62b41347-aff8-4d69-9bf0-fffe685f63ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146539424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.146539424
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.63805550
Short name T33
Test name
Test status
Simulation time 109786173 ps
CPU time 0.72 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 198144 kb
Host smart-14b50183-143f-4c5e-b8f4-d6a6332c824e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63805550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.63805550
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3039570596
Short name T400
Test name
Test status
Simulation time 164338866 ps
CPU time 0.75 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 209492 kb
Host smart-2daebbde-8a49-4e5f-8db5-c0d5466bdd95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039570596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3039570596
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3210530446
Short name T406
Test name
Test status
Simulation time 86764856 ps
CPU time 0.74 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:52 PM PDT 24
Peak memory 199068 kb
Host smart-915b32e5-faae-420d-813e-ffb7ec317b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210530446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3210530446
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.202371798
Short name T226
Test name
Test status
Simulation time 153825304 ps
CPU time 0.6 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:17 PM PDT 24
Peak memory 198472 kb
Host smart-9441ad0f-8584-43bc-ad6e-7f948a94e401
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202371798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.202371798
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.186580490
Short name T425
Test name
Test status
Simulation time 45338794 ps
CPU time 0.67 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 199088 kb
Host smart-9a01a4ce-afbc-4bba-8dbf-e9e0c077ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186580490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.186580490
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3009985716
Short name T138
Test name
Test status
Simulation time 54760566 ps
CPU time 0.84 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 199052 kb
Host smart-08dab9e2-e39c-4854-93fe-c2659b5c1ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009985716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3009985716
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1498307003
Short name T281
Test name
Test status
Simulation time 28906018 ps
CPU time 0.68 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 197920 kb
Host smart-b721a1cf-e45d-466e-ac7c-b577fc615f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498307003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1498307003
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.4294744765
Short name T206
Test name
Test status
Simulation time 163721132 ps
CPU time 0.95 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 198408 kb
Host smart-3c326d83-9aaa-4539-9066-105bcd8d81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294744765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.4294744765
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.4154830932
Short name T252
Test name
Test status
Simulation time 65808118 ps
CPU time 0.68 seconds
Started Aug 07 04:53:59 PM PDT 24
Finished Aug 07 04:53:59 PM PDT 24
Peak memory 197908 kb
Host smart-4ed27c14-5494-4a1b-a192-1186454f42ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154830932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.4154830932
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.1922912872
Short name T482
Test name
Test status
Simulation time 54864371 ps
CPU time 0.63 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198316 kb
Host smart-caabd017-d982-4b40-a554-91650c6c1038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922912872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1922912872
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1107700288
Short name T192
Test name
Test status
Simulation time 69548013 ps
CPU time 0.65 seconds
Started Aug 07 04:53:52 PM PDT 24
Finished Aug 07 04:53:53 PM PDT 24
Peak memory 201228 kb
Host smart-a71fb355-03c9-40b0-8766-62f35c133564
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107700288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1107700288
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.4169279112
Short name T360
Test name
Test status
Simulation time 29957806 ps
CPU time 0.64 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 198220 kb
Host smart-fa75cd32-51bf-4498-b32a-eb50e7203fbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169279112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.4169279112
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1747712125
Short name T289
Test name
Test status
Simulation time 152193156 ps
CPU time 0.85 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 209432 kb
Host smart-d10366ae-9b15-4080-8a00-80d5f1252fd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747712125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1747712125
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4263675295
Short name T278
Test name
Test status
Simulation time 233116483 ps
CPU time 0.71 seconds
Started Aug 07 04:53:58 PM PDT 24
Finished Aug 07 04:53:59 PM PDT 24
Peak memory 198016 kb
Host smart-da831c6f-4cfa-45f4-8949-b92a7c2392ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263675295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4263675295
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.4167558358
Short name T324
Test name
Test status
Simulation time 54373759 ps
CPU time 0.64 seconds
Started Aug 07 04:53:42 PM PDT 24
Finished Aug 07 04:53:43 PM PDT 24
Peak memory 199276 kb
Host smart-1d02d48d-ae00-41b5-9d20-dc40129ba11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167558358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.4167558358
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.162284769
Short name T1
Test name
Test status
Simulation time 34540717 ps
CPU time 1.08 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:57 PM PDT 24
Peak memory 200836 kb
Host smart-bd058e37-bea6-4443-9ebe-5766ae92793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162284769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.162284769
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2709818842
Short name T304
Test name
Test status
Simulation time 88264581 ps
CPU time 0.67 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 198380 kb
Host smart-88ef979a-f64e-49ce-a3ee-3bbc7aac2ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709818842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2709818842
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2148429290
Short name T263
Test name
Test status
Simulation time 38717414 ps
CPU time 0.61 seconds
Started Aug 07 04:53:59 PM PDT 24
Finished Aug 07 04:54:00 PM PDT 24
Peak memory 197188 kb
Host smart-f96930d0-ec21-4f74-a81f-477cf8664faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148429290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2148429290
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.4025473360
Short name T466
Test name
Test status
Simulation time 786558162 ps
CPU time 0.97 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198048 kb
Host smart-7c26445a-63cf-41ae-adfb-51258cc771aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025473360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.4025473360
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2097854180
Short name T463
Test name
Test status
Simulation time 22578965 ps
CPU time 0.59 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 197972 kb
Host smart-a7ee0ff7-b938-47b9-9420-d490990ac1e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097854180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2097854180
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3969016795
Short name T480
Test name
Test status
Simulation time 68134867 ps
CPU time 0.85 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 199096 kb
Host smart-db03cc9d-a16c-432a-a1d7-5c0ea89c6886
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969016795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3969016795
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3393219197
Short name T566
Test name
Test status
Simulation time 168809262 ps
CPU time 0.78 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 209380 kb
Host smart-0a81c236-efbd-4417-9439-b4774d350bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393219197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3393219197
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2862959448
Short name T74
Test name
Test status
Simulation time 71754320 ps
CPU time 0.75 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 198164 kb
Host smart-afe784e7-e4de-47ce-89bf-6959a913bf44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862959448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2862959448
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.47872813
Short name T299
Test name
Test status
Simulation time 35975589 ps
CPU time 0.61 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 199268 kb
Host smart-5bd6179b-78a3-47ad-a377-d38cf454d097
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47872813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.47872813
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1859094651
Short name T100
Test name
Test status
Simulation time 37568202 ps
CPU time 0.83 seconds
Started Aug 07 04:52:55 PM PDT 24
Finished Aug 07 04:52:56 PM PDT 24
Peak memory 200044 kb
Host smart-4058bb76-2a7e-4a7d-87eb-c9df7b6acbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859094651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1859094651
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.4201850228
Short name T596
Test name
Test status
Simulation time 46246991 ps
CPU time 0.8 seconds
Started Aug 07 04:52:50 PM PDT 24
Finished Aug 07 04:52:51 PM PDT 24
Peak memory 199052 kb
Host smart-425db33c-923d-440b-a626-092a8e5d77e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201850228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.4201850228
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1053377023
Short name T295
Test name
Test status
Simulation time 29301192 ps
CPU time 0.64 seconds
Started Aug 07 04:52:52 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 197896 kb
Host smart-35f82345-68c9-49d0-8ae4-010269298026
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053377023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.1053377023
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2996094134
Short name T393
Test name
Test status
Simulation time 158896647 ps
CPU time 0.98 seconds
Started Aug 07 04:52:51 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 197996 kb
Host smart-0a9c0521-e5be-41a7-afca-8b34788003d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996094134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2996094134
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.3517103653
Short name T510
Test name
Test status
Simulation time 55607355 ps
CPU time 0.59 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:54 PM PDT 24
Peak memory 197928 kb
Host smart-f2106f9b-3cb9-4aac-919e-a67056acb723
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517103653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3517103653
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.358340455
Short name T265
Test name
Test status
Simulation time 38033136 ps
CPU time 0.7 seconds
Started Aug 07 04:52:52 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 197992 kb
Host smart-77962676-c020-492a-8f38-c594f570388c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358340455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.358340455
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.258711863
Short name T186
Test name
Test status
Simulation time 78506323 ps
CPU time 0.67 seconds
Started Aug 07 04:52:50 PM PDT 24
Finished Aug 07 04:52:51 PM PDT 24
Peak memory 201292 kb
Host smart-7c487cd6-2a59-4115-ab44-9f684cf92474
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258711863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid
.258711863
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.2792958988
Short name T431
Test name
Test status
Simulation time 119659499 ps
CPU time 0.7 seconds
Started Aug 07 04:52:40 PM PDT 24
Finished Aug 07 04:52:41 PM PDT 24
Peak memory 199092 kb
Host smart-6d05b0a4-6ef5-4b14-809f-8e12eb6bc305
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792958988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2792958988
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.713925711
Short name T420
Test name
Test status
Simulation time 113423713 ps
CPU time 1.01 seconds
Started Aug 07 04:52:59 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 209364 kb
Host smart-c5b895a8-138e-4075-9e73-99cb9f6fc58a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713925711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.713925711
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2176252869
Short name T32
Test name
Test status
Simulation time 354847435 ps
CPU time 1.48 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:03 PM PDT 24
Peak memory 216796 kb
Host smart-56e34000-c5c2-4365-a27c-3ed486e844dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176252869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2176252869
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.33455021
Short name T441
Test name
Test status
Simulation time 52420319 ps
CPU time 0.82 seconds
Started Aug 07 04:52:56 PM PDT 24
Finished Aug 07 04:52:57 PM PDT 24
Peak memory 199220 kb
Host smart-8aee6688-0f2f-4c73-9dc1-2863c3678d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33455021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mu
bi.33455021
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.448294801
Short name T82
Test name
Test status
Simulation time 33549113 ps
CPU time 0.69 seconds
Started Aug 07 04:52:43 PM PDT 24
Finished Aug 07 04:52:44 PM PDT 24
Peak memory 198396 kb
Host smart-e1092749-c1a7-4157-9832-4517b82d0fbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448294801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.448294801
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1871484967
Short name T185
Test name
Test status
Simulation time 50440016 ps
CPU time 0.98 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 200316 kb
Host smart-614b079f-a55e-425b-ab55-11ea370f6b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871484967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1871484967
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3656888535
Short name T135
Test name
Test status
Simulation time 30996136 ps
CPU time 0.6 seconds
Started Aug 07 04:54:00 PM PDT 24
Finished Aug 07 04:54:00 PM PDT 24
Peak memory 197272 kb
Host smart-8940ef6a-f9f8-42e3-98d4-447f5c8bf502
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656888535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3656888535
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.996662501
Short name T291
Test name
Test status
Simulation time 164324301 ps
CPU time 1.01 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198324 kb
Host smart-2d11bdcb-16ed-404a-a120-e7da46201d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996662501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.996662501
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2565188038
Short name T440
Test name
Test status
Simulation time 52252244 ps
CPU time 0.61 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 197984 kb
Host smart-4154928d-5369-42a2-8fed-4ab85742663a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565188038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2565188038
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2406411832
Short name T383
Test name
Test status
Simulation time 24369390 ps
CPU time 0.62 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198000 kb
Host smart-b57071a7-dec3-4c01-87a0-cfa2b3f16fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406411832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2406411832
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.536474135
Short name T177
Test name
Test status
Simulation time 81986339 ps
CPU time 0.67 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 201288 kb
Host smart-45f803fd-0850-4c6d-8567-c8cc8979b076
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536474135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali
d.536474135
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.145195480
Short name T34
Test name
Test status
Simulation time 37128262 ps
CPU time 0.71 seconds
Started Aug 07 04:53:57 PM PDT 24
Finished Aug 07 04:53:57 PM PDT 24
Peak memory 199064 kb
Host smart-00cd94d5-a5bf-4b0b-94f1-32e23802edb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145195480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.145195480
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3649749561
Short name T443
Test name
Test status
Simulation time 106651304 ps
CPU time 1.01 seconds
Started Aug 07 04:53:54 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 201176 kb
Host smart-7db172cc-93a3-439a-8169-92aa84c57b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649749561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3649749561
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.752427778
Short name T228
Test name
Test status
Simulation time 239687301 ps
CPU time 0.76 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 198916 kb
Host smart-dceb4d0b-c69c-4cf6-ab15-1930ba45d6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752427778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_
mubi.752427778
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3907690223
Short name T337
Test name
Test status
Simulation time 66005560 ps
CPU time 0.64 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 198388 kb
Host smart-a6ef5ac9-c96f-4169-b614-41b375ce333e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907690223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3907690223
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3821075175
Short name T505
Test name
Test status
Simulation time 27988179 ps
CPU time 0.87 seconds
Started Aug 07 04:53:57 PM PDT 24
Finished Aug 07 04:53:58 PM PDT 24
Peak memory 200684 kb
Host smart-d548422b-ce6e-44d6-9ddb-b7ac60441bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821075175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3821075175
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.334299767
Short name T36
Test name
Test status
Simulation time 68263402 ps
CPU time 0.75 seconds
Started Aug 07 04:53:49 PM PDT 24
Finished Aug 07 04:53:50 PM PDT 24
Peak memory 198520 kb
Host smart-0721cdda-f8d1-4d2c-9ed5-63983e2e7383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334299767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.334299767
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1332781451
Short name T237
Test name
Test status
Simulation time 29938373 ps
CPU time 0.63 seconds
Started Aug 07 04:53:57 PM PDT 24
Finished Aug 07 04:53:57 PM PDT 24
Peak memory 197852 kb
Host smart-a098a576-f809-4dab-9fe1-342a7edca73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332781451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1332781451
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1985794296
Short name T507
Test name
Test status
Simulation time 606845636 ps
CPU time 0.91 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 197540 kb
Host smart-b1bdee8f-5efb-4be1-9d5d-74628ba1b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985794296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1985794296
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3616866997
Short name T232
Test name
Test status
Simulation time 37217067 ps
CPU time 0.59 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 197980 kb
Host smart-10d1ac32-9d82-4acc-a649-15575de78201
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616866997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3616866997
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.2153017813
Short name T524
Test name
Test status
Simulation time 37383580 ps
CPU time 0.65 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:03 PM PDT 24
Peak memory 198040 kb
Host smart-e145677a-ca3d-4631-a255-1af5216a95a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153017813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2153017813
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2928876966
Short name T180
Test name
Test status
Simulation time 69777074 ps
CPU time 0.68 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 201308 kb
Host smart-bd5c5665-feb0-41c5-b177-d4029ad060ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928876966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2928876966
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.1820183800
Short name T520
Test name
Test status
Simulation time 40631726 ps
CPU time 0.75 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 199028 kb
Host smart-e6a9b5d1-64da-4538-85c9-f3368e8dec6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820183800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1820183800
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4224093163
Short name T534
Test name
Test status
Simulation time 106674998 ps
CPU time 1.11 seconds
Started Aug 07 04:54:00 PM PDT 24
Finished Aug 07 04:54:01 PM PDT 24
Peak memory 209344 kb
Host smart-f92e344c-7546-450d-9e9d-5ed8448acaa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224093163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4224093163
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3534407716
Short name T332
Test name
Test status
Simulation time 137260290 ps
CPU time 0.69 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 198012 kb
Host smart-bd639508-30cb-4f48-a601-ae97f88729f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534407716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3534407716
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.533789193
Short name T81
Test name
Test status
Simulation time 31906427 ps
CPU time 0.66 seconds
Started Aug 07 04:54:02 PM PDT 24
Finished Aug 07 04:54:03 PM PDT 24
Peak memory 199376 kb
Host smart-598fce4e-c59b-4af3-81a5-08802da10893
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533789193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.533789193
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2033528728
Short name T124
Test name
Test status
Simulation time 25736987 ps
CPU time 0.88 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 200272 kb
Host smart-84ec51ab-64c0-421f-a652-db054667a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033528728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2033528728
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2776246256
Short name T371
Test name
Test status
Simulation time 75746885 ps
CPU time 0.72 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 198500 kb
Host smart-d30b8524-f53d-48a4-9ce9-e157bc0b8cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776246256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.2776246256
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2886006522
Short name T519
Test name
Test status
Simulation time 30416125 ps
CPU time 0.6 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 197944 kb
Host smart-446d68cc-6179-4e05-aa4d-66e3fa0538c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886006522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2886006522
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.854832186
Short name T328
Test name
Test status
Simulation time 1081641743 ps
CPU time 0.94 seconds
Started Aug 07 04:53:59 PM PDT 24
Finished Aug 07 04:54:00 PM PDT 24
Peak memory 198072 kb
Host smart-b730fac9-eadf-4476-b634-9c1997496238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854832186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.854832186
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.406656975
Short name T247
Test name
Test status
Simulation time 38658308 ps
CPU time 0.65 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198056 kb
Host smart-16df3a3a-e1f1-491a-8765-359466f44187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406656975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.406656975
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2070932201
Short name T372
Test name
Test status
Simulation time 47372970 ps
CPU time 0.64 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198292 kb
Host smart-d0cae3a9-6cd5-46df-9fe0-9cc7854ceb46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070932201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2070932201
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1478983243
Short name T288
Test name
Test status
Simulation time 65255246 ps
CPU time 0.66 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:05 PM PDT 24
Peak memory 198248 kb
Host smart-1025ea56-f753-45d9-ad5a-12e4c5cf9af4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478983243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1478983243
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2304125826
Short name T326
Test name
Test status
Simulation time 104082149 ps
CPU time 1.09 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 209384 kb
Host smart-a24bb46a-61c0-4332-897c-991f2f08c10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304125826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2304125826
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719878637
Short name T126
Test name
Test status
Simulation time 95897865 ps
CPU time 0.88 seconds
Started Aug 07 04:54:14 PM PDT 24
Finished Aug 07 04:54:15 PM PDT 24
Peak memory 198948 kb
Host smart-88849b5a-3186-43d3-9a7a-4f9a9070b187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719878637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2719878637
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1960451955
Short name T486
Test name
Test status
Simulation time 29998441 ps
CPU time 0.71 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 198516 kb
Host smart-f8c70029-08fe-4e72-8d82-7f9001dda3ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960451955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1960451955
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.789337403
Short name T449
Test name
Test status
Simulation time 55179243 ps
CPU time 0.83 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 199880 kb
Host smart-755feb4e-dec5-480f-a339-2d5152a48afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789337403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.789337403
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1140997622
Short name T262
Test name
Test status
Simulation time 108287375 ps
CPU time 0.63 seconds
Started Aug 07 04:54:00 PM PDT 24
Finished Aug 07 04:54:01 PM PDT 24
Peak memory 198384 kb
Host smart-188bed73-0f11-42d2-bdb8-c12ef0186210
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140997622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1140997622
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1462607873
Short name T426
Test name
Test status
Simulation time 37691511 ps
CPU time 0.59 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 197188 kb
Host smart-9c9b0b36-d791-4f72-8f6c-a28e9388b000
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462607873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.1462607873
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2259820503
Short name T222
Test name
Test status
Simulation time 1140544410 ps
CPU time 0.94 seconds
Started Aug 07 04:54:18 PM PDT 24
Finished Aug 07 04:54:19 PM PDT 24
Peak memory 198356 kb
Host smart-2fceb5c7-8af1-4a30-96b4-1b4d34642fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259820503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2259820503
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.1461571702
Short name T462
Test name
Test status
Simulation time 52424824 ps
CPU time 0.57 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198136 kb
Host smart-f9d7914c-cb1d-4d63-9bae-7ee9a85317e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461571702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1461571702
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.2759332803
Short name T412
Test name
Test status
Simulation time 34820503 ps
CPU time 0.6 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 197976 kb
Host smart-7a997b41-2789-4d61-86bc-8fd1257d2105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759332803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2759332803
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3639477427
Short name T168
Test name
Test status
Simulation time 54232508 ps
CPU time 0.66 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 201368 kb
Host smart-9438d7d4-e9a2-470e-9462-e5dfaae11c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639477427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3639477427
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.3105017842
Short name T474
Test name
Test status
Simulation time 63934543 ps
CPU time 0.81 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 198260 kb
Host smart-d72d9a60-26b8-4c8e-9c09-8e7e3d511c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105017842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.3105017842
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2637715255
Short name T498
Test name
Test status
Simulation time 123005607 ps
CPU time 0.85 seconds
Started Aug 07 04:53:57 PM PDT 24
Finished Aug 07 04:53:58 PM PDT 24
Peak memory 209380 kb
Host smart-fd639a7d-d864-407a-8c0d-3cc0b9bbb975
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637715255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2637715255
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1955361907
Short name T246
Test name
Test status
Simulation time 59968659 ps
CPU time 0.7 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 197820 kb
Host smart-51a4e3a6-ca1f-4d11-9682-dbeb7c942417
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955361907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1955361907
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2924400881
Short name T514
Test name
Test status
Simulation time 36981167 ps
CPU time 0.63 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 199288 kb
Host smart-6b5affac-8066-4301-ac8a-64990814bacc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924400881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2924400881
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2103280875
Short name T488
Test name
Test status
Simulation time 65396335 ps
CPU time 0.9 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 199980 kb
Host smart-66cac462-cf28-4b95-abb7-b56160872af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103280875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2103280875
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.307198710
Short name T294
Test name
Test status
Simulation time 50738762 ps
CPU time 0.76 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 199080 kb
Host smart-7876d9be-1707-43b7-a303-290a8930012f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307198710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.307198710
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3156658832
Short name T330
Test name
Test status
Simulation time 31205554 ps
CPU time 0.62 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 197992 kb
Host smart-558c7dfc-16a6-4f4d-b68d-316c577116f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156658832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3156658832
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2272658782
Short name T436
Test name
Test status
Simulation time 161466733 ps
CPU time 0.98 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 198032 kb
Host smart-51dbbc01-8e03-4a1d-954a-18d764b5ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272658782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2272658782
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.651963282
Short name T18
Test name
Test status
Simulation time 62158414 ps
CPU time 0.62 seconds
Started Aug 07 04:54:05 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 197244 kb
Host smart-55a21228-7032-410d-b0ac-18f8791dca19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651963282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.651963282
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3547563035
Short name T201
Test name
Test status
Simulation time 32794363 ps
CPU time 0.64 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198008 kb
Host smart-d6c44dad-1b75-48b6-82e8-000c9a7f96d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547563035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3547563035
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2225582576
Short name T61
Test name
Test status
Simulation time 42120529 ps
CPU time 0.68 seconds
Started Aug 07 04:53:59 PM PDT 24
Finished Aug 07 04:54:00 PM PDT 24
Peak memory 201400 kb
Host smart-ed94ae74-2837-4373-a46b-e3af26e5561e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225582576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2225582576
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.4175548014
Short name T570
Test name
Test status
Simulation time 89628340 ps
CPU time 0.7 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:56 PM PDT 24
Peak memory 198984 kb
Host smart-50c6ca0b-4d13-478c-a1be-a3a46edb4c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175548014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.4175548014
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.200012780
Short name T450
Test name
Test status
Simulation time 130964256 ps
CPU time 0.8 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 201204 kb
Host smart-52d3e19d-7ce7-4e71-bb34-80a7de6f48c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200012780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.200012780
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2847206300
Short name T125
Test name
Test status
Simulation time 80267910 ps
CPU time 0.75 seconds
Started Aug 07 04:53:53 PM PDT 24
Finished Aug 07 04:53:54 PM PDT 24
Peak memory 198156 kb
Host smart-f67cc6fe-eb51-420f-bb48-7746b6336509
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847206300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2847206300
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1497991355
Short name T300
Test name
Test status
Simulation time 32781928 ps
CPU time 0.69 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 198368 kb
Host smart-1875a239-bc9f-4c2b-a227-36147f403669
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497991355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1497991355
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.137398088
Short name T571
Test name
Test status
Simulation time 28803710 ps
CPU time 0.75 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198864 kb
Host smart-a5aef9aa-4b76-402a-804a-ded498efdc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137398088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.137398088
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.488739150
Short name T321
Test name
Test status
Simulation time 152257307 ps
CPU time 0.64 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 199104 kb
Host smart-d4b83f37-3906-4b14-93bd-dd038247676a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488739150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.488739150
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.53791576
Short name T605
Test name
Test status
Simulation time 32450118 ps
CPU time 0.57 seconds
Started Aug 07 04:54:14 PM PDT 24
Finished Aug 07 04:54:15 PM PDT 24
Peak memory 197200 kb
Host smart-cd5f8bd0-ff5c-4b5c-9746-054a6c95f404
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53791576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_m
alfunc.53791576
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.254765392
Short name T386
Test name
Test status
Simulation time 161726123 ps
CPU time 0.94 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:19 PM PDT 24
Peak memory 198000 kb
Host smart-0b8af322-19a5-4b80-a656-4d8bbd5c5ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254765392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.254765392
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1798959708
Short name T446
Test name
Test status
Simulation time 52890050 ps
CPU time 0.63 seconds
Started Aug 07 04:53:57 PM PDT 24
Finished Aug 07 04:53:58 PM PDT 24
Peak memory 197324 kb
Host smart-b07cdd82-09c2-4d2e-9f52-0abbd3cfa71d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798959708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1798959708
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.2570786706
Short name T493
Test name
Test status
Simulation time 23334916 ps
CPU time 0.58 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198264 kb
Host smart-ea993f0d-8cf2-4e24-83aa-69369c750a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570786706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2570786706
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2289538767
Short name T179
Test name
Test status
Simulation time 78339975 ps
CPU time 0.67 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 201324 kb
Host smart-a1471929-2ef6-4d36-a659-76a5a08a8ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289538767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.2289538767
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1734457261
Short name T285
Test name
Test status
Simulation time 54824430 ps
CPU time 0.64 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 199048 kb
Host smart-341bbd79-04d5-4f3c-ae7e-f1cc9d316740
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734457261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1734457261
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.2660902974
Short name T390
Test name
Test status
Simulation time 160787088 ps
CPU time 0.82 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:05 PM PDT 24
Peak memory 209440 kb
Host smart-a343533c-7258-4ad3-b983-2ec18e77a505
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660902974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2660902974
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1267360536
Short name T313
Test name
Test status
Simulation time 218693205 ps
CPU time 0.7 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198156 kb
Host smart-568215b1-abf0-40d9-a210-d8b29922ca76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267360536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1267360536
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.780848262
Short name T409
Test name
Test status
Simulation time 29280699 ps
CPU time 0.64 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 199280 kb
Host smart-011b19dd-daf3-44fe-9f13-62de9caf8a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780848262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.780848262
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2763910345
Short name T489
Test name
Test status
Simulation time 133667661 ps
CPU time 0.92 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 200124 kb
Host smart-a6cc5f0e-f578-4e85-8036-cbafa4cd1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763910345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2763910345
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2202878744
Short name T451
Test name
Test status
Simulation time 29583746 ps
CPU time 0.64 seconds
Started Aug 07 04:54:16 PM PDT 24
Finished Aug 07 04:54:16 PM PDT 24
Peak memory 197928 kb
Host smart-2c2dfa7c-ff98-4b87-b5ea-9c017357f706
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202878744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2202878744
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.281830074
Short name T408
Test name
Test status
Simulation time 165663634 ps
CPU time 0.95 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 197912 kb
Host smart-bcdf2229-3c78-4896-b89a-428beec3268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281830074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.281830074
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3725188277
Short name T218
Test name
Test status
Simulation time 62797408 ps
CPU time 0.67 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 198024 kb
Host smart-28c94348-44fd-4acb-b242-75dac1795c02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725188277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3725188277
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.9028109
Short name T261
Test name
Test status
Simulation time 32725560 ps
CPU time 0.63 seconds
Started Aug 07 04:54:36 PM PDT 24
Finished Aug 07 04:54:36 PM PDT 24
Peak memory 198072 kb
Host smart-ab281c59-1a69-4ded-a62f-64603b2138cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9028109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.9028109
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1383274675
Short name T195
Test name
Test status
Simulation time 78577222 ps
CPU time 0.67 seconds
Started Aug 07 04:54:16 PM PDT 24
Finished Aug 07 04:54:17 PM PDT 24
Peak memory 201232 kb
Host smart-f6f2e1be-27e5-42f3-a97c-b987ab1366cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383274675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1383274675
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.3333022694
Short name T380
Test name
Test status
Simulation time 79205510 ps
CPU time 0.76 seconds
Started Aug 07 04:54:01 PM PDT 24
Finished Aug 07 04:54:02 PM PDT 24
Peak memory 199088 kb
Host smart-09e63abd-12fb-4691-b446-6e1478ff74a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333022694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.3333022694
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.2999880875
Short name T530
Test name
Test status
Simulation time 111482882 ps
CPU time 1.03 seconds
Started Aug 07 04:54:45 PM PDT 24
Finished Aug 07 04:54:46 PM PDT 24
Peak memory 209292 kb
Host smart-e450af27-62ba-4848-933a-d4498f6d6bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999880875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.2999880875
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1965868449
Short name T522
Test name
Test status
Simulation time 214332869 ps
CPU time 0.73 seconds
Started Aug 07 04:54:19 PM PDT 24
Finished Aug 07 04:54:20 PM PDT 24
Peak memory 198104 kb
Host smart-27f01da0-435f-4701-9cae-2d33d4f4d72e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965868449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1965868449
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3949708310
Short name T256
Test name
Test status
Simulation time 31428126 ps
CPU time 0.67 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 198408 kb
Host smart-0dbb87e3-ac65-4630-a5cc-b984f71ccbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949708310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3949708310
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.956953360
Short name T234
Test name
Test status
Simulation time 91562886 ps
CPU time 0.75 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 199860 kb
Host smart-97726cb6-486c-4ddd-9fa8-c21716711eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956953360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.956953360
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3019662885
Short name T163
Test name
Test status
Simulation time 61535640 ps
CPU time 0.64 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:05 PM PDT 24
Peak memory 198360 kb
Host smart-f34e865a-67cd-4b93-bc01-c8b46f69cae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019662885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3019662885
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.569824154
Short name T311
Test name
Test status
Simulation time 28414814 ps
CPU time 0.69 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 194028 kb
Host smart-66463d36-ebb1-407d-9360-470ce86520d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569824154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.569824154
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1038313471
Short name T134
Test name
Test status
Simulation time 173338258 ps
CPU time 0.94 seconds
Started Aug 07 04:54:07 PM PDT 24
Finished Aug 07 04:54:08 PM PDT 24
Peak memory 198096 kb
Host smart-4ffd6828-2f66-4446-9fab-fe529535f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038313471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1038313471
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.530159453
Short name T452
Test name
Test status
Simulation time 37427747 ps
CPU time 0.6 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 197988 kb
Host smart-06df11d3-1981-4b87-91f6-a0ec72cd508d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530159453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.530159453
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1355351745
Short name T239
Test name
Test status
Simulation time 30521339 ps
CPU time 0.63 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198296 kb
Host smart-9d557bee-504c-4b93-8cf7-838bc34813d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355351745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1355351745
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.1288790512
Short name T2
Test name
Test status
Simulation time 79028038 ps
CPU time 0.7 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 201252 kb
Host smart-896c17a6-33aa-47d9-b852-57a7717de68d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288790512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.1288790512
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2289535148
Short name T8
Test name
Test status
Simulation time 43022863 ps
CPU time 0.78 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 198160 kb
Host smart-4feec30a-ee0f-4333-8b6f-3bab0b390462
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289535148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2289535148
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.3391493730
Short name T227
Test name
Test status
Simulation time 98805470 ps
CPU time 0.94 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 209520 kb
Host smart-6836344b-a6d9-4a72-9063-e3077fe463a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391493730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3391493730
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1743964621
Short name T509
Test name
Test status
Simulation time 54226349 ps
CPU time 0.8 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 199436 kb
Host smart-e11ae8de-28fd-4c00-978a-ecfebe260772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743964621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1743964621
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.2917886013
Short name T358
Test name
Test status
Simulation time 52294594 ps
CPU time 0.61 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 199204 kb
Host smart-c72b38a1-dfa2-4cff-b9c7-090bfd1f1776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917886013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2917886013
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.672138383
Short name T583
Test name
Test status
Simulation time 53847324 ps
CPU time 0.94 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 200276 kb
Host smart-50427204-9a21-4853-87c0-a6269fbd99dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672138383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.672138383
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1195577986
Short name T153
Test name
Test status
Simulation time 243090615 ps
CPU time 0.63 seconds
Started Aug 07 04:54:16 PM PDT 24
Finished Aug 07 04:54:17 PM PDT 24
Peak memory 198260 kb
Host smart-d65a71d9-e592-496e-95f9-ecca899569d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195577986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.1195577986
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1356418596
Short name T296
Test name
Test status
Simulation time 33098839 ps
CPU time 0.6 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 198032 kb
Host smart-fcd0baae-eb88-4c31-8b33-01b71033c353
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356418596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1356418596
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.2396311365
Short name T487
Test name
Test status
Simulation time 296975529 ps
CPU time 1 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 196544 kb
Host smart-ccece856-9c9d-4f4d-b53d-11ce7f85c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396311365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2396311365
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2728464425
Short name T203
Test name
Test status
Simulation time 31602893 ps
CPU time 0.62 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 197548 kb
Host smart-ed4099fd-0824-4303-b06c-d7c97305cd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728464425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2728464425
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.523229970
Short name T460
Test name
Test status
Simulation time 29830237 ps
CPU time 0.59 seconds
Started Aug 07 04:54:19 PM PDT 24
Finished Aug 07 04:54:20 PM PDT 24
Peak memory 198084 kb
Host smart-47f130bd-276d-4586-ac75-9fede8067e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523229970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.523229970
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.4074791204
Short name T532
Test name
Test status
Simulation time 75904941 ps
CPU time 0.67 seconds
Started Aug 07 04:53:55 PM PDT 24
Finished Aug 07 04:53:55 PM PDT 24
Peak memory 201264 kb
Host smart-1d1de561-ef83-45f5-8910-48b1482ddb32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074791204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.4074791204
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3038608757
Short name T455
Test name
Test status
Simulation time 112541106 ps
CPU time 0.78 seconds
Started Aug 07 04:54:29 PM PDT 24
Finished Aug 07 04:54:30 PM PDT 24
Peak memory 199172 kb
Host smart-d6b671ab-6f14-4971-b6ff-a1f189b2b6a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038608757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3038608757
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3754271255
Short name T352
Test name
Test status
Simulation time 407965240 ps
CPU time 0.78 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 208964 kb
Host smart-aaaf2520-0bb4-475b-b121-9c5d36f491c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754271255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3754271255
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.891300391
Short name T485
Test name
Test status
Simulation time 74027067 ps
CPU time 0.98 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 199116 kb
Host smart-ee451f6b-e347-4953-9259-641a1bcf3b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891300391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.891300391
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.851193889
Short name T335
Test name
Test status
Simulation time 32489300 ps
CPU time 0.69 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 198460 kb
Host smart-d3ee0974-f9ff-4f03-aeca-89e0e5531e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851193889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.851193889
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.3810071195
Short name T333
Test name
Test status
Simulation time 74513749 ps
CPU time 0.64 seconds
Started Aug 07 04:54:00 PM PDT 24
Finished Aug 07 04:54:06 PM PDT 24
Peak memory 198188 kb
Host smart-22a9fd6c-ae40-4247-8ed5-bedef883fce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810071195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.3810071195
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3839665199
Short name T428
Test name
Test status
Simulation time 38764782 ps
CPU time 0.58 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 197900 kb
Host smart-f660332c-eea8-41dc-9b79-1cebea245446
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839665199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3839665199
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2052181089
Short name T314
Test name
Test status
Simulation time 165896901 ps
CPU time 1.04 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:07 PM PDT 24
Peak memory 196748 kb
Host smart-0eaad568-2066-4b24-a628-2bccb210d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052181089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2052181089
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3014986575
Short name T359
Test name
Test status
Simulation time 52619806 ps
CPU time 0.6 seconds
Started Aug 07 04:54:04 PM PDT 24
Finished Aug 07 04:54:04 PM PDT 24
Peak memory 198080 kb
Host smart-d01a9450-796d-47dd-b551-a2cac1f10e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014986575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3014986575
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.3077515442
Short name T59
Test name
Test status
Simulation time 22734649 ps
CPU time 0.62 seconds
Started Aug 07 04:54:03 PM PDT 24
Finished Aug 07 04:54:03 PM PDT 24
Peak memory 198320 kb
Host smart-e4fa549a-9cb9-4f57-91c9-f55c40721b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077515442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.3077515442
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.720630479
Short name T190
Test name
Test status
Simulation time 37871629 ps
CPU time 0.7 seconds
Started Aug 07 04:54:12 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 201296 kb
Host smart-2932f30b-c1f8-4cdf-b3f1-ae0878659451
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720630479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invali
d.720630479
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.2077918072
Short name T363
Test name
Test status
Simulation time 89720938 ps
CPU time 0.84 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198976 kb
Host smart-96de4b02-8ffe-47f0-a070-27ca4354551c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077918072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2077918072
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2221324965
Short name T308
Test name
Test status
Simulation time 113329235 ps
CPU time 0.97 seconds
Started Aug 07 04:54:25 PM PDT 24
Finished Aug 07 04:54:26 PM PDT 24
Peak memory 209492 kb
Host smart-a4b81d49-6c2a-41c8-8342-3f83b74755f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221324965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2221324965
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2759882085
Short name T274
Test name
Test status
Simulation time 52798738 ps
CPU time 0.71 seconds
Started Aug 07 04:55:46 PM PDT 24
Finished Aug 07 04:55:47 PM PDT 24
Peak memory 197900 kb
Host smart-08b7d859-48aa-4b07-9947-ba60073f2a20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759882085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2759882085
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2432461500
Short name T476
Test name
Test status
Simulation time 55052056 ps
CPU time 0.67 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 198288 kb
Host smart-58a5e99c-ba6d-4f83-acc9-027497c25b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432461500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2432461500
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.4008949825
Short name T174
Test name
Test status
Simulation time 64689251 ps
CPU time 0.89 seconds
Started Aug 07 04:52:46 PM PDT 24
Finished Aug 07 04:52:47 PM PDT 24
Peak memory 199964 kb
Host smart-d447d3a2-0180-44af-8340-c9f6cde80a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008949825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.4008949825
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1491146836
Short name T513
Test name
Test status
Simulation time 75585343 ps
CPU time 0.64 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 198980 kb
Host smart-389f71a6-6c1d-4ccc-9755-e6f2cc96b773
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491146836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1491146836
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2196710121
Short name T444
Test name
Test status
Simulation time 31419132 ps
CPU time 0.6 seconds
Started Aug 07 04:52:50 PM PDT 24
Finished Aug 07 04:52:51 PM PDT 24
Peak memory 197860 kb
Host smart-166489cf-9d42-451e-b1df-45a51b18e5f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196710121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.2196710121
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.209599042
Short name T503
Test name
Test status
Simulation time 309580196 ps
CPU time 0.94 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 197964 kb
Host smart-952863fd-1c49-4779-95e3-acc1cbbd54b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209599042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.209599042
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.1284251992
Short name T315
Test name
Test status
Simulation time 62380561 ps
CPU time 0.58 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:03 PM PDT 24
Peak memory 197980 kb
Host smart-e9c3d247-666e-4b3d-9e79-4075323284fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284251992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.1284251992
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.3797267291
Short name T591
Test name
Test status
Simulation time 44394209 ps
CPU time 0.63 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 198328 kb
Host smart-09ef42be-1ece-485e-b279-e454a6048bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797267291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3797267291
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.4127909892
Short name T191
Test name
Test status
Simulation time 88936001 ps
CPU time 0.68 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 201216 kb
Host smart-8c886c35-ed0e-4e34-b149-217965fbe4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127909892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.4127909892
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1163952251
Short name T325
Test name
Test status
Simulation time 88238133 ps
CPU time 0.84 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:03 PM PDT 24
Peak memory 199060 kb
Host smart-5cc7ebcf-f413-45b7-8da8-540043ccee18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163952251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1163952251
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1023455491
Short name T526
Test name
Test status
Simulation time 99618757 ps
CPU time 0.91 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 209388 kb
Host smart-1cc49f2f-9b7f-4afb-9454-d50ef432632b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023455491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1023455491
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.618994793
Short name T21
Test name
Test status
Simulation time 462373211 ps
CPU time 1.13 seconds
Started Aug 07 04:52:59 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 217424 kb
Host smart-be013bc7-cdc7-4552-bc18-f278f89ffd2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618994793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.618994793
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.4227186446
Short name T143
Test name
Test status
Simulation time 46910256 ps
CPU time 0.68 seconds
Started Aug 07 04:52:58 PM PDT 24
Finished Aug 07 04:52:59 PM PDT 24
Peak memory 198524 kb
Host smart-83d0d4fa-5cde-41b8-b159-c787301da16f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227186446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.4227186446
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3257873886
Short name T439
Test name
Test status
Simulation time 570409478 ps
CPU time 0.87 seconds
Started Aug 07 04:52:52 PM PDT 24
Finished Aug 07 04:52:53 PM PDT 24
Peak memory 199004 kb
Host smart-67514786-7e78-49f7-83d2-3bccf5b8ef85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257873886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3257873886
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1430725857
Short name T587
Test name
Test status
Simulation time 28385465 ps
CPU time 0.71 seconds
Started Aug 07 04:52:57 PM PDT 24
Finished Aug 07 04:52:58 PM PDT 24
Peak memory 198492 kb
Host smart-b990f7d9-19ea-49e0-bb9a-485cfcd69b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430725857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1430725857
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1380092588
Short name T97
Test name
Test status
Simulation time 77132753 ps
CPU time 0.68 seconds
Started Aug 07 04:54:12 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 198368 kb
Host smart-b4d54d42-8d0b-4674-959d-d640ed56d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380092588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1380092588
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2280499375
Short name T162
Test name
Test status
Simulation time 70893023 ps
CPU time 0.63 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:55:41 PM PDT 24
Peak memory 198980 kb
Host smart-f28046f5-47f7-4a9b-983f-0e751fed4605
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280499375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2280499375
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1877665284
Short name T389
Test name
Test status
Simulation time 34159267 ps
CPU time 0.61 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 197960 kb
Host smart-2c134faf-64bc-42a8-81eb-e714d8c6e194
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877665284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1877665284
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.480131309
Short name T242
Test name
Test status
Simulation time 306520574 ps
CPU time 0.95 seconds
Started Aug 07 04:54:22 PM PDT 24
Finished Aug 07 04:54:23 PM PDT 24
Peak memory 198012 kb
Host smart-f503b332-3393-4c96-a655-778d9bf34810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480131309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.480131309
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1551797389
Short name T600
Test name
Test status
Simulation time 39801074 ps
CPU time 0.58 seconds
Started Aug 07 04:54:15 PM PDT 24
Finished Aug 07 04:54:16 PM PDT 24
Peak memory 198060 kb
Host smart-a08080cc-c8da-4b63-b907-b1cafd6c2270
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551797389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1551797389
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.535497558
Short name T319
Test name
Test status
Simulation time 30548895 ps
CPU time 0.59 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:55:38 PM PDT 24
Peak memory 197892 kb
Host smart-d2f67496-bf7b-47e0-a9f0-d7b600a70894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535497558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.535497558
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2124772836
Short name T339
Test name
Test status
Simulation time 39068753 ps
CPU time 0.72 seconds
Started Aug 07 04:54:43 PM PDT 24
Finished Aug 07 04:54:44 PM PDT 24
Peak memory 201276 kb
Host smart-db710db9-80b3-4d2e-9f40-f98c9f3af6e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124772836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2124772836
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.1246281434
Short name T544
Test name
Test status
Simulation time 64461696 ps
CPU time 0.86 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 196828 kb
Host smart-e2c0b2b7-7647-40a6-98b6-970b9042d308
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246281434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1246281434
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3403605433
Short name T342
Test name
Test status
Simulation time 153075425 ps
CPU time 0.89 seconds
Started Aug 07 04:54:24 PM PDT 24
Finished Aug 07 04:54:25 PM PDT 24
Peak memory 201180 kb
Host smart-eac6e59f-63b5-4931-abc2-42a18b036543
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403605433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3403605433
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.3860313411
Short name T395
Test name
Test status
Simulation time 68032968 ps
CPU time 0.85 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 199216 kb
Host smart-fe6b988d-b4fe-4fb6-aa97-539c584d1260
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860313411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3860313411
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1897916859
Short name T272
Test name
Test status
Simulation time 141105652 ps
CPU time 0.61 seconds
Started Aug 07 04:54:29 PM PDT 24
Finished Aug 07 04:54:30 PM PDT 24
Peak memory 198404 kb
Host smart-b1f6713d-8900-47d7-b897-0c2b550c870a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897916859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1897916859
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.3947074112
Short name T322
Test name
Test status
Simulation time 350564725 ps
CPU time 0.75 seconds
Started Aug 07 04:54:43 PM PDT 24
Finished Aug 07 04:54:44 PM PDT 24
Peak memory 198632 kb
Host smart-16e72479-6f2a-4b63-8927-489f110dac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947074112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3947074112
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.160217525
Short name T164
Test name
Test status
Simulation time 49233635 ps
CPU time 0.8 seconds
Started Aug 07 04:54:12 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 199076 kb
Host smart-aff5c440-3629-4053-8593-7572c5eb7306
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160217525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.160217525
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2823556311
Short name T137
Test name
Test status
Simulation time 62548565 ps
CPU time 0.57 seconds
Started Aug 07 04:55:31 PM PDT 24
Finished Aug 07 04:55:33 PM PDT 24
Peak memory 195928 kb
Host smart-ddaa9b6a-64f7-46f9-a637-1d63230655c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823556311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.2823556311
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.332244065
Short name T388
Test name
Test status
Simulation time 586025234 ps
CPU time 0.95 seconds
Started Aug 07 04:54:18 PM PDT 24
Finished Aug 07 04:54:19 PM PDT 24
Peak memory 198036 kb
Host smart-c805128e-b031-43aa-a611-cb73ffbad007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332244065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.332244065
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3728942844
Short name T586
Test name
Test status
Simulation time 172019023 ps
CPU time 0.66 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 197296 kb
Host smart-21e781a3-4a05-4f26-bed8-52ecbdd8ce89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728942844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3728942844
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.258937991
Short name T350
Test name
Test status
Simulation time 214885289 ps
CPU time 0.62 seconds
Started Aug 07 04:54:06 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 198104 kb
Host smart-db52e1cd-a8d6-4c79-9d15-042cc5231092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258937991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.258937991
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.4227637601
Short name T3
Test name
Test status
Simulation time 72540085 ps
CPU time 0.66 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 201312 kb
Host smart-37837e11-e119-4fe3-85b0-185cb7d4fde6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227637601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.4227637601
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2123483368
Short name T558
Test name
Test status
Simulation time 28486494 ps
CPU time 0.74 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 199028 kb
Host smart-b00c09bb-5960-43a3-957d-16682e5a91e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123483368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2123483368
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1729524261
Short name T277
Test name
Test status
Simulation time 128496984 ps
CPU time 0.92 seconds
Started Aug 07 04:54:15 PM PDT 24
Finished Aug 07 04:54:16 PM PDT 24
Peak memory 209416 kb
Host smart-5e42546a-e17c-4c00-84c5-dcf34ae2af99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729524261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1729524261
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1284068381
Short name T533
Test name
Test status
Simulation time 65193221 ps
CPU time 0.74 seconds
Started Aug 07 04:54:12 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 198076 kb
Host smart-a75e3908-0acc-4ccb-9602-c3b278461757
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284068381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1284068381
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.210101108
Short name T518
Test name
Test status
Simulation time 33586725 ps
CPU time 0.68 seconds
Started Aug 07 04:54:17 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 198528 kb
Host smart-9f854da3-1d84-4b6c-b18a-47b1600bb47b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210101108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.210101108
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.560701476
Short name T85
Test name
Test status
Simulation time 70987644 ps
CPU time 0.83 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:13 PM PDT 24
Peak memory 200176 kb
Host smart-f94f474b-24c8-4f07-b4e9-67292c3dabef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560701476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.560701476
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2074503127
Short name T378
Test name
Test status
Simulation time 30181326 ps
CPU time 0.6 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:21 PM PDT 24
Peak memory 197248 kb
Host smart-bc905079-cf9b-430f-8ae6-8a26e049a7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074503127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2074503127
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3015437236
Short name T437
Test name
Test status
Simulation time 166964071 ps
CPU time 0.97 seconds
Started Aug 07 04:54:31 PM PDT 24
Finished Aug 07 04:54:32 PM PDT 24
Peak memory 198000 kb
Host smart-0b1dfc11-c777-4f27-9843-a9203614a004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015437236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3015437236
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.3150108884
Short name T347
Test name
Test status
Simulation time 141695380 ps
CPU time 0.59 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 198048 kb
Host smart-db04a8a4-8d13-4de1-b6e8-223057ccbac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150108884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3150108884
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.3193998478
Short name T336
Test name
Test status
Simulation time 38390615 ps
CPU time 0.64 seconds
Started Aug 07 04:54:14 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 197976 kb
Host smart-6c01500f-f2f7-40ca-ba00-70e0af512e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193998478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3193998478
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.1130481052
Short name T165
Test name
Test status
Simulation time 42466869 ps
CPU time 0.72 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 201352 kb
Host smart-339f70dc-92cc-47c7-a6bf-89a3cffdc8ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130481052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.1130481052
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2287101807
Short name T88
Test name
Test status
Simulation time 121526772 ps
CPU time 0.75 seconds
Started Aug 07 04:54:24 PM PDT 24
Finished Aug 07 04:54:25 PM PDT 24
Peak memory 198992 kb
Host smart-beb606c2-f7bd-40e0-bb39-cfb693c25061
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287101807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2287101807
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.371521172
Short name T341
Test name
Test status
Simulation time 257836520 ps
CPU time 0.74 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 209436 kb
Host smart-a0bd9d7b-9a84-4dcb-bd69-f57d1e66594e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371521172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.371521172
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1328235921
Short name T593
Test name
Test status
Simulation time 139128843 ps
CPU time 0.81 seconds
Started Aug 07 04:54:26 PM PDT 24
Finished Aug 07 04:54:27 PM PDT 24
Peak memory 199468 kb
Host smart-242caed6-7e03-4349-88e2-fd8733246b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328235921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1328235921
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.4031095300
Short name T381
Test name
Test status
Simulation time 26835004 ps
CPU time 0.66 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:17 PM PDT 24
Peak memory 199288 kb
Host smart-30bbdee5-1cd1-4213-ac79-7cfd47506b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031095300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.4031095300
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1393505115
Short name T551
Test name
Test status
Simulation time 49537540 ps
CPU time 0.92 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 200196 kb
Host smart-e53d6d82-a899-4103-ad71-81d2586c3856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393505115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1393505115
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.634061235
Short name T7
Test name
Test status
Simulation time 49185342 ps
CPU time 0.78 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198392 kb
Host smart-296c732c-0bee-4c60-9524-7d5139db61e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634061235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.634061235
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.2392139412
Short name T133
Test name
Test status
Simulation time 157831458 ps
CPU time 0.99 seconds
Started Aug 07 04:54:19 PM PDT 24
Finished Aug 07 04:54:21 PM PDT 24
Peak memory 197996 kb
Host smart-8fe5a79a-6429-4969-8ce8-190a69a53d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392139412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2392139412
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.1179433423
Short name T456
Test name
Test status
Simulation time 46371389 ps
CPU time 0.61 seconds
Started Aug 07 04:54:25 PM PDT 24
Finished Aug 07 04:54:26 PM PDT 24
Peak memory 197248 kb
Host smart-4680ba32-703e-4efb-bd8a-ca2e53a10294
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179433423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1179433423
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3426462936
Short name T221
Test name
Test status
Simulation time 106872569 ps
CPU time 0.65 seconds
Started Aug 07 04:54:23 PM PDT 24
Finished Aug 07 04:54:24 PM PDT 24
Peak memory 198296 kb
Host smart-342b5a4d-dd4e-4308-87ce-f6ae4f9e0aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426462936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3426462936
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1374147900
Short name T584
Test name
Test status
Simulation time 26967830 ps
CPU time 0.62 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198096 kb
Host smart-83293de7-ec45-40c9-8ad1-35208955ea19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374147900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1374147900
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.758958491
Short name T357
Test name
Test status
Simulation time 258786004 ps
CPU time 0.75 seconds
Started Aug 07 04:54:02 PM PDT 24
Finished Aug 07 04:54:03 PM PDT 24
Peak memory 209436 kb
Host smart-0649a3f7-a5a1-4a93-9e06-8e30d984a269
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758958491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.758958491
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1663797126
Short name T4
Test name
Test status
Simulation time 77123659 ps
CPU time 0.64 seconds
Started Aug 07 04:54:10 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198096 kb
Host smart-f4878b44-6c82-4c88-8166-f8c6bb38c5c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663797126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1663797126
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1654156446
Short name T233
Test name
Test status
Simulation time 60087130 ps
CPU time 0.62 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 199260 kb
Host smart-97c1fc0d-ae90-45ac-ab98-55a39d444455
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654156446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1654156446
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3634809065
Short name T310
Test name
Test status
Simulation time 53034042 ps
CPU time 0.68 seconds
Started Aug 07 04:54:25 PM PDT 24
Finished Aug 07 04:54:26 PM PDT 24
Peak memory 198172 kb
Host smart-8ff67db1-ced9-49f9-bfc8-1266a8bc913f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634809065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.3634809065
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2800199684
Short name T230
Test name
Test status
Simulation time 32399094 ps
CPU time 0.63 seconds
Started Aug 07 04:54:28 PM PDT 24
Finished Aug 07 04:54:29 PM PDT 24
Peak memory 197332 kb
Host smart-88511296-d63d-4e42-8d17-0fe704f976ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800199684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.2800199684
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.34259370
Short name T529
Test name
Test status
Simulation time 628554467 ps
CPU time 0.96 seconds
Started Aug 07 04:54:09 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 198116 kb
Host smart-3d83ec11-f1a5-42b5-a1d8-4fa21e5cc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34259370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.34259370
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.3879457901
Short name T83
Test name
Test status
Simulation time 21394581 ps
CPU time 0.6 seconds
Started Aug 07 04:54:55 PM PDT 24
Finished Aug 07 04:54:56 PM PDT 24
Peak memory 198108 kb
Host smart-6a1e0c81-0f90-46a3-be5e-a6ba143f0e0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879457901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3879457901
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3147651286
Short name T559
Test name
Test status
Simulation time 35053103 ps
CPU time 0.61 seconds
Started Aug 07 04:54:35 PM PDT 24
Finished Aug 07 04:54:36 PM PDT 24
Peak memory 197984 kb
Host smart-7f52b940-130f-4ba6-85fe-2fa703bbecfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147651286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3147651286
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.4129323675
Short name T187
Test name
Test status
Simulation time 68439212 ps
CPU time 0.66 seconds
Started Aug 07 04:54:11 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 201312 kb
Host smart-882242c1-7aea-42d1-8c02-136a869b2ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129323675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.4129323675
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2311384785
Short name T613
Test name
Test status
Simulation time 67971355 ps
CPU time 0.75 seconds
Started Aug 07 04:54:39 PM PDT 24
Finished Aug 07 04:54:40 PM PDT 24
Peak memory 198336 kb
Host smart-a1c7992e-79d3-4ac7-a0f6-2613b476ce2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311384785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2311384785
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3992053640
Short name T364
Test name
Test status
Simulation time 161659719 ps
CPU time 0.83 seconds
Started Aug 07 04:54:27 PM PDT 24
Finished Aug 07 04:54:28 PM PDT 24
Peak memory 209440 kb
Host smart-80abd8a8-7bdf-4c73-b83c-fbe32f2237a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992053640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3992053640
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.925788203
Short name T575
Test name
Test status
Simulation time 58403139 ps
CPU time 0.85 seconds
Started Aug 07 04:54:31 PM PDT 24
Finished Aug 07 04:54:32 PM PDT 24
Peak memory 198008 kb
Host smart-f55c4391-38df-4d7f-88eb-7fb9cd5f5b46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925788203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.925788203
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.2330387975
Short name T79
Test name
Test status
Simulation time 61423598 ps
CPU time 0.6 seconds
Started Aug 07 04:54:08 PM PDT 24
Finished Aug 07 04:54:09 PM PDT 24
Peak memory 199316 kb
Host smart-d8abb125-6822-4f3c-a2c0-e25eaeb15344
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330387975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2330387975
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2752628107
Short name T555
Test name
Test status
Simulation time 77570784 ps
CPU time 0.67 seconds
Started Aug 07 04:54:20 PM PDT 24
Finished Aug 07 04:54:21 PM PDT 24
Peak memory 198740 kb
Host smart-957745c3-689e-4c8f-bbd3-433bc714d4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752628107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2752628107
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3452593461
Short name T475
Test name
Test status
Simulation time 54203744 ps
CPU time 0.83 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:45 PM PDT 24
Peak memory 199064 kb
Host smart-7c733b30-7868-4c67-a70c-bf9c7c1b29f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452593461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3452593461
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2299609523
Short name T397
Test name
Test status
Simulation time 38946538 ps
CPU time 0.56 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 197912 kb
Host smart-280451ac-28a0-42fc-93e4-260310a94bed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299609523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2299609523
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.739776871
Short name T219
Test name
Test status
Simulation time 688486079 ps
CPU time 0.96 seconds
Started Aug 07 04:54:38 PM PDT 24
Finished Aug 07 04:54:39 PM PDT 24
Peak memory 198020 kb
Host smart-b997a8f0-0694-4b55-9785-d7ef537fd54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739776871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.739776871
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.3952800920
Short name T445
Test name
Test status
Simulation time 48452562 ps
CPU time 0.57 seconds
Started Aug 07 04:54:47 PM PDT 24
Finished Aug 07 04:54:48 PM PDT 24
Peak memory 198000 kb
Host smart-21c9cb41-1c9c-49a0-9631-5ec226c56b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952800920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3952800920
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.4000114321
Short name T47
Test name
Test status
Simulation time 35150573 ps
CPU time 0.59 seconds
Started Aug 07 04:54:27 PM PDT 24
Finished Aug 07 04:54:27 PM PDT 24
Peak memory 197988 kb
Host smart-ad97dac9-a4bc-490c-8199-7da9f34d49a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000114321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.4000114321
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.3710840764
Short name T183
Test name
Test status
Simulation time 42599819 ps
CPU time 0.68 seconds
Started Aug 07 04:54:29 PM PDT 24
Finished Aug 07 04:54:30 PM PDT 24
Peak memory 201240 kb
Host smart-76444a76-b422-4693-9902-38e155ad5e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710840764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.3710840764
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.806794437
Short name T223
Test name
Test status
Simulation time 91929661 ps
CPU time 0.84 seconds
Started Aug 07 04:54:15 PM PDT 24
Finished Aug 07 04:54:16 PM PDT 24
Peak memory 199024 kb
Host smart-2c7a4c58-6846-4d0e-8076-ac8740b8748b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806794437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.806794437
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.4251987626
Short name T418
Test name
Test status
Simulation time 111837192 ps
CPU time 1.05 seconds
Started Aug 07 04:54:39 PM PDT 24
Finished Aug 07 04:54:40 PM PDT 24
Peak memory 209388 kb
Host smart-ee948b50-ad7f-42b5-ba80-1f58dbb91031
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251987626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.4251987626
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2213034625
Short name T411
Test name
Test status
Simulation time 117500509 ps
CPU time 0.85 seconds
Started Aug 07 04:54:24 PM PDT 24
Finished Aug 07 04:54:24 PM PDT 24
Peak memory 199224 kb
Host smart-c1ef5cf3-3171-4118-b0f3-2bb8b254d923
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213034625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2213034625
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2891231400
Short name T528
Test name
Test status
Simulation time 39624432 ps
CPU time 0.67 seconds
Started Aug 07 04:54:23 PM PDT 24
Finished Aug 07 04:54:24 PM PDT 24
Peak memory 199344 kb
Host smart-1ecbb022-4bb8-44cf-ad83-bf2f59512b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891231400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2891231400
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.4089491904
Short name T95
Test name
Test status
Simulation time 35047967 ps
CPU time 0.7 seconds
Started Aug 07 04:54:39 PM PDT 24
Finished Aug 07 04:54:40 PM PDT 24
Peak memory 198776 kb
Host smart-ebd29d0c-b654-4274-acd8-1189a955af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089491904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.4089491904
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.667044682
Short name T150
Test name
Test status
Simulation time 151827859 ps
CPU time 0.65 seconds
Started Aug 07 04:54:13 PM PDT 24
Finished Aug 07 04:54:14 PM PDT 24
Peak memory 198356 kb
Host smart-f675b45a-cce4-4a4d-8919-cad07557e679
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667044682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.667044682
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.943878650
Short name T301
Test name
Test status
Simulation time 30322652 ps
CPU time 0.64 seconds
Started Aug 07 04:54:33 PM PDT 24
Finished Aug 07 04:54:33 PM PDT 24
Peak memory 197968 kb
Host smart-0a964ddc-0316-4612-b2c4-c768f55f6458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943878650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.943878650
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3705034097
Short name T287
Test name
Test status
Simulation time 161095276 ps
CPU time 0.99 seconds
Started Aug 07 04:54:43 PM PDT 24
Finished Aug 07 04:54:44 PM PDT 24
Peak memory 198012 kb
Host smart-223e6943-44ff-4098-aec1-31abad8781a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705034097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3705034097
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.940056903
Short name T604
Test name
Test status
Simulation time 55349622 ps
CPU time 0.76 seconds
Started Aug 07 04:54:37 PM PDT 24
Finished Aug 07 04:54:38 PM PDT 24
Peak memory 197152 kb
Host smart-6ef5d19c-e03f-47c7-b1fb-1dfd72ead1bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940056903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.940056903
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1143465876
Short name T500
Test name
Test status
Simulation time 163425466 ps
CPU time 0.63 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:54:51 PM PDT 24
Peak memory 197996 kb
Host smart-e7aec2c9-4d23-4545-a218-e5cf84696bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143465876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1143465876
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.2935234946
Short name T564
Test name
Test status
Simulation time 44935835 ps
CPU time 0.71 seconds
Started Aug 07 04:54:20 PM PDT 24
Finished Aug 07 04:54:21 PM PDT 24
Peak memory 201396 kb
Host smart-7c492485-8684-475f-9f11-1a0975461641
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935234946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.2935234946
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1707393748
Short name T590
Test name
Test status
Simulation time 108076134 ps
CPU time 0.62 seconds
Started Aug 07 04:54:37 PM PDT 24
Finished Aug 07 04:54:37 PM PDT 24
Peak memory 198220 kb
Host smart-d99af9b3-d4e0-4214-9e32-bf5de1f44ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707393748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1707393748
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3803759606
Short name T204
Test name
Test status
Simulation time 101311617 ps
CPU time 0.95 seconds
Started Aug 07 04:54:30 PM PDT 24
Finished Aug 07 04:54:31 PM PDT 24
Peak memory 209368 kb
Host smart-66e347b8-cb8c-4b34-b2d2-1c03c4b49b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803759606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3803759606
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1808942053
Short name T264
Test name
Test status
Simulation time 77782253 ps
CPU time 0.78 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:47 PM PDT 24
Peak memory 199132 kb
Host smart-fdb2bb4f-156b-43ef-988d-909cc4d4c775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808942053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1808942053
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2663573249
Short name T404
Test name
Test status
Simulation time 37471581 ps
CPU time 0.65 seconds
Started Aug 07 04:54:38 PM PDT 24
Finished Aug 07 04:54:39 PM PDT 24
Peak memory 198744 kb
Host smart-bebf2063-94d5-4917-944d-78d31ffca10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663573249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2663573249
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3654962791
Short name T608
Test name
Test status
Simulation time 35759345 ps
CPU time 1.15 seconds
Started Aug 07 04:54:43 PM PDT 24
Finished Aug 07 04:54:44 PM PDT 24
Peak memory 200860 kb
Host smart-23b14440-b90e-499a-808f-c4b6aadc88e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654962791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3654962791
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4117301498
Short name T588
Test name
Test status
Simulation time 32239456 ps
CPU time 0.64 seconds
Started Aug 07 04:54:36 PM PDT 24
Finished Aug 07 04:54:36 PM PDT 24
Peak memory 197228 kb
Host smart-cb3ce192-cdde-4929-9e5f-afa4bddcad79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117301498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.4117301498
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.1135286617
Short name T211
Test name
Test status
Simulation time 622722800 ps
CPU time 1 seconds
Started Aug 07 04:54:41 PM PDT 24
Finished Aug 07 04:54:42 PM PDT 24
Peak memory 198108 kb
Host smart-fe623a57-1aef-48e7-a745-183d38ca287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135286617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1135286617
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.2093336273
Short name T269
Test name
Test status
Simulation time 35937432 ps
CPU time 0.65 seconds
Started Aug 07 04:54:30 PM PDT 24
Finished Aug 07 04:54:36 PM PDT 24
Peak memory 197400 kb
Host smart-71d34a7b-abf1-4ebf-b4c8-052a6f574473
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093336273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2093336273
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2633753565
Short name T334
Test name
Test status
Simulation time 65771784 ps
CPU time 0.57 seconds
Started Aug 07 04:54:51 PM PDT 24
Finished Aug 07 04:54:52 PM PDT 24
Peak memory 197900 kb
Host smart-9577dc17-9568-4b54-aac3-929df5ff389d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633753565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2633753565
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2525454371
Short name T176
Test name
Test status
Simulation time 53565518 ps
CPU time 0.68 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:54:58 PM PDT 24
Peak memory 201292 kb
Host smart-a8f4cf11-1fe4-493b-834b-a3369670048c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525454371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2525454371
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2922691760
Short name T303
Test name
Test status
Simulation time 39963408 ps
CPU time 0.7 seconds
Started Aug 07 04:54:47 PM PDT 24
Finished Aug 07 04:54:48 PM PDT 24
Peak memory 198220 kb
Host smart-bc1f9ea9-26a6-4ee1-99ee-6ccc4b9df6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922691760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2922691760
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3625240855
Short name T384
Test name
Test status
Simulation time 162246964 ps
CPU time 0.83 seconds
Started Aug 07 04:54:42 PM PDT 24
Finished Aug 07 04:54:43 PM PDT 24
Peak memory 209528 kb
Host smart-77cfd040-fc59-4e1b-8194-3dc6136a6405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625240855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3625240855
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3701070573
Short name T415
Test name
Test status
Simulation time 58714249 ps
CPU time 0.8 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:47 PM PDT 24
Peak memory 198048 kb
Host smart-d16b0f71-bbb3-4763-9aec-e3d7bb33eb62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701070573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3701070573
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2836256632
Short name T501
Test name
Test status
Simulation time 37214237 ps
CPU time 0.65 seconds
Started Aug 07 04:54:41 PM PDT 24
Finished Aug 07 04:54:42 PM PDT 24
Peak memory 198476 kb
Host smart-415bf0b8-924b-4b69-8a15-479e3b405823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836256632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2836256632
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3706651134
Short name T565
Test name
Test status
Simulation time 33081168 ps
CPU time 0.85 seconds
Started Aug 07 04:54:41 PM PDT 24
Finished Aug 07 04:54:42 PM PDT 24
Peak memory 199900 kb
Host smart-2d32a992-161e-467e-9661-3aa32185ba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706651134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3706651134
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1478947649
Short name T243
Test name
Test status
Simulation time 61924498 ps
CPU time 0.71 seconds
Started Aug 07 04:54:45 PM PDT 24
Finished Aug 07 04:54:46 PM PDT 24
Peak memory 199004 kb
Host smart-179dc820-3e15-4642-a578-e8f6ba076664
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478947649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1478947649
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1280786110
Short name T292
Test name
Test status
Simulation time 28469932 ps
CPU time 0.62 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:01 PM PDT 24
Peak memory 197900 kb
Host smart-b67b23a2-8c11-42be-9fd4-725d48cd0fa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280786110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.1280786110
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.3618435381
Short name T136
Test name
Test status
Simulation time 158706246 ps
CPU time 1.03 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:54:58 PM PDT 24
Peak memory 198128 kb
Host smart-be366657-5040-493b-893c-158474c812ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618435381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3618435381
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.2350184230
Short name T432
Test name
Test status
Simulation time 49154356 ps
CPU time 0.67 seconds
Started Aug 07 04:54:38 PM PDT 24
Finished Aug 07 04:54:39 PM PDT 24
Peak memory 197268 kb
Host smart-332fac2c-60f6-431c-a68b-53ba4f3bd263
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350184230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2350184230
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.1132560514
Short name T560
Test name
Test status
Simulation time 79772301 ps
CPU time 0.58 seconds
Started Aug 07 04:54:27 PM PDT 24
Finished Aug 07 04:54:28 PM PDT 24
Peak memory 198012 kb
Host smart-0f7d6a38-2f35-4d6a-b804-e148bb564dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132560514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1132560514
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.105507668
Short name T29
Test name
Test status
Simulation time 150899345 ps
CPU time 0.66 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:54:49 PM PDT 24
Peak memory 201044 kb
Host smart-cccc587c-f75d-4012-adc2-f19b0534cf6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105507668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invali
d.105507668
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3808006792
Short name T327
Test name
Test status
Simulation time 200245107 ps
CPU time 0.69 seconds
Started Aug 07 04:54:47 PM PDT 24
Finished Aug 07 04:54:48 PM PDT 24
Peak memory 198252 kb
Host smart-df23eb31-3aff-4ba3-86f9-cade41fe494b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808006792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3808006792
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.983374070
Short name T377
Test name
Test status
Simulation time 111138850 ps
CPU time 1.05 seconds
Started Aug 07 04:54:36 PM PDT 24
Finished Aug 07 04:54:38 PM PDT 24
Peak memory 209308 kb
Host smart-03d13546-02c7-4b3a-960a-4140163c1c7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983374070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.983374070
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.778385475
Short name T75
Test name
Test status
Simulation time 56221613 ps
CPU time 0.82 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:45 PM PDT 24
Peak memory 198096 kb
Host smart-2cc00b84-f942-4e4f-b872-d798b948e113
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778385475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_
mubi.778385475
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.325979751
Short name T553
Test name
Test status
Simulation time 56590657 ps
CPU time 0.65 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:46 PM PDT 24
Peak memory 198396 kb
Host smart-4277ce2f-9678-4a35-b37f-5926c7b05801
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325979751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.325979751
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1104028784
Short name T589
Test name
Test status
Simulation time 118716010 ps
CPU time 0.68 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:54:55 PM PDT 24
Peak memory 198456 kb
Host smart-58c7be80-ea28-49ce-90fb-c2c1f9772aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104028784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1104028784
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1334132640
Short name T569
Test name
Test status
Simulation time 59936350 ps
CPU time 0.82 seconds
Started Aug 07 04:54:36 PM PDT 24
Finished Aug 07 04:54:37 PM PDT 24
Peak memory 198436 kb
Host smart-e7d7ff96-b7c1-4be9-bffd-4856bac1f407
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334132640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1334132640
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1531683614
Short name T616
Test name
Test status
Simulation time 36853968 ps
CPU time 0.57 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:03 PM PDT 24
Peak memory 197960 kb
Host smart-6d992f53-4330-40c5-9989-2084d08a1abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531683614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1531683614
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.2968985120
Short name T427
Test name
Test status
Simulation time 403532203 ps
CPU time 0.96 seconds
Started Aug 07 04:54:42 PM PDT 24
Finished Aug 07 04:54:43 PM PDT 24
Peak memory 197988 kb
Host smart-c7675e3e-75d4-4080-a542-f930a88a8975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968985120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.2968985120
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.4125190193
Short name T521
Test name
Test status
Simulation time 31124899 ps
CPU time 0.7 seconds
Started Aug 07 04:54:41 PM PDT 24
Finished Aug 07 04:54:42 PM PDT 24
Peak memory 197356 kb
Host smart-5ec5958c-021b-44f9-b590-9274ecb514de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125190193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.4125190193
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.865369007
Short name T275
Test name
Test status
Simulation time 34536969 ps
CPU time 0.68 seconds
Started Aug 07 04:54:41 PM PDT 24
Finished Aug 07 04:54:41 PM PDT 24
Peak memory 197980 kb
Host smart-ecd0593f-481d-4c9e-895a-1541646bbfab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865369007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.865369007
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1740431575
Short name T193
Test name
Test status
Simulation time 46863070 ps
CPU time 0.76 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:45 PM PDT 24
Peak memory 201240 kb
Host smart-8884325a-589f-4e5a-a46d-7fdbb7436c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740431575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1740431575
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.3346100904
Short name T290
Test name
Test status
Simulation time 171486735 ps
CPU time 0.71 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:54:59 PM PDT 24
Peak memory 199012 kb
Host smart-cd340f85-7759-4935-85a5-c40c1bf97efa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346100904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.3346100904
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3852010841
Short name T419
Test name
Test status
Simulation time 143976396 ps
CPU time 0.85 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:45 PM PDT 24
Peak memory 209364 kb
Host smart-f65d7ce1-6cdb-4ad0-981b-5f48eb9a06e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852010841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3852010841
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.617365318
Short name T547
Test name
Test status
Simulation time 70199314 ps
CPU time 0.9 seconds
Started Aug 07 04:54:42 PM PDT 24
Finished Aug 07 04:54:44 PM PDT 24
Peak memory 199244 kb
Host smart-22a75d12-ac86-49a5-bbd9-59cb21a49bd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617365318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.617365318
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2211742177
Short name T467
Test name
Test status
Simulation time 59188035 ps
CPU time 0.61 seconds
Started Aug 07 04:54:40 PM PDT 24
Finished Aug 07 04:54:46 PM PDT 24
Peak memory 198424 kb
Host smart-81d4ef6d-434c-44d6-87bf-188dde04fa54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211742177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2211742177
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1203817799
Short name T617
Test name
Test status
Simulation time 36562701 ps
CPU time 0.75 seconds
Started Aug 07 04:52:48 PM PDT 24
Finished Aug 07 04:52:49 PM PDT 24
Peak memory 199068 kb
Host smart-54e6d145-53cc-4475-b43f-b6e18f5061db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203817799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1203817799
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1177389569
Short name T151
Test name
Test status
Simulation time 59874670 ps
CPU time 0.82 seconds
Started Aug 07 04:52:50 PM PDT 24
Finished Aug 07 04:52:52 PM PDT 24
Peak memory 198404 kb
Host smart-63bef475-6e6f-445a-bc52-3479fdb09b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177389569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1177389569
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1972814650
Short name T224
Test name
Test status
Simulation time 49804418 ps
CPU time 0.56 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 198028 kb
Host smart-18eac6af-1990-4aa3-b599-835c3e7ba016
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972814650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1972814650
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2503759697
Short name T361
Test name
Test status
Simulation time 158833613 ps
CPU time 1 seconds
Started Aug 07 04:53:04 PM PDT 24
Finished Aug 07 04:53:05 PM PDT 24
Peak memory 198160 kb
Host smart-d131f364-47c9-422a-bab8-bd7ce37b0994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503759697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2503759697
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.4109997303
Short name T19
Test name
Test status
Simulation time 43591528 ps
CPU time 0.64 seconds
Started Aug 07 04:52:57 PM PDT 24
Finished Aug 07 04:52:58 PM PDT 24
Peak memory 197960 kb
Host smart-cfedf050-41f3-418e-a188-8a744976942a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109997303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4109997303
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.118464710
Short name T254
Test name
Test status
Simulation time 52008548 ps
CPU time 0.69 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 198344 kb
Host smart-76b842b3-e68b-486c-a4eb-98fc66edfcba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118464710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.118464710
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2761041890
Short name T349
Test name
Test status
Simulation time 116129812 ps
CPU time 0.77 seconds
Started Aug 07 04:52:59 PM PDT 24
Finished Aug 07 04:53:00 PM PDT 24
Peak memory 198288 kb
Host smart-c7b00f3d-c165-49f8-8d59-e71ff79d921e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761041890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2761041890
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.3592047028
Short name T368
Test name
Test status
Simulation time 119231427 ps
CPU time 0.84 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 209464 kb
Host smart-207c693d-95cf-4980-b88e-bfaeb4e9db8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592047028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3592047028
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3345599638
Short name T582
Test name
Test status
Simulation time 119743089 ps
CPU time 0.78 seconds
Started Aug 07 04:53:03 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 197940 kb
Host smart-4063866d-1154-46b8-81b8-ad1a8a85c68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345599638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3345599638
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2207121139
Short name T552
Test name
Test status
Simulation time 57383917 ps
CPU time 0.66 seconds
Started Aug 07 04:52:54 PM PDT 24
Finished Aug 07 04:52:54 PM PDT 24
Peak memory 199324 kb
Host smart-02df5625-de9a-4c20-90b1-4f5d50d28065
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207121139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2207121139
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1400464180
Short name T574
Test name
Test status
Simulation time 34809096 ps
CPU time 1.1 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 200408 kb
Host smart-20952ff0-7817-46aa-b4df-64f6dc6f5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400464180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1400464180
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3758406768
Short name T345
Test name
Test status
Simulation time 59971044 ps
CPU time 0.81 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198164 kb
Host smart-5cc2b6bc-b80d-4485-acda-4289d987d3fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758406768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.3758406768
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.178950547
Short name T402
Test name
Test status
Simulation time 31837202 ps
CPU time 0.67 seconds
Started Aug 07 04:53:04 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 197204 kb
Host smart-b9fb5660-b97c-4260-a6bb-cfb00ba37ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178950547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_m
alfunc.178950547
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.662726450
Short name T212
Test name
Test status
Simulation time 632870221 ps
CPU time 0.95 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 198364 kb
Host smart-17264fc2-ca67-477f-aa2e-7ec707e4efbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662726450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.662726450
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.464924126
Short name T527
Test name
Test status
Simulation time 73291687 ps
CPU time 0.65 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198016 kb
Host smart-803b0f8a-e6e6-4895-a604-853019bdfc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464924126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.464924126
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1202554259
Short name T236
Test name
Test status
Simulation time 47065261 ps
CPU time 0.6 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:03 PM PDT 24
Peak memory 198040 kb
Host smart-53bb127b-1857-4fe8-80a6-73ded564f593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202554259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1202554259
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2551799302
Short name T182
Test name
Test status
Simulation time 44125004 ps
CPU time 0.74 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 201304 kb
Host smart-1fc714d2-d48b-4300-946a-7663ef2864f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551799302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2551799302
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1544940765
Short name T531
Test name
Test status
Simulation time 141824300 ps
CPU time 0.81 seconds
Started Aug 07 04:53:08 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 199072 kb
Host smart-643633b9-1364-4902-b071-4a5dff590eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544940765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1544940765
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.92703559
Short name T548
Test name
Test status
Simulation time 100412593 ps
CPU time 1.07 seconds
Started Aug 07 04:53:00 PM PDT 24
Finished Aug 07 04:53:01 PM PDT 24
Peak memory 209456 kb
Host smart-69aa3d12-e780-4080-b9d0-6f39cc15aa03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92703559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.92703559
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1095388952
Short name T298
Test name
Test status
Simulation time 146978639 ps
CPU time 0.68 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:10 PM PDT 24
Peak memory 198104 kb
Host smart-571f6a4e-6a80-4ee3-a040-e1959e99bf4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095388952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1095388952
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.548339828
Short name T127
Test name
Test status
Simulation time 58236754 ps
CPU time 0.63 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:10 PM PDT 24
Peak memory 198420 kb
Host smart-b9d59aa2-636b-4466-8e67-adeeff57db05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548339828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.548339828
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.1730445907
Short name T557
Test name
Test status
Simulation time 78223566 ps
CPU time 0.97 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 200588 kb
Host smart-3b44fd72-b9bd-412f-96f4-1ca30b3dfe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730445907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1730445907
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.2334110424
Short name T394
Test name
Test status
Simulation time 69464510 ps
CPU time 0.67 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198472 kb
Host smart-1d6d98c4-9725-4a64-8f0c-e6871648b9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334110424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.2334110424
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1250956088
Short name T567
Test name
Test status
Simulation time 28810761 ps
CPU time 0.66 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:05 PM PDT 24
Peak memory 197316 kb
Host smart-53d76437-fad0-4691-b890-86993d2a285e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250956088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.1250956088
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.399098727
Short name T208
Test name
Test status
Simulation time 317435090 ps
CPU time 0.99 seconds
Started Aug 07 04:53:01 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 198068 kb
Host smart-91e57c05-1b6c-4a61-bd3c-27e5acddebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399098727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.399098727
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.581689311
Short name T448
Test name
Test status
Simulation time 58137175 ps
CPU time 0.71 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 197208 kb
Host smart-79602ff7-83f8-4b73-9e51-51fe45b42a4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581689311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.581689311
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.4289646030
Short name T238
Test name
Test status
Simulation time 59310628 ps
CPU time 0.63 seconds
Started Aug 07 04:53:10 PM PDT 24
Finished Aug 07 04:53:11 PM PDT 24
Peak memory 198040 kb
Host smart-8ed3bbe0-ba47-454e-8836-cd651e8de863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289646030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.4289646030
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.2633728967
Short name T483
Test name
Test status
Simulation time 88875183 ps
CPU time 0.93 seconds
Started Aug 07 04:53:03 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 198456 kb
Host smart-7b26d487-1331-45f9-8fa7-1a091f280484
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633728967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2633728967
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.621345490
Short name T259
Test name
Test status
Simulation time 108175638 ps
CPU time 1.08 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 209388 kb
Host smart-651ccc93-4d58-4702-9bab-275b9b8aff25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621345490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.621345490
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1948511008
Short name T35
Test name
Test status
Simulation time 181299290 ps
CPU time 0.79 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 199228 kb
Host smart-7e735394-2acc-42ac-b128-1aeec4174e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948511008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1948511008
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3226078580
Short name T249
Test name
Test status
Simulation time 167083898 ps
CPU time 0.61 seconds
Started Aug 07 04:53:10 PM PDT 24
Finished Aug 07 04:53:11 PM PDT 24
Peak memory 198524 kb
Host smart-a969d981-d382-4653-ba89-53e38bccb0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226078580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3226078580
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1551933161
Short name T470
Test name
Test status
Simulation time 76173292 ps
CPU time 0.66 seconds
Started Aug 07 04:53:14 PM PDT 24
Finished Aug 07 04:53:14 PM PDT 24
Peak memory 198728 kb
Host smart-2850b0af-eea7-4620-aec7-72785942170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551933161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1551933161
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.183312421
Short name T139
Test name
Test status
Simulation time 110787827 ps
CPU time 0.66 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 199092 kb
Host smart-21c8db75-11dc-4a6b-8341-c5bb3da30a00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183312421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.183312421
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2131853812
Short name T353
Test name
Test status
Simulation time 28831206 ps
CPU time 0.62 seconds
Started Aug 07 04:53:17 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 197312 kb
Host smart-b0254647-2144-4245-87c7-6bb33fe460ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131853812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2131853812
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2426673754
Short name T348
Test name
Test status
Simulation time 160237694 ps
CPU time 0.96 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198328 kb
Host smart-5abf82fe-ecb2-417d-a106-71d41e72e0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426673754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2426673754
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2574028168
Short name T241
Test name
Test status
Simulation time 55157661 ps
CPU time 0.7 seconds
Started Aug 07 04:53:16 PM PDT 24
Finished Aug 07 04:53:17 PM PDT 24
Peak memory 197276 kb
Host smart-dc4cd8bc-833f-434f-b49b-3e238025a329
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574028168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2574028168
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.2710798677
Short name T216
Test name
Test status
Simulation time 46605986 ps
CPU time 0.65 seconds
Started Aug 07 04:53:13 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198396 kb
Host smart-ba0418e8-fd18-447c-b4ea-52d9a84978d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710798677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2710798677
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3177996817
Short name T169
Test name
Test status
Simulation time 40121581 ps
CPU time 0.69 seconds
Started Aug 07 04:53:10 PM PDT 24
Finished Aug 07 04:53:11 PM PDT 24
Peak memory 201268 kb
Host smart-2bd0a905-eceb-4bbe-a3fc-82558f350dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177996817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.3177996817
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.3122028892
Short name T250
Test name
Test status
Simulation time 141236021 ps
CPU time 0.74 seconds
Started Aug 07 04:53:09 PM PDT 24
Finished Aug 07 04:53:10 PM PDT 24
Peak memory 199140 kb
Host smart-26d9f306-0ae0-4a78-9a41-994d18ff73a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122028892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.3122028892
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.4138414791
Short name T231
Test name
Test status
Simulation time 107821945 ps
CPU time 0.93 seconds
Started Aug 07 04:53:03 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 209376 kb
Host smart-b9181399-6362-4391-ac87-e46f3d115243
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138414791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.4138414791
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2982580660
Short name T369
Test name
Test status
Simulation time 82344024 ps
CPU time 0.72 seconds
Started Aug 07 04:53:05 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 198024 kb
Host smart-b079aff0-672b-4972-9d5f-75b27abcc21a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982580660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2982580660
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2069672161
Short name T78
Test name
Test status
Simulation time 57788656 ps
CPU time 0.66 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 198412 kb
Host smart-958d8a70-ea96-4619-8e25-17f0f1392946
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069672161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2069672161
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.4227279634
Short name T141
Test name
Test status
Simulation time 28780587 ps
CPU time 0.67 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 198380 kb
Host smart-0d39031e-2a00-47f6-8c94-bbdc6dcf3c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227279634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.4227279634
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1019398373
Short name T516
Test name
Test status
Simulation time 46731297 ps
CPU time 0.86 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 200180 kb
Host smart-804f586a-1b1f-4538-8dd3-6063e9167986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019398373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1019398373
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.931428857
Short name T148
Test name
Test status
Simulation time 58407896 ps
CPU time 0.84 seconds
Started Aug 07 04:53:03 PM PDT 24
Finished Aug 07 04:53:04 PM PDT 24
Peak memory 199056 kb
Host smart-94ce148e-7ed6-4143-847b-aedfb51d6b16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931428857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.931428857
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3843119288
Short name T255
Test name
Test status
Simulation time 72578981 ps
CPU time 0.6 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 197256 kb
Host smart-9049e359-3e36-4171-be20-384835f4e537
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843119288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3843119288
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1988101613
Short name T282
Test name
Test status
Simulation time 1014207161 ps
CPU time 0.94 seconds
Started Aug 07 04:53:02 PM PDT 24
Finished Aug 07 04:53:03 PM PDT 24
Peak memory 197964 kb
Host smart-7abc53a8-ecfa-443d-a481-cca80e447269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988101613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1988101613
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.1285812992
Short name T284
Test name
Test status
Simulation time 132321434 ps
CPU time 0.55 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 197980 kb
Host smart-b3bff725-1dbb-4992-ade8-51abc844b30c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285812992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1285812992
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2676320369
Short name T248
Test name
Test status
Simulation time 68607149 ps
CPU time 0.64 seconds
Started Aug 07 04:53:15 PM PDT 24
Finished Aug 07 04:53:16 PM PDT 24
Peak memory 198024 kb
Host smart-1ce1a9d2-d2d7-449b-a872-15cb1f571efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676320369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2676320369
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3842187425
Short name T479
Test name
Test status
Simulation time 78147702 ps
CPU time 0.89 seconds
Started Aug 07 04:53:12 PM PDT 24
Finished Aug 07 04:53:13 PM PDT 24
Peak memory 198408 kb
Host smart-18974887-bbe1-4cda-b86a-8bb9609179e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842187425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3842187425
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.862456469
Short name T309
Test name
Test status
Simulation time 182193142 ps
CPU time 0.81 seconds
Started Aug 07 04:53:06 PM PDT 24
Finished Aug 07 04:53:07 PM PDT 24
Peak memory 209384 kb
Host smart-1dd6f389-5a04-4771-ac55-790ba88109a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862456469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.862456469
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.4238252878
Short name T430
Test name
Test status
Simulation time 229385216 ps
CPU time 0.82 seconds
Started Aug 07 04:53:07 PM PDT 24
Finished Aug 07 04:53:08 PM PDT 24
Peak memory 199092 kb
Host smart-580e4a44-878f-44d8-93a3-f55d099f0645
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238252878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4238252878
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2229804577
Short name T51
Test name
Test status
Simulation time 95375988 ps
CPU time 0.61 seconds
Started Aug 07 04:53:04 PM PDT 24
Finished Aug 07 04:53:05 PM PDT 24
Peak memory 198492 kb
Host smart-254c7994-869f-4b90-87c5-ff1015fbc6db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229804577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2229804577
Directory /workspace/9.pwrmgr_smoke/latest
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