Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33267 1 T1 372 T2 5 T3 6
auto[1] 31890 1 T1 356 T2 18 T6 534


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33304 1 T1 357 T2 13 T3 4
auto[1] 31853 1 T1 371 T2 10 T3 2


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32037 1 T1 340 T2 12 T3 4
auto[1] 33120 1 T1 388 T2 11 T3 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36798 1 T1 413 T2 13 T3 3
auto[1] 28359 1 T1 315 T2 10 T3 3


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31617 1 T1 354 T2 6 T6 575
auto[1] 33540 1 T1 374 T2 17 T3 6


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33051 1 T1 351 T2 15 T3 4
auto[1] 32106 1 T1 377 T2 8 T3 2


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1113 1 T1 9 T2 1 T6 21
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 859 1 T1 6 T2 1 T6 13
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1139 1 T1 8 T6 32 T7 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 881 1 T1 7 T6 22 T7 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1133 1 T1 6 T3 1 T6 24
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 870 1 T1 5 T3 1 T6 15
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1804 1 T1 29 T4 1 T6 31
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1550 1 T1 24 T4 1 T6 27
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1121 1 T1 14 T6 30 T7 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 838 1 T1 9 T6 22 T7 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1135 1 T1 8 T2 1 T6 20
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 866 1 T1 7 T6 15 T7 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1188 1 T1 14 T2 1 T6 13
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 936 1 T1 12 T2 1 T6 10
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1139 1 T1 12 T3 1 T6 23
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 885 1 T1 9 T3 1 T6 19
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1060 1 T1 10 T6 18 T7 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 811 1 T1 6 T6 13 T7 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1129 1 T1 16 T6 21 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 843 1 T1 11 T6 15 T8 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1129 1 T1 13 T3 1 T6 22
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 875 1 T1 9 T3 1 T6 19
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1144 1 T1 14 T6 13 T13 16
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 880 1 T1 10 T6 9 T13 15
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1135 1 T1 20 T6 16 T7 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 870 1 T1 19 T6 11 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1163 1 T1 15 T6 19 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 897 1 T1 9 T6 14 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1104 1 T1 10 T6 15 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 853 1 T1 8 T6 11 T7 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1097 1 T1 12 T6 17 T7 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 820 1 T1 11 T6 11 T7 4
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1117 1 T1 9 T6 24 T7 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 886 1 T1 8 T6 16 T7 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1112 1 T1 10 T6 24 T7 4
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 856 1 T1 7 T6 20 T7 4
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1107 1 T1 9 T6 24 T7 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 878 1 T1 6 T6 18 T7 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1103 1 T1 19 T2 2 T6 12
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 857 1 T1 15 T2 2 T6 8
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1091 1 T1 14 T6 16 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 818 1 T1 11 T6 12 T7 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1135 1 T1 17 T2 1 T6 18
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 844 1 T1 13 T2 1 T6 16
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1181 1 T1 11 T6 20 T7 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 908 1 T1 8 T6 15 T7 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1115 1 T1 13 T2 1 T6 26
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 839 1 T1 8 T2 1 T6 18
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1098 1 T1 14 T6 20 T7 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 843 1 T1 10 T6 18 T7 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1116 1 T1 13 T6 19 T7 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 827 1 T1 10 T6 12 T7 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1169 1 T1 15 T2 4 T6 22
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 916 1 T1 11 T2 4 T6 19
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1112 1 T1 7 T2 1 T6 17
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 834 1 T1 5 T6 11 T74 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1107 1 T1 16 T6 19 T7 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 855 1 T1 12 T6 17 T7 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1174 1 T1 9 T2 1 T6 12
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 878 1 T1 7 T6 10 T7 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1225 1 T1 9 T6 12 T7 4
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 943 1 T1 7 T6 8 T7 4
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1103 1 T1 18 T6 19 T7 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 843 1 T1 15 T6 12 T7 1

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