Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
enable_cp 2 0 2 100.00 100 1 1 2
reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 6 0 6 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 18000 1 T1 309 T3 1 T5 2
auto[1] 27169 1 T1 315 T3 4 T4 1


Summary for Variable reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for reset_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 37404 1 T1 491 T2 10 T3 3
auto[1] 10201 1 T1 133 T3 2 T4 1


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19357 1 T1 309 T3 2 T4 1
auto[1] 28248 1 T1 315 T2 10 T3 3


Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
reset_cp   enable_cp   sleep_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] 4341 1 T1 99 T5 1 T6 64
auto[0] auto[0] auto[1] 10139 1 T1 158 T3 1 T6 188
auto[0] auto[1] auto[0] 4541 1 T1 77 T5 4 T6 63
auto[0] auto[1] auto[1] 15947 1 T1 157 T3 2 T6 281
auto[1] auto[0] auto[0] 3520 1 T1 52 T5 1 T6 60
auto[1] auto[1] auto[0] 6681 1 T1 81 T3 2 T4 1


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal