Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	1	15	93.75	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

171463

1

T1

436

T2

1

T3

16

on

18923

1

T5

2

T20

254

T21

4

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

168416

1

T1

436

T2

1

T3

16

on

25490

1

T5

2

T20

237

T21

1

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

35037

1

T1

348

T3

12

T5

2

true

19495

1

T1

88

T2

1

T3

4

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

20367

1

T1

174

T3

6

T5

3

true

41638

1

T1

262

T2

1

T3

10

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for blockers_cross

Uncovered bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[on]	[on]	0	1	1

Covered bins

done_cp

good_cp

dft_cp

debug_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

false

off

off

17604

1

T1

174

T3

6

T6

342

false

false

off

on

166

1

T20

5

T21

1

T29

3

false

false

on

off

233

1

T20

3

T153

2

T168

2

false

false

on

on

199

1

T20

1

T29

3

T153

4

false

true

off

off

14890

1

T1

174

T3

6

T6

342

false

true

off

on

4

1

T171

1

T172

1

T173

1

false

true

on

off

7

1

T166

1

T174

1

T175

1

true

false

off

off

69

1

T21

2

T22

3

T165

1

true

false

off

on

14

1

T21

1

T176

2

T177

1

true

false

on

off

21

1

T166

1

T174

1

T175

1

true

false

on

on

86

1

T5

1

T21

1

T165

3

true

true

off

off

13926

1

T1

88

T2

1

T3

4

true

true

off

on

332

1

T20

10

T21

1

T29

3

true

true

on

off

399

1

T20

4

T29

3

T153

4

true

true

on

on

338

1

T20

6

T29

5

T153

6