Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33425 1 T2 4 T3 1 T4 10
auto[1] 31502 1 T2 10 T3 5 T4 18


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33106 1 T2 4 T3 5 T4 15
auto[1] 31821 1 T2 10 T3 1 T4 13


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31590 1 T2 10 T3 3 T4 15
auto[1] 33337 1 T2 4 T3 3 T4 13


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36474 1 T2 7 T3 4 T4 18
auto[1] 28453 1 T2 7 T3 2 T4 10


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31801 1 T2 4 T3 3 T4 10
auto[1] 33126 1 T2 10 T3 3 T4 18


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33442 1 T2 6 T3 2 T4 14
auto[1] 31485 1 T2 8 T3 4 T4 14


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1103 1 T4 1 T5 29 T10 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 855 1 T5 18 T10 2 T39 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1138 1 T5 19 T10 2 T74 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 901 1 T5 12 T10 2 T74 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1110 1 T5 28 T10 2 T34 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 836 1 T5 18 T10 2 T34 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1837 1 T5 40 T10 2 T38 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1600 1 T5 36 T10 2 T38 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1084 1 T5 28 T10 3 T38 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 853 1 T5 19 T10 3 T34 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1154 1 T5 26 T10 1 T38 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 880 1 T5 18 T10 1 T38 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1068 1 T2 1 T3 1 T4 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 835 1 T2 1 T4 1 T5 12
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1118 1 T5 12 T10 2 T38 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 869 1 T5 9 T10 2 T34 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1130 1 T4 1 T5 27 T10 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 870 1 T5 20 T10 2 T73 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1112 1 T5 21 T10 1 T73 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 857 1 T5 11 T10 1 T73 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1139 1 T4 1 T5 27 T38 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 908 1 T5 20 T38 1 T13 12
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1135 1 T5 27 T10 2 T38 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 901 1 T5 22 T10 2 T75 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1139 1 T4 1 T5 23 T10 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 913 1 T4 1 T5 14 T10 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1136 1 T5 15 T10 3 T73 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 877 1 T5 11 T10 3 T73 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1154 1 T2 1 T5 30 T8 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 900 1 T2 1 T5 20 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1141 1 T4 2 T5 27 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 872 1 T4 1 T5 16 T8 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1129 1 T3 1 T5 22 T10 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 880 1 T3 1 T5 12 T10 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1163 1 T4 1 T5 21 T10 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 918 1 T5 16 T10 2 T38 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1091 1 T2 1 T4 2 T5 24
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 850 1 T2 1 T4 2 T5 18
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1139 1 T4 1 T5 23 T10 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 877 1 T5 17 T10 1 T38 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1128 1 T5 24 T10 3 T75 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 864 1 T5 16 T10 3 T75 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1064 1 T4 1 T5 23 T10 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 832 1 T4 1 T5 10 T10 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1082 1 T4 1 T5 21 T10 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 825 1 T4 1 T5 12 T10 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1147 1 T3 1 T4 1 T5 23
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 876 1 T3 1 T4 1 T5 14
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1177 1 T4 1 T5 23 T10 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 924 1 T4 1 T5 13 T10 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1108 1 T2 1 T4 1 T5 17
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 846 1 T2 1 T5 6 T10 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1111 1 T5 19 T10 1 T38 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 839 1 T5 14 T10 1 T38 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1095 1 T2 1 T4 1 T5 16
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 863 1 T2 1 T4 1 T5 12
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1053 1 T2 1 T5 23 T74 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 832 1 T2 1 T5 11 T74 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1071 1 T3 1 T5 16 T38 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 810 1 T5 7 T13 11 T14 15
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1078 1 T2 1 T5 20 T10 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 830 1 T2 1 T5 12 T10 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1140 1 T4 1 T5 20 T8 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 860 1 T5 14 T10 1 T34 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%