Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30181

1

T1

36

T3

9

T6

2

auto[1]

28569

1

T1

64

T3

6

T5

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30035

1

T1

46

T3

7

T5

2

auto[1]

28715

1

T1

54

T3

8

T7

38

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28939

1

T1

52

T3

6

T5

1

auto[1]

29811

1

T1

48

T3

9

T5

1

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32992

1

T1

50

T3

15

T5

2

auto[1]

25758

1

T1

50

T6

1

T7

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28808

1

T1

44

T3

6

T5

1

auto[1]

29942

1

T1

56

T3

9

T5

1

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29764

1

T1

56

T3

9

T5

1

auto[1]

28986

1

T1

44

T3

6

T5

1

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1001

1

T1

1

T3

1

T7

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

775

1

T1

1

T7

2

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

997

1

T1

1

T7

2

T14

17

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

791

1

T1

1

T7

2

T14

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1052

1

T1

1

T7

4

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

825

1

T1

1

T7

4

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1650

1

T6

1

T7

2

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1425

1

T6

1

T7

2

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1061

1

T7

4

T10

1

T14

23

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T7

4

T10

1

T14

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1066

1

T1

1

T3

1

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

843

1

T1

1

T7

1

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

993

1

T1

2

T7

2

T14

18

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

802

1

T1

2

T7

2

T14

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

997

1

T1

1

T7

3

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

776

1

T1

1

T7

3

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1006

1

T1

2

T7

1

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

789

1

T1

2

T7

1

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

976

1

T1

1

T3

1

T10

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

739

1

T1

1

T10

2

T14

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1014

1

T3

1

T7

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

779

1

T7

1

T10

2

T14

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

996

1

T1

2

T3

3

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

771

1

T1

2

T10

1

T14

18

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

987

1

T3

1

T9

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

776

1

T9

1

T10

1

T14

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1038

1

T1

2

T7

1

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T1

2

T7

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1027

1

T1

1

T7

2

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

806

1

T1

1

T7

2

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1017

1

T1

3

T3

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

787

1

T1

3

T7

1

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

995

1

T1

4

T10

2

T14

19

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

764

1

T1

4

T10

2

T14

17

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

993

1

T1

1

T3

1

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

770

1

T1

1

T9

2

T10

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1007

1

T1

3

T3

1

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

781

1

T1

3

T7

2

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

979

1

T1

4

T3

1

T5

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

756

1

T1

4

T7

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1023

1

T1

1

T5

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

800

1

T1

1

T9

1

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

971

1

T1

1

T7

2

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

773

1

T1

1

T7

2

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

987

1

T1

1

T3

2

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

753

1

T1

1

T7

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1028

1

T1

1

T7

5

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

788

1

T1

1

T7

5

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1001

1

T1

4

T7

1

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

773

1

T1

4

T7

1

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1028

1

T7

3

T10

1

T14

17

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

795

1

T7

3

T10

1

T14

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1011

1

T1

2

T7

2

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

793

1

T1

2

T7

2

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

988

1

T1

2

T7

3

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

744

1

T1

2

T7

3

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1063

1

T1

2

T10

1

T14

18

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

823

1

T1

2

T10

1

T14

17

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1004

1

T1

1

T3

1

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

768

1

T1

1

T9

1

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1042

1

T1

2

T7

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

817

1

T1

2

T7

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

994

1

T1

3

T7

3

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

757

1

T1

3

T7

3

T10

1