Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21385

1

T1

50

T2

10

T3

20

auto[1]

20409

1

T1

50

T2

14

T3

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21448

1

T1

54

T2

12

T3

18

auto[1]

20346

1

T1

46

T2

12

T3

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20539

1

T1

60

T2

8

T3

16

auto[1]

21255

1

T1

40

T2

16

T3

14

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23420

1

T1

50

T2

12

T3

15

auto[1]

18374

1

T1

50

T2

12

T3

15

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20498

1

T1

46

T2

12

T3

12

auto[1]

21296

1

T1

54

T2

12

T3

18

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21237

1

T1

42

T2

14

T3

10

auto[1]

20557

1

T1

58

T2

10

T3

20

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

703

1

T1

4

T3

2

T5

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

533

1

T1

4

T3

2

T5

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

713

1

T2

1

T5

3

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

561

1

T2

1

T5

3

T8

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

703

1

T1

1

T2

1

T5

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

571

1

T1

1

T2

1

T5

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1166

1

T1

1

T5

3

T8

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

997

1

T1

1

T5

3

T8

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

689

1

T1

2

T3

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

552

1

T1

2

T3

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

713

1

T1

1

T2

1

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

552

1

T1

1

T2

1

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

744

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

581

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

730

1

T1

1

T3

2

T22

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

580

1

T1

1

T3

2

T22

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

738

1

T1

2

T5

3

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

581

1

T1

2

T5

3

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

746

1

T1

3

T2

1

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

575

1

T1

3

T2

1

T5

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

676

1

T1

3

T8

1

T22

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

518

1

T1

3

T8

1

T22

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

710

1

T1

1

T3

1

T5

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

532

1

T1

1

T3

1

T5

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

755

1

T3

2

T5

1

T8

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

595

1

T3

2

T5

1

T8

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

749

1

T5

2

T8

1

T23

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

573

1

T5

2

T8

1

T23

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

736

1

T1

3

T5

1

T22

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

578

1

T1

3

T5

1

T22

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

696

1

T1

2

T3

1

T5

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

539

1

T1

2

T3

1

T5

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

786

1

T1

1

T2

1

T5

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

623

1

T1

1

T2

1

T5

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

701

1

T5

1

T8

5

T23

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

549

1

T5

1

T8

5

T23

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

750

1

T1

2

T2

1

T5

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

598

1

T1

2

T2

1

T5

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

686

1

T3

2

T5

1

T10

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

532

1

T3

2

T5

1

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

742

1

T1

4

T5

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

587

1

T1

4

T5

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

669

1

T1

4

T5

3

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

521

1

T1

4

T5

3

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

732

1

T1

3

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

565

1

T1

3

T5

1

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

732

1

T1

2

T3

1

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

587

1

T1

2

T3

1

T5

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

675

1

T8

3

T22

3

T23

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

517

1

T8

3

T22

3

T23

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

711

1

T5

1

T7

1

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

555

1

T5

1

T8

1

T22

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

693

1

T1

2

T7

1

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

545

1

T1

2

T8

2

T22

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

734

1

T1

1

T2

2

T5

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

559

1

T1

1

T2

2

T5

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

706

1

T1

1

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

555

1

T1

1

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

720

1

T1

1

T2

2

T5

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

553

1

T1

1

T2

2

T5

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

683

1

T1

1

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

529

1

T1

1

T3

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

733

1

T1

3

T2

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

581

1

T1

3

T2

1

T5

2