Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22919

1

T1

52

T5

2

T6

115

auto[1]

21983

1

T1

48

T6

136

T7

46

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23077

1

T1

54

T5

2

T6

121

auto[1]

21825

1

T1

46

T6

130

T7

46

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

46

T6

136

T7

48

auto[1]

22813

1

T1

54

T5

2

T6

115

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25056

1

T1

50

T5

1

T6

133

auto[1]

19846

1

T1

50

T5

1

T6

118

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21947

1

T1

48

T6

106

T7

52

auto[1]

22955

1

T1

52

T5

2

T6

145

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22848

1

T1

56

T5

2

T6

117

auto[1]

22054

1

T1

44

T6

134

T7

48

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

756

1

T1

1

T6

2

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

587

1

T1

1

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

781

1

T1

2

T6

3

T7

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

626

1

T1

2

T6

2

T7

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

741

1

T6

5

T7

1

T10

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

581

1

T6

5

T7

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1160

1

T5

1

T6

2

T7

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1016

1

T5

1

T6

1

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

776

1

T6

3

T7

2

T10

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

616

1

T6

2

T7

2

T10

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

801

1

T1

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

637

1

T1

1

T6

1

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

783

1

T1

2

T6

3

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

604

1

T1

2

T6

3

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

774

1

T1

4

T6

3

T7

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

630

1

T1

4

T6

3

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

724

1

T1

2

T6

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

582

1

T1

2

T6

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

777

1

T1

2

T6

1

T7

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

625

1

T1

2

T6

1

T7

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

788

1

T1

3

T6

6

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

601

1

T1

3

T6

4

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

788

1

T1

2

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

613

1

T1

2

T6

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

781

1

T1

1

T6

3

T7

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

616

1

T1

1

T6

3

T7

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

778

1

T1

2

T6

9

T10

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

571

1

T1

2

T6

8

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

783

1

T1

3

T6

12

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

627

1

T1

3

T6

10

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

785

1

T1

1

T6

6

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

611

1

T1

1

T6

5

T7

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

786

1

T1

1

T6

5

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

623

1

T1

1

T6

4

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

809

1

T1

3

T6

8

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

665

1

T1

3

T6

8

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

794

1

T1

4

T6

7

T7

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

620

1

T1

4

T6

6

T7

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

777

1

T1

4

T6

4

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

615

1

T1

4

T6

4

T7

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

769

1

T1

2

T6

5

T7

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

615

1

T1

2

T6

5

T7

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

715

1

T1

2

T6

3

T7

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

563

1

T1

2

T6

3

T7

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

771

1

T1

1

T6

6

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

630

1

T1

1

T6

6

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

816

1

T6

3

T7

1

T10

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

640

1

T6

3

T7

1

T10

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

782

1

T1

1

T6

2

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

601

1

T1

1

T6

2

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

749

1

T1

2

T6

4

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

596

1

T1

2

T6

2

T7

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

763

1

T6

5

T7

1

T10

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

603

1

T6

5

T7

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

739

1

T1

1

T6

6

T7

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

580

1

T1

1

T6

6

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

763

1

T1

1

T6

2

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

614

1

T1

1

T6

2

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

712

1

T1

1

T6

3

T10

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

551

1

T1

1

T6

3

T10

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

791

1

T1

1

T6

4

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

618

1

T1

1

T6

4

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

744

1

T6

3

T7

1

T10

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

569

1

T6

3

T7

1

T10

6