Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22893 1 T3 268 T4 75 T5 2
auto[1] 22160 1 T3 282 T4 67 T5 1


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23011 1 T3 253 T4 65 T5 2
auto[1] 22042 1 T3 297 T4 77 T5 1


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22159 1 T3 238 T4 72 T8 10
auto[1] 22894 1 T3 312 T4 70 T5 3


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25361 1 T3 337 T4 79 T5 3
auto[1] 19692 1 T3 213 T4 63 T8 12


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22039 1 T3 274 T4 81 T8 12
auto[1] 23014 1 T3 276 T4 61 T5 3


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22905 1 T3 299 T4 60 T5 1
auto[1] 22148 1 T3 251 T4 82 T5 2


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 802 1 T3 10 T4 3 T10 4
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 626 1 T3 6 T4 1 T10 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 794 1 T3 7 T10 1 T69 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 640 1 T3 2 T10 1 T69 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 756 1 T3 10 T4 1 T10 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 601 1 T3 8 T4 1 T10 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1242 1 T3 18 T4 5 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1072 1 T3 15 T4 5 T8 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 739 1 T3 4 T4 3 T8 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 587 1 T3 4 T4 3 T8 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 741 1 T3 8 T4 3 T10 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 574 1 T3 5 T4 2 T10 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 818 1 T3 7 T4 1 T10 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 623 1 T3 4 T10 1 T35 4
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 794 1 T3 4 T4 3 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 612 1 T3 1 T4 1 T8 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 771 1 T3 11 T4 5 T10 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 589 1 T3 6 T4 5 T10 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 797 1 T3 19 T4 2 T10 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 597 1 T3 8 T4 2 T10 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 761 1 T3 5 T4 3 T10 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 603 1 T3 3 T4 1 T10 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 757 1 T3 14 T38 1 T35 4
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 578 1 T3 12 T35 4 T20 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 785 1 T3 10 T4 3 T10 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 601 1 T3 7 T4 3 T10 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 770 1 T3 11 T4 3 T10 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 594 1 T3 7 T4 3 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 735 1 T3 11 T4 3 T8 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 574 1 T3 10 T4 2 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 782 1 T3 12 T4 5 T10 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 578 1 T3 9 T4 3 T10 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 785 1 T3 6 T4 1 T10 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 601 1 T3 3 T4 1 T10 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 749 1 T3 15 T10 1 T33 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 567 1 T3 9 T10 1 T33 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 789 1 T3 8 T4 3 T10 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 613 1 T3 5 T4 3 T10 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 758 1 T3 17 T4 2 T8 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 585 1 T3 11 T4 2 T8 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 797 1 T3 8 T4 6 T20 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 622 1 T3 4 T4 4 T20 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 747 1 T3 14 T4 1 T35 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 571 1 T3 10 T4 1 T35 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 759 1 T3 7 T4 3 T38 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 605 1 T3 7 T4 2 T33 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 813 1 T3 10 T4 2 T10 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 629 1 T3 6 T4 2 T10 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 768 1 T3 13 T4 2 T10 4
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 596 1 T3 11 T4 2 T10 4
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 755 1 T3 11 T4 4 T8 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 560 1 T3 6 T4 4 T8 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 798 1 T3 8 T8 1 T10 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 610 1 T3 3 T8 1 T10 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 785 1 T3 13 T4 1 T8 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 600 1 T3 6 T4 1 T8 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 832 1 T3 15 T4 4 T8 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 659 1 T3 9 T4 3 T8 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 799 1 T3 10 T4 4 T8 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 624 1 T3 5 T4 3 T8 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 774 1 T3 11 T10 3 T38 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 580 1 T3 4 T10 3 T33 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 809 1 T3 10 T4 3 T5 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 621 1 T3 7 T4 3 T10 1

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