Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21337

1

T1

10

T2

2

T3

44

auto[1]

20520

1

T1

8

T2

4

T3

56

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21351

1

T1

8

T2

3

T3

48

auto[1]

20506

1

T1

10

T2

3

T3

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20713

1

T1

14

T2

5

T3

60

auto[1]

21144

1

T1

4

T2

1

T3

40

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23351

1

T1

9

T2

4

T3

50

auto[1]

18506

1

T1

9

T2

2

T3

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20620

1

T1

8

T2

2

T3

48

auto[1]

21237

1

T1

10

T2

4

T3

52

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21143

1

T1

8

T2

6

T3

46

auto[1]

20714

1

T1

10

T3

54

T6

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

738

1

T3

2

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

590

1

T3

2

T6

1

T23

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

702

1

T3

1

T6

1

T23

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

567

1

T3

1

T6

1

T23

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

738

1

T3

2

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

586

1

T3

2

T6

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1094

1

T37

1

T14

13

T21

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

941

1

T37

1

T14

12

T21

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

748

1

T1

1

T3

1

T7

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

590

1

T1

1

T3

1

T23

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

728

1

T3

2

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

578

1

T3

2

T23

1

T14

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

725

1

T3

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

568

1

T3

1

T10

1

T23

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

713

1

T3

1

T10

1

T23

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

573

1

T3

1

T10

1

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

700

1

T3

1

T7

2

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

556

1

T3

1

T23

1

T14

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

698

1

T8

1

T23

1

T14

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

545

1

T23

1

T14

3

T21

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

706

1

T1

1

T2

1

T3

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

553

1

T1

1

T2

1

T3

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

716

1

T3

2

T6

2

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

540

1

T3

2

T6

2

T23

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

745

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

588

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

740

1

T1

1

T8

1

T23

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

578

1

T1

1

T23

3

T14

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

679

1

T1

1

T3

3

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

535

1

T1

1

T3

3

T23

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

714

1

T3

2

T8

1

T14

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

565

1

T3

2

T14

3

T21

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

723

1

T2

1

T3

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

568

1

T2

1

T3

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

676

1

T3

3

T6

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

545

1

T3

3

T6

2

T23

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

741

1

T1

2

T3

2

T23

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

581

1

T1

2

T3

2

T23

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

671

1

T1

1

T2

1

T3

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

530

1

T1

1

T3

2

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

690

1

T3

2

T8

1

T14

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

555

1

T3

2

T14

7

T21

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

721

1

T3

1

T7

1

T23

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

575

1

T3

1

T23

1

T14

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

711

1

T3

3

T23

1

T14

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

567

1

T3

3

T23

1

T14

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

724

1

T10

1

T23

2

T14

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

594

1

T10

1

T23

2

T14

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

718

1

T3

1

T6

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

568

1

T3

1

T6

1

T23

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

715

1

T3

1

T23

1

T14

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

548

1

T3

1

T23

1

T14

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

762

1

T2

1

T3

2

T7

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

585

1

T3

2

T23

2

T14

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

707

1

T3

1

T6

1

T23

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

535

1

T3

1

T6

1

T23

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

734

1

T1

1

T3

4

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

594

1

T1

1

T3

4

T23

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

729

1

T3

2

T23

2

T14

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

570

1

T3

2

T23

2

T14

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

709

1

T3

1

T6

2

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

562

1

T3

1

T6

2

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

736

1

T3

2

T8

1

T23

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

576

1

T3

2

T23

4

T14

5