Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22516

1

T3

2

T5

52

T10

3

auto[1]

21476

1

T3

3

T5

48

T10

3

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22637

1

T3

2

T5

46

T10

2

auto[1]

21355

1

T3

3

T5

54

T10

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21626

1

T3

2

T5

44

T10

3

auto[1]

22366

1

T3

3

T5

56

T10

3

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24580

1

T3

5

T5

50

T10

4

auto[1]

19412

1

T5

50

T10

2

T12

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21520

1

T3

3

T5

44

T10

5

auto[1]

22472

1

T3

2

T5

56

T10

1

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22156

1

T3

1

T5

54

T10

4

auto[1]

21836

1

T3

4

T5

46

T10

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

740

1

T5

1

T25

4

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

577

1

T5

1

T25

4

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

816

1

T3

1

T25

2

T40

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

652

1

T25

2

T40

2

T58

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

789

1

T5

4

T25

5

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

636

1

T5

4

T25

5

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1175

1

T12

1

T13

1

T25

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1020

1

T12

1

T25

4

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

745

1

T25

3

T40

2

T14

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

607

1

T25

3

T40

2

T26

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

754

1

T5

4

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

610

1

T5

4

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

780

1

T24

1

T13

2

T25

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

602

1

T24

1

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

746

1

T13

2

T26

13

T46

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

577

1

T26

9

T21

4

T134

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

703

1

T13

1

T25

1

T26

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

560

1

T25

1

T26

3

T85

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

716

1

T5

3

T10

1

T25

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

565

1

T5

3

T10

1

T25

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

764

1

T5

4

T25

2

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

584

1

T5

4

T25

2

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

772

1

T5

3

T48

1

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

607

1

T5

3

T48

1

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

766

1

T5

1

T13

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

609

1

T5

1

T25

2

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

734

1

T3

1

T5

2

T48

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

575

1

T5

2

T48

1

T25

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

789

1

T5

1

T40

3

T26

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

633

1

T5

1

T40

3

T26

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

731

1

T5

3

T10

1

T25

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

582

1

T5

3

T25

3

T40

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

725

1

T5

2

T10

1

T40

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

581

1

T5

2

T10

1

T40

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

736

1

T5

2

T24

1

T25

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

566

1

T5

2

T24

1

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

731

1

T5

1

T25

1

T40

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

541

1

T5

1

T25

1

T40

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

762

1

T5

3

T25

1

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

608

1

T5

3

T25

1

T40

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

791

1

T48

1

T25

1

T40

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

623

1

T25

1

T40

1

T58

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

745

1

T3

1

T5

2

T13

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

588

1

T5

2

T25

2

T40

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

810

1

T5

3

T13

1

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

634

1

T5

3

T40

1

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

769

1

T5

1

T25

1

T26

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

601

1

T5

1

T25

1

T26

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

725

1

T5

1

T13

1

T25

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

564

1

T5

1

T25

1

T40

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

776

1

T5

1

T25

5

T40

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

593

1

T5

1

T25

5

T40

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

757

1

T25

1

T40

1

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

594

1

T25

1

T40

1

T26

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

695

1

T5

2

T13

1

T25

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

526

1

T5

2

T25

2

T58

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

764

1

T5

2

T10

1

T25

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

608

1

T5

2

T25

2

T40

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

781

1

T5

1

T25

4

T14

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

625

1

T5

1

T25

4

T26

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

719

1

T3

2

T5

2

T40

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

575

1

T5

2

T40

1

T26

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

774

1

T5

1

T25

4

T40

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

589

1

T5

1

T25

4

T40

2