Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21251

1

T1

11

T3

2

T5

4

auto[1]

20487

1

T1

32

T5

2

T6

3

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21357

1

T1

25

T3

2

T5

6

auto[1]

20381

1

T1

18

T6

3

T7

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20367

1

T1

20

T5

4

T6

1

auto[1]

21371

1

T1

23

T3

2

T5

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23247

1

T1

24

T3

1

T5

4

auto[1]

18491

1

T1

19

T3

1

T5

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20355

1

T1

25

T5

1

T6

2

auto[1]

21383

1

T1

18

T3

2

T5

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21668

1

T1

16

T3

2

T5

1

auto[1]

20070

1

T1

27

T5

5

T6

1

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

747

1

T7

2

T8

4

T9

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

600

1

T7

2

T8

4

T9

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

728

1

T7

1

T9

1

T36

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

584

1

T7

1

T9

1

T36

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

746

1

T1

1

T7

1

T8

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

595

1

T1

1

T7

1

T8

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1133

1

T3

1

T7

1

T8

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

985

1

T3

1

T7

1

T8

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

685

1

T7

2

T9

1

T39

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

538

1

T7

2

T9

1

T39

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

729

1

T1

1

T7

1

T8

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

597

1

T7

1

T8

2

T9

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

700

1

T5

1

T7

1

T8

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

551

1

T5

1

T7

1

T8

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

732

1

T5

1

T7

4

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

577

1

T5

1

T7

4

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

675

1

T1

1

T6

1

T7

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

537

1

T1

1

T7

4

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

722

1

T7

1

T8

2

T9

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

569

1

T7

1

T8

2

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

748

1

T1

1

T8

1

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

602

1

T8

1

T9

1

T14

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

723

1

T1

1

T7

3

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

567

1

T7

3

T9

3

T36

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

682

1

T1

1

T8

3

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

539

1

T1

1

T8

2

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

683

1

T7

2

T8

3

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

512

1

T7

2

T8

3

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

651

1

T1

1

T8

2

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

500

1

T1

1

T8

2

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

751

1

T7

5

T8

5

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

563

1

T7

5

T8

5

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

673

1

T1

1

T5

1

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

529

1

T1

1

T7

1

T8

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

737

1

T7

2

T8

3

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

597

1

T7

2

T8

3

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

744

1

T7

3

T36

1

T14

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

597

1

T7

3

T36

1

T14

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

717

1

T1

1

T6

1

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

578

1

T1

1

T7

2

T9

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

709

1

T1

2

T8

1

T36

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

555

1

T1

2

T8

1

T36

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

682

1

T1

5

T7

2

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

544

1

T1

5

T7

2

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

706

1

T5

1

T7

1

T8

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

573

1

T7

1

T8

3

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

664

1

T1

2

T8

3

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

525

1

T1

2

T8

3

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

720

1

T7

1

T9

1

T36

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

582

1

T7

1

T9

1

T36

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

738

1

T1

1

T6

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

570

1

T1

1

T7

1

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

728

1

T1

2

T8

3

T36

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

572

1

T1

1

T8

3

T36

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

738

1

T1

1

T8

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

587

1

T8

1

T9

1

T36

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

705

1

T1

1

T7

1

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

568

1

T1

1

T7

1

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

738

1

T7

6

T8

3

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

581

1

T7

6

T8

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

720

1

T7

1

T8

3

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

590

1

T7

1

T8

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

693

1

T1

1

T6

1

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

527

1

T1

1

T7

1

T8

2