Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T3

5

T4

2

T6

3

auto[1]

21861

1

T3

1

T6

3

T7

60

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T3

2

T4

2

T6

4

auto[1]

21987

1

T3

4

T6

2

T7

56

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21889

1

T3

4

T6

4

T7

52

auto[1]

23040

1

T3

2

T4

2

T6

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25007

1

T3

6

T4

1

T6

4

auto[1]

19922

1

T4

1

T6

2

T7

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21998

1

T3

2

T6

1

T7

60

auto[1]

22931

1

T3

4

T4

2

T6

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23041

1

T3

4

T4

2

T6

2

auto[1]

21888

1

T3

2

T6

4

T7

42

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

814

1

T3

1

T7

2

T8

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

646

1

T7

2

T8

2

T10

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

786

1

T10

1

T11

7

T12

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

632

1

T10

1

T11

4

T12

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

772

1

T10

1

T25

3

T11

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

604

1

T10

1

T25

3

T11

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1259

1

T4

1

T7

3

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1110

1

T4

1

T7

3

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

762

1

T7

1

T10

1

T11

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

595

1

T7

1

T10

1

T11

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

763

1

T10

1

T25

4

T11

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

590

1

T10

1

T25

4

T11

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

748

1

T3

1

T6

1

T7

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

608

1

T6

1

T7

2

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

775

1

T6

1

T10

2

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

623

1

T10

2

T24

1

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

801

1

T3

1

T7

2

T11

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

634

1

T7

2

T11

8

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

751

1

T7

4

T10

3

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

588

1

T7

4

T10

3

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

776

1

T3

1

T7

1

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

615

1

T7

1

T8

1

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

781

1

T7

1

T10

2

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

621

1

T7

1

T10

2

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

753

1

T7

2

T10

1

T11

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

598

1

T7

2

T10

1

T11

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

797

1

T7

2

T8

1

T10

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

612

1

T7

2

T8

1

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

733

1

T10

1

T11

10

T12

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

583

1

T10

1

T11

7

T12

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

754

1

T3

1

T10

1

T25

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

584

1

T10

1

T25

1

T11

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

698

1

T7

1

T8

1

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

566

1

T7

1

T8

1

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

752

1

T7

2

T8

2

T25

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

608

1

T7

2

T8

2

T25

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

728

1

T7

2

T10

2

T24

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

603

1

T7

2

T10

2

T24

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

802

1

T7

3

T8

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

627

1

T7

3

T8

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

748

1

T7

1

T10

4

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

599

1

T7

1

T10

4

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

766

1

T6

1

T7

3

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

617

1

T7

3

T8

1

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

756

1

T7

1

T10

3

T11

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

602

1

T7

1

T10

3

T11

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

777

1

T7

1

T8

2

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

606

1

T7

1

T8

2

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

779

1

T7

2

T8

1

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

641

1

T7

2

T8

1

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

761

1

T7

4

T10

1

T25

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

583

1

T7

4

T10

1

T25

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

763

1

T6

1

T7

2

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

587

1

T6

1

T7

2

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

766

1

T3

1

T8

1

T10

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

587

1

T8

1

T10

3

T11

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

754

1

T7

4

T8

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

610

1

T7

4

T8

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

774

1

T10

2

T25

3

T11

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

620

1

T10

2

T25

3

T11

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

787

1

T7

3

T10

2

T11

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

626

1

T7

3

T10

2

T11

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

771

1

T7

1

T10

2

T25

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

597

1

T7

1

T10

2

T25

2